From ec6700839573e5a3ab789c6b0fb199d7b02811b4 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 18 Dec 2025 10:03:09 +0100 Subject: [PATCH] chapter3-secureworld: correct RISC-V heading Chapter 3.3 is about RISC-V in general and not about a "RISC-V Multiprocessor Startup Protocol". While at it add a missing 'the'. Signed-off-by: Heinrich Schuchardt --- source/chapter3-secureworld.rst | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/source/chapter3-secureworld.rst b/source/chapter3-secureworld.rst index 4c5bbea..e578241 100644 --- a/source/chapter3-secureworld.rst +++ b/source/chapter3-secureworld.rst @@ -149,11 +149,12 @@ Generator Firmware Interface version 1.0, as defined in [TRNG]_. [#TRNGNote]_ it can be used at runtime. The TRNG interface requires SMCCC version 1.1 or later. -RISC-V Multiprocessor Startup Protocol -====================================== +RISC-V +====== -The resident firmware in M mode or hypervisor running in HS mode must implement -and conform to at least SBI [RVSBISPC]_ v2.0 with at least these extensions: +The resident firmware in M mode or the hypervisor running in HS mode must +implement and conform to at least SBI [RVSBISPC]_ v2.0 with at least these +extensions: * Base Extension * HART State Management Extension (HSM)