From 287f207b833d3e41bb7b0c4010ac5bb93a4d82a8 Mon Sep 17 00:00:00 2001 From: TemshinaroJamir Date: Mon, 28 Jul 2025 23:46:00 +0530 Subject: [PATCH 1/2] Add IC folders implemented during internship MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a list of all the ICs I have implemented during my internship at FOSSEE IIT BOMBAY: 1. **HD74HC30** – 8-input NAND Gate 2. **SN54S64** – 4-2-3-2 Input AND-OR-Invert Gate 3. **SN74ACT86** – Quadruple 2-Input XOR Gate 4. **CD54HC7266** – Quadruple 2-Input XNOR Gate 5. **SLOA024B_LowPass** – Sallen-Key Low Pass Filter 6. **SLOA024B_HighPass** – Sallen-Key High Pass Filter 7. **MM54C42** – BCD-to-Decimal Decoder 8. **CD4555** – Dual Binary to 1-of-4 Demultiplexer 9. **CA3045** – General Purpose NPN Transistor Array --- library/SubcircuitLibrary/CA3045/BC107.lib | 1 + .../SubcircuitLibrary/CA3045/CA3045-cache.lib | 67 ++ library/SubcircuitLibrary/CA3045/CA3045.cir | 16 + .../SubcircuitLibrary/CA3045/CA3045.cir.out | 18 + library/SubcircuitLibrary/CA3045/CA3045.pro | 73 ++ library/SubcircuitLibrary/CA3045/CA3045.sch | 319 +++++++ library/SubcircuitLibrary/CA3045/CA3045.sub | 12 + .../CA3045/CA3045_Previous_Values.xml | 1 + library/SubcircuitLibrary/CA3045/NPN.lib | 4 + library/SubcircuitLibrary/CA3045/analysis | 1 + .../SubcircuitLibrary/CD4555/3_and-cache.lib | 61 ++ library/SubcircuitLibrary/CD4555/3_and.cir | 13 + .../SubcircuitLibrary/CD4555/3_and.cir.out | 20 + library/SubcircuitLibrary/CD4555/3_and.pro | 43 + library/SubcircuitLibrary/CD4555/3_and.sch | 130 +++ library/SubcircuitLibrary/CD4555/3_and.sub | 14 + .../CD4555/3_and_Previous_Values.xml | 1 + .../SubcircuitLibrary/CD4555/CD4555-cache.lib | 76 ++ library/SubcircuitLibrary/CD4555/CD4555.cir | 45 + .../SubcircuitLibrary/CD4555/CD4555.cir.out | 125 +++ library/SubcircuitLibrary/CD4555/CD4555.pro | 73 ++ library/SubcircuitLibrary/CD4555/CD4555.sch | 779 ++++++++++++++++++ library/SubcircuitLibrary/CD4555/CD4555.sub | 119 +++ .../CD4555/CD4555_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD4555/analysis | 1 + .../CD54HC7266/CD54HC7266-cache.lib | 94 +++ .../CD54HC7266/CD54HC7266.cir | 35 + .../CD54HC7266/CD54HC7266.cir.out | 108 +++ .../CD54HC7266/CD54HC7266.pro | 73 ++ .../CD54HC7266/CD54HC7266.sch | 644 +++++++++++++++ .../CD54HC7266/CD54HC7266.sub | 102 +++ .../CD54HC7266/CD54HC7266_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD54HC7266/analysis | 1 + .../HD74HC30/3_and-cache.lib | 61 ++ library/SubcircuitLibrary/HD74HC30/3_and.cir | 13 + .../SubcircuitLibrary/HD74HC30/3_and.cir.out | 20 + library/SubcircuitLibrary/HD74HC30/3_and.pro | 43 + library/SubcircuitLibrary/HD74HC30/3_and.sch | 130 +++ library/SubcircuitLibrary/HD74HC30/3_and.sub | 14 + .../HD74HC30/3_and_Previous_Values.xml | 1 + .../HD74HC30/4_and-cache.lib | 79 ++ .../HD74HC30/4_and-rescue.lib | 22 + library/SubcircuitLibrary/HD74HC30/4_and.cir | 13 + .../SubcircuitLibrary/HD74HC30/4_and.cir.out | 18 + library/SubcircuitLibrary/HD74HC30/4_and.pro | 57 ++ library/SubcircuitLibrary/HD74HC30/4_and.sch | 151 ++++ library/SubcircuitLibrary/HD74HC30/4_and.sub | 12 + .../HD74HC30/4_and_Previous_Values.xml | 1 + .../HD74HC30/HD74HC30-cache.lib | 94 +++ .../SubcircuitLibrary/HD74HC30/HD74HC30.cir | 15 + .../HD74HC30/HD74HC30.cir.out | 23 + .../SubcircuitLibrary/HD74HC30/HD74HC30.pro | 73 ++ .../SubcircuitLibrary/HD74HC30/HD74HC30.sch | 288 +++++++ .../SubcircuitLibrary/HD74HC30/HD74HC30.sub | 17 + .../HD74HC30/HD74HC30_Previous_Values.xml | 1 + .../SubcircuitLibrary/HD74HC30/NMOS-180nm.lib | 13 + .../SubcircuitLibrary/HD74HC30/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/HD74HC30/analysis | 1 + .../MM54C42/MM54C42-cache.lib | 94 +++ library/SubcircuitLibrary/MM54C42/MM54C42.cir | 39 + .../SubcircuitLibrary/MM54C42/MM54C42.cir.out | 124 +++ library/SubcircuitLibrary/MM54C42/MM54C42.pro | 73 ++ library/SubcircuitLibrary/MM54C42/MM54C42.sch | 750 +++++++++++++++++ library/SubcircuitLibrary/MM54C42/MM54C42.sub | 118 +++ .../MM54C42/MM54C42_Previous_Values.xml | 1 + library/SubcircuitLibrary/MM54C42/analysis | 1 + .../SLOA024B_HighPass/NPN.lib | 4 + .../SLOA024B_HighPass/PNP.lib | 4 + .../SLOA024B_HighPass-cache.lib | 115 +++ .../SLOA024B_HighPass/SLOA024B_HighPass.cir | 16 + .../SLOA024B_HighPass.cir.out | 18 + .../SLOA024B_HighPass/SLOA024B_HighPass.pro | 73 ++ .../SLOA024B_HighPass/SLOA024B_HighPass.sch | 201 +++++ .../SLOA024B_HighPass/SLOA024B_HighPass.sub | 12 + .../SLOA024B_HighPass_Previous_Values.xml | 1 + .../SLOA024B_HighPass/analysis | 1 + .../SLOA024B_HighPass/lm_741-cache.lib | 119 +++ .../SLOA024B_HighPass/lm_741.cir | 43 + .../SLOA024B_HighPass/lm_741.cir.out | 46 ++ .../SLOA024B_HighPass/lm_741.pro | 44 + .../SLOA024B_HighPass/lm_741.sch | 697 ++++++++++++++++ .../SLOA024B_HighPass/lm_741.sub | 40 + .../lm_741_Previous_Values.xml | 1 + .../SLOA024B_HighPass/npn_1.lib | 29 + .../SLOA024B_HighPass/pnp_1.lib | 29 + .../SLOA024B_LowPass/NPN.lib | 4 + .../SLOA024B_LowPass/PNP.lib | 4 + .../SLOA024B_LowPass-cache.lib | 115 +++ .../SLOA024B_LowPass/SLOA024B_LowPass.cir | 16 + .../SLOA024B_LowPass/SLOA024B_LowPass.cir.out | 18 + .../SLOA024B_LowPass/SLOA024B_LowPass.out | 18 + .../SLOA024B_LowPass/SLOA024B_LowPass.pro | 73 ++ .../SLOA024B_LowPass/SLOA024B_LowPass.sch | 201 +++++ .../SLOA024B_LowPass/SLOA024B_LowPass.sub | 12 + .../SLOA024B_LowPass_Previous_Values.xml | 1 + .../SLOA024B_LowPass/analysis | 1 + .../SLOA024B_LowPass/lm_741-cache.lib | 119 +++ .../SLOA024B_LowPass/lm_741.cir | 43 + .../SLOA024B_LowPass/lm_741.cir.out | 46 ++ .../SLOA024B_LowPass/lm_741.pro | 44 + .../SLOA024B_LowPass/lm_741.sch | 697 ++++++++++++++++ .../SLOA024B_LowPass/lm_741.sub | 40 + .../lm_741_Previous_Values.xml | 1 + .../SLOA024B_LowPass/npn_1.lib | 29 + .../SLOA024B_LowPass/pnp_1.lib | 29 + .../SubcircuitLibrary/SN54S64/3_and-cache.lib | 61 ++ library/SubcircuitLibrary/SN54S64/3_and.cir | 13 + .../SubcircuitLibrary/SN54S64/3_and.cir.out | 20 + library/SubcircuitLibrary/SN54S64/3_and.pro | 43 + library/SubcircuitLibrary/SN54S64/3_and.sch | 130 +++ library/SubcircuitLibrary/SN54S64/3_and.sub | 14 + .../SN54S64/3_and_Previous_Values.xml | 1 + .../SubcircuitLibrary/SN54S64/4_OR-cache.lib | 63 ++ library/SubcircuitLibrary/SN54S64/4_OR.cir | 14 + .../SubcircuitLibrary/SN54S64/4_OR.cir.out | 24 + library/SubcircuitLibrary/SN54S64/4_OR.pro | 44 + library/SubcircuitLibrary/SN54S64/4_OR.sch | 150 ++++ library/SubcircuitLibrary/SN54S64/4_OR.sub | 18 + .../SN54S64/4_OR_Previous_Values.xml | 1 + .../SubcircuitLibrary/SN54S64/4_and-cache.lib | 79 ++ .../SN54S64/4_and-rescue.lib | 22 + library/SubcircuitLibrary/SN54S64/4_and.cir | 13 + .../SubcircuitLibrary/SN54S64/4_and.cir.out | 18 + library/SubcircuitLibrary/SN54S64/4_and.pro | 57 ++ library/SubcircuitLibrary/SN54S64/4_and.sch | 151 ++++ library/SubcircuitLibrary/SN54S64/4_and.sub | 12 + .../SN54S64/4_and_Previous_Values.xml | 1 + .../SN54S64/SN54S64-cache.lib | 133 +++ library/SubcircuitLibrary/SN54S64/SN54S64.cir | 17 + .../SubcircuitLibrary/SN54S64/SN54S64.cir.out | 30 + library/SubcircuitLibrary/SN54S64/SN54S64.pro | 73 ++ library/SubcircuitLibrary/SN54S64/SN54S64.sch | 328 ++++++++ library/SubcircuitLibrary/SN54S64/SN54S64.sub | 24 + .../SN54S64/SN54S64_Previous_Values.xml | 1 + library/SubcircuitLibrary/SN54S64/analysis | 1 + .../SN74ACT86/SN74ACT86-cache.lib | 94 +++ .../SubcircuitLibrary/SN74ACT86/SN74ACT86.cir | 31 + .../SN74ACT86/SN74ACT86.cir.out | 92 +++ .../SubcircuitLibrary/SN74ACT86/SN74ACT86.pro | 73 ++ .../SubcircuitLibrary/SN74ACT86/SN74ACT86.sch | 592 +++++++++++++ .../SubcircuitLibrary/SN74ACT86/SN74ACT86.sub | 86 ++ .../SN74ACT86/SN74ACT86_Previous_Values.xml | 1 + library/SubcircuitLibrary/SN74ACT86/analysis | 1 + 143 files changed, 10972 insertions(+) create mode 100644 library/SubcircuitLibrary/CA3045/BC107.lib create mode 100644 library/SubcircuitLibrary/CA3045/CA3045-cache.lib create mode 100644 library/SubcircuitLibrary/CA3045/CA3045.cir create mode 100644 library/SubcircuitLibrary/CA3045/CA3045.cir.out create mode 100644 library/SubcircuitLibrary/CA3045/CA3045.pro create mode 100644 library/SubcircuitLibrary/CA3045/CA3045.sch create mode 100644 library/SubcircuitLibrary/CA3045/CA3045.sub create mode 100644 library/SubcircuitLibrary/CA3045/CA3045_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CA3045/NPN.lib create mode 100644 library/SubcircuitLibrary/CA3045/analysis create mode 100644 library/SubcircuitLibrary/CD4555/3_and-cache.lib create mode 100644 library/SubcircuitLibrary/CD4555/3_and.cir create mode 100644 library/SubcircuitLibrary/CD4555/3_and.cir.out create mode 100644 library/SubcircuitLibrary/CD4555/3_and.pro create mode 100644 library/SubcircuitLibrary/CD4555/3_and.sch create mode 100644 library/SubcircuitLibrary/CD4555/3_and.sub create mode 100644 library/SubcircuitLibrary/CD4555/3_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD4555/CD4555-cache.lib create mode 100644 library/SubcircuitLibrary/CD4555/CD4555.cir create mode 100644 library/SubcircuitLibrary/CD4555/CD4555.cir.out create mode 100644 library/SubcircuitLibrary/CD4555/CD4555.pro create mode 100644 library/SubcircuitLibrary/CD4555/CD4555.sch create mode 100644 library/SubcircuitLibrary/CD4555/CD4555.sub create mode 100644 library/SubcircuitLibrary/CD4555/CD4555_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD4555/analysis create mode 100644 library/SubcircuitLibrary/CD54HC7266/CD54HC7266-cache.lib create mode 100644 library/SubcircuitLibrary/CD54HC7266/CD54HC7266.cir create mode 100644 library/SubcircuitLibrary/CD54HC7266/CD54HC7266.cir.out create mode 100644 library/SubcircuitLibrary/CD54HC7266/CD54HC7266.pro create mode 100644 library/SubcircuitLibrary/CD54HC7266/CD54HC7266.sch create mode 100644 library/SubcircuitLibrary/CD54HC7266/CD54HC7266.sub create mode 100644 library/SubcircuitLibrary/CD54HC7266/CD54HC7266_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD54HC7266/analysis create mode 100644 library/SubcircuitLibrary/HD74HC30/3_and-cache.lib create mode 100644 library/SubcircuitLibrary/HD74HC30/3_and.cir create mode 100644 library/SubcircuitLibrary/HD74HC30/3_and.cir.out create mode 100644 library/SubcircuitLibrary/HD74HC30/3_and.pro create mode 100644 library/SubcircuitLibrary/HD74HC30/3_and.sch create mode 100644 library/SubcircuitLibrary/HD74HC30/3_and.sub create mode 100644 library/SubcircuitLibrary/HD74HC30/3_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/HD74HC30/4_and-cache.lib create mode 100644 library/SubcircuitLibrary/HD74HC30/4_and-rescue.lib create mode 100644 library/SubcircuitLibrary/HD74HC30/4_and.cir create mode 100644 library/SubcircuitLibrary/HD74HC30/4_and.cir.out create mode 100644 library/SubcircuitLibrary/HD74HC30/4_and.pro create mode 100644 library/SubcircuitLibrary/HD74HC30/4_and.sch create mode 100644 library/SubcircuitLibrary/HD74HC30/4_and.sub create mode 100644 library/SubcircuitLibrary/HD74HC30/4_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/HD74HC30/HD74HC30-cache.lib create mode 100644 library/SubcircuitLibrary/HD74HC30/HD74HC30.cir create mode 100644 library/SubcircuitLibrary/HD74HC30/HD74HC30.cir.out create mode 100644 library/SubcircuitLibrary/HD74HC30/HD74HC30.pro create mode 100644 library/SubcircuitLibrary/HD74HC30/HD74HC30.sch create mode 100644 library/SubcircuitLibrary/HD74HC30/HD74HC30.sub create mode 100644 library/SubcircuitLibrary/HD74HC30/HD74HC30_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/HD74HC30/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/HD74HC30/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/HD74HC30/analysis create mode 100644 library/SubcircuitLibrary/MM54C42/MM54C42-cache.lib create mode 100644 library/SubcircuitLibrary/MM54C42/MM54C42.cir create mode 100644 library/SubcircuitLibrary/MM54C42/MM54C42.cir.out create mode 100644 library/SubcircuitLibrary/MM54C42/MM54C42.pro create mode 100644 library/SubcircuitLibrary/MM54C42/MM54C42.sch create mode 100644 library/SubcircuitLibrary/MM54C42/MM54C42.sub create mode 100644 library/SubcircuitLibrary/MM54C42/MM54C42_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/MM54C42/analysis create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/NPN.lib create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/PNP.lib create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass-cache.lib create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.cir create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.cir.out create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.pro create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.sch create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.sub create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/analysis create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/lm_741-cache.lib create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.cir create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.cir.out create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.pro create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.sch create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.sub create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/lm_741_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/npn_1.lib create mode 100644 library/SubcircuitLibrary/SLOA024B_HighPass/pnp_1.lib create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/NPN.lib create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/PNP.lib create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass-cache.lib create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.cir create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.cir.out create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.out create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.pro create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.sch create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.sub create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/analysis create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/lm_741-cache.lib create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.cir create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.cir.out create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.pro create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.sch create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.sub create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/lm_741_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/npn_1.lib create mode 100644 library/SubcircuitLibrary/SLOA024B_LowPass/pnp_1.lib create mode 100644 library/SubcircuitLibrary/SN54S64/3_and-cache.lib create mode 100644 library/SubcircuitLibrary/SN54S64/3_and.cir create mode 100644 library/SubcircuitLibrary/SN54S64/3_and.cir.out create mode 100644 library/SubcircuitLibrary/SN54S64/3_and.pro create mode 100644 library/SubcircuitLibrary/SN54S64/3_and.sch create mode 100644 library/SubcircuitLibrary/SN54S64/3_and.sub create mode 100644 library/SubcircuitLibrary/SN54S64/3_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SN54S64/4_OR-cache.lib create mode 100644 library/SubcircuitLibrary/SN54S64/4_OR.cir create mode 100644 library/SubcircuitLibrary/SN54S64/4_OR.cir.out create mode 100644 library/SubcircuitLibrary/SN54S64/4_OR.pro create mode 100644 library/SubcircuitLibrary/SN54S64/4_OR.sch create mode 100644 library/SubcircuitLibrary/SN54S64/4_OR.sub create mode 100644 library/SubcircuitLibrary/SN54S64/4_OR_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SN54S64/4_and-cache.lib create mode 100644 library/SubcircuitLibrary/SN54S64/4_and-rescue.lib create mode 100644 library/SubcircuitLibrary/SN54S64/4_and.cir create mode 100644 library/SubcircuitLibrary/SN54S64/4_and.cir.out create mode 100644 library/SubcircuitLibrary/SN54S64/4_and.pro create mode 100644 library/SubcircuitLibrary/SN54S64/4_and.sch create mode 100644 library/SubcircuitLibrary/SN54S64/4_and.sub create mode 100644 library/SubcircuitLibrary/SN54S64/4_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SN54S64/SN54S64-cache.lib create mode 100644 library/SubcircuitLibrary/SN54S64/SN54S64.cir create mode 100644 library/SubcircuitLibrary/SN54S64/SN54S64.cir.out create mode 100644 library/SubcircuitLibrary/SN54S64/SN54S64.pro create mode 100644 library/SubcircuitLibrary/SN54S64/SN54S64.sch create mode 100644 library/SubcircuitLibrary/SN54S64/SN54S64.sub create mode 100644 library/SubcircuitLibrary/SN54S64/SN54S64_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SN54S64/analysis create mode 100644 library/SubcircuitLibrary/SN74ACT86/SN74ACT86-cache.lib create mode 100644 library/SubcircuitLibrary/SN74ACT86/SN74ACT86.cir create mode 100644 library/SubcircuitLibrary/SN74ACT86/SN74ACT86.cir.out create mode 100644 library/SubcircuitLibrary/SN74ACT86/SN74ACT86.pro create mode 100644 library/SubcircuitLibrary/SN74ACT86/SN74ACT86.sch create mode 100644 library/SubcircuitLibrary/SN74ACT86/SN74ACT86.sub create mode 100644 library/SubcircuitLibrary/SN74ACT86/SN74ACT86_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SN74ACT86/analysis diff --git a/library/SubcircuitLibrary/CA3045/BC107.lib b/library/SubcircuitLibrary/CA3045/BC107.lib new file mode 100644 index 000000000..86233eda5 --- /dev/null +++ b/library/SubcircuitLibrary/CA3045/BC107.lib @@ -0,0 +1 @@ +.MODEL BC107 NPN( Is=1.527f Xti=3 Eg=1.11 Vaf=1.06.8 Bf=334.5 Ne=1.642 Ise=222f Ikf=0.1596 Xtb=1.5 Br=0788 Nc=2 Isc=0 Ikr=0 Rc=0.6 Cjc=6.072p Mjc=.3333 Vjc=.75 Fc=.5 Cje=10.67p Mje=.3333 Vje=.75 Tr=10n Tf=471.8p Itf=0 Vtf=0 Xtf=0 Rb=3 ) diff --git a/library/SubcircuitLibrary/CA3045/CA3045-cache.lib b/library/SubcircuitLibrary/CA3045/CA3045-cache.lib new file mode 100644 index 000000000..12536e1ea --- /dev/null +++ b/library/SubcircuitLibrary/CA3045/CA3045-cache.lib @@ -0,0 +1,67 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# BC107 +# +DEF BC107 Q 0 0 Y N 1 F N +F0 "Q" 200 75 50 H V L CNN +F1 "BC107" 200 0 50 H V L CNN +F2 "TO_SOT_Packages_THT:TO-18-3" 200 -75 50 H I L CIN +F3 "" 0 0 50 H I L CNN +ALIAS BC108 BC109 +$FPLIST + TO?18* +$ENDFPLIST +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X E 1 100 -200 100 U 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 I +X C 3 100 200 100 D 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CA3045/CA3045.cir b/library/SubcircuitLibrary/CA3045/CA3045.cir new file mode 100644 index 000000000..277267c6f --- /dev/null +++ b/library/SubcircuitLibrary/CA3045/CA3045.cir @@ -0,0 +1,16 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\CA3045\CA3045.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/19/25 22:04:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_Q1-Pad3_ Net-_Q1-Pad2_ Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad1_ Net-_Q3-Pad3_ Net-_Q5-Pad2_ Net-_Q5-Pad1_ Net-_Q5-Pad3_ Net-_Q4-Pad2_ Net-_Q4-Pad1_ Net-_Q4-Pad3_ PORT +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ BC107 +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ BC107 +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ BC107 +Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ BC107 +Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ BC107 + +.end diff --git a/library/SubcircuitLibrary/CA3045/CA3045.cir.out b/library/SubcircuitLibrary/CA3045/CA3045.cir.out new file mode 100644 index 000000000..81fd92528 --- /dev/null +++ b/library/SubcircuitLibrary/CA3045/CA3045.cir.out @@ -0,0 +1,18 @@ +* d:\fossee\esim\library\subcircuitlibrary\ca3045\ca3045.cir + +.include BC107.lib +* u1 net-_q1-pad3_ net-_q1-pad2_ net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q3-pad3_ net-_q5-pad2_ net-_q5-pad1_ net-_q5-pad3_ net-_q4-pad2_ net-_q4-pad1_ net-_q4-pad3_ port +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ BC107 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ BC107 +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ BC107 +q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ BC107 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ BC107 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CA3045/CA3045.pro b/library/SubcircuitLibrary/CA3045/CA3045.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/CA3045/CA3045.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CA3045/CA3045.sch b/library/SubcircuitLibrary/CA3045/CA3045.sch new file mode 100644 index 000000000..253496a40 --- /dev/null +++ b/library/SubcircuitLibrary/CA3045/CA3045.sch @@ -0,0 +1,319 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CA3045-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4800 2550 4800 2150 +Wire Wire Line + 4800 2150 4200 2150 +Wire Wire Line + 4500 2750 4200 2750 +Wire Wire Line + 4800 2950 4800 3450 +Wire Wire Line + 4800 3200 4200 3200 +Connection ~ 4800 3200 +Wire Wire Line + 4500 3650 4200 3650 +Wire Wire Line + 4800 3850 4800 4100 +Wire Wire Line + 4800 4100 4200 4100 +Wire Wire Line + 6200 2600 6200 2350 +Wire Wire Line + 6200 2350 6500 2350 +Wire Wire Line + 5900 2800 5800 2800 +Wire Wire Line + 5800 2800 5800 3350 +Wire Wire Line + 5800 3350 6500 3350 +Wire Wire Line + 6200 3000 6200 3100 +Wire Wire Line + 6200 3100 6500 3100 +Wire Wire Line + 6200 3650 6200 3550 +Wire Wire Line + 6200 3550 6500 3550 +Wire Wire Line + 6200 4050 6200 4200 +Wire Wire Line + 6200 4200 6500 4200 +Wire Wire Line + 5900 3850 5750 3850 +Wire Wire Line + 5750 3850 5750 4450 +Wire Wire Line + 5750 4450 6500 4450 +Wire Wire Line + 5250 4450 5250 4350 +Wire Wire Line + 5250 4350 4200 4350 +Wire Wire Line + 5050 4750 4200 4750 +Wire Wire Line + 5450 4750 6500 4750 +$Comp +L PORT U1 +U 1 1 687BB83F +P 3950 2150 +F 0 "U1" H 4000 2250 30 0000 C CNN +F 1 "PORT" H 3950 2150 30 0000 C CNN +F 2 "" H 3950 2150 60 0000 C CNN +F 3 "" H 3950 2150 60 0000 C CNN + 1 3950 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 687BB884 +P 3950 2750 +F 0 "U1" H 4000 2850 30 0000 C CNN +F 1 "PORT" H 3950 2750 30 0000 C CNN +F 2 "" H 3950 2750 60 0000 C CNN +F 3 "" H 3950 2750 60 0000 C CNN + 2 3950 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 687BB905 +P 3950 3200 +F 0 "U1" H 4000 3300 30 0000 C CNN +F 1 "PORT" H 3950 3200 30 0000 C CNN +F 2 "" H 3950 3200 60 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 3 3950 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 687BB92E +P 3950 3650 +F 0 "U1" H 4000 3750 30 0000 C CNN +F 1 "PORT" H 3950 3650 30 0000 C CNN +F 2 "" H 3950 3650 60 0000 C CNN +F 3 "" H 3950 3650 60 0000 C CNN + 4 3950 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 687BB96C +P 3950 4100 +F 0 "U1" H 4000 4200 30 0000 C CNN +F 1 "PORT" H 3950 4100 30 0000 C CNN +F 2 "" H 3950 4100 60 0000 C CNN +F 3 "" H 3950 4100 60 0000 C CNN + 5 3950 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 687BBA17 +P 3950 4350 +F 0 "U1" H 4000 4450 30 0000 C CNN +F 1 "PORT" H 3950 4350 30 0000 C CNN +F 2 "" H 3950 4350 60 0000 C CNN +F 3 "" H 3950 4350 60 0000 C CNN + 6 3950 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 687BBA5C +P 3950 4750 +F 0 "U1" H 4000 4850 30 0000 C CNN +F 1 "PORT" H 3950 4750 30 0000 C CNN +F 2 "" H 3950 4750 60 0000 C CNN +F 3 "" H 3950 4750 60 0000 C CNN + 7 3950 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 687BBAA9 +P 6750 3100 +F 0 "U1" H 6800 3200 30 0000 C CNN +F 1 "PORT" H 6750 3100 30 0000 C CNN +F 2 "" H 6750 3100 60 0000 C CNN +F 3 "" H 6750 3100 60 0000 C CNN + 13 6750 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 687BBB0C +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 12 6750 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 687BBB53 +P 6750 3550 +F 0 "U1" H 6800 3650 30 0000 C CNN +F 1 "PORT" H 6750 3550 30 0000 C CNN +F 2 "" H 6750 3550 60 0000 C CNN +F 3 "" H 6750 3550 60 0000 C CNN + 11 6750 3550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 687BBBA4 +P 6750 4200 +F 0 "U1" H 6800 4300 30 0000 C CNN +F 1 "PORT" H 6750 4200 30 0000 C CNN +F 2 "" H 6750 4200 60 0000 C CNN +F 3 "" H 6750 4200 60 0000 C CNN + 10 6750 4200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 687BBBF3 +P 6750 4450 +F 0 "U1" H 6800 4550 30 0000 C CNN +F 1 "PORT" H 6750 4450 30 0000 C CNN +F 2 "" H 6750 4450 60 0000 C CNN +F 3 "" H 6750 4450 60 0000 C CNN + 9 6750 4450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 687BBC40 +P 6750 4750 +F 0 "U1" H 6800 4850 30 0000 C CNN +F 1 "PORT" H 6750 4750 30 0000 C CNN +F 2 "" H 6750 4750 60 0000 C CNN +F 3 "" H 6750 4750 60 0000 C CNN + 8 6750 4750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 687BBC87 +P 6750 2350 +F 0 "U1" H 6800 2450 30 0000 C CNN +F 1 "PORT" H 6750 2350 30 0000 C CNN +F 2 "" H 6750 2350 60 0000 C CNN +F 3 "" H 6750 2350 60 0000 C CNN + 14 6750 2350 + -1 0 0 1 +$EndComp +$Comp +L BC107 Q1 +U 1 1 687BCA58 +P 4700 2750 +F 0 "Q1" H 4900 2825 50 0000 L CNN +F 1 "BC107" H 4900 2750 50 0000 L CNN +F 2 "TO_SOT_Packages_THT:TO-18-3" H 4900 2675 50 0001 L CIN +F 3 "" H 4700 2750 50 0001 L CNN + 1 4700 2750 + 1 0 0 -1 +$EndComp +$Comp +L BC107 Q2 +U 1 1 687BCAB0 +P 4700 3650 +F 0 "Q2" H 4900 3725 50 0000 L CNN +F 1 "BC107" H 4900 3650 50 0000 L CNN +F 2 "TO_SOT_Packages_THT:TO-18-3" H 4900 3575 50 0001 L CIN +F 3 "" H 4700 3650 50 0001 L CNN + 1 4700 3650 + 1 0 0 1 +$EndComp +$Comp +L BC107 Q3 +U 1 1 687BCB2F +P 5250 4650 +F 0 "Q3" H 5450 4725 50 0000 L CNN +F 1 "BC107" H 5450 4650 50 0000 L CNN +F 2 "TO_SOT_Packages_THT:TO-18-3" H 5450 4575 50 0001 L CIN +F 3 "" H 5250 4650 50 0001 L CNN + 1 5250 4650 + 0 1 1 0 +$EndComp +$Comp +L BC107 Q5 +U 1 1 687BCB98 +P 6100 3850 +F 0 "Q5" H 6300 3925 50 0000 L CNN +F 1 "BC107" H 6300 3850 50 0000 L CNN +F 2 "TO_SOT_Packages_THT:TO-18-3" H 6300 3775 50 0001 L CIN +F 3 "" H 6100 3850 50 0001 L CNN + 1 6100 3850 + 1 0 0 -1 +$EndComp +$Comp +L BC107 Q4 +U 1 1 687BCBF4 +P 6100 2800 +F 0 "Q4" H 6300 2875 50 0000 L CNN +F 1 "BC107" H 6300 2800 50 0000 L CNN +F 2 "TO_SOT_Packages_THT:TO-18-3" H 6300 2725 50 0001 L CIN +F 3 "" H 6100 2800 50 0001 L CNN + 1 6100 2800 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CA3045/CA3045.sub b/library/SubcircuitLibrary/CA3045/CA3045.sub new file mode 100644 index 000000000..4f17c68a1 --- /dev/null +++ b/library/SubcircuitLibrary/CA3045/CA3045.sub @@ -0,0 +1,12 @@ +* Subcircuit CA3045 +.subckt CA3045 net-_q1-pad3_ net-_q1-pad2_ net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q3-pad3_ net-_q5-pad2_ net-_q5-pad1_ net-_q5-pad3_ net-_q4-pad2_ net-_q4-pad1_ net-_q4-pad3_ +* d:\fossee\esim\library\subcircuitlibrary\ca3045\ca3045.cir +.include BC107.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ BC107 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ BC107 +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ BC107 +q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ BC107 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ BC107 +* Control Statements + +.ends CA3045 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3045/CA3045_Previous_Values.xml b/library/SubcircuitLibrary/CA3045/CA3045_Previous_Values.xml new file mode 100644 index 000000000..68d8b91dc --- /dev/null +++ b/library/SubcircuitLibrary/CA3045/CA3045_Previous_Values.xml @@ -0,0 +1 @@ +D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC107\BC107.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC107\BC107.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC107\BC107.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC107\BC107.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC107\BC107.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3045/NPN.lib b/library/SubcircuitLibrary/CA3045/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/CA3045/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/CA3045/analysis b/library/SubcircuitLibrary/CA3045/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CA3045/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4555/3_and-cache.lib b/library/SubcircuitLibrary/CD4555/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4555/3_and.cir b/library/SubcircuitLibrary/CD4555/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4555/3_and.cir.out b/library/SubcircuitLibrary/CD4555/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4555/3_and.pro b/library/SubcircuitLibrary/CD4555/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/CD4555/3_and.sch b/library/SubcircuitLibrary/CD4555/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4555/3_and.sub b/library/SubcircuitLibrary/CD4555/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4555/3_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4555/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4555/CD4555-cache.lib b/library/SubcircuitLibrary/CD4555/CD4555-cache.lib new file mode 100644 index 000000000..ca3dbb873 --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/CD4555-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4555/CD4555.cir b/library/SubcircuitLibrary/CD4555/CD4555.cir new file mode 100644 index 000000000..64fa48caa --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/CD4555.cir @@ -0,0 +1,45 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\CD4555\CD4555.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/15/25 14:55:06 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter +U5 Net-_U2-Pad2_ Net-_U5-Pad2_ d_inverter +U3 Net-_U1-Pad3_ Net-_U3-Pad2_ d_inverter +U6 Net-_U3-Pad2_ Net-_U6-Pad2_ d_inverter +U4 Net-_U1-Pad1_ Net-_U4-Pad2_ d_inverter +X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U12-Pad1_ 3_and +X2 Net-_U5-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U13-Pad1_ 3_and +X3 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U4-Pad2_ Net-_U14-Pad1_ 3_and +X4 Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U4-Pad2_ Net-_U15-Pad1_ 3_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U7 Net-_U1-Pad14_ Net-_U10-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U8 Net-_U1-Pad13_ Net-_U11-Pad1_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U9 Net-_U1-Pad15_ Net-_U9-Pad2_ d_inverter +X5 Net-_U10-Pad1_ Net-_U11-Pad1_ Net-_U9-Pad2_ Net-_U16-Pad1_ 3_and +X6 Net-_U10-Pad2_ Net-_U11-Pad1_ Net-_U9-Pad2_ Net-_U17-Pad1_ 3_and +X7 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U9-Pad2_ Net-_U18-Pad1_ 3_and +X8 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U9-Pad2_ Net-_U19-Pad1_ 3_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter +U20 Net-_U12-Pad2_ Net-_U1-Pad4_ d_inverter +U21 Net-_U13-Pad2_ Net-_U1-Pad5_ d_inverter +U22 Net-_U14-Pad2_ Net-_U1-Pad6_ d_inverter +U23 Net-_U15-Pad2_ Net-_U1-Pad7_ d_inverter +U24 Net-_U16-Pad2_ Net-_U1-Pad12_ d_inverter +U25 Net-_U17-Pad2_ Net-_U1-Pad11_ d_inverter +U26 Net-_U18-Pad2_ Net-_U1-Pad10_ d_inverter +U27 Net-_U19-Pad2_ Net-_U1-Pad9_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/CD4555/CD4555.cir.out b/library/SubcircuitLibrary/CD4555/CD4555.cir.out new file mode 100644 index 000000000..661e9a7ab --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/CD4555.cir.out @@ -0,0 +1,125 @@ +* d:\fossee\esim\library\subcircuitlibrary\cd4555\cd4555.cir + +.include 3_and.sub +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u5 net-_u2-pad2_ net-_u5-pad2_ d_inverter +* u3 net-_u1-pad3_ net-_u3-pad2_ d_inverter +* u6 net-_u3-pad2_ net-_u6-pad2_ d_inverter +* u4 net-_u1-pad1_ net-_u4-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u12-pad1_ 3_and +x2 net-_u5-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u13-pad1_ 3_and +x3 net-_u2-pad2_ net-_u6-pad2_ net-_u4-pad2_ net-_u14-pad1_ 3_and +x4 net-_u5-pad2_ net-_u6-pad2_ net-_u4-pad2_ net-_u15-pad1_ 3_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u7 net-_u1-pad14_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u8 net-_u1-pad13_ net-_u11-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u9 net-_u1-pad15_ net-_u9-pad2_ d_inverter +x5 net-_u10-pad1_ net-_u11-pad1_ net-_u9-pad2_ net-_u16-pad1_ 3_and +x6 net-_u10-pad2_ net-_u11-pad1_ net-_u9-pad2_ net-_u17-pad1_ 3_and +x7 net-_u10-pad1_ net-_u11-pad2_ net-_u9-pad2_ net-_u18-pad1_ 3_and +x8 net-_u10-pad2_ net-_u11-pad2_ net-_u9-pad2_ net-_u19-pad1_ 3_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u20 net-_u12-pad2_ net-_u1-pad4_ d_inverter +* u21 net-_u13-pad2_ net-_u1-pad5_ d_inverter +* u22 net-_u14-pad2_ net-_u1-pad6_ d_inverter +* u23 net-_u15-pad2_ net-_u1-pad7_ d_inverter +* u24 net-_u16-pad2_ net-_u1-pad12_ d_inverter +* u25 net-_u17-pad2_ net-_u1-pad11_ d_inverter +* u26 net-_u18-pad2_ net-_u1-pad10_ d_inverter +* u27 net-_u19-pad2_ net-_u1-pad9_ d_inverter +a1 net-_u1-pad2_ net-_u2-pad2_ u2 +a2 net-_u2-pad2_ net-_u5-pad2_ u5 +a3 net-_u1-pad3_ net-_u3-pad2_ u3 +a4 net-_u3-pad2_ net-_u6-pad2_ u6 +a5 net-_u1-pad1_ net-_u4-pad2_ u4 +a6 net-_u1-pad14_ net-_u10-pad1_ u7 +a7 net-_u10-pad1_ net-_u10-pad2_ u10 +a8 net-_u1-pad13_ net-_u11-pad1_ u8 +a9 net-_u11-pad1_ net-_u11-pad2_ u11 +a10 net-_u1-pad15_ net-_u9-pad2_ u9 +a11 net-_u12-pad1_ net-_u12-pad2_ u12 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u14-pad1_ net-_u14-pad2_ u14 +a14 net-_u15-pad1_ net-_u15-pad2_ u15 +a15 net-_u16-pad1_ net-_u16-pad2_ u16 +a16 net-_u17-pad1_ net-_u17-pad2_ u17 +a17 net-_u18-pad1_ net-_u18-pad2_ u18 +a18 net-_u19-pad1_ net-_u19-pad2_ u19 +a19 net-_u12-pad2_ net-_u1-pad4_ u20 +a20 net-_u13-pad2_ net-_u1-pad5_ u21 +a21 net-_u14-pad2_ net-_u1-pad6_ u22 +a22 net-_u15-pad2_ net-_u1-pad7_ u23 +a23 net-_u16-pad2_ net-_u1-pad12_ u24 +a24 net-_u17-pad2_ net-_u1-pad11_ u25 +a25 net-_u18-pad2_ net-_u1-pad10_ u26 +a26 net-_u19-pad2_ net-_u1-pad9_ u27 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4555/CD4555.pro b/library/SubcircuitLibrary/CD4555/CD4555.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/CD4555.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4555/CD4555.sch b/library/SubcircuitLibrary/CD4555/CD4555.sch new file mode 100644 index 000000000..01011d79e --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/CD4555.sch @@ -0,0 +1,779 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4555-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 687607FC +P 2400 2050 +F 0 "U2" H 2400 1950 60 0000 C CNN +F 1 "d_inverter" H 2400 2200 60 0000 C CNN +F 2 "" H 2450 2000 60 0000 C CNN +F 3 "" H 2450 2000 60 0000 C CNN + 1 2400 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 687608C6 +P 3400 2050 +F 0 "U5" H 3400 1950 60 0000 C CNN +F 1 "d_inverter" H 3400 2200 60 0000 C CNN +F 2 "" H 3450 2000 60 0000 C CNN +F 3 "" H 3450 2000 60 0000 C CNN + 1 3400 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 68760AF0 +P 2450 2750 +F 0 "U3" H 2450 2650 60 0000 C CNN +F 1 "d_inverter" H 2450 2900 60 0000 C CNN +F 2 "" H 2500 2700 60 0000 C CNN +F 3 "" H 2500 2700 60 0000 C CNN + 1 2450 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 68760B2D +P 3400 2750 +F 0 "U6" H 3400 2650 60 0000 C CNN +F 1 "d_inverter" H 3400 2900 60 0000 C CNN +F 2 "" H 3450 2700 60 0000 C CNN +F 3 "" H 3450 2700 60 0000 C CNN + 1 3400 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68760CDA +P 2500 3450 +F 0 "U4" H 2500 3350 60 0000 C CNN +F 1 "d_inverter" H 2500 3600 60 0000 C CNN +F 2 "" H 2550 3400 60 0000 C CNN +F 3 "" H 2550 3400 60 0000 C CNN + 1 2500 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 2050 1600 2050 +Wire Wire Line + 2700 2050 3100 2050 +Wire Wire Line + 3700 2050 3950 2050 +Wire Wire Line + 2150 2750 1600 2750 +Wire Wire Line + 2750 2750 3100 2750 +Wire Wire Line + 2200 3450 1600 3450 +$Comp +L 3_and X1 +U 1 1 68760DDF +P 5000 1850 +F 0 "X1" H 5100 1800 60 0000 C CNN +F 1 "3_and" H 5150 2000 60 0000 C CNN +F 2 "" H 5000 1850 60 0000 C CNN +F 3 "" H 5000 1850 60 0000 C CNN + 1 5000 1850 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 68760E1C +P 5000 2350 +F 0 "X2" H 5100 2300 60 0000 C CNN +F 1 "3_and" H 5150 2500 60 0000 C CNN +F 2 "" H 5000 2350 60 0000 C CNN +F 3 "" H 5000 2350 60 0000 C CNN + 1 5000 2350 + 1 0 0 -1 +$EndComp +$Comp +L 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1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6876137F +P 1350 2750 +F 0 "U1" H 1400 2850 30 0000 C CNN +F 1 "PORT" H 1350 2750 30 0000 C CNN +F 2 "" H 1350 2750 60 0000 C CNN +F 3 "" H 1350 2750 60 0000 C CNN + 3 1350 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68761487 +P 8350 1800 +F 0 "U1" H 8400 1900 30 0000 C CNN +F 1 "PORT" H 8350 1800 30 0000 C CNN +F 2 "" H 8350 1800 60 0000 C CNN +F 3 "" H 8350 1800 60 0000 C CNN + 4 8350 1800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 687614F8 +P 8300 2800 +F 0 "U1" H 8350 2900 30 0000 C CNN +F 1 "PORT" H 8300 2800 30 0000 C CNN +F 2 "" H 8300 2800 60 0000 C CNN +F 3 "" H 8300 2800 60 0000 C CNN + 6 8300 2800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 6876163C +P 8300 3350 +F 0 "U1" H 8350 3450 30 0000 C CNN +F 1 "PORT" H 8300 3350 30 0000 C CNN +F 2 "" H 8300 3350 60 0000 C CNN +F 3 "" H 8300 3350 60 0000 C CNN + 7 8300 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 68761693 +P 8350 2300 +F 0 "U1" H 8400 2400 30 0000 C CNN +F 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11 8100 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 6876189E +P 8100 4100 +F 0 "U1" H 8150 4200 30 0000 C CNN +F 1 "PORT" H 8100 4100 30 0000 C CNN +F 2 "" H 8100 4100 60 0000 C CNN +F 3 "" H 8100 4100 60 0000 C CNN + 12 8100 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 687618EF +P 1750 5050 +F 0 "U1" H 1800 5150 30 0000 C CNN +F 1 "PORT" H 1750 5050 30 0000 C CNN +F 2 "" H 1750 5050 60 0000 C CNN +F 3 "" H 1750 5050 60 0000 C CNN + 13 1750 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 6876193A +P 1750 4350 +F 0 "U1" H 1800 4450 30 0000 C CNN +F 1 "PORT" H 1750 4350 30 0000 C CNN +F 2 "" H 1750 4350 60 0000 C CNN +F 3 "" H 1750 4350 60 0000 C CNN + 14 1750 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 687621F9 +P 1750 5750 +F 0 "U1" H 1800 5850 30 0000 C CNN +F 1 "PORT" H 1750 5750 30 0000 C CNN +F 2 "" H 1750 5750 60 0000 C CNN +F 3 "" H 1750 5750 60 0000 C CNN + 15 1750 5750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 6876226E +P 950 4300 +F 0 "U1" H 1000 4400 30 0000 C CNN +F 1 "PORT" H 950 4300 30 0000 C CNN +F 2 "" H 950 4300 60 0000 C CNN +F 3 "" H 950 4300 60 0000 C CNN + 16 950 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 687636D9 +P 2800 4350 +F 0 "U7" H 2800 4250 60 0000 C CNN +F 1 "d_inverter" H 2800 4500 60 0000 C CNN +F 2 "" H 2850 4300 60 0000 C CNN +F 3 "" H 2850 4300 60 0000 C CNN + 1 2800 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 687636DF +P 3800 4350 +F 0 "U10" H 3800 4250 60 0000 C CNN +F 1 "d_inverter" H 3800 4500 60 0000 C CNN +F 2 "" H 3850 4300 60 0000 C CNN +F 3 "" H 3850 4300 60 0000 C CNN + 1 3800 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 687636E5 +P 2850 5050 +F 0 "U8" H 2850 4950 60 0000 C CNN +F 1 "d_inverter" H 2850 5200 60 0000 C CNN +F 2 "" H 2900 5000 60 0000 C CNN +F 3 "" H 2900 5000 60 0000 C CNN + 1 2850 5050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 687636EB +P 3800 5050 +F 0 "U11" H 3800 4950 60 0000 C CNN +F 1 "d_inverter" H 3800 5200 60 0000 C CNN +F 2 "" H 3850 5000 60 0000 C CNN +F 3 "" H 3850 5000 60 0000 C CNN + 1 3800 5050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 687636F1 +P 2900 5750 +F 0 "U9" H 2900 5650 60 0000 C CNN +F 1 "d_inverter" H 2900 5900 60 0000 C CNN +F 2 "" H 2950 5700 60 0000 C CNN +F 3 "" H 2950 5700 60 0000 C CNN + 1 2900 5750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2500 4350 2000 4350 +Wire Wire Line + 3100 4350 3500 4350 +Wire Wire Line + 4100 4350 4350 4350 +Wire Wire Line + 2550 5050 2000 5050 +Wire Wire Line + 3150 5050 3500 5050 +Wire Wire Line + 2600 5750 2000 5750 +$Comp +L 3_and X5 +U 1 1 687636FD +P 5400 4150 +F 0 "X5" H 5500 4100 60 0000 C CNN +F 1 "3_and" H 5550 4300 60 0000 C CNN +F 2 "" H 5400 4150 60 0000 C CNN +F 3 "" H 5400 4150 60 0000 C CNN + 1 5400 4150 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X6 +U 1 1 68763703 +P 5400 4650 +F 0 "X6" H 5500 4600 60 0000 C CNN +F 1 "3_and" H 5550 4800 60 0000 C CNN +F 2 "" H 5400 4650 60 0000 C CNN +F 3 "" H 5400 4650 60 0000 C CNN + 1 5400 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H 5900 2450 60 0000 C CNN +F 2 "" H 5950 2250 60 0000 C CNN +F 3 "" H 5950 2250 60 0000 C CNN + 1 5900 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 687667C6 +P 5900 2800 +F 0 "U14" H 5900 2700 60 0000 C CNN +F 1 "d_inverter" H 5900 2950 60 0000 C CNN +F 2 "" H 5950 2750 60 0000 C CNN +F 3 "" H 5950 2750 60 0000 C CNN + 1 5900 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 68766859 +P 5900 3350 +F 0 "U15" H 5900 3250 60 0000 C CNN +F 1 "d_inverter" H 5900 3500 60 0000 C CNN +F 2 "" H 5950 3300 60 0000 C CNN +F 3 "" H 5950 3300 60 0000 C CNN + 1 5900 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5500 1800 5600 1800 +Wire Wire Line + 5500 2300 5600 2300 +Wire Wire Line + 5500 2800 5600 2800 +Wire Wire Line + 5500 3350 5600 3350 +$Comp +L d_inverter U16 +U 1 1 687670D2 +P 6250 4100 +F 0 "U16" H 6250 4000 60 0000 C CNN +F 1 "d_inverter" H 6250 4250 60 0000 C CNN +F 2 "" H 6300 4050 60 0000 C CNN +F 3 "" H 6300 4050 60 0000 C CNN + 1 6250 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 687670D8 +P 6250 4600 +F 0 "U17" H 6250 4500 60 0000 C CNN +F 1 "d_inverter" H 6250 4750 60 0000 C CNN +F 2 "" H 6300 4550 60 0000 C CNN +F 3 "" H 6300 4550 60 0000 C CNN + 1 6250 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 687670DE +P 6250 5100 +F 0 "U18" H 6250 5000 60 0000 C CNN +F 1 "d_inverter" H 6250 5250 60 0000 C CNN +F 2 "" H 6300 5050 60 0000 C CNN +F 3 "" H 6300 5050 60 0000 C CNN + 1 6250 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 687670E4 +P 6250 5650 +F 0 "U19" H 6250 5550 60 0000 C CNN +F 1 "d_inverter" H 6250 5800 60 0000 C CNN +F 2 "" H 6300 5600 60 0000 C CNN +F 3 "" H 6300 5600 60 0000 C CNN + 1 6250 5650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 4100 5950 4100 +Wire Wire Line + 5900 4600 5950 4600 +Wire Wire Line + 5900 5100 5950 5100 +Wire Wire Line + 5900 5650 5950 5650 +$Comp +L d_inverter U20 +U 1 1 6876221E +P 6750 1800 +F 0 "U20" H 6750 1700 60 0000 C CNN +F 1 "d_inverter" H 6750 1950 60 0000 C CNN +F 2 "" H 6800 1750 60 0000 C CNN +F 3 "" H 6800 1750 60 0000 C CNN + 1 6750 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 687622E6 +P 6750 2300 +F 0 "U21" H 6750 2200 60 0000 C CNN +F 1 "d_inverter" H 6750 2450 60 0000 C CNN +F 2 "" H 6800 2250 60 0000 C CNN +F 3 "" H 6800 2250 60 0000 C CNN + 1 6750 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 6876238C +P 6750 2800 +F 0 "U22" H 6750 2700 60 0000 C CNN +F 1 "d_inverter" H 6750 2950 60 0000 C CNN +F 2 "" H 6800 2750 60 0000 C CNN +F 3 "" H 6800 2750 60 0000 C CNN + 1 6750 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 68762433 +P 6750 3350 +F 0 "U23" H 6750 3250 60 0000 C CNN +F 1 "d_inverter" H 6750 3500 60 0000 C CNN +F 2 "" H 6800 3300 60 0000 C CNN +F 3 "" H 6800 3300 60 0000 C CNN + 1 6750 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6200 1800 6450 1800 +Wire Wire Line + 6200 2300 6450 2300 +Wire Wire Line + 6200 2800 6450 2800 +Wire Wire Line + 6200 3350 6450 3350 +$Comp +L d_inverter U24 +U 1 1 6876338B +P 7200 4100 +F 0 "U24" H 7200 4000 60 0000 C CNN +F 1 "d_inverter" H 7200 4250 60 0000 C CNN +F 2 "" H 7250 4050 60 0000 C CNN +F 3 "" H 7250 4050 60 0000 C CNN + 1 7200 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 68763391 +P 7200 4600 +F 0 "U25" H 7200 4500 60 0000 C CNN +F 1 "d_inverter" H 7200 4750 60 0000 C CNN +F 2 "" H 7250 4550 60 0000 C CNN +F 3 "" H 7250 4550 60 0000 C CNN + 1 7200 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U26 +U 1 1 68763397 +P 7200 5100 +F 0 "U26" H 7200 5000 60 0000 C CNN +F 1 "d_inverter" H 7200 5250 60 0000 C CNN +F 2 "" H 7250 5050 60 0000 C CNN +F 3 "" H 7250 5050 60 0000 C CNN + 1 7200 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U27 +U 1 1 6876339D +P 7200 5650 +F 0 "U27" H 7200 5550 60 0000 C CNN +F 1 "d_inverter" H 7200 5800 60 0000 C CNN +F 2 "" H 7250 5600 60 0000 C CNN +F 3 "" H 7250 5600 60 0000 C CNN + 1 7200 5650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6550 4600 6900 4600 +Wire Wire Line + 6550 5100 6900 5100 +Wire Wire Line + 6900 5650 6550 5650 +Wire Wire Line + 6550 4100 6900 4100 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4555/CD4555.sub b/library/SubcircuitLibrary/CD4555/CD4555.sub new file mode 100644 index 000000000..18b4b7840 --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/CD4555.sub @@ -0,0 +1,119 @@ +* Subcircuit CD4555 +.subckt CD4555 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* d:\fossee\esim\library\subcircuitlibrary\cd4555\cd4555.cir +.include 3_and.sub +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u5 net-_u2-pad2_ net-_u5-pad2_ d_inverter +* u3 net-_u1-pad3_ net-_u3-pad2_ d_inverter +* u6 net-_u3-pad2_ net-_u6-pad2_ d_inverter +* u4 net-_u1-pad1_ net-_u4-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u12-pad1_ 3_and +x2 net-_u5-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u13-pad1_ 3_and +x3 net-_u2-pad2_ net-_u6-pad2_ net-_u4-pad2_ net-_u14-pad1_ 3_and +x4 net-_u5-pad2_ net-_u6-pad2_ net-_u4-pad2_ net-_u15-pad1_ 3_and +* u7 net-_u1-pad14_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u8 net-_u1-pad13_ net-_u11-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u9 net-_u1-pad15_ net-_u9-pad2_ d_inverter +x5 net-_u10-pad1_ net-_u11-pad1_ net-_u9-pad2_ net-_u16-pad1_ 3_and +x6 net-_u10-pad2_ net-_u11-pad1_ net-_u9-pad2_ net-_u17-pad1_ 3_and +x7 net-_u10-pad1_ net-_u11-pad2_ net-_u9-pad2_ net-_u18-pad1_ 3_and +x8 net-_u10-pad2_ net-_u11-pad2_ net-_u9-pad2_ net-_u19-pad1_ 3_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u20 net-_u12-pad2_ net-_u1-pad4_ d_inverter +* u21 net-_u13-pad2_ net-_u1-pad5_ d_inverter +* u22 net-_u14-pad2_ net-_u1-pad6_ d_inverter +* u23 net-_u15-pad2_ net-_u1-pad7_ d_inverter +* u24 net-_u16-pad2_ net-_u1-pad12_ d_inverter +* u25 net-_u17-pad2_ net-_u1-pad11_ d_inverter +* u26 net-_u18-pad2_ net-_u1-pad10_ d_inverter +* u27 net-_u19-pad2_ net-_u1-pad9_ d_inverter +a1 net-_u1-pad2_ net-_u2-pad2_ u2 +a2 net-_u2-pad2_ net-_u5-pad2_ u5 +a3 net-_u1-pad3_ net-_u3-pad2_ u3 +a4 net-_u3-pad2_ net-_u6-pad2_ u6 +a5 net-_u1-pad1_ net-_u4-pad2_ u4 +a6 net-_u1-pad14_ net-_u10-pad1_ u7 +a7 net-_u10-pad1_ net-_u10-pad2_ u10 +a8 net-_u1-pad13_ net-_u11-pad1_ u8 +a9 net-_u11-pad1_ net-_u11-pad2_ u11 +a10 net-_u1-pad15_ net-_u9-pad2_ u9 +a11 net-_u12-pad1_ net-_u12-pad2_ u12 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u14-pad1_ net-_u14-pad2_ u14 +a14 net-_u15-pad1_ net-_u15-pad2_ u15 +a15 net-_u16-pad1_ net-_u16-pad2_ u16 +a16 net-_u17-pad1_ net-_u17-pad2_ u17 +a17 net-_u18-pad1_ net-_u18-pad2_ u18 +a18 net-_u19-pad1_ net-_u19-pad2_ u19 +a19 net-_u12-pad2_ net-_u1-pad4_ u20 +a20 net-_u13-pad2_ net-_u1-pad5_ u21 +a21 net-_u14-pad2_ net-_u1-pad6_ u22 +a22 net-_u15-pad2_ net-_u1-pad7_ u23 +a23 net-_u16-pad2_ net-_u1-pad12_ u24 +a24 net-_u17-pad2_ net-_u1-pad11_ u25 +a25 net-_u18-pad2_ net-_u1-pad10_ u26 +a26 net-_u19-pad2_ net-_u1-pad9_ u27 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD4555 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4555/CD4555_Previous_Values.xml b/library/SubcircuitLibrary/CD4555/CD4555_Previous_Values.xml new file mode 100644 index 000000000..9e3fa465a --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/CD4555_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4555/analysis b/library/SubcircuitLibrary/CD4555/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CD4555/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54HC7266/CD54HC7266-cache.lib b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266-cache.lib new file mode 100644 index 000000000..889b42675 --- /dev/null +++ b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.cir b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.cir new file mode 100644 index 000000000..638061e4a --- /dev/null +++ b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.cir @@ -0,0 +1,35 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54HC7266\CD54HC7266.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/19/25 12:08:31 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U2 Net-_U10-Pad1_ Net-_U2-Pad2_ d_inverter +U9 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U17-Pad1_ d_and +U10 Net-_U10-Pad1_ Net-_U1-Pad2_ Net-_U10-Pad3_ d_and +U17 Net-_U17-Pad1_ Net-_U10-Pad3_ Net-_U17-Pad3_ d_or +U21 Net-_U17-Pad3_ Net-_U21-Pad2_ d_inverter +U3 Net-_U11-Pad1_ Net-_U12-Pad2_ d_inverter +U4 Net-_U12-Pad1_ Net-_U11-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U18-Pad3_ d_or +U22 Net-_U18-Pad3_ Net-_U22-Pad2_ d_inverter +U5 Net-_U13-Pad1_ Net-_U14-Pad2_ d_inverter +U6 Net-_U14-Pad1_ Net-_U13-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and +U19 Net-_U13-Pad3_ Net-_U14-Pad3_ Net-_U19-Pad3_ d_or +U23 Net-_U19-Pad3_ Net-_U23-Pad2_ d_inverter +U7 Net-_U15-Pad1_ Net-_U16-Pad2_ d_inverter +U8 Net-_U16-Pad1_ Net-_U15-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_and +U20 Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U20-Pad3_ d_or +U24 Net-_U20-Pad3_ Net-_U24-Pad2_ d_inverter +U25 Net-_U1-Pad1_ Net-_U10-Pad1_ Net-_U21-Pad2_ Net-_U22-Pad2_ Net-_U11-Pad1_ Net-_U12-Pad1_ ? Net-_U13-Pad1_ Net-_U14-Pad1_ Net-_U23-Pad2_ Net-_U24-Pad2_ Net-_U15-Pad1_ Net-_U16-Pad1_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.cir.out b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.cir.out new file mode 100644 index 000000000..93f87eeb5 --- /dev/null +++ b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.cir.out @@ -0,0 +1,108 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd54hc7266\cd54hc7266.cir + +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u10-pad1_ net-_u2-pad2_ d_inverter +* u9 net-_u1-pad1_ net-_u2-pad2_ net-_u17-pad1_ d_and +* u10 net-_u10-pad1_ net-_u1-pad2_ net-_u10-pad3_ d_and +* u17 net-_u17-pad1_ net-_u10-pad3_ net-_u17-pad3_ d_or +* u21 net-_u17-pad3_ net-_u21-pad2_ d_inverter +* u3 net-_u11-pad1_ net-_u12-pad2_ d_inverter +* u4 net-_u12-pad1_ net-_u11-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u18-pad3_ d_or +* u22 net-_u18-pad3_ net-_u22-pad2_ d_inverter +* u5 net-_u13-pad1_ net-_u14-pad2_ d_inverter +* u6 net-_u14-pad1_ net-_u13-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and +* u19 net-_u13-pad3_ net-_u14-pad3_ net-_u19-pad3_ d_or +* u23 net-_u19-pad3_ net-_u23-pad2_ d_inverter +* u7 net-_u15-pad1_ net-_u16-pad2_ d_inverter +* u8 net-_u16-pad1_ net-_u15-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u20 net-_u15-pad3_ net-_u16-pad3_ net-_u20-pad3_ d_or +* u24 net-_u20-pad3_ net-_u24-pad2_ d_inverter +* u25 net-_u1-pad1_ net-_u10-pad1_ net-_u21-pad2_ net-_u22-pad2_ net-_u11-pad1_ net-_u12-pad1_ ? net-_u13-pad1_ net-_u14-pad1_ net-_u23-pad2_ net-_u24-pad2_ net-_u15-pad1_ net-_u16-pad1_ ? port +a1 net-_u1-pad1_ net-_u1-pad2_ u1 +a2 net-_u10-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u17-pad1_ u9 +a4 [net-_u10-pad1_ net-_u1-pad2_ ] net-_u10-pad3_ u10 +a5 [net-_u17-pad1_ net-_u10-pad3_ ] net-_u17-pad3_ u17 +a6 net-_u17-pad3_ net-_u21-pad2_ u21 +a7 net-_u11-pad1_ net-_u12-pad2_ u3 +a8 net-_u12-pad1_ net-_u11-pad2_ u4 +a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a10 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a11 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u18-pad3_ u18 +a12 net-_u18-pad3_ net-_u22-pad2_ u22 +a13 net-_u13-pad1_ net-_u14-pad2_ u5 +a14 net-_u14-pad1_ net-_u13-pad2_ u6 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a17 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u19-pad3_ u19 +a18 net-_u19-pad3_ net-_u23-pad2_ u23 +a19 net-_u15-pad1_ net-_u16-pad2_ u7 +a20 net-_u16-pad1_ net-_u15-pad2_ u8 +a21 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a22 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a23 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u20-pad3_ u20 +a24 net-_u20-pad3_ net-_u24-pad2_ u24 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.pro b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.sch b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.sch new file mode 100644 index 000000000..41d078920 --- /dev/null +++ b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.sch @@ -0,0 +1,644 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U1 +U 1 1 6853AE81 +P 3150 2050 +F 0 "U1" H 3150 1950 60 0000 C CNN +F 1 "d_inverter" H 3150 2200 60 0000 C CNN +F 2 "" H 3200 2000 60 0000 C CNN +F 3 "" H 3200 2000 60 0000 C CNN + 1 3150 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6853AEEE +P 3150 3100 +F 0 "U2" H 3150 3000 60 0000 C CNN +F 1 "d_inverter" H 3150 3250 60 0000 C CNN +F 2 "" H 3200 3050 60 0000 C CNN +F 3 "" H 3200 3050 60 0000 C CNN + 1 3150 3100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 6853AF26 +P 4500 2100 +F 0 "U9" H 4500 2100 60 0000 C CNN +F 1 "d_and" H 4550 2200 60 0000 C CNN +F 2 "" H 4500 2100 60 0000 C CNN +F 3 "" H 4500 2100 60 0000 C CNN + 1 4500 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 6853AF82 +P 4500 2950 +F 0 "U10" H 4500 2950 60 0000 C CNN +F 1 "d_and" H 4550 3050 60 0000 C CNN +F 2 "" H 4500 2950 60 0000 C CNN +F 3 "" H 4500 2950 60 0000 C CNN + 1 4500 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2200 1750 4050 1750 +Wire Wire Line + 2600 1750 2600 2050 +Wire Wire Line + 2600 2050 2850 2050 +Connection ~ 2600 1750 +Wire Wire Line + 2250 2800 4050 2800 +Wire Wire Line + 2600 2800 2600 3100 +Wire Wire Line + 2600 3100 2850 3100 +Connection ~ 2600 2800 +Wire Wire Line + 4050 1750 4050 2000 +Wire Wire Line + 3450 3100 3900 3100 +Wire Wire Line + 3900 3100 3900 2100 +Wire Wire Line + 3900 2100 4050 2100 +Wire Wire Line + 4050 2800 4050 2850 +Wire Wire Line + 3450 2050 3650 2050 +Wire Wire Line + 3650 2050 3650 2950 +Wire Wire Line + 3650 2950 4050 2950 +$Comp +L d_or U17 +U 1 1 6853B01B +P 5700 2500 +F 0 "U17" H 5700 2500 60 0000 C CNN +F 1 "d_or" H 5700 2600 60 0000 C CNN +F 2 "" H 5700 2500 60 0000 C CNN +F 3 "" H 5700 2500 60 0000 C CNN + 1 5700 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 6853B068 +P 6800 2450 +F 0 "U21" H 6800 2350 60 0000 C CNN +F 1 "d_inverter" H 6800 2600 60 0000 C CNN +F 2 "" H 6850 2400 60 0000 C CNN +F 3 "" H 6850 2400 60 0000 C CNN + 1 6800 2450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4950 2050 5250 2050 +Wire Wire Line + 5250 2050 5250 2400 +Wire Wire Line + 4950 2900 5250 2900 +Wire Wire Line + 5250 2900 5250 2500 +Wire Wire Line + 6150 2450 6500 2450 +Wire Wire Line + 7100 2450 7300 2450 +$Comp +L d_inverter U3 +U 1 1 6853B24D +P 3150 4050 +F 0 "U3" H 3150 3950 60 0000 C CNN +F 1 "d_inverter" H 3150 4200 60 0000 C CNN +F 2 "" H 3200 4000 60 0000 C CNN +F 3 "" H 3200 4000 60 0000 C CNN + 1 3150 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6853B253 +P 3150 5100 +F 0 "U4" H 3150 5000 60 0000 C CNN +F 1 "d_inverter" H 3150 5250 60 0000 C CNN +F 2 "" H 3200 5050 60 0000 C CNN +F 3 "" H 3200 5050 60 0000 C CNN + 1 3150 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 6853B259 +P 4500 4100 +F 0 "U11" H 4500 4100 60 0000 C CNN +F 1 "d_and" H 4550 4200 60 0000 C CNN +F 2 "" H 4500 4100 60 0000 C CNN +F 3 "" H 4500 4100 60 0000 C CNN + 1 4500 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 6853B25F +P 4500 4950 +F 0 "U12" H 4500 4950 60 0000 C CNN +F 1 "d_and" H 4550 5050 60 0000 C CNN +F 2 "" H 4500 4950 60 0000 C CNN +F 3 "" H 4500 4950 60 0000 C CNN + 1 4500 4950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2200 3750 4050 3750 +Wire Wire Line + 2600 3750 2600 4050 +Wire Wire Line + 2600 4050 2850 4050 +Connection ~ 2600 3750 +Wire Wire Line + 2250 4800 4050 4800 +Wire Wire Line + 2600 4800 2600 5100 +Wire Wire Line + 2600 5100 2850 5100 +Connection ~ 2600 4800 +Wire Wire Line + 4050 3750 4050 4000 +Wire Wire Line + 3450 5100 3900 5100 +Wire Wire Line + 3900 5100 3900 4100 +Wire Wire Line + 3900 4100 4050 4100 +Wire Wire Line + 4050 4800 4050 4850 +Wire Wire Line + 3450 4050 3650 4050 +Wire Wire Line + 3650 4050 3650 4950 +Wire Wire Line + 3650 4950 4050 4950 +$Comp +L d_or U18 +U 1 1 6853B275 +P 5700 4500 +F 0 "U18" H 5700 4500 60 0000 C CNN +F 1 "d_or" H 5700 4600 60 0000 C CNN +F 2 "" H 5700 4500 60 0000 C CNN +F 3 "" H 5700 4500 60 0000 C CNN + 1 5700 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 6853B27B +P 6800 4450 +F 0 "U22" H 6800 4350 60 0000 C CNN +F 1 "d_inverter" H 6800 4600 60 0000 C CNN +F 2 "" H 6850 4400 60 0000 C CNN +F 3 "" H 6850 4400 60 0000 C CNN + 1 6800 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4950 4050 5250 4050 +Wire Wire Line + 5250 4050 5250 4400 +Wire Wire Line + 4950 4900 5250 4900 +Wire Wire Line + 5250 4900 5250 4500 +Wire Wire Line + 6150 4450 6500 4450 +Wire Wire Line + 7100 4450 7300 4450 +$Comp +L d_inverter U5 +U 1 1 6853B461 +P 3150 5950 +F 0 "U5" H 3150 5850 60 0000 C CNN +F 1 "d_inverter" H 3150 6100 60 0000 C CNN +F 2 "" H 3200 5900 60 0000 C CNN +F 3 "" H 3200 5900 60 0000 C CNN + 1 3150 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6853B467 +P 3150 7000 +F 0 "U6" H 3150 6900 60 0000 C CNN +F 1 "d_inverter" H 3150 7150 60 0000 C CNN +F 2 "" H 3200 6950 60 0000 C CNN +F 3 "" H 3200 6950 60 0000 C CNN + 1 3150 7000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 6853B46D +P 4500 6000 +F 0 "U13" H 4500 6000 60 0000 C CNN +F 1 "d_and" H 4550 6100 60 0000 C CNN +F 2 "" H 4500 6000 60 0000 C CNN +F 3 "" H 4500 6000 60 0000 C CNN + 1 4500 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 6853B473 +P 4500 6850 +F 0 "U14" H 4500 6850 60 0000 C CNN +F 1 "d_and" H 4550 6950 60 0000 C CNN +F 2 "" H 4500 6850 60 0000 C CNN +F 3 "" H 4500 6850 60 0000 C CNN + 1 4500 6850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2200 5650 4050 5650 +Wire Wire Line + 2600 5650 2600 5950 +Wire Wire Line + 2600 5950 2850 5950 +Connection ~ 2600 5650 +Wire Wire Line + 2250 6700 4050 6700 +Wire Wire Line + 2600 6700 2600 7000 +Wire Wire Line + 2600 7000 2850 7000 +Connection ~ 2600 6700 +Wire Wire Line + 4050 5650 4050 5900 +Wire Wire Line + 3450 7000 3900 7000 +Wire Wire Line + 3900 7000 3900 6000 +Wire Wire Line + 3900 6000 4050 6000 +Wire Wire Line + 4050 6700 4050 6750 +Wire Wire Line + 3450 5950 3650 5950 +Wire Wire Line + 3650 5950 3650 6850 +Wire Wire Line + 3650 6850 4050 6850 +$Comp +L d_or U19 +U 1 1 6853B489 +P 5700 6400 +F 0 "U19" H 5700 6400 60 0000 C CNN +F 1 "d_or" H 5700 6500 60 0000 C CNN +F 2 "" H 5700 6400 60 0000 C CNN +F 3 "" H 5700 6400 60 0000 C CNN + 1 5700 6400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 6853B48F +P 6800 6350 +F 0 "U23" H 6800 6250 60 0000 C CNN +F 1 "d_inverter" H 6800 6500 60 0000 C CNN +F 2 "" H 6850 6300 60 0000 C CNN +F 3 "" H 6850 6300 60 0000 C CNN + 1 6800 6350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4950 5950 5250 5950 +Wire Wire Line + 5250 5950 5250 6300 +Wire Wire Line + 4950 6800 5250 6800 +Wire Wire Line + 5250 6800 5250 6400 +Wire Wire Line + 6150 6350 6500 6350 +Wire Wire Line + 7100 6350 7300 6350 +$Comp +L d_inverter U7 +U 1 1 6853B5DF +P 3150 7850 +F 0 "U7" H 3150 7750 60 0000 C CNN +F 1 "d_inverter" H 3150 8000 60 0000 C CNN +F 2 "" H 3200 7800 60 0000 C CNN +F 3 "" H 3200 7800 60 0000 C CNN + 1 3150 7850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6853B5E5 +P 3150 8900 +F 0 "U8" H 3150 8800 60 0000 C CNN +F 1 "d_inverter" H 3150 9050 60 0000 C CNN +F 2 "" H 3200 8850 60 0000 C CNN +F 3 "" H 3200 8850 60 0000 C CNN + 1 3150 8900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U15 +U 1 1 6853B5EB +P 4500 7900 +F 0 "U15" H 4500 7900 60 0000 C CNN +F 1 "d_and" H 4550 8000 60 0000 C CNN +F 2 "" H 4500 7900 60 0000 C CNN +F 3 "" H 4500 7900 60 0000 C CNN + 1 4500 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 6853B5F1 +P 4500 8750 +F 0 "U16" H 4500 8750 60 0000 C CNN +F 1 "d_and" H 4550 8850 60 0000 C CNN +F 2 "" H 4500 8750 60 0000 C CNN +F 3 "" H 4500 8750 60 0000 C CNN + 1 4500 8750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2200 7550 4050 7550 +Wire Wire Line + 2600 7550 2600 7850 +Wire Wire Line + 2600 7850 2850 7850 +Connection ~ 2600 7550 +Wire Wire Line + 2250 8600 4050 8600 +Wire Wire Line + 2600 8600 2600 8900 +Wire Wire Line + 2600 8900 2850 8900 +Connection ~ 2600 8600 +Wire Wire Line + 4050 7550 4050 7800 +Wire Wire Line + 3450 8900 3900 8900 +Wire Wire Line + 3900 8900 3900 7900 +Wire Wire Line + 3900 7900 4050 7900 +Wire Wire Line + 4050 8600 4050 8650 +Wire Wire Line + 3450 7850 3650 7850 +Wire Wire Line + 3650 7850 3650 8750 +Wire Wire Line + 3650 8750 4050 8750 +$Comp +L d_or U20 +U 1 1 6853B607 +P 5700 8300 +F 0 "U20" H 5700 8300 60 0000 C CNN +F 1 "d_or" H 5700 8400 60 0000 C CNN +F 2 "" H 5700 8300 60 0000 C CNN +F 3 "" H 5700 8300 60 0000 C CNN + 1 5700 8300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U24 +U 1 1 6853B60D +P 6800 8250 +F 0 "U24" H 6800 8150 60 0000 C CNN +F 1 "d_inverter" H 6800 8400 60 0000 C CNN +F 2 "" H 6850 8200 60 0000 C CNN +F 3 "" H 6850 8200 60 0000 C CNN + 1 6800 8250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4950 7850 5250 7850 +Wire Wire Line + 5250 7850 5250 8200 +Wire Wire Line + 4950 8700 5250 8700 +Wire Wire Line + 5250 8700 5250 8300 +Wire Wire Line + 6150 8250 6500 8250 +Wire Wire Line + 7100 8250 7300 8250 +$Comp +L PORT U25 +U 1 1 6853B813 +P 1950 1750 +F 0 "U25" H 2000 1850 30 0000 C CNN +F 1 "PORT" H 1950 1750 30 0000 C CNN +F 2 "" H 1950 1750 60 0000 C CNN +F 3 "" H 1950 1750 60 0000 C CNN + 1 1950 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 2 1 6853B91D +P 2000 2800 +F 0 "U25" H 2050 2900 30 0000 C CNN +F 1 "PORT" H 2000 2800 30 0000 C CNN +F 2 "" H 2000 2800 60 0000 C CNN +F 3 "" H 2000 2800 60 0000 C CNN + 2 2000 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 3 1 6853B97C +P 7550 2450 +F 0 "U25" H 7600 2550 30 0000 C CNN +F 1 "PORT" H 7550 2450 30 0000 C CNN +F 2 "" H 7550 2450 60 0000 C CNN +F 3 "" H 7550 2450 60 0000 C CNN + 3 7550 2450 + -1 0 0 1 +$EndComp +$Comp +L PORT U25 +U 4 1 6853B9F7 +P 7550 4450 +F 0 "U25" H 7600 4550 30 0000 C CNN +F 1 "PORT" H 7550 4450 30 0000 C CNN +F 2 "" H 7550 4450 60 0000 C CNN +F 3 "" H 7550 4450 60 0000 C CNN + 4 7550 4450 + -1 0 0 1 +$EndComp +$Comp +L PORT U25 +U 5 1 6853BA80 +P 1950 3750 +F 0 "U25" H 2000 3850 30 0000 C CNN +F 1 "PORT" H 1950 3750 30 0000 C CNN +F 2 "" H 1950 3750 60 0000 C CNN +F 3 "" H 1950 3750 60 0000 C CNN + 5 1950 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 6 1 6853BB25 +P 2000 4800 +F 0 "U25" H 2050 4900 30 0000 C CNN +F 1 "PORT" H 2000 4800 30 0000 C CNN +F 2 "" H 2000 4800 60 0000 C CNN +F 3 "" H 2000 4800 60 0000 C CNN + 6 2000 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 7 1 6853BBB6 +P 7600 1500 +F 0 "U25" H 7650 1600 30 0000 C CNN +F 1 "PORT" H 7600 1500 30 0000 C CNN +F 2 "" H 7600 1500 60 0000 C CNN +F 3 "" H 7600 1500 60 0000 C CNN + 7 7600 1500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 14 1 6853BC59 +P 7600 1800 +F 0 "U25" H 7650 1900 30 0000 C CNN +F 1 "PORT" H 7600 1800 30 0000 C CNN +F 2 "" H 7600 1800 60 0000 C CNN +F 3 "" H 7600 1800 60 0000 C CNN + 14 7600 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 8 1 6853BCE6 +P 1950 5650 +F 0 "U25" H 2000 5750 30 0000 C CNN +F 1 "PORT" H 1950 5650 30 0000 C CNN +F 2 "" H 1950 5650 60 0000 C CNN +F 3 "" H 1950 5650 60 0000 C CNN + 8 1950 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 9 1 6853BD51 +P 2000 6700 +F 0 "U25" H 2050 6800 30 0000 C CNN +F 1 "PORT" H 2000 6700 30 0000 C CNN +F 2 "" H 2000 6700 60 0000 C CNN +F 3 "" H 2000 6700 60 0000 C CNN + 9 2000 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 10 1 6853BDD2 +P 7550 6350 +F 0 "U25" H 7600 6450 30 0000 C CNN +F 1 "PORT" H 7550 6350 30 0000 C CNN +F 2 "" H 7550 6350 60 0000 C CNN +F 3 "" H 7550 6350 60 0000 C CNN + 10 7550 6350 + -1 0 0 1 +$EndComp +$Comp +L PORT U25 +U 11 1 6853BE75 +P 7550 8250 +F 0 "U25" H 7600 8350 30 0000 C CNN +F 1 "PORT" H 7550 8250 30 0000 C CNN +F 2 "" H 7550 8250 60 0000 C CNN +F 3 "" H 7550 8250 60 0000 C CNN + 11 7550 8250 + -1 0 0 1 +$EndComp +$Comp +L PORT U25 +U 12 1 6853BF16 +P 1950 7550 +F 0 "U25" H 2000 7650 30 0000 C CNN +F 1 "PORT" H 1950 7550 30 0000 C CNN +F 2 "" H 1950 7550 60 0000 C CNN +F 3 "" H 1950 7550 60 0000 C CNN + 12 1950 7550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 13 1 6853BFAF +P 2000 8600 +F 0 "U25" H 2050 8700 30 0000 C CNN +F 1 "PORT" H 2000 8600 30 0000 C CNN +F 2 "" H 2000 8600 60 0000 C CNN +F 3 "" H 2000 8600 60 0000 C CNN + 13 2000 8600 + 1 0 0 -1 +$EndComp +NoConn ~ 7850 1500 +NoConn ~ 7850 1800 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.sub b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.sub new file mode 100644 index 000000000..95a862553 --- /dev/null +++ b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266.sub @@ -0,0 +1,102 @@ +* Subcircuit CD54HC7266 +.subckt CD54HC7266 net-_u1-pad1_ net-_u10-pad1_ net-_u21-pad2_ net-_u22-pad2_ net-_u11-pad1_ net-_u12-pad1_ ? net-_u13-pad1_ net-_u14-pad1_ net-_u23-pad2_ net-_u24-pad2_ net-_u15-pad1_ net-_u16-pad1_ ? +* c:\fossee\esim\library\subcircuitlibrary\cd54hc7266\cd54hc7266.cir +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u10-pad1_ net-_u2-pad2_ d_inverter +* u9 net-_u1-pad1_ net-_u2-pad2_ net-_u17-pad1_ d_and +* u10 net-_u10-pad1_ net-_u1-pad2_ net-_u10-pad3_ d_and +* u17 net-_u17-pad1_ net-_u10-pad3_ net-_u17-pad3_ d_or +* u21 net-_u17-pad3_ net-_u21-pad2_ d_inverter +* u3 net-_u11-pad1_ net-_u12-pad2_ d_inverter +* u4 net-_u12-pad1_ net-_u11-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u18-pad3_ d_or +* u22 net-_u18-pad3_ net-_u22-pad2_ d_inverter +* u5 net-_u13-pad1_ net-_u14-pad2_ d_inverter +* u6 net-_u14-pad1_ net-_u13-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and +* u19 net-_u13-pad3_ net-_u14-pad3_ net-_u19-pad3_ d_or +* u23 net-_u19-pad3_ net-_u23-pad2_ d_inverter +* u7 net-_u15-pad1_ net-_u16-pad2_ d_inverter +* u8 net-_u16-pad1_ net-_u15-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u20 net-_u15-pad3_ net-_u16-pad3_ net-_u20-pad3_ d_or +* u24 net-_u20-pad3_ net-_u24-pad2_ d_inverter +a1 net-_u1-pad1_ net-_u1-pad2_ u1 +a2 net-_u10-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u17-pad1_ u9 +a4 [net-_u10-pad1_ net-_u1-pad2_ ] net-_u10-pad3_ u10 +a5 [net-_u17-pad1_ net-_u10-pad3_ ] net-_u17-pad3_ u17 +a6 net-_u17-pad3_ net-_u21-pad2_ u21 +a7 net-_u11-pad1_ net-_u12-pad2_ u3 +a8 net-_u12-pad1_ net-_u11-pad2_ u4 +a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a10 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a11 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u18-pad3_ u18 +a12 net-_u18-pad3_ net-_u22-pad2_ u22 +a13 net-_u13-pad1_ net-_u14-pad2_ u5 +a14 net-_u14-pad1_ net-_u13-pad2_ u6 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a17 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u19-pad3_ u19 +a18 net-_u19-pad3_ net-_u23-pad2_ u23 +a19 net-_u15-pad1_ net-_u16-pad2_ u7 +a20 net-_u16-pad1_ net-_u15-pad2_ u8 +a21 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a22 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a23 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u20-pad3_ u20 +a24 net-_u20-pad3_ net-_u24-pad2_ u24 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD54HC7266 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54HC7266/CD54HC7266_Previous_Values.xml b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266_Previous_Values.xml new file mode 100644 index 000000000..960008d52 --- /dev/null +++ b/library/SubcircuitLibrary/CD54HC7266/CD54HC7266_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterd_andd_andd_ord_inverterd_inverterd_inverterd_andd_andd_ord_inverterd_inverterd_inverterd_andd_andd_ord_inverterd_inverterd_inverterd_andd_andd_ord_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54HC7266/analysis b/library/SubcircuitLibrary/CD54HC7266/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CD54HC7266/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74HC30/3_and-cache.lib b/library/SubcircuitLibrary/HD74HC30/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/HD74HC30/3_and.cir b/library/SubcircuitLibrary/HD74HC30/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/HD74HC30/3_and.cir.out b/library/SubcircuitLibrary/HD74HC30/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/HD74HC30/3_and.pro b/library/SubcircuitLibrary/HD74HC30/3_and.pro new file mode 100644 index 000000000..06813ca78 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/HD74HC30/3_and.sch b/library/SubcircuitLibrary/HD74HC30/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/HD74HC30/3_and.sub b/library/SubcircuitLibrary/HD74HC30/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74HC30/3_and_Previous_Values.xml b/library/SubcircuitLibrary/HD74HC30/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74HC30/4_and-cache.lib b/library/SubcircuitLibrary/HD74HC30/4_and-cache.lib new file mode 100644 index 000000000..60f1a83d4 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/HD74HC30/4_and-rescue.lib b/library/SubcircuitLibrary/HD74HC30/4_and-rescue.lib new file mode 100644 index 000000000..e38330518 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/HD74HC30/4_and.cir b/library/SubcircuitLibrary/HD74HC30/4_and.cir new file mode 100644 index 000000000..fdf2e1074 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/HD74HC30/4_and.cir.out b/library/SubcircuitLibrary/HD74HC30/4_and.cir.out new file mode 100644 index 000000000..f40e5bc62 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/HD74HC30/4_and.pro b/library/SubcircuitLibrary/HD74HC30/4_and.pro new file mode 100644 index 000000000..b13a0a825 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/HD74HC30/4_and.sch b/library/SubcircuitLibrary/HD74HC30/4_and.sch new file mode 100644 index 000000000..f5e8febdc --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/HD74HC30/4_and.sub b/library/SubcircuitLibrary/HD74HC30/4_and.sub new file mode 100644 index 000000000..8663f37e6 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74HC30/4_and_Previous_Values.xml b/library/SubcircuitLibrary/HD74HC30/4_and_Previous_Values.xml new file mode 100644 index 000000000..f2ba0130e --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74HC30/HD74HC30-cache.lib b/library/SubcircuitLibrary/HD74HC30/HD74HC30-cache.lib new file mode 100644 index 000000000..b6cadcfcc --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/HD74HC30-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/HD74HC30/HD74HC30.cir b/library/SubcircuitLibrary/HD74HC30/HD74HC30.cir new file mode 100644 index 000000000..8508c2c2c --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/HD74HC30.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\HD74HC30\HD74HC30.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/09/25 15:20:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U2-Pad1_ 4_and +X2 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U2-Pad2_ 4_and +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad8_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ ? ? Net-_U1-Pad11_ Net-_U1-Pad12_ ? ? PORT + +.end diff --git a/library/SubcircuitLibrary/HD74HC30/HD74HC30.cir.out b/library/SubcircuitLibrary/HD74HC30/HD74HC30.cir.out new file mode 100644 index 000000000..884224707 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/HD74HC30.cir.out @@ -0,0 +1,23 @@ +* c:\fossee\esim\library\subcircuitlibrary\hd74hc30\hd74hc30.cir + +.include 4_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad1_ 4_and +x2 net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad11_ net-_u1-pad12_ net-_u2-pad2_ 4_and +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad8_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ ? ? net-_u1-pad11_ net-_u1-pad12_ ? ? port +a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a2 net-_u2-pad3_ net-_u1-pad8_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/HD74HC30/HD74HC30.pro b/library/SubcircuitLibrary/HD74HC30/HD74HC30.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/HD74HC30.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/HD74HC30/HD74HC30.sch b/library/SubcircuitLibrary/HD74HC30/HD74HC30.sch new file mode 100644 index 000000000..85a8b7177 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/HD74HC30.sch @@ -0,0 +1,288 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:HD74HC30-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4900 2150 5550 2150 +Wire Wire Line + 5550 2150 5550 2600 +Wire Wire Line + 5550 3200 4900 3200 +Wire Wire Line + 5550 2700 5550 3200 +Wire Wire Line + 7200 2650 7650 2650 +Wire Wire Line + 3650 2000 4000 2000 +Wire Wire Line + 4000 2100 3650 2100 +Wire Wire Line + 4000 2200 3650 2200 +Wire Wire Line + 4000 2300 3650 2300 +Wire Wire Line + 4000 3050 3600 3050 +Wire Wire Line + 4000 3150 3600 3150 +Wire Wire Line + 4000 3250 3600 3250 +Wire Wire Line + 4000 3350 3600 3350 +$Comp +L 4_and X1 +U 1 1 6846B75D +P 4400 2150 +F 0 "X1" H 4450 2100 60 0000 C CNN +F 1 "4_and" H 4500 2250 60 0000 C CNN +F 2 "" H 4400 2150 60 0000 C CNN +F 3 "" H 4400 2150 60 0000 C CNN + 1 4400 2150 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 6846B8B9 +P 4400 3200 +F 0 "X2" H 4450 3150 60 0000 C CNN +F 1 "4_and" H 4500 3300 60 0000 C CNN +F 2 "" H 4400 3200 60 0000 C CNN +F 3 "" H 4400 3200 60 0000 C CNN + 1 4400 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 6846BDBC +P 6000 2700 +F 0 "U2" H 6000 2700 60 0000 C CNN +F 1 "d_and" H 6050 2800 60 0000 C CNN +F 2 "" H 6000 2700 60 0000 C CNN +F 3 "" H 6000 2700 60 0000 C CNN + 1 6000 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 6846AC41 +P 6900 2650 +F 0 "U3" H 6900 2550 60 0000 C CNN +F 1 "d_inverter" H 6900 2800 60 0000 C CNN +F 2 "" H 6950 2600 60 0000 C CNN +F 3 "" H 6950 2600 60 0000 C CNN + 1 6900 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 2650 6600 2650 +$Comp +L PORT U1 +U 1 1 6846CA03 +P 3400 2000 +F 0 "U1" H 3450 2100 30 0000 C CNN +F 1 "PORT" H 3400 2000 30 0000 C CNN +F 2 "" H 3400 2000 60 0000 C CNN +F 3 "" H 3400 2000 60 0000 C CNN + 1 3400 2000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6846CA36 +P 3400 2100 +F 0 "U1" H 3450 2200 30 0000 C CNN +F 1 "PORT" H 3400 2100 30 0000 C CNN +F 2 "" H 3400 2100 60 0000 C CNN +F 3 "" H 3400 2100 60 0000 C CNN + 2 3400 2100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6846CA67 +P 3400 2200 +F 0 "U1" H 3450 2300 30 0000 C CNN +F 1 "PORT" H 3400 2200 30 0000 C CNN +F 2 "" H 3400 2200 60 0000 C CNN +F 3 "" H 3400 2200 60 0000 C CNN + 3 3400 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6846CAA0 +P 3400 2300 +F 0 "U1" H 3450 2400 30 0000 C CNN +F 1 "PORT" H 3400 2300 30 0000 C CNN +F 2 "" H 3400 2300 60 0000 C CNN +F 3 "" H 3400 2300 60 0000 C CNN + 4 3400 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6846CAF3 +P 3350 3050 +F 0 "U1" H 3400 3150 30 0000 C CNN +F 1 "PORT" H 3350 3050 30 0000 C CNN +F 2 "" H 3350 3050 60 0000 C CNN +F 3 "" H 3350 3050 60 0000 C CNN + 5 3350 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6846CB64 +P 3350 3150 +F 0 "U1" H 3400 3250 30 0000 C CNN +F 1 "PORT" H 3350 3150 30 0000 C CNN +F 2 "" H 3350 3150 60 0000 C CNN +F 3 "" H 3350 3150 60 0000 C CNN + 6 3350 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6846CBCD +P 3050 1350 +F 0 "U1" H 3100 1450 30 0000 C CNN +F 1 "PORT" H 3050 1350 30 0000 C CNN +F 2 "" H 3050 1350 60 0000 C CNN +F 3 "" H 3050 1350 60 0000 C CNN + 7 3050 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6846CC0C +P 7900 2650 +F 0 "U1" H 7950 2750 30 0000 C CNN +F 1 "PORT" H 7900 2650 30 0000 C CNN +F 2 "" H 7900 2650 60 0000 C CNN +F 3 "" H 7900 2650 60 0000 C CNN + 8 7900 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 6846CC59 +P 2500 2200 +F 0 "U1" H 2550 2300 30 0000 C CNN +F 1 "PORT" H 2500 2200 30 0000 C CNN +F 2 "" H 2500 2200 60 0000 C CNN +F 3 "" H 2500 2200 60 0000 C CNN + 9 2500 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6846CC9A +P 2500 2550 +F 0 "U1" H 2550 2650 30 0000 C CNN +F 1 "PORT" H 2500 2550 30 0000 C CNN +F 2 "" H 2500 2550 60 0000 C CNN +F 3 "" H 2500 2550 60 0000 C CNN + 10 2500 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6846CCDB +P 2500 1950 +F 0 "U1" H 2550 2050 30 0000 C CNN +F 1 "PORT" H 2500 1950 30 0000 C CNN +F 2 "" H 2500 1950 60 0000 C CNN +F 3 "" H 2500 1950 60 0000 C CNN + 13 2500 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 6846CD3E +P 3050 1550 +F 0 "U1" H 3100 1650 30 0000 C CNN +F 1 "PORT" H 3050 1550 30 0000 C CNN +F 2 "" H 3050 1550 60 0000 C CNN +F 3 "" H 3050 1550 60 0000 C CNN + 14 3050 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6846CD81 +P 3350 3350 +F 0 "U1" H 3400 3450 30 0000 C CNN +F 1 "PORT" H 3350 3350 30 0000 C CNN +F 2 "" H 3350 3350 60 0000 C CNN +F 3 "" H 3350 3350 60 0000 C CNN + 12 3350 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6846CDD8 +P 3350 3250 +F 0 "U1" H 3400 3350 30 0000 C CNN +F 1 "PORT" H 3350 3250 30 0000 C CNN +F 2 "" H 3350 3250 60 0000 C CNN +F 3 "" H 3350 3250 60 0000 C CNN + 11 3350 3250 + 1 0 0 -1 +$EndComp +NoConn ~ 3300 1350 +NoConn ~ 3300 1550 +NoConn ~ 2750 1950 +NoConn ~ 2750 2200 +NoConn ~ 2750 2550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/HD74HC30/HD74HC30.sub b/library/SubcircuitLibrary/HD74HC30/HD74HC30.sub new file mode 100644 index 000000000..96ff2d159 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/HD74HC30.sub @@ -0,0 +1,17 @@ +* Subcircuit HD74HC30 +.subckt HD74HC30 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ ? ? net-_u1-pad11_ net-_u1-pad12_ ? ? +* c:\fossee\esim\library\subcircuitlibrary\hd74hc30\hd74hc30.cir +.include 4_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad1_ 4_and +x2 net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad11_ net-_u1-pad12_ net-_u2-pad2_ 4_and +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad8_ d_inverter +a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a2 net-_u2-pad3_ net-_u1-pad8_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends HD74HC30 \ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74HC30/HD74HC30_Previous_Values.xml b/library/SubcircuitLibrary/HD74HC30/HD74HC30_Previous_Values.xml new file mode 100644 index 000000000..650ffc797 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/HD74HC30_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74HC30/NMOS-180nm.lib b/library/SubcircuitLibrary/HD74HC30/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/HD74HC30/PMOS-180nm.lib b/library/SubcircuitLibrary/HD74HC30/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/HD74HC30/analysis b/library/SubcircuitLibrary/HD74HC30/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC30/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MM54C42/MM54C42-cache.lib b/library/SubcircuitLibrary/MM54C42/MM54C42-cache.lib new file mode 100644 index 000000000..889b42675 --- /dev/null +++ b/library/SubcircuitLibrary/MM54C42/MM54C42-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MM54C42/MM54C42.cir b/library/SubcircuitLibrary/MM54C42/MM54C42.cir new file mode 100644 index 000000000..47b37a3ce --- /dev/null +++ b/library/SubcircuitLibrary/MM54C42/MM54C42.cir @@ -0,0 +1,39 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\MM54C42\MM54C42.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/17/25 20:49:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U4 Net-_U39-Pad15_ Net-_U4-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U2 Net-_U11-Pad1_ Net-_U10-Pad1_ d_inverter +U3 Net-_U10-Pad2_ Net-_U11-Pad2_ d_inverter +U7 Net-_U39-Pad15_ Net-_U1-Pad2_ Net-_U12-Pad1_ d_and +U6 Net-_U4-Pad2_ Net-_U1-Pad1_ Net-_U17-Pad1_ d_and +U8 Net-_U1-Pad2_ Net-_U4-Pad2_ Net-_U13-Pad1_ d_and +U5 Net-_U39-Pad15_ Net-_U1-Pad1_ Net-_U18-Pad1_ d_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U9 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U14-Pad1_ d_and +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U15 Net-_U11-Pad3_ Net-_U15-Pad2_ d_inverter +U16 Net-_U10-Pad3_ Net-_U16-Pad2_ d_inverter +U19 Net-_U14-Pad2_ Net-_U13-Pad2_ Net-_U19-Pad3_ d_or +U20 Net-_U14-Pad2_ Net-_U12-Pad2_ Net-_U20-Pad3_ d_or +U21 Net-_U14-Pad2_ Net-_U17-Pad2_ Net-_U21-Pad3_ d_or +U22 Net-_U18-Pad2_ Net-_U14-Pad2_ Net-_U22-Pad3_ d_or +U23 Net-_U12-Pad2_ Net-_U15-Pad2_ Net-_U23-Pad3_ d_or +U24 Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U24-Pad3_ d_or +U27 Net-_U13-Pad2_ Net-_U16-Pad2_ Net-_U27-Pad3_ d_or +U28 Net-_U12-Pad2_ Net-_U16-Pad2_ Net-_U28-Pad3_ d_or +U25 Net-_U17-Pad2_ Net-_U15-Pad2_ Net-_U25-Pad3_ d_or +U26 Net-_U18-Pad2_ Net-_U15-Pad2_ Net-_U26-Pad3_ d_or +U39 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U25-Pad3_ ? Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U28-Pad3_ Net-_U10-Pad2_ Net-_U11-Pad1_ Net-_U1-Pad1_ Net-_U39-Pad15_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/MM54C42/MM54C42.cir.out b/library/SubcircuitLibrary/MM54C42/MM54C42.cir.out new file mode 100644 index 000000000..04f1a68cd --- /dev/null +++ b/library/SubcircuitLibrary/MM54C42/MM54C42.cir.out @@ -0,0 +1,124 @@ +* d:\fossee\esim\library\subcircuitlibrary\mm54c42\mm54c42.cir + +* u4 net-_u39-pad15_ net-_u4-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u11-pad1_ net-_u10-pad1_ d_inverter +* u3 net-_u10-pad2_ net-_u11-pad2_ d_inverter +* u7 net-_u39-pad15_ net-_u1-pad2_ net-_u12-pad1_ d_and +* u6 net-_u4-pad2_ net-_u1-pad1_ net-_u17-pad1_ d_and +* u8 net-_u1-pad2_ net-_u4-pad2_ net-_u13-pad1_ d_and +* u5 net-_u39-pad15_ net-_u1-pad1_ net-_u18-pad1_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u9 net-_u10-pad1_ net-_u11-pad2_ net-_u14-pad1_ d_and +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u15 net-_u11-pad3_ net-_u15-pad2_ d_inverter +* u16 net-_u10-pad3_ net-_u16-pad2_ d_inverter +* u19 net-_u14-pad2_ net-_u13-pad2_ net-_u19-pad3_ d_or +* u20 net-_u14-pad2_ net-_u12-pad2_ net-_u20-pad3_ d_or +* u21 net-_u14-pad2_ net-_u17-pad2_ net-_u21-pad3_ d_or +* u22 net-_u18-pad2_ net-_u14-pad2_ net-_u22-pad3_ d_or +* u23 net-_u12-pad2_ net-_u15-pad2_ net-_u23-pad3_ d_or +* u24 net-_u13-pad2_ net-_u15-pad2_ net-_u24-pad3_ d_or +* u27 net-_u13-pad2_ net-_u16-pad2_ net-_u27-pad3_ d_or +* u28 net-_u12-pad2_ net-_u16-pad2_ net-_u28-pad3_ d_or +* u25 net-_u17-pad2_ net-_u15-pad2_ net-_u25-pad3_ d_or +* u26 net-_u18-pad2_ net-_u15-pad2_ net-_u26-pad3_ d_or +* u39 net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ net-_u22-pad3_ net-_u23-pad3_ net-_u24-pad3_ net-_u25-pad3_ ? net-_u26-pad3_ net-_u27-pad3_ net-_u28-pad3_ net-_u10-pad2_ net-_u11-pad1_ net-_u1-pad1_ net-_u39-pad15_ ? port +a1 net-_u39-pad15_ net-_u4-pad2_ u4 +a2 net-_u1-pad1_ net-_u1-pad2_ u1 +a3 net-_u11-pad1_ net-_u10-pad1_ u2 +a4 net-_u10-pad2_ net-_u11-pad2_ u3 +a5 [net-_u39-pad15_ net-_u1-pad2_ ] net-_u12-pad1_ u7 +a6 [net-_u4-pad2_ net-_u1-pad1_ ] net-_u17-pad1_ u6 +a7 [net-_u1-pad2_ net-_u4-pad2_ ] net-_u13-pad1_ u8 +a8 [net-_u39-pad15_ net-_u1-pad1_ ] net-_u18-pad1_ u5 +a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a10 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a11 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u14-pad1_ u9 +a12 net-_u18-pad1_ net-_u18-pad2_ u18 +a13 net-_u12-pad1_ net-_u12-pad2_ u12 +a14 net-_u17-pad1_ net-_u17-pad2_ u17 +a15 net-_u13-pad1_ net-_u13-pad2_ u13 +a16 net-_u14-pad1_ net-_u14-pad2_ u14 +a17 net-_u11-pad3_ net-_u15-pad2_ u15 +a18 net-_u10-pad3_ net-_u16-pad2_ u16 +a19 [net-_u14-pad2_ net-_u13-pad2_ ] net-_u19-pad3_ u19 +a20 [net-_u14-pad2_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a21 [net-_u14-pad2_ net-_u17-pad2_ ] net-_u21-pad3_ u21 +a22 [net-_u18-pad2_ net-_u14-pad2_ ] net-_u22-pad3_ u22 +a23 [net-_u12-pad2_ net-_u15-pad2_ ] net-_u23-pad3_ u23 +a24 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u24-pad3_ u24 +a25 [net-_u13-pad2_ net-_u16-pad2_ ] net-_u27-pad3_ u27 +a26 [net-_u12-pad2_ net-_u16-pad2_ ] net-_u28-pad3_ u28 +a27 [net-_u17-pad2_ net-_u15-pad2_ ] net-_u25-pad3_ u25 +a28 [net-_u18-pad2_ net-_u15-pad2_ ] net-_u26-pad3_ u26 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u23 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u24 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u25 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u26 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MM54C42/MM54C42.pro b/library/SubcircuitLibrary/MM54C42/MM54C42.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/MM54C42/MM54C42.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MM54C42/MM54C42.sch b/library/SubcircuitLibrary/MM54C42/MM54C42.sch new file mode 100644 index 000000000..e721ae033 --- /dev/null +++ b/library/SubcircuitLibrary/MM54C42/MM54C42.sch @@ -0,0 +1,750 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:MM54C42-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U4 +U 1 1 685E72F6 +P 5250 3000 +F 0 "U4" H 5250 2900 60 0000 C CNN +F 1 "d_inverter" H 5250 3150 60 0000 C CNN +F 2 "" H 5300 2950 60 0000 C CNN +F 3 "" H 5300 2950 60 0000 C CNN + 1 5250 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U1 +U 1 1 685E73D1 +P 5100 5000 +F 0 "U1" H 5100 4900 60 0000 C CNN +F 1 "d_inverter" H 5100 5150 60 0000 C CNN +F 2 "" H 5150 4950 60 0000 C CNN +F 3 "" H 5150 4950 60 0000 C CNN + 1 5100 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 685E7425 +P 5100 6700 +F 0 "U2" H 5100 6600 60 0000 C CNN +F 1 "d_inverter" H 5100 6850 60 0000 C CNN +F 2 "" H 5150 6650 60 0000 C CNN +F 3 "" H 5150 6650 60 0000 C CNN + 1 5100 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 685E747C +P 5100 8250 +F 0 "U3" H 5100 8150 60 0000 C CNN +F 1 "d_inverter" H 5100 8400 60 0000 C CNN +F 2 "" H 5150 8200 60 0000 C CNN +F 3 "" H 5150 8200 60 0000 C CNN + 1 5100 8250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 685E75A8 +P 7350 4050 +F 0 "U7" H 7350 4050 60 0000 C CNN +F 1 "d_and" H 7400 4150 60 0000 C CNN +F 2 "" H 7350 4050 60 0000 C CNN +F 3 "" H 7350 4050 60 0000 C CNN + 1 7350 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 685E765A +P 7300 5150 +F 0 "U6" H 7300 5150 60 0000 C CNN +F 1 "d_and" H 7350 5250 60 0000 C CNN +F 2 "" H 7300 5150 60 0000 C CNN +F 3 "" H 7300 5150 60 0000 C CNN + 1 7300 5150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 685E76F0 +P 7350 6250 +F 0 "U8" H 7350 6250 60 0000 C CNN +F 1 "d_and" H 7400 6350 60 0000 C CNN +F 2 "" H 7350 6250 60 0000 C CNN +F 3 "" H 7350 6250 60 0000 C CNN + 1 7350 6250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 685E774D +P 7300 3300 +F 0 "U5" H 7300 3300 60 0000 C CNN +F 1 "d_and" H 7350 3400 60 0000 C CNN +F 2 "" H 7300 3300 60 0000 C CNN +F 3 "" H 7300 3300 60 0000 C CNN + 1 7300 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 685E78C5 +P 7450 7850 +F 0 "U11" H 7450 7850 60 0000 C CNN +F 1 "d_and" H 7500 7950 60 0000 C CNN +F 2 "" H 7450 7850 60 0000 C CNN +F 3 "" H 7450 7850 60 0000 C CNN + 1 7450 7850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 685E78CB +P 7350 8650 +F 0 "U10" H 7350 8650 60 0000 C CNN +F 1 "d_and" H 7400 8750 60 0000 C CNN +F 2 "" H 7350 8650 60 0000 C CNN +F 3 "" H 7350 8650 60 0000 C CNN + 1 7350 8650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 685E78D7 +P 7350 7100 +F 0 "U9" H 7350 7100 60 0000 C CNN +F 1 "d_and" H 7400 7200 60 0000 C CNN +F 2 "" H 7350 7100 60 0000 C CNN +F 3 "" H 7350 7100 60 0000 C CNN + 1 7350 7100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 685E792E +P 8600 3250 +F 0 "U18" H 8600 3150 60 0000 C CNN +F 1 "d_inverter" H 8600 3400 60 0000 C CNN +F 2 "" H 8650 3200 60 0000 C CNN +F 3 "" H 8650 3200 60 0000 C CNN + 1 8600 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 685E7A13 +P 8500 4000 +F 0 "U12" H 8500 3900 60 0000 C CNN +F 1 "d_inverter" H 8500 4150 60 0000 C CNN +F 2 "" H 8550 3950 60 0000 C CNN +F 3 "" H 8550 3950 60 0000 C CNN + 1 8500 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 685E7B29 +P 8550 5100 +F 0 "U17" H 8550 5000 60 0000 C CNN +F 1 "d_inverter" H 8550 5250 60 0000 C CNN +F 2 "" H 8600 5050 60 0000 C CNN +F 3 "" H 8600 5050 60 0000 C CNN + 1 8550 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 685E7B2F +P 8500 6200 +F 0 "U13" H 8500 6100 60 0000 C CNN +F 1 "d_inverter" H 8500 6350 60 0000 C CNN +F 2 "" H 8550 6150 60 0000 C CNN +F 3 "" H 8550 6150 60 0000 C CNN + 1 8500 6200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 685E7DEF +P 8500 7050 +F 0 "U14" H 8500 6950 60 0000 C CNN +F 1 "d_inverter" H 8500 7200 60 0000 C CNN +F 2 "" H 8550 7000 60 0000 C CNN +F 3 "" H 8550 7000 60 0000 C CNN + 1 8500 7050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 685E7DF5 +P 8500 7800 +F 0 "U15" H 8500 7700 60 0000 C CNN +F 1 "d_inverter" H 8500 7950 60 0000 C CNN +F 2 "" H 8550 7750 60 0000 C CNN +F 3 "" H 8550 7750 60 0000 C CNN + 1 8500 7800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 685E7DFB +P 8500 8600 +F 0 "U16" H 8500 8500 60 0000 C CNN +F 1 "d_inverter" H 8500 8750 60 0000 C CNN +F 2 "" H 8550 8550 60 0000 C CNN +F 3 "" H 8550 8550 60 0000 C CNN + 1 8500 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_or U19 +U 1 1 685E971A +P 11650 2950 +F 0 "U19" H 11650 2950 60 0000 C CNN +F 1 "d_or" H 11650 3050 60 0000 C CNN +F 2 "" H 11650 2950 60 0000 C CNN +F 3 "" H 11650 2950 60 0000 C CNN + 1 11650 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U20 +U 1 1 685E983E +P 11650 3500 +F 0 "U20" H 11650 3500 60 0000 C CNN +F 1 "d_or" H 11650 3600 60 0000 C CNN +F 2 "" H 11650 3500 60 0000 C CNN +F 3 "" H 11650 3500 60 0000 C CNN + 1 11650 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U21 +U 1 1 685E991A +P 11700 4200 +F 0 "U21" H 11700 4200 60 0000 C CNN +F 1 "d_or" H 11700 4300 60 0000 C CNN +F 2 "" H 11700 4200 60 0000 C CNN +F 3 "" H 11700 4200 60 0000 C CNN + 1 11700 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U22 +U 1 1 685E9920 +P 11700 4750 +F 0 "U22" H 11700 4750 60 0000 C CNN +F 1 "d_or" H 11700 4850 60 0000 C CNN +F 2 "" H 11700 4750 60 0000 C CNN +F 3 "" H 11700 4750 60 0000 C CNN + 1 11700 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_or U23 +U 1 1 685E9ACE +P 11750 5250 +F 0 "U23" H 11750 5250 60 0000 C CNN +F 1 "d_or" H 11750 5350 60 0000 C CNN +F 2 "" H 11750 5250 60 0000 C CNN +F 3 "" H 11750 5250 60 0000 C CNN + 1 11750 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_or U24 +U 1 1 685E9AD4 +P 11750 5800 +F 0 "U24" H 11750 5800 60 0000 C CNN +F 1 "d_or" H 11750 5900 60 0000 C CNN +F 2 "" H 11750 5800 60 0000 C CNN +F 3 "" H 11750 5800 60 0000 C CNN + 1 11750 5800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U27 +U 1 1 685E9ADA +P 11850 7750 +F 0 "U27" H 11850 7750 60 0000 C CNN +F 1 "d_or" H 11850 7850 60 0000 C CNN +F 2 "" H 11850 7750 60 0000 C CNN +F 3 "" H 11850 7750 60 0000 C CNN + 1 11850 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_or U28 +U 1 1 685E9AE0 +P 11850 8300 +F 0 "U28" H 11850 8300 60 0000 C CNN +F 1 "d_or" H 11850 8400 60 0000 C CNN +F 2 "" H 11850 8300 60 0000 C CNN +F 3 "" H 11850 8300 60 0000 C CNN + 1 11850 8300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U25 +U 1 1 685E9C2A +P 11850 6450 +F 0 "U25" H 11850 6450 60 0000 C CNN +F 1 "d_or" H 11850 6550 60 0000 C CNN +F 2 "" H 11850 6450 60 0000 C CNN +F 3 "" H 11850 6450 60 0000 C CNN + 1 11850 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U26 +U 1 1 685E9C30 +P 11850 7000 +F 0 "U26" H 11850 7000 60 0000 C CNN +F 1 "d_or" H 11850 7100 60 0000 C CNN +F 2 "" H 11850 7000 60 0000 C CNN +F 3 "" H 11850 7000 60 0000 C CNN + 1 11850 7000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 3000 4950 3000 +Wire Wire Line + 4300 3000 4300 3700 +Wire Wire Line + 4300 3700 5850 3700 +Connection ~ 4300 3000 +Wire Wire Line + 3850 5000 4800 5000 +Wire Wire Line + 4300 5000 4300 5600 +Wire Wire Line + 4300 5600 6550 5600 +Connection ~ 4300 5000 +Wire Wire Line + 3600 6700 4800 6700 +Wire Wire Line + 4300 6700 4300 7300 +Wire Wire Line + 4300 7300 5750 7300 +Connection ~ 4300 6700 +Wire Wire Line + 3500 8250 4800 8250 +Wire Wire Line + 4200 8250 4200 8850 +Wire Wire Line + 4200 8850 6450 8850 +Connection ~ 4200 8250 +Wire Wire Line + 5850 3200 5850 3950 +Wire Wire Line + 5850 3200 6850 3200 +Wire Wire Line + 5550 3000 6300 3000 +Wire Wire Line + 6300 3000 6300 6250 +Wire Wire Line + 6300 5050 6850 5050 +Wire Wire Line + 6300 6250 6900 6250 +Connection ~ 6300 5050 +Wire Wire Line + 5850 3950 6900 3950 +Connection ~ 5850 3700 +Wire Wire Line + 5400 5000 5900 5000 +Wire Wire Line + 5900 4050 5900 6150 +Wire Wire Line + 5900 4050 6900 4050 +Wire Wire Line + 5900 6150 6900 6150 +Connection ~ 5900 5000 +Wire Wire Line + 6550 5600 6550 3300 +Wire Wire Line + 6550 5150 6850 5150 +Wire Wire Line + 6550 3300 6850 3300 +Connection ~ 6550 5150 +Wire Wire Line + 5400 6700 6400 6700 +Wire Wire Line + 6400 6700 6400 8550 +Wire Wire Line + 6400 8550 6900 8550 +Wire Wire Line + 6900 7000 6400 7000 +Connection ~ 6400 7000 +Wire Wire Line + 5750 7300 5750 7750 +Wire Wire Line + 5750 7750 7000 7750 +Wire Wire Line + 5400 8250 5750 8250 +Wire Wire Line + 5750 8250 5750 7850 +Wire Wire Line + 5750 7850 7000 7850 +Wire Wire Line + 6450 8850 6450 8650 +Wire Wire Line + 6450 8650 6900 8650 +Wire Wire Line + 7750 3250 8300 3250 +Wire Wire Line + 7800 4000 8200 4000 +Wire Wire Line + 8900 3250 10050 3250 +Wire Wire Line + 8800 4000 10450 4000 +Wire Wire Line + 7750 5100 8250 5100 +Wire Wire Line + 8850 5100 9350 5100 +Wire Wire Line + 7800 6200 8200 6200 +Wire Wire Line + 8800 6200 11200 6200 +Wire Wire Line + 7800 7050 8200 7050 +Wire Wire Line + 6600 7850 6600 7100 +Wire Wire Line + 6600 7100 6900 7100 +Connection ~ 6600 7850 +Wire Wire Line + 9800 7050 8800 7050 +Wire Wire Line + 7900 7800 8200 7800 +Wire Wire Line + 10200 7800 8800 7800 +Wire Wire Line + 7800 8600 8200 8600 +Wire Wire Line + 8800 8600 10450 8600 +Wire Wire Line + 10050 3250 10050 6900 +Wire Wire Line + 10050 4650 11250 4650 +Wire Wire Line + 10050 6900 11400 6900 +Connection ~ 10050 4650 +Wire Wire Line + 10450 3500 10450 8200 +Wire Wire Line + 10450 3500 11200 3500 +Wire Wire Line + 10450 5150 11300 5150 +Connection ~ 10450 4000 +Wire Wire Line + 10450 8200 11400 8200 +Connection ~ 10450 5150 +Wire Wire Line + 10450 8600 10450 8300 +Wire Wire Line + 10450 8300 11400 8300 +Wire Wire Line + 11150 8300 11150 7750 +Wire Wire Line + 11150 7750 11400 7750 +Connection ~ 11150 8300 +Wire Wire Line + 10200 5250 10200 7800 +Wire Wire Line + 10200 7000 11400 7000 +Wire Wire Line + 10200 6450 11400 6450 +Connection ~ 10200 7000 +Wire Wire Line + 10200 5800 11300 5800 +Connection ~ 10200 6450 +Wire Wire Line + 10200 5250 11300 5250 +Connection ~ 10200 5800 +Wire Wire Line + 9800 2850 9800 7050 +Wire Wire Line + 9800 4750 11250 4750 +Wire Wire Line + 9800 4100 11250 4100 +Connection ~ 9800 4750 +Wire Wire Line + 9800 3400 11200 3400 +Connection ~ 9800 4100 +Wire Wire Line + 9800 2850 11200 2850 +Connection ~ 9800 3400 +Wire Wire Line + 11200 2950 11200 7650 +Wire Wire Line + 11200 7650 11400 7650 +Wire Wire Line + 11200 5700 11300 5700 +Connection ~ 11200 6200 +Connection ~ 11200 5700 +Wire Wire Line + 9350 4200 9350 6350 +Wire Wire Line + 9350 4200 11250 4200 +Wire Wire Line + 9350 6350 11400 6350 +Connection ~ 9350 5100 +Wire Wire Line + 12100 2900 13700 2900 +Wire Wire Line + 12100 3450 13700 3450 +Wire Wire Line + 12150 4150 13700 4150 +Wire Wire Line + 12150 4700 12650 4700 +Wire Wire Line + 12650 4700 12650 4650 +Wire Wire Line + 12200 5200 13700 5200 +Wire Wire Line + 12200 5750 13750 5750 +Wire Wire Line + 12300 6400 13800 6400 +Wire Wire Line + 12300 6950 13750 6950 +Wire Wire Line + 12300 7700 13850 7700 +Wire Wire Line + 12300 8250 13800 8250 +Wire Wire Line + 12650 4650 13700 4650 +$Comp +L PORT U39 +U 1 1 686CE65F +P 13950 2900 +F 0 "U39" H 14000 3000 30 0000 C CNN +F 1 "PORT" H 13950 2900 30 0000 C CNN +F 2 "" H 13950 2900 60 0000 C CNN +F 3 "" H 13950 2900 60 0000 C CNN + 1 13950 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U39 +U 2 1 686CE7D5 +P 13950 3450 +F 0 "U39" H 14000 3550 30 0000 C CNN +F 1 "PORT" H 13950 3450 30 0000 C CNN +F 2 "" H 13950 3450 60 0000 C CNN +F 3 "" H 13950 3450 60 0000 C CNN + 2 13950 3450 + -1 0 0 1 +$EndComp +$Comp +L PORT U39 +U 3 1 686CE842 +P 13950 4150 +F 0 "U39" H 14000 4250 30 0000 C CNN +F 1 "PORT" H 13950 4150 30 0000 C CNN +F 2 "" H 13950 4150 60 0000 C CNN +F 3 "" H 13950 4150 60 0000 C CNN + 3 13950 4150 + -1 0 0 1 +$EndComp +$Comp +L PORT U39 +U 4 1 686CE8CF +P 13950 4650 +F 0 "U39" H 14000 4750 30 0000 C CNN +F 1 "PORT" H 13950 4650 30 0000 C CNN +F 2 "" H 13950 4650 60 0000 C CNN +F 3 "" H 13950 4650 60 0000 C CNN + 4 13950 4650 + -1 0 0 1 +$EndComp +$Comp +L PORT U39 +U 5 1 686CE968 +P 13950 5200 +F 0 "U39" H 14000 5300 30 0000 C CNN +F 1 "PORT" H 13950 5200 30 0000 C CNN +F 2 "" H 13950 5200 60 0000 C CNN +F 3 "" H 13950 5200 60 0000 C CNN + 5 13950 5200 + -1 0 0 1 +$EndComp +$Comp +L PORT U39 +U 7 1 686CEA07 +P 14050 6400 +F 0 "U39" H 14100 6500 30 0000 C CNN +F 1 "PORT" H 14050 6400 30 0000 C CNN +F 2 "" H 14050 6400 60 0000 C CNN +F 3 "" H 14050 6400 60 0000 C CNN + 7 14050 6400 + -1 0 0 1 +$EndComp +$Comp +L PORT U39 +U 6 1 686CEA9C +P 14000 5750 +F 0 "U39" H 14050 5850 30 0000 C CNN +F 1 "PORT" H 14000 5750 30 0000 C CNN +F 2 "" H 14000 5750 60 0000 C CNN +F 3 "" H 14000 5750 60 0000 C CNN + 6 14000 5750 + -1 0 0 1 +$EndComp +$Comp +L PORT U39 +U 8 1 686CEB2D +P 15700 6050 +F 0 "U39" H 15750 6150 30 0000 C CNN +F 1 "PORT" H 15700 6050 30 0000 C CNN +F 2 "" H 15700 6050 60 0000 C CNN +F 3 "" H 15700 6050 60 0000 C CNN + 8 15700 6050 + -1 0 0 1 +$EndComp +$Comp +L PORT U39 +U 10 1 686CEBCC +P 14100 7700 +F 0 "U39" H 14150 7800 30 0000 C CNN +F 1 "PORT" H 14100 7700 30 0000 C CNN +F 2 "" H 14100 7700 60 0000 C CNN +F 3 "" H 14100 7700 60 0000 C CNN + 10 14100 7700 + -1 0 0 1 +$EndComp +$Comp +L PORT U39 +U 9 1 686CEC77 +P 14000 6950 +F 0 "U39" H 14050 7050 30 0000 C CNN +F 1 "PORT" H 14000 6950 30 0000 C CNN +F 2 "" H 14000 6950 60 0000 C CNN +F 3 "" H 14000 6950 60 0000 C CNN + 9 14000 6950 + -1 0 0 1 +$EndComp +$Comp +L PORT U39 +U 11 1 686CED28 +P 14050 8250 +F 0 "U39" H 14100 8350 30 0000 C CNN +F 1 "PORT" H 14050 8250 30 0000 C CNN +F 2 "" H 14050 8250 60 0000 C CNN +F 3 "" H 14050 8250 60 0000 C CNN + 11 14050 8250 + -1 0 0 1 +$EndComp +$Comp +L PORT U39 +U 12 1 686CEDCF +P 3250 8250 +F 0 "U39" H 3300 8350 30 0000 C CNN +F 1 "PORT" H 3250 8250 30 0000 C CNN +F 2 "" H 3250 8250 60 0000 C CNN +F 3 "" H 3250 8250 60 0000 C CNN + 12 3250 8250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U39 +U 13 1 686CEE70 +P 3350 6700 +F 0 "U39" H 3400 6800 30 0000 C CNN +F 1 "PORT" H 3350 6700 30 0000 C CNN +F 2 "" H 3350 6700 60 0000 C CNN +F 3 "" H 3350 6700 60 0000 C CNN + 13 3350 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U39 +U 14 1 686D43A4 +P 3600 5000 +F 0 "U39" H 3650 5100 30 0000 C CNN +F 1 "PORT" H 3600 5000 30 0000 C CNN +F 2 "" H 3600 5000 60 0000 C CNN +F 3 "" H 3600 5000 60 0000 C CNN + 14 3600 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U39 +U 15 1 6879353F +P 3350 3000 +F 0 "U39" H 3400 3100 30 0000 C CNN +F 1 "PORT" H 3350 3000 30 0000 C CNN +F 2 "" H 3350 3000 60 0000 C CNN +F 3 "" H 3350 3000 60 0000 C CNN + 15 3350 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U39 +U 16 1 687935CA +P 15600 6500 +F 0 "U39" H 15650 6600 30 0000 C CNN +F 1 "PORT" H 15600 6500 30 0000 C CNN +F 2 "" H 15600 6500 60 0000 C CNN +F 3 "" H 15600 6500 60 0000 C CNN + 16 15600 6500 + 1 0 0 -1 +$EndComp +NoConn ~ 15850 6500 +NoConn ~ 15450 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MM54C42/MM54C42.sub b/library/SubcircuitLibrary/MM54C42/MM54C42.sub new file mode 100644 index 000000000..645eda91a --- /dev/null +++ b/library/SubcircuitLibrary/MM54C42/MM54C42.sub @@ -0,0 +1,118 @@ +* Subcircuit MM54C42 +.subckt MM54C42 net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ net-_u22-pad3_ net-_u23-pad3_ net-_u24-pad3_ net-_u25-pad3_ ? net-_u26-pad3_ net-_u27-pad3_ net-_u28-pad3_ net-_u10-pad2_ net-_u11-pad1_ net-_u1-pad1_ net-_u39-pad15_ ? +* d:\fossee\esim\library\subcircuitlibrary\mm54c42\mm54c42.cir +* u4 net-_u39-pad15_ net-_u4-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u11-pad1_ net-_u10-pad1_ d_inverter +* u3 net-_u10-pad2_ net-_u11-pad2_ d_inverter +* u7 net-_u39-pad15_ net-_u1-pad2_ net-_u12-pad1_ d_and +* u6 net-_u4-pad2_ net-_u1-pad1_ net-_u17-pad1_ d_and +* u8 net-_u1-pad2_ net-_u4-pad2_ net-_u13-pad1_ d_and +* u5 net-_u39-pad15_ net-_u1-pad1_ net-_u18-pad1_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u9 net-_u10-pad1_ net-_u11-pad2_ net-_u14-pad1_ d_and +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u15 net-_u11-pad3_ net-_u15-pad2_ d_inverter +* u16 net-_u10-pad3_ net-_u16-pad2_ d_inverter +* u19 net-_u14-pad2_ net-_u13-pad2_ net-_u19-pad3_ d_or +* u20 net-_u14-pad2_ net-_u12-pad2_ net-_u20-pad3_ d_or +* u21 net-_u14-pad2_ net-_u17-pad2_ net-_u21-pad3_ d_or +* u22 net-_u18-pad2_ net-_u14-pad2_ net-_u22-pad3_ d_or +* u23 net-_u12-pad2_ net-_u15-pad2_ net-_u23-pad3_ d_or +* u24 net-_u13-pad2_ net-_u15-pad2_ net-_u24-pad3_ d_or +* u27 net-_u13-pad2_ net-_u16-pad2_ net-_u27-pad3_ d_or +* u28 net-_u12-pad2_ net-_u16-pad2_ net-_u28-pad3_ d_or +* u25 net-_u17-pad2_ net-_u15-pad2_ net-_u25-pad3_ d_or +* u26 net-_u18-pad2_ net-_u15-pad2_ net-_u26-pad3_ d_or +a1 net-_u39-pad15_ net-_u4-pad2_ u4 +a2 net-_u1-pad1_ net-_u1-pad2_ u1 +a3 net-_u11-pad1_ net-_u10-pad1_ u2 +a4 net-_u10-pad2_ net-_u11-pad2_ u3 +a5 [net-_u39-pad15_ net-_u1-pad2_ ] net-_u12-pad1_ u7 +a6 [net-_u4-pad2_ net-_u1-pad1_ ] net-_u17-pad1_ u6 +a7 [net-_u1-pad2_ net-_u4-pad2_ ] net-_u13-pad1_ u8 +a8 [net-_u39-pad15_ net-_u1-pad1_ ] net-_u18-pad1_ u5 +a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a10 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a11 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u14-pad1_ u9 +a12 net-_u18-pad1_ net-_u18-pad2_ u18 +a13 net-_u12-pad1_ net-_u12-pad2_ u12 +a14 net-_u17-pad1_ net-_u17-pad2_ u17 +a15 net-_u13-pad1_ net-_u13-pad2_ u13 +a16 net-_u14-pad1_ net-_u14-pad2_ u14 +a17 net-_u11-pad3_ net-_u15-pad2_ u15 +a18 net-_u10-pad3_ net-_u16-pad2_ u16 +a19 [net-_u14-pad2_ net-_u13-pad2_ ] net-_u19-pad3_ u19 +a20 [net-_u14-pad2_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a21 [net-_u14-pad2_ net-_u17-pad2_ ] net-_u21-pad3_ u21 +a22 [net-_u18-pad2_ net-_u14-pad2_ ] net-_u22-pad3_ u22 +a23 [net-_u12-pad2_ net-_u15-pad2_ ] net-_u23-pad3_ u23 +a24 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u24-pad3_ u24 +a25 [net-_u13-pad2_ net-_u16-pad2_ ] net-_u27-pad3_ u27 +a26 [net-_u12-pad2_ net-_u16-pad2_ ] net-_u28-pad3_ u28 +a27 [net-_u17-pad2_ net-_u15-pad2_ ] net-_u25-pad3_ u25 +a28 [net-_u18-pad2_ net-_u15-pad2_ ] net-_u26-pad3_ u26 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u23 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u24 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u25 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u26 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends MM54C42 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MM54C42/MM54C42_Previous_Values.xml b/library/SubcircuitLibrary/MM54C42/MM54C42_Previous_Values.xml new file mode 100644 index 000000000..94bda11ff --- /dev/null +++ b/library/SubcircuitLibrary/MM54C42/MM54C42_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_inverterd_inverterd_inverterd_andd_andd_andd_andd_andd_andd_andd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_ord_ord_ord_ord_ord_ord_ord_ord_ord_ord_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/MM54C42/analysis b/library/SubcircuitLibrary/MM54C42/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/MM54C42/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/NPN.lib b/library/SubcircuitLibrary/SLOA024B_HighPass/NPN.lib new file mode 100644 index 000000000..6509fe7ab --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/PNP.lib b/library/SubcircuitLibrary/SLOA024B_HighPass/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass-cache.lib b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass-cache.lib new file mode 100644 index 000000000..56a34eac5 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass-cache.lib @@ -0,0 +1,115 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.cir b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.cir new file mode 100644 index 000000000..caac11928 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.cir @@ -0,0 +1,16 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SLOA024B_HighPass\SLOA024B_HighPass.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 14:28:26 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10n +C2 Net-_C2-Pad1_ Net-_C1-Pad1_ 10n +R1 Net-_C1-Pad1_ Net-_R1-Pad2_ 11k +X1 ? Net-_C2-Pad1_ Net-_R1-Pad2_ Net-_U1-Pad3_ ? Net-_R1-Pad2_ Net-_U1-Pad2_ ? lm_741 +R2 Net-_C2-Pad1_ GND 22k +U1 Net-_C1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_R1-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.cir.out b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.cir.out new file mode 100644 index 000000000..f679f1135 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.cir.out @@ -0,0 +1,18 @@ +* c:\fossee\esim\library\subcircuitlibrary\sloa024b_highpass\sloa024b_highpass.cir + +.include lm_741.sub +c1 net-_c1-pad1_ net-_c1-pad2_ 10n +c2 net-_c2-pad1_ net-_c1-pad1_ 10n +r1 net-_c1-pad1_ net-_r1-pad2_ 11k +x1 ? net-_c2-pad1_ net-_r1-pad2_ net-_u1-pad3_ ? net-_r1-pad2_ net-_u1-pad2_ ? lm_741 +r2 net-_c2-pad1_ gnd 22k +* u1 net-_c1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_r1-pad2_ port +.ac dec 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.pro b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.sch b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.sch new file mode 100644 index 000000000..1a04473a6 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.sch @@ -0,0 +1,201 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SLOA024B_HighPass-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L capacitor C1 +U 1 1 685A603D +P 3100 2900 +F 0 "C1" H 3125 3000 50 0000 L CNN +F 1 "10n" H 3125 2800 50 0000 L CNN +F 2 "" H 3138 2750 30 0000 C CNN +F 3 "" H 3100 2900 60 0000 C CNN + 1 3100 2900 + 0 1 1 0 +$EndComp +$Comp +L capacitor C2 +U 1 1 685A608F +P 3650 2900 +F 0 "C2" H 3675 3000 50 0000 L CNN +F 1 "10n" H 3675 2800 50 0000 L CNN +F 2 "" H 3688 2750 30 0000 C CNN +F 3 "" H 3650 2900 60 0000 C CNN + 1 3650 2900 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 685A60BB +P 3950 2300 +F 0 "R1" H 4000 2430 50 0000 C CNN +F 1 "11k" H 4000 2250 50 0000 C CNN +F 2 "" H 4000 2280 30 0000 C CNN +F 3 "" V 4000 2350 30 0000 C CNN + 1 3950 2300 + 1 0 0 -1 +$EndComp +$Comp +L lm_741 X1 +U 1 1 685A613C +P 5000 3050 +F 0 "X1" H 4800 3050 60 0000 C CNN +F 1 "lm_741" H 4900 2800 60 0000 C CNN +F 2 "" H 5000 3050 60 0000 C CNN +F 3 "" H 5000 3050 60 0000 C CNN + 1 5000 3050 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 685A61B5 +P 4050 3650 +F 0 "R2" H 4100 3780 50 0000 C CNN +F 1 "22k" H 4100 3600 50 0000 C CNN +F 2 "" H 4100 3630 30 0000 C CNN +F 3 "" V 4100 3700 30 0000 C CNN + 1 4050 3650 + 0 1 1 0 +$EndComp +Wire Wire Line + 2700 2900 2950 2900 +Wire Wire Line + 3250 2900 3500 2900 +Wire Wire Line + 3800 2900 4450 2900 +Wire Wire Line + 3850 2250 3350 2250 +Wire Wire Line + 3350 2250 3350 2900 +Connection ~ 3350 2900 +Wire Wire Line + 4150 2250 5800 2250 +Wire Wire Line + 5800 2250 5800 3050 +Wire Wire Line + 5550 3050 6450 3050 +Connection ~ 5800 3050 +Wire Wire Line + 4100 3550 4100 2900 +Connection ~ 4100 2900 +Wire Wire Line + 4100 3850 4100 4050 +Wire Wire Line + 4450 3150 4400 3150 +Wire Wire Line + 4400 3150 4400 3700 +Wire Wire Line + 4400 3700 5650 3700 +Wire Wire Line + 5650 3700 5650 3050 +Connection ~ 5650 3050 +$Comp +L GND #PWR01 +U 1 1 685A6333 +P 4100 4050 +F 0 "#PWR01" H 4100 3800 50 0001 C CNN +F 1 "GND" H 4100 3900 50 0000 C CNN +F 2 "" H 4100 4050 50 0001 C CNN +F 3 "" H 4100 4050 50 0001 C CNN + 1 4100 4050 + 1 0 0 -1 +$EndComp +NoConn ~ 4950 2650 +NoConn ~ 5050 2700 +$Comp +L PORT U1 +U 1 1 685A6406 +P 2450 2900 +F 0 "U1" H 2500 3000 30 0000 C CNN +F 1 "PORT" H 2450 2900 30 0000 C CNN +F 2 "" H 2450 2900 60 0000 C CNN +F 3 "" H 2450 2900 60 0000 C CNN + 1 2450 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685A6463 +P 4850 2350 +F 0 "U1" H 4900 2450 30 0000 C CNN +F 1 "PORT" H 4850 2350 30 0000 C CNN +F 2 "" H 4850 2350 60 0000 C CNN +F 3 "" H 4850 2350 60 0000 C CNN + 2 4850 2350 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 685A649C +P 4850 3750 +F 0 "U1" H 4900 3850 30 0000 C CNN +F 1 "PORT" H 4850 3750 30 0000 C CNN +F 2 "" H 4850 3750 60 0000 C CNN +F 3 "" H 4850 3750 60 0000 C CNN + 3 4850 3750 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 685A64F1 +P 6700 3050 +F 0 "U1" H 6750 3150 30 0000 C CNN +F 1 "PORT" H 6700 3050 30 0000 C CNN +F 2 "" H 6700 3050 60 0000 C CNN +F 3 "" H 6700 3050 60 0000 C CNN + 4 6700 3050 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.sub b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.sub new file mode 100644 index 000000000..a3c9c0088 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass.sub @@ -0,0 +1,12 @@ +* Subcircuit SLOA024B_HighPass +.subckt SLOA024B_HighPass net-_c1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_r1-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\sloa024b_highpass\sloa024b_highpass.cir +.include lm_741.sub +c1 net-_c1-pad1_ net-_c1-pad2_ 10n +c2 net-_c2-pad1_ net-_c1-pad1_ 10n +r1 net-_c1-pad1_ net-_r1-pad2_ 11k +x1 ? net-_c2-pad1_ net-_r1-pad2_ net-_u1-pad3_ ? net-_r1-pad2_ net-_u1-pad2_ ? lm_741 +r2 net-_c2-pad1_ gnd 22k +* Control Statements + +.ends SLOA024B_HighPass \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass_Previous_Values.xml b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass_Previous_Values.xml new file mode 100644 index 000000000..f82fcb55c --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/SLOA024B_HighPass_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741falsetruefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/analysis b/library/SubcircuitLibrary/SLOA024B_HighPass/analysis new file mode 100644 index 000000000..f8c1b52a5 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/analysis @@ -0,0 +1 @@ +.ac dec 0 0Hz 0Hz \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741-cache.lib b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741-cache.lib new file mode 100644 index 000000000..04e3fecd3 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.cir b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.cir new file mode 100644 index 000000000..4a5917ea6 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.cir.out b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.cir.out new file mode 100644 index 000000000..a00bd86af --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.pro b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.pro new file mode 100644 index 000000000..b56de1b0f --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.pro @@ -0,0 +1,44 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.sch b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.sch new file mode 100644 index 000000000..b017fd2b8 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CE90A85 +P 3550 5200 +F 0 "R2" H 3600 5330 50 0000 C CNN +F 1 "50k" H 3600 5250 50 0000 C CNN +F 2 "" H 3600 5180 30 0000 C CNN +F 3 "" V 3600 5250 30 0000 C CNN + 1 3550 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CE90A86 +P 4000 5200 +F 0 "R3" H 4050 5330 50 0000 C CNN +F 1 "1k" H 4050 5250 50 0000 C CNN +F 2 "" H 4050 5180 30 0000 C CNN +F 3 "" V 4050 5250 30 0000 C CNN + 1 4000 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE90A87 +P 6300 4700 +F 0 "Q12" H 6200 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN +F 2 "" H 6500 4800 29 0000 C CNN +F 3 "" H 6300 4700 60 0000 C CNN + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE90A88 +P 5400 4700 +F 0 "Q13" H 5300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN +F 2 "" H 5600 4800 29 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 1 5400 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 5CE90A89 +P 5250 5200 +F 0 "R4" H 5300 5330 50 0000 C CNN +F 1 "5k" H 5300 5250 50 0000 C CNN +F 2 "" H 5300 5180 30 0000 C CNN +F 3 "" V 5300 5250 30 0000 C CNN + 1 5250 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5CE90A8A +P 6350 2750 +F 0 "R11" H 6400 2880 50 0000 C CNN +F 1 "39k" H 6400 2800 50 0000 C CNN +F 2 "" H 6400 2730 30 0000 C CNN +F 3 "" V 6400 2800 30 0000 C CNN + 1 6350 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 5CE90A8B +P 6500 1950 +F 0 "Q10" H 6400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 6450 2100 50 0000 R CNN +F 2 "" H 6700 2050 29 0000 C CNN +F 3 "" H 6500 1950 60 0000 C CNN + 1 6500 1950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 5CE90A8C +P 7500 1950 +F 0 "Q11" H 7400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 7450 2100 50 0000 R CNN +F 2 "" H 7700 2050 29 0000 C CNN +F 3 "" H 7500 1950 60 0000 C CNN + 1 7500 1950 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 5CE90A8D +P 7500 3050 +F 0 "Q14" H 7400 3100 50 0000 R CNN +F 1 "eSim_NPN" H 7450 3200 50 0000 R CNN +F 2 "" H 7700 3150 29 0000 C CNN +F 3 "" H 7500 3050 60 0000 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R8 +U 1 1 5CE90A8E +P 7300 2600 +F 0 "R8" H 7350 2730 50 0000 C CNN +F 1 "4.5k" H 7350 2650 50 0000 C CNN +F 2 "" H 7350 2580 30 0000 C CNN +F 3 "" V 7350 2650 30 0000 C CNN + 1 7300 2600 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R7 +U 1 1 5CE90A8F +P 7300 3400 +F 0 "R7" H 7350 3530 50 0000 C CNN +F 1 "7.5k" H 7350 3450 50 0000 C CNN +F 2 "" H 7350 3380 30 0000 C CNN +F 3 "" V 7350 3450 30 0000 C CNN + 1 7300 3400 + -1 0 0 1 +$EndComp +$Comp +L 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"50" H 7600 5100 50 0000 C CNN +F 2 "" H 7600 5030 30 0000 C CNN +F 3 "" V 7600 5100 30 0000 C CNN + 1 7550 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE90A95 +P 6800 4700 +F 0 "Q17" H 6700 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6750 4850 50 0000 R CNN +F 2 "" H 7000 4800 29 0000 C CNN +F 3 "" H 6800 4700 60 0000 C CNN + 1 6800 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 5CE90A96 +P 8800 2300 +F 0 "Q18" H 8700 2350 50 0000 R CNN +F 1 "eSim_NPN" H 8750 2450 50 0000 R CNN +F 2 "" H 9000 2400 29 0000 C CNN +F 3 "" H 8800 2300 60 0000 C CNN + 1 8800 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 5CE90A97 +P 8400 2750 +F 0 "Q20" H 8300 2800 50 0000 R CNN +F 1 "eSim_NPN" H 8350 2900 50 0000 R CNN +F 2 "" H 8600 2850 29 0000 C CNN +F 3 "" H 8400 2750 60 0000 C CNN + 1 8400 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CE90A98 +P 8850 3000 +F 0 "R9" H 8900 3130 50 0000 C CNN +F 1 "25" H 8900 3050 50 0000 C CNN +F 2 "" H 8900 2980 30 0000 C CNN +F 3 "" V 8900 3050 30 0000 C CNN + 1 8850 3000 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5CE90A99 +P 8850 3750 +F 0 "R10" H 8900 3880 50 0000 C CNN +F 1 "50" H 8900 3800 50 0000 C CNN +F 2 "" H 8900 3730 30 0000 C CNN +F 3 "" V 8900 3800 30 0000 C CNN + 1 8850 3750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q19 +U 1 1 5CE90A9A +P 8800 4600 +F 0 "Q19" H 8700 4650 50 0000 R CNN +F 1 "eSim_PNP" H 8750 4750 50 0000 R CNN +F 2 "" H 9000 4700 29 0000 C CNN +F 3 "" H 8800 4600 60 0000 C CNN + 1 8800 4600 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CE90A9B +P 1900 1200 +F 0 "U1" H 1950 1300 30 0000 C CNN +F 1 "PORT" H 1900 1200 30 0000 C CNN +F 2 "" H 1900 1200 60 0000 C CNN +F 3 "" H 1900 1200 60 0000 C CNN + 3 1900 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CE90A9C +P 4500 1050 +F 0 "U1" H 4550 1150 30 0000 C CNN +F 1 "PORT" H 4500 1050 30 0000 C CNN +F 2 "" H 4500 1050 60 0000 C CNN +F 3 "" H 4500 1050 60 0000 C CNN + 2 4500 1050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CE90A9D 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0000 C CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.sub b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.sub new file mode 100644 index 000000000..fa8d27b16 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741_Previous_Values.xml new file mode 100644 index 000000000..b61322bb5 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/npn_1.lib b/library/SubcircuitLibrary/SLOA024B_HighPass/npn_1.lib new file mode 100644 index 000000000..a1818ed83 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_HighPass/pnp_1.lib b/library/SubcircuitLibrary/SLOA024B_HighPass/pnp_1.lib new file mode 100644 index 000000000..a4ee06da6 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_HighPass/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/NPN.lib b/library/SubcircuitLibrary/SLOA024B_LowPass/NPN.lib new file mode 100644 index 000000000..6509fe7ab --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/PNP.lib b/library/SubcircuitLibrary/SLOA024B_LowPass/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass-cache.lib b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass-cache.lib new file mode 100644 index 000000000..56a34eac5 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass-cache.lib @@ -0,0 +1,115 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.cir b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.cir new file mode 100644 index 000000000..b2e8cc49b --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.cir @@ -0,0 +1,16 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SLOA024B_LowPass\SLOA024B_LowPass.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/18/25 20:33:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 ? Net-_C1-Pad1_ Net-_C2-Pad1_ Net-_U1-Pad4_ ? Net-_C2-Pad1_ Net-_U1-Pad2_ ? lm_741 +R1 Net-_R1-Pad1_ Net-_C2-Pad2_ 4.99k +R2 Net-_C2-Pad2_ Net-_C1-Pad1_ 12.1k +C1 Net-_C1-Pad1_ GND 10n +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 82n +U1 Net-_R1-Pad1_ Net-_U1-Pad2_ Net-_C2-Pad1_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.cir.out b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.cir.out new file mode 100644 index 000000000..691988058 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.cir.out @@ -0,0 +1,18 @@ +* d:\fossee\esim\library\subcircuitlibrary\sloa024b_lowpass\sloa024b_lowpass.cir + +.include lm_741.sub +x1 ? net-_c1-pad1_ net-_c2-pad1_ net-_u1-pad4_ ? net-_c2-pad1_ net-_u1-pad2_ ? lm_741 +r1 net-_r1-pad1_ net-_c2-pad2_ 4.99k +r2 net-_c2-pad2_ net-_c1-pad1_ 12.1k +c1 net-_c1-pad1_ gnd 10n +c2 net-_c2-pad1_ net-_c2-pad2_ 82n +* u1 net-_r1-pad1_ net-_u1-pad2_ net-_c2-pad1_ net-_u1-pad4_ port +.ac dec 0 0Hz 0Meg + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.out b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.out new file mode 100644 index 000000000..22bca4bb4 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.out @@ -0,0 +1,18 @@ +* c:\fossee\esim\library\subcircuitlibrary\sallenkey_lowpass\sallenkey_lowpass.cir + +.include lm_741.sub +x1 ? net-_c1-pad1_ net-_c2-pad1_ net-_u1-pad4_ ? net-_c2-pad1_ net-_u1-pad2_ ? lm_741 +r1 net-_r1-pad1_ net-_c2-pad2_ 4.99k +r2 net-_c2-pad2_ net-_c1-pad1_ 12.1k +c1 net-_c1-pad1_ gnd 10n +c2 net-_c2-pad1_ net-_c2-pad2_ 82n +* u1 net-_r1-pad1_ net-_u1-pad2_ net-_c2-pad1_ net-_u1-pad4_ port +.ac dec 10 10Hz 100Meg + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.pro b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.sch b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.sch new file mode 100644 index 000000000..580d51d03 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.sch @@ -0,0 +1,201 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SLOA024B_LowPass-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L lm_741 X1 +U 1 1 685A3869 +P 6150 3500 +F 0 "X1" H 5950 3500 60 0000 C CNN +F 1 "lm_741" H 6050 3250 60 0000 C CNN +F 2 "" H 6150 3500 60 0000 C CNN +F 3 "" H 6150 3500 60 0000 C CNN + 1 6150 3500 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 685A38EC +P 4200 3400 +F 0 "R1" H 4250 3530 50 0000 C CNN +F 1 "4.99k" H 4250 3350 50 0000 C CNN +F 2 "" H 4250 3380 30 0000 C CNN +F 3 "" V 4250 3450 30 0000 C CNN + 1 4200 3400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 685A391B +P 4950 3400 +F 0 "R2" H 5000 3530 50 0000 C CNN +F 1 "12.1k" H 5000 3350 50 0000 C CNN +F 2 "" H 5000 3380 30 0000 C CNN +F 3 "" V 5000 3450 30 0000 C CNN + 1 4950 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 3350 5600 3350 +Wire Wire Line + 4400 3350 4850 3350 +Wire Wire Line + 4100 3350 3800 3350 +$Comp +L capacitor C1 +U 1 1 685A399A +P 5350 3850 +F 0 "C1" H 5375 3950 50 0000 L CNN +F 1 "10n" H 5375 3750 50 0000 L CNN +F 2 "" H 5388 3700 30 0000 C CNN +F 3 "" H 5350 3850 60 0000 C CNN + 1 5350 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3700 5350 3350 +Connection ~ 5350 3350 +Wire Wire Line + 6700 3500 7550 3500 +$Comp +L capacitor C2 +U 1 1 685A3AA0 +P 5550 2500 +F 0 "C2" H 5575 2600 50 0000 L CNN +F 1 "82n" H 5575 2400 50 0000 L CNN +F 2 "" H 5588 2350 30 0000 C CNN +F 3 "" H 5550 2500 60 0000 C CNN + 1 5550 2500 + 0 1 1 0 +$EndComp +Wire Wire Line + 4650 3350 4650 2500 +Wire Wire Line + 4650 2500 5400 2500 +Connection ~ 4650 3350 +Wire Wire Line + 5700 2500 6850 2500 +Wire Wire Line + 6850 2500 6850 3500 +Connection ~ 6850 3500 +Wire Wire Line + 5600 3600 5600 4450 +Wire Wire Line + 5600 4450 6800 4450 +Wire Wire Line + 6800 4450 6800 3500 +Connection ~ 6800 3500 +Wire Wire Line + 5350 4000 5350 4300 +$Comp +L GND #PWR01 +U 1 1 685A3B77 +P 5350 4300 +F 0 "#PWR01" H 5350 4050 50 0001 C CNN +F 1 "GND" H 5350 4150 50 0000 C CNN +F 2 "" H 5350 4300 50 0001 C CNN +F 3 "" H 5350 4300 50 0001 C CNN + 1 5350 4300 + 1 0 0 -1 +$EndComp +NoConn ~ 6100 3100 +NoConn ~ 6200 3150 +$Comp +L PORT U1 +U 1 1 685A3D93 +P 3550 3350 +F 0 "U1" H 3600 3450 30 0000 C CNN +F 1 "PORT" H 3550 3350 30 0000 C CNN +F 2 "" H 3550 3350 60 0000 C CNN +F 3 "" H 3550 3350 60 0000 C CNN + 1 3550 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685A3DFE +P 6000 2800 +F 0 "U1" H 6050 2900 30 0000 C CNN +F 1 "PORT" H 6000 2800 30 0000 C CNN +F 2 "" H 6000 2800 60 0000 C CNN +F 3 "" H 6000 2800 60 0000 C CNN + 2 6000 2800 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 685A3E35 +P 7800 3500 +F 0 "U1" H 7850 3600 30 0000 C CNN +F 1 "PORT" H 7800 3500 30 0000 C CNN +F 2 "" H 7800 3500 60 0000 C CNN +F 3 "" H 7800 3500 60 0000 C CNN + 3 7800 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 685A3E82 +P 6000 4200 +F 0 "U1" H 6050 4300 30 0000 C CNN +F 1 "PORT" H 6000 4200 30 0000 C CNN +F 2 "" H 6000 4200 60 0000 C CNN +F 3 "" H 6000 4200 60 0000 C CNN + 4 6000 4200 + 0 -1 -1 0 +$EndComp +Text Notes 4950 1900 0 60 ~ 0 +Sallen-Key Low Pass Filter - UNITY GAIN +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.sub b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.sub new file mode 100644 index 000000000..b5f8a6026 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass.sub @@ -0,0 +1,12 @@ +* Subcircuit SLOA024B_LowPass +.subckt SLOA024B_LowPass net-_r1-pad1_ net-_u1-pad2_ net-_c2-pad1_ net-_u1-pad4_ +* d:\fossee\esim\library\subcircuitlibrary\sloa024b_lowpass\sloa024b_lowpass.cir +.include lm_741.sub +x1 ? net-_c1-pad1_ net-_c2-pad1_ net-_u1-pad4_ ? net-_c2-pad1_ net-_u1-pad2_ ? lm_741 +r1 net-_r1-pad1_ net-_c2-pad2_ 4.99k +r2 net-_c2-pad2_ net-_c1-pad1_ 12.1k +c1 net-_c1-pad1_ gnd 10n +c2 net-_c2-pad1_ net-_c2-pad2_ 82n +* Control Statements + +.ends SLOA024B_LowPass \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass_Previous_Values.xml b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass_Previous_Values.xml new file mode 100644 index 000000000..02639168d --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/SLOA024B_LowPass_Previous_Values.xml @@ -0,0 +1 @@ +D:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741falsetruefalseHzMeg0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes00.110secmsms \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/analysis b/library/SubcircuitLibrary/SLOA024B_LowPass/analysis new file mode 100644 index 000000000..43b85d361 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/analysis @@ -0,0 +1 @@ +.ac dec 0 0Hz 0Meg \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741-cache.lib b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741-cache.lib new file mode 100644 index 000000000..04e3fecd3 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.cir b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.cir new file mode 100644 index 000000000..4a5917ea6 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.cir.out b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.cir.out new file mode 100644 index 000000000..a00bd86af --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.pro b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.pro new file mode 100644 index 000000000..b56de1b0f --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.pro @@ -0,0 +1,44 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.sch b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.sch new file mode 100644 index 000000000..b017fd2b8 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 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"50" H 7600 5100 50 0000 C CNN +F 2 "" H 7600 5030 30 0000 C CNN +F 3 "" V 7600 5100 30 0000 C CNN + 1 7550 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE90A95 +P 6800 4700 +F 0 "Q17" H 6700 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6750 4850 50 0000 R CNN +F 2 "" H 7000 4800 29 0000 C CNN +F 3 "" H 6800 4700 60 0000 C CNN + 1 6800 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 5CE90A96 +P 8800 2300 +F 0 "Q18" H 8700 2350 50 0000 R CNN +F 1 "eSim_NPN" H 8750 2450 50 0000 R CNN +F 2 "" H 9000 2400 29 0000 C CNN +F 3 "" H 8800 2300 60 0000 C CNN + 1 8800 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 5CE90A97 +P 8400 2750 +F 0 "Q20" H 8300 2800 50 0000 R CNN +F 1 "eSim_NPN" H 8350 2900 50 0000 R CNN +F 2 "" H 8600 2850 29 0000 C CNN +F 3 "" H 8400 2750 60 0000 C CNN + 1 8400 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CE90A98 +P 8850 3000 +F 0 "R9" H 8900 3130 50 0000 C CNN +F 1 "25" H 8900 3050 50 0000 C CNN +F 2 "" H 8900 2980 30 0000 C CNN +F 3 "" V 8900 3050 30 0000 C CNN + 1 8850 3000 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5CE90A99 +P 8850 3750 +F 0 "R10" H 8900 3880 50 0000 C CNN +F 1 "50" H 8900 3800 50 0000 C CNN +F 2 "" H 8900 3730 30 0000 C CNN +F 3 "" V 8900 3800 30 0000 C CNN + 1 8850 3750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q19 +U 1 1 5CE90A9A +P 8800 4600 +F 0 "Q19" H 8700 4650 50 0000 R CNN +F 1 "eSim_PNP" H 8750 4750 50 0000 R CNN +F 2 "" H 9000 4700 29 0000 C CNN +F 3 "" H 8800 4600 60 0000 C CNN + 1 8800 4600 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CE90A9B +P 1900 1200 +F 0 "U1" H 1950 1300 30 0000 C CNN +F 1 "PORT" H 1900 1200 30 0000 C CNN +F 2 "" H 1900 1200 60 0000 C CNN +F 3 "" H 1900 1200 60 0000 C CNN + 3 1900 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CE90A9C +P 4500 1050 +F 0 "U1" H 4550 1150 30 0000 C CNN +F 1 "PORT" H 4500 1050 30 0000 C CNN +F 2 "" H 4500 1050 60 0000 C CNN +F 3 "" H 4500 1050 60 0000 C CNN + 2 4500 1050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CE90A9D +P 9750 1650 +F 0 "U1" H 9800 1750 30 0000 C CNN +F 1 "PORT" H 9750 1650 30 0000 C CNN +F 2 "" H 9750 1650 60 0000 C CNN +F 3 "" H 9750 1650 60 0000 C CNN + 7 9750 1650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CE90A9E +P 9750 3500 +F 0 "U1" H 9800 3600 30 0000 C CNN +F 1 "PORT" H 9750 3500 30 0000 C CNN +F 2 "" H 9750 3500 60 0000 C CNN +F 3 "" H 9750 3500 60 0000 C CNN + 6 9750 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CE90A9F +P 9700 5550 +F 0 "U1" H 9750 5650 30 0000 C CNN +F 1 "PORT" H 9700 5550 30 0000 C CNN +F 2 "" H 9700 5550 60 0000 C CNN +F 3 "" H 9700 5550 60 0000 C CNN + 4 9700 5550 + -1 0 0 1 +$EndComp +Wire Wire Line + 3200 3200 3750 3200 +Wire Wire Line + 2750 2900 2750 2950 +Wire Wire Line + 2750 2950 2900 2950 +Wire Wire Line + 2900 2950 2900 3000 +Wire Wire Line + 4200 2900 4200 2950 +Wire Wire Line + 4200 2950 4050 2950 +Wire Wire Line + 4050 2950 4050 3000 +Wire Wire Line + 2900 3400 2900 4400 +Wire Wire Line + 2900 4000 3100 4000 +Wire Wire Line + 4200 2000 4200 2500 +Wire Wire Line + 4200 2350 2750 2350 +Wire Wire Line + 2750 2350 2750 2500 +Wire Wire Line + 5000 2000 4050 2000 +Connection ~ 4200 2350 +Connection ~ 4200 2000 +Wire Wire Line + 3750 2200 3750 2350 +Connection ~ 3750 2350 +Wire Wire Line + 3750 1800 3750 1650 +Wire Wire Line + 3400 1650 7600 1650 +Wire Wire Line + 3400 1650 3400 3800 +Wire Wire Line + 5300 1650 5300 1800 +Connection ~ 3750 1650 +Wire Wire Line + 5300 2200 5300 4500 +Wire Wire Line + 5300 3500 3650 3500 +Wire Wire Line + 3650 3500 3650 3200 +Connection ~ 3650 3200 +Connection ~ 2900 4000 +Wire Wire Line + 4050 4400 4050 3400 +Wire Wire Line + 3400 4200 3400 4600 +Wire Wire Line + 3200 4600 3750 4600 +Connection ~ 3400 4600 +Wire Wire Line + 4050 5100 4050 4800 +Wire Wire Line + 3600 5100 3600 4600 +Connection ~ 3600 4600 +Wire Wire Line + 2900 5100 2900 4800 +Wire Wire Line + 2900 5400 2900 5550 +Wire Wire Line + 2900 5550 9450 5550 +Wire Wire Line + 4050 5550 4050 5400 +Wire Wire Line + 3600 5400 3600 5550 +Connection ~ 3600 5550 +Wire Wire Line + 6100 4700 5600 4700 +Wire Wire Line + 6400 2950 6400 4500 +Wire Wire Line + 6400 4250 5900 4250 +Wire Wire Line + 5900 4250 5900 4700 +Connection ~ 5900 4700 +Wire Wire Line + 5300 5100 5300 4900 +Wire Wire Line + 5300 5550 5300 5400 +Connection ~ 4050 5550 +Wire Wire Line + 6400 5550 6400 4900 +Connection ~ 5300 5550 +Connection ~ 5300 3500 +Wire Wire Line + 6400 1650 6400 1750 +Connection ~ 5300 1650 +Wire Wire Line + 6400 2150 6400 2650 +Connection ~ 6400 4250 +Wire Wire Line + 6700 1950 7300 1950 +Wire Wire Line + 7000 1950 7000 2250 +Wire Wire Line + 7000 2250 6400 2250 +Connection ~ 6400 2250 +Wire Wire Line + 7600 1650 7600 1750 +Connection ~ 6400 1650 +Connection ~ 7000 1950 +Wire Wire Line + 7600 3250 7600 4100 +Wire Wire Line + 7600 3450 7400 3450 +Wire Wire Line + 6900 3450 7100 3450 +Wire Wire Line + 6900 2650 6900 3450 +Wire Wire Line + 6900 3050 7300 3050 +Wire Wire Line + 7600 2150 7600 2850 +Wire Wire Line + 7600 2650 7400 2650 +Wire Wire Line + 7100 2650 6900 2650 +Connection ~ 6900 3050 +Connection ~ 7600 2650 +Wire Wire Line + 7300 4300 7150 4300 +Wire Wire Line + 7150 4150 7150 4950 +Connection ~ 7600 3450 +Wire Wire Line + 7600 3700 7150 3700 +Wire Wire Line + 7150 3700 7150 3750 +Connection ~ 7600 3700 +Wire Wire Line + 6600 3050 6600 2450 +Wire Wire Line + 6600 2450 7600 2450 +Connection ~ 7600 2450 +Wire Wire Line + 6600 3350 6600 3950 +Wire Wire Line + 4050 3950 6850 3950 +Wire Wire Line + 6700 3950 6700 4500 +Connection ~ 6700 3950 +Wire Wire Line + 6700 4900 6700 5550 +Connection ~ 6400 5550 +Connection ~ 7150 4300 +Wire Wire Line + 7600 4950 7600 4500 +Wire Wire Line + 7000 4700 7600 4700 +Connection ~ 7600 4700 +Wire Wire Line + 7600 5550 7600 5250 +Connection ~ 6700 5550 +Wire Wire Line + 7150 5250 7150 5550 +Connection ~ 7150 5550 +Wire Wire Line + 7600 2300 8600 2300 +Wire Wire Line + 8300 2300 8300 2550 +Connection ~ 8300 2300 +Connection ~ 7600 2300 +Wire Wire Line + 8900 2100 8900 1650 +Wire Wire Line + 7550 1650 9500 1650 +Connection ~ 7550 1650 +Connection ~ 8900 1650 +Wire Wire Line + 8900 2500 8900 2900 +Wire Wire Line + 8900 2750 8600 2750 +Connection ~ 8900 2750 +Wire Wire Line + 8300 2950 8300 3350 +Wire Wire Line + 8300 3350 8900 3350 +Wire Wire Line + 8900 3200 8900 3650 +Wire Wire Line + 8900 4400 8900 3950 +Connection ~ 8900 3350 +Wire Wire Line + 8900 3500 9500 3500 +Connection ~ 8900 3500 +Wire Wire Line + 8900 5550 8900 4800 +Connection ~ 7600 5550 +Connection ~ 8900 5550 +Wire Wire Line + 8600 4600 8100 4600 +Wire Wire Line + 8100 4600 8100 3850 +Wire Wire Line + 8100 3850 7600 3850 +Connection ~ 7600 3850 +Connection ~ 4050 3950 +Connection ~ 6600 3950 +Wire Wire Line + 4500 2700 4750 2700 +Wire Wire Line + 4750 2700 4750 1050 +Wire Wire Line + 2450 2700 2150 2700 +Wire Wire Line + 2150 2700 2150 1200 +$Comp +L PORT U1 +U 5 1 5CE90AA0 +P 1850 4850 +F 0 "U1" H 1900 4950 30 0000 C CNN +F 1 "PORT" H 1850 4850 30 0000 C CNN +F 2 "" H 1850 4850 60 0000 C CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.sub b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.sub new file mode 100644 index 000000000..fa8d27b16 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741_Previous_Values.xml new file mode 100644 index 000000000..b61322bb5 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/npn_1.lib b/library/SubcircuitLibrary/SLOA024B_LowPass/npn_1.lib new file mode 100644 index 000000000..a1818ed83 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file diff --git a/library/SubcircuitLibrary/SLOA024B_LowPass/pnp_1.lib b/library/SubcircuitLibrary/SLOA024B_LowPass/pnp_1.lib new file mode 100644 index 000000000..a4ee06da6 --- /dev/null +++ b/library/SubcircuitLibrary/SLOA024B_LowPass/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54S64/3_and-cache.lib b/library/SubcircuitLibrary/SN54S64/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54S64/3_and.cir b/library/SubcircuitLibrary/SN54S64/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54S64/3_and.cir.out b/library/SubcircuitLibrary/SN54S64/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54S64/3_and.pro b/library/SubcircuitLibrary/SN54S64/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54S64/3_and.sch b/library/SubcircuitLibrary/SN54S64/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54S64/3_and.sub b/library/SubcircuitLibrary/SN54S64/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54S64/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54S64/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54S64/4_OR-cache.lib b/library/SubcircuitLibrary/SN54S64/4_OR-cache.lib new file mode 100644 index 000000000..155f5e601 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54S64/4_OR.cir b/library/SubcircuitLibrary/SN54S64/4_OR.cir new file mode 100644 index 000000000..b338b7b5f --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54S64/4_OR.cir.out b/library/SubcircuitLibrary/SN54S64/4_OR.cir.out new file mode 100644 index 000000000..adb6b01be --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54S64/4_OR.pro b/library/SubcircuitLibrary/SN54S64/4_OR.pro new file mode 100644 index 000000000..881563ebd --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54S64/4_OR.sch b/library/SubcircuitLibrary/SN54S64/4_OR.sch new file mode 100644 index 000000000..118968656 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54S64/4_OR.sub b/library/SubcircuitLibrary/SN54S64/4_OR.sub new file mode 100644 index 000000000..d1fd3a241 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54S64/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN54S64/4_OR_Previous_Values.xml new file mode 100644 index 000000000..0683d9eb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54S64/4_and-cache.lib b/library/SubcircuitLibrary/SN54S64/4_and-cache.lib new file mode 100644 index 000000000..60f1a83d4 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54S64/4_and-rescue.lib b/library/SubcircuitLibrary/SN54S64/4_and-rescue.lib new file mode 100644 index 000000000..e38330518 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54S64/4_and.cir b/library/SubcircuitLibrary/SN54S64/4_and.cir new file mode 100644 index 000000000..fdf2e1074 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54S64/4_and.cir.out b/library/SubcircuitLibrary/SN54S64/4_and.cir.out new file mode 100644 index 000000000..f40e5bc62 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54S64/4_and.pro b/library/SubcircuitLibrary/SN54S64/4_and.pro new file mode 100644 index 000000000..b13a0a825 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/SN54S64/4_and.sch b/library/SubcircuitLibrary/SN54S64/4_and.sch new file mode 100644 index 000000000..f5e8febdc --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54S64/4_and.sub b/library/SubcircuitLibrary/SN54S64/4_and.sub new file mode 100644 index 000000000..8663f37e6 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54S64/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54S64/4_and_Previous_Values.xml new file mode 100644 index 000000000..f2ba0130e --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54S64/SN54S64-cache.lib b/library/SubcircuitLibrary/SN54S64/SN54S64-cache.lib new file mode 100644 index 000000000..34b993cdc --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/SN54S64-cache.lib @@ -0,0 +1,133 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54S64/SN54S64.cir b/library/SubcircuitLibrary/SN54S64/SN54S64.cir new file mode 100644 index 000000000..f0fbbaeb9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/SN54S64.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN54S64\SN54S64.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/12/25 13:37:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X2 Net-_U1-Pad1_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_X2-Pad5_ 4_and +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and +X1 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_X1-Pad4_ 3_and +U3 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U3-Pad3_ d_and +X3 Net-_X2-Pad5_ Net-_U2-Pad3_ Net-_X1-Pad4_ Net-_U3-Pad3_ Net-_U4-Pad1_ 4_OR +U4 Net-_U4-Pad1_ Net-_U1-Pad8_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN54S64/SN54S64.cir.out b/library/SubcircuitLibrary/SN54S64/SN54S64.cir.out new file mode 100644 index 000000000..12ba7e058 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/SN54S64.cir.out @@ -0,0 +1,30 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn54s64\sn54s64.cir + +.include 4_and.sub +.include 4_OR.sub +.include 3_and.sub +x2 net-_u1-pad1_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_x2-pad5_ 4_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +x1 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_x1-pad4_ 3_and +* u3 net-_u1-pad9_ net-_u1-pad10_ net-_u3-pad3_ d_and +x3 net-_x2-pad5_ net-_u2-pad3_ net-_x1-pad4_ net-_u3-pad3_ net-_u4-pad1_ 4_OR +* u4 net-_u4-pad1_ net-_u1-pad8_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u3-pad3_ u3 +a3 net-_u4-pad1_ net-_u1-pad8_ u4 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54S64/SN54S64.pro b/library/SubcircuitLibrary/SN54S64/SN54S64.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/SN54S64.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN54S64/SN54S64.sch b/library/SubcircuitLibrary/SN54S64/SN54S64.sch new file mode 100644 index 000000000..5b850e806 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/SN54S64.sch @@ -0,0 +1,328 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4_and X2 +U 1 1 684A892E +P 3450 2300 +F 0 "X2" H 3500 2250 60 0000 C CNN +F 1 "4_and" H 3550 2400 60 0000 C CNN +F 2 "" H 3450 2300 60 0000 C CNN +F 3 "" H 3450 2300 60 0000 C CNN + 1 3450 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 684A898B +P 3450 3250 +F 0 "U2" H 3450 3250 60 0000 C CNN +F 1 "d_and" H 3500 3350 60 0000 C CNN +F 2 "" H 3450 3250 60 0000 C CNN +F 3 "" H 3450 3250 60 0000 C CNN + 1 3450 3250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 684A89E4 +P 3350 4000 +F 0 "X1" H 3450 3950 60 0000 C CNN +F 1 "3_and" H 3500 4150 60 0000 C CNN +F 2 "" H 3350 4000 60 0000 C CNN +F 3 "" H 3350 4000 60 0000 C CNN + 1 3350 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 684A8A1B +P 3450 4950 +F 0 "U3" H 3450 4950 60 0000 C CNN +F 1 "d_and" H 3500 5050 60 0000 C CNN +F 2 "" H 3450 4950 60 0000 C CNN +F 3 "" H 3450 4950 60 0000 C CNN + 1 3450 4950 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X3 +U 1 1 684A8A96 +P 5450 3500 +F 0 "X3" H 5600 3400 60 0000 C CNN +F 1 "4_OR" H 5600 3600 60 0000 C CNN +F 2 "" H 5450 3500 60 0000 C CNN +F 3 "" H 5450 3500 60 0000 C CNN + 1 5450 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 684A8AEF +P 7000 3500 +F 0 "U4" H 7000 3400 60 0000 C CNN +F 1 "d_inverter" H 7000 3650 60 0000 C CNN +F 2 "" H 7050 3450 60 0000 C CNN +F 3 "" H 7050 3450 60 0000 C CNN + 1 7000 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3050 2150 2400 2150 +Wire Wire Line + 3050 2250 2400 2250 +Wire Wire Line + 3050 2350 2400 2350 +Wire Wire Line + 3050 2450 2400 2450 +Wire Wire Line + 3000 3150 2400 3150 +Wire Wire Line + 3000 3250 2400 3250 +Wire Wire Line + 3000 3850 2400 3850 +Wire Wire Line + 3000 3950 2400 3950 +Wire Wire Line + 3000 4050 2400 4050 +Wire Wire Line + 3950 2300 4800 2300 +Wire Wire Line + 4800 2300 4800 3350 +Wire Wire Line + 4800 3350 5100 3350 +Wire Wire Line + 3900 3200 4600 3200 +Wire Wire Line + 4600 3200 4600 3450 +Wire Wire Line + 4600 3450 5100 3450 +Wire Wire Line + 3850 3950 4650 3950 +Wire Wire Line + 4650 3950 4650 3550 +Wire Wire Line + 4650 3550 5100 3550 +Wire Wire Line + 3900 4900 4850 4900 +Wire Wire Line + 4850 4900 4850 3650 +Wire Wire Line + 4850 3650 5100 3650 +Wire Wire Line + 3000 4850 2400 4850 +Wire Wire Line + 3000 4950 2400 4950 +Wire Wire Line + 6000 3500 6700 3500 +Wire Wire Line + 7300 3500 7850 3500 +$Comp +L PORT U1 +U 9 1 684A8DC0 +P 2150 4850 +F 0 "U1" H 2200 4950 30 0000 C CNN +F 1 "PORT" H 2150 4850 30 0000 C CNN +F 2 "" H 2150 4850 60 0000 C CNN +F 3 "" H 2150 4850 60 0000 C CNN + 9 2150 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 684A8E3B +P 2150 4950 +F 0 "U1" H 2200 5050 30 0000 C CNN +F 1 "PORT" H 2150 4950 30 0000 C CNN +F 2 "" H 2150 4950 60 0000 C CNN +F 3 "" H 2150 4950 60 0000 C CNN + 10 2150 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 684A8E6A +P 2150 2250 +F 0 "U1" H 2200 2350 30 0000 C CNN +F 1 "PORT" H 2150 2250 30 0000 C CNN +F 2 "" H 2150 2250 60 0000 C CNN +F 3 "" H 2150 2250 60 0000 C CNN + 11 2150 2250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 684A8EA9 +P 2150 2350 +F 0 "U1" H 2200 2450 30 0000 C CNN +F 1 "PORT" H 2150 2350 30 0000 C CNN +F 2 "" H 2150 2350 60 0000 C CNN +F 3 "" H 2150 2350 60 0000 C CNN + 12 2150 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 684A8F10 +P 2150 2450 +F 0 "U1" H 2200 2550 30 0000 C CNN +F 1 "PORT" H 2150 2450 30 0000 C CNN +F 2 "" H 2150 2450 60 0000 C CNN +F 3 "" H 2150 2450 60 0000 C CNN + 13 2150 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 684A8F5B +P 2150 2150 +F 0 "U1" H 2200 2250 30 0000 C CNN +F 1 "PORT" H 2150 2150 30 0000 C CNN +F 2 "" H 2150 2150 60 0000 C CNN +F 3 "" H 2150 2150 60 0000 C CNN + 1 2150 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 684A8F9C +P 2150 3150 +F 0 "U1" H 2200 3250 30 0000 C CNN +F 1 "PORT" H 2150 3150 30 0000 C CNN +F 2 "" H 2150 3150 60 0000 C CNN +F 3 "" H 2150 3150 60 0000 C CNN + 2 2150 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 684A8FE9 +P 2150 3250 +F 0 "U1" H 2200 3350 30 0000 C CNN +F 1 "PORT" H 2150 3250 30 0000 C CNN +F 2 "" H 2150 3250 60 0000 C CNN +F 3 "" H 2150 3250 60 0000 C CNN + 3 2150 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 684A905C +P 2150 3850 +F 0 "U1" H 2200 3950 30 0000 C CNN +F 1 "PORT" H 2150 3850 30 0000 C CNN +F 2 "" H 2150 3850 60 0000 C CNN +F 3 "" H 2150 3850 60 0000 C CNN + 4 2150 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 684A90DA +P 2150 3950 +F 0 "U1" H 2200 4050 30 0000 C CNN +F 1 "PORT" H 2150 3950 30 0000 C CNN +F 2 "" H 2150 3950 60 0000 C CNN +F 3 "" H 2150 3950 60 0000 C CNN + 5 2150 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 684A9113 +P 2150 4050 +F 0 "U1" H 2200 4150 30 0000 C CNN +F 1 "PORT" H 2150 4050 30 0000 C CNN +F 2 "" H 2150 4050 60 0000 C CNN +F 3 "" H 2150 4050 60 0000 C CNN + 6 2150 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 684A9150 +P 5700 1900 +F 0 "U1" H 5750 2000 30 0000 C CNN +F 1 "PORT" H 5700 1900 30 0000 C CNN +F 2 "" H 5700 1900 60 0000 C CNN +F 3 "" H 5700 1900 60 0000 C CNN + 7 5700 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 684A91A1 +P 8100 3500 +F 0 "U1" H 8150 3600 30 0000 C CNN +F 1 "PORT" H 8100 3500 30 0000 C CNN +F 2 "" H 8100 3500 60 0000 C CNN +F 3 "" H 8100 3500 60 0000 C CNN + 8 8100 3500 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 684A91F2 +P 5750 2350 +F 0 "U1" H 5800 2450 30 0000 C CNN +F 1 "PORT" H 5750 2350 30 0000 C CNN +F 2 "" H 5750 2350 60 0000 C CNN +F 3 "" H 5750 2350 60 0000 C CNN + 14 5750 2350 + 1 0 0 -1 +$EndComp +NoConn ~ 5950 1900 +NoConn ~ 6000 2350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54S64/SN54S64.sub b/library/SubcircuitLibrary/SN54S64/SN54S64.sub new file mode 100644 index 000000000..8b3c2ca5d --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/SN54S64.sub @@ -0,0 +1,24 @@ +* Subcircuit SN54S64 +.subckt SN54S64 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee\esim\library\subcircuitlibrary\sn54s64\sn54s64.cir +.include 4_and.sub +.include 4_OR.sub +.include 3_and.sub +x2 net-_u1-pad1_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_x2-pad5_ 4_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +x1 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_x1-pad4_ 3_and +* u3 net-_u1-pad9_ net-_u1-pad10_ net-_u3-pad3_ d_and +x3 net-_x2-pad5_ net-_u2-pad3_ net-_x1-pad4_ net-_u3-pad3_ net-_u4-pad1_ 4_OR +* u4 net-_u4-pad1_ net-_u1-pad8_ d_inverter +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u3-pad3_ u3 +a3 net-_u4-pad1_ net-_u1-pad8_ u4 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN54S64 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54S64/SN54S64_Previous_Values.xml b/library/SubcircuitLibrary/SN54S64/SN54S64_Previous_Values.xml new file mode 100644 index 000000000..08a425b16 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/SN54S64_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_OR \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54S64/analysis b/library/SubcircuitLibrary/SN54S64/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN54S64/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ACT86/SN74ACT86-cache.lib b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86-cache.lib new file mode 100644 index 000000000..889b42675 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.cir b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.cir new file mode 100644 index 000000000..ca1b83c71 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.cir @@ -0,0 +1,31 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74ACT86\SN74ACT86.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 12:15:21 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U9 Net-_U1-Pad1_ Net-_U5-Pad2_ Net-_U17-Pad1_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U5 Net-_U10-Pad2_ Net-_U5-Pad2_ d_inverter +U10 Net-_U1-Pad2_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U17 Net-_U17-Pad1_ Net-_U10-Pad3_ Net-_U17-Pad3_ d_or +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U2 Net-_U11-Pad1_ Net-_U12-Pad1_ d_inverter +U6 Net-_U12-Pad2_ Net-_U11-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U18-Pad3_ d_or +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U3 Net-_U13-Pad1_ Net-_U14-Pad1_ d_inverter +U7 Net-_U14-Pad2_ Net-_U13-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and +U19 Net-_U13-Pad3_ Net-_U14-Pad3_ Net-_U19-Pad3_ d_or +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and +U4 Net-_U15-Pad1_ Net-_U16-Pad1_ d_inverter +U8 Net-_U16-Pad2_ Net-_U15-Pad2_ d_inverter +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_and +U20 Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U20-Pad3_ d_or +U21 Net-_U1-Pad1_ Net-_U10-Pad2_ Net-_U17-Pad3_ Net-_U11-Pad1_ Net-_U12-Pad2_ Net-_U18-Pad3_ ? Net-_U19-Pad3_ Net-_U13-Pad1_ Net-_U14-Pad2_ Net-_U20-Pad3_ Net-_U15-Pad1_ Net-_U16-Pad2_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.cir.out b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.cir.out new file mode 100644 index 000000000..e9cdb522d --- /dev/null +++ b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.cir.out @@ -0,0 +1,92 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74act86\sn74act86.cir + +* u9 net-_u1-pad1_ net-_u5-pad2_ net-_u17-pad1_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u5 net-_u10-pad2_ net-_u5-pad2_ d_inverter +* u10 net-_u1-pad2_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u17 net-_u17-pad1_ net-_u10-pad3_ net-_u17-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u2 net-_u11-pad1_ net-_u12-pad1_ d_inverter +* u6 net-_u12-pad2_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u18-pad3_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u3 net-_u13-pad1_ net-_u14-pad1_ d_inverter +* u7 net-_u14-pad2_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and +* u19 net-_u13-pad3_ net-_u14-pad3_ net-_u19-pad3_ d_or +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and +* u4 net-_u15-pad1_ net-_u16-pad1_ d_inverter +* u8 net-_u16-pad2_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u20 net-_u15-pad3_ net-_u16-pad3_ net-_u20-pad3_ d_or +* u21 net-_u1-pad1_ net-_u10-pad2_ net-_u17-pad3_ net-_u11-pad1_ net-_u12-pad2_ net-_u18-pad3_ ? net-_u19-pad3_ net-_u13-pad1_ net-_u14-pad2_ net-_u20-pad3_ net-_u15-pad1_ net-_u16-pad2_ ? port +a1 [net-_u1-pad1_ net-_u5-pad2_ ] net-_u17-pad1_ u9 +a2 net-_u1-pad1_ net-_u1-pad2_ u1 +a3 net-_u10-pad2_ net-_u5-pad2_ u5 +a4 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a5 [net-_u17-pad1_ net-_u10-pad3_ ] net-_u17-pad3_ u17 +a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a7 net-_u11-pad1_ net-_u12-pad1_ u2 +a8 net-_u12-pad2_ net-_u11-pad2_ u6 +a9 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a10 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u18-pad3_ u18 +a11 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a12 net-_u13-pad1_ net-_u14-pad1_ u3 +a13 net-_u14-pad2_ net-_u13-pad2_ u7 +a14 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a15 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u19-pad3_ u19 +a16 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a17 net-_u15-pad1_ net-_u16-pad1_ u4 +a18 net-_u16-pad2_ net-_u15-pad2_ u8 +a19 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a20 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u20-pad3_ u20 +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.pro b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.sch b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.sch new file mode 100644 index 000000000..b1d01d619 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.sch @@ -0,0 +1,592 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U9 +U 1 1 68510B55 +P 4900 1950 +F 0 "U9" H 4900 1950 60 0000 C CNN +F 1 "d_and" H 4950 2050 60 0000 C CNN +F 2 "" H 4900 1950 60 0000 C CNN +F 3 "" H 4900 1950 60 0000 C CNN + 1 4900 1950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U1 +U 1 1 68510C60 +P 3300 2000 +F 0 "U1" H 3300 1900 60 0000 C CNN +F 1 "d_inverter" H 3300 2150 60 0000 C CNN +F 2 "" H 3350 1950 60 0000 C CNN +F 3 "" H 3350 1950 60 0000 C CNN + 1 3300 2000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 68510CF5 +P 3400 2800 +F 0 "U5" H 3400 2700 60 0000 C CNN +F 1 "d_inverter" H 3400 2950 60 0000 C CNN +F 2 "" H 3450 2750 60 0000 C CNN +F 3 "" H 3450 2750 60 0000 C CNN + 1 3400 2800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 1750 4450 1750 +Wire Wire Line + 2850 1750 2850 2000 +Wire Wire Line + 2850 2000 3000 2000 +Connection ~ 2850 1750 +Wire Wire Line + 3600 2000 4050 2000 +Wire Wire Line + 2700 2600 4450 2600 +Wire Wire Line + 2900 2600 2900 2800 +Wire Wire Line + 2900 2800 3100 2800 +Connection ~ 2900 2600 +$Comp +L d_and U10 +U 1 1 68510DED +P 4900 2450 +F 0 "U10" H 4900 2450 60 0000 C CNN +F 1 "d_and" H 4950 2550 60 0000 C CNN +F 2 "" H 4900 2450 60 0000 C CNN +F 3 "" H 4900 2450 60 0000 C CNN + 1 4900 2450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 1750 4450 1850 +Wire Wire Line + 3700 2800 4250 2800 +Wire Wire Line + 4250 2800 4250 1950 +Wire Wire Line + 4250 1950 4450 1950 +Wire Wire Line + 4450 2600 4450 2450 +Wire Wire Line + 4050 2000 4050 2350 +Wire Wire Line + 4050 2350 4450 2350 +$Comp +L d_or U17 +U 1 1 68510E6C +P 5950 2250 +F 0 "U17" H 5950 2250 60 0000 C CNN +F 1 "d_or" H 5950 2350 60 0000 C CNN +F 2 "" H 5950 2250 60 0000 C CNN +F 3 "" H 5950 2250 60 0000 C CNN + 1 5950 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 1900 5500 1900 +Wire Wire Line + 5500 1900 5500 2150 +Wire Wire Line + 5350 2400 5500 2400 +Wire Wire Line + 5500 2400 5500 2250 +Wire Wire Line + 6400 2200 6600 2200 +$Comp +L d_and U11 +U 1 1 68511527 +P 4900 3750 +F 0 "U11" H 4900 3750 60 0000 C CNN +F 1 "d_and" H 4950 3850 60 0000 C CNN +F 2 "" H 4900 3750 60 0000 C CNN +F 3 "" H 4900 3750 60 0000 C CNN + 1 4900 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6851152D +P 3300 3800 +F 0 "U2" H 3300 3700 60 0000 C CNN +F 1 "d_inverter" H 3300 3950 60 0000 C CNN +F 2 "" H 3350 3750 60 0000 C CNN +F 3 "" H 3350 3750 60 0000 C CNN + 1 3300 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 68511533 +P 3400 4600 +F 0 "U6" H 3400 4500 60 0000 C CNN +F 1 "d_inverter" H 3400 4750 60 0000 C CNN +F 2 "" H 3450 4550 60 0000 C CNN +F 3 "" H 3450 4550 60 0000 C CNN + 1 3400 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 3550 4450 3550 +Wire Wire Line + 2850 3550 2850 3800 +Wire Wire Line + 2850 3800 3000 3800 +Connection ~ 2850 3550 +Wire Wire Line + 3600 3800 4050 3800 +Wire Wire Line + 2700 4400 4450 4400 +Wire Wire Line + 2900 4400 2900 4600 +Wire Wire Line + 2900 4600 3100 4600 +Connection ~ 2900 4400 +$Comp +L d_and U12 +U 1 1 68511542 +P 4900 4250 +F 0 "U12" H 4900 4250 60 0000 C CNN +F 1 "d_and" H 4950 4350 60 0000 C CNN +F 2 "" H 4900 4250 60 0000 C CNN +F 3 "" H 4900 4250 60 0000 C CNN + 1 4900 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 3550 4450 3650 +Wire Wire Line + 3700 4600 4250 4600 +Wire Wire Line + 4250 4600 4250 3750 +Wire Wire Line + 4250 3750 4450 3750 +Wire Wire Line + 4450 4400 4450 4250 +Wire Wire Line + 4050 3800 4050 4150 +Wire Wire Line + 4050 4150 4450 4150 +$Comp +L d_or U18 +U 1 1 6851154F +P 5950 4050 +F 0 "U18" H 5950 4050 60 0000 C CNN +F 1 "d_or" H 5950 4150 60 0000 C CNN +F 2 "" H 5950 4050 60 0000 C CNN +F 3 "" H 5950 4050 60 0000 C CNN + 1 5950 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3700 5500 3700 +Wire Wire Line + 5500 3700 5500 3950 +Wire Wire Line + 5350 4200 5500 4200 +Wire Wire Line + 5500 4200 5500 4050 +Wire Wire Line + 6400 4000 6600 4000 +$Comp +L d_and U13 +U 1 1 6851164F +P 4900 5900 +F 0 "U13" H 4900 5900 60 0000 C CNN +F 1 "d_and" H 4950 6000 60 0000 C CNN +F 2 "" H 4900 5900 60 0000 C CNN +F 3 "" H 4900 5900 60 0000 C CNN + 1 4900 5900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 68511655 +P 3300 5950 +F 0 "U3" H 3300 5850 60 0000 C CNN +F 1 "d_inverter" H 3300 6100 60 0000 C CNN +F 2 "" H 3350 5900 60 0000 C CNN +F 3 "" H 3350 5900 60 0000 C CNN + 1 3300 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6851165B +P 3400 6750 +F 0 "U7" H 3400 6650 60 0000 C CNN +F 1 "d_inverter" H 3400 6900 60 0000 C CNN +F 2 "" H 3450 6700 60 0000 C CNN +F 3 "" H 3450 6700 60 0000 C CNN + 1 3400 6750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 5700 4450 5700 +Wire Wire Line + 2850 5700 2850 5950 +Wire Wire Line + 2850 5950 3000 5950 +Connection ~ 2850 5700 +Wire Wire Line + 3600 5950 4050 5950 +Wire Wire Line + 2700 6550 4450 6550 +Wire Wire Line + 2900 6550 2900 6750 +Wire Wire Line + 2900 6750 3100 6750 +Connection ~ 2900 6550 +$Comp +L d_and U14 +U 1 1 6851166A +P 4900 6400 +F 0 "U14" H 4900 6400 60 0000 C CNN +F 1 "d_and" H 4950 6500 60 0000 C CNN +F 2 "" H 4900 6400 60 0000 C CNN +F 3 "" H 4900 6400 60 0000 C CNN + 1 4900 6400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 5700 4450 5800 +Wire Wire Line + 3700 6750 4250 6750 +Wire Wire Line + 4250 6750 4250 5900 +Wire Wire Line + 4250 5900 4450 5900 +Wire Wire Line + 4450 6550 4450 6400 +Wire Wire Line + 4050 5950 4050 6300 +Wire Wire Line + 4050 6300 4450 6300 +$Comp +L d_or U19 +U 1 1 68511677 +P 5950 6200 +F 0 "U19" H 5950 6200 60 0000 C CNN +F 1 "d_or" H 5950 6300 60 0000 C CNN +F 2 "" H 5950 6200 60 0000 C CNN +F 3 "" H 5950 6200 60 0000 C CNN + 1 5950 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 5850 5500 5850 +Wire Wire Line + 5500 5850 5500 6100 +Wire Wire Line + 5350 6350 5500 6350 +Wire Wire Line + 5500 6350 5500 6200 +Wire Wire Line + 6400 6150 6600 6150 +$Comp +L d_and U15 +U 1 1 68511803 +P 4950 7700 +F 0 "U15" H 4950 7700 60 0000 C CNN +F 1 "d_and" H 5000 7800 60 0000 C CNN +F 2 "" H 4950 7700 60 0000 C CNN +F 3 "" H 4950 7700 60 0000 C CNN + 1 4950 7700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68511809 +P 3350 7750 +F 0 "U4" H 3350 7650 60 0000 C CNN +F 1 "d_inverter" H 3350 7900 60 0000 C CNN +F 2 "" H 3400 7700 60 0000 C CNN +F 3 "" H 3400 7700 60 0000 C CNN + 1 3350 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6851180F +P 3450 8550 +F 0 "U8" H 3450 8450 60 0000 C CNN +F 1 "d_inverter" H 3450 8700 60 0000 C CNN +F 2 "" H 3500 8500 60 0000 C CNN +F 3 "" H 3500 8500 60 0000 C CNN + 1 3450 8550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2650 7500 4500 7500 +Wire Wire Line + 2900 7500 2900 7750 +Wire Wire Line + 2900 7750 3050 7750 +Connection ~ 2900 7500 +Wire Wire Line + 3650 7750 4100 7750 +Wire Wire Line + 2750 8350 4500 8350 +Wire Wire Line + 2950 8350 2950 8550 +Wire Wire Line + 2950 8550 3150 8550 +Connection ~ 2950 8350 +$Comp +L d_and U16 +U 1 1 6851181E +P 4950 8200 +F 0 "U16" H 4950 8200 60 0000 C CNN +F 1 "d_and" H 5000 8300 60 0000 C CNN +F 2 "" H 4950 8200 60 0000 C CNN +F 3 "" H 4950 8200 60 0000 C CNN + 1 4950 8200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4500 7500 4500 7600 +Wire Wire Line + 3750 8550 4300 8550 +Wire Wire Line + 4300 8550 4300 7700 +Wire Wire Line + 4300 7700 4500 7700 +Wire Wire Line + 4500 8350 4500 8200 +Wire Wire Line + 4100 7750 4100 8100 +Wire Wire Line + 4100 8100 4500 8100 +$Comp +L d_or U20 +U 1 1 6851182B +P 6000 8000 +F 0 "U20" H 6000 8000 60 0000 C CNN +F 1 "d_or" H 6000 8100 60 0000 C CNN +F 2 "" H 6000 8000 60 0000 C CNN +F 3 "" H 6000 8000 60 0000 C CNN + 1 6000 8000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5400 7650 5550 7650 +Wire Wire Line + 5550 7650 5550 7900 +Wire Wire Line + 5400 8150 5550 8150 +Wire Wire Line + 5550 8150 5550 8000 +Wire Wire Line + 6450 7950 6650 7950 +$Comp +L PORT U21 +U 1 1 68511928 +P 2350 1750 +F 0 "U21" H 2400 1850 30 0000 C CNN +F 1 "PORT" H 2350 1750 30 0000 C CNN +F 2 "" H 2350 1750 60 0000 C CNN +F 3 "" H 2350 1750 60 0000 C CNN + 1 2350 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U21 +U 2 1 68511A2C +P 2450 2600 +F 0 "U21" H 2500 2700 30 0000 C CNN +F 1 "PORT" H 2450 2600 30 0000 C CNN +F 2 "" H 2450 2600 60 0000 C CNN +F 3 "" H 2450 2600 60 0000 C CNN + 2 2450 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U21 +U 3 1 68511A9D +P 6850 2200 +F 0 "U21" H 6900 2300 30 0000 C CNN +F 1 "PORT" H 6850 2200 30 0000 C CNN +F 2 "" H 6850 2200 60 0000 C CNN +F 3 "" H 6850 2200 60 0000 C CNN + 3 6850 2200 + -1 0 0 -1 +$EndComp +$Comp +L PORT U21 +U 4 1 68511B22 +P 2350 3550 +F 0 "U21" H 2400 3650 30 0000 C CNN +F 1 "PORT" H 2350 3550 30 0000 C CNN +F 2 "" H 2350 3550 60 0000 C CNN +F 3 "" H 2350 3550 60 0000 C CNN + 4 2350 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U21 +U 5 1 68511BCB +P 2450 4400 +F 0 "U21" H 2500 4500 30 0000 C CNN +F 1 "PORT" H 2450 4400 30 0000 C CNN +F 2 "" H 2450 4400 60 0000 C CNN +F 3 "" H 2450 4400 60 0000 C CNN + 5 2450 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U21 +U 6 1 68511C60 +P 6850 4000 +F 0 "U21" H 6900 4100 30 0000 C CNN +F 1 "PORT" H 6850 4000 30 0000 C CNN +F 2 "" H 6850 4000 60 0000 C CNN +F 3 "" H 6850 4000 60 0000 C CNN + 6 6850 4000 + -1 0 0 1 +$EndComp +$Comp +L PORT U21 +U 7 1 68511D11 +P 7550 1800 +F 0 "U21" H 7600 1900 30 0000 C CNN +F 1 "PORT" H 7550 1800 30 0000 C CNN +F 2 "" H 7550 1800 60 0000 C CNN +F 3 "" H 7550 1800 60 0000 C CNN + 7 7550 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U21 +U 9 1 68511DB8 +P 2350 5700 +F 0 "U21" H 2400 5800 30 0000 C CNN +F 1 "PORT" H 2350 5700 30 0000 C CNN +F 2 "" H 2350 5700 60 0000 C CNN +F 3 "" H 2350 5700 60 0000 C CNN + 9 2350 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U21 +U 10 1 68511E53 +P 2450 6550 +F 0 "U21" H 2500 6650 30 0000 C CNN +F 1 "PORT" H 2450 6550 30 0000 C CNN +F 2 "" H 2450 6550 60 0000 C CNN +F 3 "" H 2450 6550 60 0000 C CNN + 10 2450 6550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U21 +U 11 1 68511EDA +P 6900 7950 +F 0 "U21" H 6950 8050 30 0000 C CNN +F 1 "PORT" H 6900 7950 30 0000 C CNN +F 2 "" H 6900 7950 60 0000 C CNN +F 3 "" H 6900 7950 60 0000 C CNN + 11 6900 7950 + -1 0 0 1 +$EndComp +$Comp +L PORT U21 +U 12 1 68511F91 +P 2400 7500 +F 0 "U21" H 2450 7600 30 0000 C CNN +F 1 "PORT" H 2400 7500 30 0000 C CNN +F 2 "" H 2400 7500 60 0000 C CNN +F 3 "" H 2400 7500 60 0000 C CNN + 12 2400 7500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U21 +U 13 1 6851204C +P 2500 8350 +F 0 "U21" H 2550 8450 30 0000 C CNN +F 1 "PORT" H 2500 8350 30 0000 C CNN +F 2 "" H 2500 8350 60 0000 C CNN +F 3 "" H 2500 8350 60 0000 C CNN + 13 2500 8350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U21 +U 14 1 68512105 +P 7500 2200 +F 0 "U21" H 7550 2300 30 0000 C CNN +F 1 "PORT" H 7500 2200 30 0000 C CNN +F 2 "" H 7500 2200 60 0000 C CNN +F 3 "" H 7500 2200 60 0000 C CNN + 14 7500 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U21 +U 8 1 685121D0 +P 6850 6150 +F 0 "U21" H 6900 6250 30 0000 C CNN +F 1 "PORT" H 6850 6150 30 0000 C CNN +F 2 "" H 6850 6150 60 0000 C CNN +F 3 "" H 6850 6150 60 0000 C CNN + 8 6850 6150 + -1 0 0 1 +$EndComp +NoConn ~ 7800 1800 +NoConn ~ 7750 2200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.sub b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.sub new file mode 100644 index 000000000..93f537428 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86.sub @@ -0,0 +1,86 @@ +* Subcircuit SN74ACT86 +.subckt SN74ACT86 net-_u1-pad1_ net-_u10-pad2_ net-_u17-pad3_ net-_u11-pad1_ net-_u12-pad2_ net-_u18-pad3_ ? net-_u19-pad3_ net-_u13-pad1_ net-_u14-pad2_ net-_u20-pad3_ net-_u15-pad1_ net-_u16-pad2_ ? +* c:\fossee\esim\library\subcircuitlibrary\sn74act86\sn74act86.cir +* u9 net-_u1-pad1_ net-_u5-pad2_ net-_u17-pad1_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u5 net-_u10-pad2_ net-_u5-pad2_ d_inverter +* u10 net-_u1-pad2_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u17 net-_u17-pad1_ net-_u10-pad3_ net-_u17-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u2 net-_u11-pad1_ net-_u12-pad1_ d_inverter +* u6 net-_u12-pad2_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u18-pad3_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u3 net-_u13-pad1_ net-_u14-pad1_ d_inverter +* u7 net-_u14-pad2_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and +* u19 net-_u13-pad3_ net-_u14-pad3_ net-_u19-pad3_ d_or +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and +* u4 net-_u15-pad1_ net-_u16-pad1_ d_inverter +* u8 net-_u16-pad2_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u20 net-_u15-pad3_ net-_u16-pad3_ net-_u20-pad3_ d_or +a1 [net-_u1-pad1_ net-_u5-pad2_ ] net-_u17-pad1_ u9 +a2 net-_u1-pad1_ net-_u1-pad2_ u1 +a3 net-_u10-pad2_ net-_u5-pad2_ u5 +a4 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a5 [net-_u17-pad1_ net-_u10-pad3_ ] net-_u17-pad3_ u17 +a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a7 net-_u11-pad1_ net-_u12-pad1_ u2 +a8 net-_u12-pad2_ net-_u11-pad2_ u6 +a9 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a10 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u18-pad3_ u18 +a11 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a12 net-_u13-pad1_ net-_u14-pad1_ u3 +a13 net-_u14-pad2_ net-_u13-pad2_ u7 +a14 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a15 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u19-pad3_ u19 +a16 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a17 net-_u15-pad1_ net-_u16-pad1_ u4 +a18 net-_u16-pad2_ net-_u15-pad2_ u8 +a19 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a20 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u20-pad3_ u20 +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74ACT86 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ACT86/SN74ACT86_Previous_Values.xml b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86_Previous_Values.xml new file mode 100644 index 000000000..8fecd3bcb --- /dev/null +++ b/library/SubcircuitLibrary/SN74ACT86/SN74ACT86_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_inverterd_inverterd_andd_ord_andd_inverterd_inverterd_andd_ord_andd_inverterd_inverterd_andd_ord_andd_inverterd_inverterd_andd_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ACT86/analysis b/library/SubcircuitLibrary/SN74ACT86/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ACT86/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From 9f40f24b2241261d41caa3e1e3fb38d186e92fbf Mon Sep 17 00:00:00 2001 From: TemshinaroJamir Date: Tue, 29 Jul 2025 00:01:54 +0530 Subject: [PATCH 2/2] Failed IC This folder contains the attempted implementation of the NJM4151, a precision monostable multivibrator IC. The goal was to simulate its timing characteristics and waveform behavior as part of the internship task. Despite multiple attempts, the simulation failed to produce accurate or expected output in the selected SPICE environment. Key issues encountered include: 1. Incorrect timing pulse generation 2. Unstable or non-triggering waveform behavior --- library/Failed IC/NJM4151/NJF.lib | 4 + library/Failed IC/NJM4151/NJM4151-cache.dcm | 3 + library/Failed IC/NJM4151/NJM4151-cache.lib | 171 ++ library/Failed IC/NJM4151/NJM4151.cir | 85 + library/Failed IC/NJM4151/NJM4151.cir.out | 95 + library/Failed IC/NJM4151/NJM4151.pro | 83 + library/Failed IC/NJM4151/NJM4151.sch | 1714 +++++++++++++++++ library/Failed IC/NJM4151/NJM4151.sub | 89 + .../NJM4151/NJM4151_Previous_Values.xml | 1 + library/Failed IC/NJM4151/NPN.lib | 4 + library/Failed IC/NJM4151/PNP.lib | 4 + library/Failed IC/NJM4151/analysis | 1 + library/Failed IC/NJM4151/njm4151.dcm | 3 + library/Failed IC/NJM4151/njm4151.lib | 24 + 14 files changed, 2281 insertions(+) create mode 100644 library/Failed IC/NJM4151/NJF.lib create mode 100644 library/Failed IC/NJM4151/NJM4151-cache.dcm create mode 100644 library/Failed IC/NJM4151/NJM4151-cache.lib create mode 100644 library/Failed IC/NJM4151/NJM4151.cir create mode 100644 library/Failed IC/NJM4151/NJM4151.cir.out create mode 100644 library/Failed IC/NJM4151/NJM4151.pro create mode 100644 library/Failed IC/NJM4151/NJM4151.sch create mode 100644 library/Failed IC/NJM4151/NJM4151.sub create mode 100644 library/Failed IC/NJM4151/NJM4151_Previous_Values.xml create mode 100644 library/Failed IC/NJM4151/NPN.lib create mode 100644 library/Failed IC/NJM4151/PNP.lib create mode 100644 library/Failed IC/NJM4151/analysis create mode 100644 library/Failed IC/NJM4151/njm4151.dcm create mode 100644 library/Failed IC/NJM4151/njm4151.lib diff --git a/library/Failed IC/NJM4151/NJF.lib b/library/Failed IC/NJM4151/NJF.lib new file mode 100644 index 000000000..dbb2cbae5 --- /dev/null +++ b/library/Failed IC/NJM4151/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/Failed IC/NJM4151/NJM4151-cache.dcm b/library/Failed IC/NJM4151/NJM4151-cache.dcm new file mode 100644 index 000000000..5f3ed79b7 --- /dev/null +++ b/library/Failed IC/NJM4151/NJM4151-cache.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/library/Failed IC/NJM4151/NJM4151-cache.lib b/library/Failed IC/NJM4151/NJM4151-cache.lib new file mode 100644 index 000000000..62527cc94 --- /dev/null +++ b/library/Failed IC/NJM4151/NJM4151-cache.lib @@ -0,0 +1,171 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# GNDPWR +# +DEF GNDPWR #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -200 50 H I C CNN +F1 "GNDPWR" 0 -130 50 H V C CNN +F2 "" 0 -50 50 H I C CNN +F3 "" 0 -50 50 H I C CNN +DRAW +P 2 0 1 0 0 -50 0 0 N +P 3 0 1 8 -40 -50 -50 -80 -50 -80 N +P 3 0 1 8 -20 -50 -30 -80 -30 -80 N +P 3 0 1 8 0 -50 -10 -80 -10 -80 N +P 3 0 1 8 20 -50 10 -80 10 -80 N +P 3 0 1 8 40 -50 -40 -50 -40 -50 N +P 4 0 1 8 40 -50 30 -80 30 -80 30 -80 N +X GNDPWR 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/Failed IC/NJM4151/NJM4151.cir b/library/Failed IC/NJM4151/NJM4151.cir new file mode 100644 index 000000000..08429f7bc --- /dev/null +++ b/library/Failed IC/NJM4151/NJM4151.cir @@ -0,0 +1,85 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\NJM4151\NJM4151.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/08/25 14:42:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q5 Net-_Q5-Pad1_ Net-_Q5-Pad1_ Net-_J1-Pad3_ eSim_PNP +Q6 Net-_Q6-Pad1_ Net-_Q10-Pad1_ Net-_Q5-Pad1_ eSim_PNP +Q8 Net-_Q10-Pad1_ Net-_Q5-Pad1_ Net-_J1-Pad3_ eSim_PNP +Q9 Net-_Q10-Pad1_ Net-_Q10-Pad3_ Net-_Q9-Pad3_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R1 Net-_Q10-Pad3_ Net-_Q9-Pad3_ 20k +R2 Net-_Q12-Pad3_ Net-_Q10-Pad2_ 10k +R3 Net-_Q10-Pad2_ Net-_Q13-Pad1_ 5k +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_Q13-Pad3_ eSim_NPN +Q14 Net-_Q14-Pad1_ Net-_Q14-Pad1_ GND eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q14-Pad1_ 20k +Q16 Net-_Q13-Pad1_ Net-_Q13-Pad3_ Net-_Q14-Pad1_ eSim_NPN +Q18 Net-_Q18-Pad1_ Net-_Q18-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q19 Net-_Q15-Pad1_ Net-_Q18-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q21 Net-_Q20-Pad2_ Net-_Q18-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q30 Net-_Q27-Pad1_ Net-_Q18-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q32 Net-_Q12-Pad2_ Net-_Q18-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q23 Net-_Q23-Pad1_ Net-_Q18-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q29 Net-_Q29-Pad1_ Net-_Q27-Pad1_ GND eSim_NPN +Q26 Net-_Q10-Pad2_ Net-_Q26-Pad2_ GND eSim_NPN +R7 Net-_Q26-Pad2_ Net-_Q23-Pad1_ 2k +Q27 Net-_Q27-Pad1_ Net-_Q27-Pad2_ GND eSim_NPN +R9 Net-_Q27-Pad2_ Net-_Q23-Pad1_ 2k +Q28 Net-_Q12-Pad2_ Net-_Q28-Pad2_ GND eSim_NPN +R8 Net-_Q28-Pad2_ Net-_Q23-Pad1_ 2k +Q25 Net-_Q23-Pad1_ Net-_Q25-Pad2_ GND eSim_NPN +R10 Net-_Q17-Pad1_ Net-_Q25-Pad2_ 2k +Q35 Net-_Q12-Pad2_ Net-_Q12-Pad2_ Net-_Q34-Pad2_ eSim_NPN +Q34 Net-_Q12-Pad2_ Net-_Q34-Pad2_ Net-_Q34-Pad3_ eSim_NPN +R12 Net-_Q34-Pad3_ Net-_Q34-Pad2_ 20k +U2 GNDPWR Net-_Q34-Pad3_ zener +Q37 Net-_Q17-Pad1_ Net-_Q18-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q40 Net-_Q31-Pad1_ Net-_Q18-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q42 Net-_Q38-Pad3_ Net-_Q18-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q45 Net-_Q24-Pad2_ Net-_Q18-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q47 Net-_Q18-Pad2_ Net-_Q47-Pad2_ GND eSim_NPN +Q46 Net-_J1-Pad3_ Net-_J1-Pad1_ Net-_Q46-Pad3_ eSim_NPN +Q50 Net-_Q47-Pad2_ Net-_J1-Pad1_ Net-_Q46-Pad3_ eSim_NPN +R13 Net-_Q46-Pad3_ GND 12k +U3 GND Net-_J1-Pad1_ zener +J1 Net-_J1-Pad1_ GND Net-_J1-Pad3_ jfet_n +Q1 GND Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q4 GND Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_PNP +Q7 Net-_Q11-Pad2_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q15 Net-_Q15-Pad1_ Net-_Q11-Pad1_ Net-_Q11-Pad3_ eSim_NPN +Q17 Net-_Q17-Pad1_ Net-_Q17-Pad2_ Net-_Q11-Pad3_ eSim_NPN +R5 Net-_Q15-Pad1_ Net-_Q17-Pad2_ 2k +Q20 Net-_Q15-Pad1_ Net-_Q20-Pad2_ Net-_Q11-Pad3_ eSim_NPN +R6 Net-_Q15-Pad1_ Net-_Q22-Pad2_ 2k +Q22 Net-_Q20-Pad2_ Net-_Q22-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q24 Net-_Q20-Pad2_ Net-_Q24-Pad2_ Net-_Q11-Pad3_ eSim_NPN +R11 Net-_Q17-Pad1_ Net-_Q31-Pad2_ 2k +Q31 Net-_Q31-Pad1_ Net-_Q31-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q33 Net-_Q33-Pad1_ Net-_Q31-Pad1_ Net-_Q11-Pad3_ eSim_NPN +Q36 GNDPWR Net-_Q33-Pad1_ Net-_Q36-Pad3_ eSim_PNP +Q38 GND Net-_Q36-Pad3_ Net-_Q38-Pad3_ eSim_PNP +Q39 Net-_Q39-Pad1_ Net-_Q39-Pad1_ Net-_Q11-Pad3_ eSim_NPN +Q41 Net-_Q41-Pad1_ Net-_Q39-Pad1_ Net-_Q11-Pad3_ eSim_NPN +Q44 Net-_Q24-Pad2_ Net-_Q41-Pad1_ Net-_Q11-Pad3_ eSim_NPN +Q48 Net-_Q11-Pad3_ Net-_Q48-Pad2_ Net-_Q48-Pad3_ eSim_PNP +R14 Net-_J1-Pad3_ Net-_Q48-Pad2_ 100 +R15 Net-_Q48-Pad2_ Net-_R15-Pad2_ 100 +R16 Net-_R15-Pad2_ Net-_Q11-Pad3_ 100 +U1 Net-_Q6-Pad1_ Net-_Q9-Pad3_ Net-_Q29-Pad1_ Net-_Q11-Pad3_ Net-_Q33-Pad1_ Net-_Q4-Pad2_ Net-_Q1-Pad2_ Net-_J1-Pad3_ PORT +Q12 Net-_J1-Pad3_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +Q51 Net-_Q41-Pad1_ Net-_Q36-Pad3_ Net-_Q38-Pad3_ eSim_PNP +Q52 Net-_Q39-Pad1_ Net-_Q48-Pad3_ Net-_Q38-Pad3_ eSim_PNP +Q53 Net-_Q48-Pad3_ Net-_Q48-Pad3_ Net-_Q38-Pad3_ eSim_PNP +Q54 Net-_Q47-Pad2_ Net-_Q18-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q55 Net-_J1-Pad1_ Net-_Q18-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q2 Net-_Q1-Pad3_ Net-_Q1-Pad3_ Net-_Q18-Pad1_ eSim_PNP +Q3 Net-_Q11-Pad2_ Net-_Q1-Pad3_ Net-_Q18-Pad1_ eSim_PNP +Q49 Net-_Q4-Pad3_ Net-_Q4-Pad3_ Net-_Q18-Pad1_ eSim_PNP +Q43 Net-_Q11-Pad1_ Net-_Q4-Pad3_ Net-_Q18-Pad1_ eSim_PNP + +.end diff --git a/library/Failed IC/NJM4151/NJM4151.cir.out b/library/Failed IC/NJM4151/NJM4151.cir.out new file mode 100644 index 000000000..f8e157e8a --- /dev/null +++ b/library/Failed IC/NJM4151/NJM4151.cir.out @@ -0,0 +1,95 @@ +* d:\fossee\esim\library\subcircuitlibrary\njm4151\njm4151.cir + +.include NJF.lib +.include NPN.lib +.include PNP.lib +q5 net-_q5-pad1_ net-_q5-pad1_ net-_j1-pad3_ Q2N2907A +q6 net-_q6-pad1_ net-_q10-pad1_ net-_q5-pad1_ Q2N2907A +q8 net-_q10-pad1_ net-_q5-pad1_ net-_j1-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q10-pad3_ net-_q9-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +r1 net-_q10-pad3_ net-_q9-pad3_ 20k +r2 net-_q12-pad3_ net-_q10-pad2_ 10k +r3 net-_q10-pad2_ net-_q13-pad1_ 5k +q13 net-_q13-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222 +q14 net-_q14-pad1_ net-_q14-pad1_ gnd Q2N2222 +r4 net-_q13-pad3_ net-_q14-pad1_ 20k +q16 net-_q13-pad1_ net-_q13-pad3_ net-_q14-pad1_ Q2N2222 +q18 net-_q18-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q19 net-_q15-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q21 net-_q20-pad2_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q30 net-_q27-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q32 net-_q12-pad2_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q23 net-_q23-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q29 net-_q29-pad1_ net-_q27-pad1_ gnd Q2N2222 +q26 net-_q10-pad2_ net-_q26-pad2_ gnd Q2N2222 +r7 net-_q26-pad2_ net-_q23-pad1_ 2k +q27 net-_q27-pad1_ net-_q27-pad2_ gnd Q2N2222 +r9 net-_q27-pad2_ net-_q23-pad1_ 2k +q28 net-_q12-pad2_ net-_q28-pad2_ gnd Q2N2222 +r8 net-_q28-pad2_ net-_q23-pad1_ 2k +q25 net-_q23-pad1_ net-_q25-pad2_ gnd Q2N2222 +r10 net-_q17-pad1_ net-_q25-pad2_ 2k +q35 net-_q12-pad2_ net-_q12-pad2_ net-_q34-pad2_ Q2N2222 +q34 net-_q12-pad2_ net-_q34-pad2_ net-_q34-pad3_ Q2N2222 +r12 net-_q34-pad3_ net-_q34-pad2_ 20k +* u2 gndpwr net-_q34-pad3_ zener +q37 net-_q17-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q40 net-_q31-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q42 net-_q38-pad3_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q45 net-_q24-pad2_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q47 net-_q18-pad2_ net-_q47-pad2_ gnd Q2N2222 +q46 net-_j1-pad3_ net-_j1-pad1_ net-_q46-pad3_ Q2N2222 +q50 net-_q47-pad2_ net-_j1-pad1_ net-_q46-pad3_ Q2N2222 +r13 net-_q46-pad3_ gnd 12k +* u3 gnd net-_j1-pad1_ zener +j1 net-_j1-pad1_ gnd net-_j1-pad3_ J2N3819 +q1 gnd net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q4 gnd net-_q4-pad2_ net-_q4-pad3_ Q2N2907A +q7 net-_q11-pad2_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q15 net-_q15-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2222 +q17 net-_q17-pad1_ net-_q17-pad2_ net-_q11-pad3_ Q2N2222 +r5 net-_q15-pad1_ net-_q17-pad2_ 2k +q20 net-_q15-pad1_ net-_q20-pad2_ net-_q11-pad3_ Q2N2222 +r6 net-_q15-pad1_ net-_q22-pad2_ 2k +q22 net-_q20-pad2_ net-_q22-pad2_ net-_q11-pad3_ Q2N2222 +q24 net-_q20-pad2_ net-_q24-pad2_ net-_q11-pad3_ Q2N2222 +r11 net-_q17-pad1_ net-_q31-pad2_ 2k +q31 net-_q31-pad1_ net-_q31-pad2_ net-_q11-pad3_ Q2N2222 +q33 net-_q33-pad1_ net-_q31-pad1_ net-_q11-pad3_ Q2N2222 +q36 gndpwr net-_q33-pad1_ net-_q36-pad3_ Q2N2907A +q38 gnd net-_q36-pad3_ net-_q38-pad3_ Q2N2907A +q39 net-_q39-pad1_ net-_q39-pad1_ net-_q11-pad3_ Q2N2222 +q41 net-_q41-pad1_ net-_q39-pad1_ net-_q11-pad3_ Q2N2222 +q44 net-_q24-pad2_ net-_q41-pad1_ net-_q11-pad3_ Q2N2222 +q48 net-_q11-pad3_ net-_q48-pad2_ net-_q48-pad3_ Q2N2907A +r14 net-_j1-pad3_ net-_q48-pad2_ 100 +r15 net-_q48-pad2_ net-_r15-pad2_ 100 +r16 net-_r15-pad2_ net-_q11-pad3_ 100 +* u1 net-_q6-pad1_ net-_q9-pad3_ net-_q29-pad1_ net-_q11-pad3_ net-_q33-pad1_ net-_q4-pad2_ net-_q1-pad2_ net-_j1-pad3_ port +q12 net-_j1-pad3_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +q51 net-_q41-pad1_ net-_q36-pad3_ net-_q38-pad3_ Q2N2907A +q52 net-_q39-pad1_ net-_q48-pad3_ net-_q38-pad3_ Q2N2907A +q53 net-_q48-pad3_ net-_q48-pad3_ net-_q38-pad3_ Q2N2907A +q54 net-_q47-pad2_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q55 net-_j1-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q2 net-_q1-pad3_ net-_q1-pad3_ net-_q18-pad1_ Q2N2907A +q3 net-_q11-pad2_ net-_q1-pad3_ net-_q18-pad1_ Q2N2907A +q49 net-_q4-pad3_ net-_q4-pad3_ net-_q18-pad1_ Q2N2907A +q43 net-_q11-pad1_ net-_q4-pad3_ net-_q18-pad1_ Q2N2907A +a1 gndpwr net-_q34-pad3_ u2 +a2 gnd net-_j1-pad1_ u3 +* Schematic Name: zener, Ngspice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/Failed IC/NJM4151/NJM4151.pro b/library/Failed IC/NJM4151/NJM4151.pro new file mode 100644 index 000000000..21856e2e4 --- /dev/null +++ b/library/Failed IC/NJM4151/NJM4151.pro @@ -0,0 +1,83 @@ +update=06/03/25 10:30:42 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/Failed IC/NJM4151/NJM4151.sch b/library/Failed IC/NJM4151/NJM4151.sch new file mode 100644 index 000000000..954037fbf --- /dev/null +++ b/library/Failed IC/NJM4151/NJM4151.sch @@ -0,0 +1,1714 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:NJM4151-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q5 +U 1 1 68383839 +P 2200 2450 +F 0 "Q5" H 2100 2500 50 0000 R CNN +F 1 "eSim_PNP" H 2150 2600 50 0000 R CNN +F 2 "" H 2400 2550 29 0000 C CNN +F 3 "" H 2200 2450 60 0000 C CNN + 1 2200 2450 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 6838390B +P 2200 3000 +F 0 "Q6" H 2100 3050 50 0000 R CNN +F 1 "eSim_PNP" H 2150 3150 50 0000 R CNN +F 2 "" H 2400 3100 29 0000 C CNN +F 3 "" H 2200 3000 60 0000 C CNN + 1 2200 3000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 68383937 +P 3000 2450 +F 0 "Q8" H 2900 2500 50 0000 R CNN +F 1 "eSim_PNP" H 2950 2600 50 0000 R CNN +F 2 "" H 3200 2550 29 0000 C CNN +F 3 "" H 3000 2450 60 0000 C CNN + 1 3000 2450 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 68383977 +P 3200 3700 +F 0 "Q9" H 3100 3750 50 0000 R CNN +F 1 "eSim_NPN" H 3150 3850 50 0000 R CNN +F 2 "" H 3400 3800 29 0000 C CNN +F 3 "" H 3200 3700 60 0000 C CNN + 1 3200 3700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 68383A00 +P 3550 3200 +F 0 "Q10" H 3450 3250 50 0000 R CNN +F 1 "eSim_NPN" H 3500 3350 50 0000 R CNN +F 2 "" H 3750 3300 29 0000 C CNN +F 3 "" H 3550 3200 60 0000 C CNN + 1 3550 3200 + -1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 68383C6A +P 3400 3900 +F 0 "R1" H 3450 4030 50 0000 C CNN +F 1 "20k" H 3450 3850 50 0000 C CNN +F 2 "" H 3450 3880 30 0000 C CNN +F 3 "" V 3450 3950 30 0000 C CNN + 1 3400 3900 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 68383DCF +P 4050 2850 +F 0 "R2" H 4100 2980 50 0000 C CNN +F 1 "10k" H 4100 2800 50 0000 C CNN +F 2 "" H 4100 2830 30 0000 C CNN +F 3 "" V 4100 2900 30 0000 C CNN + 1 4050 2850 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 68383EC7 +P 4050 3400 +F 0 "R3" H 4100 3530 50 0000 C CNN +F 1 "5k" H 4100 3350 50 0000 C CNN +F 2 "" H 4100 3380 30 0000 C CNN +F 3 "" V 4100 3450 30 0000 C CNN + 1 4050 3400 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 68383F3E +P 4200 3950 +F 0 "Q13" H 4100 4000 50 0000 R CNN +F 1 "eSim_NPN" H 4150 4100 50 0000 R CNN +F 2 "" H 4400 4050 29 0000 C CNN +F 3 "" H 4200 3950 60 0000 C CNN + 1 4200 3950 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 68384020 +P 4200 5000 +F 0 "Q14" H 4100 5050 50 0000 R CNN +F 1 "eSim_NPN" H 4150 5150 50 0000 R CNN +F 2 "" H 4400 5100 29 0000 C CNN +F 3 "" H 4200 5000 60 0000 C CNN + 1 4200 5000 + -1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 68384082 +P 4050 4500 +F 0 "R4" H 4100 4630 50 0000 C CNN +F 1 "20k" H 4100 4450 50 0000 C CNN +F 2 "" H 4100 4480 30 0000 C CNN +F 3 "" V 4100 4550 30 0000 C CNN + 1 4050 4500 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 6838421D +P 4650 4250 +F 0 "Q16" H 4550 4300 50 0000 R CNN +F 1 "eSim_NPN" H 4600 4400 50 0000 R CNN +F 2 "" H 4850 4350 29 0000 C CNN +F 3 "" H 4650 4250 60 0000 C CNN + 1 4650 4250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q18 +U 1 1 68384C21 +P 5500 2450 +F 0 "Q18" H 5400 2500 50 0000 R CNN +F 1 "eSim_PNP" H 5450 2600 50 0000 R CNN +F 2 "" H 5700 2550 29 0000 C CNN +F 3 "" H 5500 2450 60 0000 C CNN + 1 5500 2450 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q19 +U 1 1 68384C75 +P 6100 2450 +F 0 "Q19" H 6000 2500 50 0000 R CNN +F 1 "eSim_PNP" H 6050 2600 50 0000 R CNN +F 2 "" H 6300 2550 29 0000 C CNN +F 3 "" H 6100 2450 60 0000 C CNN + 1 6100 2450 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q21 +U 1 1 68384CCC +P 6750 2450 +F 0 "Q21" H 6650 2500 50 0000 R CNN +F 1 "eSim_PNP" H 6700 2600 50 0000 R CNN +F 2 "" H 6950 2550 29 0000 C CNN +F 3 "" H 6750 2450 60 0000 C CNN + 1 6750 2450 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q30 +U 1 1 68385317 +P 8500 2450 +F 0 "Q30" H 8400 2500 50 0000 R CNN +F 1 "eSim_PNP" H 8450 2600 50 0000 R CNN +F 2 "" H 8700 2550 29 0000 C CNN +F 3 "" H 8500 2450 60 0000 C CNN + 1 8500 2450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q32 +U 1 1 683853EB +P 9200 2450 +F 0 "Q32" H 9100 2500 50 0000 R CNN +F 1 "eSim_PNP" H 9150 2600 50 0000 R CNN +F 2 "" H 9400 2550 29 0000 C CNN +F 3 "" H 9200 2450 60 0000 C CNN + 1 9200 2450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q23 +U 1 1 683862ED +P 7500 2450 +F 0 "Q23" H 7400 2500 50 0000 R CNN +F 1 "eSim_PNP" H 7450 2600 50 0000 R CNN +F 2 "" H 7700 2550 29 0000 C CNN +F 3 "" H 7500 2450 60 0000 C CNN + 1 7500 2450 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q29 +U 1 1 68386720 +P 8400 3050 +F 0 "Q29" H 8300 3100 50 0000 R CNN +F 1 "eSim_NPN" H 8350 3200 50 0000 R CNN +F 2 "" H 8600 3150 29 0000 C CNN +F 3 "" H 8400 3050 60 0000 C CNN + 1 8400 3050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q26 +U 1 1 68386A28 +P 8300 3850 +F 0 "Q26" H 8200 3900 50 0000 R CNN +F 1 "eSim_NPN" H 8250 4000 50 0000 R CNN +F 2 "" H 8500 3950 29 0000 C CNN +F 3 "" H 8300 3850 60 0000 C CNN + 1 8300 3850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 68386CB7 +P 7850 3800 +F 0 "R7" H 7900 3930 50 0000 C CNN +F 1 "2k" H 7900 3750 50 0000 C CNN +F 2 "" H 7900 3780 30 0000 C CNN +F 3 "" V 7900 3850 30 0000 C CNN + 1 7850 3800 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q27 +U 1 1 68386F68 +P 8300 4700 +F 0 "Q27" H 8200 4750 50 0000 R CNN +F 1 "eSim_NPN" H 8250 4850 50 0000 R CNN +F 2 "" H 8500 4800 29 0000 C CNN +F 3 "" H 8300 4700 60 0000 C CNN + 1 8300 4700 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 683871A7 +P 7900 4650 +F 0 "R9" H 7950 4780 50 0000 C CNN +F 1 "2k" H 7950 4600 50 0000 C CNN +F 2 "" H 7950 4630 30 0000 C CNN +F 3 "" V 7950 4700 30 0000 C CNN + 1 7900 4650 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q28 +U 1 1 683872F6 +P 8300 5600 +F 0 "Q28" H 8200 5650 50 0000 R CNN +F 1 "eSim_NPN" H 8250 5750 50 0000 R CNN +F 2 "" H 8500 5700 29 0000 C CNN +F 3 "" H 8300 5600 60 0000 C CNN + 1 8300 5600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R8 +U 1 1 6838736F +P 7850 5550 +F 0 "R8" H 7900 5680 50 0000 C CNN +F 1 "2k" H 7900 5500 50 0000 C CNN +F 2 "" H 7900 5530 30 0000 C CNN +F 3 "" V 7900 5600 30 0000 C CNN + 1 7850 5550 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q25 +U 1 1 68387747 +P 7800 6350 +F 0 "Q25" H 7700 6400 50 0000 R CNN +F 1 "eSim_NPN" H 7750 6500 50 0000 R CNN +F 2 "" H 8000 6450 29 0000 C CNN +F 3 "" H 7800 6350 60 0000 C CNN + 1 7800 6350 + -1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 68387938 +P 8350 6300 +F 0 "R10" H 8400 6430 50 0000 C CNN +F 1 "2k" H 8400 6250 50 0000 C CNN +F 2 "" H 8400 6280 30 0000 C CNN +F 3 "" V 8400 6350 30 0000 C CNN + 1 8350 6300 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q35 +U 1 1 68387B71 +P 9750 3100 +F 0 "Q35" H 9650 3150 50 0000 R CNN +F 1 "eSim_NPN" H 9700 3250 50 0000 R CNN +F 2 "" H 9950 3200 29 0000 C CNN +F 3 "" H 9750 3100 60 0000 C CNN + 1 9750 3100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q34 +U 1 1 68387EE7 +P 9650 3600 +F 0 "Q34" H 9550 3650 50 0000 R CNN +F 1 "eSim_NPN" H 9600 3750 50 0000 R CNN +F 2 "" H 9850 3700 29 0000 C CNN +F 3 "" H 9650 3600 60 0000 C CNN + 1 9650 3600 + -1 0 0 -1 +$EndComp +$Comp +L resistor R12 +U 1 1 683880D3 +P 9900 3900 +F 0 "R12" H 9950 4030 50 0000 C CNN +F 1 "20k" H 9950 3850 50 0000 C CNN +F 2 "" H 9950 3880 30 0000 C CNN +F 3 "" V 9950 3950 30 0000 C CNN + 1 9900 3900 + 0 -1 -1 0 +$EndComp +$Comp +L zener U2 +U 1 1 683882F4 +P 9850 4550 +F 0 "U2" H 9800 4450 60 0000 C CNN +F 1 "zener" H 9850 4650 60 0000 C CNN +F 2 "" H 9900 4550 60 0000 C CNN +F 3 "" H 9900 4550 60 0000 C CNN + 1 9850 4550 + 0 1 -1 0 +$EndComp +$Comp +L eSim_PNP Q37 +U 1 1 68388FCB +P 11000 2450 +F 0 "Q37" H 10900 2500 50 0000 R CNN +F 1 "eSim_PNP" H 10950 2600 50 0000 R CNN +F 2 "" H 11200 2550 29 0000 C CNN +F 3 "" H 11000 2450 60 0000 C CNN + 1 11000 2450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q40 +U 1 1 683890CD +P 11750 2450 +F 0 "Q40" H 11650 2500 50 0000 R CNN +F 1 "eSim_PNP" H 11700 2600 50 0000 R CNN +F 2 "" H 11950 2550 29 0000 C CNN +F 3 "" H 11750 2450 60 0000 C CNN + 1 11750 2450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q42 +U 1 1 68389167 +P 12500 2450 +F 0 "Q42" H 12400 2500 50 0000 R CNN +F 1 "eSim_PNP" H 12450 2600 50 0000 R CNN +F 2 "" H 12700 2550 29 0000 C CNN +F 3 "" H 12500 2450 60 0000 C CNN + 1 12500 2450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q45 +U 1 1 683892D1 +P 13150 2450 +F 0 "Q45" H 13050 2500 50 0000 R CNN +F 1 "eSim_PNP" H 13100 2600 50 0000 R CNN +F 2 "" H 13350 2550 29 0000 C CNN +F 3 "" H 13150 2450 60 0000 C CNN + 1 13150 2450 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q47 +U 1 1 6838A1C7 +P 13650 3050 +F 0 "Q47" H 13550 3100 50 0000 R CNN +F 1 "eSim_NPN" H 13600 3200 50 0000 R CNN +F 2 "" H 13850 3150 29 0000 C CNN +F 3 "" H 13650 3050 60 0000 C CNN + 1 13650 3050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q46 +U 1 1 6838A8ED +P 13450 4050 +F 0 "Q46" H 13350 4100 50 0000 R CNN +F 1 "eSim_NPN" H 13400 4200 50 0000 R CNN +F 2 "" H 13650 4150 29 0000 C CNN +F 3 "" H 13450 4050 60 0000 C CNN + 1 13450 4050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q50 +U 1 1 6838AAEB +P 14300 4050 +F 0 "Q50" H 14200 4100 50 0000 R CNN +F 1 "eSim_NPN" H 14250 4200 50 0000 R CNN +F 2 "" H 14500 4150 29 0000 C CNN +F 3 "" H 14300 4050 60 0000 C CNN + 1 14300 4050 + -1 0 0 -1 +$EndComp +$Comp +L resistor R13 +U 1 1 6838AD8C +P 14150 4750 +F 0 "R13" H 14200 4880 50 0000 C CNN +F 1 "12k" H 14200 4700 50 0000 C CNN +F 2 "" H 14200 4730 30 0000 C CNN +F 3 "" V 14200 4800 30 0000 C CNN + 1 14150 4750 + 0 1 1 0 +$EndComp +$Comp +L zener U3 +U 1 1 6838B0EF +P 14800 4600 +F 0 "U3" H 14750 4500 60 0000 C CNN +F 1 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Wire Line + 3450 3700 3400 3700 +Wire Wire Line + 7800 8650 8000 8650 +Wire Wire Line + 8000 8650 8000 9700 +Wire Wire Line + 8000 9700 13250 9700 +Wire Wire Line + 4400 3950 4750 3950 +Wire Wire Line + 14800 5050 14800 4800 +Wire Wire Line + 4100 3700 4750 3700 +Wire Wire Line + 4750 4750 4100 4750 +Connection ~ 4100 4750 +Wire Wire Line + 5550 7000 8550 7000 +Wire Wire Line + 10400 6350 10400 2800 +Connection ~ 8550 6350 +Wire Wire Line + 8150 2900 7900 2900 +Wire Wire Line + 15650 7250 14350 7250 +Wire Wire Line + 14350 7250 14350 7400 +Wire Wire Line + 1800 6200 1950 6200 +Wire Wire Line + 1950 6200 1950 6800 +Wire Wire Line + 1950 6550 2100 6550 +Wire Wire Line + 2400 6750 2400 6800 +Wire Wire Line + 2400 6800 1950 6800 +Connection ~ 1950 6550 +Wire Wire Line + 2550 6550 2600 6550 +Wire Wire Line + 2400 6350 2400 6300 +Wire Wire Line + 2400 6300 2900 6300 +Wire Wire Line + 2900 6300 2900 6350 +Wire Wire Line + 2600 6300 2600 6150 +Connection ~ 2600 6300 +Wire Wire Line + 2900 6750 2900 8000 +Wire Wire Line + 2900 8000 2550 8000 +Wire Wire Line + 4900 6600 5000 6600 +Wire Wire Line + 5000 6300 5000 6900 +Wire Wire Line + 5000 6300 5150 6300 +Wire Wire Line + 4600 6800 4600 6900 +Wire Wire Line + 4600 6900 5000 6900 +Connection ~ 5000 6600 +Wire Wire Line + 4350 6400 4350 6600 +Wire Wire Line + 4900 6400 4900 6600 +Wire Wire Line + 4600 6300 4600 6400 +Wire Wire Line + 4050 6300 4600 6300 +Wire Wire Line + 4050 6300 4050 6400 +Wire Wire Line + 4350 6150 4350 6300 +Connection ~ 4350 6300 +Wire Wire Line + 4050 6800 4050 7850 +Wire Wire Line + 4050 7850 3650 7850 +Wire Wire Line + 3650 7850 3650 8150 +Wire Wire Line + 10000 7700 10800 7700 +Wire Wire Line + 11100 7900 11100 8050 +Wire Wire Line + 11100 7500 11100 7350 +Wire Wire Line + 11100 7350 11550 7350 +Wire Wire Line + 11550 7350 11550 7500 +Wire Wire Line + 10600 7700 10600 7450 +Wire Wire Line + 10600 7450 11250 7450 +Wire Wire Line + 11250 7450 11250 7700 +Connection ~ 10600 7700 +Wire Wire Line + 11550 7900 11750 7900 +Wire Wire Line + 11750 7900 11750 8050 +Wire Wire Line + 11350 7350 11350 7200 +Wire Wire Line + 11350 7200 12600 7200 +Connection ~ 11950 7200 +Connection ~ 11350 7350 +Wire Wire Line + 11950 7200 11950 3400 +Wire Wire Line + 12350 7450 12350 7350 +Wire Wire Line + 12350 7350 12850 7350 +Wire Wire Line + 12850 7350 12850 7450 +Wire Wire Line + 12600 7200 12600 7350 +Connection ~ 12600 7350 +Wire Wire Line + 13150 7650 13700 7650 +Wire Wire Line + 12850 7850 13350 7850 +Wire Wire Line + 13350 7850 13350 7650 +Connection ~ 13350 7650 +Wire Wire Line + 12650 7400 12650 7650 +Wire Wire Line + 13200 7400 13200 7650 +Connection ~ 13200 7650 +Wire Wire Line + 12350 7850 12050 7850 +Wire Wire Line + 12050 7850 12050 8100 +Wire Wire Line + 14050 2250 14050 2200 +Wire Wire Line + 14050 2200 14600 2200 +Wire Wire Line + 14600 2200 14600 2250 +Wire Wire Line + 14300 2200 14300 2050 +Connection ~ 14300 2050 +Connection ~ 14300 2200 +Wire Wire Line + 14050 2650 14200 2650 +Wire Wire Line + 14200 2650 14200 3850 +Wire Wire Line + 13700 2450 13700 2250 +Wire Wire Line + 14300 2250 14300 2450 +Connection ~ 13700 2450 +Wire Wire Line + 14600 2650 14800 2650 +Wire Wire Line + 12950 2450 13750 2450 +Wire Wire Line + 13700 2250 14300 2250 +Wire Wire Line + 14500 4050 14950 4050 +Wire Wire Line + 13650 4050 14800 4050 +Wire Wire Line + 12650 7400 13200 7400 +Wire Wire Line + 4350 6400 4900 6400 +Wire Wire Line + 2550 6550 2550 6350 +Wire Wire Line + 2550 6350 2100 6350 +Wire Wire Line + 2100 6350 2100 6550 +Wire Wire Line + 5700 2450 5700 2250 +Wire Wire Line + 5700 2250 12950 2250 +Wire Wire Line + 12950 2250 12950 2450 +Wire Wire Line + 6300 2250 6300 2450 +Connection ~ 6300 2250 +Wire Wire Line + 6950 2450 6950 2250 +Connection ~ 6950 2250 +Wire Wire Line + 7700 2450 7700 2250 +Connection ~ 7700 2250 +Wire Wire Line + 8300 2450 8300 2250 +Connection ~ 8300 2250 +Wire Wire Line + 9000 2450 9000 2250 +Connection ~ 9000 2250 +Wire Wire Line + 10800 2450 10800 2250 +Connection ~ 10800 2250 +Wire Wire Line + 11550 2450 11550 2250 +Connection ~ 11550 2250 +Wire Wire Line + 12300 2450 12200 2450 +Wire Wire Line + 12200 2450 12200 2250 +Connection ~ 12200 2250 +$Comp +L eSim_PNP Q2 +U 1 1 6843288F +P 2300 6550 +F 0 "Q2" H 2200 6600 50 0000 R CNN +F 1 "eSim_PNP" H 2250 6700 50 0000 R CNN +F 2 "" H 2500 6650 29 0000 C CNN +F 3 "" H 2300 6550 60 0000 C CNN + 1 2300 6550 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 6843299E +P 2800 6550 +F 0 "Q3" H 2700 6600 50 0000 R CNN +F 1 "eSim_PNP" H 2750 6700 50 0000 R CNN +F 2 "" H 3000 6650 29 0000 C CNN +F 3 "" H 2800 6550 60 0000 C CNN + 1 2800 6550 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q49 +U 1 1 68433E88 +P 4700 6600 +F 0 "Q49" H 4600 6650 50 0000 R CNN +F 1 "eSim_PNP" H 4650 6750 50 0000 R CNN +F 2 "" H 4900 6700 29 0000 C CNN +F 3 "" H 4700 6600 60 0000 C CNN + 1 4700 6600 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q43 +U 1 1 68433F9B +P 4150 6600 +F 0 "Q43" H 4050 6650 50 0000 R CNN +F 1 "eSim_PNP" H 4100 6750 50 0000 R CNN +F 2 "" H 4350 6700 29 0000 C CNN +F 3 "" H 4150 6600 60 0000 C CNN + 1 4150 6600 + -1 0 0 1 +$EndComp +Connection ~ 14800 5050 +$Comp +L GNDPWR #PWR01 +U 1 1 684504E2 +P 9850 4900 +F 0 "#PWR01" H 9850 4700 50 0001 C CNN +F 1 "GNDPWR" H 9850 4770 50 0000 C CNN +F 2 "" H 9850 4850 50 0001 C CNN +F 3 "" H 9850 4850 50 0001 C CNN + 1 9850 4900 + 1 0 0 -1 +$EndComp +$Comp +L GNDPWR #PWR02 +U 1 1 6845545C +P 10000 8300 +F 0 "#PWR02" H 10000 8100 50 0001 C CNN +F 1 "GNDPWR" H 10000 8170 50 0000 C CNN +F 2 "" H 10000 8250 50 0001 C CNN +F 3 "" H 10000 8250 50 0001 C CNN + 1 10000 8300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4100 5200 4100 5250 +Connection ~ 15650 2050 +Connection ~ 15400 2050 +Wire Wire Line + 15650 2050 15650 7250 +$Comp +L GND #PWR03 +U 1 1 686D0623 +P 4100 5250 +F 0 "#PWR03" H 4100 5000 50 0001 C CNN +F 1 "GND" H 4100 5100 50 0000 C CNN +F 2 "" H 4100 5250 50 0001 C CNN +F 3 "" H 4100 5250 50 0001 C CNN + 1 4100 5250 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 686D1E91 +P 8300 3250 +F 0 "#PWR04" H 8300 3000 50 0001 C CNN +F 1 "GND" H 8300 3100 50 0000 C CNN +F 2 "" H 8300 3250 50 0001 C CNN +F 3 "" H 8300 3250 50 0001 C CNN + 1 8300 3250 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 686D1FED +P 8400 4050 +F 0 "#PWR05" H 8400 3800 50 0001 C CNN +F 1 "GND" H 8400 3900 50 0000 C CNN +F 2 "" H 8400 4050 50 0001 C CNN +F 3 "" H 8400 4050 50 0001 C CNN + 1 8400 4050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR06 +U 1 1 686D2424 +P 8400 4900 +F 0 "#PWR06" H 8400 4650 50 0001 C CNN +F 1 "GND" H 8400 4750 50 0000 C CNN +F 2 "" H 8400 4900 50 0001 C CNN +F 3 "" H 8400 4900 50 0001 C CNN + 1 8400 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR07 +U 1 1 686D27B9 +P 8400 5800 +F 0 "#PWR07" H 8400 5550 50 0001 C CNN +F 1 "GND" H 8400 5650 50 0000 C CNN +F 2 "" H 8400 5800 50 0001 C CNN +F 3 "" H 8400 5800 50 0001 C CNN + 1 8400 5800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR08 +U 1 1 686D2960 +P 7700 6550 +F 0 "#PWR08" H 7700 6300 50 0001 C CNN +F 1 "GND" H 7700 6400 50 0000 C CNN +F 2 "" H 7700 6550 50 0001 C CNN +F 3 "" H 7700 6550 50 0001 C CNN + 1 7700 6550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR09 +U 1 1 686D3215 +P 13550 3250 +F 0 "#PWR09" H 13550 3000 50 0001 C CNN +F 1 "GND" H 13550 3100 50 0000 C CNN +F 2 "" H 13550 3250 50 0001 C CNN +F 3 "" H 13550 3250 50 0001 C CNN + 1 13550 3250 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR010 +U 1 1 686D355D +P 14800 5050 +F 0 "#PWR010" H 14800 4800 50 0001 C CNN +F 1 "GND" H 14800 4900 50 0000 C CNN +F 2 "" H 14800 5050 50 0001 C CNN +F 3 "" H 14800 5050 50 0001 C CNN + 1 14800 5050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR011 +U 1 1 686D3EE1 +P 11100 8050 +F 0 "#PWR011" H 11100 7800 50 0001 C CNN +F 1 "GND" H 11100 7900 50 0000 C CNN +F 2 "" H 11100 8050 50 0001 C CNN +F 3 "" H 11100 8050 50 0001 C CNN + 1 11100 8050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR012 +U 1 1 686D6BCD +P 1800 7000 +F 0 "#PWR012" H 1800 6750 50 0001 C CNN +F 1 "GND" H 1800 6850 50 0000 C CNN +F 2 "" H 1800 7000 50 0001 C CNN +F 3 "" H 1800 7000 50 0001 C CNN + 1 1800 7000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR013 +U 1 1 686D70B1 +P 5150 6900 +F 0 "#PWR013" H 5150 6650 50 0001 C CNN +F 1 "GND" H 5150 6750 50 0000 C CNN +F 2 "" H 5150 6900 50 0001 C CNN +F 3 "" H 5150 6900 50 0001 C CNN + 1 5150 6900 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/Failed IC/NJM4151/NJM4151.sub b/library/Failed IC/NJM4151/NJM4151.sub new file mode 100644 index 000000000..704c12416 --- /dev/null +++ b/library/Failed IC/NJM4151/NJM4151.sub @@ -0,0 +1,89 @@ +* Subcircuit NJM4151 +.subckt NJM4151 net-_q6-pad1_ net-_q9-pad3_ net-_q29-pad1_ net-_q11-pad3_ net-_q33-pad1_ net-_q4-pad2_ net-_q1-pad2_ net-_j1-pad3_ +* d:\fossee\esim\library\subcircuitlibrary\njm4151\njm4151.cir +.include NJF.lib +.include NPN.lib +.include PNP.lib +q5 net-_q5-pad1_ net-_q5-pad1_ net-_j1-pad3_ Q2N2907A +q6 net-_q6-pad1_ net-_q10-pad1_ net-_q5-pad1_ Q2N2907A +q8 net-_q10-pad1_ net-_q5-pad1_ net-_j1-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q10-pad3_ net-_q9-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +r1 net-_q10-pad3_ net-_q9-pad3_ 20k +r2 net-_q12-pad3_ net-_q10-pad2_ 10k +r3 net-_q10-pad2_ net-_q13-pad1_ 5k +q13 net-_q13-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222 +q14 net-_q14-pad1_ net-_q14-pad1_ gnd Q2N2222 +r4 net-_q13-pad3_ net-_q14-pad1_ 20k +q16 net-_q13-pad1_ net-_q13-pad3_ net-_q14-pad1_ Q2N2222 +q18 net-_q18-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q19 net-_q15-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q21 net-_q20-pad2_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q30 net-_q27-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q32 net-_q12-pad2_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q23 net-_q23-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q29 net-_q29-pad1_ net-_q27-pad1_ gnd Q2N2222 +q26 net-_q10-pad2_ net-_q26-pad2_ gnd Q2N2222 +r7 net-_q26-pad2_ net-_q23-pad1_ 2k +q27 net-_q27-pad1_ net-_q27-pad2_ gnd Q2N2222 +r9 net-_q27-pad2_ net-_q23-pad1_ 2k +q28 net-_q12-pad2_ net-_q28-pad2_ gnd Q2N2222 +r8 net-_q28-pad2_ net-_q23-pad1_ 2k +q25 net-_q23-pad1_ net-_q25-pad2_ gnd Q2N2222 +r10 net-_q17-pad1_ net-_q25-pad2_ 2k +q35 net-_q12-pad2_ net-_q12-pad2_ net-_q34-pad2_ Q2N2222 +q34 net-_q12-pad2_ net-_q34-pad2_ net-_q34-pad3_ Q2N2222 +r12 net-_q34-pad3_ net-_q34-pad2_ 20k +* u2 gndpwr net-_q34-pad3_ zener +q37 net-_q17-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q40 net-_q31-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q42 net-_q38-pad3_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q45 net-_q24-pad2_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q47 net-_q18-pad2_ net-_q47-pad2_ gnd Q2N2222 +q46 net-_j1-pad3_ net-_j1-pad1_ net-_q46-pad3_ Q2N2222 +q50 net-_q47-pad2_ net-_j1-pad1_ net-_q46-pad3_ Q2N2222 +r13 net-_q46-pad3_ gnd 12k +* u3 gnd net-_j1-pad1_ zener +j1 net-_j1-pad1_ gnd net-_j1-pad3_ J2N3819 +q1 gnd net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q4 gnd net-_q4-pad2_ net-_q4-pad3_ Q2N2907A +q7 net-_q11-pad2_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q15 net-_q15-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2222 +q17 net-_q17-pad1_ net-_q17-pad2_ net-_q11-pad3_ Q2N2222 +r5 net-_q15-pad1_ net-_q17-pad2_ 2k +q20 net-_q15-pad1_ net-_q20-pad2_ net-_q11-pad3_ Q2N2222 +r6 net-_q15-pad1_ net-_q22-pad2_ 2k +q22 net-_q20-pad2_ net-_q22-pad2_ net-_q11-pad3_ Q2N2222 +q24 net-_q20-pad2_ net-_q24-pad2_ net-_q11-pad3_ Q2N2222 +r11 net-_q17-pad1_ net-_q31-pad2_ 2k +q31 net-_q31-pad1_ net-_q31-pad2_ net-_q11-pad3_ Q2N2222 +q33 net-_q33-pad1_ net-_q31-pad1_ net-_q11-pad3_ Q2N2222 +q36 gndpwr net-_q33-pad1_ net-_q36-pad3_ Q2N2907A +q38 gnd net-_q36-pad3_ net-_q38-pad3_ Q2N2907A +q39 net-_q39-pad1_ net-_q39-pad1_ net-_q11-pad3_ Q2N2222 +q41 net-_q41-pad1_ net-_q39-pad1_ net-_q11-pad3_ Q2N2222 +q44 net-_q24-pad2_ net-_q41-pad1_ net-_q11-pad3_ Q2N2222 +q48 net-_q11-pad3_ net-_q48-pad2_ net-_q48-pad3_ Q2N2907A +r14 net-_j1-pad3_ net-_q48-pad2_ 100 +r15 net-_q48-pad2_ net-_r15-pad2_ 100 +r16 net-_r15-pad2_ net-_q11-pad3_ 100 +q12 net-_j1-pad3_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +q51 net-_q41-pad1_ net-_q36-pad3_ net-_q38-pad3_ Q2N2907A +q52 net-_q39-pad1_ net-_q48-pad3_ net-_q38-pad3_ Q2N2907A +q53 net-_q48-pad3_ net-_q48-pad3_ net-_q38-pad3_ Q2N2907A +q54 net-_q47-pad2_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q55 net-_j1-pad1_ net-_q18-pad2_ net-_j1-pad3_ Q2N2907A +q2 net-_q1-pad3_ net-_q1-pad3_ net-_q18-pad1_ Q2N2907A +q3 net-_q11-pad2_ net-_q1-pad3_ net-_q18-pad1_ Q2N2907A +q49 net-_q4-pad3_ net-_q4-pad3_ net-_q18-pad1_ Q2N2907A +q43 net-_q11-pad1_ net-_q4-pad3_ net-_q18-pad1_ Q2N2907A +a1 gndpwr net-_q34-pad3_ u2 +a2 gnd net-_j1-pad1_ u3 +* Schematic Name: zener, Ngspice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends NJM4151 \ No newline at end of file diff --git a/library/Failed IC/NJM4151/NJM4151_Previous_Values.xml b/library/Failed IC/NJM4151/NJM4151_Previous_Values.xml new file mode 100644 index 000000000..e8fe401c1 --- /dev/null +++ b/library/Failed IC/NJM4151/NJM4151_Previous_Values.xml @@ -0,0 +1 @@ +zenerzenerD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/Failed IC/NJM4151/NPN.lib b/library/Failed IC/NJM4151/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/Failed IC/NJM4151/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/Failed IC/NJM4151/PNP.lib b/library/Failed IC/NJM4151/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/Failed IC/NJM4151/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/Failed IC/NJM4151/analysis b/library/Failed IC/NJM4151/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/Failed IC/NJM4151/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/Failed IC/NJM4151/njm4151.dcm b/library/Failed IC/NJM4151/njm4151.dcm new file mode 100644 index 000000000..5f3ed79b7 --- /dev/null +++ b/library/Failed IC/NJM4151/njm4151.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/library/Failed IC/NJM4151/njm4151.lib b/library/Failed IC/NJM4151/njm4151.lib new file mode 100644 index 000000000..5dc322ed0 --- /dev/null +++ b/library/Failed IC/NJM4151/njm4151.lib @@ -0,0 +1,24 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# NJM4151 +# +DEF NJM4151 X 0 40 Y Y 1 F N +F0 "X" 0 -1000 60 H V C CNN +F1 "NJM4151" 0 700 60 H V C CNN +F2 "" -50 0 60 H I C CNN +F3 "" -50 0 60 H I C CNN +DRAW +S -550 600 500 -900 0 1 0 N +X Io 1 -750 350 200 R 50 50 1 1 I +X Rs 2 -750 0 200 R 50 50 1 1 I +X Vlo 3 -750 -350 200 R 50 50 1 1 I +X GND 4 -750 -700 200 R 50 50 1 1 I +X Ro 5 700 -700 200 L 50 50 1 1 I +X Th 6 700 -350 200 L 50 50 1 1 I +X Vin 7 700 0 200 L 50 50 1 1 I +X Vp 8 700 350 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library