From 9164c210fe5d334e30cb01c45c273c065f3ba7e8 Mon Sep 17 00:00:00 2001 From: Jrvvv Date: Tue, 12 Sep 2023 23:34:34 +0300 Subject: [PATCH 001/114] git ignore added --- .gitignore | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 .gitignore diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..e468aad --- /dev/null +++ b/.gitignore @@ -0,0 +1,86 @@ +######################################################################################################### +## This is an example .gitignore file for Vivado, please treat it as an example as +## it might not be complete. In addition, XAPP 1165 should be followed. +######################################################################################################### +######### +#Exclude all +######### +* +!*/ +!.gitignore +########################################################################### +## VIVADO +########################################################################### +######### +#Source files: +######### +#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. +!*.vhd +!*.v +!*.bd +!*.edif +######### +#IP files +######### +#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products +#.xci + .dcp: implementation possible but not re-synthesis +#*.xci(www.spiritconsortium.org) +!*.xci +#*.dcp(checkpoint files) +!*.dcp +!*.vds +!*.pb +#All bd comments and layout coordinates are stored within .ui +!*.ui +!*.ooc +######### +#System Generator +######### +!*.mdl +!*.slx +!*.bxml +######### +#Simulation logic analyzer +######### +!*.wcfg +!*.coe +######### +#MIG +######### +!*.prj +!*.mem +######### +#Project files +######### +#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) +#Do NOT ignore *.xpr files +!*.xpr +#Include *.xml files for 2013.4 or earlier version +!*.xml +######### +#Constraint files +######### +#Do NOT ignore *.xdc files +!*.xdc +######### +#TCL - files +######### +!*.tcl +######### +#Journal - files +######### +!*.jou +######### +#Reports +######### +!*.rpt +!*.txt +!*.vdi +######### +#C-files +######### +!*.c +!*.h +!*.elf +!*.bmm +!*.xmp \ No newline at end of file From fc94b84aecd6dbf285eb771e9c5f58f0b4597dc1 Mon Sep 17 00:00:00 2001 From: Jrvvv Date: Thu, 14 Sep 2023 01:47:37 +0300 Subject: [PATCH 002/114] constraint added --- nexys_a7_100t.xdc | 211 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 211 insertions(+) create mode 100644 nexys_a7_100t.xdc diff --git a/nexys_a7_100t.xdc b/nexys_a7_100t.xdc new file mode 100644 index 0000000..3a443b5 --- /dev/null +++ b/nexys_a7_100t.xdc @@ -0,0 +1,211 @@ +## This file is a general .xdc for the Nexys A7-100T +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +# Clock signal +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100 }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100}]; + + +#Switches +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] + +### LEDs +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] + +## RGB LEDs +#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b +#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r + +##7 segment display +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca +set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc +set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf +set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] + +##Buttons +set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd + + +##Pmod Headers +##Pmod Header JA +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10] + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1] +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3] +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7] +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] + +##Pmod Header JD +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] + +##Pmod Header JXADC +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] + +##VGA Connector +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] +#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] +#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs + +##Micro SD Connector +#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd +#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] + +##Accelerometer +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] + +##Temperature Sensor +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct + +##Omnidirectional Microphone +#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk +#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel + +##PWM Audio Amplifier +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd + +##USB-RS232 Interface +#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts + +##USB HID (PS/2) +#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data + +##SMSC Ethernet PHY +#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv +#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn + +##Quad SPI Flash +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn \ No newline at end of file From 5ae488f55e5dcff2d895e86e2f25a298ddb647a9 Mon Sep 17 00:00:00 2001 From: Jrvvv Date: Thu, 14 Sep 2023 04:22:30 +0300 Subject: [PATCH 003/114] done but not tested --- 01/vivado.jou | 12 + 01/vivado_111601.backup.jou | 12 + riscv_cpu/riscv_cpu.cache/wt/webtalk_pa.xml | 115 +++++ riscv_cpu/riscv_cpu.ip_user_files/README.txt | 1 + .../riscv_cpu.runs/.jobs/vrs_config_1.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_10.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_11.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_12.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_13.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_14.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_15.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_16.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_17.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_18.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_19.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_2.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_20.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_21.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_22.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_23.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_24.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_25.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_26.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_3.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_4.xml | 12 + .../riscv_cpu.runs/.jobs/vrs_config_5.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_6.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_7.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_8.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_9.xml | 9 + .../riscv_cpu.runs/synth_1/fulladder32.dcp | Bin 0 -> 25834 bytes .../riscv_cpu.runs/synth_1/fulladder32.tcl | 64 +++ .../riscv_cpu.runs/synth_1/fulladder32.vds | 427 ++++++++++++++++++ .../synth_1/fulladder32_utilization_synth.pb | Bin 0 -> 242 bytes .../synth_1/fulladder32_utilization_synth.rpt | 171 +++++++ riscv_cpu/riscv_cpu.runs/synth_1/gen_run.xml | 60 +++ riscv_cpu/riscv_cpu.runs/synth_1/htr.txt | 9 + riscv_cpu/riscv_cpu.runs/synth_1/vivado.jou | 12 + riscv_cpu/riscv_cpu.runs/synth_1/vivado.pb | Bin 0 -> 51628 bytes riscv_cpu/riscv_cpu.xpr | 201 +++++++++ 40 files changed, 1321 insertions(+) create mode 100644 01/vivado.jou create mode 100644 01/vivado_111601.backup.jou create mode 100644 riscv_cpu/riscv_cpu.cache/wt/webtalk_pa.xml create mode 100644 riscv_cpu/riscv_cpu.ip_user_files/README.txt create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_1.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_10.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_11.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_12.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_13.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_14.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_15.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_16.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_17.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_18.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_19.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_2.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_20.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_21.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_22.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_23.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_24.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_25.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_26.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_3.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_4.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_5.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_6.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_7.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_8.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_9.xml create mode 100644 riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.dcp create mode 100644 riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.tcl create mode 100644 riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.vds create mode 100644 riscv_cpu/riscv_cpu.runs/synth_1/fulladder32_utilization_synth.pb create mode 100644 riscv_cpu/riscv_cpu.runs/synth_1/fulladder32_utilization_synth.rpt create mode 100644 riscv_cpu/riscv_cpu.runs/synth_1/gen_run.xml create mode 100644 riscv_cpu/riscv_cpu.runs/synth_1/htr.txt create mode 100644 riscv_cpu/riscv_cpu.runs/synth_1/vivado.jou create mode 100644 riscv_cpu/riscv_cpu.runs/synth_1/vivado.pb create mode 100644 riscv_cpu/riscv_cpu.xpr diff --git a/01/vivado.jou b/01/vivado.jou new file mode 100644 index 0000000..0f3d0ea --- /dev/null +++ b/01/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Thu Sep 14 01:18:56 2023 +# Process ID: 113089 +# Current directory: /home/jrvv/Prog_dir/study/APSLabs/01 +# Command line: vivado +# Log file: /home/jrvv/Prog_dir/study/APSLabs/01/vivado.log +# Journal file: /home/jrvv/Prog_dir/study/APSLabs/01/vivado.jou +#----------------------------------------------------------- +start_gui diff --git a/01/vivado_111601.backup.jou b/01/vivado_111601.backup.jou new file mode 100644 index 0000000..1d08815 --- /dev/null +++ b/01/vivado_111601.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Thu Sep 14 01:09:08 2023 +# Process ID: 111601 +# Current directory: /home/jrvv/Prog_dir/study/APSLabs/01 +# Command line: vivado +# Log file: /home/jrvv/Prog_dir/study/APSLabs/01/vivado.log +# Journal file: /home/jrvv/Prog_dir/study/APSLabs/01/vivado.jou +#----------------------------------------------------------- +start_gui diff --git a/riscv_cpu/riscv_cpu.cache/wt/webtalk_pa.xml b/riscv_cpu/riscv_cpu.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..2598427 --- /dev/null +++ b/riscv_cpu/riscv_cpu.cache/wt/webtalk_pa.xml @@ -0,0 +1,115 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/riscv_cpu/riscv_cpu.ip_user_files/README.txt b/riscv_cpu/riscv_cpu.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/riscv_cpu/riscv_cpu.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_1.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_10.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_11.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_12.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_13.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_14.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_15.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_16.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_16.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_16.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_17.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_17.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_18.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_18.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_19.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_19.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_2.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_20.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_20.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_21.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_21.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_21.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_22.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_22.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_22.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git 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0000000..087b2cf --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.tcl @@ -0,0 +1,64 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param chipscope.maxJobs 2 +set_param synth.incrementalSynthesisCache ./.Xil/Vivado-32477-jrvv-TM1703/incrSyn +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 +create_project -in_memory -part xc7a100tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.cache/wt [current_project] +set_property parent.project_path /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog { + /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/fulladder/fulladder.sv + /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/fulladder/fulladder4.sv +} +set_property file_type "Verilog Header" [get_files /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/fulladder/fulladder.sv] +set_property file_type "Verilog Header" [get_files /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/fulladder/fulladder4.sv] +read_verilog -library xil_defaultlib -sv /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/fulladder/fulladder32.sv +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc /home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc +set_property used_in_implementation false [get_files /home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc] + +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top fulladder32 -part xc7a100tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef fulladder32.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file fulladder32_utilization_synth.rpt -pb fulladder32_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.vds b/riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.vds new file mode 100644 index 0000000..7c956f3 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.vds @@ -0,0 +1,427 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Thu Sep 14 04:16:38 2023 +# Process ID: 53513 +# Current directory: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.runs/synth_1 +# Command line: vivado -log fulladder32.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fulladder32.tcl +# Log file: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.vds +# Journal file: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.runs/synth_1/vivado.jou +#----------------------------------------------------------- +source fulladder32.tcl -notrace +Command: synth_design -top fulladder32 -part xc7a100tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 53634 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1803.984 ; gain = 202.719 ; free physical = 550 ; free virtual = 2883 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'fulladder32' [/home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/fulladder/fulladder32.sv:3] +INFO: [Synth 8-6157] synthesizing module 'fulladder4' [/home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/fulladder/fulladder4.sv:3] +INFO: [Synth 8-6157] synthesizing module 'fulladder' [/home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/fulladder/fulladder.sv:1] +INFO: [Synth 8-6155] done synthesizing module 'fulladder' (1#1) [/home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/fulladder/fulladder.sv:1] +INFO: [Synth 8-6155] done synthesizing module 'fulladder4' (2#1) [/home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/fulladder/fulladder4.sv:3] +INFO: [Synth 8-6155] done synthesizing module 'fulladder32' (3#1) [/home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/fulladder/fulladder32.sv:3] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 1865.734 ; gain = 264.469 ; free physical = 579 ; free virtual = 2915 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1868.703 ; gain = 267.438 ; free physical = 573 ; free virtual = 2911 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1868.703 ; gain = 267.438 ; free physical = 573 ; free virtual = 2911 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1868.703 ; gain = 0.000 ; free physical = 567 ; free virtual = 2904 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc] +WARNING: [Vivado 12-584] No ports matched 'CLK100'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:7] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:7] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CLK100'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:8] +CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports CLK100]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:8] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +WARNING: [Vivado 12-584] No ports matched 'SW[0]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:12] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:12] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[1]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:13] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:13] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[2]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:14] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:14] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[3]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:15] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:15] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[4]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:16] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:16] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[5]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:17] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:17] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[6]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:18] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:18] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[7]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:19] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:19] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[8]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[9]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[10]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[11]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[12]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:24] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:24] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[13]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:25] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[14]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:26] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:26] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'SW[15]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[0]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:30] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:30] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[1]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:31] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:31] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[2]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[3]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:33] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:33] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[4]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[5]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[6]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[7]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[8]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[9]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[10]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[11]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:41] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:41] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[12]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:42] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:42] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[13]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[14]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:44] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:44] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'LED[15]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:45] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:45] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CA'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CB'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CC'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CD'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CE'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CF'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CG'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'DP'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:63] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:63] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[0]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[1]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[2]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[3]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[4]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:68] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:68] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[5]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[6]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'AN[7]'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'resetn'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'BTND'. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:79] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc:79] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [/home/jrvv/Prog_dir/study/APSLabs/nexys_a7_100t.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2028.516 ; gain = 0.000 ; free physical = 471 ; free virtual = 2808 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +Constraint Validation Runtime : Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2028.516 ; gain = 0.000 ; free physical = 471 ; free virtual = 2809 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 550 ; free virtual = 2886 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 550 ; free virtual = 2886 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 550 ; free virtual = 2886 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 554 ; free virtual = 2890 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---XORs : + 3 Input 1 Bit XORs := 32 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module fulladder +Detailed RTL Component Info : ++---XORs : + 3 Input 1 Bit XORs := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 532 ; free virtual = 2872 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 384 ; free virtual = 2724 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 383 ; free virtual = 2724 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 380 ; free virtual = 2721 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT3 | 16| +|2 |LUT5 | 32| +|3 |IBUF | 65| +|4 |OBUF | 33| ++------+-----+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 146| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2028.516 ; gain = 267.438 ; free physical = 442 ; free virtual = 2783 +Synthesis Optimization Complete : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 442 ; free virtual = 2783 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2028.516 ; gain = 0.000 ; free physical = 524 ; free virtual = 2864 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2028.516 ; gain = 0.000 ; free physical = 466 ; free virtual = 2806 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +15 Infos, 53 Warnings, 52 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:38 . Memory (MB): peak = 2028.516 ; gain = 582.688 ; free physical = 588 ; free virtual = 2928 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2028.516 ; gain = 0.000 ; free physical = 588 ; free virtual = 2928 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file fulladder32_utilization_synth.rpt -pb fulladder32_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Thu Sep 14 04:17:25 2023... diff --git a/riscv_cpu/riscv_cpu.runs/synth_1/fulladder32_utilization_synth.pb b/riscv_cpu/riscv_cpu.runs/synth_1/fulladder32_utilization_synth.pb new file mode 100644 index 0000000000000000000000000000000000000000..01996541a9bb8621cb4972479d2c936eae39dace GIT binary patch literal 242 zcmd;LGcqu=)H9mItPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- z0STwQ!VD|Q-CIR|?D4bhl>~|3m1HQG; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/synth_1/htr.txt b/riscv_cpu/riscv_cpu.runs/synth_1/htr.txt new file mode 100644 index 0000000..755fe6a --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log fulladder32.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fulladder32.tcl diff --git a/riscv_cpu/riscv_cpu.runs/synth_1/vivado.jou b/riscv_cpu/riscv_cpu.runs/synth_1/vivado.jou new file mode 100644 index 0000000..d48e4d5 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Thu Sep 14 04:16:38 2023 +# Process ID: 53513 +# Current directory: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.runs/synth_1 +# Command line: vivado -log fulladder32.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fulladder32.tcl +# Log file: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.vds +# Journal file: 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + From b99c751fb0c8dcbb9fdc37aa59d74451a8dc70d6 Mon Sep 17 00:00:00 2001 From: Jrvvv Date: Thu, 14 Sep 2023 04:25:14 +0300 Subject: [PATCH 004/114] git ignore sv added and .sv pushed --- 01/vivado.jou | 12 ------------ 01/vivado_111601.backup.jou | 12 ------------ 2 files changed, 24 deletions(-) delete mode 100644 01/vivado.jou delete mode 100644 01/vivado_111601.backup.jou diff --git a/01/vivado.jou b/01/vivado.jou deleted file mode 100644 index 0f3d0ea..0000000 --- a/01/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.2 (64-bit) -# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 -# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 -# Start of session at: Thu Sep 14 01:18:56 2023 -# Process ID: 113089 -# Current directory: /home/jrvv/Prog_dir/study/APSLabs/01 -# Command line: vivado -# Log file: /home/jrvv/Prog_dir/study/APSLabs/01/vivado.log -# Journal file: /home/jrvv/Prog_dir/study/APSLabs/01/vivado.jou -#----------------------------------------------------------- -start_gui diff --git a/01/vivado_111601.backup.jou b/01/vivado_111601.backup.jou deleted file mode 100644 index 1d08815..0000000 --- a/01/vivado_111601.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.2 (64-bit) -# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 -# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 -# Start of session at: Thu Sep 14 01:09:08 2023 -# Process ID: 111601 -# Current directory: /home/jrvv/Prog_dir/study/APSLabs/01 -# Command line: vivado -# Log file: /home/jrvv/Prog_dir/study/APSLabs/01/vivado.log -# Journal file: /home/jrvv/Prog_dir/study/APSLabs/01/vivado.jou -#----------------------------------------------------------- -start_gui From c9d448e8f7a66ff19e23f431cc27f967a528a331 Mon Sep 17 00:00:00 2001 From: Jrvvv Date: Thu, 14 Sep 2023 04:26:36 +0300 Subject: [PATCH 005/114] minor --- .gitignore | 1 + riscv_cpu/fulladder/fulladder.sv | 13 +++++++ riscv_cpu/fulladder/fulladder32.sv | 34 +++++++++++++++++++ riscv_cpu/fulladder/fulladder4.sv | 31 +++++++++++++++++ .../sources_1/new/fulladder32.sv | 26 ++++++++++++++ .../sources_1/new/fulladder4.sv | 0 6 files changed, 105 insertions(+) create mode 100644 riscv_cpu/fulladder/fulladder.sv create mode 100644 riscv_cpu/fulladder/fulladder32.sv create mode 100644 riscv_cpu/fulladder/fulladder4.sv create mode 100644 riscv_cpu/riscv_cpu.srcs/sources_1/new/fulladder32.sv create mode 100644 riscv_cpu/riscv_cpu.srcs/sources_1/new/fulladder4.sv diff --git a/.gitignore b/.gitignore index e468aad..e16b4fe 100644 --- a/.gitignore +++ b/.gitignore @@ -17,6 +17,7 @@ #Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. !*.vhd !*.v +!*.sv !*.bd !*.edif ######### diff --git a/riscv_cpu/fulladder/fulladder.sv b/riscv_cpu/fulladder/fulladder.sv new file mode 100644 index 0000000..2dac7aa --- /dev/null +++ b/riscv_cpu/fulladder/fulladder.sv @@ -0,0 +1,13 @@ +module fulladder +( + input logic carry_i, + input logic a_i, + input logic b_i, + output logic sum_o, + output logic carry_o +); + +assign sum_o = (a_i ^ b_i) ^ carry_i; +assign carry_o = (a_i & b_i) | (a_i & carry_i) | (b_i & carry_i); + +endmodule diff --git a/riscv_cpu/fulladder/fulladder32.sv b/riscv_cpu/fulladder/fulladder32.sv new file mode 100644 index 0000000..a38fe13 --- /dev/null +++ b/riscv_cpu/fulladder/fulladder32.sv @@ -0,0 +1,34 @@ +`include "fulladder4.sv" + +module fulladder32 +( + input logic carry_i, + input logic [31:0] a_i, + input logic [31:0] b_i, + output logic [31:0] sum_o, + output logic carry_o +); + +logic [8:0] carry_wires; + +assign carry_wires[0] = carry_i; +assign carry_o = carry_wires[8]; + +genvar i; + +generate + for (i = 0; i < 8; i = i + 1) begin : newgen + localparam from = i * 4; + localparam to = (i + 1) * 4 - 1; + + fulladder4 adder ( + .carry_i(carry_wires[i]), + .a_i(a_i[to:from]), + .b_i(b_i[to:from]), + .sum_o(sum_o[to:from]), + .carry_o(carry_wires[i+1]) + ); + end +endgenerate + +endmodule diff --git a/riscv_cpu/fulladder/fulladder4.sv b/riscv_cpu/fulladder/fulladder4.sv new file mode 100644 index 0000000..40e56c3 --- /dev/null +++ b/riscv_cpu/fulladder/fulladder4.sv @@ -0,0 +1,31 @@ +`include "fulladder.sv" + +module fulladder4 +( + input logic carry_i, + input logic [3:0] a_i, + input logic [3:0] b_i, + output logic [3:0] sum_o, + output logic carry_o +); + +logic [4:0] carry_wires; + +assign carry_wires[0] = carry_i; +assign carry_o = carry_wires[4]; + +genvar i; + +generate + for (i = 0; i < 4; i = i + 1) begin : newgen + fulladder adder ( + .carry_i(carry_wires[i]), + .a_i(a_i[i]), + .b_i(b_i[i]), + .sum_o(sum_o[i]), + .carry_o(carry_wires[i+1]) + ); + end +endgenerate + +endmodule diff --git a/riscv_cpu/riscv_cpu.srcs/sources_1/new/fulladder32.sv b/riscv_cpu/riscv_cpu.srcs/sources_1/new/fulladder32.sv new file mode 100644 index 0000000..20898a0 --- /dev/null +++ b/riscv_cpu/riscv_cpu.srcs/sources_1/new/fulladder32.sv @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 09/14/2023 02:09:11 AM +// Design Name: +// Module Name: fulladder32 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module fulladder32( + + ); +endmodule diff --git a/riscv_cpu/riscv_cpu.srcs/sources_1/new/fulladder4.sv b/riscv_cpu/riscv_cpu.srcs/sources_1/new/fulladder4.sv new file mode 100644 index 0000000..e69de29 From be6666c8a3c4bf2bb2a20b7dd006b72b65d10aca Mon Sep 17 00:00:00 2001 From: Jrvvv Date: Thu, 14 Sep 2023 15:21:13 +0300 Subject: [PATCH 006/114] ALU done not tested --- riscv_cpu/ALU/alu_opcodes_pkg.sv | 28 ++++++++++++++++++++++ riscv_cpu/ALU/alu_riscv.sv | 41 ++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 riscv_cpu/ALU/alu_opcodes_pkg.sv create mode 100644 riscv_cpu/ALU/alu_riscv.sv diff --git a/riscv_cpu/ALU/alu_opcodes_pkg.sv b/riscv_cpu/ALU/alu_opcodes_pkg.sv new file mode 100644 index 0000000..ce206bc --- /dev/null +++ b/riscv_cpu/ALU/alu_opcodes_pkg.sv @@ -0,0 +1,28 @@ +package alu_opcodes_pkg; +parameter ALU_OP_WIDTH = 5; + +parameter ALU_ADD = 5'b00000; +parameter ALU_SUB = 5'b01000; + +parameter ALU_XOR = 5'b00100; +parameter ALU_OR = 5'b00110; +parameter ALU_AND = 5'b00111; + +// shifts +parameter ALU_SRA = 5'b01101; +parameter ALU_SRL = 5'b00101; +parameter ALU_SLL = 5'b00001; + +// comparisons +parameter ALU_LTS = 5'b11100; +parameter ALU_LTU = 5'b11110; +parameter ALU_GES = 5'b11101; +parameter ALU_GEU = 5'b11111; +parameter ALU_EQ = 5'b11000; +parameter ALU_NE = 5'b11001; + +// set lower than operations +parameter ALU_SLTS = 5'b00010; +parameter ALU_SLTU = 5'b00011; + +endpackage \ No newline at end of file diff --git a/riscv_cpu/ALU/alu_riscv.sv b/riscv_cpu/ALU/alu_riscv.sv new file mode 100644 index 0000000..224d16a --- /dev/null +++ b/riscv_cpu/ALU/alu_riscv.sv @@ -0,0 +1,41 @@ +module alu_riscv +( + input logic [31:0] a_i, + input logic [31:0] b_i, + input logic [4:0] alu_op_i, + output logic flag_o, + output logic [31:0] result_o +); + + import alu_opcodes_pkg::*; + + always_comb begin + case(alu_op_i) + ALU_ADD : result_o = a_i + b_i; + ALU_SUB : result_o = a_i - b_i; + ALU_XOR : result_o = a_i ^ b_i; + ALU_OR : result_o = a_i | b_i; + ALU_AND : result_o = a_i & b_i; + ALU_SRA : result_o = $signed(a_i) >>> b_i[4:0]; + ALU_SRL : result_o = a_i >> b_i[4:0]; + ALU_SLL : result_o = a_i << b_i[4:0]; + ALU_SLTS : result_o = {31'b0, ($signed(a_i) < $signed(b_i))}; + ALU_SLTU : result_o = {31'b0, (a_i < b_i)}; + default : result_o = 32'b0; + endcase + end + + always_comb begin + case(alu_op_i) + ALU_LTS : flag_o = ($signed(a_i) < $signed(b_i)); + ALU_LTU : flag_o = (a_i < b_i); + ALU_GES : flag_o = ($signed(a_i) >= $signed(b_i)); + ALU_GEU : flag_o = (a_i >= b_i); + ALU_EQ : flag_o = (a_i == b_i); + ALU_NE : flag_o = (a_i != b_i); + default : flag_o = 1'b0; + endcase + end + + +endmodule From 7e3d30a1c78447f8c78a9b3a25af0042b7e1b9b6 Mon Sep 17 00:00:00 2001 From: Jrvvv Date: Fri, 15 Sep 2023 00:14:52 +0300 Subject: [PATCH 007/114] ALU done not tested --- riscv_cpu/ALU/alu_riscv.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv_cpu/ALU/alu_riscv.sv b/riscv_cpu/ALU/alu_riscv.sv index 224d16a..e08a075 100644 --- a/riscv_cpu/ALU/alu_riscv.sv +++ b/riscv_cpu/ALU/alu_riscv.sv @@ -17,8 +17,8 @@ module alu_riscv ALU_OR : result_o = a_i | b_i; ALU_AND : result_o = a_i & b_i; ALU_SRA : result_o = $signed(a_i) >>> b_i[4:0]; - ALU_SRL : result_o = a_i >> b_i[4:0]; - ALU_SLL : result_o = a_i << b_i[4:0]; + ALU_SRL : result_o = a_i >> b_i[4:0]; + ALU_SLL : result_o = a_i << b_i[4:0]; ALU_SLTS : result_o = {31'b0, ($signed(a_i) < $signed(b_i))}; ALU_SLTU : result_o = {31'b0, (a_i < b_i)}; default : result_o = 32'b0; From 53b5b45f246e33df0cdb476d12ca35121d47c620 Mon Sep 17 00:00:00 2001 From: jrvvv Date: Wed, 27 Sep 2023 00:08:36 +0300 Subject: [PATCH 008/114] dynamic indication added --- dyn_ind/HEX.v | 33 + dyn_ind/dyn_ind.v | 70 + dyn_ind/hex_decoder.v | 25 + riscv_cpu/ALU/alu_riscv.sv | 2 + riscv_cpu/ALU/tb/tb_miriscv_alu.sv | 10105 ++++++++++++++++ riscv_cpu/fulladder/fulladder32.sv | 6 +- riscv_cpu/fulladder/fulladder4.sv | 2 - riscv_cpu/riscv_cpu.cache/wt/webtalk_pa.xml | 115 +- .../riscv_cpu.runs/.jobs/vrs_config_27.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_28.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_29.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_30.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_31.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_32.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_33.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_34.xml | 9 + .../riscv_cpu.runs/.jobs/vrs_config_35.xml | 9 + .../riscv_cpu.runs/synth_1/alu_riscv.dcp | Bin 0 -> 88203 bytes .../{fulladder32.tcl => alu_riscv.tcl} | 18 +- .../{fulladder32.vds => alu_riscv.vds} | 131 +- ...ynth.pb => alu_riscv_utilization_synth.pb} | Bin 242 -> 242 bytes ...th.rpt => alu_riscv_utilization_synth.rpt} | 30 +- .../riscv_cpu.runs/synth_1/fulladder32.dcp | Bin 25834 -> 0 bytes riscv_cpu/riscv_cpu.runs/synth_1/gen_run.xml | 42 +- riscv_cpu/riscv_cpu.runs/synth_1/htr.txt | 2 +- riscv_cpu/riscv_cpu.runs/synth_1/vivado.jou | 10 +- riscv_cpu/riscv_cpu.runs/synth_1/vivado.pb | Bin 51628 -> 52505 bytes .../riscv_cpu.sim/sim_1/behav/xsim/glbl.v | 71 + .../sim_1/behav/xsim/tb_miriscv_alu.tcl | 11 + .../sim_1/behav/xsim/tb_miriscv_alu_vlog.prj | 14 + .../sim_1/behav/xsim/webtalk.jou | 12 + .../sim_1/behav/xsim/webtalk_35472.backup.jou | 12 + .../riscv_cpu.sim/sim_1/behav/xsim/xelab.pb | Bin 0 -> 2601 bytes .../tb_miriscv_alu_behav/Compile_Options.txt | 1 + .../TempBreakPointFile.txt | 1 + .../tb_miriscv_alu_behav/obj/xsim_1.c | 120 + .../webtalk/usage_statistics_ext_xsim.xml | 45 + .../xsim.dir/tb_miriscv_alu_behav/xsim.mem | Bin 0 -> 5111 bytes .../riscv_cpu.sim/sim_1/behav/xsim/xvlog.pb | 4 + riscv_cpu/riscv_cpu.xpr | 34 +- vivado.jou | 15 + 41 files changed, 10853 insertions(+), 159 deletions(-) create mode 100644 dyn_ind/HEX.v create mode 100644 dyn_ind/dyn_ind.v create mode 100644 dyn_ind/hex_decoder.v create mode 100644 riscv_cpu/ALU/tb/tb_miriscv_alu.sv create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_27.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_28.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_29.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_30.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_31.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_32.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_33.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_34.xml create mode 100644 riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_35.xml create mode 100644 riscv_cpu/riscv_cpu.runs/synth_1/alu_riscv.dcp rename riscv_cpu/riscv_cpu.runs/synth_1/{fulladder32.tcl => alu_riscv.tcl} (75%) rename riscv_cpu/riscv_cpu.runs/synth_1/{fulladder32.vds => alu_riscv.vds} (83%) rename riscv_cpu/riscv_cpu.runs/synth_1/{fulladder32_utilization_synth.pb => alu_riscv_utilization_synth.pb} (73%) rename riscv_cpu/riscv_cpu.runs/synth_1/{fulladder32_utilization_synth.rpt => alu_riscv_utilization_synth.rpt} (86%) delete mode 100644 riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.dcp create mode 100644 riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/glbl.v create mode 100644 riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/tb_miriscv_alu.tcl create mode 100644 riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/tb_miriscv_alu_vlog.prj create mode 100644 riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/webtalk.jou create mode 100644 riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/webtalk_35472.backup.jou create mode 100644 riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xelab.pb create mode 100644 riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/Compile_Options.txt create mode 100644 riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/TempBreakPointFile.txt create mode 100644 riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/obj/xsim_1.c create mode 100644 riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/webtalk/usage_statistics_ext_xsim.xml create mode 100644 riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/xsim.mem create mode 100644 riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xvlog.pb create mode 100644 vivado.jou diff --git a/dyn_ind/HEX.v b/dyn_ind/HEX.v new file mode 100644 index 0000000..e402f81 --- /dev/null +++ b/dyn_ind/HEX.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps + +module HEX( +input CLK100MHZ, +input [15:0] SW, +output [7:0] AN, +output [6:0] HEX +); + +reg [9:0] cntr; +wire isMax; + +initial begin + cntr = 10'b0; +end + +always@(posedge CLK100MHZ) begin + cntr = cntr + 1'b1; +end + +assign isMax = (cntr[9] == 1'b1); + +dyn_ind( +isMax, +SW[3:0], +SW[7:4], +SW[11:8], +SW[15:12], +HEX[6:0], +AN[7:0] +); + +endmodule diff --git a/dyn_ind/dyn_ind.v b/dyn_ind/dyn_ind.v new file mode 100644 index 0000000..aa4f210 --- /dev/null +++ b/dyn_ind/dyn_ind.v @@ -0,0 +1,70 @@ +`timescale 1ns / 1ps + +module dyn_ind +#(parameter WIDTH = 8) +( +input clk, +input [3:0] to_dec0, +input [3:0] to_dec1, +input [3:0] to_dec2, +input [3:0] to_dec3, +output reg [6:0] to_hex, +output reg [WIDTH-1:0] to_hex_ans +); + +reg [2:0] state; +reg [3:0] to_decoder; +wire [6:0] hex_dig; + +localparam DIG1 = 3'd0; +localparam DIG2 = 3'd1; +localparam DIG3 = 3'd2; +localparam DIG4 = 3'd3; + +initial begin + state = DIG1; + to_decoder = 4'b0; +end + +hex_decoder inst1( +to_decoder, +hex_dig +); + +always@(posedge clk) begin + case(state) + DIG1: + begin + to_decoder = to_dec0; + to_hex_ans = 8'b11111110; + to_hex = hex_dig; + state = DIG2; + end + + DIG2: + begin + to_decoder = to_dec1; + to_hex_ans = 8'b11111101; + to_hex = hex_dig ; + state = DIG3; + end + + DIG3: + begin + to_decoder = to_dec2; + to_hex_ans = 8'b11111011; + to_hex = hex_dig ; + state = DIG4; + end + + DIG4: + begin + to_decoder = to_dec3; + to_hex_ans = 8'b11110111; + to_hex = hex_dig ; + state = DIG1; + end + endcase +end + +endmodule diff --git a/dyn_ind/hex_decoder.v b/dyn_ind/hex_decoder.v new file mode 100644 index 0000000..3485096 --- /dev/null +++ b/dyn_ind/hex_decoder.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps + +module hex_decoder( +input [3:0] to_dec, +output reg [6:0] to_hex +); + +always@* begin + case(to_dec) + 4'b0000: to_hex = 7'b1000000; + 4'b0001: to_hex = 7'b1111001; + 4'b0010: to_hex = 7'b0100100; + 4'b0011: to_hex = 7'b0110000; + 4'b0100: to_hex = 7'b0011001; + 4'b0101: to_hex = 7'b0010010; + 4'b0110: to_hex = 7'b0000010; + 4'b0111: to_hex = 7'b1111000; + 4'b1000: to_hex = 7'b0000000; + 4'b1001: to_hex = 7'b0010000; + default: to_hex = 7'b1111111; + endcase +end + + +endmodule diff --git a/riscv_cpu/ALU/alu_riscv.sv b/riscv_cpu/ALU/alu_riscv.sv index e08a075..420d6f9 100644 --- a/riscv_cpu/ALU/alu_riscv.sv +++ b/riscv_cpu/ALU/alu_riscv.sv @@ -1,3 +1,5 @@ +`timescale 1ns / 1ps + module alu_riscv ( input logic [31:0] a_i, diff --git a/riscv_cpu/ALU/tb/tb_miriscv_alu.sv b/riscv_cpu/ALU/tb/tb_miriscv_alu.sv new file mode 100644 index 0000000..5bb02a3 --- /dev/null +++ b/riscv_cpu/ALU/tb/tb_miriscv_alu.sv @@ -0,0 +1,10105 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: MIET +// Engineer: Nikita Bulavin +// +// Create Date: +// Design Name: +// Module Name: tb_miriscv_alu +// Project Name: RISCV_practicum +// Target Devices: Nexys A7-100T +// Tool Versions: +// Description: tb for miriscv alu +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module tb_miriscv_alu(); + +import alu_opcodes_pkg::*; + +parameter TEST_VALUES = 10000; +parameter TIME_OPERATION = 100; + + +wire [4:0] operator_i; +wire [31:0] operand_a_i; +wire [31:0] operand_b_i; + +wire [31:0] result_o; +wire comparison_result_o; + +alu_riscv DUT +( + .alu_op_i (operator_i ), + .a_i (operand_a_i ), + .b_i (operand_b_i ), + + .result_o (result_o ), + .flag_o (comparison_result_o) +); + +integer i, err_count = 0; +reg [8*9:1] operator_type; +reg [103*10000:0] line_dump; +wire [31:0] result_dump; +wire comparison_result_dump; + +reg [102:0] running_line; + + assign operator_i = running_line[102:97]; + assign operand_a_i = running_line[96:65]; + assign operand_b_i = running_line[64:33]; + assign comparison_result_dump = running_line[32]; + assign result_dump = running_line[31:0]; + +initial + begin + running_line <= 0; + $display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop(); + for ( i = 0; i < TEST_VALUES; i = i + 1 ) + begin + running_line = line_dump[i*103+:103]; + #TIME_OPERATION; + if( (result_dump !== result_o) || (comparison_result_dump !== comparison_result_o) ) begin + $display("ERROR Operator: %s", operator_type, " operand_A: %h", operand_a_i, " operand_B: %h", operand_b_i, " your_Result: %h", result_o, " Result_dump: %h", result_dump, " your_Flag: %h", comparison_result_o, " Flag_dump: %h", comparison_result_dump); + err_count = err_count + 1'b1; + end + end + + $display("Number of errors: %d", err_count); + if( !err_count ) $display("\nALU SUCCESS!!!\n"); + $finish(); + end + +always @(*) begin + case(operator_i) + ALU_ADD : operator_type = "ALU_ADD "; + ALU_SUB : operator_type = "ALU_SUB "; + ALU_XOR : operator_type = "ALU_XOR "; + ALU_OR : operator_type = "ALU_OR "; + ALU_AND : operator_type = "ALU_AND "; + ALU_SRA : operator_type = "ALU_SRA "; + ALU_SRL : operator_type = "ALU_SRL "; + ALU_SLL : operator_type = "ALU_SLL "; + ALU_LTS : operator_type = "ALU_LTS "; + ALU_LTU : operator_type = "ALU_LTU "; + ALU_GES : operator_type = "ALU_GES "; + ALU_GEU : operator_type = "ALU_GEU "; + ALU_EQ : operator_type = "ALU_EQ "; + ALU_NE : operator_type = "ALU_NE "; + ALU_SLTS : operator_type = "ALU_SLTS "; + ALU_SLTU : operator_type = "ALU_SLTU "; + default : operator_type = "NOP "; + endcase +end + +initial line_dump = { +103'h1e88592d984c690cac00000000, +103'h18f51e266e7dff015e00000000, +103'h22fd89520d06582ef800000000, +103'h0e6a324c64fb76556635192232, +103'h2eb6654386f8ffa77200000000, +103'h274f0147566331f3d600000000, +103'h0d659c4c851997375ebecfbfef, +103'h3e828f80ab68987eb400000000, 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from = i * 4; + localparam to = (i + 1) * 4 - 1; fulladder4 adder ( .carry_i(carry_wires[i]), diff --git a/riscv_cpu/fulladder/fulladder4.sv b/riscv_cpu/fulladder/fulladder4.sv index 40e56c3..d6f8be8 100644 --- a/riscv_cpu/fulladder/fulladder4.sv +++ b/riscv_cpu/fulladder/fulladder4.sv @@ -1,5 +1,3 @@ -`include "fulladder.sv" - module fulladder4 ( input logic carry_i, diff --git a/riscv_cpu/riscv_cpu.cache/wt/webtalk_pa.xml b/riscv_cpu/riscv_cpu.cache/wt/webtalk_pa.xml index 2598427..5aaa8dc 100644 --- a/riscv_cpu/riscv_cpu.cache/wt/webtalk_pa.xml +++ b/riscv_cpu/riscv_cpu.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -17,98 +17,117 @@ This means code written to parse this file will need to be revisited each subseq - - + + - - - - - - - - + + + + + + + + + + + - - - + + + + - + + + + + - - - + + + - + - + - + - + - + - + - - + + + + + - + + - - - + + + + - + + + + - + - - + + - - + + - - - + + + + - - - + + + - - - + + + + + - + - +
diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_27.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_27.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_27.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_28.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_28.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_28.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_29.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_29.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_29.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_30.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_30.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_30.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_31.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_31.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_31.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_32.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_32.xml new file mode 100644 index 0000000..8dbde3f --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_32.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_33.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_33.xml new file mode 100644 index 0000000..cf8b084 --- /dev/null +++ b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_33.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_34.xml b/riscv_cpu/riscv_cpu.runs/.jobs/vrs_config_34.xml new file mode 100644 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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2028.516 ; gain = 0.000 ; free physical = 471 ; free virtual = 2808 +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1998.484 ; gain = 0.000 ; free physical = 746 ; free virtual = 4232 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2028.516 ; gain = 0.000 ; free physical = 471 ; free virtual = 2809 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2001.453 ; gain = 2.969 ; free physical = 746 ; free virtual = 4231 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 550 ; free virtual = 2886 +Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 807 ; free virtual = 4287 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 550 ; free virtual = 2886 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 807 ; free virtual = 4287 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 550 ; free virtual = 2886 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 810 ; free virtual = 4290 --------------------------------------------------------------------------------- +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/ALU/alu_riscv.sv:13] --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 554 ; free virtual = 2890 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 803 ; free virtual = 4283 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -246,8 +243,14 @@ Report RTL Partitions: Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : ++---Adders : + 3 Input 32 Bit Adders := 1 +---XORs : - 3 Input 1 Bit XORs := 32 + 2 Input 32 Bit XORs := 1 ++---Muxes : + 2 Input 32 Bit Muxes := 2 + 11 Input 32 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -255,10 +258,16 @@ Finished RTL Component Statistics Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report -Module fulladder +Module alu_riscv Detailed RTL Component Info : ++---Adders : + 3 Input 32 Bit Adders := 1 +---XORs : - 3 Input 1 Bit XORs := 1 + 2 Input 32 Bit XORs := 1 ++---Muxes : + 2 Input 32 Bit Muxes := 2 + 11 Input 32 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- @@ -276,7 +285,7 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 532 ; free virtual = 2872 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 788 ; free virtual = 4274 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -288,13 +297,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 384 ; free virtual = 2724 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 617 ; free virtual = 4103 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 383 ; free virtual = 2724 +Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 620 ; free virtual = 4105 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -306,7 +315,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 380 ; free virtual = 2721 +Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 627 ; free virtual = 4112 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -330,13 +339,13 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:33 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 654 ; free virtual = 4141 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:33 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 654 ; free virtual = 4141 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -355,25 +364,25 @@ Report Check Netlist: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:33 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 654 ; free virtual = 4141 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:33 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 654 ; free virtual = 4141 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:33 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 654 ; free virtual = 4141 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:33 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 654 ; free virtual = 4141 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -386,42 +395,50 @@ Report BlackBoxes: +-+--------------+----------+ Report Cell Usage: -+------+-----+------+ -| |Cell |Count | -+------+-----+------+ -|1 |LUT3 | 16| -|2 |LUT5 | 32| -|3 |IBUF | 65| -|4 |OBUF | 33| -+------+-----+------+ ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |CARRY4 | 26| +|2 |LUT1 | 1| +|3 |LUT2 | 5| +|4 |LUT3 | 44| +|5 |LUT4 | 136| +|6 |LUT5 | 72| +|7 |LUT6 | 222| +|8 |MUXF7 | 24| +|9 |IBUF | 69| +|10 |OBUF | 33| ++------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ -|1 |top | | 146| +|1 |top | | 632| +------+---------+-------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 392 ; free virtual = 2733 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:33 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 654 ; free virtual = 4141 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2028.516 ; gain = 267.438 ; free physical = 442 ; free virtual = 2783 -Synthesis Optimization Complete : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2028.516 ; gain = 427.250 ; free physical = 442 ; free virtual = 2783 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2001.453 ; gain = 267.406 ; free physical = 706 ; free virtual = 4192 +Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:33 . Memory (MB): peak = 2001.453 ; gain = 400.188 ; free physical = 706 ; free virtual = 4192 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2028.516 ; gain = 0.000 ; free physical = 524 ; free virtual = 2864 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2001.453 ; gain = 0.000 ; free physical = 772 ; free virtual = 4258 +INFO: [Netlist 29-17] Analyzing 50 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2028.516 ; gain = 0.000 ; free physical = 466 ; free virtual = 2806 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2023.234 ; gain = 0.000 ; free physical = 721 ; free virtual = 4206 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -15 Infos, 53 Warnings, 52 Critical Warnings and 0 Errors encountered. +14 Infos, 53 Warnings, 52 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:38 . Memory (MB): peak = 2028.516 ; gain = 582.688 ; free physical = 588 ; free virtual = 2928 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2028.516 ; gain = 0.000 ; free physical = 588 ; free virtual = 2928 +synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:43 . Memory (MB): peak = 2023.234 ; gain = 577.406 ; free physical = 847 ; free virtual = 4331 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2023.234 ; gain = 0.000 ; free physical = 847 ; free virtual = 4331 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file fulladder32_utilization_synth.rpt -pb fulladder32_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Thu Sep 14 04:17:25 2023... +INFO: [Common 17-1381] The checkpoint '/home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.runs/synth_1/alu_riscv.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file alu_riscv_utilization_synth.rpt -pb alu_riscv_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sat Sep 23 13:46:41 2023... diff --git a/riscv_cpu/riscv_cpu.runs/synth_1/fulladder32_utilization_synth.pb b/riscv_cpu/riscv_cpu.runs/synth_1/alu_riscv_utilization_synth.pb similarity index 73% rename from riscv_cpu/riscv_cpu.runs/synth_1/fulladder32_utilization_synth.pb rename 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a/riscv_cpu/riscv_cpu.runs/synth_1/gen_run.xml +++ b/riscv_cpu/riscv_cpu.runs/synth_1/gen_run.xml @@ -1,25 +1,27 @@ - - - - - - - - - - + + + + + + + + + + - + + - + + @@ -30,9 +32,23 @@ + + + + + + + + + + + + + + diff --git a/riscv_cpu/riscv_cpu.runs/synth_1/htr.txt b/riscv_cpu/riscv_cpu.runs/synth_1/htr.txt index 755fe6a..968e0b4 100644 --- a/riscv_cpu/riscv_cpu.runs/synth_1/htr.txt +++ b/riscv_cpu/riscv_cpu.runs/synth_1/htr.txt @@ -6,4 +6,4 @@ # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -vivado -log fulladder32.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fulladder32.tcl +vivado -log alu_riscv.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source alu_riscv.tcl diff --git a/riscv_cpu/riscv_cpu.runs/synth_1/vivado.jou b/riscv_cpu/riscv_cpu.runs/synth_1/vivado.jou index d48e4d5..5636920 100644 --- a/riscv_cpu/riscv_cpu.runs/synth_1/vivado.jou +++ b/riscv_cpu/riscv_cpu.runs/synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2019.2 (64-bit) # SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 # IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 -# Start of session at: Thu Sep 14 04:16:38 2023 -# Process ID: 53513 +# Start of session at: Sat Sep 23 13:45:49 2023 +# Process ID: 34268 # Current directory: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.runs/synth_1 -# Command line: vivado -log fulladder32.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fulladder32.tcl -# Log file: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.runs/synth_1/fulladder32.vds +# Command line: vivado -log alu_riscv.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source alu_riscv.tcl +# Log file: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.runs/synth_1/alu_riscv.vds # Journal file: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.runs/synth_1/vivado.jou #----------------------------------------------------------- -source fulladder32.tcl -notrace +source alu_riscv.tcl -notrace diff --git a/riscv_cpu/riscv_cpu.runs/synth_1/vivado.pb b/riscv_cpu/riscv_cpu.runs/synth_1/vivado.pb index 5c3d1d66a5b01beb42634bc5f1af6295d0db3290..628ae1c3e85cbbd46f159f269769241f98cda9c6 100644 GIT binary patch delta 3667 zcmds4TWk|Y6z#66*b#!RaP#vl^xdLYe>lbTsQ{j{riX~bjxRJwVXEf2i zHKd#2?NQ`S#NtScB)1x2vo+PXD$Fu6JdT%^3o0-A0)7!ahqi0sC|Zs%kA1SLLe(yJ znWFf~M4O@OC>1smNi9ME5>`OyMb4iYt^zjZRDkR($eY9Ej?hEBYq6t=TLw(YJh-3D z<=3wdE*+h{M9PrQaz@ykO+M0p6LOBEL`J$1Xya;Q7MR zaz&LhEg-yODrx!6 zMX=(^2J4Rde#<}O{Mmtk>XTFnm}`PVkz}ZMm#`8B%~1^Z85eAe6vFOnZ^6qqH^Lt~ zZb2W(F}QO<7BBcDzeu7=T-X!DjAYADwhMJV8G#xV9Ac^OF zLi)UvtGtq_-K6@y%O_!z`Hpojn#2A_RB_`f^E6bfD!^mbO;$s;oz!ulm*w`YU9%q5 zui3J$d1DjuqLy|Y#p1f5C1M6LbTgJTT6MIn+FXIcCNkSKLl5~-OAN&gJ*7tz_E0#w z9ks@yW;mo9NQ=iKopeM)FE%u6La``HP|{=~o=l)vTl&dPF)L;ixGHFK#Tr*kGdoRO z&beTjt8CKqUIuGDbMv!QuU{3^_GjX*JuWzz`e5h~mcU<0kKK(U?@hW#^bj+L=pk0= z3A7Hsudvp(&ML-J$FbFB0axR)l>^V?W-Re~z4aloJh-#JVYZ0Ts&E3OKlZSR>Xsvc z4uH1Tn1Ru{C|xc6h!`I1odvZAsw)EHd8@d5%DW-CM<=v_MdPE!q(Bs6r@)kvq(Bfi zifVHa5`=N7G6oITH4=ozW+G*eE@m`SI!M@e-a6ZLm>nZ&H2K+B5$xT+{D0l3d8E5j zG|F0dU`saRC$d@0@I*DsCzS+6RWnI~BGFfooW9>334;bvr{zH4{X;d7H{j8cqYQlCQv$jD6_c(<#u>{H@F>^aqrYU?{c*FRI8}ql zpGQ1Z?34sapbS(b;Y3%F_4;SWndy>{wq9VYZ%^HJPL~1Bb$((kJ#%E*CD>vg{Oa_- zB7h&y7g?vy9hyD~Sq3aUlV$y6b+PU>wh-kF3tTN%wgetss)f&I=AtL(x~b?O)V*4d zM2PzIUtBa9!NLp#wwMrt`lhB=C1mqq*!*?X;tW_@;!yYcU<-{(=N7uDOUZ;5)1?tK zjZ35b6QZRNG>x;-l4PSZRqY=^(>RJ2#EGhwN3b-?W>)Zobtoff8b{F>PmEU6=ncVF z8cCqdjnh?U>PR4sUbiaPIK++QfL%$Ztrd6*@7`#mVfLj-x7PabQj~GZA}RH8VWs8y zX8yF!qt$mg#4wWWHi@muq?>ruYnCf~Cg&;yhN z$-(@HGZa|G_M}<15%m*K>K?L`GaK4CZ+%pYbnd0jr`klpXxI#QAU&dY5SL`4Hrr0c zBU-CHz!BfW3QA3OR8K_0W&)RRte+%#{wr*VSV5o@SEt<_r^oOS4(QcaeTjM7_PH`fja2dc-|l>PzFn5SO{y2_fh1Zvjf2#e%Bu9M_CNuXCe Mkr0={!CQ0x21+|OBme*a delta 2969 zcmb`JT}&KR6vumKb{7~aU0K)5G+Y}{p8vn&e> z2#N{mqaOi1G=8Oa8&gSYV@fXC7->^liM30NzUdP&CdRLa@@9OgcV=;bWwX$*^EBD} zzrQ{A%>SHoKlqTn3T!(!$(45u4GxA9;UHh1;_Q|hMv)rJ#$)55@X+W>ar`7FrzR7l z122XnsaQ0@H;)b_`TntZJQNN`MkKt@7GsbCb;RWnH9_(PG?{;bkA`9izLm!U_Nih3 zx{1T1C<0yRABjZx@z}`dSSYRwG);o_nIq_LIL0f`&S$1Ntpa_AGZ2hBL?A z=30ySCShM{9O@o*Bg%QK2L5F$(Vsf&pqJxJm29G3;5u}a%Us$-$va8EQ<6|-YE8=X zT)R$jnk$=>4G65U&FB+2XldQC{Up1m?Rq{CP>Dr4=X~! za`SIwh@5}9lqm{~TpR2t4oUxTUyXF>Q9((vc9-+%*2;B&77)n#%ufs~&3j0EycB_b zq6hB2QqJ%qBqypF3B&Z{QAl5$Bj;b8WwsROFOxi^7b~If_15j1f;230b^3~pmIR7b zfj3oCC^EMq;e3&)o>Il~|6lR9x8Hv#T)wiQ zIGVJCg`u5#uVLluQnaeMyqih zz>S=ge#4O?I-ZK(!;Am4Fe#ZrUH_P(L zu_;%wa$4;LFD4=n#)HcQD}1$tlZu3yxmH>Pn8liCfRofLaRmH&0=Lcli`deDhDv z1XT2nrO!;wZ_Z3;JJd-Y+!;pOwG2(u{iut<8d+WmBfUvF9VGDWAYw4RJVcz3zFR`a zr~_^xODVl!nzOU4mMc*-?DK2-vJJa9Rxw^nu$!af8XLp+>~}fAF?mFpdz~l)wVBgw zKi5OAdL7&Dr8hE7?hDAM2Wt(I8*L+F3H`1-jkq{G$kcBWcdt62ZM8J#x7QqJ2FCc) Tkt8q5ydVcfHHZ~hTMhmP2PTtD diff --git a/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/glbl.v b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/tb_miriscv_alu.tcl b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/tb_miriscv_alu.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/tb_miriscv_alu.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/tb_miriscv_alu_vlog.prj b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/tb_miriscv_alu_vlog.prj new file mode 100644 index 0000000..f55d380 --- /dev/null +++ b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/tb_miriscv_alu_vlog.prj @@ -0,0 +1,14 @@ +# compile verilog/system verilog design source files +sv xil_defaultlib \ +"../../../../fulladder/fulladder.sv" \ +"../../../../fulladder/fulladder4.sv" \ +"../../../../fulladder/fulladder32.sv" \ +"../../../../ALU/alu_opcodes_pkg.sv" \ +"../../../../ALU/alu_riscv.sv" \ +"../../../../ALU/tb/tb_miriscv_alu.sv" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/webtalk.jou b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..d3293f6 --- /dev/null +++ b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sat Sep 23 13:56:32 2023 +# Process ID: 36044 +# Current directory: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/webtalk_35472.backup.jou b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/webtalk_35472.backup.jou new file mode 100644 index 0000000..5c6b808 --- /dev/null +++ b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/webtalk_35472.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sat Sep 23 13:52:27 2023 +# Process ID: 35472 +# Current directory: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/jrvv/Prog_dir/study/APSLabs/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xelab.pb b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000000000000000000000000000000000000..c841ac53867251aad02057a02e9b6807500b65e6 GIT binary patch literal 2601 zcmc&$-EP}96mFcrMTxaAu%C8CGjPGY7DX*tlx$1EE|zA)Fu?7yBpr&~7?i|FY$;I{ zDaYwcbT2UMZZENy+9Qm#Y?uDS(yIbCB>tW6oR8l*M<55ywt#H`T6_0*J*WHlmY`Y1 zu;eBB2DE;oV;pmMwwSvalM7ric{qPT_dyeNoxnn9KDAi;{if%3++Z+BZxnlzy+3wt zv>M9sJf*^PTQMc=Kv~~EBGMZ1Gz@PKTf=7(OQ@vNf zQzA$?Cb6}SZi4>X0H2&zc~0}>a2~Dex~32RG{D~tTXN2XU8C7`^mZMd9n##c^2-tz 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b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/Compile_Options.txt new file mode 100644 index 0000000..ea71678 --- /dev/null +++ b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "ebda44bc581548ea940ad611bfa7c6d2" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_miriscv_alu_behav" "xil_defaultlib.tb_miriscv_alu" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/TempBreakPointFile.txt b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/obj/xsim_1.c b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/obj/xsim_1.c new file mode 100644 index 0000000..5dd6830 --- /dev/null +++ b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/obj/xsim_1.c @@ -0,0 +1,120 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_4(char*, char *); +extern void execute_5(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[21] = {(funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_4, (funcp)execute_5, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 21; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_miriscv_alu_behav/xsim.reloc", (void **)funcTab, 21); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_miriscv_alu_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_miriscv_alu_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstantiate(); + +extern void implicit_HDL_SCcleanup(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_miriscv_alu_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_miriscv_alu_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_miriscv_alu_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/webtalk/usage_statistics_ext_xsim.xml b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..999d3bf --- /dev/null +++ b/riscv_cpu/riscv_cpu.sim/sim_1/behav/xsim/xsim.dir/tb_miriscv_alu_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,45 @@ + + +