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Minor changelog changes (#2069)
[sc-100377](https://app.shortcut.com/xanaduai/story/100377/initial-changelog-ordering-for-pl)
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‎doc/releases/changelog-dev.md‎

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@@ -14,8 +14,8 @@
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[(#2002)](https://github.com/PennyLaneAI/catalyst/pull/2002)
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Two new functions, ``qml.allocate()`` and ``qml.deallocate()``, [have been added to
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PennyLane](https://docs.pennylane.ai/en/stable/development/release_notes.html#release-0-43-0) to support
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dynamic wire allocation. With Catalyst, these features can be accessed on
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PennyLane](https://docs.pennylane.ai/en/stable/development/release_notes.html#release-0-43-0)
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to support dynamic wire allocation. With Catalyst, these features can be accessed on
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``lightning.qubit``, ``lightning.kokkos``, and ``lightning.gpu``.
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Dynamic wire allocation refers to the allocation of wires in the middle of a circuit, as opposed to the static allocation during device initialization. For example:
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@qjit
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@qml.qnode(qml.device("lightning.qubit", wires=3)) # 3 initial qubits
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def circuit():
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qml.X(1) # |010>
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qml.X(0) # |10>
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with qml.allocate(1) as q: # |010> and |0>, 1 dynamically allocted qubit
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qml.X(q[0]) # |010> and |1>
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qml.CNOT(wires=[q[0], 2]) # |011> and |1>
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with qml.allocate(1) as q: # |10> and |0>, 1 dynamically allocated qubit
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qml.X(q[0]) # |10> and |1>
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qml.CNOT(wires=[q[0], 1]) # |11> and |1>
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return qml.probs(wires=[0, 1, 2])
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qml.capture.disable()
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```
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```pycon
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>>> print(circuit())
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[0. 0. 0. 1. 0. 0. 0. 0.]
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```
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In the above program, 3 qubits are allocated during device initialization, and 1
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additional qubit is allocated inside the circuit with ``qml.allocate(1)``. This is clear
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when we inspect the compiled MLIR:
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```
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>>> print(circuit.mlir)
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func.func public @circuit() -> tensor<8xf64> attributes {qnode} {
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%c0_i64 = arith.constant 0 : i64
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quantum.device shots(%c0_i64) ["/path/to/liblightning_qubit_catalyst.so", "LightningSimulator", "{'mcmc': False, 'num_burnin': 0, 'kernel_name': None}"]
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%0 = quantum.alloc( 3) : !quantum.reg
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%1 = quantum.extract %0[ 1] : !quantum.reg -> !quantum.bit
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%out_qubits = quantum.custom "PauliX"() %1 : !quantum.bit
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%2 = quantum.alloc( 1) : !quantum.reg
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%3 = quantum.extract %2[ 0] : !quantum.reg -> !quantum.bit
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%out_qubits_0 = quantum.custom "PauliX"() %3 : !quantum.bit
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%4 = quantum.extract %0[ 2] : !quantum.reg -> !quantum.bit
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%out_qubits_1:2 = quantum.custom "CNOT"() %out_qubits_0, %4 : !quantum.bit, !quantum.bit
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%5 = quantum.insert %2[ 0], %out_qubits_1#0 : !quantum.reg, !quantum.bit
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quantum.dealloc %5 : !quantum.reg
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%6 = quantum.extract %0[ 0] : !quantum.reg -> !quantum.bit
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%7 = quantum.compbasis qubits %6, %out_qubits, %out_qubits_1#1 : !quantum.obs
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%8 = quantum.probs %7 : tensor<8xf64>
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%9 = quantum.insert %0[ 1], %out_qubits : !quantum.reg, !quantum.bit
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%10 = quantum.insert %9[ 2], %out_qubits_1#1 : !quantum.reg, !quantum.bit
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%11 = quantum.insert %10[ 0], %6 : !quantum.reg, !quantum.bit
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quantum.dealloc %11 : !quantum.reg
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quantum.device_release
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return %8 : tensor<8xf64>
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}
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[0. 0. 0. 1.]
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```
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We can see that there are now 2 pairs of ``quantum.alloc`` and ``quantum.dealloc``
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operations. The quantum register value ``%0`` corresponds to the initial wires on the
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device, and the quantum register value ``%2`` corresponds to the dynamically allocated
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wire.
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In the above program, 2 qubits are allocated during device initialization, and 1
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additional qubit is allocated inside the circuit with ``qml.allocate(1)``.
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For more information on what ``qml.allocate`` and ``qml.deallocate`` do, please consult the
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[PennyLane v0.43 release notes](https://docs.pennylane.ai/en/stable/development/release_notes.html#release-0-43-0).
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However, there are some notable differences between the behaviour of these features
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with ``qjit`` versus without. For details, please see
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[the relevant sections on the Catalyst sharp bits page](https://docs.pennylane.ai/projects/catalyst/en/stable/dev/sharp_bits.html#functionality-differences-from-pennylane).
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with ``qjit`` versus without. For details, please see the relevant sections in the
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[Catalyst sharp bits page](https://docs.pennylane.ai/projects/catalyst/en/stable/dev/sharp_bits.html#functionality-differences-from-pennylane).
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* A new quantum compilation pass that reduces the depth and count of non-Clifford Pauli product
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rotations (PPRs) in circuits is now available. This compilation pass works by commuting
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non-Clifford PPRs (often referred to as ``T`` gates) in adjacent
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non-Clifford PPRs (often just referred to as ``T`` gates) in adjacent
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layers and merging compatible ones. More details can be found in Figure 6 of
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[A Game of Surface Codes](https://arXiv:1808.02892v3).
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[(#1975)](https://github.com/PennyLaneAI/catalyst/pull/1975)
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[(#2048)](https://github.com/PennyLaneAI/catalyst/pull/2048)
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Consider the following circuit.
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Consider the following circuit:
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```python
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import pennylane as qml
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from catalyst import qjit, measure
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from catalyst.passes import to_ppr, commute_ppr, t_layer_reduction, merge_ppr_ppm
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from catalyst.passes import to_ppr, commute_ppr, t_layer_reduction, merge_ppr_ppm, ppm_specs
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pips = [("pipe", ["enforce-runtime-invariants-pipeline"])]
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no_reduce_T = {
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"to_ppr": {},
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"commute_ppr": {},
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"merge_ppr_ppm": {},
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}
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@qjit(pipelines=pips, target="mlir")
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@t_layer_reduction
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@merge_ppr_ppm
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@commute_ppr
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@to_ppr
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@qml.qnode(qml.device("null.qubit", wires=3))
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def circuit():
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for i in range(3):
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qml.H(wires=i)
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qml.S(wires=i)
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qml.CNOT(wires=[i, (i + 1) % n])
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qml.T(wires=i)
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qml.H(wires=i)
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qml.T(wires=i)
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return [measure(wires=i) for i in range(n)]
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```
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reduce_T = {
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"to_ppr": {},
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"commute_ppr": {},
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"merge_ppr_ppm": {},
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"t_layer_reduction": {}
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}
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After performing the ``catalyst.passes.to_ppr`` and ``catalyst.passes.merge_ppr_ppm``
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passes, the circuit contains a depth of four of non-Clifford PPRs. Subsequently applying the
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``t_layer_reduction`` pass will move PPRs around via commutation, resulting in a circuit with a
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smaller PPR depth of three.
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for pipeline in [reduce_T, no_reduce_T]:
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@qjit(pipelines=pips, target="mlir", circuit_transform_pipeline=pipeline)
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@qml.qnode(qml.device("null.qubit", wires=3))
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def circuit():
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n = 3
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for i in range(n):
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qml.H(wires=i)
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qml.S(wires=i)
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qml.CNOT(wires=[i, (i + 1) % n])
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qml.T(wires=i)
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qml.H(wires=i)
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qml.T(wires=i)
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return [measure(wires=i) for i in range(n)]
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print(ppm_specs(circuit))
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```
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```pycon
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>>> print(circuit.mlir_opt)
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...
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%1 = quantum.extract %0[ 0] : !quantum.reg -> !quantum.bit
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%2 = quantum.extract %0[ 1] : !quantum.reg -> !quantum.bit
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// layer 1
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%3 = qec.ppr ["X"](8) %1 : !quantum.bit
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%4 = qec.ppr ["X"](8) %2 : !quantum.bit
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// layer 2
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%5 = quantum.extract %0[ 2] : !quantum.reg -> !quantum.bit
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%6:2 = qec.ppr ["Y", "X"](8) %3, %4 : !quantum.bit, !quantum.bit
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%7 = qec.ppr ["X"](8) %5 : !quantum.bit
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%8:3 = qec.ppr ["X", "Y", "X"](8) %6#0, %6#1, %7:!quantum.bit, !quantum.bit, !quantum.bit
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// layer 3
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%9:3 = qec.ppr ["X", "X", "Y"](8) %8#0, %8#1, %8#2:!quantum.bit, !quantum.bit, !quantum.bit
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...
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{'circuit_0': {'depth_pi8_ppr': 3, 'depth_ppm': 1, 'logical_qubits': 3, 'max_weight_pi8': 3, 'num_of_ppm': 3, 'pi8_ppr': 6}}
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{'circuit_0': {'depth_pi8_ppr': 4, 'depth_ppm': 1, 'logical_qubits': 3, 'max_weight_pi8': 3, 'num_of_ppm': 3, 'pi8_ppr': 6}}
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```
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After performing the :func:`~.passes.to_ppr`, :func:`~.passes.commute_ppr`, and :func:`~.passes.merge_ppr_ppm`,
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passes, the circuit contains a depth of four of non-Clifford PPRs (`depth_pi8_ppr`). Subsequently applying the
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:func:`~.passes.t_layer_reduction` pass will move PPRs around via commutation, resulting in a circuit with a
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smaller PPR depth of three.
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* Catalyst now provides native support for `SingleExcitation`, `DoubleExcitation`,
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and `PCPhase` on compatible devices like Lightning simulators.
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This enhancement avoids unnecessary gate decomposition,
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return qml.probs()
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```
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<h3>Improvements 🛠</h3>
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* Significantly improved resource tracking with `null.qubit`.
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The new tracking has better integration with PennyLane (e.g. for passing the filename to write out), cleaner documentation, and its own wrapper class.
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It also now tracks circuit depth, as well as gate counts by number of wires.
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[(#2033)](https://github.com/PennyLaneAI/catalyst/pull/2033)
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[(#2055)](https://github.com/PennyLaneAI/catalyst/pull/2055)
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* Catalyst now supports returning classical and MCM values with the dynamic one-shot MCM method.
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[(#2004)](https://github.com/PennyLaneAI/catalyst/pull/2004)
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True], dtype=bool))
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```
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* Improve the pass `--ppm-specs` to count the depth of PPRs and PPMs in the circuit.
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[(#2014)](https://github.com/PennyLaneAI/catalyst/pull/2014)
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* The default mid-circuit measurement method in catalyst has been changed from `"single-branch-statistics"` to `"one-shot"`.
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[[#2017]](https://github.com/PennyLaneAI/catalyst/pull/2017)
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[[#2019]](https://github.com/PennyLaneAI/catalyst/pull/2019)
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<h3>Improvements 🛠</h3>
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* Significantly improved resource tracking with `null.qubit`.
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The new tracking has better integration with PennyLane (e.g. for passing the filename to write out), cleaner documentation, and its own wrapper class.
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It also now tracks circuit depth, as well as gate counts by number of wires.
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[(#2033)](https://github.com/PennyLaneAI/catalyst/pull/2033)
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[(#2055)](https://github.com/PennyLaneAI/catalyst/pull/2055)
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* Improve the pass `--ppm-specs` to count the depth of PPRs and PPMs in the circuit.
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[(#2014)](https://github.com/PennyLaneAI/catalyst/pull/2014)
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* A new pass `--partition-layers` has been added to group PPR/PPM operations into `qec.layer`
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operations based on qubit interactive and commutativity, enabling circuit analysis and
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potentially to support parallel execution.
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<h3>Deprecations 👋</h3>
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* Deprecated usages of `Device.shots` along with setting `device(..., shots=...)`.
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* Deprecated usages of ``Device.shots`` along with setting ``device(..., shots=...)``.
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Heavily adjusted frontend pipelines within qfunc, tracer, verification and QJITDevice to account for this change.
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Please use ``qml.set_shots(shots=...)`` or set shots at the QNode level (i.e., ``qml.QNode(..., shots=...)``).
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[(#1952)](https://github.com/PennyLaneAI/catalyst/pull/1952)
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<h3>Bug fixes 🐛</h3>
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[(#2057)](https://github.com/PennyLaneAI/catalyst/pull/2057)
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This pass is part of a bottom-of-stack MBQC execution pathway, with a thin shim between the
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PPR/PPM layer and MBQC to enable end-to-end compilation on a mocked backend. Also, in MBQC gate
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PPR/PPM layer and MBQC to enable end-to-end compilation on a mocked backend. Also, in an MBQC gate
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set, one of the gate `RotXZX` cannot yet be executed on available backends.
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```python

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