Skip to content

Commit 5afe64e

Browse files
crasbecrasbe
authored
Merge pull request #21775 from crasbe/pr/stm32c0_new
cpu, boards: add new STM32C0 and NUCLEO-C071RB [new PR]
2 parents 5a7be6b + e0f9f11 commit 5afe64e

File tree

25 files changed

+452
-37
lines changed

25 files changed

+452
-37
lines changed

‎boards/nucleo-c031c6/include/periph_conf.h‎

Lines changed: 18 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
* @{
1111
*
1212
* @file
13-
* @brief Peripheral MCU configuration for the nucleo-c031c6 board
13+
* @brief Peripheral MCU configuration for the Nucleo-C031C6 board
1414
*
1515
* @author Jason Parker <[email protected]>
1616
*/
@@ -69,7 +69,7 @@ static const uart_conf_t uart_config[] = {
6969
.tx_pin = GPIO_PIN(PORT_B, 6),
7070
.rx_af = GPIO_AF0,
7171
.tx_af = GPIO_AF0,
72-
.bus = APB12, //?
72+
.bus = APB12,
7373
.irqn = USART1_IRQn,
7474
},
7575
};
@@ -88,19 +88,14 @@ static const uart_conf_t uart_config[] = {
8888
* just define 6 ADC channels, for the Nucleo
8989
* Arduino header pins A0-A5.
9090
*
91-
* To find appropriate device and channel find in the
92-
* board manual, table showing pin assignments and
93-
* information about ADC - a text similar to ARD_A[N]_IN[X],
94-
* where:
95-
* [N] - describes analog pin number,
96-
* [X] - describes used channel - indexed from 1,
97-
* for example ARD_A5_IN16 is channel 16
91+
* The appropriate ADC device and channel for each pin
92+
* can be found in the board manual in the pin assignment
93+
* table. The format of the entries is ARD_A[N]_IN[X], where [N] describes the
94+
* analog arduino pin and [Y] describes the used channel - indexed from 1.
95+
* For example: ARD_A0_IN11 is Arduino A4, Channel 11.
9896
*
99-
* For Nucleo-C031C6 this information is in board manual,
100-
* Table 11, page 20.
101-
*
102-
* STM32C031C6 do not have internal channel for VBAT, more details provided
103-
* in the MCU datasheet - section 3.14, page 20.
97+
* For the Nucleo-C031C6 this information is in the board manual,
98+
* Table 11 "ARDUINO connector pinout".
10499
*
105100
* @{
106101
*/
@@ -120,15 +115,16 @@ static const adc_conf_t adc_config[] = {
120115
* @name PWM configuration
121116
* @{
122117
*
123-
* To find appriopate device and channel find in the MCU datasheet table
124-
* concerning "Alternate function AF0 to AF7" a text similar to TIM[X]_CH[Y],
125-
* where:
126-
* TIM[X] - is device,
127-
* [Y] - describes used channel (indexed from 0), for example TIM2_CH1 is
128-
* channel 0 in configuration structure (cc_chan - field),
129-
* Port column in the table describes connected port.
118+
* The appropriate PWM device and channel for each pin can be found
119+
* in the MCU datasheet table "Alternate function AF0 to AF7".
120+
* The format of the entries is TIM[X]_CH[Y], where TIM[X] is the timer device
121+
* and [Y] describes the used channel (indexed from 0). For example TIM2_CH1 is
122+
* Timer 2, Channel 1 which corresponds to Channel 0 in the PWM configuration
123+
* structure.
124+
* The port column in the table describes the connected port.
130125
*
131-
* For Nucleo-c031c6 this information is in the MCU datasheet, Table 13, page 35.
126+
* For the Nucleo-C031C6 this information can be found in the MCU datasheet,
127+
* Table 15 "Port B alternate function mapping (AF0 to AF7)".
132128
*
133129
*/
134130
static const pwm_conf_t pwm_config[] = {

‎boards/nucleo-c071rb/Kconfig‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
# SPDX-FileCopyrightText: 2024 BISSELL Homecare, Inc.
2+
# SPDX-License-Identifier: LGPL-2.1-only
3+
4+
config BOARD
5+
default "nucleo-c071rb" if BOARD_NUCLEO_C071RB
6+
7+
config BOARD_NUCLEO_C071RB
8+
bool
9+
default y
10+
select BOARD_COMMON_NUCLEO64
11+
select CPU_MODEL_STM32C071RB
12+
13+
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

‎boards/nucleo-c071rb/Makefile‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
MODULE = board
2+
DIRS = $(RIOTBOARD)/common/nucleo
3+
4+
include $(RIOTBASE)/Makefile.base

‎boards/nucleo-c071rb/Makefile.dep‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
include $(RIOTBOARD)/common/nucleo64/Makefile.dep

‎boards/nucleo-c071rb/Makefile.features‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
CPU = stm32
2+
CPU_MODEL = stm32c071rb
3+
4+
# Put defined MCU peripherals here (in alphabetical order)
5+
FEATURES_PROVIDED += periph_adc
6+
FEATURES_PROVIDED += periph_i2c
7+
FEATURES_PROVIDED += periph_pwm
8+
FEATURES_PROVIDED += periph_spi
9+
FEATURES_PROVIDED += periph_timer
10+
FEATURES_PROVIDED += periph_uart
11+
12+
# Put other features for this board (in alphabetical order)
13+
FEATURES_PROVIDED += riotboot
14+
15+
# load the common Makefile.features for Nucleo boards
16+
include $(RIOTBOARD)/common/nucleo64/Makefile.features

‎boards/nucleo-c071rb/Makefile.include‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
# load the common Makefile.include for Nucleo boards
2+
include $(RIOTBOARD)/common/nucleo64/Makefile.include

‎boards/nucleo-c071rb/doc.md‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
@defgroup boards_nucleo-c071rb STM32 Nucleo-C071RB
2+
@ingroup boards_common_nucleo64
3+
@brief Support for the STM32 Nucleo-C071RB
4+
5+
## Overview
6+
7+
The Nucleo-C071RB is a board from ST's Nucleo family supporting a ARM
8+
Cortex-M0+ STM32C071RB microcontroller with 24KiB of RAM and 128KiB of Flash.
9+
10+
## Pinout
11+
12+
See Board Manual referenced below, section 7 pages 19-21.
13+
14+
### MCU
15+
16+
| MCU | STM32C071RB |
17+
|:---------- |:------------------- |
18+
| Family | ARM Cortex-M0+ |
19+
| Vendor | ST Microelectronics |
20+
| RAM | 24KiB |
21+
| Flash | 128KiB |
22+
| Frequency | up to 48MHz |
23+
| FPU | no |
24+
| Timers | 12 (2x watchdog, 1 SysTick, 5x 16-bit) |
25+
| ADCs | 1x 12-bit (up to 19 channels) |
26+
| UARTs | 2 |
27+
| SPIs | 1 |
28+
| I2Cs | 1 |
29+
| RTC | 1 |
30+
| Vcc | 2.0V - 3.6V |
31+
| Datasheet | [Datasheet](https://www.st.com/resource/en/datasheet/stm32c071rb.pdf) |
32+
| Reference Manual | [Reference Manual](https://www.st.com/resource/en/reference_manual/rm0490-stm32c0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) |
33+
| Programming Manual | [Programming Manual](https://www.st.com/resource/en/programming_manual/pm0223-stm32-cortexm0-mcus-programming-manual-stmicroelectronics.pdf) |
34+
| Board Manual | [Board Manual](https://www.st.com/resource/en/user_manual/um3353-stm32-nucleo64-board-mb2046-stmicroelectronics.pdf) |
35+
36+
## Flashing the Board
37+
38+
A detailed description about the flashing process can be found on the
39+
[guides page](https://guide.riot-os.org/board_specific/stm32/).
40+
The board name for the Nucleo-C071RB is `nucleo-c071rb`.

‎boards/nucleo-c071rb/include/periph_conf.h‎

Lines changed: 173 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,173 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2024 BISSELL Homecare, Inc.
3+
* SPDX-License-Identifier: LGPL-2.1-only
4+
*/
5+
6+
/**
7+
* @ingroup boards_nucleo-c071rb
8+
* @{
9+
*
10+
* @file
11+
* @brief Peripheral MCU configuration for the Nucleo-C071RB board
12+
*
13+
* @author Jason Parker <[email protected]>
14+
*/
15+
16+
#pragma once
17+
18+
/* Add specific clock configuration (HSE, LSE) for this board here */
19+
#ifndef CONFIG_BOARD_HAS_LSE
20+
# define CONFIG_BOARD_HAS_LSE 1
21+
#endif
22+
23+
#include "clk_conf.h"
24+
#include "cfg_i2c1_pb8_pb9.h"
25+
#include "cfg_rtt_default.h"
26+
27+
#ifdef __cplusplus
28+
extern "C" {
29+
#endif
30+
31+
/**
32+
* @name Timer configuration
33+
* @{
34+
*/
35+
static const timer_conf_t timer_config[] = {
36+
{
37+
.dev = TIM3,
38+
.max = 0x0000ffff,
39+
.rcc_mask = RCC_APBENR1_TIM3EN,
40+
.bus = APB1,
41+
.irqn = TIM3_IRQn
42+
}
43+
};
44+
45+
#define TIMER_0_ISR isr_tim3
46+
47+
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
48+
/** @} */
49+
50+
/**
51+
* @name UART configuration
52+
* @{
53+
*/
54+
static const uart_conf_t uart_config[] = {
55+
{
56+
.dev = USART2,
57+
.rcc_mask = RCC_APBENR1_USART2EN,
58+
.rx_pin = GPIO_PIN(PORT_A, 3),
59+
.tx_pin = GPIO_PIN(PORT_A, 2),
60+
.rx_af = GPIO_AF1,
61+
.tx_af = GPIO_AF1,
62+
.bus = APB1,
63+
.irqn = USART2_IRQn,
64+
},
65+
{ /* Arduino pinout on D0/D1 */
66+
.dev = USART1,
67+
.rcc_mask = RCC_APBENR2_USART1EN,
68+
.rx_pin = GPIO_PIN(PORT_B, 7),
69+
.tx_pin = GPIO_PIN(PORT_B, 6),
70+
.rx_af = GPIO_AF0,
71+
.tx_af = GPIO_AF0,
72+
.bus = APB12,
73+
.irqn = USART1_IRQn,
74+
},
75+
};
76+
77+
#define UART_0_ISR (isr_usart2)
78+
#define UART_1_ISR (isr_usart1)
79+
80+
#define UART_NUMOF ARRAY_SIZE(uart_config)
81+
/** @} */
82+
83+
/**
84+
* @name ADC configuration
85+
*
86+
* Note that we do not configure all ADC channels,
87+
* and not in the STM32C071 order. Instead, we
88+
* just define 6 ADC channels, for the Nucleo
89+
* Arduino header pins A0-A5.
90+
*
91+
* The appropriate ADC device and channel for each pin
92+
* can be found in the board manual in the pin assignment
93+
* table. The format of the entries is ADC_IN[Y], where
94+
* [Y] - describes the used channel - indexed from 1.
95+
* For example: ADC_IN11 is Channel 11.
96+
*
97+
* For the Nucleo-C071RB this information is in the board manual,
98+
* Table 12 "ARDUINO connectors on NUCLEO-C071RB and NUCLEO-C092RC".
99+
*
100+
* @{
101+
*/
102+
static const adc_conf_t adc_config[] = {
103+
{ .pin = GPIO_PIN(PORT_A, 0), .dev = 0, .chan = 0 }, /* ADC_IN0 */
104+
{ .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 1 }, /* ADC_IN1 */
105+
{ .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 4 }, /* ADC_IN4 */
106+
{ .pin = GPIO_PIN(PORT_B, 0), .dev = 0, .chan = 17 }, /* ADC_IN17 */
107+
{ .pin = GPIO_PIN(PORT_C, 4), .dev = 0, .chan = 11 }, /* ADC_IN11 */
108+
{ .pin = GPIO_PIN(PORT_C, 5), .dev = 0, .chan = 12 }, /* ADC_IN12 */
109+
};
110+
111+
#define ADC_NUMOF ARRAY_SIZE(adc_config)
112+
/** @} */
113+
114+
/**
115+
* @name PWM configuration
116+
* @{
117+
*
118+
* The appropriate PWM device and channel for each pin can be found
119+
* in the MCU datasheet table "Alternate function AF0 to AF7".
120+
* The format of the entries is TIM[X]_CH[Y], where TIM[X] is the timer device
121+
* and [Y] describes the used channel (indexed from 0). For example TIM3_CH1 is
122+
* Timer 3, Channel 1 which corresponds to Channel 0 in the PWM configuration
123+
* structure.
124+
* The port column in the table describes the connected port.
125+
*
126+
* For the Nucleo-C071RB this information can be found in the MCU datasheet,
127+
* Table 15 "Port B alternate function mapping (AF0 to AF7)".
128+
*
129+
*/
130+
static const pwm_conf_t pwm_config[] = {
131+
{
132+
.dev = TIM3,
133+
.rcc_mask = RCC_APBENR1_TIM3EN,
134+
.chan = { { .pin = GPIO_PIN(PORT_B, 5) /*CN9 D6 */, .cc_chan = 1 },
135+
{ .pin = GPIO_PIN(PORT_B, 0) /*CN5 D10 */, .cc_chan = 2 },
136+
{ .pin = GPIO_PIN(PORT_B, 1) /*CN8 A3 */, .cc_chan = 3 },
137+
{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
138+
.af = GPIO_AF1,
139+
.bus = APB1
140+
},
141+
};
142+
143+
#define PWM_NUMOF ARRAY_SIZE(pwm_config)
144+
/** @} */
145+
146+
/**
147+
* @name SPI configuration
148+
* @{
149+
*/
150+
static const spi_conf_t spi_config[] = {
151+
{
152+
.dev = SPI1,
153+
.mosi_pin = GPIO_PIN(PORT_A, 7), /* Arduino D11 */
154+
.miso_pin = GPIO_PIN(PORT_A, 6), /* Arduino D12 */
155+
.sclk_pin = GPIO_PIN(PORT_A, 5), /* Arduino D13 */
156+
.cs_pin = GPIO_UNDEF,
157+
.mosi_af = GPIO_AF0,
158+
.miso_af = GPIO_AF0,
159+
.sclk_af = GPIO_AF0,
160+
.cs_af = GPIO_AF0,
161+
.rccmask = RCC_APBENR2_SPI1EN,
162+
.apbbus = APB12,
163+
},
164+
};
165+
166+
#define SPI_NUMOF ARRAY_SIZE(spi_config)
167+
/** @} */
168+
169+
#ifdef __cplusplus
170+
}
171+
#endif
172+
173+
/** @} */

‎cpu/stm32/Makefile.cmsis‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@ PKG_NAME=stm32cmsis
33
# The package URL depends on the family of the target STM32
44
PKG_URL=https://github.com/STMicroelectronics/cmsis_device_$(CPU_FAM)
55

6-
# v1.1.0
7-
PKG_VERSION_c0=7e32bf9d8117ee4c8f6a1d138b814fc24bf4c906
6+
# v1.3.0
7+
PKG_VERSION_c0=517611273f835ffe95318947647bc1408f69120d
88
# v2.3.7
99
PKG_VERSION_f0=3973d99a89ac5fdf1f2593abc29a73d2981ce94a
1010
# v4.3.4

‎cpu/stm32/kconfigs/c0/Kconfig.lines‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,10 +14,18 @@ config CPU_LINE_STM32C031XX
1414
bool
1515
select CPU_FAM_C0
1616

17+
config CPU_LINE_STM32C051XX
18+
bool
19+
select CPU_FAM_C0
20+
1721
config CPU_LINE_STM32C071XX
1822
bool
1923
select CPU_FAM_C0
2024

2125
config CPU_LINE_STM32C091XX
2226
bool
2327
select CPU_FAM_C0
28+
29+
config CPU_LINE_STM32C092XX
30+
bool
31+
select CPU_FAM_C0

0 commit comments

Comments
 (0)