diff --git a/.murdock b/.murdock index 416a7cffbfbf..39955956fcbf 100755 --- a/.murdock +++ b/.murdock @@ -6,21 +6,8 @@ #export APPS="examples/basic/hello-world tests/unittests" QUICKBUILD_BOARDS=" -adafruit-itsybitsy-m4 -atmega256rfr2-xpro -esp32-wroom-32 -esp32s3-devkit -frdm-k64f -hifive1b -msb-430 -msba2 -native32 -native64 -nrf52840dk -qn9080dk -samr21-xpro -stk3200 -stm32f429i-disc1" +rpi-pico-2-riscv +rpi-pico-2-arm" # this configures boards that are available via pifleet case "${CI_MURDOCK_PROJECT}" in diff --git a/boards/Makefile b/boards/Makefile index ae92f259427e..a0d19ba7ac5b 100644 --- a/boards/Makefile +++ b/boards/Makefile @@ -6,6 +6,9 @@ DIRS += $(RIOTBOARD)/common/init ifneq (,$(filter boards_common_adafruit-nrf52-bootloader,$(USEMODULE))) DIRS += $(RIOTBOARD)/common/adafruit-nrf52-bootloader endif +ifneq (,$(filter boards_common_rpi_pico_2,$(USEMODULE))) + DIRS += $(RIOTBOARD)/common/rpi-pico-2 +endif ifneq (,$(filter boards_common_seeedstudio-xiao-nrf52840,$(USEMODULE))) DIRS += $(RIOTBOARD)/common/seeedstudio-xiao-nrf52840 endif diff --git a/boards/Makefile.features b/boards/Makefile.features index 895bb1116850..42c2bf3852fd 100644 --- a/boards/Makefile.features +++ b/boards/Makefile.features @@ -1,4 +1,7 @@ # SORT THIS ALPHABETICALLY BY COMMON BOARD NAME! +ifneq (,$(filter boards_common_rpi_pico_2,$(USEMODULE))) + include $(RIOTBOARD)/common/rpi-pico-2/Makefile.features +endif ifneq (,$(filter boards_common_seeedstudio-xiao-nrf52840,$(USEMODULE))) include $(RIOTBOARD)/common/seeedstudio-xiao-nrf52840/Makefile.features endif diff --git a/boards/Makefile.include b/boards/Makefile.include index 4fb738b7adb0..6168b3f21ada 100644 --- a/boards/Makefile.include +++ b/boards/Makefile.include @@ -2,6 +2,9 @@ ifneq (,$(filter boards_common_adafruit-nrf52-bootloader,$(USEMODULE))) include $(RIOTBOARD)/common/adafruit-nrf52-bootloader/Makefile.include endif +ifneq (,$(filter boards_common_rpi_pico_2,$(USEMODULE))) + include $(RIOTBOARD)/common/rpi-pico-2/Makefile.include +endif ifneq (,$(filter boards_common_seeedstudio-xiao-nrf52840,$(USEMODULE))) include $(RIOTBOARD)/common/seeedstudio-xiao-nrf52840/Makefile.include endif diff --git a/boards/common/rpi-pico-2/Makefile b/boards/common/rpi-pico-2/Makefile new file mode 100644 index 000000000000..67b301c3b4fa --- /dev/null +++ b/boards/common/rpi-pico-2/Makefile @@ -0,0 +1,3 @@ +MODULE = boards_common_rpi_pico_2 + +include $(RIOTBASE)/Makefile.base diff --git a/boards/common/rpi-pico-2/Makefile.features b/boards/common/rpi-pico-2/Makefile.features new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/boards/common/rpi-pico-2/Makefile.include b/boards/common/rpi-pico-2/Makefile.include new file mode 100644 index 000000000000..b98f525a7a27 --- /dev/null +++ b/boards/common/rpi-pico-2/Makefile.include @@ -0,0 +1,2 @@ +# add the common header files to the include path +INCLUDES += -I$(RIOTBOARD)/common/rpi-pico-2/include diff --git a/boards/rpi-pico-2/board.c b/boards/common/rpi-pico-2/board.c similarity index 100% rename from boards/rpi-pico-2/board.c rename to boards/common/rpi-pico-2/board.c diff --git a/boards/rpi-pico-2/include/board.h b/boards/common/rpi-pico-2/include/board.h similarity index 88% rename from boards/rpi-pico-2/include/board.h rename to boards/common/rpi-pico-2/include/board.h index 0cdbc0d51ff6..563cb74cafb1 100644 --- a/boards/rpi-pico-2/include/board.h +++ b/boards/common/rpi-pico-2/include/board.h @@ -7,7 +7,7 @@ #pragma once /** - * @ingroup boards_rpi_pico_2 + * @ingroup boards_rpi_pico_2_arm * @{ * * @file @@ -16,11 +16,10 @@ * @author Tom Hert */ -#include "RP2350.h" #include "cpu.h" -#include "cpu_conf.h" #include "periph_conf.h" -#include "periph_cpu.h" + +#include "periph/gpio.h" /** GPIO Pin ID for the onboard LED */ #define LED0_PIN_ID 25u diff --git a/boards/rpi-pico-2/include/gpio_params.h b/boards/common/rpi-pico-2/include/gpio_params.h similarity index 100% rename from boards/rpi-pico-2/include/gpio_params.h rename to boards/common/rpi-pico-2/include/gpio_params.h diff --git a/boards/common/rpi-pico-2/include/periph_conf.h b/boards/common/rpi-pico-2/include/periph_conf.h new file mode 100644 index 000000000000..aa7d31c0a922 --- /dev/null +++ b/boards/common/rpi-pico-2/include/periph_conf.h @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: 2025 Tom Hert + * SPDX-FileCopyrightText: 2025 HAW Hamburg + * SPDX-License-Identifier: LGPL-2.1-only + */ + +#pragma once + +/** + * @ingroup boards_rpi_pico_2_arm + * @{ + * + * @file + * @brief Board periph definitions for the Raspberry Pi Pico 2 + * + * @author Tom Hert + */ + +#include + +#include "RP2350.h" +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Configuration details for an UART interface + */ +typedef struct { + UART0_Type *dev; /**< Base address of the I/O registers of the device */ + gpio_t rx_pin; /**< GPIO pin to use for RX */ + gpio_t tx_pin; /**< GPIO pin to use for TX */ + IRQn_Type irqn; /**< IRQ number of the UART interface */ +} uart_conf_t; + +static const uart_conf_t uart_config[] = { + { + .dev = UART0, + .rx_pin = GPIO_PIN(0, 1), + .tx_pin = GPIO_PIN(0, 0), + .irqn = UART0_IRQ_IRQn + }, + { + .dev = UART1, + .rx_pin = GPIO_PIN(0, 9), + .tx_pin = GPIO_PIN(0, 8), + .irqn = UART1_IRQ_IRQn + } +}; + +#define UART_0_ISR (isr_uart0) +#define UART_1_ISR (isr_uart1) + +#define UART_NUMOF ARRAY_SIZE(uart_config) + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/boards/rpi-pico-2/Kconfig b/boards/rpi-pico-2-arm/Kconfig similarity index 61% rename from boards/rpi-pico-2/Kconfig rename to boards/rpi-pico-2-arm/Kconfig index d0ac0bb5744c..0733e813ef55 100644 --- a/boards/rpi-pico-2/Kconfig +++ b/boards/rpi-pico-2-arm/Kconfig @@ -3,9 +3,9 @@ # SPDX-License-Identifier: LGPL-2.1-only config BOARD - default "rpi-pico-2" if BOARD_RPI_PICO_2 + default "rpi-pico-2-arm" if BOARD_RPI_PICO_2_ARM -config BOARD_RPI_PICO_2 +config BOARD_RPI_PICO_2_ARM bool default y - select CPU_MODEL_RP2350 + select CPU_MODEL_RP2350_ARM diff --git a/boards/rpi-pico-2/Makefile b/boards/rpi-pico-2-arm/Makefile similarity index 100% rename from boards/rpi-pico-2/Makefile rename to boards/rpi-pico-2-arm/Makefile diff --git a/boards/rpi-pico-2-arm/Makefile.dep b/boards/rpi-pico-2-arm/Makefile.dep new file mode 100644 index 000000000000..73d807ad5db4 --- /dev/null +++ b/boards/rpi-pico-2-arm/Makefile.dep @@ -0,0 +1 @@ +USEMODULE += boards_common_rpi_pico_2 diff --git a/boards/rpi-pico-2-arm/Makefile.features b/boards/rpi-pico-2-arm/Makefile.features new file mode 100644 index 000000000000..f6baa706cf83 --- /dev/null +++ b/boards/rpi-pico-2-arm/Makefile.features @@ -0,0 +1 @@ +CPU := rp2350_arm diff --git a/boards/rpi-pico-2/Makefile.include b/boards/rpi-pico-2-arm/Makefile.include similarity index 81% rename from boards/rpi-pico-2/Makefile.include rename to boards/rpi-pico-2-arm/Makefile.include index b80aa5b4da25..94a0f6a0aec4 100644 --- a/boards/rpi-pico-2/Makefile.include +++ b/boards/rpi-pico-2-arm/Makefile.include @@ -1,4 +1,4 @@ -CPU_MODEL := RP2350 +CPU_MODEL := RP2350_ARM PORT_LINUX ?= /dev/ttyACM0 # JLink isnt tested yet on RP2350 diff --git a/boards/rpi-pico-2/dist/openocd.cfg b/boards/rpi-pico-2-arm/dist/openocd.cfg similarity index 50% rename from boards/rpi-pico-2/dist/openocd.cfg rename to boards/rpi-pico-2-arm/dist/openocd.cfg index 69faf2c879bd..85a621c1e613 100644 --- a/boards/rpi-pico-2/dist/openocd.cfg +++ b/boards/rpi-pico-2-arm/dist/openocd.cfg @@ -1,7 +1,10 @@ echo "Make sure to use the Raspberry Pi OpenOCD version!" +echo "For further details see Appendix A Building OpenOCD:" +echo "https://datasheets.raspberrypi.com/pico/getting-started-with-pico.pdf" source [find target/rp2350.cfg] -set USE_CORE 0 +set USE_CORE SMP set RESCUE 1 $_TARGETNAME_0 configure -rtos auto adapter speed 5000 rp2350.dap.core1 cortex_m reset_config sysresetreq +rp2350.dap.core0 cortex_m reset_config sysresetreq diff --git a/boards/rpi-pico-2-arm/doc.md b/boards/rpi-pico-2-arm/doc.md new file mode 100644 index 000000000000..12b28d7b9929 --- /dev/null +++ b/boards/rpi-pico-2-arm/doc.md @@ -0,0 +1,5 @@ +@defgroup boards_rpi_pico_2_arm Raspberry Pi Pico 2 +@ingroup boards +@brief Support for the RP2350 based Raspberry Pi Pico board + +See @ref boards_rpi_pico_2_riscv for further information. diff --git a/boards/rpi-pico-2-riscv/Kconfig b/boards/rpi-pico-2-riscv/Kconfig new file mode 100644 index 000000000000..e9e2ff4413ab --- /dev/null +++ b/boards/rpi-pico-2-riscv/Kconfig @@ -0,0 +1,11 @@ +# SPDX-FileCopyrightText: 2025 Tom Hert +# SPDX-FileCopyrightText: 2025 HAW Hamburg +# SPDX-License-Identifier: LGPL-2.1-only + +config BOARD + default "rpi-pico-2-riscv" if BOARD_RPI_PICO_2_RISCV + +config BOARD_RPI_PICO_2_RISV + bool + default y + select CPU_MODEL_RP2350_RISCV diff --git a/boards/rpi-pico-2-riscv/Makefile b/boards/rpi-pico-2-riscv/Makefile new file mode 100644 index 000000000000..f8fcbb53a065 --- /dev/null +++ b/boards/rpi-pico-2-riscv/Makefile @@ -0,0 +1,3 @@ +MODULE = board + +include $(RIOTBASE)/Makefile.base diff --git a/boards/rpi-pico-2-riscv/Makefile.dep b/boards/rpi-pico-2-riscv/Makefile.dep new file mode 100644 index 000000000000..73d807ad5db4 --- /dev/null +++ b/boards/rpi-pico-2-riscv/Makefile.dep @@ -0,0 +1 @@ +USEMODULE += boards_common_rpi_pico_2 diff --git a/boards/rpi-pico-2-riscv/Makefile.features b/boards/rpi-pico-2-riscv/Makefile.features new file mode 100644 index 000000000000..1df8fa1b8571 --- /dev/null +++ b/boards/rpi-pico-2-riscv/Makefile.features @@ -0,0 +1 @@ +CPU := rp2350_riscv diff --git a/boards/rpi-pico-2-riscv/Makefile.include b/boards/rpi-pico-2-riscv/Makefile.include new file mode 100644 index 000000000000..b440109c92d5 --- /dev/null +++ b/boards/rpi-pico-2-riscv/Makefile.include @@ -0,0 +1,7 @@ +CPU_MODEL := RP2350_RISCV +PORT_LINUX ?= /dev/ttyACM0 + +# JLink isnt tested yet on RP2350 +# ifeq ($(PROGRAMMER),jlink) +# JLINK_DEVICE = RP2350_M33_0 +# endif diff --git a/boards/rpi-pico-2-riscv/dist/openocd.cfg b/boards/rpi-pico-2-riscv/dist/openocd.cfg new file mode 100644 index 000000000000..c90d870b123c --- /dev/null +++ b/boards/rpi-pico-2-riscv/dist/openocd.cfg @@ -0,0 +1,8 @@ +echo "Make sure to use the Raspberry Pi OpenOCD version!" +echo "For further details see Appendix A Building OpenOCD:" +echo "https://datasheets.raspberrypi.com/pico/getting-started-with-pico.pdf" +source [find target/rp2350-riscv.cfg] +set USE_CORE SMP +set RESCUE 1 +$_TARGETNAME_0 configure -rtos auto +adapter speed 5000 diff --git a/boards/rpi-pico-2/doc.md b/boards/rpi-pico-2-riscv/doc.md similarity index 82% rename from boards/rpi-pico-2/doc.md rename to boards/rpi-pico-2-riscv/doc.md index f441304714cd..8cdec6378cd2 100644 --- a/boards/rpi-pico-2/doc.md +++ b/boards/rpi-pico-2-riscv/doc.md @@ -1,9 +1,9 @@ -@defgroup boards_rpi_pico_2 Raspberry Pi Pico 2 +@defgroup boards_rpi_pico_2_riscv Raspberry Pi Pico 2 @ingroup boards -@brief Support for the RP2350 based Raspberry Pi Pico board +@brief Support for the RP2350 RISCV based Raspberry Pi Pico board @warning The support for the Raspberry Pi Pico 2 is still in a very early stage! -See [Known Issues](#rpi_pico_2_known_issues). +See [Known Issues](#rpi_pico_2_riscv_known_issues). ## Overview @@ -55,6 +55,12 @@ If you are using picotool, you need to hold the bootselect button your computer via USB. This will put the board into bootloader mode, allowing you to flash it. +Generally while Picotool is the easiest way to flash the board, +it does not allow for debugging using GDB. + +It does tend to be more reliable than OpenOCD though, +especially when switching between RISC-V and ARM cores. + ### Flashing using OpenOCD If you have two Raspberry Pi Pico boards, @@ -76,13 +82,25 @@ To do this, you need to connect the board to your computer and use the following command: ```bash -PROGRAMMER=openocd BOARD=rpi-pico-2 make flash +PROGRAMMER=openocd BOARD=rpi-pico-2-riscv make flash +``` + +or, if you want to use the CortexM: + +```bash +PROGRAMMER=openocd BOARD=rpi-pico-2-arm make flash ``` You can then debug your application using GDB with the following command: ```bash -PROGRAMMER=openocd BOARD=rpi-pico-2 make debug +PROGRAMMER=openocd BOARD=rpi-pico-2-riscv make debug +``` + +or, if you want to use the CortexM: + +```bash +PROGRAMMER=openocd BOARD=rpi-pico-2-arm make debug ``` ### Flashing using Picotool @@ -90,7 +108,13 @@ PROGRAMMER=openocd BOARD=rpi-pico-2 make debug Simply connect the board to your computer via USB and use the following command: ```bash -BOARD=rpi-pico-2 make flash +BOARD=rpi-pico-2-riscv make flash +``` + +or, if you want to use the CortexM: + +```bash +BOARD=rpi-pico-2-arm make flash ``` This is the default method for flashing the Raspberry Pi Pico 2. @@ -100,17 +124,16 @@ However, it does not allow for debugging using GDB. RIOT will download and install the Picotool locally in the RIOT folder. This process will take some minutes to complete. -## Known Issues {#rpi_pico_2_known_issues} +## Known Issues {#rpi_pico_2_riscv_known_issues} Currently RP2350 support is rather minimal, as such peripheral support is extremely limited. The following peripherals are supported: +- XH3IRQ RISC-V Interrupt Controller (CortexM Interrupts also work) - GPIO -- Non-configurable write-only UART (UART0 using Pin 0 and 1) +- UART - The UART Baudrate is set to 115200. - UART does not work via USB, you need to connect it directly to the GPIO pins. More peripherals will be added in the future. -It should also be noted that we currently only support the Cortex M33 cores, -not the RISC-V Hazard cores. diff --git a/boards/rpi-pico-2/Makefile.features b/boards/rpi-pico-2/Makefile.features deleted file mode 100644 index b19f996d1407..000000000000 --- a/boards/rpi-pico-2/Makefile.features +++ /dev/null @@ -1 +0,0 @@ -CPU := rp2350 diff --git a/boards/rpi-pico-2/include/periph_conf.h b/boards/rpi-pico-2/include/periph_conf.h deleted file mode 100644 index ed237d2c3b58..000000000000 --- a/boards/rpi-pico-2/include/periph_conf.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2025 Tom Hert - * SPDX-FileCopyrightText: 2025 HAW Hamburg - * SPDX-License-Identifier: LGPL-2.1-only - */ - -#pragma once - -#include - -#include "RP2350.h" -#include "periph_cpu.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif diff --git a/cpu/riscv_common/Makefile b/cpu/riscv_common/Makefile index e09377cd1e39..880129078d0d 100644 --- a/cpu/riscv_common/Makefile +++ b/cpu/riscv_common/Makefile @@ -1,3 +1,3 @@ -DIRS = periph +DIRS += periph include $(RIOTBASE)/Makefile.base diff --git a/cpu/riscv_common/include/xh3irq.h b/cpu/riscv_common/include/xh3irq.h new file mode 100644 index 000000000000..89c6489345e1 --- /dev/null +++ b/cpu/riscv_common/include/xh3irq.h @@ -0,0 +1,90 @@ +/* + * SPDX-FileCopyrightText: 2025 Tom Hert + * SPDX-FileCopyrightText: 2025 HAW Hamburg + * SPDX-License-Identifier: LGPL-2.1-only + */ + +#pragma once + +#include + +#include "panic.h" +#include "cpu_conf.h" + +/** + * @ingroup cpu_riscv_common + * @{ + * + * @file + * @brief xh3irq.h interrupt controller support + * + * @author Tom Hert + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** CPU specific interrupt vector table + * @see 3.2 Interrupts and IRQn_Type in RP2350.h + */ +extern const void *vector_cpu[CPU_IRQ_NUMOF]; + +/** + * Hazard3 has internal registers to individually filter which + * external IRQs appear in meip. When meip is 1, + * this indicates there is at least one external interrupt + * which is asserted (hence pending in mieipa), enabled in meiea, + * and of priority greater than or equal to the current + * preemption level in meicontext.preempt. + */ +#define MEIP_OFFSET 11 +/** Mask to extract the MEIP bit from MIP/MISE */ +#define MEIP_MASK 0x1 +/** + * Index of the highest-priority active external interrupt. + * Zero when no external interrupts with sufficient priority + * are both pending and enabled + */ +#define MEINEXT_IRQ_OFFSET 2 +/** Mask to extract the IRQ number from MEINEXT */ +#define MEINEXT_MASK 0x1FF +/** XH3IRQ Interrupt arrays have a window to access the IRQ bits */ +#define INTERRUPT_ARRAY_MASK_OFFSET 16 + +/** + * @brief Check if there are any pending interrupts + * @return 1 if there are pending interrupts, 0 otherwise + */ +uint32_t xh3irq_has_pending(void); + +/** + * @brief The main IRQ handler, called from the assembly IRQ handler + * @note This function must clear the pending interrupt in the interrupt controller + */ +void xh3irq_handler(void); + +/** + * @brief Enable the given IRQ number + * @param irq_no The IRQ number to enable + */ +void xh3irq_enable_irq(uint32_t irq_no); + +/** + * @brief Disable the given IRQ number + * @param irq_no The IRQ number to disable + */ +void xh3irq_disable_irq(uint32_t irq_no); + +/** + * @brief Force the given IRQ number to be pending + * @param irq_no The IRQ number to force + * @note The IRQ still must be enabled to be handled + */ +void xh3irq_force_irq(uint32_t irq_no); + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/cpu/riscv_common/irq_arch.c b/cpu/riscv_common/irq_arch.c index f37b58e55050..6bff5a9eef60 100644 --- a/cpu/riscv_common/irq_arch.c +++ b/cpu/riscv_common/irq_arch.c @@ -32,10 +32,14 @@ #include "clic.h" #include "architecture.h" +#if MODULE_PERIPH_XH3IRQ || DOXYGEN +# include "xh3irq.h" +#endif + #include "vendor/riscv_csr.h" /* Default state of mstatus register */ -#define MSTATUS_DEFAULT (MSTATUS_MPP | MSTATUS_MPIE) +#define MSTATUS_DEFAULT (MSTATUS_MPP | MSTATUS_MPIE) volatile int riscv_in_isr = 0; @@ -83,8 +87,7 @@ void riscv_irq_init(void) /** * @brief Global trap and interrupt handler */ -__attribute((used)) -static void handle_trap(uword_t mcause) +__attribute((used)) static void handle_trap(uword_t mcause) { /* Tell RIOT to set sched_context_switch_request instead of * calling thread_yield(). */ @@ -92,11 +95,55 @@ static void handle_trap(uword_t mcause) uword_t trap = mcause & CPU_CSR_MCAUSE_CAUSE_MSK; +#ifdef DEVELHELP + printf("Trap: mcause=0x%" PRIx32 " mepc=0x%lx mtval=0x%lx\n", + (uint32_t)mcause, read_csr(mepc), read_csr(mtval)); + + /* See https://riscv.github.io/riscv-isa-manual/snapshot/privileged/#mcause */ + if ((mcause & ~MCAUSE_INT) <= 0xb) { + const char *error_messages[] = { + "Instruction address misaligned", + "Instruction access fault", + "Illegal instruction", + "Breakpoint", + "Load address misaligned", + "Load access fault", + "Store/AMO address misaligned", + "Store/AMO access fault", + "Environment call from U-mode", + "Environment call from S-mode", + NULL, + "Environment call from M-mode", + "Instruction page fault", + "Load page fault", + NULL, + "Store/AMO page fault", + "Double trap", + NULL, + "Software check", + "Hardware error" + }; + + uword_t cause_code = mcause & ~MCAUSE_INT; + if (cause_code <= (ARRAY_SIZE(error_messages) - 1)) { + if (error_messages[cause_code] != NULL) { + printf("Machine Cause Error 0x%lx: %s\n", + cause_code, error_messages[cause_code] + ); + } else { + printf("Machine Cause indicates that 0x%lx" + " is a reserved or custom cause code\n", + cause_code + ); + } + } + } +#endif + /* Check for INT or TRAP */ if ((mcause & MCAUSE_INT) == MCAUSE_INT) { /* Cause is an interrupt - determine type */ switch (mcause & MCAUSE_CAUSE) { - #ifdef MODULE_PERIPH_CORETIMER case IRQ_M_TIMER: /* Handle timer interrupt */ @@ -108,6 +155,9 @@ static void handle_trap(uword_t mcause) if (IS_ACTIVE(MODULE_PERIPH_PLIC)) { plic_isr_handler(); } + if (IS_ACTIVE(MODULE_PERIPH_XH3IRQ)) { + xh3irq_handler(); + } break; default: diff --git a/cpu/riscv_common/ldscripts/riscv_base.ld b/cpu/riscv_common/ldscripts/riscv_base.ld index c77f152a1963..2718816b318a 100644 --- a/cpu/riscv_common/ldscripts/riscv_base.ld +++ b/cpu/riscv_common/ldscripts/riscv_base.ld @@ -41,6 +41,13 @@ SECTIONS .text : { + /* + * Keep picobin block used by RP2350. + * This gives the Pico2 bootloader metadata about the + * exact configuration we are trying to run. + * E.g. secure mode, riscv, arm, etc. + */ + KEEP(*(SORT(.picobin_block*))) *(.text.unlikely .text.unlikely.*) *(.text.startup .text.startup.*) *(.text .text.*) diff --git a/cpu/riscv_common/periph/xh3irq.c b/cpu/riscv_common/periph/xh3irq.c new file mode 100644 index 000000000000..9d3fc90c9b34 --- /dev/null +++ b/cpu/riscv_common/periph/xh3irq.c @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: 2025 Tom Hert + * SPDX-FileCopyrightText: 2025 HAW Hamburg + * SPDX-License-Identifier: LGPL-2.1-only + */ + +#include + +#include "bit.h" +#include "xh3irq.h" + +uint32_t xh3irq_has_pending(void) +{ + /* + * Get MEIP which is the external interrupt pending bit + * from the Machine Interrupt Pending Register address + */ + uint32_t mip_reg = read_csr(0x344); + uint32_t meip = bit_check32(&mip_reg, MEIP_OFFSET); + + return (meip != 0); +} + +void xh3irq_handler(void) +{ + /* + * Get MEINEXT at 0xbe4 which is the next highest interrupt to handle (Bit 2-10). + * This will also automagically clear the interrupt (See 3.8.6.1.2.) + * + * Contains the index of the highest-priority external interrupt + * which is both asserted in meipa and enabled in meiea, left- + * shifted by 2 so that it can be used to index an array of 32-bit + * function pointers. If there is no such interrupt, the MSB is set. + */ + uint32_t meinext = (read_csr(0xBE4) >> MEINEXT_IRQ_OFFSET) & MEINEXT_MASK; + + void (*isr)(void) = (void (*)(void)) vector_cpu[meinext]; +#ifdef DEVELHELP + printf("Calling isr %p for irq %ld\n", isr, meinext); +#endif + isr(); +} + +void _meiea_set_req_bit(uint32_t irq_no, uint32_t bit_val) +{ + uint32_t index = irq_no / INTERRUPT_ARRAY_MASK_OFFSET; + uint32_t mask = bit_val << (irq_no % INTERRUPT_ARRAY_MASK_OFFSET); + + /* + * 0xbe0 is the external interrupt enable array. + * The array contains a read-write bit for each external interrupt request: + * a 1 bit indicates that interrupt is currently enabled. + * There are up to 512 external interrupts. + * The upper half of this register contains a 16-bit window into the full + * 512-bit vector. The window is indexed by the 5 LSBs of the write data. + */ + __asm__ volatile( + "csrs 0xbe0, %0\n" + : : "r"(index | (mask << INTERRUPT_ARRAY_MASK_OFFSET)) + ); +} + +void xh3irq_enable_irq(uint32_t irq_no) +{ + _meiea_set_req_bit(irq_no, 1); +} + +void xh3irq_disable_irq(uint32_t irq_no) +{ + _meiea_set_req_bit(irq_no, 0); +} + +void xh3irq_force_irq(uint32_t irq_no) +{ + uint32_t index = irq_no / INTERRUPT_ARRAY_MASK_OFFSET; + uint32_t mask = 1u << (irq_no % INTERRUPT_ARRAY_MASK_OFFSET); + + /** + * 0xbe2 is the external interrupt force array. + * See _meiea_set_req_bit / 0xbe0 for more details. + */ + __asm__ volatile( + "csrs 0xbe2, %0\n" + : : "r"(index | (mask << INTERRUPT_ARRAY_MASK_OFFSET))); +} diff --git a/cpu/rp2350/Makefile.dep b/cpu/rp2350/Makefile.dep deleted file mode 100644 index 75b95e8112ed..000000000000 --- a/cpu/rp2350/Makefile.dep +++ /dev/null @@ -1,3 +0,0 @@ -USEPKG += picosdk - -include $(RIOTCPU)/cortexm_common/Makefile.dep diff --git a/cpu/rp2350/periph/uart.c b/cpu/rp2350/periph/uart.c deleted file mode 100644 index 4b6c21677e72..000000000000 --- a/cpu/rp2350/periph/uart.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2025 Tom Hert - * SPDX-FileCopyrightText: 2025 HAW Hamburg - * SPDX-License-Identifier: LGPL-2.1-only - */ - -/** - * @ingroup cpu_rp2350 - * @{ - * - * @file - * @brief UART implementation for the RP2350 - * - * @author Tom Hert - */ - -#include "periph/uart.h" - -#include "periph_cpu.h" - -int uart_init(uart_t uart, uint32_t baud, uart_rx_cb_t rx_cb, void *arg) { - (void)uart; - (void)baud; - (void)rx_cb; - (void)arg; - /* Set the UART pins to the correct function */ - IO_BANK0->GPIO0_CTRL = FUNCTION_SELECT_UART; - IO_BANK0->GPIO1_CTRL = FUNCTION_SELECT_UART; - /* Clear the ISO bits */ - atomic_clear(&PADS_BANK0->GPIO0, PADS_BANK0_ISO_BITS); - atomic_clear(&PADS_BANK0->GPIO1, PADS_BANK0_ISO_BITS); - /* Set IE bit for gpio1 */ - PADS_BANK0->GPIO1 = PADS_BANK0->GPIO1 | PADS_BANK0_GPIO0_IE_BITS; - - /* We reset UART0 here, so we can be sure it is in a known state */ - reset_component(RESET_UART0, RESET_UART0); - - UART0->UARTIBRD = IBRD; - UART0->UARTFBRD = FBRD; - uart_mode(0, 8, UART_PARITY_NONE, 1); - return 0; -} - -int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t parity, - uart_stop_bits_t stop_bits) { - (void)uart; - (void)data_bits; - (void)stop_bits; - atomic_clear(&UART0->UARTCR, UART_UARTCR_UARTEN_BITS | UART_UARTCR_RXE_BITS | - UART_UARTCR_TXE_BITS); - - /* Set the data bits, parity, and stop bits - * Set to 8 bits (0b11) based on Table 1035 page 976 - */ - UART0->UARTLCR_H = 0b11 << 5; - - switch (parity) { - case UART_PARITY_NONE: - break; - default: - return UART_NOMODE; - } - - UART0->UARTCR = UART_UARTCR_TXE_BITS | UART_UARTCR_UARTEN_BITS; - - return UART_OK; -} - -void uart_write(uart_t uart, const uint8_t *data, size_t len) { - (void)uart; - for (size_t i = 0; i < len; i++) { - UART0->UARTDR = data[i]; - /* Wait until the TX FIFO is empty before sending the next byte */ - while (!(UART0->UARTFR & UART_UARTFR_TXFE_BITS)) { - } - } -} - -void uart_poweron(uart_t uart) { - (void)uart; -} -void uart_poweroff(uart_t uart) { - (void)uart; -} - -/** @} */ diff --git a/cpu/rp2350/Kconfig b/cpu/rp2350_arm/Kconfig similarity index 55% rename from cpu/rp2350/Kconfig rename to cpu/rp2350_arm/Kconfig index 867bcf84f90b..a53b79b69122 100644 --- a/cpu/rp2350/Kconfig +++ b/cpu/rp2350_arm/Kconfig @@ -2,22 +2,22 @@ # SPDX-FileCopyrightText: 2025 HAW Hamburg # SPDX-License-Identifier: LGPL-2.1-only -config CPU_FAM_RP2350 +config CPU_FAM_RP2350_ARM bool select CPU_CORE_CORTEX_M33 config CPU_FAM - default "RP2350" if CPU_FAM_RP2350 + default "RP2350_ARM" if CPU_FAM_RP2350_ARM -config CPU_MODEL_RP2350 +config CPU_MODEL_RP2350_ARM bool - select CPU_FAM_RP2350 + select CPU_FAM_RP2350_ARM config CPU_MODEL - default "RP2350" if CPU_MODEL_RP2350 + default "RP2350_ARM" if CPU_MODEL_RP2350_ARM config CPU - default "rp2350" if CPU_FAM_RP2350 + default "rp2350_arm" if CPU_FAM_RP2350_ARM source "$(RIOTCPU)/cortexm_common/Kconfig" diff --git a/cpu/rp2350_arm/Makefile b/cpu/rp2350_arm/Makefile new file mode 100644 index 000000000000..d097b987ce69 --- /dev/null +++ b/cpu/rp2350_arm/Makefile @@ -0,0 +1,8 @@ +# define the module that is built +MODULE = cpu + +# add a list of subdirectories, that should also be built +DIRS += $(RIOTCPU)/rp2350_common +DIRS += $(RIOTCPU)/cortexm_common + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/rp2350_arm/Makefile.dep b/cpu/rp2350_arm/Makefile.dep new file mode 100644 index 000000000000..0c4c8e18303e --- /dev/null +++ b/cpu/rp2350_arm/Makefile.dep @@ -0,0 +1,4 @@ +USEMODULE += cortexm_common + +include $(RIOTCPU)/rp2350_common/Makefile.dep +include $(RIOTCPU)/cortexm_common/Makefile.dep diff --git a/cpu/rp2350/Makefile.features b/cpu/rp2350_arm/Makefile.features similarity index 58% rename from cpu/rp2350/Makefile.features rename to cpu/rp2350_arm/Makefile.features index 5fc956bd1ba3..049467c49595 100644 --- a/cpu/rp2350/Makefile.features +++ b/cpu/rp2350_arm/Makefile.features @@ -1,9 +1,7 @@ CPU_CORE := cortex-m33 CPU_FAM := RP2350 CPU_ARCH = armv8m -CPU_MODEL = rp2350 +CPU_MODEL = rp2350_cortexm +include $(RIOTCPU)/rp2350_common/Makefile.features include $(RIOTCPU)/cortexm_common/Makefile.features - -FEATURES_PROVIDED += periph_gpio -FEATURES_PROVIDED += periph_uart diff --git a/cpu/rp2350_arm/Makefile.include b/cpu/rp2350_arm/Makefile.include new file mode 100644 index 000000000000..eb5931c3cc04 --- /dev/null +++ b/cpu/rp2350_arm/Makefile.include @@ -0,0 +1,18 @@ +# CPU and architecture specific flags +CFLAGS += -D$(CPU_MODEL) +CFLAGS += -DROM_START_ADDR=$(ROM_START_ADDR) +CFLAGS += -DRAM_START_ADDR=$(RAM_START_ADDR) + +# Linker flags +LINKFLAGS += -mcpu=$(CPU_ARCH) -mthumb +LINKFLAGS += -Wl,--gc-sections +LINKFLAGS += -Wl,--start-group -lc -lm -Wl,--end-group + +# Vector table configuration +VECTORS_O ?= $(BINDIR)/cpu/vectors.o +VECTORS_FILE := $(RIOTCPU)/rp2350_common/vectors.c + +include $(RIOTCPU)/rp2350_common/Makefile.include + +# Include the base Cortex-M makefile +include $(RIOTMAKE)/arch/cortexm.inc.mk diff --git a/cpu/rp2350_arm/cpu.c b/cpu/rp2350_arm/cpu.c new file mode 100644 index 000000000000..d89d5ab270c9 --- /dev/null +++ b/cpu/rp2350_arm/cpu.c @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2025 Tom Hert + * SPDX-FileCopyrightText: 2025 HAW Hamburg + * SPDX-License-Identifier: LGPL-2.1-only + */ + +/** + * @ingroup cpu_rp2350_arm + * @{ + * + * @file + * @brief CPU initialization implementation for the RP2350 + * + * @author Tom Hert + */ + +#include "cpu.h" +#include "periph_cpu.h" + +void cpu_init(void) +{ + cortexm_init(); + rp2350_init(); +} + +/** @} */ diff --git a/cpu/rp2350_arm/doc.md b/cpu/rp2350_arm/doc.md new file mode 100644 index 000000000000..aefe5eef356e --- /dev/null +++ b/cpu/rp2350_arm/doc.md @@ -0,0 +1,5 @@ +@defgroup cpu_rp2350_arm RP2350 MCUs +@ingroup cpu +@brief RP2350 MCU code and definitions + +This module contains the code and definitions for MCUs of the RP2350 family used by the Pi Pico 2. diff --git a/cpu/rp2350/include/cpu_conf.h b/cpu/rp2350_arm/include/cpu_conf.h similarity index 80% rename from cpu/rp2350/include/cpu_conf.h rename to cpu/rp2350_arm/include/cpu_conf.h index 652be6fe27e5..b6d38c449e7c 100644 --- a/cpu/rp2350/include/cpu_conf.h +++ b/cpu/rp2350_arm/include/cpu_conf.h @@ -7,7 +7,7 @@ #pragma once /** - * @ingroup cpu_rp2350 + * @ingroup cpu_rp2350_arm * @{ * @file * @brief CPU configuration for the RP2350 @@ -21,6 +21,8 @@ #define CPU_DEFAULT_IRQ_PRIO 1u #define CPU_IRQ_NUMOF 52u +/** This tells rp2350_common that we are using the ARM core */ +#define RP2350_USE_ARM 1 #ifdef __cplusplus extern "C" { diff --git a/cpu/rp2350/ldscripts/RP2350.ld b/cpu/rp2350_arm/ldscripts/RP2350_ARM.ld similarity index 100% rename from cpu/rp2350/ldscripts/RP2350.ld rename to cpu/rp2350_arm/ldscripts/RP2350_ARM.ld diff --git a/cpu/rp2350/picobin_block.s b/cpu/rp2350_arm/picobin_block.s similarity index 100% rename from cpu/rp2350/picobin_block.s rename to cpu/rp2350_arm/picobin_block.s diff --git a/cpu/rp2350/Makefile b/cpu/rp2350_common/Makefile similarity index 51% rename from cpu/rp2350/Makefile rename to cpu/rp2350_common/Makefile index 33d57306d1a7..880129078d0d 100644 --- a/cpu/rp2350/Makefile +++ b/cpu/rp2350_common/Makefile @@ -1,6 +1,3 @@ -MODULE = cpu - -DIRS += $(RIOTCPU)/cortexm_common DIRS += periph include $(RIOTBASE)/Makefile.base diff --git a/cpu/rp2350_common/Makefile.dep b/cpu/rp2350_common/Makefile.dep new file mode 100644 index 000000000000..51983f6a1cf8 --- /dev/null +++ b/cpu/rp2350_common/Makefile.dep @@ -0,0 +1,4 @@ +USEMODULE += periph +USEPKG += picosdk +# We tell the build system that common needs to be built +USEMODULE += rp2350_common diff --git a/cpu/rp2350_common/Makefile.features b/cpu/rp2350_common/Makefile.features new file mode 100644 index 000000000000..783de0af307d --- /dev/null +++ b/cpu/rp2350_common/Makefile.features @@ -0,0 +1,2 @@ +FEATURES_PROVIDED += periph_gpio +FEATURES_PROVIDED += periph_uart diff --git a/cpu/rp2350/Makefile.include b/cpu/rp2350_common/Makefile.include similarity index 53% rename from cpu/rp2350/Makefile.include rename to cpu/rp2350_common/Makefile.include index 67a10640106d..d25da2943b04 100644 --- a/cpu/rp2350/Makefile.include +++ b/cpu/rp2350_common/Makefile.include @@ -4,30 +4,14 @@ RAM_LEN := 0x82000 # 520kB = 532479 used in the RPi Pico 2350 ROM_START_ADDR := 0x10000000 # XIP Non-Secure address for rp2350 RAM_START_ADDR := 0x20000000 # Non-Secure RAM address for rp2350 -# CPU and architecture specific flags -CFLAGS += -D$(CPU_MODEL) -CFLAGS += -DROM_START_ADDR=$(ROM_START_ADDR) -CFLAGS += -DRAM_START_ADDR=$(RAM_START_ADDR) -CFLAGS += -Wno-error +CFLAGS += -DISR_STACKSIZE=8192 -# Include paths -INCLUDES += -I$(RIOTCPU)/rp2350/include +INCLUDES += -I$(RIOTCPU)/rp2350_common/include INCLUDES += -isystem$(RIOTBASE)/build/pkg/picosdk/src/rp2_common/cmsis/stub/CMSIS/Core/Include INCLUDES += -isystem$(RIOTBASE)/build/pkg/picosdk/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include - -# Linker flags -LINKFLAGS += -mcpu=$(CPU_ARCH) -mthumb -LINKFLAGS += -Wl,--gc-sections -LINKFLAGS += -Wl,--start-group -lc -lm -Wl,--end-group - -# Vector table configuration -VECTORS_O ?= $(BINDIR)/cpu/vectors.o -VECTORS_FILE := $(RIOTCPU)/rp2350/vectors.c +INCLUDES += -isystem$(RIOTBASE)/build/pkg/picosdk/src/rp2350/hardware_regs/include/hardware # Supported programmers and debuggers PROGRAMMERS_SUPPORTED := picotool openocd jlink PROGRAMMER ?= picotool OPENOCD_DEBUG_ADAPTER ?= dap - -# Include the base Cortex-M makefile -include $(RIOTMAKE)/arch/cortexm.inc.mk diff --git a/cpu/rp2350/clock.c b/cpu/rp2350_common/clock.c similarity index 100% rename from cpu/rp2350/clock.c rename to cpu/rp2350_common/clock.c diff --git a/cpu/rp2350/cpu.c b/cpu/rp2350_common/cpu.c similarity index 58% rename from cpu/rp2350/cpu.c rename to cpu/rp2350_common/cpu.c index f4ff0006d8c8..91e44a910b9e 100644 --- a/cpu/rp2350/cpu.c +++ b/cpu/rp2350_common/cpu.c @@ -5,38 +5,37 @@ */ /** - * @ingroup cpu_rp2350 + * @ingroup cpu_rp2350 * @{ * * @file - * @brief CPU initialization implementation for the RP2350 + * @brief Implementation of the CPU initialization for RP2350 * - * @author Tom Hert + * @author Tom Hert + * @} */ -#include "cpu.h" +#include -#include "RP2350.h" #include "board.h" +#include "cpu.h" +#include "clock_conf.h" #include "kernel_init.h" -#include "macros/units.h" -#include "periph/gpio.h" #include "periph/init.h" -#include "periph_cpu.h" -#include "stdio_base.h" +#include "periph/uart.h" +#include "periph_conf.h" -#define DEBUG_WITH_OSC - -void gpio_reset(void) { +void gpio_reset(void) +{ reset_component(RESET_PADS_BANK0, RESET_PADS_BANK0); reset_component(RESET_IO_BANK0, RESET_IO_BANK0); } -void cpu_init(void) { - /* initialize the Cortex-M core, once UART support is moved - * to shared driver as currently this will cause unhandled interrupts */ - /* cortexm_init(); */ - +/** + * @brief Initialize the CPU, set IRQ priorities, clocks, peripheral + */ +void rp2350_init(void) +{ /* Reset GPIO state */ gpio_reset(); @@ -55,5 +54,3 @@ void cpu_init(void) { /* initialize the board */ board_init(); } - -/** @} */ diff --git a/cpu/rp2350/doc.md b/cpu/rp2350_common/doc.md similarity index 83% rename from cpu/rp2350/doc.md rename to cpu/rp2350_common/doc.md index cc2f01362ef9..c080f9fe1b89 100644 --- a/cpu/rp2350/doc.md +++ b/cpu/rp2350_common/doc.md @@ -2,4 +2,4 @@ @ingroup cpu @brief RP2350 MCU code and definitions -This module contains the code and definitions for MCUs of the RP2350 family used by the Pi Pico 2. +This module contains the code and definitions for MCUs of the RP2350 used by the Pi Pico 2. diff --git a/cpu/rp2350/include/clock_conf.h b/cpu/rp2350_common/include/clock_conf.h similarity index 99% rename from cpu/rp2350/include/clock_conf.h rename to cpu/rp2350_common/include/clock_conf.h index f5137e4c57d0..c6451d225afc 100644 --- a/cpu/rp2350/include/clock_conf.h +++ b/cpu/rp2350_common/include/clock_conf.h @@ -89,7 +89,7 @@ * clock */ #define CLK_SYS_PERI_CTRL_ENABLE_BIT (1u << 0u) /** Selected field value for the system clock control register -* to select the peripheral clock */ + * to select the peripheral clock */ #define CLK_SYS_SELECTED_PERI_FIELD_VALUE 2u /** RIOT core clock frequency defined as the CPU frequency */ #define CLOCK_CORECLOCK MHZ(12u) diff --git a/cpu/rp2350_common/include/compat_layer.h b/cpu/rp2350_common/include/compat_layer.h new file mode 100644 index 000000000000..134c0809bdc6 --- /dev/null +++ b/cpu/rp2350_common/include/compat_layer.h @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: 2025 Tom Hert + * SPDX-FileCopyrightText: 2025 HAW Hamburg + * SPDX-License-Identifier: LGPL-2.1-only + */ + +#pragma once + +/** + * @ingroup cpu_rp2350 + * @{ + * + * @file + * @brief Compatibility layer for different CPU architectures + * + * @author Tom Hert + */ + +#include "periph_cpu.h" + +#ifdef RP2350_USE_RISCV +# include "xh3irq.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the given IRQ + * @param[in] irq_no IRQ number to enable + */ +static inline void rp_irq_enable(uint32_t irq_no) +{ +#ifdef RP2350_USE_RISCV + xh3irq_enable_irq(irq_no); +#else + NVIC_EnableIRQ(irq_no); +#endif +} + +/** + * @brief Called upon the end of an ISR + */ +static inline void rp_end_isr(void) +{ +#ifdef RP2350_USE_ARM + cortexm_isr_end(); +#endif +} + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/cpu/rp2350/include/gpio_conf.h b/cpu/rp2350_common/include/gpio_conf.h similarity index 100% rename from cpu/rp2350/include/gpio_conf.h rename to cpu/rp2350_common/include/gpio_conf.h diff --git a/cpu/rp2350/include/helpers.h b/cpu/rp2350_common/include/helpers.h similarity index 99% rename from cpu/rp2350/include/helpers.h rename to cpu/rp2350_common/include/helpers.h index 556088201772..6ab9b4dd9c03 100644 --- a/cpu/rp2350/include/helpers.h +++ b/cpu/rp2350_common/include/helpers.h @@ -6,8 +6,6 @@ #pragma once -#include "RP2350.h" - /** * @ingroup cpu_rp2350 * @{ diff --git a/cpu/rp2350/include/periph_cpu.h b/cpu/rp2350_common/include/periph_cpu.h similarity index 55% rename from cpu/rp2350/include/periph_cpu.h rename to cpu/rp2350_common/include/periph_cpu.h index 0eb149a4a009..74af385437ff 100644 --- a/cpu/rp2350/include/periph_cpu.h +++ b/cpu/rp2350_common/include/periph_cpu.h @@ -16,21 +16,45 @@ * @author Tom Hert */ -#include -#include +#include -#include "RP2350.h" -#include "clock_conf.h" +/** Overwrite the default GPIO type to use uint32_t */ +#define HAVE_GPIO_T +typedef uint32_t gpio_t; + +/** + * @brief Macro to create a GPIO pin identifier + * @param port The GPIO port (Currently only GPIO0) + * @param pin The GPIO pin number + */ +#define GPIO_PIN(port, pin) (((port) & 0) | (pin)) + +/** This is a define used throughout the pico sdk */ +#define _u(x) ((uint32_t)(x)) + +#ifdef RP2350_USE_RISCV +# include "periph_cpu_common.h" +# include "xh3irq.h" +#endif #include "cpu.h" -#include "gpio_conf.h" +#include "core_cm33.h" /* Trick RP2350 into believing the file exists on RISCV */ +#include "RP2350.h" #include "helpers.h" +#include "gpio_conf.h" +#include "clock_conf.h" #include "uart_conf.h" -/** Overwrite the default GPIO type to use uint32_t */ -#define HAVE_GPIO_T -typedef uint32_t gpio_t; +#if !(defined(RP2350_USE_ARM) || defined(RP2350_USE_RISCV)) +# error "Either RP2350_USE_ARM or RP2350_USE_RISCV must be defined" +#endif -#include "periph/gpio.h" +#if (defined(RP2350_USE_ARM) && defined(RP2350_USE_RISCV)) +# error "Only one of RP2350_USE_ARM or RP2350_USE_RISCV can be defined" +#endif + +#ifdef __cplusplus +extern "C" { +#endif /** GPIO Pin ID for oscillator debugging */ #define OSC_DEBUG_PIN_ID 15u @@ -56,20 +80,23 @@ typedef uint32_t gpio_t; /** Isolation bits for PADS_BANK0 */ #define PADS_BANK0_ISO_BITS (1u << 8u) -#ifdef __cplusplus -extern "C" { -#endif +/** + * @brief Initialize RP2350 specific CPU peripherals that are not + * architecture specific + */ +void rp2350_init(void); /** - * @brief Calculate the address of the GPIO pad register for a given pin - * @param pin The GPIO pin number - * @return The address of the GPIO pad register for the given pin + * @brief Calculate the address of the GPIO pad register for a given pin + * @param[in] pin The GPIO pin number + * @return The address of the GPIO pad register for the given pin */ -static inline uint32_t calculate_gpio_pad_register_addr(gpio_t pin) { +static inline uint32_t* calculate_gpio_pad_register_addr(gpio_t pin) +{ /* Each pin has a 4 byte register, so we can calculate the address - * by adding 4 bytes for each pin, starting at the base address of PADS_BANK0 - * and adding 4 bytes to skip VOLTAGE_SELECT */ - return PADS_BANK0_BASE + 4 * (pin + 1); + * by adding 4 bytes for each pin, starting at the base address of PADS_BANK0 + * and adding 4 bytes to skip VOLTAGE_SELECT */ + return (uint32_t*) (PADS_BANK0_BASE + (4 * (pin + 1))); } /** @@ -78,8 +105,8 @@ static inline uint32_t calculate_gpio_pad_register_addr(gpio_t pin) { * @return The address of the GPIO IO status register for the given pin */ static uint32_t calculate_gpio_io_status_register_addr(gpio_t pin) { - /* Each status register is followed by a ctrl register, */ - return IO_BANK0_BASE + 8 * pin; + /* Each status register is followed by a ctrl register */ + return IO_BANK0_BASE + (8 * pin); } /** @@ -88,11 +115,11 @@ static uint32_t calculate_gpio_io_status_register_addr(gpio_t pin) { * @param pin The GPIO pin number * @return The address of the GPIO IO control register for the given pin */ -static inline uint32_t calculate_gpio_io_ctrl_register_addr(gpio_t pin) { +static inline uint32_t* calculate_gpio_io_ctrl_register_addr(gpio_t pin) { /* Each pin has a 8 byte register (4 Bytes of Status, 4 Bytes of CTRL), * so we can calculate the address by adding 8 bytes for each pin, * starting at the base address of IO_BANK0 */ - return calculate_gpio_io_status_register_addr(pin) + 4; + return (uint32_t*) (calculate_gpio_io_status_register_addr(pin) + 4); } #ifdef __cplusplus diff --git a/cpu/rp2350/include/uart_conf.h b/cpu/rp2350_common/include/uart_conf.h similarity index 65% rename from cpu/rp2350/include/uart_conf.h rename to cpu/rp2350_common/include/uart_conf.h index ed25e9f6eae3..829da0dcf3c1 100644 --- a/cpu/rp2350/include/uart_conf.h +++ b/cpu/rp2350_common/include/uart_conf.h @@ -44,6 +44,27 @@ /** UART transmit FIFO empty flag bit in flag register */ #define UART_UARTFR_TXFE_BITS (1u << 7u) +/** UART data register break error mask */ +#define UART0_UARTDR_BE_Msk (0x400UL) + +/** UART data register parity error mask */ +#define UART0_UARTDR_PE_Msk (0x200UL) + +/** UART data register framing error mask */ +#define UART0_UARTDR_FE_Msk (0x100UL) + +/** UART raw interrupt status transmit interrupt mask */ +#define UART0_UARTRIS_TXRIS_Msk (0x20UL) + +/** UART line control register two stop bits mask */ +#define UART0_UARTLCR_H_STP2_Msk (0x8UL) + +/** UART line control register even parity select mask */ +#define UART0_UARTLCR_H_EPS_Msk (0x4UL) + +/** UART line control register parity enable mask */ +#define UART0_UARTLCR_H_PEN_Msk (0x2UL) + #ifdef __cplusplus extern "C" { #endif diff --git a/cpu/rp2350/periph/Makefile b/cpu/rp2350_common/periph/Makefile similarity index 100% rename from cpu/rp2350/periph/Makefile rename to cpu/rp2350_common/periph/Makefile diff --git a/cpu/rp2350/periph/gpio.c b/cpu/rp2350_common/periph/gpio.c similarity index 92% rename from cpu/rp2350/periph/gpio.c rename to cpu/rp2350_common/periph/gpio.c index e949b344451d..c910230d06e7 100644 --- a/cpu/rp2350/periph/gpio.c +++ b/cpu/rp2350_common/periph/gpio.c @@ -36,13 +36,13 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) { switch (mode) { case GPIO_OUT: - *(uint32_t*)calculate_gpio_io_ctrl_register_addr(pin) = + *calculate_gpio_io_ctrl_register_addr(pin) = FUNCTION_SELECT_SIO; volatile uint32_t* pad_reg = - (uint32_t*)calculate_gpio_pad_register_addr(pin); + calculate_gpio_pad_register_addr(pin); - /* We clear all bits except the drive strength bit + /* We clear all bits except the drive strength bit. * We set that to the highest one possible (12mA) * to mimic the behavior of the pico1 GPIO driver * (Not too sure why we do this, but it seems to be the standard) */ diff --git a/cpu/rp2350_common/periph/uart.c b/cpu/rp2350_common/periph/uart.c new file mode 100644 index 000000000000..2b057d1bc394 --- /dev/null +++ b/cpu/rp2350_common/periph/uart.c @@ -0,0 +1,270 @@ +/* + * SPDX-FileCopyrightText: 2025 Tom Hert + * SPDX-FileCopyrightText: 2025 HAW Hamburg + * SPDX-License-Identifier: LGPL-2.1-only + */ + +/** + * @ingroup cpu_rp2350 + * @{ + * + * @file + * @brief UART implementation for the RP2350 + * + * @author Tom Hert + */ + +#include "board.h" +#include "compat_layer.h" +#include "periph_cpu.h" + +#include "regs/uart.h" +#include "periph/uart.h" + +#define ENABLE_DEBUG 0 +#include "debug.h" + +static uart_isr_ctx_t ctx[UART_NUMOF]; + +/* back up values of registers used during uart_poweroff() / uart_poweron() */ +static uint32_t uartibrd; +static uint32_t uartfbrd; +static uint32_t uartlcr_h; +static uint32_t uartcr; + +void _irq_enable(uart_t uart) +{ + UART0_Type *dev = uart_config[uart].dev; + /* We set the UART Receive Interrupt Mask (Bit 4) [See p979 UART 12.1]*/ + dev->UARTIMSC = UART_UARTIMSC_RXIM_BITS; + /* Enable the IRQ */ + rp_irq_enable(uart_config[uart].irqn); +} + +void _set_symbolrate(uart_t uart, uint32_t baud) +{ + assert(baud != 0); + UART0_Type *dev = uart_config[uart].dev; + uint32_t baud_rate_div = (8 * CPUFREQ / baud); + uint32_t baud_ibrd = baud_rate_div >> 7; + uint32_t baud_fbrd; + + if (baud_ibrd == 0) { + baud_ibrd = 1; + baud_fbrd = 0; + } + else if (baud_ibrd >= 65535) { + baud_ibrd = 65535; + baud_fbrd = 0; + } + else { + baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2; + } + + dev->UARTIBRD = baud_ibrd; + dev->UARTFBRD = baud_fbrd; +} + +int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t parity, + uart_stop_bits_t stop_bits) +{ + assert((unsigned)uart < UART_NUMOF); + UART0_Type *dev = uart_config[uart].dev; + + /* Disable the UART before changing the mode */ + atomic_clear(&dev->UARTCR, UART_UARTCR_UARTEN_BITS | UART_UARTCR_RXE_BITS | + UART_UARTCR_TXE_BITS | 1 << 7); + + /* Beware of strange hardware bug: If the configuration bitmask is prepared in register and + * transferred with a single 32 bit write (updating both parity and number of data bits at the + * same time), the configuration change of the parity bits will not take place until after the + * next char send out. If the configuration is updated in multiple bus accesses, it will apply + * directly to the next char. So: Double check e.g. with tests/periph/uart_mode after touching + * the initialization code here + * based on Table 1035 page 976 */ + dev->UARTLCR_H = (uint32_t)data_bits << 5; + + if (stop_bits == UART_STOP_BITS_2) { + atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_STP2_Msk); + } + + switch (parity) { + case UART_PARITY_NONE: + break; + case UART_PARITY_EVEN: + atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk); + break; + case UART_PARITY_ODD: + atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_PEN_Msk); + break; + default: + return UART_NOMODE; + } + + atomic_set(&dev->UARTCR, UART_UARTCR_TXE_BITS | UART_UARTCR_UARTEN_BITS | UART_UARTCR_RXE_BITS); + + return UART_OK; +} + +static void _reset_uart(uart_t uart) +{ + switch (uart) { + case 0: + /* We reset UART0 here, so we can be sure it is in a known state */ + reset_component(RESET_UART0, RESET_UART0); + break; + case 1: + /* We reset UART1 here, so we can be sure it is in a known state */ + reset_component(RESET_UART1, RESET_UART1); + break; + default: + break; + } +} + +void uart_init_pins(uart_t uart) +{ + assert((unsigned)uart < UART_NUMOF); + + /* We reset UART0 here, so we can be sure it is in a known state */ + _reset_uart(uart); + + /* Set the UART pins to the correct function */ + *calculate_gpio_io_ctrl_register_addr(uart_config[uart].tx_pin) = FUNCTION_SELECT_UART; + *calculate_gpio_io_ctrl_register_addr(uart_config[uart].rx_pin) = FUNCTION_SELECT_UART; + /* Clear the ISO bits */ + atomic_clear( + calculate_gpio_pad_register_addr(uart_config[uart].tx_pin), + PADS_BANK0_ISO_BITS); + atomic_clear( + calculate_gpio_pad_register_addr(uart_config[uart].rx_pin), + PADS_BANK0_ISO_BITS); + + /* Set Input Enable Flag */ + atomic_set( + calculate_gpio_pad_register_addr(uart_config[uart].rx_pin), + PADS_BANK0_GPIO0_IE_BITS); +} + +int uart_init(uart_t uart, uint32_t baud, uart_rx_cb_t rx_cb, void *arg) +{ + if (uart >= UART_NUMOF) { + return UART_NODEV; + } + + UART0_Type *dev = uart_config[uart].dev; + ctx[uart].rx_cb = rx_cb; + ctx[uart].arg = arg; + + uart_init_pins(uart); + + _set_symbolrate(uart, baud); + + if (uart_mode( + uart, + UART_DATA_BITS_8, + UART_PARITY_NONE, + UART_STOP_BITS_1) != UART_OK) { + return UART_NOMODE; + } + + /* enable RX and IRQs, if needed */ + if (rx_cb != NULL) { + _irq_enable(uart); + /* clear any pending data and IRQ to avoid receiving a garbage char */ + uint32_t status = dev->UARTRIS; + dev->UARTICR = status; + (void)dev->UARTDR; + atomic_set(&dev->UARTCR, UART_UARTCR_RXE_BITS); + } + + return UART_OK; +} + +void uart_write(uart_t uart, const uint8_t *data, size_t len) +{ + assert((unsigned)uart < UART_NUMOF); + UART0_Type *dev = uart_config[uart].dev; + + for (size_t i = 0; i < len; i++) { + dev->UARTDR = data[i]; + /* Wait until the TX FIFO is empty before sending the next byte */ + while (!(dev->UARTRIS & UART0_UARTRIS_TXRIS_Msk)) { } + } +} + +void uart_poweron(uart_t uart) +{ + assert((unsigned)uart < UART_NUMOF); + /* Get into a safe state where we know what's up */ + _reset_uart(uart); + UART0_Type *dev = uart_config[uart].dev; + /* Restore config from registers */ + dev->UARTIBRD = uartibrd; + dev->UARTFBRD = uartfbrd; + dev->UARTLCR_H = uartlcr_h; + dev->UARTCR = uartcr; + /* restore IRQs, if needed */ + if (ctx[uart].rx_cb != NULL) { + _irq_enable(uart); + } + uart_init_pins(uart); +} + +void uart_deinit_pins(uart_t uart) +{ + assert((unsigned)uart < UART_NUMOF); + /* @TODO */ + /* gpio_reset_all_config(uart_config[uart].tx_pin); */ + SIO->GPIO_OE_CLR = 1LU << uart_config[uart].tx_pin; + if (ctx[uart].rx_cb) { + /* gpio_reset_all_config(uart_config[uart].rx_pin); */ + } +} + +void uart_poweroff(uart_t uart) +{ + assert((unsigned)uart < UART_NUMOF); + UART0_Type *dev = uart_config[uart].dev; + /* backup configuration registers */ + uartibrd = dev->UARTIBRD; + uartfbrd = dev->UARTFBRD; + uartlcr_h = dev->UARTLCR_H; + uartcr = dev->UARTCR; + /* disconnect GPIOs and power off peripheral */ + uart_deinit_pins(uart); + _reset_uart(uart); +} + +void isr_handler(uint8_t num) +{ + UART0_Type *dev = uart_config[num].dev; + + uint32_t status = dev->UARTMIS; + atomic_set(&dev->UARTICR, status); + + if (status & UART_UARTMIS_RXMIS_BITS) { + uint32_t data = dev->UARTDR; + if (data & (UART0_UARTDR_BE_Msk | UART0_UARTDR_PE_Msk | UART0_UARTDR_FE_Msk)) { + puts("[rpx0xx] uart RX error (parity, break, or framing error"); + } + else { + ctx[num].rx_cb(ctx[num].arg, (uint8_t)data); + } + } +} + +/** Overwrites the WEAK_DEFAULT isr_uart0 */ +void isr_uart0(void) +{ + isr_handler(0); + rp_end_isr(); +} + +void isr_uart1(void) +{ + isr_handler(1); + rp_end_isr(); +} + +/** @} */ diff --git a/cpu/rp2350/vectors.c b/cpu/rp2350_common/vectors.c similarity index 90% rename from cpu/rp2350/vectors.c rename to cpu/rp2350_common/vectors.c index 36d0079f4c59..4a4cf43d1c7d 100644 --- a/cpu/rp2350/vectors.c +++ b/cpu/rp2350_common/vectors.c @@ -14,13 +14,27 @@ * @author Tom Hert */ -#include "RP2350.h" +#include + #include "cpu_conf.h" -#include "vectors_cortexm.h" +#include "panic.h" + +#ifdef RP2350_USE_RISCV +# include "xh3irq.h" +#else +# include "vectors_cortexm.h" +#endif + +#ifndef WEAK_DEFAULT +# define WEAK_DEFAULT __attribute__((weak, alias("dummy_handler"))) +#endif /* define a local dummy handler as it needs to be in the same compilation unit * as the alias definition */ -void dummy_handler(void) { dummy_handler_default(); } +void dummy_handler(void) +{ + core_panic(PANIC_GENERAL_ERROR, "DUMMY HANDLER"); +} /* rp2350 specific interrupt vector */ WEAK_DEFAULT void isr_timer0_0(void); @@ -76,9 +90,14 @@ WEAK_DEFAULT void isr_spareirq_3(void); WEAK_DEFAULT void isr_spareirq_4(void); WEAK_DEFAULT void isr_spareirq_5(void); -/* CPU specific interrupt vector table */ +/** CPU specific interrupt vector table + * @see 3.2 Interrupts and IRQn_Type in RP2350.h + */ +#ifdef RP2350_USE_ARM +/* Cortex-M does some macro magic, RISC-V does not */ ISR_VECTOR(1) -const isr_t vector_cpu[CPU_IRQ_NUMOF] = { +#endif +const void* vector_cpu[CPU_IRQ_NUMOF] = { (void*)isr_timer0_0, /* 0 TIMER0_IRQ_0 */ (void*)isr_timer0_1, /* 1 TIMER0_IRQ_1 */ (void*)isr_timer0_2, /* 2 TIMER0_IRQ_2 */ diff --git a/cpu/rp2350/xosc.c b/cpu/rp2350_common/xosc.c similarity index 100% rename from cpu/rp2350/xosc.c rename to cpu/rp2350_common/xosc.c diff --git a/cpu/rp2350_riscv/Makefile b/cpu/rp2350_riscv/Makefile new file mode 100644 index 000000000000..ee03da8b7063 --- /dev/null +++ b/cpu/rp2350_riscv/Makefile @@ -0,0 +1,8 @@ +# define the module that is built +MODULE = cpu + +# add a list of subdirectories, that should also be built +DIRS += $(RIOTCPU)/rp2350_common +DIRS += $(RIOTCPU)/riscv_common + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/rp2350_riscv/Makefile.dep b/cpu/rp2350_riscv/Makefile.dep new file mode 100644 index 000000000000..d648a1452e80 --- /dev/null +++ b/cpu/rp2350_riscv/Makefile.dep @@ -0,0 +1,3 @@ +FEATURES_REQUIRED += periph_xh3irq +include $(RIOTCPU)/rp2350_common/Makefile.dep +include $(RIOTCPU)/riscv_common/Makefile.dep diff --git a/cpu/rp2350_riscv/Makefile.features b/cpu/rp2350_riscv/Makefile.features new file mode 100644 index 000000000000..587c6d29fcab --- /dev/null +++ b/cpu/rp2350_riscv/Makefile.features @@ -0,0 +1,10 @@ +CPU_CORE := rv32imac +CPU_FAM := RP2350 +CPU_MODEL = rp2350_hazard3 + +FEATURES_PROVIDED += periph_pmp +FEATURES_PROVIDED += periph_xh3irq + +include $(RIOTCPU)/rp2350_common/Makefile.features + +include $(RIOTCPU)/riscv_common/Makefile.features diff --git a/cpu/rp2350_riscv/Makefile.include b/cpu/rp2350_riscv/Makefile.include new file mode 100644 index 000000000000..f579f2204560 --- /dev/null +++ b/cpu/rp2350_riscv/Makefile.include @@ -0,0 +1,17 @@ +# CPU and architecture specific flags +CFLAGS += -D$(CPU_MODEL) +CFLAGS += -DROM_START_ADDR=$(ROM_START_ADDR) +CFLAGS += -DRAM_START_ADDR=$(RAM_START_ADDR) +CFLAGS += -march=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs +CFLAGS += -mabi=lp64 + +# Linker flags +LINKFLAGS += -mcpu=$(CPU_ARCH) +LINKFLAGS += -Wl,--gc-sections +LINKFLAGS += -Wl,--start-group -lc -lm -Wl,--end-group +LINKFLAGS += -march=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs + +include $(RIOTCPU)/rp2350_common/Makefile.include +include $(RIOTCPU)/riscv_common/Makefile.include + +INCLUDES += -I$(RIOTCPU)/rp2350_riscv/include diff --git a/cpu/rp2350_riscv/cpu.c b/cpu/rp2350_riscv/cpu.c new file mode 100644 index 000000000000..a46e2b3548ce --- /dev/null +++ b/cpu/rp2350_riscv/cpu.c @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2025 Tom Hert + * SPDX-FileCopyrightText: 2025 HAW Hamburg + * SPDX-License-Identifier: LGPL-2.1-only + */ + +/** + * @ingroup cpu_rp2350_riscv + * @{ + * + * @file cpu.c + * @brief Implementation of the CPU initialization for RP2350 + * + * @author Tom Hert + * @} + */ + + #include + + #include "board.h" + #include "cpu.h" + #include "clock_conf.h" + #include "kernel_init.h" + #include "periph/init.h" + #include "periph/uart.h" + #include "periph_conf.h" + +/** + * @brief Initialize the CPU, set IRQ priorities, clocks, peripheral + */ +void cpu_init(void) +{ + /* rp2350 common startup routine */ + rp2350_init(); + /* initialize the RISC-V core (Interrupts, FPU, etc) */ + riscv_init(); +} diff --git a/cpu/rp2350_riscv/doc.md b/cpu/rp2350_riscv/doc.md new file mode 100644 index 000000000000..f9d0b1664f2d --- /dev/null +++ b/cpu/rp2350_riscv/doc.md @@ -0,0 +1,5 @@ +@defgroup cpu_rp2350_riscv RP2350 RISCV MCUs +@ingroup cpu +@brief RP2350 RISCV MCU code and definitions + +This module contains the code and definitions for MCUs of the RP2350 RISCV family used by the Pi Pico 2. diff --git a/cpu/rp2350_riscv/include/core_cm33.h b/cpu/rp2350_riscv/include/core_cm33.h new file mode 100644 index 000000000000..f5e13719a4d3 --- /dev/null +++ b/cpu/rp2350_riscv/include/core_cm33.h @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2025 Tom Hert + * SPDX-FileCopyrightText: 2025 HAW Hamburg + * SPDX-License-Identifier: LGPL-2.1-only + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define __IM volatile const /**< Defines 'read only' structure member permissions */ +#define __OM volatile /**< Defines 'write only' structure member permissions */ +#define __IOM volatile /**< Defines 'read / write' structure member permissions */ + +#ifdef __cplusplus +} +#endif diff --git a/cpu/rp2350_riscv/include/cpu.h b/cpu/rp2350_riscv/include/cpu.h new file mode 100644 index 000000000000..d995f19efcc7 --- /dev/null +++ b/cpu/rp2350_riscv/include/cpu.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2025 Tom Hert git@annsann.eu> + * SPDX-FileCopyrightText: 2025 HAW Hamburg + * SPDX-License-Identifier: LGPL-2.1-only + */ + +#pragma once + +/** + * @ingroup cpu_rp2350_riscv + * @{ + * + * @file + * @brief CPU specific definitions + */ + +#include "cpu_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/cpu/rp2350_riscv/include/cpu_conf.h b/cpu/rp2350_riscv/include/cpu_conf.h new file mode 100644 index 000000000000..17780774e319 --- /dev/null +++ b/cpu/rp2350_riscv/include/cpu_conf.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: 2025 Tom Hert git@annsann.eu> + * SPDX-FileCopyrightText: 2025 HAW Hamburg + * SPDX-License-Identifier: LGPL-2.1-only + */ + +#pragma once + +/** + * @ingroup cpu_rp2350_riscv + * @{ + * @file + * @brief CPU configuration for the RP2350 + * + * @author Tom Hert + */ + +#include "cpu_conf_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Default IRQ priority for the CPU, + * we don't have different levels at the moment */ +#define CPU_DEFAULT_IRQ_PRIO 1u +/** The RP2350 has 52 IRQs, see vectors.c for more details */ +#define CPU_IRQ_NUMOF 52u +/** + * The Hazard3 core supports 16 PMP entries + * Only the first 8 are dynamic + * the next 3 hard-wired + * the remaining ones OFF + */ +#define NUM_PMP_ENTRIES 8u +/** This tells rp2350_common that we are using the RISC-V core */ +#define RP2350_USE_RISCV 1 + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/cpu/rp2350_riscv/picobin_block.s b/cpu/rp2350_riscv/picobin_block.s new file mode 100644 index 000000000000..1f1747347bf5 --- /dev/null +++ b/cpu/rp2350_riscv/picobin_block.s @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2025 Tom Hert + * SPDX-FileCopyrightText: 2025 HAW Hamburg + * SPDX-License-Identifier: LGPL-2.1-only + */ + +/* Picobin block required for the binary. + * This defines the minimum viable image metadata to be recognized by the RP2350 bootloader + * based on RP2350 Chapter 5.9.1 */ + +.section .picobin_block, "a" /* "a" means "allocatable" (can be moved by the linker) */ + +/* PICOBIN_BLOCK_MARKER_START */ +.word 0xffffded3 + /* ITEM 0 START based on 5.9.3.1 */ + .byte 0x42 /* (size_flag == 0, item_type == PICOBIN_BLOCK_ITEM_1BS_IMAGE_TYPE) */ + .byte 0x1 /* Block Size in words */ + /* image_type_flags (2 bytes) [See 5.9.3.1 / p419] */ + /* 15 -> 0 (1 for "Try before you buy" image [Wacky] */ + /* 12-14 -> 001 (RP2350 = 1) */ + /* 11 -> 0 (Reserved) */ + /* 8-10 -> 001 (EXE_CPU_ARM == 000) || (EXE_CPU_RISCV == 001^) */ + /* 6-7 -> 00 (Reserved) */ + /* 4-5 -> 10 (2) EXE Security + * (As far as I understand we cant run in EXE_SECURITY_NS on the RP2350) + * thus EXE_SECURITY_S = 2 + */ + /* 0-3 // 0001 IMAGE_TYPE_EXE */ + .hword 0b0001000100100001 + /* ITEM 0 END see 5.1.5.1 for explanation and 5.9.5.1 for the value / structure */ + .byte 0xff /* PICOBIN_BLOCK_ITEM_2BS_LAST */ + .hword 0x0001 /* Size of the item in words (predefined value) */ + .byte 0x00 /* Padding */ + /* Next Block Pointer */ + .word 0x00000000 /* Next block pointer (0 means no more blocks) */ +/* PICOBIN_BLOCK_MARKER_END */ +.word 0xab123579 /* Marker for the end of the picobin block */ diff --git a/features.yaml b/features.yaml index 7113af63e6c5..3f1ea71e2021 100644 --- a/features.yaml +++ b/features.yaml @@ -283,8 +283,10 @@ groups: features: - name: cpu_rpx0xx help: The MCU is part of the Raspberry PI RPx0xx family. - - name: cpu_rp2350 - help: The MCU is a Raspberry Pi RP2350 + - name: cpu_rp2350_arm + help: The MCU is a Raspberry Pi RP2350 Cortex-M33 ARM, + - name: cpu_rp2350_riscv + help: The MCU is a Raspberry Pi RP2350 Hazard3 RISC-V. - title: Silicon Laboratories EFM32 Grouping features: @@ -827,6 +829,9 @@ groups: help: A RISC-V Core-local Interrupt Controller (CLIC) peripheral is present. - name: periph_plic help: A RISC-V Platform-local Interrupt Controller (PLIC) peripheral is present. + - name: periph_xh3irq + help: An XH3IRQ peripheral is present. This is a special interrupt controller + for the Hazard3 used by the RP2350. - title: Cryptographic Features help: Hardware acceleration for cryptographic primitives, hardware random diff --git a/makefiles/arch/riscv.inc.mk b/makefiles/arch/riscv.inc.mk index 55ae154c581e..4d2736aa8743 100644 --- a/makefiles/arch/riscv.inc.mk +++ b/makefiles/arch/riscv.inc.mk @@ -52,6 +52,7 @@ endif GCC_DEFAULTS_TO_NEW_RISCV_ISA ?= 0 CFLAGS_CPU := -march=rv32imac -mabi=ilp32 +ASFLAGS := $(CFLAGS_CPU) # Since RISC-V ISA specifications 20191213 instructions previously included in # rv32imac have been moved to the ZICSR extension. See diff --git a/makefiles/features_existing.inc.mk b/makefiles/features_existing.inc.mk index 6420ccd089cd..8889dc5f5b1e 100644 --- a/makefiles/features_existing.inc.mk +++ b/makefiles/features_existing.inc.mk @@ -86,7 +86,8 @@ FEATURES_EXISTING := \ cpu_nrf53 \ cpu_nrf9160 \ cpu_qn908x \ - cpu_rp2350 \ + cpu_rp2350_arm \ + cpu_rp2350_riscv \ cpu_rpx0xx \ cpu_sam3 \ cpu_sam4s \ @@ -257,6 +258,7 @@ FEATURES_EXISTING := \ periph_wdt \ periph_wdt_cb \ periph_wdt_warning_period \ + periph_xh3irq \ picolibc \ pio_i2c \ puf_sram \ diff --git a/makefiles/features_modules.inc.mk b/makefiles/features_modules.inc.mk index 975cf003c0c2..38dc3faff6f8 100644 --- a/makefiles/features_modules.inc.mk +++ b/makefiles/features_modules.inc.mk @@ -57,6 +57,7 @@ PERIPH_IGNORE_MODULES := \ periph_uart_rxstart_irq \ periph_wdog \ periph_wdt_auto_start \ + periph_xh3irq \ # PERIPH_MODULES := $(filter-out $(PERIPH_IGNORE_MODULES),\ $(filter periph_%,$(USEMODULE))) diff --git a/pkg/picosdk/patches/bit.patch b/pkg/picosdk/patches/bit.patch new file mode 100644 index 000000000000..dd5ee4742f83 --- /dev/null +++ b/pkg/picosdk/patches/bit.patch @@ -0,0 +1,48 @@ +From ac99966860b9101739361412e1374cdd3e4fadf0 Mon Sep 17 00:00:00 2001 +From: AnnsAnn +Date: Thu, 2 Oct 2025 15:31:10 +0200 +Subject: [PATCH] Remove the evil lines + +--- + .../stub/CMSIS/Device/RP2350/Include/RP2350.h | 25 ------------------- + 1 file changed, 25 deletions(-) + +diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h b/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h +index ba5d206..154e7c4 100644 +--- a/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h ++++ b/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h +@@ -671,31 +671,6 @@ typedef struct { /*!< HSTX_FIFO Structure + + + +-/* =========================================================================================================================== */ +-/* ================ HSTX_CTRL ================ */ +-/* =========================================================================================================================== */ +- +- +-/** +- * @brief Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. (HSTX_CTRL) +- */ +- +-typedef struct { /*!< HSTX_CTRL Structure */ +- __IOM uint32_t CSR; /*!< CSR */ +- __IOM uint32_t BIT0; /*!< Data control register for output bit 0 */ +- __IOM uint32_t BIT1; /*!< Data control register for output bit 1 */ +- __IOM uint32_t BIT2; /*!< Data control register for output bit 2 */ +- __IOM uint32_t BIT3; /*!< Data control register for output bit 3 */ +- __IOM uint32_t BIT4; /*!< Data control register for output bit 4 */ +- __IOM uint32_t BIT5; /*!< Data control register for output bit 5 */ +- __IOM uint32_t BIT6; /*!< Data control register for output bit 6 */ +- __IOM uint32_t BIT7; /*!< Data control register for output bit 7 */ +- __IOM uint32_t EXPAND_SHIFT; /*!< Configure the optional shifter inside the command expander */ +- __IOM uint32_t EXPAND_TMDS; /*!< Configure the optional TMDS encoder inside the command expander */ +-} HSTX_CTRL_Type; /*!< Size = 44 (0x2c) */ +- +- +- + /* =========================================================================================================================== */ + /* ================ EPPB ================ */ + /* =========================================================================================================================== */ +-- +2.51.0 +