diff --git a/edalize/yosys.py b/edalize/yosys.py
index f162affee..dd0f22453 100644
--- a/edalize/yosys.py
+++ b/edalize/yosys.py
@@ -110,6 +110,8 @@ def configure_main(self):
                     cmd = 'read_verilog'
                 elif f.file_type.startswith('systemVerilogSource'):
                     cmd = 'read_verilog -sv'
+                elif f.file_type.startswith('yosys_lib'):
+                    cmd = 'read_verilog -lib'
                 elif f.file_type == 'tclSource':
                     cmd = 'source'
                 else: