suggested work-around

Signed-off-by: joydeep049 <[email protected]>

Author: joydeep049

model/riscv_insts_base.sail

@@ -788,7 +788,7 @@ union clause ast = FENCEI : unit
 // The rs1, rd and imm fields are marked as reserved to indicate
 // that they are not currently used but may be reserved for future extensions.
 mapping clause encdec = FENCEI()
-  <-> map_twelve(TWELVE) @ map_five(FIVE) @ 0b001 @ map_five(FIVE) @ 0b0001111
+  <-> reserved_bits_12(ZERO) @ reserved_bits_5(ZERO) @ 0b001 @ reserved_bits_5(ZERO) @ 0b0001111
 
 /* fence.i is a nop for the memory model */
 function clause execute FENCEI() = { /* __barrier(Barrier_RISCV_i); */ RETIRE_SUCCESS }

model/riscv_types.sail

@@ -134,21 +134,9 @@ union AccessType ('a : Type) = {
   Execute   : unit
 }
 
-enum reserve = {
-  TWELVE,
-  FIVE
-}
-
-val map_twelve : reserve <-> bits(12)
-val map_five : reserve <-> bits(5)
-
-mapping map_twelve = {
-  TWELVE <-> 0b000000000000
-}
-
-mapping map_five = {
-  FIVE <-> 0b00000
-}
+enum reserved_bits_enum = { ZERO }
+mapping reserved_bits_5 : reserved_bits_enum <-> bits(5) = { ZERO <-> 0b00000 }
+mapping reserved_bits_12 : reserved_bits_enum <-> bits(12) = { ZERO <-> 0b000000000000 }
 
 enum word_width = {BYTE, HALF, WORD, DOUBLE}