Possible incorrect register used for waitForLock() in ClkWiz

[qxzg]

Description

In vrt/src/driver/clk_wiz.cpp, the function waitForLock() waits for clock lock using this loop:

while (!read(XCLK_WIZ_REG4_OFFSET) & 1) {
    // ...
}

According to the PG321 documentation, the register at C_BASEADDR + 0x04 (Status Register, SR) has bit[0] = Locked. The register at C_BASEADDR + 0x33C (CLKOUT0_2) is a configuration register for output0, not a status/locked register.

So reading XCLK_WIZ_REG4_OFFSET (which appears to map to +0x33C) and checking its lowest bit doesn’t correspond to the documented “locked” indicator. That means waitForLock() may never observe the lock bit correctly, causing unintended timeouts.

Questions

• Is there any special reason XCLK_WIZ_REG4_OFFSET (CLKOUT0_2) was used instead of the SR (+0x04) register?
• Could there be variant/older/newer versions of the Clocking Wizard IP on Versal V80 HBM where +0x33C is repurposed or aliased to provide a “locked” status bit?
• Should the code be changed to read XCLK_WIZ_STATUS_OFFSET (i.e. base + 0x04) bit0 for locking?