06_dcmac receive code

[vysh55]

I am currently working with the 06_dcmac example and have successfully generated traffic on the transmit side. However, I have not been able to observe any data reception.

Before proceeding with the development of custom receiver logic, I would like to inquire whether pre-existing receive code for this specific example, or a related demonstration, is available.

Could you please direct me to the location of the reference receiver implementation, if one exists?

[mariodruiz]

Hi @vysh55,

Can you please comment on your configuration? Which ports are connected? What cable are you using?

I provided steps to verify the design here: #35 (comment)

[vysh55]

Ah! I was not using Python but ran the 06_dcmac.cpp executable directly and assumed the GTM was configured in loopback mode. We have two 200 Gbps cable on order and should be here this week. Once the cable arrives, should I be running compiled C++ code or running a Python script to test?

[mariodruiz]

The python script is more complete. If you look at the code in detail, you can even put the design in internal loopback if you'd like to try something before the cables arrive.

[vysh55]

Sorry for a long and possibly very naive question!

Two 200G cables arrived today! But before I even plug one in, I wanted to
understand the code. I scanned the utils.py and trafficgen.py down to
generic_mmio.py. I think I understand but I'm not sure how AXI bus addresses
and PCIe addresses line up. This is how I think the Python is supposed
to map addresses on the Versal design ...

Python Var Vivado Address Editor IP Master Base Address
DCMAC_BASEADDR /qsfp_0_n_1/DCMAC_subsys/dcmac_0_core/s_axi 0x201_0200_0000
DCMAC_BASEADDR /qsfp_2_n_3/DCMAC_subsys/dcmac_1_core/s_axi 0x201_0300_0000

TRAFFICGEN_BASEADDR /base_logic/traffic_producer_0/s_axi_control 0x201_0000_0000
TRAFFICGEN_BASEADDR /base_logic/traffic_producer_1/s_axi_control 0x201_0000_0080

NL_BASEADDR ? ?
NL_BASEADDR ? ?

But (1) What IP core is NetworkLayer in Address Editor? Do I have the
right numbers for the DCMAC_BASEADDR and TRAFFICGEN_BASEADDR?

And (2) Since we only have two trafficgen cores in our system, we think
parameter 2 (2) in get_ip_offset() in
tget1 = TrafficGenerator(... get_ip_offset(TRAFFICGEN_BASEADDR, 2) ...)
is a mistake because the second IP is 0x100_0000 * 1 away from the first;
not 0x100_0000 * 2

Can I just hard-code:

DCMAC_BASEADDR0 = 0x201_0200_0000
DCMAC_BASEADDR1 = 0x201_0300_0000

TRAFFICGEN_BASEADDR0 = 0x201_0000_0000
TRAFFICGEN_BASEADDR1 = 0x201_0000_0080

then write

tgen0 = TrafficGenerator(args.dev, TRAFFICGEN_BASEADDR0)
tgen1 = TrafficGenerator(args.dev, TRAFFICGEN_BASEADDR1)

but I still don't know what NL is supposed to be.

[mariodruiz]

Hi @vysh55,

The parts of the code you mention are targeting IP that have not been merged yet. The --udp flag should be ignored for this example.

[mariodruiz]

Your questions about the addressing are not specific to this design. The BAR addresses starting with 0x201_0000_0000 (256MB aperture) are remapped for AXI4-Lite transactions in the design.

1. This IP does not exists in the current design
2. Interface 0 and 2 are used so the multiply by 2 is correct.

Why would you hardcode? The driver is automatically computing the addressees.

[mariodruiz]

See the interface index here

SLASH/submodules/v80-vitis-flow/resources/dcmac/tcl/dcmac_config.tcl

Lines 4 to 13 in 16a1cbd

	# A front view of the V80 and QSFP56 index and associated DCMAC
	# Use this diagram to guide the configuration
	#
	# _________________________
	# | 0 | 1 | 2 | 3 |
	# ----------------------------> PCIe
	#
	# \___________/\__________/
	# | |
	# DCMAC0 DCMAC1

[vysh55]

Hi Mario,

Sorry, for the delayed response. After a little research I figured that we are talking about two different designs. (Yes, you are right I was looked at an incorrect design when I was talking about the NetworkLayer IP. Now I've switched to the 1-dcmac-integration branch.)

Currently, I'm building a vivado (2024.2) project using the tcl script given at submodules/v80-vitis-flow/resources. It is failing while running the implementation because this line in the XDC is failing

# BASE NSUs/NMUs
set_property LOC NOC_NSU512_X0Y0  [get_cells -filter {REF_NAME == NOC_NSU512} -of [get_pins -leaf -filter {DIRECTION == OUT} -of [get_nets -of [get_pins top_i/base_logic/pcie_slr0_mgmt_sc/S00_AXI_wvalid]]]]

It says "[Common 17-55] 'set_property' expects at least one object. ["/home/rsass/Documents/SLASH/submodules/v80-vitis-flow/resources/build/prj.srcs/constrs_1/imports/constraints/impl.xdc":47]" but when I go down the hierarchy on Netlist, I can find the signal name.

Any suggestions when implementing?

[mariodruiz]

Hi @vysh55, this should only be a warning.

@hpc-aulmamei any idea about this issue?

[vysh55]

In case this helps, here is the filtered Messages with the error.

[quetric]

Hi @vysh55 @mariodruiz could you please merge the changes from main and try this build again? Or let me know if you have already done so.

[mariodruiz]

Merged in this branch where I will add the UDP logic. https://github.com/mariodruiz/SLASH/tree/dcmac-udp

I haven't build yet

[mariodruiz]

For tracking purposes, I do see the same error as reported above

ERROR: [Common 17-69] Command failed: Placer could not place all instances

[vysh55]

Hello Mario,

I was able to get past this error by uncommenting the QSFP pins from impl.pins.xdc file but it was failing while trying to generate the image.