diff --git a/.gitignore b/.gitignore index c3fc2a99..5685a598 100644 --- a/.gitignore +++ b/.gitignore @@ -55,3 +55,4 @@ Thumbs.db !build_all.sh .clang-format +.cache diff --git a/deploy/base_pdi/tcl/export_noc.tcl b/deploy/base_pdi/tcl/export_noc.tcl index 76e5feb3..5cb07119 100644 --- a/deploy/base_pdi/tcl/export_noc.tcl +++ b/deploy/base_pdi/tcl/export_noc.tcl @@ -1,4 +1,4 @@ -deploy/base_pdi/build.py# ################################################################################################## +# ################################################################################################## # The MIT License (MIT) # Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. # @@ -22,6 +22,5 @@ set build_dir "build" open_project $build_dir/prj.xpr open_run synth_1 set_property lock true [get_noc_net_routes -of [get_noc_logical_paths -filter {initial_boot == 1}]] -set_property lock true [get_noc_net_routes -of [get_noc_logical_paths -of [get_noc_logical_instances *n?u128*]]] write_noc_solution -file noc_sol.ncr exit diff --git a/deploy/package/package.py b/deploy/package/package.py index abe2469d..414215a4 100755 --- a/deploy/package/package.py +++ b/deploy/package/package.py @@ -244,8 +244,9 @@ def write_debian_scripts(debian_dir): fi for dev in /dev/pcie_hotplug*; do if [ -e "$dev" ]; then - chmod 666 "$dev" || true - chown root:users "$dev" || true + chmod 666 "$dev" || echo "Warning: Failed to set permissions for $dev" + chown root:users "$dev" || echo "Warning: Failed to change owner for $dev" + echo "Set permissions for $dev" fi done EOF diff --git a/driver/.gitignore b/driver/.gitignore new file mode 100644 index 00000000..d3ae4f14 --- /dev/null +++ b/driver/.gitignore @@ -0,0 +1,10 @@ +# Kernel module build artifacts +*.o +*.ko +*.mod +*.mod.c +*.mod.o +*.cmd +Module.symvers +modules.order +compile_commands_driver.json diff --git a/driver/Makefile b/driver/Makefile new file mode 100644 index 00000000..ffa5886b --- /dev/null +++ b/driver/Makefile @@ -0,0 +1,82 @@ +#/** +# * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# * This program is free software; you can redistribute it and/or modify it under the terms of the +# * GNU General Public License as published by the Free Software Foundation; version 2. +# * +# * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without +# * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# * General Public License for more details. +# * +# * You should have received a copy of the GNU General Public License along with this program; if +# * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA +# * 02110-1301, USA. +# */ + + +MODULE := slash + +KDIR ?= /lib/modules/$(shell uname -r)/build +PWD := $(shell pwd) + +QDMA_DRV_ROOT := ../submodules/qdma_drv/QDMA/linux-kernel/driver + +obj-m := $(MODULE).o +$(MODULE)-objs := $(MODULE)_main.o $(MODULE)_ctldev.o $(MODULE)_pcie.o $(MODULE)_dmabuf.o $(MODULE)_hotplug.o $(MODULE)_qdma.o +ccflags-y += \ + -I$(src)/libslash/include \ + -I$(src)/libslash/include/slash/uapi \ + -I$(src)/$(QDMA_DRV_ROOT)/libqdma \ + -I$(src)/$(QDMA_DRV_ROOT)/libqdma/qdma_access \ + -I$(src)/$(QDMA_DRV_ROOT)/libqdma/qdma_access/eqdma_cpm5_access \ + -I$(src)/$(QDMA_DRV_ROOT)/libqdma/qdma_access/eqdma_soft_access \ + -I$(src)/$(QDMA_DRV_ROOT)/libqdma/qdma_access/qdma_cpm4_access \ + -I$(src)/$(QDMA_DRV_ROOT)/libqdma/qdma_access/qdma_soft_access + + +LIBQDMA_OBJS := \ + $(QDMA_DRV_ROOT)/libqdma/qdma_mbox.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_intr.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_st_c2h.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_thread.o \ + $(QDMA_DRV_ROOT)/libqdma/libqdma_export.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_context.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_sriov.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_platform.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_descq.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_regs.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_debugfs.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_debugfs_dev.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_debugfs_queue.o \ + $(QDMA_DRV_ROOT)/libqdma/libqdma_config.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_device.o \ + $(QDMA_DRV_ROOT)/libqdma/xdev.o \ + $(QDMA_DRV_ROOT)/libqdma/thread.o + +QDMA_ACCESS_OBJS := \ + $(QDMA_DRV_ROOT)/libqdma/qdma_access/qdma_mbox_protocol.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_access/qdma_list.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_access/qdma_access_common.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_access/qdma_resource_mgmt.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.o \ + $(QDMA_DRV_ROOT)/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.o + +$(MODULE)-objs += $(LIBQDMA_OBJS) $(QDMA_ACCESS_OBJS) + + +all: + $(MAKE) -C $(KDIR) M=$(PWD) modules + +clean: + $(MAKE) -C $(KDIR) M=$(PWD) clean + +install: all + sudo install -d -m 755 /lib/modules/$(shell uname -r)/extra + sudo install -m 644 $(MODULE).ko /lib/modules/$(shell uname -r)/extra + sudo depmod -a + +.PHONY: all clean install diff --git a/driver/libslash/CMakeLists.txt b/driver/libslash/CMakeLists.txt new file mode 100644 index 00000000..ba129b0c --- /dev/null +++ b/driver/libslash/CMakeLists.txt @@ -0,0 +1,99 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +cmake_minimum_required(VERSION 3.16) + +project(libslash + VERSION 0.1.0 + LANGUAGES C +) + +# Allow user to choose shared vs static (standard CMake variable) +option(BUILD_SHARED_LIBS "Build shared libraries" ON) +# Optionally build examples +option(SLASH_BUILD_EXAMPLES "Build example executables" ON) + +include(CTest) +option(SLASH_BUILD_TESTS "Build libslash unit tests" ON) + +include(GNUInstallDirs) +include(CMakePackageConfigHelpers) + +add_subdirectory(src) +if(SLASH_BUILD_EXAMPLES) + add_subdirectory(examples) +endif() +if(BUILD_TESTING AND SLASH_BUILD_TESTS) + add_subdirectory(tests) +endif() + +# -------- Installation: headers and library -------- +# Public headers are under include/ (layout: include/slash/*.h) +install( + DIRECTORY "${PROJECT_SOURCE_DIR}/include/" + DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +install( + TARGETS slash + EXPORT slashTargets + ARCHIVE DESTINATION "${CMAKE_INSTALL_LIBDIR}" + LIBRARY DESTINATION "${CMAKE_INSTALL_LIBDIR}" + RUNTIME DESTINATION "${CMAKE_INSTALL_BINDIR}" + INCLUDES DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +# -------- CMake package configuration -------- +# Generate the version file +write_basic_package_version_file( + "${CMAKE_CURRENT_BINARY_DIR}/slashConfigVersion.cmake" + VERSION ${PROJECT_VERSION} + COMPATIBILITY SameMinorVersion +) + +# Configure the main package config from template +configure_package_config_file( + "${PROJECT_SOURCE_DIR}/cmake/slashConfig.cmake.in" + "${CMAKE_CURRENT_BINARY_DIR}/slashConfig.cmake" + INSTALL_DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/slash" +) + +# Export targets for *install* tree +install( + EXPORT slashTargets + NAMESPACE slash:: + FILE slashTargets.cmake + DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/slash" +) + +# Install the config + version files +install( + FILES + "${CMAKE_CURRENT_BINARY_DIR}/slashConfig.cmake" + "${CMAKE_CURRENT_BINARY_DIR}/slashConfigVersion.cmake" + DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/slash" +) + +# Export targets for *build* tree so a project can use this directory directly +export( + EXPORT slashTargets + NAMESPACE slash:: + FILE "${CMAKE_CURRENT_BINARY_DIR}/slashTargets.cmake" +) diff --git a/driver/libslash/cmake/slashConfig.cmake.in b/driver/libslash/cmake/slashConfig.cmake.in new file mode 100644 index 00000000..53bf2ed5 --- /dev/null +++ b/driver/libslash/cmake/slashConfig.cmake.in @@ -0,0 +1,26 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +@PACKAGE_INIT@ + +# If you have dependencies, call find_dependency() here. +# e.g.: find_dependency(Threads) + +include("${CMAKE_CURRENT_LIST_DIR}/slashTargets.cmake") diff --git a/driver/libslash/examples/01_bar/CMakeLists.txt b/driver/libslash/examples/01_bar/CMakeLists.txt new file mode 100644 index 00000000..2b308c16 --- /dev/null +++ b/driver/libslash/examples/01_bar/CMakeLists.txt @@ -0,0 +1,22 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +add_executable(print_bar ${CMAKE_CURRENT_SOURCE_DIR}/print_bar.c) +target_link_libraries(print_bar PRIVATE slash::slash) diff --git a/driver/libslash/examples/01_bar/print_bar.c b/driver/libslash/examples/01_bar/print_bar.c new file mode 100644 index 00000000..7ff0e1b6 --- /dev/null +++ b/driver/libslash/examples/01_bar/print_bar.c @@ -0,0 +1,74 @@ +#define _GNU_SOURCE + +#include +#include +#include + +#include + +int main() +{ + struct slash_ioctl_bar_info *bar_info; + struct slash_bar_file *bar_file; + struct slash_ctldev *ctldev; + + ctldev = slash_ctldev_open("/dev/slash_ctl0"); + if (ctldev == NULL) { + perror("1"); + return 1; + } + + for (int i = 0; i < 6; i++) { + bar_info = slash_bar_info_read(ctldev, i); + if (bar_info == NULL) { + perror("2"); + continue; + } else { + printf("BAR Info:\n"); + printf(" bar_number: %d\n", bar_info->bar_number); + printf(" usable: %s\n", bar_info->usable ? "true" : "false"); + printf(" in_use: %s\n", bar_info->in_use ? "true" : "false"); + printf(" start_address: 0x%llx\n", bar_info->start_address); + printf(" length: 0x%llx\n", bar_info->length); + + if (bar_info->usable) { + volatile uint32_t *p; + uint32_t val; + + bar_file = slash_bar_file_open(ctldev, i, O_CLOEXEC); + if (bar_file == NULL) { + perror("3"); + continue; + } + + p = bar_file->map; + + slash_bar_file_start_write(bar_file); + + p[0] = 1; + + slash_bar_file_end_write(bar_file); + + slash_bar_file_start_read(bar_file); + + val = p[0]; + + slash_bar_file_end_read(bar_file); + + printf("BAR%d: wrote 1 read back %u\n", i, val); + + if (slash_bar_file_close(bar_file) != 0) { + perror("4"); + } + } + + slash_bar_info_free(bar_info); + } + } + + if (slash_ctldev_close(ctldev) != 0) { + perror("5"); + return 1; + } + return 0; +} diff --git a/driver/libslash/examples/02_test/CMakeLists.txt b/driver/libslash/examples/02_test/CMakeLists.txt new file mode 100644 index 00000000..a68232dd --- /dev/null +++ b/driver/libslash/examples/02_test/CMakeLists.txt @@ -0,0 +1,22 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +add_executable(some_tb ${CMAKE_CURRENT_SOURCE_DIR}/some_tb.c) +target_link_libraries(some_tb PRIVATE slash::slash) \ No newline at end of file diff --git a/driver/libslash/examples/02_test/some_tb.c b/driver/libslash/examples/02_test/some_tb.c new file mode 100644 index 00000000..5ebda375 --- /dev/null +++ b/driver/libslash/examples/02_test/some_tb.c @@ -0,0 +1,342 @@ +#include + +#include + +#include +#include +#include +#include +#include +#include + + +/* ---------- Constants / Registers ---------- */ + +#define NUM_CORES 64 +#define ITERATIONS 10 /* HLS iterations per core */ + +#define REG_AP_CTRL 0x00 +#define REG_HBM_PTR_L 0x10 +#define REG_HBM_PTR_H 0x14 +#define REG_MODE 0x1C +#define REG_LENGTH 0x24 +#define REG_ITERATIONS 0x2C + +#define MODE_WRITE 0 +#define LENGTH_WORDS 0x800000U /* 8M * 64B = 512MB */ +#define AP_DONE_VALUE 0x04U +#define UNMAPPED_SENTINEL 0xFFFFFFFFU + +#define BAR_SIZE_BYTES (128U * 1024U * 1024U) +#define TIMEOUT_SECONDS 100 +#define POLL_NS 1000000L /* 1 ms */ + +/* MMIO offsets per core (base of each core's register window) */ +static const unsigned int MMIO_OFFSETS[NUM_CORES] = { + 0x000000, 0x010000, 0x0C0000, 0x170000, + 0x220000, 0x2D0000, 0x380000, 0x3D0000, + 0x3E0000, 0x3F0000, 0x020000, 0x030000, + 0x040000, 0x050000, 0x060000, 0x070000, + 0x080000, 0x090000, 0x0A0000, 0x0B0000, + 0x0D0000, 0x0E0000, 0x0F0000, 0x100000, + 0x110000, 0x120000, 0x130000, 0x140000, + 0x150000, 0x160000, 0x180000, 0x190000, + 0x1A0000, 0x1B0000, 0x1C0000, 0x1D0000, + 0x1E0000, 0x1F0000, 0x200000, 0x210000, + 0x230000, 0x240000, 0x250000, 0x260000, + 0x270000, 0x280000, 0x290000, 0x2A0000, + 0x2B0000, 0x2C0000, 0x2E0000, 0x2F0000, + 0x300000, 0x310000, 0x320000, 0x330000, + 0x340000, 0x350000, 0x360000, 0x370000, + 0x390000, 0x3A0000, 0x3B0000, 0x3C0000 +}; + +/* ---------- Low-level MMIO helpers (unsafe: must be bracketed) ---------- */ + +static __inline__ void mmio_write32_unsafe(struct slash_bar_file *bar, unsigned int off, unsigned int val) +{ + volatile unsigned int *p; + p = (volatile unsigned int *)((char *)bar->map + off); + *p = val; +} + +static __inline__ unsigned int mmio_read32_unsafe(struct slash_bar_file *bar, unsigned int off) +{ + volatile unsigned int *p; + p = (volatile unsigned int *)((char *)bar->map + off); + return *p; +} + +/* ---------- HBM address computation without 64-bit types ---------- */ +/* + * HBM base address = 0x00000004_00000000 + * Per-core stride = 0x00000000_20000000 (512MB) + * For core in [0..63], split into HI/LO 32-bit parts: + * carry = core >> 3 + * lo = (core & 0x7) << 29 + * hi = 0x00000004 + carry + */ +static void compute_hbm_addr_parts(unsigned int core, + unsigned int *lo32, unsigned int *hi32) +{ + unsigned int carry = (core >> 3) & 0xFFFFFFFFU; + unsigned int lo = (core & 0x7U) << 29; + unsigned int hi = 0x00000004U + carry; + + *lo32 = lo; + *hi32 = hi; +} + +/* ---------- Utility: timespec difference in seconds (double) ---------- */ + +static double timespec_diff_sec(const struct timespec *a, const struct timespec *b) +{ + /* returns a - b */ + double s = (double)a->tv_sec - (double)b->tv_sec; + double n = (double)a->tv_nsec - (double)b->tv_nsec; + return s + n * 1e-9; +} + +/* ---------- Core routines ---------- */ + +static int prepare_all_cores(struct slash_bar_file *bar, unsigned int iterations) +{ + int rc; + unsigned int i; + + rc = slash_bar_file_start_write(bar); + if (rc < 0) { + fprintf(stderr, "start_write failed: %s\n", strerror(errno)); + return -1; + } + + for (i = 0; i < NUM_CORES; ++i) { + unsigned int base = MMIO_OFFSETS[i]; + unsigned int lo32, hi32; + + compute_hbm_addr_parts(i, &lo32, &hi32); + + mmio_write32_unsafe(bar, base + REG_HBM_PTR_L, lo32); + mmio_write32_unsafe(bar, base + REG_HBM_PTR_H, hi32); + mmio_write32_unsafe(bar, base + REG_MODE, MODE_WRITE); + mmio_write32_unsafe(bar, base + REG_LENGTH, LENGTH_WORDS); + mmio_write32_unsafe(bar, base + REG_ITERATIONS, iterations); + } + + rc = slash_bar_file_end_write(bar); + if (rc < 0) { + fprintf(stderr, "end_write failed: %s\n", strerror(errno)); + return -1; + } + return 0; +} + +static int start_all_cores(struct slash_bar_file *bar) +{ + int rc; + unsigned int i; + + rc = slash_bar_file_start_write(bar); + if (rc < 0) { + fprintf(stderr, "start_write failed: %s\n", strerror(errno)); + return -1; + } + + for (i = 0; i < NUM_CORES; ++i) { + unsigned int base = MMIO_OFFSETS[i]; + mmio_write32_unsafe(bar, base + REG_AP_CTRL, 0x1U); + } + + rc = slash_bar_file_end_write(bar); + if (rc < 0) { + fprintf(stderr, "end_write failed: %s\n", strerror(errno)); + return -1; + } + return 0; +} + +/* Polls all cores until done or timeout. Returns 0 on success, -1 on failure. */ +static int wait_all_done(struct slash_bar_file *bar, double timeout_sec, + int *failed_out, unsigned int *num_failed_out) +{ + int rc; + unsigned char done[NUM_CORES]; + unsigned int remaining = NUM_CORES; + unsigned int i; + struct timespec t_start, t_now; + struct timespec req; + + for (i = 0; i < NUM_CORES; ++i) done[i] = 0; + + if (clock_gettime(CLOCK_MONOTONIC, &t_start) != 0) { + fprintf(stderr, "clock_gettime(CLOCK_MONOTONIC) failed: %s\n", strerror(errno)); + return -1; + } + + req.tv_sec = 0; + req.tv_nsec = POLL_NS; + + while (1) { + rc = slash_bar_file_start_read(bar); + if (rc < 0) { + fprintf(stderr, "start_read failed: %s\n", strerror(errno)); + return -1; + } + + for (i = 0; i < NUM_CORES; ++i) { + unsigned int base, v; + + if (done[i]) continue; + + base = MMIO_OFFSETS[i]; + v = mmio_read32_unsafe(bar, base + REG_AP_CTRL); + + if (v == UNMAPPED_SENTINEL) { + /* Treat as failure for this core */ + done[i] = 1; + if (failed_out) failed_out[*num_failed_out] = (int)i; + if (num_failed_out) (*num_failed_out)++; + if (remaining > 0) remaining--; + fprintf(stderr, "[!] Core %u BAR region not mapped (read 0xFFFFFFFF)\n", i); + } else if (v == AP_DONE_VALUE) { + done[i] = 1; + if (remaining > 0) remaining--; + } else { + /* still running */ + } + } + + rc = slash_bar_file_end_read(bar); + if (rc < 0) { + fprintf(stderr, "end_read failed: %s\n", strerror(errno)); + return -1; + } + + if (remaining == 0) break; + + if (clock_gettime(CLOCK_MONOTONIC, &t_now) != 0) { + fprintf(stderr, "clock_gettime() failed: %s\n", strerror(errno)); + return -1; + } + if (timespec_diff_sec(&t_now, &t_start) >= timeout_sec) { + /* Timeout: mark any still-running cores as failed */ + for (i = 0; i < NUM_CORES; ++i) { + if (!done[i]) { + if (failed_out) failed_out[*num_failed_out] = (int)i; + if (num_failed_out) (*num_failed_out)++; + } + } + fprintf(stderr, "[!] Timeout waiting for cores\n"); + return -1; + } + + /* 1 ms sleep between polls */ + nanosleep(&req, (struct timespec *)0); + } + + return 0; +} + +/* ---------- Public entry: run the testbench on an already-mapped BAR ---------- */ + +int run_testbench(struct slash_bar_file *bar) +{ + int rc; + struct timespec t0, t1; + int failed_idx[NUM_CORES]; + unsigned int num_failed = 0; + double duration_s, total_bytes, throughput_gib_s; + + if (!bar || !bar->map) { + fprintf(stderr, "Invalid BAR mapping\n"); + return -1; + } + if (bar->len < BAR_SIZE_BYTES) { + /* Not strictly required if your design only uses the listed offsets, + but keep the check to mirror the Python's BAR_SIZE intent. */ + /* Not fatal; warn only. */ + fprintf(stderr, "[!] Warning: BAR length (%lu) < expected (%u)\n", + (unsigned long)bar->len, (unsigned int)BAR_SIZE_BYTES); + } + + /* Prepare cores */ + if (prepare_all_cores(bar, (unsigned int)ITERATIONS) < 0) { + return -1; + } + + /* Start timing before asserting start, like the Python version */ + if (clock_gettime(CLOCK_MONOTONIC, &t0) != 0) { + fprintf(stderr, "clock_gettime(CLOCK_MONOTONIC) failed: %s\n", strerror(errno)); + return -1; + } + + /* Kick all cores */ + rc = start_all_cores(bar); + if (rc < 0) return -1; + + /* Wait for completion (single-threaded polling) */ + num_failed = 0; + rc = wait_all_done(bar, (double)TIMEOUT_SECONDS, failed_idx, &num_failed); + + if (clock_gettime(CLOCK_MONOTONIC, &t1) != 0) { + fprintf(stderr, "clock_gettime(CLOCK_MONOTONIC) failed: %s\n", strerror(errno)); + return -1; + } + + duration_s = timespec_diff_sec(&t1, &t0); + + if (rc < 0) { + unsigned int i; + if (num_failed > 0) { + fprintf(stderr, "[!] Cores failed: "); + for (i = 0; i < num_failed; ++i) { + fprintf(stderr, "%d%s", failed_idx[i], (i + 1 < num_failed) ? ", " : ""); + } + fprintf(stderr, "\n"); + } + return -1; + } + + /* Success: compute throughput (GiB/s) */ + total_bytes = (double)NUM_CORES * (double)ITERATIONS * (512.0 * 1024.0 * 1024.0); /* 512MB per iter per core */ + throughput_gib_s = total_bytes / duration_s / (1024.0 * 1024.0 * 1024.0); + + printf("[\xE2\x9C\x93] All cores done in %.3f ms (%.2f GiB/s)\n", + duration_s * 1000.0, throughput_gib_s); + + return 0; +} + +int main() +{ + struct slash_bar_file *bar_file; + struct slash_ctldev *ctldev; + + ctldev = slash_ctldev_open("/dev/slash_ctl0"); + if (ctldev == NULL) { + perror("1"); + return 1; + } + + bar_file = slash_bar_file_open(ctldev, 0, 0); + if (bar_file == NULL) { + perror("2"); + (void) slash_ctldev_close(ctldev); + return 2; + } + + run_testbench(bar_file); + + if (slash_bar_file_close(bar_file) != 0) { + perror("3"); + (void) slash_ctldev_close(ctldev); + return 3; + } + + if (slash_ctldev_close(ctldev) != 0) { + perror("4"); + return 4; + } + + return 0; +} diff --git a/driver/libslash/examples/CMakeLists.txt b/driver/libslash/examples/CMakeLists.txt new file mode 100644 index 00000000..645cd881 --- /dev/null +++ b/driver/libslash/examples/CMakeLists.txt @@ -0,0 +1,22 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +add_subdirectory(01_bar) +add_subdirectory(02_test) diff --git a/driver/libslash/include/slash/ctldev.h b/driver/libslash/include/slash/ctldev.h new file mode 100644 index 00000000..5058f80d --- /dev/null +++ b/driver/libslash/include/slash/ctldev.h @@ -0,0 +1,86 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef LIBSLASH_CTLDEV_H +#define LIBSLASH_CTLDEV_H + +#include "uapi/slash_interface.h" + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct slash_ctldev { + int fd; + bool mock; +}; + +struct slash_bar_file { + void *map; + size_t len; + int fd; + bool mock; + char *mock_path; +}; + +struct slash_ctldev *slash_ctldev_open(const char *path); +int slash_ctldev_close(struct slash_ctldev *ctldev); + +struct slash_ioctl_bar_info *slash_bar_info_read(struct slash_ctldev *ctldev, int bar_number); +void slash_bar_info_free(struct slash_ioctl_bar_info *ctldev); + +struct slash_bar_file *slash_bar_file_open(struct slash_ctldev *ctldev, int bar_number, int flags); +int slash_bar_file_close(struct slash_bar_file *bar_file); + +static __inline__ int slash_bar_file_sync(struct slash_bar_file *bar_file, unsigned int flags) +{ + struct dma_buf_sync sync = { .flags = flags }; + + if (bar_file->mock) { + return 0; + } + + return ioctl(bar_file->fd, DMA_BUF_IOCTL_SYNC, &sync); +} + +static __inline__ int slash_bar_file_start_write(struct slash_bar_file *bar_file) +{ + return slash_bar_file_sync(bar_file, DMA_BUF_SYNC_START | DMA_BUF_SYNC_WRITE); +} + +static __inline__ int slash_bar_file_end_write(struct slash_bar_file *bar_file) +{ + return slash_bar_file_sync(bar_file, DMA_BUF_SYNC_END | DMA_BUF_SYNC_WRITE); +} + +static __inline__ int slash_bar_file_start_read(struct slash_bar_file *bar_file) +{ + return slash_bar_file_sync(bar_file, DMA_BUF_SYNC_START | DMA_BUF_SYNC_READ); +} + +static __inline__ int slash_bar_file_end_read(struct slash_bar_file *bar_file) +{ + return slash_bar_file_sync(bar_file, DMA_BUF_SYNC_END | DMA_BUF_SYNC_READ); +} + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#endif /* LIBSLASH_CTLDEV_H */ diff --git a/driver/libslash/include/slash/qdma.h b/driver/libslash/include/slash/qdma.h new file mode 100644 index 00000000..9c4bfea8 --- /dev/null +++ b/driver/libslash/include/slash/qdma.h @@ -0,0 +1,51 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef LIBSLASH_QDMA_H +#define LIBSLASH_QDMA_H + +#include "uapi/slash_interface.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct slash_qdma { + int fd; + bool mock; +}; + +struct slash_qdma *slash_qdma_open(const char *path); +int slash_qdma_close(struct slash_qdma *qdma); + +int slash_qdma_info_read(struct slash_qdma *qdma, struct slash_qdma_info *info); + +int slash_qdma_qpair_add(struct slash_qdma *qdma, + struct slash_qdma_qpair_add *req); + +int slash_qdma_qpair_start(struct slash_qdma *qdma, uint32_t qid); +int slash_qdma_qpair_stop(struct slash_qdma *qdma, uint32_t qid); +int slash_qdma_qpair_del(struct slash_qdma *qdma, uint32_t qid); + +int slash_qdma_qpair_get_fd(struct slash_qdma *qdma, uint32_t qid, int flags); + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#endif /* LIBSLASH_QDMA_H */ + diff --git a/driver/libslash/include/slash/uapi/slash_hotplug.h b/driver/libslash/include/slash/uapi/slash_hotplug.h new file mode 100644 index 00000000..2dc7e52b --- /dev/null +++ b/driver/libslash/include/slash/uapi/slash_hotplug.h @@ -0,0 +1,41 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef SLASH_HOTPLUG_UAPI_H +#define SLASH_HOTPLUG_UAPI_H + +#include + +#ifdef __KERNEL__ +#include +#else +#include +#endif /* __KERNEL__ */ + +#define SLASH_HOTPLUG_DEVICE_NAME "slash_hotplug" +#define SLASH_HOTPLUG_BDF_LEN 32 + +struct slash_hotplug_device_request { + __u32 size; + char bdf[SLASH_HOTPLUG_BDF_LEN]; /* Optional: empty string targets the only tracked device */ +}; + +#define SLASH_HOTPLUG_IOCTL_MAGIC 'w' + +#define SLASH_HOTPLUG_IOCTL_RESCAN _IO(SLASH_HOTPLUG_IOCTL_MAGIC, 0x30) +#define SLASH_HOTPLUG_IOCTL_REMOVE _IOW(SLASH_HOTPLUG_IOCTL_MAGIC, 0x31, struct slash_hotplug_device_request) +#define SLASH_HOTPLUG_IOCTL_TOGGLE_SBR _IOW(SLASH_HOTPLUG_IOCTL_MAGIC, 0x32, struct slash_hotplug_device_request) +#define SLASH_HOTPLUG_IOCTL_HOTPLUG _IOW(SLASH_HOTPLUG_IOCTL_MAGIC, 0x33, struct slash_hotplug_device_request) + +#endif /* SLASH_HOTPLUG_UAPI_H */ diff --git a/driver/libslash/include/slash/uapi/slash_interface.h b/driver/libslash/include/slash/uapi/slash_interface.h new file mode 100644 index 00000000..55fe6f1f --- /dev/null +++ b/driver/libslash/include/slash/uapi/slash_interface.h @@ -0,0 +1,125 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef SLASH_USER_H +#define SLASH_USER_H + +#include + +#ifdef __KERNEL__ +#include +#else +#include +#endif /* __KERNEL__ */ + +/** + * ioctl numbers are defined here: + * https://www.kernel.org/doc/Documentation/userspace-api/ioctl/ioctl-number.rst + * + * The following codes are currently free: + * Code: 'v' + * Seq#: 30-BF + * + * We will aim to be good citizens and use a small range like 'v' 30-4F, which is 32 ioctls. + * However, both these codes and the range used is subject to change for future versoins of the driver. + */ + +struct slash_ioctl_bar_info { + __u32 size; + + /* Userspace to kernel */ + __u8 bar_number; + + /* Kernel to userspace */ + __u8 usable; + __u8 in_use; + __u8 pad0; + + __u64 start_address; + __u64 length; +}; + +struct slash_ioctl_bar_fd_request { + __u32 size; + + /* Userspace to kernel */ + __u8 bar_number; + __u8 pad0; + __u16 pad1; + + __u32 flags; /* Only O_CLOEXEC */ + + /* Kernel to userspace */ + __u64 length; +}; + +#define SLASH_CTLDEV_IOCTL_GET_BAR_INFO _IOWR('v', 0x30, struct slash_ioctl_bar_info) +#define SLASH_CTLDEV_IOCTL_GET_BAR_FD _IOWR('v', 0x31, struct slash_ioctl_bar_fd_request) + +/* The following are QDMA operations */ + +struct slash_qdma_info { + __u32 size; + + /* Kernel to userspace */ + __u32 qsets_max; + __u32 msix_qvecs; + __u32 vf_max; + __u32 caps; +}; + +struct slash_qdma_qpair_add { + __u32 size; + + /* Userspace to kernel */ + __u32 mode; + __u32 dir_mask; + + __u32 h2c_ring_sz; + __u32 c2h_ring_sz; + __u32 cmpt_ring_sz; + + /* Kernel to userspace */ + __u32 qid; +}; + +enum { + SLASH_QDMA_QUEUE_OP_START, + SLASH_QDMA_QUEUE_OP_STOP, + SLASH_QDMA_QUEUE_OP_DEL, +}; + +struct slash_qdma_qpair_op { + __u32 size; + + /* Userspace to kernel */ + __u32 qid; + __u32 op; +}; + +struct slash_qdma_qpair_fd_request { + __u32 size; + + /* Userspace to kernel */ + __u32 qid; + __u32 flags; /* Only O_CLOEXEC */ +}; + +#define SLASH_QDMA_IOCTL_INFO _IOWR('v', 0x50, struct slash_qdma_info) +#define SLASH_QDMA_IOCTL_QPAIR_ADD _IOWR('v', 0x51, struct slash_qdma_qpair_add) +#define SLASH_QDMA_IOCTL_Q_OP _IOWR('v', 0x52, struct slash_qdma_qpair_op) +#define SLASH_QDMA_IOCTL_QPAIR_GET_FD _IOWR('v', 0x53, struct slash_qdma_qpair_fd_request) + + +#endif diff --git a/driver/libslash/src/CMakeLists.txt b/driver/libslash/src/CMakeLists.txt new file mode 100644 index 00000000..c0ab5f96 --- /dev/null +++ b/driver/libslash/src/CMakeLists.txt @@ -0,0 +1,47 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +# Library sources (list explicitly; avoid GLOB for reproducible builds) +add_library(slash + ${CMAKE_CURRENT_SOURCE_DIR}/ctldev.c + ${CMAKE_CURRENT_SOURCE_DIR}/ctldev_mock.c + ${CMAKE_CURRENT_SOURCE_DIR}/qdma.c +) + +# Provide an alias target with namespace (nice for internal use too) +add_library(slash::slash ALIAS slash) + +# C standard / properties +set_target_properties(slash PROPERTIES + C_STANDARD 90 + C_STANDARD_REQUIRED YES + C_EXTENSIONS NO + VERSION ${PROJECT_VERSION} + SOVERSION ${PROJECT_VERSION_MAJOR} +) + +# Public include dir (for consumers) and private include dir (for .c / private headers) +target_include_directories(slash + PUBLIC + $ + $ + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR} +) diff --git a/driver/libslash/src/ctldev.c b/driver/libslash/src/ctldev.c new file mode 100644 index 00000000..e9893ab7 --- /dev/null +++ b/driver/libslash/src/ctldev.c @@ -0,0 +1,198 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#define _GNU_SOURCE + +#include + +#include "ctldev_mock.h" + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +struct slash_ctldev *slash_ctldev_open(const char *path) +{ + struct slash_ctldev *ctldev; + + if (path != NULL && strcmp(path, "@mock") == 0) { + return slash_ctldev_mock_open(); + } + + ctldev = calloc(1, sizeof(*ctldev)); + if (ctldev == NULL) { + return NULL; + } + + ctldev->fd = open(path, O_RDWR); + if (ctldev->fd < 0) { + goto err_free_ctldev; + } + + ctldev->mock = false; + + return ctldev; + +err_free_ctldev: + free(ctldev); + + return NULL; +} + +int slash_ctldev_close(struct slash_ctldev *ctldev) +{ + int ret; + + if (ctldev == NULL) { + errno = EINVAL; + return -1; + } + + if (ctldev->mock) { + return slash_ctldev_mock_close(ctldev); + } + + ret = 0; + if (ctldev->fd >= 0 && close(ctldev->fd) != 0) { + ret = -1; + } + + free(ctldev); + + return ret; +} + +struct slash_ioctl_bar_info *slash_bar_info_read(struct slash_ctldev *ctldev, int bar_number) +{ + int ret; + struct slash_ioctl_bar_info *bar_info; + + if (ctldev == NULL) { + errno = EINVAL; + return NULL; + } + + if (ctldev->mock) { + return slash_bar_info_mock_read(ctldev, bar_number); + } + + bar_info = calloc(1, sizeof(*bar_info)); + if (bar_info == NULL) { + return NULL; + } + + bar_info->size = sizeof(*bar_info); + bar_info->bar_number = bar_number; + + ret = ioctl(ctldev->fd, SLASH_CTLDEV_IOCTL_GET_BAR_INFO, bar_info); + if (ret < 0) { + goto err_free_bar_info; + } + + return bar_info; + +err_free_bar_info: + free(bar_info); + + return NULL; +} + +struct slash_bar_file *slash_bar_file_open(struct slash_ctldev *ctldev, int bar_number, int flags) +{ + struct slash_ioctl_bar_fd_request req = { + .size = sizeof(req), + + .bar_number = bar_number, + .flags = flags, + }; + + struct slash_bar_file *bar_file; + + if (ctldev == NULL) { + errno = EINVAL; + return NULL; + } + + if (ctldev->mock) { + return slash_bar_file_mock_open(ctldev, bar_number, flags); + } + + bar_file = calloc(1, sizeof(*bar_file)); + if (bar_file == NULL) { + return NULL; + } + + bar_file->fd = ioctl(ctldev->fd, SLASH_CTLDEV_IOCTL_GET_BAR_FD, &req); + if (bar_file->fd < 0) { + goto err_free_bar_file; + } + + bar_file->len = (size_t) req.length; + + bar_file->map = mmap(NULL, bar_file->len, PROT_READ | PROT_WRITE, MAP_SHARED, bar_file->fd, 0); + if (bar_file->map == MAP_FAILED) { + goto err_close_fd; + } + + bar_file->mock = false; + + return bar_file; + +err_close_fd: + (void) close(bar_file->fd); + +err_free_bar_file: + free(bar_file); + + return NULL; +} + +int slash_bar_file_close(struct slash_bar_file *bar_file) +{ + int ret = 0; + + if (bar_file == NULL) { + errno = EINVAL; + return -1; + } + + if (bar_file->mock) { + return slash_bar_file_mock_close(bar_file); + } + + if (munmap(bar_file->map, bar_file->len) != 0) { + ret = -1; + } + + if (close(bar_file->fd) != 0) { + ret = -1; + } + + free(bar_file); + + return ret; +} + +void slash_bar_info_free(struct slash_ioctl_bar_info *bar_info) +{ + free(bar_info); +} diff --git a/driver/libslash/src/ctldev_mock.c b/driver/libslash/src/ctldev_mock.c new file mode 100644 index 00000000..5e8dcab7 --- /dev/null +++ b/driver/libslash/src/ctldev_mock.c @@ -0,0 +1,276 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#define _GNU_SOURCE + +#include "ctldev_mock.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SLASH_MOCK_BAR_SIZE (64ULL * 1024ULL * 1024ULL) + +static uint64_t slash_mock_random(void) +{ + uint64_t value; + ssize_t ret; + ret = getrandom(&value, sizeof(value), 0); + + if (ret != (ssize_t) sizeof(value)) { + struct timespec ts; + + if (clock_gettime(CLOCK_REALTIME, &ts) == 0) { + value = ((uint64_t) ts.tv_sec << 32) ^ (uint64_t) ts.tv_nsec; + } else { + value = (uint64_t) time(NULL); + } + + value ^= (uint64_t) (uintptr_t) &value; + value ^= (uint64_t) getpid(); + } + + return value; +} + +static int slash_mock_create_backing_file(char **path_out) +{ + const char *env_dir = getenv("XDG_RUNTIME_DIR"); + const char *dir_path = {0}; + int last_errno = EIO; + size_t i; + int attempt; + + if (env_dir != NULL && env_dir[0] != '\0') { + dir_path = env_dir; + } else { + dir_path = "/tmp"; + } + + for (attempt = 0; attempt < 32; ++attempt) { + uint64_t rnd; + int needed; + size_t buf_len; + char *path; + int fd; + + rnd = slash_mock_random(); + needed = snprintf(NULL, 0, "%s/%s%llu", dir_path, "slash.mock.", (unsigned long long) rnd); + if (needed < 0) { + last_errno = EINVAL; + continue; + } + + if ((size_t) needed >= PATH_MAX) { + last_errno = ENAMETOOLONG; + continue; + } + + buf_len = (size_t) needed + 1; + path = malloc(buf_len); + if (path == NULL) { + last_errno = ENOMEM; + errno = ENOMEM; + return -1; + } + + (void) snprintf(path, buf_len, "%s/slash.mock.%llu", dir_path, (unsigned long long) rnd); + + fd = open(path, O_RDWR | O_CREAT | O_EXCL | O_CLOEXEC, 0600); + if (fd >= 0) { + *path_out = path; + return fd; + } + + last_errno = errno; + free(path); + + if (errno == EEXIST) { + continue; + } + + if (errno == ENOENT || errno == EACCES) { + break; + } + + return -1; + } + + errno = last_errno; + return -1; +} + +struct slash_ctldev *slash_ctldev_mock_open(void) +{ + struct slash_ctldev *ctldev; + + ctldev = calloc(1, sizeof(*ctldev)); + if (ctldev == NULL) { + return NULL; + } + + ctldev->fd = -1; + ctldev->mock = true; + + return ctldev; +} + +int slash_ctldev_mock_close(struct slash_ctldev *ctldev) +{ + if (ctldev == NULL) { + errno = EINVAL; + return -1; + } + + free(ctldev); + + return 0; +} + +struct slash_ioctl_bar_info *slash_bar_info_mock_read(struct slash_ctldev *ctldev, int bar_number) +{ + struct slash_ioctl_bar_info *bar_info; + + if (ctldev == NULL || !ctldev->mock) { + errno = EINVAL; + return NULL; + } + + bar_info = calloc(1, sizeof(*bar_info)); + if (bar_info == NULL) { + return NULL; + } + + bar_info->size = sizeof(*bar_info); + bar_info->bar_number = (uint8_t) bar_number; + + if (bar_number == 0) { + bar_info->usable = 1; + bar_info->in_use = 0; + bar_info->start_address = 0; + bar_info->length = SLASH_MOCK_BAR_SIZE; + } else { + bar_info->usable = 0; + bar_info->in_use = 0; + bar_info->start_address = 0; + bar_info->length = 0; + } + + return bar_info; +} + +void slash_bar_info_mock_free(struct slash_ioctl_bar_info *bar_info) +{ + free(bar_info); +} + +struct slash_bar_file *slash_bar_file_mock_open(struct slash_ctldev *ctldev, int bar_number, int flags) +{ + (void) flags; + + struct slash_bar_file *bar_file; + char *path; + int fd; + void *map; + + if (ctldev == NULL || !ctldev->mock) { + errno = EINVAL; + return NULL; + } + + if (bar_number != 0) { + errno = ENODEV; + return NULL; + } + + bar_file = calloc(1, sizeof(*bar_file)); + if (bar_file == NULL) { + return NULL; + } + + path = NULL; + fd = slash_mock_create_backing_file(&path); + if (fd < 0) { + free(bar_file); + return NULL; + } + + if (ftruncate(fd, (off_t) SLASH_MOCK_BAR_SIZE) != 0) { + (void) unlink(path); + free(path); + (void) close(fd); + free(bar_file); + return NULL; + } + + map = mmap(NULL, (size_t) SLASH_MOCK_BAR_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); + if (map == MAP_FAILED) { + (void) unlink(path); + free(path); + (void) close(fd); + free(bar_file); + return NULL; + } + + bar_file->fd = fd; + bar_file->len = (size_t) SLASH_MOCK_BAR_SIZE; + bar_file->map = map; + bar_file->mock = true; + bar_file->mock_path = path; + + return bar_file; +} + +int slash_bar_file_mock_close(struct slash_bar_file *bar_file) +{ + int ret = 0; + + if (bar_file == NULL) { + errno = EINVAL; + return -1; + } + + if (bar_file->map != NULL && bar_file->len != 0) { + if (munmap(bar_file->map, bar_file->len) != 0) { + ret = -1; + } + } + + if (bar_file->fd >= 0) { + if (close(bar_file->fd) != 0) { + ret = -1; + } + } + + if (bar_file->mock_path != NULL) { + if (unlink(bar_file->mock_path) != 0 && errno != ENOENT) { + ret = -1; + } + free(bar_file->mock_path); + } + + free(bar_file); + + return ret; +} diff --git a/driver/libslash/src/ctldev_mock.h b/driver/libslash/src/ctldev_mock.h new file mode 100644 index 00000000..5e4e61e8 --- /dev/null +++ b/driver/libslash/src/ctldev_mock.h @@ -0,0 +1,29 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef LIBSLASH_CTLDEV_MOCK_H +#define LIBSLASH_CTLDEV_MOCK_H + +#include + +struct slash_ctldev *slash_ctldev_mock_open(void); +int slash_ctldev_mock_close(struct slash_ctldev *ctldev); + +struct slash_ioctl_bar_info *slash_bar_info_mock_read(struct slash_ctldev *ctldev, int bar_number); +void slash_bar_info_mock_free(struct slash_ioctl_bar_info *ctldev); + +struct slash_bar_file *slash_bar_file_mock_open(struct slash_ctldev *ctldev, int bar_number, int flags); +int slash_bar_file_mock_close(struct slash_bar_file *bar_file); + +#endif /* LIBSLASH_CTLDEV_MOCK_H */ diff --git a/driver/libslash/src/qdma.c b/driver/libslash/src/qdma.c new file mode 100644 index 00000000..caec710b --- /dev/null +++ b/driver/libslash/src/qdma.c @@ -0,0 +1,186 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#define _GNU_SOURCE + +#include + +#include +#include +#include +#include +#include +#include + +#include + +struct slash_qdma *slash_qdma_open(const char *path) +{ + struct slash_qdma *qdma; + + if (path == NULL) { + errno = EINVAL; + return NULL; + } + + qdma = calloc(1, sizeof(*qdma)); + if (qdma == NULL) { + return NULL; + } + + qdma->fd = open(path, O_RDWR); + if (qdma->fd < 0) { + free(qdma); + return NULL; + } + + qdma->mock = false; + + return qdma; +} + +int slash_qdma_close(struct slash_qdma *qdma) +{ + int ret; + + if (qdma == NULL) { + errno = EINVAL; + return -1; + } + + ret = 0; + if (qdma->fd >= 0 && close(qdma->fd) != 0) { + ret = -1; + } + + free(qdma); + + return ret; +} + +int slash_qdma_info_read(struct slash_qdma *qdma, struct slash_qdma_info *info) +{ + struct slash_qdma_info tmp; + int ret; + + if (qdma == NULL || info == NULL) { + errno = EINVAL; + return -1; + } + + memset(&tmp, 0, sizeof(tmp)); + tmp.size = sizeof(tmp); + + ret = ioctl(qdma->fd, SLASH_QDMA_IOCTL_INFO, &tmp); + if (ret < 0) { + return -1; + } + + *info = tmp; + + return 0; +} + +int slash_qdma_qpair_add(struct slash_qdma *qdma, + struct slash_qdma_qpair_add *req) +{ + struct slash_qdma_qpair_add tmp; + int ret; + + if (qdma == NULL || req == NULL) { + errno = EINVAL; + return -1; + } + + memset(&tmp, 0, sizeof(tmp)); + tmp.size = sizeof(tmp); + tmp.mode = req->mode; + tmp.dir_mask = req->dir_mask; + tmp.h2c_ring_sz = req->h2c_ring_sz; + tmp.c2h_ring_sz = req->c2h_ring_sz; + tmp.cmpt_ring_sz = req->cmpt_ring_sz; + + ret = ioctl(qdma->fd, SLASH_QDMA_IOCTL_QPAIR_ADD, &tmp); + if (ret < 0) { + return -1; + } + + *req = tmp; + + return 0; +} + +static int slash_qdma_qpair_op(struct slash_qdma *qdma, + uint32_t qid, + uint32_t op) +{ + struct slash_qdma_qpair_op req; + int ret; + + if (qdma == NULL) { + errno = EINVAL; + return -1; + } + + memset(&req, 0, sizeof(req)); + req.size = sizeof(req); + req.qid = qid; + req.op = op; + + ret = ioctl(qdma->fd, SLASH_QDMA_IOCTL_Q_OP, &req); + if (ret < 0) { + return -1; + } + + return 0; +} + +int slash_qdma_qpair_start(struct slash_qdma *qdma, uint32_t qid) +{ + return slash_qdma_qpair_op(qdma, qid, SLASH_QDMA_QUEUE_OP_START); +} + +int slash_qdma_qpair_stop(struct slash_qdma *qdma, uint32_t qid) +{ + return slash_qdma_qpair_op(qdma, qid, SLASH_QDMA_QUEUE_OP_STOP); +} + +int slash_qdma_qpair_del(struct slash_qdma *qdma, uint32_t qid) +{ + return slash_qdma_qpair_op(qdma, qid, SLASH_QDMA_QUEUE_OP_DEL); +} + +int slash_qdma_qpair_get_fd(struct slash_qdma *qdma, uint32_t qid, int flags) +{ + struct slash_qdma_qpair_fd_request req; + int fd; + + if (qdma == NULL) { + errno = EINVAL; + return -1; + } + + memset(&req, 0, sizeof(req)); + req.size = sizeof(req); + req.qid = qid; + req.flags = flags; + + fd = ioctl(qdma->fd, SLASH_QDMA_IOCTL_QPAIR_GET_FD, &req); + if (fd < 0) { + return -1; + } + + return fd; +} + diff --git a/driver/libslash/tests/CMakeLists.txt b/driver/libslash/tests/CMakeLists.txt new file mode 100644 index 00000000..d46b5b0c --- /dev/null +++ b/driver/libslash/tests/CMakeLists.txt @@ -0,0 +1,14 @@ +add_executable(slash_mock_tests + slash_mock_tests.c +) + +set_target_properties(slash_mock_tests PROPERTIES + C_STANDARD 90 + C_STANDARD_REQUIRED YES + C_EXTENSIONS NO +) + +target_link_libraries(slash_mock_tests PRIVATE slash) +target_include_directories(slash_mock_tests PRIVATE ${PROJECT_SOURCE_DIR}/include) + +add_test(NAME slash_mock_tests COMMAND slash_mock_tests) diff --git a/driver/libslash/tests/slash_mock_tests.c b/driver/libslash/tests/slash_mock_tests.c new file mode 100644 index 00000000..904f6f23 --- /dev/null +++ b/driver/libslash/tests/slash_mock_tests.c @@ -0,0 +1,159 @@ +#include + +#include +#include +#include +#include + +static int test_bar_info(struct slash_ctldev *ctldev) +{ + struct slash_ioctl_bar_info *bar0; + struct slash_ioctl_bar_info *bar1; + + bar0 = slash_bar_info_read(ctldev, 0); + if (bar0 == NULL) { + fprintf(stderr, "slash_bar_info_read returned NULL for bar 0\n"); + return 1; + } + + if (bar0->bar_number != 0) { + fprintf(stderr, "Unexpected bar number %u for bar 0\n", (unsigned) bar0->bar_number); + slash_bar_info_free(bar0); + return 1; + } + + if (!bar0->usable || bar0->length == 0) { + fprintf(stderr, "Mock bar 0 should be usable with non-zero length\n"); + slash_bar_info_free(bar0); + return 1; + } + + slash_bar_info_free(bar0); + + bar1 = slash_bar_info_read(ctldev, 1); + if (bar1 == NULL) { + fprintf(stderr, "slash_bar_info_read returned NULL for bar 1\n"); + return 1; + } + + if (bar1->usable || bar1->length != 0) { + fprintf(stderr, "Mock bar 1 should be unusable with zero length\n"); + slash_bar_info_free(bar1); + return 1; + } + + slash_bar_info_free(bar1); + + return 0; +} + +static int test_bar_file(struct slash_ctldev *ctldev) +{ + struct slash_bar_file *bar; + uint32_t *mapped; + + bar = slash_bar_file_open(ctldev, 0, O_RDWR); + if (bar == NULL) { + fprintf(stderr, "slash_bar_file_open failed for bar 0\n"); + return 1; + } + + if (!bar->mock) { + fprintf(stderr, "Mock bar file should be marked as mock\n"); + (void) slash_bar_file_close(bar); + return 1; + } + + if (bar->len == 0 || bar->map == NULL) { + fprintf(stderr, "Mock bar file should expose a mapped region\n"); + (void) slash_bar_file_close(bar); + return 1; + } + + mapped = (uint32_t *) bar->map; + mapped[0] = 0xA5A5A5A5U; + if (mapped[0] != 0xA5A5A5A5U) { + fprintf(stderr, "Mock BAR memory did not retain written value\n"); + (void) slash_bar_file_close(bar); + return 1; + } + + if (slash_bar_file_start_write(bar) != 0) { + fprintf(stderr, "slash_bar_file_start_write failed for mock BAR\n"); + (void) slash_bar_file_close(bar); + return 1; + } + + if (slash_bar_file_end_write(bar) != 0) { + fprintf(stderr, "slash_bar_file_end_write failed for mock BAR\n"); + (void) slash_bar_file_close(bar); + return 1; + } + + if (slash_bar_file_start_read(bar) != 0) { + fprintf(stderr, "slash_bar_file_start_read failed for mock BAR\n"); + (void) slash_bar_file_close(bar); + return 1; + } + + if (slash_bar_file_end_read(bar) != 0) { + fprintf(stderr, "slash_bar_file_end_read failed for mock BAR\n"); + (void) slash_bar_file_close(bar); + return 1; + } + + if (slash_bar_file_close(bar) != 0) { + fprintf(stderr, "slash_bar_file_close failed for mock BAR\n"); + return 1; + } + + errno = 0; + bar = slash_bar_file_open(ctldev, 1, O_RDONLY); + if (bar != NULL) { + fprintf(stderr, "Mock bar file open should fail for bar 1\n"); + (void) slash_bar_file_close(bar); + return 1; + } + + if (errno != ENODEV) { + fprintf(stderr, "Expected ENODEV when opening mock bar 1, got %d\n", errno); + return 1; + } + + return 0; +} + +int main(void) +{ + struct slash_ctldev *ctldev; + + ctldev = slash_ctldev_open("@mock"); + if (ctldev == NULL) { + fprintf(stderr, "slash_ctldev_open failed for @mock\n"); + return 1; + } + + if (!ctldev->mock) { + fprintf(stderr, "Mock device should set mock flag\n"); + (void) slash_ctldev_close(ctldev); + return 1; + } + + if (test_bar_info(ctldev) != 0) { + (void) slash_ctldev_close(ctldev); + return 1; + } + + if (test_bar_file(ctldev) != 0) { + (void) slash_ctldev_close(ctldev); + return 1; + } + + if (slash_ctldev_close(ctldev) != 0) { + fprintf(stderr, "slash_ctldev_close failed for mock device\n"); + return 1; + } + + printf("libslash mock tests passed\n"); + return 0; +} diff --git a/driver/slash.h b/driver/slash.h new file mode 100644 index 00000000..2d27f541 --- /dev/null +++ b/driver/slash.h @@ -0,0 +1,20 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ +#ifndef SLASH_H +#define SLASH_H + +#include "slash_config.h" +#include "slash_interface.h" + +#endif /* SLASH_H */ diff --git a/driver/slash_config.h b/driver/slash_config.h new file mode 100644 index 00000000..2180b195 --- /dev/null +++ b/driver/slash_config.h @@ -0,0 +1,36 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ +#ifndef SLASH_CONFIG_H +#define SLASH_CONFIG_H + +#define SLASH_PCIE_VENDOR_ID 0x10EE +#define SLASH_PCIE_DEVICE_ID 0x50B6 +#define SLASH_PCIE_PF 2 +// subsystem id e + +#define SLASH_NAME "slash" + +#define SLASH_CTLDEV_NAME_FMT "slash_ctl_%s" /* uses pci_name, appears in /sys/class/misc */ +#define SLASH_CTLDEV_NODENAME_FMT "slash/ctl%d" /* uses an incrementing variable, appears in /dev */ +#define SLASH_QDMA_CTLDEV_NAME_FMT "slash_qdma_ctl_%s" +#define SLASH_QDMA_CTLDEV_NODENAME_FMT "slash/qdma_ctl%d" + +/* Mode of /dev device, prefer using an udev rule instead of changing this */ +#define SLASH_CTLDEV_MODE 0600 +#define SLASH_CTLDEV_QDMA_MODE 0600 + +#undef pr_fmt +#define pr_fmt(fmt) "%s:%s: " fmt, SLASH_NAME, __func__ + +#endif /* SLASH_CONFIG_H */ diff --git a/driver/slash_ctldev.c b/driver/slash_ctldev.c new file mode 100644 index 00000000..2251e421 --- /dev/null +++ b/driver/slash_ctldev.c @@ -0,0 +1,397 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include "slash_ctldev.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "slash.h" +#include "slash_dmabuf.h" + +#define SLASH_FIELD_SIZE(_type, _member) (sizeof(((_type *)0)->_member)) + +#define SLASH_IOCTL_BAR_INFO_MIN_SIZE \ + (offsetof(struct slash_ioctl_bar_info, bar_number) + SLASH_FIELD_SIZE(struct slash_ioctl_bar_info, bar_number)) +#define SLASH_IOCTL_BAR_INFO_RESPONSE_SIZE \ + (offsetof(struct slash_ioctl_bar_info, length) + SLASH_FIELD_SIZE(struct slash_ioctl_bar_info, length)) + +#define SLASH_IOCTL_BAR_FD_MIN_SIZE \ + (offsetof(struct slash_ioctl_bar_fd_request, flags) + SLASH_FIELD_SIZE(struct slash_ioctl_bar_fd_request, flags)) +#define SLASH_IOCTL_BAR_FD_RESPONSE_SIZE \ + (offsetof(struct slash_ioctl_bar_fd_request, length) + SLASH_FIELD_SIZE(struct slash_ioctl_bar_fd_request, length)) + +static int slash_ctldev_set_bar_info(struct pci_dev *pdev, struct slash_ctldev *ctldev); +static int slash_ctldev_create_bar_dmabufs(struct slash_ctldev *ctldev); +static int slash_ctldev_create_misc(struct slash_ctldev *ctldev); + +static void slash_ctldev_destroy_misc(struct slash_ctldev *ctldev); +static void slash_ctldev_destroy_dmabufs(struct slash_ctldev *ctldev); + +static long slash_ctldev_fop_ioctl(struct file *, unsigned int, unsigned long); + +static atomic_t slash_ctldev_devcount = ATOMIC_INIT(0); + +static struct file_operations slash_ctldev_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = slash_ctldev_fop_ioctl, +}; + +int slash_ctldev_create(struct pci_dev *pdev) +{ + int err; + + struct slash_ctldev *ctldev = kzalloc(sizeof(*ctldev), GFP_KERNEL); + if (!ctldev) { + dev_err(&pdev->dev, "ctldev: kzalloc failed\n"); + return -ENOMEM; + } + ctldev->pdev = pdev; + + dev_info(&pdev->dev, "ctldev: creating control device\n"); + + pci_set_drvdata(pdev, ctldev); + + err = slash_ctldev_set_bar_info(pdev, ctldev); + if (err) { + dev_err(&pdev->dev, "ctldev: set_bar_info failed: %d\n", err); + goto err_free_ctldev; + } + + err = slash_ctldev_create_bar_dmabufs(ctldev); + if (err) { + dev_err(&pdev->dev, "ctldev: creating BAR dma-bufs failed: %d\n", err); + /** + * We go here because there may be some dmabufs to free + * if some succeded and some failed. + */ + goto err_destroy_dmabufs; + } + + err = slash_ctldev_create_misc(ctldev); + if (err) { + dev_err(&pdev->dev, "ctldev: creating misc ctldev failed: %d\n", err); + goto err_destroy_dmabufs; + } + + dev_info(&pdev->dev, "ctldev: device created successfully\n"); + + return 0; + +err_destroy_dmabufs: + slash_ctldev_destroy_dmabufs(ctldev); + +err_free_ctldev: + kfree(ctldev); + + return err; +} + +static int slash_ctldev_set_bar_info(struct pci_dev *pdev, struct slash_ctldev *ctldev) +{ + int i; + + dev_dbg(&pdev->dev, "ctldev: probing PCI BARs\n"); + for (i = 0; i < PCI_STD_NUM_BARS; i++) { + unsigned long flags; + + if (!pci_resource_start(pdev, i)) { + dev_dbg(&pdev->dev, "ctldev: BAR%d unused\n", i); + continue; /* Unused BAR */ + } + + ctldev->bars[i].active = 1; + ctldev->bars[i].start = pci_resource_start(pdev, i); + ctldev->bars[i].end = pci_resource_end(pdev, i); + ctldev->bars[i].len = pci_resource_len(pdev, i); + flags = pci_resource_flags(pdev, i); + ctldev->bars[i].mmio = ((flags & IORESOURCE_MEM) != 0); + + + dev_info(&pdev->dev, + "Found BAR%d: 0x%pa - 0x%pa (size: %pa) %s\n", + i, &ctldev->bars[i].start, &ctldev->bars[i].end, &ctldev->bars[i].len, + (flags & IORESOURCE_MEM) ? "MMIO" : + (flags & IORESOURCE_IO) ? "IO" : "UNKNOWN"); + } + + return 0; +} + +static int slash_ctldev_create_bar_dmabufs(struct slash_ctldev *ctldev) +{ + int i; + struct dma_buf *dmabuf; + + dev_dbg(&ctldev->pdev->dev, "ctldev: creating dma-bufs for MMIO BARs\n"); + for (i = 0; i < PCI_STD_NUM_BARS; i++) { + if (!ctldev->bars[i].active || !ctldev->bars[i].mmio) { + continue; + } + + dmabuf = slash_bar_dmabuf_create(ctldev->pdev, i); + if (IS_ERR(dmabuf)) { + dev_err(&ctldev->pdev->dev, "ctldev: BAR%d dmabuf create failed: %ld\n", i, PTR_ERR(dmabuf)); + return PTR_ERR(dmabuf); + } + + ctldev->bars[i].dmabuf = dmabuf; + dev_dbg(&ctldev->pdev->dev, "ctldev: BAR%d dmabuf created\n", i); + } + + return 0; +} + +static int slash_ctldev_create_misc(struct slash_ctldev *ctldev) +{ + int err, id; + const char *name, *nodename; + + name = kasprintf(GFP_KERNEL, SLASH_CTLDEV_NAME_FMT, pci_name(ctldev->pdev)); + if (!name) { + dev_err(&ctldev->pdev->dev, "ctldev: kasprintf(name) failed\n"); + return -ENOMEM; + } + + id = atomic_inc_return(&slash_ctldev_devcount) - 1; + nodename = kasprintf(GFP_KERNEL, SLASH_CTLDEV_NODENAME_FMT, id); + if (!nodename) { + dev_err(&ctldev->pdev->dev, "ctldev: kasprintf(nodename) failed\n"); + + err = -ENOMEM; + goto err_free_name; + } + + ctldev->misc.minor = MISC_DYNAMIC_MINOR; + ctldev->misc.name = name; + ctldev->misc.fops = &slash_ctldev_fops; + ctldev->misc.parent = &ctldev->pdev->dev; + ctldev->misc.nodename = nodename; + ctldev->misc.mode = SLASH_CTLDEV_MODE; + + err = misc_register(&ctldev->misc); + if (err) { + dev_err(&ctldev->pdev->dev, "ctldev: misc_register failed: %d\n", err); + goto err_free_nodename; + } + + return 0; + +err_free_nodename: + kfree(nodename); + +err_free_name: + kfree(name); + + return err; +} + +void slash_ctldev_destroy(struct pci_dev *pdev) +{ + struct slash_ctldev *ctldev = pci_get_drvdata(pdev); + + dev_info(&pdev->dev, "ctldev: destroying control device\n"); + slash_ctldev_destroy_misc(ctldev); + slash_ctldev_destroy_dmabufs(ctldev); + + kfree(ctldev); +} + +static void slash_ctldev_destroy_misc(struct slash_ctldev *ctldev) +{ + dev_dbg(&ctldev->pdev->dev, "ctldev: deregistering misc device\n"); + misc_deregister(&ctldev->misc); + kfree(ctldev->misc.name); + kfree(ctldev->misc.nodename); + ctldev->misc.name = NULL; + ctldev->misc.nodename = NULL; +} + +static void slash_ctldev_destroy_dmabufs(struct slash_ctldev *ctldev) +{ + int i; + + for (i = 0; i < PCI_STD_NUM_BARS; i++) { + if (ctldev->bars[i].dmabuf) { + dev_dbg(&ctldev->pdev->dev, "ctldev: destroying BAR%d dmabuf\n", i); + slash_bar_dmabuf_destroy(ctldev->bars[i].dmabuf); + } + } +} + +static long slash_ctldev_fop_ioctl(struct file *file, unsigned int op, unsigned long arg) +{ + struct miscdevice *misc = file->private_data; + struct pci_dev *pdev = to_pci_dev(misc->parent); + struct slash_ctldev *ctldev = pci_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "ctldev: ioctl op=0x%x\n", op); + switch(op) { + case SLASH_CTLDEV_IOCTL_GET_BAR_INFO: { + struct slash_ioctl_bar_info bar_info = {0}; + struct slash_ctldev_bar *bar = NULL; + u32 bar_info_alleged_size; + size_t copy_size; + + if (copy_from_user(&bar_info_alleged_size, (void __user *)arg, sizeof(bar_info_alleged_size))) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO copy_from_user failed\n"); + return -EFAULT; + } + + if (bar_info_alleged_size < SLASH_IOCTL_BAR_INFO_MIN_SIZE) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO size too small (%u)\n", bar_info_alleged_size); + return -EINVAL; + } + + copy_size = min_t(size_t, bar_info_alleged_size, sizeof(bar_info)); + if (copy_from_user(&bar_info, (void __user *)arg, copy_size)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO copy_from_user failed\n"); + return -EFAULT; + } + if (copy_size < sizeof(bar_info)) { + memset((u8 *)&bar_info + copy_size, 0, sizeof(bar_info) - copy_size); + } + + if (bar_info.bar_number < 0 || bar_info.bar_number >= PCI_STD_NUM_BARS) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO invalid BAR %d\n", bar_info.bar_number); + return -EINVAL; + } + + bar = &ctldev->bars[bar_info.bar_number]; + + bar_info.usable = bar->active && bar->mmio; + bar_info.in_use = 0; + bar_info.start_address = bar->start; + bar_info.length = bar->len; + + bar_info.size = sizeof(bar_info); + + if (bar_info_alleged_size < SLASH_IOCTL_BAR_INFO_RESPONSE_SIZE) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO response size too small (%u)\n", bar_info_alleged_size); + return -EINVAL; + } + + copy_size = min_t(size_t, bar_info_alleged_size, sizeof(bar_info)); + if (copy_to_user((void __user *)arg, &bar_info, copy_size)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO copy_to_user failed\n"); + return -EFAULT; + } + if (bar_info_alleged_size > sizeof(bar_info)) { + size_t extra = bar_info_alleged_size - sizeof(bar_info); + void __user *dst = (void __user *)((unsigned long)arg + sizeof(bar_info)); + + if (clear_user(dst, extra)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO clear_user failed\n"); + return -EFAULT; + } + } + + return 0; + } + + case SLASH_CTLDEV_IOCTL_GET_BAR_FD: { + struct slash_ioctl_bar_fd_request fd_request = {0}; + struct slash_ctldev_bar *bar = NULL; + int ret; + u32 fd_request_alleged_size; + size_t copy_size; + + if (!capable(CAP_SYS_RAWIO)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD capability check failed\n"); + return -EPERM; + } + + if (copy_from_user(&fd_request_alleged_size, (void __user *)arg, sizeof(fd_request_alleged_size))) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD copy_from_user failed\n"); + return -EFAULT; + } + + if (fd_request_alleged_size < SLASH_IOCTL_BAR_FD_MIN_SIZE) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD size too small (%u)\n", fd_request_alleged_size); + return -EINVAL; + } + + copy_size = min_t(size_t, fd_request_alleged_size, sizeof(fd_request)); + if (copy_from_user(&fd_request, (void __user *)arg, copy_size)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD copy_from_user failed\n"); + return -EFAULT; + } + if (copy_size < sizeof(fd_request)) { + memset((u8 *)&fd_request + copy_size, 0, sizeof(fd_request) - copy_size); + } + + if (fd_request.bar_number < 0 || fd_request.bar_number >= PCI_STD_NUM_BARS) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD invalid BAR %d\n", fd_request.bar_number); + return -EINVAL; + } + if (fd_request.flags & ~O_CLOEXEC) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD invalid flags 0x%x\n", fd_request.flags); + return -EINVAL; + } + + bar = &ctldev->bars[fd_request.bar_number]; + + if (!bar->dmabuf) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD BAR%d has no dmabuf\n", fd_request.bar_number); + return -ENODEV; + } + + fd_request.length = bar->len; + + fd_request.size = sizeof(fd_request); + + if (fd_request_alleged_size < SLASH_IOCTL_BAR_FD_RESPONSE_SIZE) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD response size too small (%u)\n", fd_request_alleged_size); + return -EINVAL; + } + + copy_size = min_t(size_t, fd_request_alleged_size, sizeof(fd_request)); + if (copy_to_user((void __user *)arg, &fd_request, copy_size)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD copy_to_user failed\n"); + return -EFAULT; + } + if (fd_request_alleged_size > sizeof(fd_request)) { + size_t extra = fd_request_alleged_size - sizeof(fd_request); + void __user *dst = (void __user *)((unsigned long)arg + sizeof(fd_request)); + + if (clear_user(dst, extra)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD clear_user failed\n"); + return -EFAULT; + } + } + + get_dma_buf(bar->dmabuf); + ret = dma_buf_fd(bar->dmabuf, fd_request.flags); + if (ret < 0) { + dev_err(&pdev->dev, "ctldev: GET_BAR_FD dma_buf_fd failed: %d\n", ret); + dma_buf_put(bar->dmabuf); + return ret; + } + + dev_dbg(&pdev->dev, "ctldev: GET_BAR_FD BAR%d -> fd %d\n", fd_request.bar_number, ret); + return ret; + } + + default: + dev_warn(&pdev->dev, "ctldev: unknown ioctl op=0x%x\n", op); + return -ENOTTY; + } +} diff --git a/driver/slash_ctldev.h b/driver/slash_ctldev.h new file mode 100644 index 00000000..be16b51a --- /dev/null +++ b/driver/slash_ctldev.h @@ -0,0 +1,41 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef SLASH_CTLDEV_H +#define SLASH_CTLDEV_H + +#include +#include +#include + +struct slash_ctldev_bar { + unsigned int active : 1; + unsigned int mmio : 1; + resource_size_t start; + resource_size_t end; + resource_size_t len; + + struct dma_buf *dmabuf; +}; + +struct slash_ctldev { + struct pci_dev *pdev; + struct miscdevice misc; + struct slash_ctldev_bar bars[PCI_STD_NUM_BARS]; +}; + +int slash_ctldev_create(struct pci_dev *pdev); +void slash_ctldev_destroy(struct pci_dev *pdev); + +#endif /* SLASH_CTLDEV_H */ diff --git a/driver/slash_dmabuf.c b/driver/slash_dmabuf.c new file mode 100644 index 00000000..36934519 --- /dev/null +++ b/driver/slash_dmabuf.c @@ -0,0 +1,174 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include "slash_dmabuf.h" + +#include "slash.h" + +#include +#include +#include +#include + +struct slash_bar_dmabuf_data { + int bar_number; + resource_size_t len; + + struct pci_dev *pdev; +}; + +/* We only support userspace mmaps of the BAR; importing into other devices is + * intentionally rejected because a PCI BAR is not system memory. */ +static int slash_bar_dmabuf_attach(struct dma_buf *dmabuf, struct dma_buf_attachment *attach) +{ + dev_warn(attach->dev, "%s: device attachments are not supported for BAR dmabuf", SLASH_NAME); + return -EOPNOTSUPP; +} + +static void slash_bar_dmabuf_detach(struct dma_buf *dmabuf, struct dma_buf_attachment *attach) +{ + dev_dbg(attach->dev, "slash: dmabuf detach (noop)\n"); +} + +static struct sg_table *slash_bar_dmabuf_map(struct dma_buf_attachment *attach, + enum dma_data_direction dir) +{ + dev_dbg(attach->dev, "slash: dmabuf map requested -> not supported\n"); + return ERR_PTR(-EOPNOTSUPP); +} + +static void slash_bar_dmabuf_unmap(struct dma_buf_attachment *attach, + struct sg_table *sgl, enum dma_data_direction dir) +{ + dev_dbg(attach->dev, "slash: dmabuf unmap (noop)\n"); +} + +static int slash_bar_dmabuf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma) +{ + struct slash_bar_dmabuf_data *priv = dmabuf->priv; + unsigned long pfn; + int err; + unsigned long size = vma->vm_end - vma->vm_start; + u64 offset = (u64)vma->vm_pgoff << PAGE_SHIFT; + + + bool wc = !!(pci_resource_flags(priv->pdev, priv->bar_number) & IORESOURCE_PREFETCH); + + /* Ensure the requested range lies fully within the BAR */ + if (offset > priv->len || size > priv->len - offset) + return -EINVAL; + + vma->vm_flags |= VM_DONTDUMP | VM_DONTEXPAND; + + wc = !!(pci_resource_flags(priv->pdev, priv->bar_number) & IORESOURCE_PREFETCH); + vma->vm_page_prot = wc ? pgprot_writecombine(vma->vm_page_prot) + : pgprot_device(vma->vm_page_prot); + + /* Map within the BAR: add BAR start (in PFNs) to user-provided offset */ + pfn = (pci_resource_start(priv->pdev, priv->bar_number) >> PAGE_SHIFT) + vma->vm_pgoff; + + dev_dbg(&priv->pdev->dev, "slash: mmap BAR%d wc=%d start_pfn=0x%lx len=0x%lx\n", priv->bar_number, wc, pfn, vma->vm_end - vma->vm_start); + + err = io_remap_pfn_range(vma, vma->vm_start, pfn, + vma->vm_end - vma->vm_start, vma->vm_page_prot); + if (err) { + dev_err(&priv->pdev->dev, "slash: io_remap_pfn_range failed: %d\n", err); + return err; + } + + return 0; +} + +static void slash_bar_dmabuf_release(struct dma_buf *dmabuf) +{ + struct slash_bar_dmabuf_data *priv = dmabuf->priv; + + dev_dbg(&priv->pdev->dev, "slash: dmabuf release (BAR%d)\n", priv->bar_number); + + pci_dev_put(priv->pdev); + kfree(priv); +} + +static const struct dma_buf_ops slash_bar_dmabuf_ops = { + .attach = slash_bar_dmabuf_attach, + .detach = slash_bar_dmabuf_detach, + .map_dma_buf = slash_bar_dmabuf_map, + .unmap_dma_buf = slash_bar_dmabuf_unmap, + .mmap = slash_bar_dmabuf_mmap, + .release = slash_bar_dmabuf_release, +}; + +struct dma_buf *slash_bar_dmabuf_create(struct pci_dev *pdev, int bar_number) +{ + long err; + resource_size_t len; + DEFINE_DMA_BUF_EXPORT_INFO(exp_info); + struct dma_buf *dmabuf; + struct slash_bar_dmabuf_data *priv; + + if (bar_number < 0 || bar_number >= PCI_STD_NUM_BARS) { + dev_err(&pdev->dev, "slash: invalid BAR %d\n", bar_number); + return ERR_PTR(-EINVAL); + } + if (!pci_resource_start(pdev, bar_number)) { + dev_err(&pdev->dev, "slash: BAR%d not present\n", bar_number); + return ERR_PTR(-ENODEV); + } + if ((pci_resource_flags(pdev, bar_number) & IORESOURCE_MEM) == 0) { + dev_err(&pdev->dev, "slash: BAR%d is not MMIO\n", bar_number); + return ERR_PTR(-ENODEV); + } + + len = pci_resource_len(pdev, bar_number); + + dev_dbg(&pdev->dev, "slash: exporting BAR%d as dma-buf (size=%pa)\n", bar_number, &len); + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(&pdev->dev, "slash: kzalloc(priv) failed\n"); + return ERR_PTR(-ENOMEM); + } + + priv->bar_number = bar_number; + priv->len = len; + priv->pdev = pci_dev_get(pdev); + + exp_info.ops = &slash_bar_dmabuf_ops; + exp_info.size = len; + exp_info.flags = O_RDWR; + exp_info.priv = priv; + exp_info.exp_name = SLASH_NAME; + + dmabuf = dma_buf_export(&exp_info); + if (IS_ERR(dmabuf)) { + err = PTR_ERR(dmabuf); + dev_err(&pdev->dev, "slash: dma_buf_export failed: %ld\n", err); + goto err_free_priv; + } + + dev_info(&pdev->dev, "slash: BAR%d exported as dma-buf (size=%pa)\n", bar_number, &len); + return dmabuf; + +err_free_priv: + pci_dev_put(priv->pdev); + kfree(priv); + + return ERR_PTR(err); +} + +void slash_bar_dmabuf_destroy(struct dma_buf *dmabuf) +{ + pr_debug("slash: dmabuf_destroy()\n"); + dma_buf_put(dmabuf); +} diff --git a/driver/slash_dmabuf.h b/driver/slash_dmabuf.h new file mode 100644 index 00000000..00ff1a14 --- /dev/null +++ b/driver/slash_dmabuf.h @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef SLASH_DMABUF_H +#define SLASH_DMABUF_H + +#include +#include + +struct dma_buf *slash_bar_dmabuf_create(struct pci_dev *pdev, int bar_number); +void slash_bar_dmabuf_destroy(struct dma_buf *dmabuf); + +#endif /* SLASH_DMABUF_H */ diff --git a/driver/slash_hotplug.c b/driver/slash_hotplug.c new file mode 100644 index 00000000..c8f7f422 --- /dev/null +++ b/driver/slash_hotplug.c @@ -0,0 +1,389 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include "slash_hotplug_driver.h" + +#include "slash.h" + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SLASH_HOTPLUG_MODE 0600 + +struct slash_hotplug_entry { + struct list_head node; + char bdf[SLASH_HOTPLUG_BDF_LEN]; +}; + +static DEFINE_MUTEX(slash_hotplug_devices_lock); +static LIST_HEAD(slash_hotplug_devices); +static unsigned int slash_hotplug_device_count; + +static struct slash_hotplug_entry *slash_hotplug_find_entry_locked(const char *bdf) +{ + struct slash_hotplug_entry *entry; + + list_for_each_entry(entry, &slash_hotplug_devices, node) { + if (!strcmp(entry->bdf, bdf)) + return entry; + } + + return NULL; +} + +static int slash_hotplug_copy_request(unsigned long arg, struct slash_hotplug_device_request *req) +{ + if (copy_from_user(req, (void __user *)arg, sizeof(*req))) + return -EFAULT; + + if (req->size && req->size < sizeof(*req)) + return -EINVAL; + + if (!req->size) + req->size = sizeof(*req); + + req->bdf[SLASH_HOTPLUG_BDF_LEN - 1] = '\0'; + strim(req->bdf); + + return 0; +} + +static int slash_hotplug_resolve_request_locked(struct slash_hotplug_device_request *req, bool allow_default) +{ + struct slash_hotplug_entry *entry; + + if (!req->bdf[0]) { + if (!allow_default) + return -EINVAL; + + if (slash_hotplug_device_count == 0) + return -ENODEV; + + if (slash_hotplug_device_count > 1) + return -EOPNOTSUPP; + + entry = list_first_entry(&slash_hotplug_devices, struct slash_hotplug_entry, node); + strscpy(req->bdf, entry->bdf, sizeof(req->bdf)); + return 0; + } + + entry = slash_hotplug_find_entry_locked(req->bdf); + if (!entry) + return -ENODEV; + + return 0; +} + +static int slash_hotplug_get_pci_dev(const char *bdf, struct pci_dev **pdev_out) +{ + int domain, bus, slot, func; + struct pci_dev *pdev; + + if (sscanf(bdf, "%x:%x:%x.%x", &domain, &bus, &slot, &func) != 4) + return -EINVAL; + + pdev = pci_get_domain_bus_and_slot(domain, bus, PCI_DEVFN(slot, func)); + if (!pdev) + return -ENODEV; + + *pdev_out = pdev; + return 0; +} + +static int slash_hotplug_handle_rescan(void) +{ + struct pci_bus *bus; + + list_for_each_entry(bus, &pci_root_buses, node) + pci_rescan_bus(bus); + + return 0; +} + +static int slash_hotplug_handle_remove(const char *bdf) +{ + struct pci_dev *pdev; + int ret = slash_hotplug_get_pci_dev(bdf, &pdev); + + if (ret) { + pr_err("slash_hotplug: remove: BDF %s unavailable (%d)\n", bdf, ret); + return ret; + } + + pr_info("slash_hotplug: removing %s\n", pci_name(pdev)); + pci_stop_and_remove_bus_device(pdev); + pci_dev_put(pdev); + + return 0; +} + +static int slash_hotplug_handle_toggle_sbr(const char *bdf) +{ + struct pci_dev *pdev; + struct pci_dev *root; + int ret; + u16 ctrl; + + ret = slash_hotplug_get_pci_dev(bdf, &pdev); + if (ret) { + pr_err("slash_hotplug: toggle_sbr: BDF %s unavailable (%d)\n", bdf, ret); + return ret; + } + + root = pcie_find_root_port(pdev); + if (!root) { + pr_err("slash_hotplug: toggle_sbr: no root port for %s\n", pci_name(pdev)); + pci_dev_put(pdev); + return -ENODEV; + } + + pci_dev_get(root); + + ret = pci_read_config_word(root, PCI_BRIDGE_CONTROL, &ctrl); + if (ret) { + pr_err("slash_hotplug: toggle_sbr: read control failed (%d)\n", ret); + goto out_put; + } + + ret = pci_write_config_word(root, PCI_BRIDGE_CONTROL, ctrl | PCI_BRIDGE_CTL_BUS_RESET); + if (ret) { + pr_err("slash_hotplug: toggle_sbr: assert SBR failed (%d)\n", ret); + goto out_put; + } + + msleep(2); + + ret = pci_write_config_word(root, PCI_BRIDGE_CONTROL, ctrl & ~PCI_BRIDGE_CTL_BUS_RESET); + if (ret) + pr_err("slash_hotplug: toggle_sbr: deassert SBR failed (%d)\n", ret); + else + msleep(5000); + +out_put: + pci_dev_put(root); + pci_dev_put(pdev); + return ret; +} + +static int slash_hotplug_handle_hotplug(const char *bdf) +{ + struct pci_dev *pdev; + struct pci_dev *root; + struct pci_bus *bus; + int ret; + + ret = slash_hotplug_get_pci_dev(bdf, &pdev); + if (ret) { + pr_err("slash_hotplug: hotplug: BDF %s unavailable (%d)\n", bdf, ret); + return ret; + } + + root = pcie_find_root_port(pdev); + if (!root) { + pr_err("slash_hotplug: hotplug: no root port for %s\n", pci_name(pdev)); + pci_dev_put(pdev); + return -ENODEV; + } + + pci_dev_get(root); + bus = root->subordinate; + if (!bus) { + pr_err("slash_hotplug: hotplug: root port has no subordinate bus\n"); + ret = -ENODEV; + goto out_put_root; + } + + dev_info(&pdev->dev, "slash_hotplug: removing device for hotplug cycle\n"); + pci_stop_and_remove_bus_device(pdev); + pci_dev_put(pdev); + + pci_rescan_bus(bus); + ret = 0; + +out_put_root: + pci_dev_put(root); + return ret; +} + +static long slash_hotplug_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + struct slash_hotplug_device_request req = {0}; + int ret; + + switch (cmd) { + case SLASH_HOTPLUG_IOCTL_RESCAN: + ret = slash_hotplug_handle_rescan(); + break; + case SLASH_HOTPLUG_IOCTL_REMOVE: + ret = slash_hotplug_copy_request(arg, &req); + if (ret) + break; + mutex_lock(&slash_hotplug_devices_lock); + ret = slash_hotplug_resolve_request_locked(&req, true); + mutex_unlock(&slash_hotplug_devices_lock); + if (!ret) + ret = slash_hotplug_handle_remove(req.bdf); + break; + case SLASH_HOTPLUG_IOCTL_TOGGLE_SBR: + ret = slash_hotplug_copy_request(arg, &req); + if (ret) + break; + mutex_lock(&slash_hotplug_devices_lock); + ret = slash_hotplug_resolve_request_locked(&req, true); + mutex_unlock(&slash_hotplug_devices_lock); + if (!ret) + ret = slash_hotplug_handle_toggle_sbr(req.bdf); + break; + case SLASH_HOTPLUG_IOCTL_HOTPLUG: + ret = slash_hotplug_copy_request(arg, &req); + if (ret) + break; + mutex_lock(&slash_hotplug_devices_lock); + ret = slash_hotplug_resolve_request_locked(&req, true); + mutex_unlock(&slash_hotplug_devices_lock); + if (!ret) + ret = slash_hotplug_handle_hotplug(req.bdf); + break; + default: + ret = -ENOTTY; + break; + } + + if (ret == -EOPNOTSUPP) + pr_err("slash_hotplug: multiple devices tracked; specify BDF explicitly\n"); + + return ret; +} + +#ifdef CONFIG_COMPAT +static long slash_hotplug_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + return slash_hotplug_ioctl(file, cmd, (unsigned long)compat_ptr(arg)); +} +#endif + +static const struct file_operations slash_hotplug_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = slash_hotplug_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = slash_hotplug_compat_ioctl, +#endif +}; + +static struct miscdevice slash_hotplug_misc = { + .minor = MISC_DYNAMIC_MINOR, + .name = SLASH_HOTPLUG_DEVICE_NAME, + .fops = &slash_hotplug_fops, + .mode = SLASH_HOTPLUG_MODE, +}; + +int slash_hotplug_register_device(struct pci_dev *pdev) +{ + struct slash_hotplug_entry *entry; + char bdf[SLASH_HOTPLUG_BDF_LEN]; + + snprintf(bdf, sizeof(bdf), "%04x:%02x:%02x.%x", + pci_domain_nr(pdev->bus), pdev->bus->number, + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); + + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + strscpy(entry->bdf, bdf, sizeof(entry->bdf)); + + mutex_lock(&slash_hotplug_devices_lock); + if (slash_hotplug_find_entry_locked(entry->bdf)) { + mutex_unlock(&slash_hotplug_devices_lock); + kfree(entry); + return 0; + } + + list_add_tail(&entry->node, &slash_hotplug_devices); + slash_hotplug_device_count++; + mutex_unlock(&slash_hotplug_devices_lock); + + dev_info(&pdev->dev, "slash_hotplug: tracking device %s\n", entry->bdf); + + return 0; +} + +void slash_hotplug_unregister_device(struct pci_dev *pdev) +{ + struct slash_hotplug_entry *entry; + char bdf[SLASH_HOTPLUG_BDF_LEN]; + + snprintf(bdf, sizeof(bdf), "%04x:%02x:%02x.%x", + pci_domain_nr(pdev->bus), pdev->bus->number, + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); + + mutex_lock(&slash_hotplug_devices_lock); + entry = slash_hotplug_find_entry_locked(bdf); + if (entry) { + list_del(&entry->node); + if (slash_hotplug_device_count) + slash_hotplug_device_count--; + } + mutex_unlock(&slash_hotplug_devices_lock); + + if (entry) { + dev_info(&pdev->dev, "slash_hotplug: untracked device %s\n", bdf); + kfree(entry); + } else { + dev_dbg(&pdev->dev, "slash_hotplug: device %s not tracked\n", bdf); + } +} + +int slash_hotplug_init(void) +{ + int ret; + + pr_info("slash_hotplug: registering misc device\n"); + + ret = misc_register(&slash_hotplug_misc); + if (ret) { + pr_err("slash_hotplug: misc_register failed: %d\n", ret); + return ret; + } + + return 0; +} + +void slash_hotplug_exit(void) +{ + struct slash_hotplug_entry *entry, *tmp; + + mutex_lock(&slash_hotplug_devices_lock); + list_for_each_entry_safe(entry, tmp, &slash_hotplug_devices, node) { + list_del(&entry->node); + kfree(entry); + } + slash_hotplug_device_count = 0; + mutex_unlock(&slash_hotplug_devices_lock); + + misc_deregister(&slash_hotplug_misc); + pr_info("slash_hotplug: misc device unregistered\n"); +} diff --git a/driver/slash_hotplug_driver.h b/driver/slash_hotplug_driver.h new file mode 100644 index 00000000..dd112439 --- /dev/null +++ b/driver/slash_hotplug_driver.h @@ -0,0 +1,25 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef SLASH_HOTPLUG_DRIVER_H +#define SLASH_HOTPLUG_DRIVER_H + +#include + +int slash_hotplug_init(void); +void slash_hotplug_exit(void); +int slash_hotplug_register_device(struct pci_dev *pdev); +void slash_hotplug_unregister_device(struct pci_dev *pdev); + +#endif /* SLASH_HOTPLUG_DRIVER_H */ diff --git a/driver/slash_main.c b/driver/slash_main.c new file mode 100644 index 00000000..016250c8 --- /dev/null +++ b/driver/slash_main.c @@ -0,0 +1,76 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include "slash.h" + +#include +#include +#include +#include + +#include "slash_pcie.h" +#include "slash_hotplug_driver.h" +#include "slash_qdma.h" + +static unsigned int qdma_num_threads = 8; +static char *qdma_debugfs_path = NULL; + +static int __init slash_init(void) +{ + int err; + + pr_info("slash: module init\n"); + + err = slash_qdma_init(qdma_num_threads, NULL); + if (err) { + pr_err("slash: libqdma init failed: %d\n", err); + return err; + } + + err = slash_hotplug_init(); + if (err) { + pr_err("slash: hotplug init failed: %d\n", err); + return err; + } + + err = slash_pcie_init(); + if (err) { + pr_err("slash: PCIe init failed: %d\n", err); + slash_hotplug_exit(); + return err; + } + + pr_info("slash: module init complete\n"); + return 0; +} + +static void __exit slash_exit(void) +{ + pr_info("slash: module exit\n"); + slash_pcie_exit(); + slash_hotplug_exit(); + slash_qdma_exit(); + pr_info("slash: module exit complete\n"); +} + +module_init(slash_init); +module_exit(slash_exit); + +module_param(qdma_num_threads, uint, 0644); +module_param(qdma_debugfs_path, charp, 0644); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("AMD Inc."); +MODULE_DESCRIPTION("SLASH/VRT module"); +MODULE_VERSION("1.0"); diff --git a/driver/slash_pcie.c b/driver/slash_pcie.c new file mode 100644 index 00000000..6c31c460 --- /dev/null +++ b/driver/slash_pcie.c @@ -0,0 +1,123 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include "slash_pcie.h" + +#include +#include + +#include "slash.h" +#include "slash_ctldev.h" +#include "slash_hotplug_driver.h" + +static int slash_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id); +static void slash_pcie_remove(struct pci_dev *pdev); + +static const struct pci_device_id slash_pcie_ids[] = { + {PCI_DEVICE(SLASH_PCIE_VENDOR_ID, SLASH_PCIE_DEVICE_ID)}, + {0,} +}; +MODULE_DEVICE_TABLE(pci, slash_pcie_ids); + +static struct pci_driver slash_pcie_driver = { + .name = SLASH_NAME, + .id_table = slash_pcie_ids, + .probe = slash_pcie_probe, + .remove = slash_pcie_remove, +}; + +static int slash_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + int err; + + (void) id; /* Unused */ + + dev_info(&pdev->dev, "slash: probe start for %s\n", pci_name(pdev)); + dev_dbg(&pdev->dev, "slash: vendor=0x%04x device=0x%04x fn=%u\n", pdev->vendor, pdev->device, PCI_FUNC(pdev->devfn)); + + if (PCI_FUNC(pdev->devfn) != SLASH_PCIE_PF) { + dev_err(&pdev->dev, "slash: expected PF %u, got %u\n", SLASH_PCIE_PF, PCI_FUNC(pdev->devfn)); + return -EINVAL; + } + + pci_dev_get(pdev); + + err = pci_enable_device(pdev); + if (err) { + dev_err(&pdev->dev, "slash: pci_enable_device() failed: %d\n", err); + goto err_put_device; + } + + pci_set_master(pdev); + dev_dbg(&pdev->dev, "slash: bus mastering enabled\n"); + + err = slash_ctldev_create(pdev); + if (err) { + dev_err(&pdev->dev, "slash: control device create failed: %d\n", err); + goto err_disable_device; + } + + err = slash_hotplug_register_device(pdev); + if (err) { + dev_warn(&pdev->dev, "slash: hotplug registration failed: %d\n", err); + } + + dev_info(&pdev->dev, "slash: probe successful\n"); + return 0; + +err_disable_device: + pci_clear_master(pdev); + pci_disable_device(pdev); + +err_put_device: + pci_dev_put(pdev); + + return err; +} + +static void slash_pcie_remove(struct pci_dev *pdev) +{ + dev_info(&pdev->dev, "slash: remove start for %s\n", pci_name(pdev)); + + slash_hotplug_unregister_device(pdev); + slash_ctldev_destroy(pdev); + pci_clear_master(pdev); + pci_disable_device(pdev); + pci_dev_put(pdev); + + dev_info(&pdev->dev, "slash: remove complete\n"); +} + +int __init slash_pcie_init(void) +{ + int err; + + pr_info("slash: registering PCIe driver '%s'\n", SLASH_NAME); + err = pci_register_driver(&slash_pcie_driver); + + if (err) { + pr_err("slash: pci_register_driver failed: %d\n", err); + return err; + } + + pr_info("slash: driver '%s' registered\n", SLASH_NAME); + return 0; +} + +void __exit slash_pcie_exit(void) +{ + pr_info("slash: unregistering PCIe driver '%s'\n", SLASH_NAME); + pci_unregister_driver(&slash_pcie_driver); + pr_info("slash: driver '%s' unregistered\n", SLASH_NAME); +} diff --git a/driver/slash_pcie.h b/driver/slash_pcie.h new file mode 100644 index 00000000..bd3dbcf2 --- /dev/null +++ b/driver/slash_pcie.h @@ -0,0 +1,23 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef SLASH_PCIE_H +#define SLASH_PCIE_H + +#include + +int __init slash_pcie_init(void); +void __exit slash_pcie_exit(void); + +#endif /* SLASH_PCIE_H */ diff --git a/driver/slash_qdma.c b/driver/slash_qdma.c new file mode 100644 index 00000000..a21d1559 --- /dev/null +++ b/driver/slash_qdma.c @@ -0,0 +1,1290 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include "slash_qdma.h" + +#include "libqdma_export.h" + +#include "slash.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SLASH_QDMA_PF 0 + +#define SLASH_QDMA_DIR_H2C BIT(0) +#define SLASH_QDMA_DIR_C2H BIT(1) +#define SLASH_QDMA_DIR_CMPT BIT(2) +#define SLASH_QDMA_DIR_MASK (SLASH_QDMA_DIR_H2C | SLASH_QDMA_DIR_C2H | \ + SLASH_QDMA_DIR_CMPT) + +#define SLASH_QDMA_QTYPE_COUNT (Q_CMPT + 1) + +#define SLASH_QDMA_MAX_QPAIRS 256 +#define SLASH_QDMA_QPAIR_ID_RANGE XA_LIMIT(0, SLASH_QDMA_MAX_QPAIRS - 1) + +struct slash_qdma_dev; + +struct slash_qdma_qpair_entry { + struct kref ref; + unsigned long qhndl[SLASH_QDMA_QTYPE_COUNT]; + u32 dir_mask; + enum qdma_q_mode mode; + u32 irq_mode; + u32 irq_vector; +}; + +struct slash_qdma_dev { + struct pci_dev *pdev; + unsigned long qdma_handle; + + struct miscdevice misc; + struct kref ref; + struct mutex lock; + struct xarray qpairs; + + /* + * Initialization booleans. + * Assume these are always true outside of create/destroy. + */ + bool have_qdma_handle; + bool is_misc_registered; + bool hw_shutdown; +}; + +typedef int (*slash_qdma_queue_cmd_fn)(unsigned long qdma_handle, + unsigned long qhndl, + char *errbuf, + int errbuf_sz); + +__attribute__((unused)) +static enum queue_type_t slash_qdma_dir_to_qtype(u32 dir_bit) +{ + switch (dir_bit) { + case SLASH_QDMA_DIR_H2C: + return Q_H2C; + case SLASH_QDMA_DIR_C2H: + return Q_C2H; + case SLASH_QDMA_DIR_CMPT: + return Q_CMPT; + default: + return Q_H2C; /* should never reach */ + } +} + +static u32 slash_qdma_qtype_to_dir(enum queue_type_t qtype) +{ + switch (qtype) { + case Q_H2C: + return SLASH_QDMA_DIR_H2C; + case Q_C2H: + return SLASH_QDMA_DIR_C2H; + case Q_CMPT: + return SLASH_QDMA_DIR_CMPT; + default: + return 0; + } +} + +static inline struct slash_qdma_qpair_entry * +slash_qdma_qpair_lookup(struct slash_qdma_dev *qdma_dev, u32 qid) +{ + return xa_load(&qdma_dev->qpairs, qid); +} + +static void slash_qdma_qpair_entry_release(struct kref *ref) +{ + struct slash_qdma_qpair_entry *entry = + container_of(ref, struct slash_qdma_qpair_entry, ref); + + kfree(entry); +} + +static inline void slash_qdma_qpair_get(struct slash_qdma_qpair_entry *entry) +{ + kref_get(&entry->ref); +} + +static inline void slash_qdma_qpair_put(struct slash_qdma_qpair_entry *entry) +{ + kref_put(&entry->ref, slash_qdma_qpair_entry_release); +} + +static inline int +slash_qdma_qpair_insert(struct slash_qdma_dev *qdma_dev, struct slash_qdma_qpair_entry *entry, u32 *id) +{ + kref_init(&entry->ref); + return xa_alloc(&qdma_dev->qpairs, id, entry, SLASH_QDMA_QPAIR_ID_RANGE, GFP_KERNEL); +} + +static inline void +slash_qdma_qpair_remove(struct slash_qdma_dev *qdma_dev, u32 qid) +{ + struct slash_qdma_qpair_entry *entry; + + entry = xa_erase(&qdma_dev->qpairs, qid); + if (entry) + slash_qdma_qpair_put(entry); +} + +struct slash_qdma_qpair_file_ctx { + struct slash_qdma_dev *qdma_dev; + struct slash_qdma_qpair_entry *entry; + u32 qid; +}; + +struct slash_qdma_io_cb { + void __user *buf; + size_t len; + unsigned int pages_nr; + struct qdma_sw_sg *sgl; + struct page **pages; + struct qdma_request req; +}; + +static int slash_qdma_probe(struct pci_dev *pdev, const struct pci_device_id *id); +static void slash_qdma_remove(struct pci_dev *pdev); +static int slash_qdma_create_qdma_device(struct pci_dev *pdev, struct slash_qdma_dev **pdevice); +static void slash_qdma_destroy_qdma_device(struct slash_qdma_dev *device); +static void slash_qdma_dev_release(struct kref *ref); +static void slash_qdma_conf_options(struct qdma_dev_conf *conf, struct pci_dev *pdev); +static int slash_qdma_ioctl_info_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg); +static int slash_qdma_ioctl_qpair_add_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg); +static int slash_qdma_ioctl_qpair_add(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_add *req); +static int slash_qdma_ioctl_qpair_add_q(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_add *req, + struct slash_qdma_qpair_entry *entry, + enum queue_type_t qtype); +static void slash_qdma_ioctl_qpair_rm_q(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_entry *entry, + enum queue_type_t qtype); +static int slash_qdma_ioctl_qpair_op_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg); +static int slash_qdma_ioctl_qpair_op(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_op *req); +static int slash_qdma_ioctl_qpair_op_apply(struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_entry *entry, + struct slash_qdma_qpair_op *req, + slash_qdma_queue_cmd_fn fn, + const char *op_name, + bool stop_on_err); +static int slash_qdma_ioctl_qpair_get_fd_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg); + +static ssize_t slash_qdma_qpair_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos); +static ssize_t slash_qdma_qpair_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos); +static int slash_qdma_qpair_release(struct inode *inode, struct file *file); +static long slash_qdma_qpair_ioctl(struct file *file, + unsigned int cmd, unsigned long arg); + +static const struct file_operations slash_qdma_qpair_fops = { + .owner = THIS_MODULE, + .read = slash_qdma_qpair_read, + .write = slash_qdma_qpair_write, + .unlocked_ioctl = slash_qdma_qpair_ioctl, + .release = slash_qdma_qpair_release, + .llseek = default_llseek, +}; + + +static int slash_qdma_fop_open(struct inode *inode, struct file *file); +static int slash_qdma_fop_release(struct inode *inode, struct file *file); +static long slash_qdma_fop_ioctl(struct file *file, unsigned int op, unsigned long arg); +static void slash_qdma_ioctl_info(struct miscdevice *misc, struct slash_qdma_dev *qdma_dev, struct slash_qdma_info *qdma_info); + +#define SLASH_QDMA_PCI_VENDOR_ID 0x00 //TOOD: Change +#define SLASH_QDMA_PCI_DEVICE_ID 0x00 + +static const struct pci_device_id slash_qdma_ids[] = { + {PCI_DEVICE(SLASH_QDMA_PCI_VENDOR_ID, SLASH_QDMA_PCI_DEVICE_ID)}, + {0,} +}; +MODULE_DEVICE_TABLE(pci, slash_qdma_ids); + +static struct pci_driver slash_qdma_driver = { + .name = SLASH_NAME "_qdma", + .id_table = slash_qdma_ids, + .probe = slash_qdma_probe, + .remove = slash_qdma_remove, +}; + +static struct file_operations slash_qdma_fops = { + .owner = THIS_MODULE, + .open = slash_qdma_fop_open, + .release = slash_qdma_fop_release, + .unlocked_ioctl = slash_qdma_fop_ioctl, +}; + +int __init slash_qdma_init(unsigned int num_threads, char *debugfs) +{ + int err; + + pr_debug("slash: initializing qdma\n"); + + err = libqdma_init(num_threads, debugfs); + if (err) { + pr_err("slash: libqdma_init failed: %d\n", err); + return err; + } + + err = pci_register_driver(&slash_qdma_driver); + if (err) { + pr_err("slash: register qdma driver failed: %d\n", err); + goto err_exit_libqdma; + } + + return 0; + +err_exit_libqdma: + libqdma_exit(); + + return err; +} + +void __exit slash_qdma_exit(void) +{ + pr_debug("slash: deinitializing qdma\n"); + + pci_unregister_driver(&slash_qdma_driver); + + libqdma_exit(); +} + +/* --- PCI Operations --- */ + +static int slash_qdma_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + int err; + struct qdma_dev_conf conf; + struct slash_qdma_dev *device = NULL; + + memset(&conf, 0, sizeof(conf)); + + dev_info(&pdev->dev, "slash: qdma: probe start for %s\n", pci_name(pdev)); + dev_dbg(&pdev->dev, "slash: qdma: vendor=0x%04x device=0x%04x fn=%u\n", pdev->vendor, pdev->device, PCI_FUNC(pdev->devfn)); + + if (PCI_FUNC(pdev->devfn) != SLASH_QDMA_PF) { + dev_err(&pdev->dev, "slash: expected PF %u, got %u\n", SLASH_QDMA_PF, PCI_FUNC(pdev->devfn)); + return -EINVAL; + } + + err = slash_qdma_create_qdma_device(pdev, &device); + if (err) { + goto err_free; + } + + slash_qdma_conf_options(&conf, pdev); + err = qdma_device_open(SLASH_NAME, &conf, &device->qdma_handle); + if (err) { + dev_err(&pdev->dev, "slash: qdma: could not open qdma device %d", err); + goto err_free; + } + device->have_qdma_handle = true; + + err = misc_register(&device->misc); + if (err) { + dev_err(&pdev->dev, "slash: qdma: could not register misc device: %d", err); + goto err_free; + } + device->is_misc_registered = true; + + return 0; + +err_free: + if (device) { + slash_qdma_destroy_qdma_device(device); + kref_put(&device->ref, slash_qdma_dev_release); + } + + return err; +} + +static void slash_qdma_remove(struct pci_dev *pdev) +{ + struct slash_qdma_dev *device = pci_get_drvdata(pdev); + + if (!device) + return; + + slash_qdma_destroy_qdma_device(device); + kref_put(&device->ref, slash_qdma_dev_release); +} + +static int slash_qdma_create_qdma_device(struct pci_dev *pdev, struct slash_qdma_dev **pdevice) +{ + int err; + struct slash_qdma_dev *device; + static atomic_t devcount = ATOMIC_INIT(0); + int id; + + device = kzalloc(sizeof(*device), GFP_KERNEL); + if (!device) { + return -ENOMEM; + } + device->pdev = pdev; + kref_init(&device->ref); + mutex_init(&device->lock); + xa_init(&device->qpairs); + device->hw_shutdown = false; + pci_set_drvdata(pdev, device); + + { /* Miscdevice */ + device->misc.minor = MISC_DYNAMIC_MINOR; + device->misc.fops = &slash_qdma_fops; + device->misc.parent = &pdev->dev; + device->misc.mode = SLASH_CTLDEV_QDMA_MODE; + + device->misc.name = kasprintf(GFP_KERNEL, SLASH_QDMA_CTLDEV_NAME_FMT, pci_name(device->pdev)); + if (!device->misc.name) { + dev_err(&device->pdev->dev, "qdma: kasprintf(name) failed\n"); + err = -ENOMEM; + goto err_free; + } + + id = atomic_inc_return(&devcount) - 1; + device->misc.nodename = kasprintf(GFP_KERNEL, SLASH_QDMA_CTLDEV_NODENAME_FMT, id); + if (!device->misc.nodename) { + dev_err(&device->pdev->dev, "qdma: kasprintf(nodename) failed\n"); + + err = -ENOMEM; + goto err_free; + } + } + + *pdevice = device; + return 0; + +err_free: + slash_qdma_destroy_qdma_device(device); + *pdevice = NULL; + + return err; +} + +static void slash_qdma_destroy_qdma_device(struct slash_qdma_dev *device) +{ + int err; + + if (!device) { + return; + } + + mutex_lock(&device->lock); + if (device->hw_shutdown) { + mutex_unlock(&device->lock); + return; + } + device->hw_shutdown = true; + mutex_unlock(&device->lock); + + pci_set_drvdata(device->pdev, NULL); + + if (device->is_misc_registered) { + misc_deregister(&device->misc); + device->is_misc_registered = false; + } + + mutex_lock(&device->lock); + + { + struct slash_qdma_qpair_entry *entry; + unsigned long index; + unsigned int idx; + + xa_for_each(&device->qpairs, index, entry) { + for (idx = 0; idx < SLASH_QDMA_QTYPE_COUNT; idx++) { + enum queue_type_t qtype = idx; + u32 dir_bit = slash_qdma_qtype_to_dir(qtype); + + if (!(entry->dir_mask & dir_bit)) + continue; + + slash_qdma_ioctl_qpair_rm_q(&device->misc, device, entry, qtype); + } + xa_erase(&device->qpairs, index); + slash_qdma_qpair_put(entry); + } + xa_destroy(&device->qpairs); + } + + if (device->have_qdma_handle) { + err = qdma_device_close(device->pdev, device->qdma_handle); + if (err) { + dev_err(&device->pdev->dev, "Error in qdma_device_close: %d\n", err); + } + device->have_qdma_handle = false; + } + + mutex_unlock(&device->lock); +} + +static void slash_qdma_dev_release(struct kref *ref) +{ + struct slash_qdma_dev *device = + container_of(ref, struct slash_qdma_dev, ref); + + mutex_destroy(&device->lock); + + if (device->misc.name) { + kfree(device->misc.name); + } + + if (device->misc.nodename) { + kfree(device->misc.nodename); + } + + kfree(device); +} + +static void slash_qdma_conf_options(struct qdma_dev_conf *conf, struct pci_dev *pdev) +{ + conf->pdev = pdev; + conf->qsets_max = 256; /* Maximum number of queue paris. Might be lowered. TODO: tune */ + conf->zerolen_dma = 0; /* Disallow 0-length transfers */ + conf->master_pf = 1; /* This is the master PF */ + conf->intr_moderation = 1; + conf->vf_max = 8; + conf->intr_rngsz = 128; // TODO: tune + + // Ask for as many queue MSI-X vectors as you’d like to dedicate to queues + conf->msix_qvec_max = 256; + conf->user_msix_qvec_max = 0; + conf->data_msix_qvec_max = 0; + + conf->qdma_drv_mode = POLL_MODE; // TODO: experiment with this + conf->uld = 0; + + conf->bar_num_config = 0; + conf->bar_num_user = -1; + conf->bar_num_bypass = -1; + conf->qsets_base = 0; + + // Optional callbacks + conf->fp_user_isr_handler = NULL; + conf->fp_q_isr_top_dev = NULL; + conf->fp_flr_free_resource= NULL; + conf->debugfs_dev_root = NULL; +} + +/* --- Miscdevice operations --- */ +static long slash_qdma_fop_ioctl(struct file *file, unsigned int op, unsigned long arg) +{ + struct slash_qdma_dev *qdma_dev = file->private_data; + struct miscdevice *misc = &qdma_dev->misc; + void __user *uarg = (void __user *)arg; + long ret = 0; + + if (!qdma_dev) + return -ENODEV; + + dev_dbg(&qdma_dev->pdev->dev, "qdma: ioctl op=0x%x\n", op); + + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + mutex_unlock(&qdma_dev->lock); + + switch (op) { + case SLASH_QDMA_IOCTL_INFO: + ret = slash_qdma_ioctl_info_w(misc, qdma_dev, uarg); + break; + + case SLASH_QDMA_IOCTL_QPAIR_ADD: + ret = slash_qdma_ioctl_qpair_add_w(misc, qdma_dev, uarg); + break; + + case SLASH_QDMA_IOCTL_Q_OP: + ret = slash_qdma_ioctl_qpair_op_w(misc, qdma_dev, uarg); + break; + + case SLASH_QDMA_IOCTL_QPAIR_GET_FD: + ret = slash_qdma_ioctl_qpair_get_fd_w(misc, qdma_dev, uarg); + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +static int slash_qdma_fop_open(struct inode *inode, struct file *file) +{ + struct miscdevice *misc = file->private_data; + struct slash_qdma_dev *qdma_dev = + container_of(misc, struct slash_qdma_dev, misc); + int ret = 0; + + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + ret = -ENODEV; + } else { + kref_get(&qdma_dev->ref); + file->private_data = qdma_dev; + } + mutex_unlock(&qdma_dev->lock); + + return ret; +} + +static int slash_qdma_fop_release(struct inode *inode, struct file *file) +{ + struct slash_qdma_dev *qdma_dev = file->private_data; + + if (qdma_dev) + kref_put(&qdma_dev->ref, slash_qdma_dev_release); + + return 0; +} + +static int slash_qdma_ioctl_info_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg) +{ + struct slash_qdma_info info; + u32 user_size = 0; + size_t copy_size; + + if (copy_from_user(&user_size, uarg, sizeof(user_size))) + return -EFAULT; + + if (!user_size || user_size > sizeof(info)) + user_size = sizeof(info); + + + memset(&info, 0, sizeof(info)); + info.size = sizeof(info); + + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + slash_qdma_ioctl_info(misc, qdma_dev, &info); + mutex_unlock(&qdma_dev->lock); + + copy_size = min_t(size_t, user_size, sizeof(info)); + if (copy_to_user(uarg, &info, copy_size)) + return -EFAULT; + + return 0; +} + +static void slash_qdma_ioctl_info(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_info *qdma_info) +{ + (void) misc; + (void) qdma_dev; + + qdma_info->qsets_max = 0; + qdma_info->msix_qvecs = 0; + qdma_info->vf_max = 0; + qdma_info->caps = 0; +} + +static int slash_qdma_ioctl_qpair_add_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg) +{ + struct slash_qdma_qpair_add req; + __u32 user_size = 0; + size_t copy_size; + u32 dir_mask; + int err; + + /* + * First, fetch the size field from userspace so we can + * safely handle callers built against older or newer + * versions of the struct. + */ + if (copy_from_user(&user_size, uarg, sizeof(user_size))) + return -EFAULT; + + if (!user_size || user_size > sizeof(req)) + user_size = sizeof(req); + + memset(&req, 0, sizeof(req)); + + if (copy_from_user(&req, uarg, user_size)) + return -EFAULT; + + dir_mask = req.dir_mask & SLASH_QDMA_DIR_MASK; + if (!dir_mask || dir_mask != req.dir_mask) + return -EINVAL; + + if (req.mode != QDMA_Q_MODE_MM && req.mode != QDMA_Q_MODE_ST) + return -EINVAL; + + if (req.h2c_ring_sz >= 16 || req.c2h_ring_sz >= 16 || req.cmpt_ring_sz >= 16) + return -EINVAL; + + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + err = slash_qdma_ioctl_qpair_add(misc, qdma_dev, &req); + mutex_unlock(&qdma_dev->lock); + + if (err) + return err; + + /* + * On success, update the size field to reflect the + * kernel's view of the struct and copy back only as + * many bytes as the caller originally provided. + */ + req.size = sizeof(req); + copy_size = min_t(size_t, user_size, sizeof(req)); + if (copy_to_user(uarg, &req, copy_size)) + return -EFAULT; + + return err; +} + +static int slash_qdma_ioctl_qpair_add(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_add *req) +{ + struct slash_qdma_qpair_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL); + unsigned int idx; + bool added[SLASH_QDMA_QTYPE_COUNT] = {0}; + int ret = 0; + + if (!entry) + return -ENOMEM; + + entry->mode = req->mode; + entry->irq_mode = 0; + entry->irq_vector = 0; + + /* + * Allocate a new qpair ID in the xarray and use it as the + * QDMA queue index for all queues in this pair. Any qid + * value provided by userspace is ignored. + */ + ret = slash_qdma_qpair_insert(qdma_dev, entry, &req->qid); + if (ret) { + dev_err(&qdma_dev->pdev->dev, + "qdma: qpair insert failed: %d\n", ret); + kfree(entry); + return ret; + } + + for (idx = 0; idx < SLASH_QDMA_QTYPE_COUNT; idx++) { + enum queue_type_t qtype = idx; + u32 dir_bit = slash_qdma_qtype_to_dir(qtype); + + if (!(req->dir_mask & dir_bit)) + continue; + + ret = slash_qdma_ioctl_qpair_add_q(misc, qdma_dev, req, entry, qtype); + if (ret) + goto rollback; + + added[idx] = true; + } + + return 0; + +rollback: + for (idx = 0; idx < SLASH_QDMA_QTYPE_COUNT; idx++) { + if (added[idx]) + slash_qdma_ioctl_qpair_rm_q(misc, qdma_dev, entry, idx); + } + + slash_qdma_qpair_remove(qdma_dev, req->qid); + + return ret; +} + +static int slash_qdma_ioctl_qpair_add_q(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_add *req, + struct slash_qdma_qpair_entry *entry, + enum queue_type_t qtype) +{ + u32 dir_bit = slash_qdma_qtype_to_dir(qtype); + struct qdma_queue_conf qconf = {0}; + char errbuf[128] = {0}; + u32 dir_mask = req->dir_mask; + int err; + unsigned long qhndl = 0; + + if (!(dir_mask & dir_bit)) + return -EINVAL; + + qconf.qidx = req->qid; + qconf.q_type = qtype; + qconf.st = (req->mode == QDMA_Q_MODE_ST); + qconf.irq_en = 0; + qconf.cmpl_en_intr = 0; + qconf.cmpl_trig_mode = TRIG_MODE_DISABLE; + + switch (qtype) { + case Q_H2C: + qconf.desc_rng_sz_idx = req->h2c_ring_sz; + break; + case Q_C2H: + qconf.desc_rng_sz_idx = req->c2h_ring_sz; + qconf.cmpl_rng_sz_idx = req->cmpt_ring_sz; + qconf.cmpl_desc_sz = CMPT_DESC_SZ_16B; + break; + case Q_CMPT: + qconf.st = 0; + qconf.desc_rng_sz_idx = req->cmpt_ring_sz; + qconf.cmpl_rng_sz_idx = req->cmpt_ring_sz; + qconf.cmpl_desc_sz = CMPT_DESC_SZ_16B; + qconf.cmpl_en_intr = 0; + break; + default: + break; + } + + err = qdma_queue_add(qdma_dev->qdma_handle, &qconf, &qhndl, + errbuf, sizeof(errbuf)); + if (err) { + dev_err(&qdma_dev->pdev->dev, + "qdma: queue add failed (qid=%u, type=%u): %d (%s)\n", + req->qid, qtype, err, errbuf); + return err; + } + + entry->qhndl[qtype] = qhndl; + entry->dir_mask |= dir_bit; + + return 0; +} + +static void slash_qdma_ioctl_qpair_rm_q(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_entry *entry, + enum queue_type_t qtype) +{ + unsigned long qhndl = entry->qhndl[qtype]; + char errbuf[128] = {0}; + int err; + + err = qdma_queue_remove(qdma_dev->qdma_handle, qhndl, + errbuf, sizeof(errbuf)); + + if (err) { + dev_err(&qdma_dev->pdev->dev, + "qdma: queue remove failed (type=%u): %d (%s)\n", + qtype, err, errbuf); + } + + entry->qhndl[qtype] = 0; + entry->dir_mask &= ~slash_qdma_qtype_to_dir(qtype); +} + +static int slash_qdma_ioctl_qpair_op_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg) +{ + struct slash_qdma_qpair_op req; + __u32 user_size = 0; + size_t copy_size; + int ret; + + /* + * First, fetch the size field from userspace so we can + * safely handle callers built against older or newer + * versions of the struct. + */ + if (copy_from_user(&user_size, uarg, sizeof(user_size))) + return -EFAULT; + + if (!user_size || user_size > sizeof(req)) + user_size = sizeof(req); + + memset(&req, 0, sizeof(req)); + + if (copy_from_user(&req, uarg, user_size)) + return -EFAULT; + + if (req.op > SLASH_QDMA_QUEUE_OP_DEL) + return -EINVAL; + + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + ret = slash_qdma_ioctl_qpair_op(misc, qdma_dev, &req); + mutex_unlock(&qdma_dev->lock); + + if (ret) + return ret; + + /* + * On success, update the size field to reflect the + * kernel's view of the struct and copy back only as + * many bytes as the caller originally provided. + */ + req.size = sizeof(req); + copy_size = min_t(size_t, user_size, sizeof(req)); + if (copy_to_user(uarg, &req, copy_size)) + return -EFAULT; + + return ret; +} + +static int slash_qdma_ioctl_qpair_op(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_op *req) +{ + struct slash_qdma_qpair_entry *entry; + int ret = 0; + + (void) misc; + + if (!qdma_dev->have_qdma_handle) + return -ENODEV; + + entry = slash_qdma_qpair_lookup(qdma_dev, req->qid); + if (!entry) + return -ENOENT; + + switch (req->op) { + case SLASH_QDMA_QUEUE_OP_START: + ret = slash_qdma_ioctl_qpair_op_apply(qdma_dev, entry, req, + qdma_queue_start, + "start", true); + break; + case SLASH_QDMA_QUEUE_OP_STOP: + ret = slash_qdma_ioctl_qpair_op_apply(qdma_dev, entry, req, + qdma_queue_stop, + "stop", true); + break; + case SLASH_QDMA_QUEUE_OP_DEL: + ret = slash_qdma_ioctl_qpair_op_apply(qdma_dev, entry, req, + qdma_queue_remove, + "remove", false); + if (!ret) + slash_qdma_qpair_remove(qdma_dev, req->qid); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int slash_qdma_ioctl_qpair_op_apply(struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_entry *entry, + struct slash_qdma_qpair_op *req, + slash_qdma_queue_cmd_fn fn, + const char *op_name, + bool stop_on_err) +{ + int idx; + int first_err = 0; + + for (idx = 0; idx < SLASH_QDMA_QTYPE_COUNT; idx++) { + enum queue_type_t qtype = idx; + u32 dir_bit = slash_qdma_qtype_to_dir(qtype); + char errbuf[128] = {0}; + int err; + + if (!(entry->dir_mask & dir_bit) || !entry->qhndl[qtype]) + continue; + + err = fn(qdma_dev->qdma_handle, entry->qhndl[qtype], + errbuf, (int)sizeof(errbuf)); + if (err) { + dev_err(&qdma_dev->pdev->dev, + "qdma: queue %s failed (qid=%u, type=%u): %d (%s)\n", + op_name, req->qid, qtype, err, errbuf); + + if (stop_on_err) + return err; + + if (!first_err) + first_err = err; + } + } + + return first_err; +} + +static inline void slash_qdma_iocb_release(struct slash_qdma_io_cb *iocb) +{ + if (iocb->pages) + iocb->pages = NULL; + + kfree(iocb->sgl); + iocb->sgl = NULL; + iocb->buf = NULL; +} + +static void slash_qdma_unmap_user_buf(struct slash_qdma_io_cb *iocb, bool write) +{ + int i; + + if (!iocb->pages || !iocb->pages_nr) + return; + + for (i = 0; i < iocb->pages_nr; i++) { + if (iocb->pages[i]) { + if (!write) + set_page_dirty(iocb->pages[i]); + put_page(iocb->pages[i]); + } else { + break; + } + } + + if (i != iocb->pages_nr) + pr_err("slash: qdma: sgl pages %d/%u.\n", i, iocb->pages_nr); + + iocb->pages_nr = 0; +} + +static int slash_qdma_map_user_buf_to_sgl(struct slash_qdma_io_cb *iocb, + bool write) +{ + unsigned long len = iocb->len; + char *buf = (char *)iocb->buf; + struct qdma_sw_sg *sg; + unsigned int pg_off = offset_in_page(buf); + unsigned int pages_nr = (len + pg_off + PAGE_SIZE - 1) >> PAGE_SHIFT; + int i; + int rv; + + if (len == 0) + pages_nr = 1; + if (pages_nr == 0) + return -EINVAL; + + iocb->pages_nr = 0; + sg = kmalloc(pages_nr * (sizeof(struct qdma_sw_sg) + + sizeof(struct page *)), GFP_KERNEL); + if (!sg) { + pr_err("slash: qdma: sgl allocation failed for %u pages\n", + pages_nr); + return -ENOMEM; + } + memset(sg, 0, pages_nr * (sizeof(struct qdma_sw_sg) + + sizeof(struct page *))); + iocb->sgl = sg; + + iocb->pages = (struct page **)(sg + pages_nr); + rv = get_user_pages_fast((unsigned long)buf, pages_nr, + 1 /* write */, iocb->pages); + if (rv < 0) { + pr_err("slash: qdma: unable to pin down %u user pages, %d\n", + pages_nr, rv); + goto err_out; + } + if (rv != pages_nr) { + pr_err("slash: qdma: unable to pin down all %u user pages, %d\n", + pages_nr, rv); + iocb->pages_nr = rv; + rv = -EFAULT; + goto err_out; + } + + sg = iocb->sgl; + for (i = 0; i < pages_nr; i++, sg++) { + unsigned int offset = offset_in_page(buf); + unsigned int nbytes = min_t(unsigned int, + PAGE_SIZE - offset, len); + struct page *pg = iocb->pages[i]; + + flush_dcache_page(pg); + + sg->next = sg + 1; + sg->pg = pg; + sg->offset = offset; + sg->len = nbytes; + sg->dma_addr = 0UL; + + buf += nbytes; + len -= nbytes; + } + + iocb->sgl[pages_nr - 1].next = NULL; + iocb->pages_nr = pages_nr; + return 0; + +err_out: + slash_qdma_unmap_user_buf(iocb, write); + slash_qdma_iocb_release(iocb); + + return rv; +} + +static ssize_t slash_qdma_qpair_read_write(struct file *file, char __user *buf, + size_t count, loff_t *ppos, + bool write) +{ + struct slash_qdma_qpair_file_ctx *ctx = file->private_data; + struct slash_qdma_dev *qdma_dev; + struct slash_qdma_qpair_entry *entry; + struct slash_qdma_io_cb iocb; + struct qdma_request *req; + unsigned long qhndl; + ssize_t res; + int rv; + + if (!ctx) + return -EINVAL; + + qdma_dev = ctx->qdma_dev; + entry = ctx->entry; + + if (!qdma_dev || !entry) + return -ENODEV; + + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + + if (write) { + if (!(entry->dir_mask & SLASH_QDMA_DIR_H2C) || + !entry->qhndl[Q_H2C]) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + qhndl = entry->qhndl[Q_H2C]; + } else { + if (!(entry->dir_mask & SLASH_QDMA_DIR_C2H) || + !entry->qhndl[Q_C2H]) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + qhndl = entry->qhndl[Q_C2H]; + } + mutex_unlock(&qdma_dev->lock); + + memset(&iocb, 0, sizeof(iocb)); + iocb.buf = buf; + iocb.len = count; + rv = slash_qdma_map_user_buf_to_sgl(&iocb, write); + if (rv < 0) + return rv; + + req = &iocb.req; + req->sgcnt = iocb.pages_nr; + req->sgl = iocb.sgl; + req->write = write ? 1 : 0; + req->dma_mapped = 0; + req->udd_len = 0; + req->ep_addr = (u64)*ppos; + req->count = count; + req->timeout_ms = 10 * 1000; + req->fp_done = NULL; + req->h2c_eot = 1; + + res = qdma_request_submit(qdma_dev->qdma_handle, qhndl, req); + if (res > 0) + *ppos += res; + + slash_qdma_unmap_user_buf(&iocb, write); + slash_qdma_iocb_release(&iocb); + + return res; +} + +static ssize_t slash_qdma_qpair_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + return slash_qdma_qpair_read_write(file, buf, count, ppos, false); +} + +static ssize_t slash_qdma_qpair_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + return slash_qdma_qpair_read_write(file, (char __user *)buf, + count, ppos, true); +} + +static long slash_qdma_qpair_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + (void)file; + (void)cmd; + (void)arg; + + return -ENOTTY; +} + +static int slash_qdma_qpair_release(struct inode *inode, struct file *file) +{ + struct slash_qdma_qpair_file_ctx *ctx = file->private_data; + + (void)inode; + + if (ctx) { + if (ctx->entry) + slash_qdma_qpair_put(ctx->entry); + if (ctx->qdma_dev) + kref_put(&ctx->qdma_dev->ref, slash_qdma_dev_release); + kfree(ctx); + file->private_data = NULL; + } + + return 0; +} + +static int slash_qdma_ioctl_qpair_get_fd_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg) +{ + struct slash_qdma_qpair_fd_request req; + __u32 user_size = 0; + size_t copy_size; + struct slash_qdma_qpair_entry *entry; + struct slash_qdma_qpair_file_ctx *ctx; + struct file *file; + int fd; + int err; + + (void)misc; + + if (copy_from_user(&user_size, uarg, sizeof(user_size))) + return -EFAULT; + + if (!user_size || user_size > sizeof(req)) + user_size = sizeof(req); + + memset(&req, 0, sizeof(req)); + + if (copy_from_user(&req, uarg, user_size)) + return -EFAULT; + + if (req.flags & ~O_CLOEXEC) + return -EINVAL; + + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + + entry = slash_qdma_qpair_lookup(qdma_dev, req.qid); + if (!entry || !entry->dir_mask) { + mutex_unlock(&qdma_dev->lock); + return -ENOENT; + } + + slash_qdma_qpair_get(entry); + kref_get(&qdma_dev->ref); + mutex_unlock(&qdma_dev->lock); + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + slash_qdma_qpair_put(entry); + kref_put(&qdma_dev->ref, slash_qdma_dev_release); + return -ENOMEM; + } + + ctx->qdma_dev = qdma_dev; + ctx->entry = entry; + ctx->qid = req.qid; + + file = anon_inode_getfile("slash_qdma_qpair", &slash_qdma_qpair_fops, + ctx, O_RDWR | (req.flags & O_CLOEXEC)); + if (IS_ERR(file)) { + err = PTR_ERR(file); + slash_qdma_qpair_put(entry); + kref_put(&qdma_dev->ref, slash_qdma_dev_release); + kfree(ctx); + return err; + } + + fd = get_unused_fd_flags(req.flags & O_CLOEXEC); + if (fd < 0) { + fput(file); + slash_qdma_qpair_put(entry); + kref_put(&qdma_dev->ref, slash_qdma_dev_release); + kfree(ctx); + return fd; + } + + req.size = sizeof(req); + copy_size = min_t(size_t, user_size, sizeof(req)); + if (copy_to_user(uarg, &req, copy_size)) { + put_unused_fd(fd); + fput(file); + slash_qdma_qpair_put(entry); + kref_put(&qdma_dev->ref, slash_qdma_dev_release); + kfree(ctx); + return -EFAULT; + } + + fd_install(fd, file); + + return fd; +} + +/* Must be called with qdma_dev->lock held */ +static void slash_qdma_qpair_teardown(struct slash_qdma_dev *qdma_dev, u32 qid, + struct slash_qdma_qpair_entry *entry) +{ + unsigned int idx; + + if (!entry) + return; + + /* Remove any queues that still exist */ + for (idx = 0; idx < SLASH_QDMA_QTYPE_COUNT; idx++) { + enum queue_type_t qtype = idx; + + if (entry->dir_mask & slash_qdma_qtype_to_dir(qtype)) + slash_qdma_ioctl_qpair_rm_q(&qdma_dev->misc, qdma_dev, entry, qtype); + } + + /* Mark entry dead for any stale FDs */ + memset(entry->qhndl, 0, sizeof(entry->qhndl)); + entry->dir_mask = 0; + + /* Drop from xarray and release ref */ + xa_erase(&qdma_dev->qpairs, qid); + slash_qdma_qpair_put(entry); +} diff --git a/driver/slash_qdma.h b/driver/slash_qdma.h new file mode 100644 index 00000000..5558a38c --- /dev/null +++ b/driver/slash_qdma.h @@ -0,0 +1,23 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef SLASH_QDMA_H +#define SLASH_QDMA_H + +#include + +int __init slash_qdma_init(unsigned int num_threads, char *debugfs); +void __exit slash_qdma_exit(void); + +#endif /* SLASH_QDMA_H */ diff --git a/examples/05_perf/Makefile b/examples/05_perf/Makefile index 8a080dbf..070fd178 100644 --- a/examples/05_perf/Makefile +++ b/examples/05_perf/Makefile @@ -48,7 +48,7 @@ hls: hw: setup hls @echo "Running HW step" (cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform hw --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_PERF)/sol1 && \ + ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform hw --segmented --source-pre-synth $(HOME_DIR)/c.tcl --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_PERF)/sol1 && \ cp build/$(DESIGN_NAME)_hw.vrtbin $(BUILD_DIR)) emu: setup hls diff --git a/examples/05_perf/config.cfg b/examples/05_perf/config.cfg index 0d5889da..7a436577 100644 --- a/examples/05_perf/config.cfg +++ b/examples/05_perf/config.cfg @@ -23,4 +23,8 @@ nk=perf:15:perf_0.perf_1.perf_2.perf_3.perf_4.perf_5.perf_6.perf_7.perf_8.perf_9.perf_10.perf_11.perf_12.perf_13.perf_14 [clock] -freqhz=300000000 \ No newline at end of file +freqhz=300000000 + +[asd] +pre_synth=a.tcl +post_build=b.tcl diff --git a/examples/06_dcmac/06_dcmac.cpp b/examples/06_dcmac/06_dcmac.cpp new file mode 100644 index 00000000..25db5a15 --- /dev/null +++ b/examples/06_dcmac/06_dcmac.cpp @@ -0,0 +1,51 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include +#include +#include + +int main(int argc, char* argv[]) { + try { + if (argc < 3) { + std::cerr << "Usage: " << argv[0] << " " << std::endl; + return 1; + } + std::string bdf = argv[1]; + std::string vrtbinFile = argv[2]; + vrt::utils::Logger::setLogLevel(vrt::utils::LogLevel::DEBUG); + uint32_t size = 1024; + + vrt::Device device(bdf, vrtbinFile); + vrt::Kernel traffic_producer_0(device, "traffic_producer_0"); + vrt::Kernel traffic_producer_1(device, "traffic_producer_1"); + traffic_producer_0.start(100, 0); + traffic_producer_0.wait(); + traffic_producer_1.start(100, 1); + traffic_producer_1.wait(); + device.cleanup(); + } catch (std::exception const& e) { + std::cerr << "Exception: " << e.what() << std::endl; + return 1; + } +} \ No newline at end of file diff --git a/examples/06_dcmac/CMakeLists.txt b/examples/06_dcmac/CMakeLists.txt new file mode 100644 index 00000000..56c71fc4 --- /dev/null +++ b/examples/06_dcmac/CMakeLists.txt @@ -0,0 +1,41 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +cmake_minimum_required(VERSION 3.10) +project(00_axilite) + +set(CMAKE_CXX_STANDARD 20) +set(CMAKE_CXX_STANDARD_REQUIRED ON) +set(CMAKE_CXX_FLAGS "-O3") + +# Include directories +include_directories(/usr/local/vrt/include + /usr/include/ami + /usr/include/libxml2 + /usr/include/jsoncpp) + +# Define sources for the executable +set(EXE_SOURCES 06_dcmac.cpp) + +# Create the executable +add_executable(${PROJECT_NAME} ${EXE_SOURCES}) + +# Link the library to the executable +target_link_libraries(${PROJECT_NAME} vrt ami xml2 zmq jsoncpp) \ No newline at end of file diff --git a/examples/06_dcmac/Makefile b/examples/06_dcmac/Makefile new file mode 100644 index 00000000..f76b8302 --- /dev/null +++ b/examples/06_dcmac/Makefile @@ -0,0 +1,61 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +HLS_BUILD_DIR_TRAFFIC_PRODUCER=build_traffic_producer.xcv80-lsva4737-2MHP-e-S +DESIGN_NAME=06_dcmac +HOME_DIR=$(shell realpath .) +BUILD_DIR=$(shell realpath ./build) +HLS_DIR=$(shell realpath ./hls) +V80PP_PATH=$(shell realpath ../../submodules/v80-vitis-flow) +VPP_DIR=$(BUILD_DIR)/v80-vitis-flow + +.PHONY: all setup hls hw app clean + +all: setup hls hw app + +hw_all: setup hls hw app + +setup: + mkdir -p $(BUILD_DIR) + cp -r $(V80PP_PATH) $(BUILD_DIR) + +hls: + @echo "Running HLS step" + $(MAKE) -C $(HLS_DIR) + +hw: setup hls + @echo "Running HW step" + cd $(VPP_DIR) && \ + ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform hw --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_TRAFFIC_PRODUCER)/sol1 && \ + cp build/$(DESIGN_NAME)_hw.vrtbin $(BUILD_DIR) + +app: setup + @echo "Running user app build step" + mkdir -p $(BUILD_DIR) && cd $(BUILD_DIR) && \ + cmake .. && \ + make -j9 + @echo "Setting LD_LIBRARY_PATH" + export LD_LIBRARY_PATH=$$(dirname $$(which vivado))/../lib/lnx64.o:$$LD_LIBRARY_PATH + @echo "Setting PATH" + export PATH=$$PATH:/usr/local/sbin + +clean: + rm -rf $(BUILD_DIR) + make -C $(HLS_DIR) clean \ No newline at end of file diff --git a/examples/06_dcmac/config.cfg b/examples/06_dcmac/config.cfg new file mode 100644 index 00000000..f461c46c --- /dev/null +++ b/examples/06_dcmac/config.cfg @@ -0,0 +1,29 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +[network] +eth_0=1 +eth_2=1 + +[connectivity] +nk=traffic_producer:2:traffic_producer_0.traffic_producer_1 + +stream_connect=traffic_producer_0.axis_out:eth_0.tx +stream_connect=traffic_producer_1.axis_out:eth_2.tx \ No newline at end of file diff --git a/examples/06_dcmac/hls/Makefile b/examples/06_dcmac/hls/Makefile new file mode 100644 index 00000000..3c943b5c --- /dev/null +++ b/examples/06_dcmac/hls/Makefile @@ -0,0 +1,34 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +TARGET=ip +DEVICE=xcv80-lsva4737-2MHP-e-S + +TRAFFIC_PRODUCER_BUILD_DIR=build_traffic_producer.$(DEVICE) + +all: $(TRAFFIC_PRODUCER_BUILD_DIR) + +$(TRAFFIC_PRODUCER_BUILD_DIR): + if [ ! -d "$(TRAFFIC_PRODUCER_BUILD_DIR)" ]; then \ + vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) traffic_producer; \ + fi + +clean: + rm -rf $(TRAFFIC_PRODUCER_BUILD_DIR) \ No newline at end of file diff --git a/examples/06_dcmac/hls/build.tcl b/examples/06_dcmac/hls/build.tcl new file mode 100644 index 00000000..5a2afc91 --- /dev/null +++ b/examples/06_dcmac/hls/build.tcl @@ -0,0 +1,79 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set command [lindex $argv 0] +set device [lindex $argv 1] +set ipname [lindex $argv 2] + +set do_sim 0 +set do_syn 0 +set do_export 0 +set do_cosim 0 + +switch $command { + "sim" { + set do_sim 1 + } + "syn" { + set do_syn 1 + } + "ip" { + set do_syn 1 + set do_export 1 + } + "cosim" { + set do_syn 1 + set do_cosim 1 + } + "all" { + set do_sim 1 + set do_syn 1 + set do_export 1 + set do_cosim 1 + } + default { + puts "Unrecognized command" + exit + } +} + + +open_project build_${ipname}.${device} + +file copy -force $ipname.cpp build_${ipname}.${device}/$ipname.cpp +add_files $ipname.cpp -cflags "-std=c++14" + +set_top $ipname + +open_solution sol1 + +if {$do_syn} { + set_part $device + create_clock -period 4 -name default + config_interface -m_axi_addr64=true + csynth_design +} + +if {$do_export} { + config_export -format ip_catalog + export_design +} + +exit \ No newline at end of file diff --git a/examples/06_dcmac/hls/traffic_producer.cpp b/examples/06_dcmac/hls/traffic_producer.cpp new file mode 100644 index 00000000..2f81dd8d --- /dev/null +++ b/examples/06_dcmac/hls/traffic_producer.cpp @@ -0,0 +1,35 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +#include "ap_axi_sdata.h" +#include "ap_int.h" +#include "hls_stream.h" + +#define DWIDTH 512 +#define TDWIDTH 3 + +typedef ap_axiu pkt; + +void traffic_producer(hls::stream &axis_out, + ap_uint<32> flits, + ap_uint dest){ + +#pragma HLS INTERFACE mode=axis port=axis_out depth=16 +#pragma HLS INTERFACE mode=s_axilite port=dest bundle=control +#pragma HLS INTERFACE mode=s_axilite port=flits bundle=control +#pragma HLS INTERFACE mode=s_axilite port=return bundle=control + + pkt axi_word; +generator: + for(unsigned int i=0; i< flits; i++){ + #pragma HLS PIPELINE II=1 + for(unsigned int j=0; j + + xilinx.com + ip + cmd_queue + 2.0 + + + S00_AXI + + + + + + + ARADDR + + + s00_axi_araddr + + + + + ARREADY + + + s00_axi_arready + + + + + ARVALID + + + s00_axi_arvalid + + + + + AWADDR + + + s00_axi_awaddr + + + + + AWREADY + + + s00_axi_awready + + + + + AWVALID + + + s00_axi_awvalid + + + + + BREADY + + + s00_axi_bready + + + + + BRESP + + + s00_axi_bresp + + + + + BVALID + + + s00_axi_bvalid + + + + + RDATA + + + s00_axi_rdata + + + + + RREADY + + + s00_axi_rready + + + + + RRESP + + + s00_axi_rresp + + + + + RVALID + + + s00_axi_rvalid + + + + + WDATA + + + s00_axi_wdata + + + + + WREADY + + + s00_axi_wready + + + + + WSTRB + + + s00_axi_wstrb + + + + + WVALID + + + s00_axi_wvalid + + + + + + S01_AXI + + + + + + + ARADDR + + + s01_axi_araddr + + + + + ARREADY + + + s01_axi_arready + + + + + ARVALID + + + s01_axi_arvalid + + + + + AWADDR + + + s01_axi_awaddr + + + + + AWREADY + + + s01_axi_awready + + + + + AWVALID + + + s01_axi_awvalid + + + + + BREADY + + + s01_axi_bready + + + + + BRESP + + + s01_axi_bresp + + + + + BVALID + + + s01_axi_bvalid + + + + + RDATA + + + s01_axi_rdata + + + + + RREADY + + + s01_axi_rready + + + + + RRESP + + + s01_axi_rresp + + + + + RVALID + + + s01_axi_rvalid + + + + + WDATA + + + s01_axi_wdata + + + + + WREADY + + + s01_axi_wready + + + + + WSTRB + + + s01_axi_wstrb + + + + + WVALID + + + s01_axi_wvalid + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + S00_AXI:S01_AXI + + + ASSOCIATED_RESET + aresetn + + + FREQ_HZ + aclk frequency + aclk frequency + 250000000 + + + + + irq_sq + irq_sq + + + + + + + INTERRUPT + + + irq_sq + + + + + + SENSITIVITY + EDGE_RISING + + + + + irq_cq + irq_cq + + + + + + + INTERRUPT + + + irq_cq + + + + + + SENSITIVITY + EDGE_RISING + + + + + + + S00_AXI + S00_AXI memory map + + S00_AXI_Reg + 0 + 4096 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_S00_AXI_BASEADDR + + + OFFSET_HIGH_PARAM + C_S00_AXI_HIGHADDR + + + + SQ_TAIL_POINTER + SQ_TAIL_POINTER + Submission Queue Tail Pointer Register + 0x000 + 32 + read-write + + 0x0 + + + TAIL_POINTER_OFFSET + TAIL_POINTER_OFFSET + Submission Queue Tail Pointer Offset +Configure the Tail Pointer offset for the Submission Queue. +If the INTERRUPT_TYPE field in SQ_RESET_INTERRUPT_CTRL register is 0x0, then a write to this register triggers the submission queue interrupt. +Once triggered, the submission queue interrupt can only be cleared by reading the the SQ_TAIL_POINTER register on the S01_AXI interface. + + 0 + 32 + read-write + + 0 + 0 + + false + + + + SQ_INTERRUPT_REG + SQ_INTERRUPT_REG + Submission Queue Interrupt Register + 0x004 + 32 + read-write + + 0x0 + + + INTERRUPT + INTERRUPT + Submission Queue Interrupt +When set - and while the INTERRUPT_TYPE field is 0x1, INTERRUPT_ENABLE field is 0x1, and RESET field is 0x0 in SQ_RESET_INTERRUPT_CTRL register - triggers an interrupt on the submission queue. +Once triggered, the submission queue interrupt can only be cleared by reading the INTERRUPT_STATUS field of the SQ_INTERRUPT_STATUS register. +0x0 - Do not trigger an interrupt on the submission queue +0x1 - Trigger an interrupt on the submission queue + + 0 + 1 + write-only + + 0 + 0 + + false + + + INTERRUPT_STATUS + INTERRUPT_STATUS + Submission Queue Interrupt Status +Reports the current status of the Submission Queue interrupt. +0x0 - Submission Queue interrupt de-asserted +0x1 - Submission Queue interrupt asserted + + 1 + 1 + read-only + + 0 + 0 + + false + + + + SQ_QUEUE_MEM_ADDR_LOW + SQ_QUEUE_MEM_ADDR_LOW + Submission Queue Memory Address Low + 0x008 + 32 + read-write + + 0x0 + + + MEM_ADDR_LOW + MEM_ADDR_LOW + Submission Queue Memory Address Low +Represents bits 31:0 of the submission queue device memory address. + + 0 + 32 + read-write + + 0 + 0 + + false + + + + SQ_RESET_INTERRUPT_CTRL + SQ_RESET_INTERRUPT_CTRL + Submission Queue Reset and Interrupt Control + 0x00C + 32 + read-write + + 0x0 + + + INTERRUPT_ENABLE + INTERRUPT_ENABLE + Submission Queue Interrupt Enable +When set, enables the submission queue interrupt output. +0x0 - Disable submission queue interrupt +0x1 - Enable submission queue interrupt + + 0 + 1 + read-write + + 0 + 0 + + false + + + INTERRUPT_TYPE + INTERRUPT_TYPE + Submission Queue Interrupt Type +Determines the interrupt type in use for the submission queue. +0x0 - Interrupt for the submission queue is triggered on a write operation to the SQ_TAIL_POINTER register +0x1 - Interrupt for the submission queue is triggered by setting the INTERRUPT field of the SQ_INTERRUPT_REG register to 0x1 + + 1 + 1 + read-write + + 0 + 0 + + false + + + RESET + RESET + Reset +Performs a soft reset of all submission queue and completion queue registers. +0x0 - Do not reset all submission/completion queue registers +0x1 - Reset all submission/completion queue registers +This field is self-clearing once set. + + 31 + 1 + write-only + + 0 + 0 + + false + + + + SQ_QUEUE_MEM_ADDR_HIGH + SQ_QUEUE_MEM_ADDR_HIGH + Submission Queue Memory Address High + 0x010 + 32 + read-write + + 0x0 + + + MEM_ADDR_HIGH + MEM_ADDR_HIGH + Submission Queue Memory Address High +Represents bits 63:32 of the submission queue device memory address. + + 0 + 32 + read-write + + 0 + 0 + + false + + + + CQ_TAIL_POINTER + CQ_TAIL_POINTER + Completion Queue Tail Pointer Register + 0x100 + 32 + read-only + + 0x0 + + + TAIL_POINTER_OFFSET + TAIL_POINTER_OFFSET + Completion Queue Tail Pointer Offset +Returns the tail pointer offset for the completion queue. +If the INTERRUPT_TYPE field in CQ_RESET_INTERRUPT_CTRL is 0x0, then reading this register clears the completion queue interrupt if asserted. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + CQ_INTERRUPT_STATUS + CQ_INTERRUPT_STATUS + Completion Queue Interrupt Status Register + 0x104 + 32 + read-only + + 0x0 + + + INTERRUPT_STATUS + INTERRUPT_STATUS + Completion Queue Interrupt Status +Returns the current state of the interrupt for the completion queue. +If the INTERRUPT_TYPE field in CQ_RESET_INTERRUPT_CTRL is 0x1, then reading this register clears the completion queue interrupt if asserted. + + 0 + 1 + read-only + + 0 + 0 + + clear + false + + + + CQ_QUEUE_MEM_ADDR_LOW + CQ_QUEUE_MEM_ADDR_LOW + Completion Queue Memory Address Low + 0x108 + 32 + read-only + + 0x0 + + + MEM_ADDR_LOW + MEM_ADDR_LOW + Completion Queue Memory Address Low +Returns bits 31:0 of the completion queue device memory address. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + CQ_RESET_INTERRUPT_CTRL + CQ_RESET_INTERRUPT_CTRL + Completion Queue Reset and Interrupt Control + 0x10C + 32 + read-only + + 0x0 + + + INTERRUPT_ENABLE + INTERRUPT_ENABLE + Completion Queue Interrupt Enable +Returns the enable state for completion queue interrupt. +0x0 - Completion Queue interrupt output disabled +0x1 - Completion Queue interrupt output enabled + + 0 + 1 + read-only + + 0 + 0 + + false + + + INTERRUPT_TYPE + INTERRUPT_TYPE + Completion Queue Interrupt Type +Returns the interrupt type for the completion queue. +0x0 - Interrupt for the completion queue is triggered on a write operation to the CQ_TAIL_POINTER register +0x1 - Interrupt for the completion queue is triggered by setting the INTERRUPT field of the CQ_INTERRUPT_REG register to 0x1 + + 1 + 1 + read-only + + 0 + 0 + + false + + + + CQ_QUEUE_MEM_ADDR_HIGH + CQ_QUEUE_MEM_ADDR_HIGH + Completion Queue Memory Address High + 0x110 + 32 + read-only + + 0x0 + + + MEM_ADDR_HIGH + MEM_ADDR_HIGH + Completion Queue Memory Address High +Returns bits 63:32 of the completion queue device memory address. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + + + S01_AXI + S01_AXI memory map + + S01_AXI_Reg + 0 + 4096 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_S01_AXI_BASEADDR + + + OFFSET_HIGH_PARAM + C_S01_AXI_HIGHADDR + + + + CQ_TAIL_POINTER + CQ_TAIL_POINTER + Completion Queue Tail Pointer Register + 0x000 + 32 + read-write + + 0x0 + + + TAIL_POINTER_OFFSET + TAIL_POINTER_OFFSET + Completion Queue Tail Pointer Offset +Configure the Tail Pointer offset for the Completion Queue. +If the INTERRUPT_TYPE field in CQ_RESET_INTERRUPT_CTRL register is 0x0, then a write to this register triggers the completion queue interrupt. +Once triggered, the completion queue interrupt can only be cleared by reading the the CQ_TAIL_POINTER register on the S00_AXI interface. + + 0 + 32 + read-write + + 0 + 0 + + false + + + + CQ_INTERRUPT_REG + CQ_INTERRUPT_REG + Completion Queue Interrupt Register + 0x004 + 32 + read-write + + 0x0 + + + INTERRUPT + INTERRUPT + Completion Queue Interrupt +When set - and while the INTERRUPT_TYPE field is 0x1, INTERRUPT_ENABLE field is 0x1, and RESET field is 0x0 in SQ_RESET_INTERRUPT_CTRL register - triggers an interrupt on the completion queue. +Once triggered, the submission queue interrupt can only be cleared by reading the INTERRUPT_STATUS field of the CQ_INTERRUPT_STATUS register. +0x0 - Do not trigger an interrupt on the completion queue +0x1 - Trigger an interrupt on the completion queue + + 0 + 1 + write-only + + 0 + 0 + + false + + + INTERRUPT_STATUS + INTERRUPT_STATUS + Completion Queue Interrupt Status +Reports the current status of the Completion Queue interrupt. +0x0 - Completion Queue interrupt de-asserted +0x1 - Completion Queue interrupt asserted + + 1 + 1 + read-only + + 0 + 0 + + false + + + + CQ_QUEUE_MEM_ADDR_LOW + CQ_QUEUE_MEM_ADDR_LOW + Completion Queue Memory Address Low + 0x008 + 32 + read-write + + 0x0 + + + MEM_ADDR_LOW + MEM_ADDR_LOW + Completion Queue Memory Address Low +Represents bits 31:0 of the completion queue device memory address. + + 0 + 32 + read-write + + 0 + 0 + + false + + + + CQ_RESET_INTERRUPT_CTRL + CQ_RESET_INTERRUPT_CTRL + Completion Queue Reset and Interrupt Control + 0x00C + 32 + read-write + + 0x0 + + + INTERRUPT_ENABLE + INTERRUPT_ENABLE + Completion Queue Interrupt Enable +When set, enables the completion queue interrupt output. +0x0 - Disable completion queue interrupt +0x1 - Enable completion queue interrupt + + 0 + 1 + read-write + + 0 + 0 + + false + + + INTERRUPT_TYPE + INTERRUPT_TYPE + Completion Queue Interrupt Type +Determines the interrupt type in use for the completion queue. +0x0 - Interrupt for the completion queue is triggered on a write operation to the CQ_TAIL_POINTER register +0x1 - Interrupt for the completion queue is triggered by setting the INTERRUPT field of the CQ_INTERRUPT_REG register to 0x1 + + 1 + 1 + read-write + + 0 + 0 + + false + + + RESET + RESET + Reset +Performs a soft reset of all submission queue and completion queue registers. +0x0 - Do not reset all submission/completion queue registers +0x1 - Reset all submission/completion queue registers +This field is self-clearing once set. + + 31 + 1 + write-only + + 0 + 0 + + false + + + + CQ_QUEUE_MEM_ADDR_HIGH + CQ_QUEUE_MEM_ADDR_HIGH + Completion Queue Memory Address High + 0x010 + 32 + read-write + + 0x0 + + + MEM_ADDR_HIGH + MEM_ADDR_HIGH + Completion Queue Memory Address High +Represents bits 63:32 of the completion queue device memory address. + + 0 + 32 + read-write + + 0 + 0 + + false + + + + SQ_TAIL_POINTER + SQ_TAIL_POINTER + Submission Queue Tail Pointer Register + 0x100 + 32 + read-only + + 0x0 + + + TAIL_POINTER_OFFSET + TAIL_POINTER_OFFSET + Submission Queue Tail Pointer Offset +Returns the tail pointer offset for the submission queue. +If the INTERRUPT_TYPE field in SQ_RESET_INTERRUPT_CTRL is 0x0, then reading this register clears the submission queue interrupt if asserted. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + SQ_INTERRUPT_STATUS + SQ_INTERRUPT_STATUS + Submission Queue Interrupt Status Register + 0x104 + 32 + read-only + + 0x0 + + + INTERRUPT_STATUS + INTERRUPT_STATUS + Submission Queue Interrupt Status +Returns the current state of the interrupt for the submission queue. +If the INTERRUPT_TYPE field in SQ_RESET_INTERRUPT_CTRL is 0x1, then reading this register clears the submission queue interrupt if asserted. + + 0 + 1 + read-only + + 0 + 0 + + clear + false + + + + SQ_QUEUE_MEM_ADDR_LOW + SQ_QUEUE_MEM_ADDR_LOW + Submission Queue Memory Address Low + 0x108 + 32 + read-only + + 0x0 + + + MEM_ADDR_LOW + MEM_ADDR_LOW + Submission Queue Memory Address Low +Returns bits 31:0 of the submission queue device memory address. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + SQ_RESET_INTERRUPT_CTRL + SQ_RESET_INTERRUPT_CTRL + Submission Queue Reset and Interrupt Control + 0x10C + 32 + read-only + + 0x0 + + + INTERRUPT_ENABLE + INTERRUPT_ENABLE + Submission Queue Interrupt Enable +Returns the enable state for submission queue interrupt. +0x0 - Submission Queue interrupt output disabled +0x1 - Submission Queue interrupt output enabled + + 0 + 1 + read-only + + 0 + 0 + + false + + + INTERRUPT_TYPE + INTERRUPT_TYPE + Submission Queue Interrupt Type +Returns the interrupt type for the submission queue. +0x0 - Interrupt for the submission queue is triggered on a write operation to the SQ_TAIL_POINTER register +0x1 - Interrupt for the submission queue is triggered by setting the INTERRUPT field of the SQ_INTERRUPT_REG register to 0x1 + + 1 + 1 + read-only + + 0 + 0 + + false + + + + SQ_QUEUE_MEM_ADDR_HIGH + SQ_QUEUE_MEM_ADDR_HIGH + Submission Queue Memory Address High + 0x110 + 32 + read-only + + 0x0 + + + MEM_ADDR_HIGH + MEM_ADDR_HIGH + Submission Queue Memory Address High +Returns bits 63:32 of the submission queue device memory address. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + viewChecksum + 5bbca8ec + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 1eb13238 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + cmd_queue_v2_0_0 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 7420b60d + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + cmd_queue_v2_0_0 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 7420b60d + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_awaddr + + in + + 11 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_wready + + out + + + wire + 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xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_araddr + + in + + 11 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + irq_sq + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + irq_cq + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + C_S00_ADDR_WIDTH + 12 + + + C_S01_ADDR_WIDTH + 12 + + + C_S00_AXI_BASEADDR + 0xFFFFFFFF + + + + true + + + + + + C_S00_AXI_HIGHADDR + 0x00000000 + + + + true + + + + + + C_S01_AXI_BASEADDR + 0xFFFFFFFF + + + + true + + + + + + C_S01_AXI_HIGHADDR + 0x00000000 + + + + true + + + + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + cmd_queue_v2_0_0 + + + + xilinx_xpgui_view_fileset + + xgui/cmd_queue_v2_0.tcl + tclSource + XGUI_VERSION_2 + cmd_queue_v2_0_0 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/cmd_queue_v2_0_axi_if.sv + systemVerilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_reg_if.sv + systemVerilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_axi_reg.sv + systemVerilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_axi.sv + systemVerilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_regs.sv + systemVerilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_top.sv + systemVerilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0.v + verilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/cmd_queue_v2_0_axi_if.sv + systemVerilogSource + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_reg_if.sv + systemVerilogSource + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_axi_reg.sv + systemVerilogSource + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_axi.sv + systemVerilogSource + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_regs.sv + systemVerilogSource + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_top.sv + systemVerilogSource + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0.v + verilogSource + CHECKSUM_1469164e + cmd_queue_v2_0_0 + + + + xilinx_versioninformation_view_fileset + + doc/cmd_queue_v2_0_changelog.txt + text + cmd_queue_v2_0_0 + + + + Generic Command Queue IP to facilitate communications between different devices + + + Component_Name + cmd_queue_v2_0 + + + + + + /Shell_Subsystems + + Generic Command Queue + level_beta + (GENERIC_FAMILY = versal) + http://www.xilinx.com/ + 0 + 2023-10-11T08:38:32Z + + + 2023.1 + + + + + + + + + diff --git a/linker/resources/base/iprepo/cmd_queue_v2_0/doc/cmd_queue_v2_0_changelog.txt b/linker/resources/base/iprepo/cmd_queue_v2_0/doc/cmd_queue_v2_0_changelog.txt new file mode 100644 index 00000000..c1422f9a --- /dev/null +++ b/linker/resources/base/iprepo/cmd_queue_v2_0/doc/cmd_queue_v2_0_changelog.txt @@ -0,0 +1,28 @@ +2023.1: + * Version 2.0 + * No changes + +2022.2.2: + * Version 2.0 + * No changes + +2022.2.1: + * Version 2.0 + * No changes + +2022.2: + * Version 2.0 + * Port Change: Updated clock/reset port naming to indicate common clock/reset association with S00/S01 + +2022.1.2: + * Version 1.0 + * No changes + +2022.1.1: + * Version 1.0 + * No changes + +2022.1: + * Version 1.0 + * Initial Release + diff --git a/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0.v b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0.v new file mode 100644 index 00000000..c1e5495f --- /dev/null +++ b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0.v @@ -0,0 +1,138 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +`timescale 1ns/1ps + +module cmd_queue_v2_0_0 #( + parameter integer C_S00_ADDR_WIDTH = 12, + parameter integer C_S01_ADDR_WIDTH = 12, + parameter C_S00_AXI_BASEADDR = 32'hFFFFFFFF, + parameter C_S00_AXI_HIGHADDR = 32'h00000000, + parameter C_S01_AXI_BASEADDR = 32'hFFFFFFFF, + parameter C_S01_AXI_HIGHADDR = 32'h00000000 +) ( + // Clock Ports + input wire aclk, + + // Reset Ports + input wire aresetn, + + // S00_AXI Interface Ports + input wire [C_S00_ADDR_WIDTH-1:0] s00_axi_awaddr, + input wire s00_axi_awvalid, + output wire s00_axi_awready, + input wire [32-1:0] s00_axi_wdata, + input wire [4-1:0] s00_axi_wstrb, + input wire s00_axi_wvalid, + output wire s00_axi_wready, + output wire [2-1:0] s00_axi_bresp, + output wire s00_axi_bvalid, + input wire s00_axi_bready, + input wire [C_S00_ADDR_WIDTH-1:0] s00_axi_araddr, + input wire s00_axi_arvalid, + output wire s00_axi_arready, + output wire [32-1:0] s00_axi_rdata, + output wire [2-1:0] s00_axi_rresp, + output wire s00_axi_rvalid, + input wire s00_axi_rready, + + // S01_AXI Interface Ports + input wire [C_S01_ADDR_WIDTH-1:0] s01_axi_awaddr, + input wire s01_axi_awvalid, + output wire s01_axi_awready, + input wire [32-1:0] s01_axi_wdata, + input wire [4-1:0] s01_axi_wstrb, + input wire s01_axi_wvalid, + output wire s01_axi_wready, + output wire [2-1:0] s01_axi_bresp, + output wire s01_axi_bvalid, + input wire s01_axi_bready, + input wire [C_S01_ADDR_WIDTH-1:0] s01_axi_araddr, + input wire s01_axi_arvalid, + output wire s01_axi_arready, + output wire [32-1:0] s01_axi_rdata, + output wire [2-1:0] s01_axi_rresp, + output wire s01_axi_rvalid, + input wire s01_axi_rready, + + // Interrupt Ports + output wire irq_sq, + output wire irq_cq +); + +// -------------------------------------------------------- +// GCQ Top Level Instantiation +// -------------------------------------------------------- +cmd_queue_v2_0_0_top #( + .C_S00_ADDR_WIDTH(C_S00_ADDR_WIDTH), + .C_S01_ADDR_WIDTH(C_S01_ADDR_WIDTH) +) cmd_queue_top_inst ( + // Clocks + .aclk(aclk), + + // Resets + .aresetn(aresetn), + + // S00_AXI Interface + .s00_axi_awaddr(s00_axi_awaddr), + .s00_axi_awvalid(s00_axi_awvalid), + .s00_axi_awready(s00_axi_awready), + .s00_axi_wdata(s00_axi_wdata), + .s00_axi_wstrb(s00_axi_wstrb), + .s00_axi_wvalid(s00_axi_wvalid), + .s00_axi_wready(s00_axi_wready), + .s00_axi_bresp(s00_axi_bresp), + .s00_axi_bvalid(s00_axi_bvalid), + .s00_axi_bready(s00_axi_bready), + .s00_axi_araddr(s00_axi_araddr), + .s00_axi_arvalid(s00_axi_arvalid), + .s00_axi_arready(s00_axi_arready), + .s00_axi_rdata(s00_axi_rdata), + .s00_axi_rresp(s00_axi_rresp), + .s00_axi_rvalid(s00_axi_rvalid), + .s00_axi_rready(s00_axi_rready), + + // S01_AXI Interface + .s01_axi_awaddr(s01_axi_awaddr), + .s01_axi_awvalid(s01_axi_awvalid), + .s01_axi_awready(s01_axi_awready), + .s01_axi_wdata(s01_axi_wdata), + .s01_axi_wstrb(s01_axi_wstrb), + .s01_axi_wvalid(s01_axi_wvalid), + .s01_axi_wready(s01_axi_wready), + .s01_axi_bresp(s01_axi_bresp), + .s01_axi_bvalid(s01_axi_bvalid), + .s01_axi_bready(s01_axi_bready), + .s01_axi_araddr(s01_axi_araddr), + .s01_axi_arvalid(s01_axi_arvalid), + .s01_axi_arready(s01_axi_arready), + .s01_axi_rdata(s01_axi_rdata), + .s01_axi_rresp(s01_axi_rresp), + .s01_axi_rvalid(s01_axi_rvalid), + .s01_axi_rready(s01_axi_rready), + + // Interrupts + .irq_sq(irq_sq), + .irq_cq(irq_cq) + +); + +endmodule diff --git a/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi.sv b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi.sv new file mode 100644 index 00000000..bddae6e6 --- /dev/null +++ b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi.sv @@ -0,0 +1,167 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +module cmd_queue_v2_0_0_axi #( + parameter int C_S00_ADDR_WIDTH = 12, // Address width of SQ AXI and Reg interfaces + parameter int C_S01_ADDR_WIDTH = 12, // Address Width of CQ AXI and Reg interfaces + parameter int C_S00_DATA_WIDTH = 32, // Data width of SQ AXI and Reg interfaces + parameter int C_S01_DATA_WIDTH = 32 // Data width of CQ AXI and Reg interfaces +) ( + // AXI4-Lite Subordinate Interface + cmd_queue_v2_0_0_axi_if.sub sq_axi_if, + cmd_queue_v2_0_0_axi_if.sub cq_axi_if, + + // Manager Register Interfaces + cmd_queue_v2_0_0_reg_if.man sq_reg_if, + cmd_queue_v2_0_0_reg_if.man cq_reg_if, + + // Clock/Reset + input logic aclk, + input logic aresetn +); + +// -------------------------------------------------------- +// Time Units/Precision +// -------------------------------------------------------- +// synthesis translate_off +timeunit 1ns/1ps; +// synthesis translate_on + +// -------------------------------------------------------- +// Parameters +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Types +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Functions +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Variables/Nets +// -------------------------------------------------------- + +logic sq_reg_rd_valid; +logic [C_S00_ADDR_WIDTH-1:0] sq_reg_rd_addr; +logic sq_reg_rd_done; +logic [1:0] sq_reg_rd_resp; +logic [C_S00_DATA_WIDTH-1:0] sq_reg_rd_data; +logic sq_reg_wr_valid; +logic [C_S00_ADDR_WIDTH-1:0] sq_reg_wr_addr; +logic [(C_S00_DATA_WIDTH/8)-1:0] sq_reg_wr_be; +logic [C_S00_DATA_WIDTH-1:0] sq_reg_wr_data; +logic sq_reg_wr_done; +logic [1:0] sq_reg_wr_resp; + +logic cq_reg_rd_valid; +logic [C_S01_ADDR_WIDTH-1:0] cq_reg_rd_addr; +logic cq_reg_rd_done; +logic [1:0] cq_reg_rd_resp; +logic [C_S01_DATA_WIDTH-1:0] cq_reg_rd_data; +logic cq_reg_wr_valid; +logic [C_S01_ADDR_WIDTH-1:0] cq_reg_wr_addr; +logic [(C_S01_DATA_WIDTH/8)-1:0] cq_reg_wr_be; +logic [C_S01_DATA_WIDTH-1:0] cq_reg_wr_data; +logic cq_reg_wr_done; +logic [1:0] cq_reg_wr_resp; + +// ======================================================== + +// -------------------------------------------------------- +// SQ AXI Register Interface Module Instantiation + +cmd_queue_v2_0_0_axi_reg #( + .C_ADDR_WIDTH(C_S00_ADDR_WIDTH), + .C_DATA_WIDTH(C_S00_DATA_WIDTH) +) sq_axi_reg_inst ( + .axi_if(sq_axi_if), + .aclk, + .aresetn, + .reg_rd_valid_o(sq_reg_rd_valid), + .reg_rd_addr_o(sq_reg_rd_addr), + .reg_rd_done_i(sq_reg_rd_done), + .reg_rd_resp_i(sq_reg_rd_resp), + .reg_rd_data_i(sq_reg_rd_data), + .reg_wr_valid_o(sq_reg_wr_valid), + .reg_wr_addr_o(sq_reg_wr_addr), + .reg_wr_be_o(sq_reg_wr_be), + .reg_wr_data_o(sq_reg_wr_data), + .reg_wr_done_i(sq_reg_wr_done), + .reg_wr_resp_i(sq_reg_wr_resp) +); + +// -------------------------------------------------------- +// CQ AXI Register Interface Module Instantiation + +cmd_queue_v2_0_0_axi_reg #( + .C_ADDR_WIDTH(C_S01_ADDR_WIDTH), + .C_DATA_WIDTH(C_S01_DATA_WIDTH) +) cq_axi_reg_inst ( + .axi_if(cq_axi_if), + .aclk, + .aresetn, + .reg_rd_valid_o(cq_reg_rd_valid), + .reg_rd_addr_o(cq_reg_rd_addr), + .reg_rd_done_i(cq_reg_rd_done), + .reg_rd_resp_i(cq_reg_rd_resp), + .reg_rd_data_i(cq_reg_rd_data), + .reg_wr_valid_o(cq_reg_wr_valid), + .reg_wr_addr_o(cq_reg_wr_addr), + .reg_wr_be_o(cq_reg_wr_be), + .reg_wr_data_o(cq_reg_wr_data), + .reg_wr_done_i(cq_reg_wr_done), + .reg_wr_resp_i(cq_reg_wr_resp) +); + +// -------------------------------------------------------- +// Register Interface assignments + +// SQ Register Interface +assign sq_reg_if.reg_rd_valid = sq_reg_rd_valid; +assign sq_reg_if.reg_rd_addr = sq_reg_rd_addr; +assign sq_reg_rd_done = sq_reg_if.reg_rd_done; +assign sq_reg_rd_resp = sq_reg_if.reg_rd_resp; +assign sq_reg_rd_data = sq_reg_if.reg_rd_data; + +assign sq_reg_if.reg_wr_valid = sq_reg_wr_valid; +assign sq_reg_if.reg_wr_addr = sq_reg_wr_addr; +assign sq_reg_if.reg_wr_be = sq_reg_wr_be; +assign sq_reg_if.reg_wr_data = sq_reg_wr_data; +assign sq_reg_wr_done = sq_reg_if.reg_wr_done; +assign sq_reg_wr_resp = sq_reg_if.reg_wr_resp; + +// CQ Register Interface +assign cq_reg_if.reg_rd_valid = cq_reg_rd_valid; +assign cq_reg_if.reg_rd_addr = cq_reg_rd_addr; +assign cq_reg_rd_done = cq_reg_if.reg_rd_done; +assign cq_reg_rd_resp = cq_reg_if.reg_rd_resp; +assign cq_reg_rd_data = cq_reg_if.reg_rd_data; + +assign cq_reg_if.reg_wr_valid = cq_reg_wr_valid; +assign cq_reg_if.reg_wr_addr = cq_reg_wr_addr; +assign cq_reg_if.reg_wr_be = cq_reg_wr_be; +assign cq_reg_if.reg_wr_data = cq_reg_wr_data; +assign cq_reg_wr_done = cq_reg_if.reg_wr_done; +assign cq_reg_wr_resp = cq_reg_if.reg_wr_resp; + +endmodule : cmd_queue_v2_0_0_axi diff --git a/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi_if.sv b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi_if.sv new file mode 100644 index 00000000..a5e858cf --- /dev/null +++ b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi_if.sv @@ -0,0 +1,134 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +interface cmd_queue_v2_0_0_axi_if #( + parameter int C_DATA_WIDTH = 32, + parameter int C_ADDR_WIDTH = 32 +); + +// -------------------------------------------------------- +// Time Units/Precision +// -------------------------------------------------------- +// synthesis translate_off +timeunit 1ns/1ps; +// synthesis translate_on + +// -------------------------------------------------------- +// AXI4-Lite Interface Signals +// -------------------------------------------------------- + +// Write Address Channel +logic [C_ADDR_WIDTH-1:0] awaddr; +logic awvalid; +logic awready; + +// Write Data Channel +logic [C_DATA_WIDTH-1:0] wdata; +logic [(C_DATA_WIDTH/8)-1:0] wstrb; +logic wvalid; +logic wready; + +// Write Response Channel +logic bvalid; +logic bready; +logic [1:0] bresp; + +// Read Address Channel +logic [C_ADDR_WIDTH-1:0] araddr; +logic arvalid; +logic arready; + +// Read Data Channel +logic [C_DATA_WIDTH-1:0] rdata; +logic [1:0] rresp; +logic rvalid; +logic rready; + +// -------------------------------------------------------- +// AXI4-Lite Manager Interface +// -------------------------------------------------------- +modport man ( + output awaddr, + output awvalid, + input awready, + output wdata, + output wstrb, + output wvalid, + input wready, + input bvalid, + input bresp, + output bready, + output araddr, + output arvalid, + input arready, + input rdata, + input rresp, + input rvalid, + output rready +); + +// -------------------------------------------------------- +// AXI4-Lite Subordinate Interface +// -------------------------------------------------------- +modport sub ( + input awaddr, + input awvalid, + output awready, + input wdata, + input wstrb, + input wvalid, + output wready, + output bvalid, + output bresp, + input bready, + input araddr, + input arvalid, + output arready, + output rdata, + output rresp, + output rvalid, + input rready +); + +// -------------------------------------------------------- +// AXI4-Lite Monitor Interface +// -------------------------------------------------------- +modport mon ( + input awaddr, + input awvalid, + input awready, + input wdata, + input wstrb, + input wvalid, + input wready, + input bvalid, + input bresp, + input bready, + input araddr, + input arvalid, + input arready, + input rdata, + input rresp, + input rvalid, + input rready +); + +endinterface : cmd_queue_v2_0_0_axi_if diff --git a/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi_reg.sv b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi_reg.sv new file mode 100644 index 00000000..f883e475 --- /dev/null +++ b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi_reg.sv @@ -0,0 +1,168 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +module cmd_queue_v2_0_0_axi_reg #( + parameter int C_DATA_WIDTH = 32, // Data width + parameter int C_ADDR_WIDTH = 32 // Address width +) ( + // AXI4-Lite Subordinate Interface + cmd_queue_v2_0_0_axi_if.sub axi_if, + + // Clock/Reset + input logic aclk, + input logic aresetn, + + // Register Read Interface + output logic reg_rd_valid_o, + output logic [C_ADDR_WIDTH-1:0] reg_rd_addr_o, + input logic reg_rd_done_i, + input logic [1:0] reg_rd_resp_i, + input logic [C_DATA_WIDTH-1:0] reg_rd_data_i, + + // Register Write Interface + output logic reg_wr_valid_o, + output logic [C_ADDR_WIDTH-1:0] reg_wr_addr_o, + output logic [(C_DATA_WIDTH/8)-1:0] reg_wr_be_o, + output logic [C_DATA_WIDTH-1:0] reg_wr_data_o, + input logic reg_wr_done_i, + input logic [1:0] reg_wr_resp_i +); + +// -------------------------------------------------------- +// Time Units/Precision +// -------------------------------------------------------- +// synthesis translate_off +timeunit 1ns/1ps; +// synthesis translate_on + +// -------------------------------------------------------- +// Parameters +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Types +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Functions +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Variables/Nets +// -------------------------------------------------------- +logic wr_rdy; +logic wr_wait; +logic rd_wait; + +// ======================================================== + +// AXI Write +always_ff @(posedge aclk) begin + if (!aresetn) begin + wr_rdy <= '0; + wr_wait <= '0; + reg_wr_valid_o <= '0; + reg_wr_addr_o <= '0; + reg_wr_be_o <= '0; + reg_wr_data_o <= '0; + axi_if.bvalid <= '0; + axi_if.bresp <= '0; + end else begin + // Defaults + wr_rdy <= '0; + wr_wait <= wr_wait; + reg_wr_valid_o <= '0; + reg_wr_addr_o <= reg_wr_addr_o; + reg_wr_be_o <= reg_wr_be_o; + reg_wr_data_o <= reg_wr_data_o; + axi_if.bvalid <= '0; + axi_if.bresp <= '0; + // coverage off -item c 1 -feccondrow 4 + if (!wr_wait && !wr_rdy && axi_if.awvalid && axi_if.wvalid) begin + // coverage on + wr_rdy <= 1'b1; + wr_wait <= 1'b1; + reg_wr_valid_o <= 1'b1; + reg_wr_addr_o <= axi_if.awaddr; + reg_wr_be_o <= axi_if.wstrb; + reg_wr_data_o <= axi_if.wdata; + end else if (reg_wr_done_i) begin + axi_if.bvalid <= 1'b1; + axi_if.bresp <= reg_wr_resp_i; + reg_wr_addr_o <= '0; + reg_wr_be_o <= '0; + reg_wr_data_o <= '0; + end else if (axi_if.bvalid) begin + if (!axi_if.bready) begin + axi_if.bvalid <= axi_if.bvalid; + axi_if.bresp <= axi_if.bresp; + end else begin + wr_wait <= 1'b0; + end + end + end +end +assign axi_if.awready = wr_rdy; +assign axi_if.wready = wr_rdy; + +// AXI Read +always_ff @(posedge aclk) begin + if (!aresetn) begin + axi_if.arready <= '0; + rd_wait <= '0; + reg_rd_valid_o <= '0; + reg_rd_addr_o <= '0; + axi_if.rvalid <= '0; + axi_if.rresp <= '0; + axi_if.rdata <= '0; + end else begin + // Defaults + axi_if.arready <= '0; + rd_wait <= rd_wait; + reg_rd_valid_o <= '0; + reg_rd_addr_o <= '0; + axi_if.rvalid <= '0; + axi_if.rresp <= '0; + axi_if.rdata <= '0; + // coverage off -item c 1 -feccondrow 4 + if (!rd_wait && !axi_if.arready && axi_if.arvalid) begin + // coverage on + axi_if.arready <= 1'b1; + rd_wait <= 1'b1; + reg_rd_valid_o <= 1'b1; + reg_rd_addr_o <= axi_if.araddr; + end else if (reg_rd_done_i) begin + axi_if.rvalid <= 1'b1; + axi_if.rresp <= reg_rd_resp_i; + axi_if.rdata <= reg_rd_data_i; + end else if (axi_if.rvalid) begin + if (!axi_if.rready) begin + axi_if.rvalid <= axi_if.rvalid; + axi_if.rresp <= axi_if.rresp; + axi_if.rdata <= axi_if.rdata; + end else begin + rd_wait <= 1'b0; + end + end + end +end + +endmodule : cmd_queue_v2_0_0_axi_reg diff --git a/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_reg_if.sv b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_reg_if.sv new file mode 100644 index 00000000..dec51c56 --- /dev/null +++ b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_reg_if.sv @@ -0,0 +1,89 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +interface cmd_queue_v2_0_0_reg_if #( + parameter int C_DATA_WIDTH = 32, + parameter int C_ADDR_WIDTH = 32 +); + +// -------------------------------------------------------- +// Time Units/Precision +// -------------------------------------------------------- +// synthesis translate_off +timeunit 1ns/1ps; +// synthesis translate_on + +// -------------------------------------------------------- +// Register Read Interface +// -------------------------------------------------------- + +logic reg_rd_valid; +logic [C_ADDR_WIDTH-1:0] reg_rd_addr; +logic reg_rd_done; +logic [1:0] reg_rd_resp; +logic [C_DATA_WIDTH-1:0] reg_rd_data; + +// -------------------------------------------------------- +// Register Write Interface +// -------------------------------------------------------- + +logic reg_wr_valid; +logic [C_ADDR_WIDTH-1:0] reg_wr_addr; +logic [(C_DATA_WIDTH/8)-1:0] reg_wr_be; +logic [C_DATA_WIDTH-1:0] reg_wr_data; +logic reg_wr_done; +logic [1:0] reg_wr_resp; + +// -------------------------------------------------------- +// Register Manager Interface +// -------------------------------------------------------- +modport man ( + output reg_rd_valid, + output reg_rd_addr, + input reg_rd_done, + input reg_rd_resp, + input reg_rd_data, + output reg_wr_valid, + output reg_wr_addr, + output reg_wr_be, + output reg_wr_data, + input reg_wr_done, + input reg_wr_resp +); + +// -------------------------------------------------------- +// Register Subordinate Interface +// -------------------------------------------------------- +modport sub ( + input reg_rd_valid, + input reg_rd_addr, + output reg_rd_done, + output reg_rd_resp, + output reg_rd_data, + input reg_wr_valid, + input reg_wr_addr, + input reg_wr_be, + input reg_wr_data, + output reg_wr_done, + output reg_wr_resp +); + +endinterface : cmd_queue_v2_0_0_reg_if diff --git a/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_regs.sv b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_regs.sv new file mode 100644 index 00000000..bc94bdd8 --- /dev/null +++ b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_regs.sv @@ -0,0 +1,450 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +module cmd_queue_v2_0_0_regs +( + // Register Interface + cmd_queue_v2_0_0_reg_if.sub sq_reg_if, + cmd_queue_v2_0_0_reg_if.sub cq_reg_if, + + // Clock/Reset + input logic aclk, + input logic aresetn, + + // Interrupts + output logic irq_sq, + output logic irq_cq +); + +// -------------------------------------------------------- +// Time Units/Precision +// -------------------------------------------------------- +// synthesis translate_off +timeunit 1ns/1ps; +// synthesis translate_on + +// -------------------------------------------------------- +// Parameters +// -------------------------------------------------------- +localparam int C_SQ_ADDR_WIDTH = $bits(sq_reg_if.reg_wr_addr); +localparam int C_CQ_ADDR_WIDTH = $bits(cq_reg_if.reg_wr_addr); +localparam int IRQ_SR_WIDTH = 2; + +// -------------------------------------------------------- +// Types +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Functions +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Variables/Nets +// -------------------------------------------------------- + +logic [31:0] sq_tail_pntr; +logic sq_irq_tail_pntr; +logic sq_irq_tail_pntr_isr; +logic sq_irq_tail_pntr_clr; +logic sq_irq_reg; +logic sq_irq_reg_isr; +logic sq_irq_reg_clr; +logic sq_irq_en; +logic [IRQ_SR_WIDTH-1:0] sq_irq_en_sr; +logic sq_irq_type; +logic sq_rst; +logic [31:0] sq_mem_addr_lo; +logic [31:0] sq_mem_addr_hi; + +logic [31:0] cq_tail_pntr; +logic cq_irq_tail_pntr; +logic cq_irq_tail_pntr_isr; +logic cq_irq_tail_pntr_clr; +logic cq_irq_reg; +logic cq_irq_reg_isr; +logic cq_irq_reg_clr; +logic cq_irq_en; +logic [IRQ_SR_WIDTH-1:0] cq_irq_en_sr; +logic cq_irq_type; +logic cq_rst; +logic [31:0] cq_mem_addr_lo; +logic [31:0] cq_mem_addr_hi; + +logic soft_rst; + +// ======================================================== + +// Assert the soft reset when either SQ/CQ resets are set +assign soft_rst = sq_rst | cq_rst; + +// ======================================================== + +// Interrupt Generation +always_ff @(posedge aclk) begin + if (!aresetn) begin + irq_sq <= '0; + sq_irq_en_sr <= '0; + sq_irq_reg_isr <= '0; + sq_irq_tail_pntr_isr <= '0; + irq_cq <= '0; + cq_irq_en_sr <= '0; + cq_irq_reg_isr <= '0; + cq_irq_tail_pntr_isr <= '0; + end else begin + // Defaults + irq_sq <= '0; + sq_irq_en_sr <= {sq_irq_en_sr[IRQ_SR_WIDTH-2:0],1'b1}; + irq_cq <= '0; + cq_irq_en_sr <= {cq_irq_en_sr[IRQ_SR_WIDTH-2:0],1'b1}; + + // SQ Interrupt Generation + + // SQ Register Interrupt - Asserted when the Interrupt Register is written + + if ((sq_irq_reg_clr && sq_irq_type) || soft_rst) begin + // Clear the register interrupt when the interrupt status register is read or on a soft reset + sq_irq_reg_isr <= '0; + sq_irq_en_sr <= '0; + end + + if (sq_irq_type && sq_irq_reg) begin + // Assert the SQ register interrupt when the interrupt register is written + sq_irq_reg_isr <= '1; + end else if (!sq_irq_type) begin + // If the interrupt type is configured for the tail pointer, then clear any pending register + // interrupts that get asserted + sq_irq_reg_isr <= '0; + end + + // SQ Tail Pointer Interrupt - Asserted when the Tail Pointer register is written + + if ((sq_irq_tail_pntr_clr && !sq_irq_type) || soft_rst) begin + // Clear the register interrupt when the interrupt status register is read or on a soft reset + sq_irq_tail_pntr_isr <= '0; + sq_irq_en_sr <= '0; + end + + if (!sq_irq_type && sq_irq_tail_pntr) begin + // Assert the interrupt when the tail pointer register is written + sq_irq_tail_pntr_isr <= '1; + end else if (sq_irq_type) begin + // If the interrupt type is configured for register interrupt, then clear any pending tail + // pointer interrupts that get asserted + sq_irq_tail_pntr_isr <= '0; + end + + if (sq_irq_en) begin + // Assert the SQ interrupt output when enabled and either the register or tail pointer + // interrupts are set. The MSB of the shift register ensures that the interrupt de-asserts + // in the event of a coincident interrupt set/clear that would prevent a new rising-edge + irq_sq <= (sq_irq_reg_isr | sq_irq_tail_pntr_isr) & sq_irq_en_sr[IRQ_SR_WIDTH-1]; + end + + // ======================================================== + + // CQ Interrupt Generation + + // CQ Register Interrupt - Asserted when the Interrupt Register is written + + if ((cq_irq_reg_clr && cq_irq_type) || soft_rst) begin + // Clear the register interrupt when the interrupt status register is read or on a soft reset + cq_irq_reg_isr <= '0; + cq_irq_en_sr <= '0; + end + + if (cq_irq_type && cq_irq_reg) begin + // Assert the CQ register interrupt when the interrupt register is written + cq_irq_reg_isr <= '1; + end else if (!cq_irq_type) begin + // If the interrupt type is configured for the tail pointer, then clear any pending register + // interrupts that get asserted + cq_irq_reg_isr <= '0; + end + + // CQ Tail Pointer Interrupt - Asserted when the Tail Pointer register is written + + if ((cq_irq_tail_pntr_clr && !cq_irq_type) || soft_rst) begin + // Clear the register interrupt when the interrupt status register is read or on a soft reset + cq_irq_tail_pntr_isr <= '0; + cq_irq_en_sr <= '0; + end + + if (!cq_irq_type && cq_irq_tail_pntr) begin + // Assert the interrupt when the tail pointer register is written + cq_irq_tail_pntr_isr <= '1; + end else if (cq_irq_type) begin + // If the interrupt type is configured for register interrupt, then clear any pending tail + // pointer interrupts that get asserted + cq_irq_tail_pntr_isr <= '0; + end + + if (cq_irq_en) begin + // Assert the CQ interrupt output when enabled and either the register or tail pointer + // interrupts are set. The MSB of the shift register ensures that the interrupt de-asserts + // in the event of a coincident interrupt set/clear that would prevent a new rising-edge + irq_cq <= (cq_irq_reg_isr | cq_irq_tail_pntr_isr) & cq_irq_en_sr[IRQ_SR_WIDTH-1]; + end + end +end + +// ======================================================== + +// Producer Register Interface - Write +always_ff @(posedge aclk) begin + if (!aresetn) begin + sq_tail_pntr <= '0; + sq_irq_tail_pntr <= '0; + sq_irq_reg <= '0; + sq_irq_en <= '0; + sq_irq_type <= '0; + sq_mem_addr_hi <= '0; + sq_mem_addr_lo <= '0; + sq_rst <= '0; + sq_reg_if.reg_wr_done <= '0; + end else begin + // Defaults + sq_reg_if.reg_wr_done <= '0; + sq_rst <= '0; + sq_irq_tail_pntr <= '0; + sq_irq_reg <= '0; + + if (sq_reg_if.reg_wr_valid) begin + // Exclude unused address space to prevent aliasing + if (!(|sq_reg_if.reg_wr_addr[C_SQ_ADDR_WIDTH-1:9])) begin + case (sq_reg_if.reg_wr_addr[8:0]) inside + 9'b0000000??: // SQ Tail Pointer - 0x000 + begin + sq_tail_pntr <= sq_reg_if.reg_wr_data; + sq_irq_tail_pntr <= '1; + end + 9'b0000001??: // SQ IRQ Control - 0x004 + sq_irq_reg <= sq_reg_if.reg_wr_data[0]; + 9'b0000010??: // SQ Queue Memory Address Low - 0x008 + sq_mem_addr_lo <= sq_reg_if.reg_wr_data; + 9'b0000011??: // SQ Reset IRQ Control - 0x00C + begin + sq_irq_en <= sq_reg_if.reg_wr_data[0]; + sq_irq_type <= sq_reg_if.reg_wr_data[1]; + sq_rst <= sq_reg_if.reg_wr_data[31]; + end + 9'b0000100??: // SQ Queue Memory Address High - 0x010 + sq_mem_addr_hi <= sq_reg_if.reg_wr_data; + endcase + end + // Signal write done + sq_reg_if.reg_wr_done <= 1'b1; + end + + // Clear the registers on a soft reset + if (soft_rst) begin + sq_tail_pntr <= '0; + sq_irq_en <= '0; + sq_irq_type <= '0; + sq_mem_addr_hi <= '0; + sq_mem_addr_lo <= '0; + end + end +end + +// Always respond with OKAY to writes +assign sq_reg_if.reg_wr_resp = '0; + +// ======================================================== + +// Producer Register Interface - Read +always_ff @(posedge aclk) begin + //Defaults + sq_reg_if.reg_rd_data <= '0; + sq_reg_if.reg_rd_done <= '0; + cq_irq_reg_clr <= '0; + cq_irq_tail_pntr_clr <= '0; + + if (sq_reg_if.reg_rd_valid) begin + // Exclude unused address space to prevent aliasing + if (!(|sq_reg_if.reg_rd_addr[C_SQ_ADDR_WIDTH-1:9])) begin + case (sq_reg_if.reg_rd_addr[8:0]) inside + 9'b0000000??: // SQ Tail Pointer - 0x000 + sq_reg_if.reg_rd_data <= sq_tail_pntr; + 9'b0000001??: // SQ IRQ Control - 0x004 + sq_reg_if.reg_rd_data[1] <= sq_irq_reg_isr | sq_irq_tail_pntr_isr; + 9'b0000010??: // SQ Queue Memory Address Low - 0x008 + sq_reg_if.reg_rd_data <= sq_mem_addr_lo; + 9'b0000011??: // SQ Reset IRQ Control - 0x00C + begin + sq_reg_if.reg_rd_data[1] <= sq_irq_type; + sq_reg_if.reg_rd_data[0] <= sq_irq_en; + end + 9'b0000100??: // SQ Queue Memory Address High - 0x010 + sq_reg_if.reg_rd_data <= sq_mem_addr_hi; + 9'b1000000??: // CQ Tail Pointer - 0x100 + begin + sq_reg_if.reg_rd_data <= cq_tail_pntr; + cq_irq_tail_pntr_clr <= '1; + end + 9'b1000001??: // CQ IRQ Status - 0x104 + begin + sq_reg_if.reg_rd_data[0] <= cq_irq_reg_isr; + cq_irq_reg_clr <= '1; + end + 9'b1000010??: // CQ Queue Memory Address Low - 0x108 + sq_reg_if.reg_rd_data <= cq_mem_addr_lo; + 9'b1000011??: // CQ Reset IRQ Control - 0x10C + begin + sq_reg_if.reg_rd_data[1] <= cq_irq_type; + sq_reg_if.reg_rd_data[0] <= cq_irq_en; + end + 9'b1000100??: // CQ Queue Memory Address High - 0x110 + sq_reg_if.reg_rd_data <= cq_mem_addr_hi; + default: + sq_reg_if.reg_rd_data <= '0; + endcase + end + // Signal read done + sq_reg_if.reg_rd_done <= 1'b1; + end +end + +// Always respond with OKAY to reads +assign sq_reg_if.reg_rd_resp = '0; + +// ======================================================== + +// Consumer Register Interface - Write +always_ff @(posedge aclk) begin + if (!aresetn) begin + cq_tail_pntr <= '0; + cq_irq_tail_pntr <= '0; + cq_irq_reg <= '0; + cq_irq_en <= '0; + cq_irq_type <= '0; + cq_mem_addr_hi <= '0; + cq_mem_addr_lo <= '0; + cq_rst <= '0; + cq_reg_if.reg_wr_done <= '0; + end else begin + // Defaults + cq_reg_if.reg_wr_done <= '0; + cq_rst <= '0; + cq_irq_tail_pntr <= '0; + cq_irq_reg <= '0; + + if (cq_reg_if.reg_wr_valid) begin + // Exclude unused address space to prevent aliasing + if (!(|cq_reg_if.reg_wr_addr[C_CQ_ADDR_WIDTH-1:9])) begin + case (cq_reg_if.reg_wr_addr[8:0]) inside + 9'b0000000??: // CQ Tail Pointer - 0x000 + begin + cq_tail_pntr <= cq_reg_if.reg_wr_data; + cq_irq_tail_pntr <= '1; + end + 9'b0000001??: // CQ IRQ Control - 0x004 + cq_irq_reg <= cq_reg_if.reg_wr_data[0]; + 9'b0000010??: // CQ Queue Memory Address Low - 0x008 + cq_mem_addr_lo <= cq_reg_if.reg_wr_data; + 9'b0000011??: // CQ Reset IRQ Control - 0x00C + begin + cq_irq_en <= cq_reg_if.reg_wr_data[0]; + cq_irq_type <= cq_reg_if.reg_wr_data[1]; + cq_rst <= cq_reg_if.reg_wr_data[31]; + end + 9'b0000100??: // CQ Queue Memory Address High - 0x010 + cq_mem_addr_hi <= cq_reg_if.reg_wr_data; + endcase + end + // Signal write done + cq_reg_if.reg_wr_done <= 1'b1; + end + + // Clear the registers on a soft reset + if (soft_rst) begin + cq_tail_pntr <= '0; + cq_irq_en <= '0; + cq_irq_type <= '0; + cq_mem_addr_hi <= '0; + cq_mem_addr_lo <= '0; + end + end +end + +// Always respond with OKAY to writes +assign cq_reg_if.reg_wr_resp = '0; + +// ======================================================== + +// Consumer Register Interface - Read +always_ff @(posedge aclk) begin + //Defaults + cq_reg_if.reg_rd_data <= '0; + cq_reg_if.reg_rd_done <= '0; + sq_irq_reg_clr <= '0; + sq_irq_tail_pntr_clr <= '0; + + if (cq_reg_if.reg_rd_valid) begin + // Exclude unused address space to prevent aliasing + if (!(|cq_reg_if.reg_rd_addr[C_CQ_ADDR_WIDTH-1:9])) begin + case (cq_reg_if.reg_rd_addr[8:0]) inside + 9'b0000000??: // CQ Tail Pointer - 0x000 + cq_reg_if.reg_rd_data <= cq_tail_pntr; + 9'b0000001??: // CQ IRQ Control - 0x004 + cq_reg_if.reg_rd_data[1] <= cq_irq_reg_isr | cq_irq_tail_pntr_isr; + 9'b0000010??: // CQ Queue Memory Address Low - 0x008 + cq_reg_if.reg_rd_data <= cq_mem_addr_lo; + 9'b0000011??: // CQ Reset IRQ Control - 0x00C + begin + cq_reg_if.reg_rd_data[1] <= cq_irq_type; + cq_reg_if.reg_rd_data[0] <= cq_irq_en; + end + 9'b0000100??: // CQ Queue Memory Address High - 0x010 + cq_reg_if.reg_rd_data <= cq_mem_addr_hi; + 9'b1000000??: // SQ Tail Pointer - 0x100 + begin + cq_reg_if.reg_rd_data <= sq_tail_pntr; + sq_irq_tail_pntr_clr <= '1; + end + 9'b1000001??: // SQ IRQ Status - 0x104 + begin + cq_reg_if.reg_rd_data[0] <= sq_irq_reg_isr; + sq_irq_reg_clr <= '1; + end + 9'b1000010??: // SQ Queue Memory Address Low - 0x108 + cq_reg_if.reg_rd_data <= sq_mem_addr_lo; + 9'b1000011??: // SQ Reset IRQ Control - 0x10C + begin + cq_reg_if.reg_rd_data[1] <= sq_irq_type; + cq_reg_if.reg_rd_data[0] <= sq_irq_en; + end + 9'b1000100??: // SQ Queue Memory Address High - 0x110 + cq_reg_if.reg_rd_data <= sq_mem_addr_hi; + default: + cq_reg_if.reg_rd_data <= '0; + endcase + end + // Signal read done + cq_reg_if.reg_rd_done <= 1'b1; + end +end + +// Always respond with OKAY to reads +assign cq_reg_if.reg_rd_resp = '0; + +// ======================================================== + +endmodule : cmd_queue_v2_0_0_regs diff --git a/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_top.sv b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_top.sv new file mode 100644 index 00000000..4fe9481b --- /dev/null +++ b/linker/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_top.sv @@ -0,0 +1,181 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +module cmd_queue_v2_0_0_top #( + parameter int C_S00_ADDR_WIDTH = 12, + parameter int C_S01_ADDR_WIDTH = 12 +) ( + // Clock Ports + input logic aclk, + + // Reset Ports + input logic aresetn, + + // S00_AXI Interface Ports + input logic [C_S00_ADDR_WIDTH-1:0] s00_axi_awaddr, + input logic s00_axi_awvalid, + output logic s00_axi_awready, + input logic [32-1:0] s00_axi_wdata, + input logic [4-1:0] s00_axi_wstrb, + input logic s00_axi_wvalid, + output logic s00_axi_wready, + output logic [2-1:0] s00_axi_bresp, + output logic s00_axi_bvalid, + input logic s00_axi_bready, + input logic [C_S00_ADDR_WIDTH-1:0] s00_axi_araddr, + input logic s00_axi_arvalid, + output logic s00_axi_arready, + output logic [32-1:0] s00_axi_rdata, + output logic [2-1:0] s00_axi_rresp, + output logic s00_axi_rvalid, + input logic s00_axi_rready, + + // S01_AXI Interface Ports + input logic [C_S01_ADDR_WIDTH-1:0] s01_axi_awaddr, + input logic s01_axi_awvalid, + output logic s01_axi_awready, + input logic [32-1:0] s01_axi_wdata, + input logic [4-1:0] s01_axi_wstrb, + input logic s01_axi_wvalid, + output logic s01_axi_wready, + output logic [2-1:0] s01_axi_bresp, + output logic s01_axi_bvalid, + input logic s01_axi_bready, + input logic [C_S01_ADDR_WIDTH-1:0] s01_axi_araddr, + input logic s01_axi_arvalid, + output logic s01_axi_arready, + output logic [32-1:0] s01_axi_rdata, + output logic [2-1:0] s01_axi_rresp, + output logic s01_axi_rvalid, + input logic s01_axi_rready, + + // Interrupt Ports + output logic irq_sq, + output logic irq_cq +); + +// -------------------------------------------------------- +// Time Units/Precision +// -------------------------------------------------------- +// synthesis translate_off +timeunit 1ns/1ps; +// synthesis translate_on + +// -------------------------------------------------------- +// Package Import +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Parameters +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Types +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Functions +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Variables/Nets +// -------------------------------------------------------- + +// ======================================================== + +// AXI4-Lite Interface Instantiations +cmd_queue_v2_0_0_axi_if #(.C_ADDR_WIDTH(C_S00_ADDR_WIDTH)) sq_axi_if(); +cmd_queue_v2_0_0_axi_if #(.C_ADDR_WIDTH(C_S01_ADDR_WIDTH)) cq_axi_if(); + +// Producer (SQ) AXI-Lite Interface/port connections +assign sq_axi_if.awaddr = s00_axi_awaddr; +assign sq_axi_if.awvalid = s00_axi_awvalid; +assign s00_axi_awready = sq_axi_if.awready; +assign sq_axi_if.wdata = s00_axi_wdata; +assign sq_axi_if.wstrb = s00_axi_wstrb; +assign sq_axi_if.wvalid = s00_axi_wvalid; +assign s00_axi_wready = sq_axi_if.wready; +assign s00_axi_bresp = sq_axi_if.bresp; +assign s00_axi_bvalid = sq_axi_if.bvalid; +assign sq_axi_if.bready = s00_axi_bready; +assign sq_axi_if.araddr = s00_axi_araddr; +assign sq_axi_if.arvalid = s00_axi_arvalid; +assign s00_axi_arready = sq_axi_if.arready; +assign s00_axi_rdata = sq_axi_if.rdata; +assign s00_axi_rresp = sq_axi_if.rresp; +assign s00_axi_rvalid = sq_axi_if.rvalid; +assign sq_axi_if.rready = s00_axi_rready; + +// Consumer (CQ) AXI-Lite Interface/port connections +assign cq_axi_if.awaddr = s01_axi_awaddr; +assign cq_axi_if.awvalid = s01_axi_awvalid; +assign s01_axi_awready = cq_axi_if.awready; +assign cq_axi_if.wdata = s01_axi_wdata; +assign cq_axi_if.wstrb = s01_axi_wstrb; +assign cq_axi_if.wvalid = s01_axi_wvalid; +assign s01_axi_wready = cq_axi_if.wready; +assign s01_axi_bresp = cq_axi_if.bresp; +assign s01_axi_bvalid = cq_axi_if.bvalid; +assign cq_axi_if.bready = s01_axi_bready; +assign cq_axi_if.araddr = s01_axi_araddr; +assign cq_axi_if.arvalid = s01_axi_arvalid; +assign s01_axi_arready = cq_axi_if.arready; +assign s01_axi_rdata = cq_axi_if.rdata; +assign s01_axi_rresp = cq_axi_if.rresp; +assign s01_axi_rvalid = cq_axi_if.rvalid; +assign cq_axi_if.rready = s01_axi_rready; + +// ======================================================== + +// Register Interface Instantiations +cmd_queue_v2_0_0_reg_if #(.C_ADDR_WIDTH(C_S00_ADDR_WIDTH)) sq_reg_if(); +cmd_queue_v2_0_0_reg_if #(.C_ADDR_WIDTH(C_S01_ADDR_WIDTH)) cq_reg_if(); + +// ======================================================== + +// AXI Module Instantiation +cmd_queue_v2_0_0_axi #( + .C_S00_ADDR_WIDTH(C_S00_ADDR_WIDTH), + .C_S01_ADDR_WIDTH(C_S01_ADDR_WIDTH) +) axi_inst ( + .sq_axi_if, + .cq_axi_if, + .sq_reg_if, + .cq_reg_if, + .aclk, + .aresetn +); + +// ======================================================== + +// Command Queue Registers Module Instantiation +cmd_queue_v2_0_0_regs top_reg_inst ( + .sq_reg_if, + .cq_reg_if, + .aclk, + .aresetn, + .irq_sq, + .irq_cq +); + +// ======================================================== + +endmodule : cmd_queue_v2_0_0_top \ No newline at end of file diff --git a/linker/resources/base/iprepo/cmd_queue_v2_0/xgui/cmd_queue_v2_0.tcl b/linker/resources/base/iprepo/cmd_queue_v2_0/xgui/cmd_queue_v2_0.tcl new file mode 100644 index 00000000..84782a49 --- /dev/null +++ b/linker/resources/base/iprepo/cmd_queue_v2_0/xgui/cmd_queue_v2_0.tcl @@ -0,0 +1,26 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + +} diff --git a/linker/resources/base/iprepo/hbm_bandwidth/Makefile b/linker/resources/base/iprepo/hbm_bandwidth/Makefile new file mode 100644 index 00000000..fa370aea --- /dev/null +++ b/linker/resources/base/iprepo/hbm_bandwidth/Makefile @@ -0,0 +1,34 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +TARGET=ip +DEVICE=xcv80-lsva4737-2MHP-e-S + +HBM_BANDWIDTH_BUILD_DIR=build_hbm_bandwidth.$(DEVICE) + +all: $(HBM_BANDWIDTH_BUILD_DIR) + +$(HBM_BANDWIDTH_BUILD_DIR): + if [ ! -d "$(HBM_BANDWIDTH_BUILD_DIR)" ]; then \ + vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) hbm_bandwidth; \ + fi + +clean: + rm -rf $(HBM_BANDWIDTH_BUILD_DIR) \ No newline at end of file diff --git a/linker/resources/base/iprepo/hbm_bandwidth/build.tcl b/linker/resources/base/iprepo/hbm_bandwidth/build.tcl new file mode 100644 index 00000000..f1dd0e00 --- /dev/null +++ b/linker/resources/base/iprepo/hbm_bandwidth/build.tcl @@ -0,0 +1,79 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set command [lindex $argv 0] +set device [lindex $argv 1] +set ipname [lindex $argv 2] + +set do_sim 0 +set do_syn 0 +set do_export 0 +set do_cosim 0 + +switch $command { + "sim" { + set do_sim 1 + } + "syn" { + set do_syn 1 + } + "ip" { + set do_syn 1 + set do_export 1 + } + "cosim" { + set do_syn 1 + set do_cosim 1 + } + "all" { + set do_sim 1 + set do_syn 1 + set do_export 1 + set do_cosim 1 + } + default { + puts "Unrecognized command" + exit + } +} + + +open_project build_${ipname}.${device} + +file copy -force $ipname.cpp build_${ipname}.${device}/$ipname.cpp +add_files $ipname.cpp -cflags "-std=c++14" + +set_top $ipname + +open_solution sol1 + +if {$do_syn} { + set_part $device + create_clock -period 4 -name default + config_interface -m_axi_addr64=true + csynth_design +} + +if {$do_export} { + config_export -format ip_catalog + export_design +} + +exit diff --git a/linker/resources/base/iprepo/hbm_bandwidth/hbm_bandwidth.cpp b/linker/resources/base/iprepo/hbm_bandwidth/hbm_bandwidth.cpp new file mode 100644 index 00000000..7177cf9d --- /dev/null +++ b/linker/resources/base/iprepo/hbm_bandwidth/hbm_bandwidth.cpp @@ -0,0 +1,20 @@ +#include +#include + +#define DATA_WIDTH 256 +typedef ap_uint uint256_t; +#define LENGTH 0x1000000 + +extern "C" void hbm_bandwidth( + uint256_t* hbm_ptr // HBM memory-mapped pointer +) { +#pragma HLS INTERFACE m_axi port=hbm_ptr offset=slave bundle=gmem0 max_read_burst_length=64 max_write_burst_length=64 depth=536870912 +#pragma HLS INTERFACE s_axilite port=hbm_ptr bundle=control +#pragma HLS INTERFACE s_axilite port=return bundle=control + + for (uint32_t i = 0; i < LENGTH; i++) { + #pragma HLS PIPELINE II=1 + hbm_ptr[i] = i; + } +} + diff --git a/linker/resources/base/iprepo/hls/Makefile b/linker/resources/base/iprepo/hls/Makefile new file mode 100644 index 00000000..c6c72c4f --- /dev/null +++ b/linker/resources/base/iprepo/hls/Makefile @@ -0,0 +1,40 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +TARGET=ip +DEVICE=xcv80-lsva4737-2MHP-e-S + +DMA_BUILD_DIR=build_dma.$(DEVICE) +OFFSET_BUILD_DIR=build_offset.$(DEVICE) + +all: $(DMA_BUILD_DIR) $(OFFSET_BUILD_DIR) + +$(DMA_BUILD_DIR): + if [ ! -d "$(DMA_BUILD_DIR)" ]; then \ + vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) dma; \ + fi + +$(OFFSET_BUILD_DIR): + if [ ! -d "$(OFFSET_BUILD_DIR)" ]; then \ + vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) offset; \ + fi + +clean: + rm -rf $(DMA_BUILD_DIR) $(OFFSET_BUILD_DIR) vitis_hls.log \ No newline at end of file diff --git a/linker/resources/base/iprepo/hls/build.tcl b/linker/resources/base/iprepo/hls/build.tcl new file mode 100644 index 00000000..6b32d0a6 --- /dev/null +++ b/linker/resources/base/iprepo/hls/build.tcl @@ -0,0 +1,78 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set command [lindex $argv 0] +set device [lindex $argv 1] +set ipname [lindex $argv 2] + +set do_sim 0 +set do_syn 0 +set do_export 0 +set do_cosim 0 + +switch $command { + "sim" { + set do_sim 1 + } + "syn" { + set do_syn 1 + } + "ip" { + set do_syn 1 + set do_export 1 + } + "cosim" { + set do_syn 1 + set do_cosim 1 + } + "all" { + set do_sim 1 + set do_syn 1 + set do_export 1 + set do_cosim 1 + } + default { + puts "Unrecognized command" + exit + } +} + + +open_project build_${ipname}.${device} +file copy -force $ipname.cpp build_${ipname}.${device}/$ipname.cpp +add_files $ipname.cpp -cflags "-std=c++14" + +set_top $ipname + +open_solution sol1 + +if {$do_syn} { + set_part $device + create_clock -period 4 -name default + config_interface -m_axi_addr64=true + csynth_design +} + +if {$do_export} { + config_export -format ip_catalog + export_design +} + +exit \ No newline at end of file diff --git a/linker/resources/base/iprepo/hls/dma.cpp b/linker/resources/base/iprepo/hls/dma.cpp new file mode 100644 index 00000000..f8434dbc --- /dev/null +++ b/linker/resources/base/iprepo/hls/dma.cpp @@ -0,0 +1,36 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +void dma(ap_uint<32> size, hls::stream>& axis_in, ap_uint<32>* out) { +#pragma hls interface mode=s_axilite port=size +#pragma hls interface mode=axis port=axis_in +#pragma hls interface m_axi bundle=gmem0 port=out max_widen_bitwidth=64 +#pragma hls interface mode=s_axilite port=return + + for(ap_uint<32> i = 0; i < size; i++) { + #pragma HLS pipeline II=1 + ap_uint<32> val; + axis_in.read(val); + out[i] = val; + } +} \ No newline at end of file diff --git a/linker/resources/base/iprepo/hls/offset.cpp b/linker/resources/base/iprepo/hls/offset.cpp new file mode 100644 index 00000000..330155f6 --- /dev/null +++ b/linker/resources/base/iprepo/hls/offset.cpp @@ -0,0 +1,38 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +void offset(ap_uint<32> size, ap_uint<32>* input, hls::stream >& axis_out, ap_uint<32> m, ap_uint<32> n) { +#pragma hls interface mode=s_axilite port=size +#pragma hls interface m_axi bundle=gmem0 port=input max_widen_bitwidth=64 +#pragma hls interface axis port=axis_out +#pragma hls interface mode=s_axilite port=m +#pragma hls interface mode=s_axilite port=n +#pragma hls interface mode=s_axilite port=return + + for(ap_uint<32> i = 0; i < size; i++) { +#pragma HLS PIPELINE II=1 + ap_uint<32> val = input[i]; + val = val * m + n; + axis_out.write(val); + } +} diff --git a/linker/resources/base/iprepo/hw_discovery_v1_0/bd/bd.tcl b/linker/resources/base/iprepo/hw_discovery_v1_0/bd/bd.tcl new file mode 100644 index 00000000..362e33a5 --- /dev/null +++ b/linker/resources/base/iprepo/hw_discovery_v1_0/bd/bd.tcl @@ -0,0 +1,201 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +proc post_config_ip {cellpath otherInfo } { +} + +proc pre_propagate {cellpath undefined_params} { + set props [list \ + C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE C_PF0_BAR_INDEX C_PF0_HIGH_OFFSET C_PF0_LOW_OFFSET \ + C_PF0_ENTRY_TYPE_0 C_PF0_ENTRY_TYPE_1 C_PF0_ENTRY_TYPE_2 C_PF0_ENTRY_TYPE_3 C_PF0_ENTRY_TYPE_4 C_PF0_ENTRY_TYPE_5 C_PF0_ENTRY_TYPE_6 C_PF0_ENTRY_TYPE_7 C_PF0_ENTRY_TYPE_8 C_PF0_ENTRY_TYPE_9 C_PF0_ENTRY_TYPE_10 C_PF0_ENTRY_TYPE_11 C_PF0_ENTRY_TYPE_12 C_PF0_ENTRY_TYPE_13 \ + C_PF0_ENTRY_BAR_0 C_PF0_ENTRY_BAR_1 C_PF0_ENTRY_BAR_2 C_PF0_ENTRY_BAR_3 C_PF0_ENTRY_BAR_4 C_PF0_ENTRY_BAR_5 C_PF0_ENTRY_BAR_6 C_PF0_ENTRY_BAR_7 C_PF0_ENTRY_BAR_8 C_PF0_ENTRY_BAR_9 C_PF0_ENTRY_BAR_10 C_PF0_ENTRY_BAR_11 C_PF0_ENTRY_BAR_12 C_PF0_ENTRY_BAR_13 \ + C_PF0_ENTRY_ADDR_0 C_PF0_ENTRY_ADDR_1 C_PF0_ENTRY_ADDR_2 C_PF0_ENTRY_ADDR_3 C_PF0_ENTRY_ADDR_4 C_PF0_ENTRY_ADDR_5 C_PF0_ENTRY_ADDR_6 C_PF0_ENTRY_ADDR_7 C_PF0_ENTRY_ADDR_8 C_PF0_ENTRY_ADDR_9 C_PF0_ENTRY_ADDR_10 C_PF0_ENTRY_ADDR_11 C_PF0_ENTRY_ADDR_12 C_PF0_ENTRY_ADDR_13 \ + C_PF0_ENTRY_VERSION_TYPE_0 C_PF0_ENTRY_VERSION_TYPE_1 C_PF0_ENTRY_VERSION_TYPE_2 C_PF0_ENTRY_VERSION_TYPE_3 C_PF0_ENTRY_VERSION_TYPE_4 C_PF0_ENTRY_VERSION_TYPE_5 C_PF0_ENTRY_VERSION_TYPE_6 C_PF0_ENTRY_VERSION_TYPE_7 C_PF0_ENTRY_VERSION_TYPE_8 C_PF0_ENTRY_VERSION_TYPE_9 C_PF0_ENTRY_VERSION_TYPE_10 C_PF0_ENTRY_VERSION_TYPE_11 C_PF0_ENTRY_VERSION_TYPE_12 C_PF0_ENTRY_VERSION_TYPE_13 \ + C_PF0_ENTRY_MAJOR_VERSION_0 C_PF0_ENTRY_MAJOR_VERSION_1 C_PF0_ENTRY_MAJOR_VERSION_2 C_PF0_ENTRY_MAJOR_VERSION_3 C_PF0_ENTRY_MAJOR_VERSION_4 C_PF0_ENTRY_MAJOR_VERSION_5 C_PF0_ENTRY_MAJOR_VERSION_6 C_PF0_ENTRY_MAJOR_VERSION_7 C_PF0_ENTRY_MAJOR_VERSION_8 C_PF0_ENTRY_MAJOR_VERSION_9 C_PF0_ENTRY_MAJOR_VERSION_10 C_PF0_ENTRY_MAJOR_VERSION_11 C_PF0_ENTRY_MAJOR_VERSION_12 C_PF0_ENTRY_MAJOR_VERSION_13 \ + C_PF0_ENTRY_MINOR_VERSION_0 C_PF0_ENTRY_MINOR_VERSION_1 C_PF0_ENTRY_MINOR_VERSION_2 C_PF0_ENTRY_MINOR_VERSION_3 C_PF0_ENTRY_MINOR_VERSION_4 C_PF0_ENTRY_MINOR_VERSION_5 C_PF0_ENTRY_MINOR_VERSION_6 C_PF0_ENTRY_MINOR_VERSION_7 C_PF0_ENTRY_MINOR_VERSION_8 C_PF0_ENTRY_MINOR_VERSION_9 C_PF0_ENTRY_MINOR_VERSION_10 C_PF0_ENTRY_MINOR_VERSION_11 C_PF0_ENTRY_MINOR_VERSION_12 C_PF0_ENTRY_MINOR_VERSION_13 \ + C_PF0_ENTRY_RSVD0_0 C_PF0_ENTRY_RSVD0_1 C_PF0_ENTRY_RSVD0_2 C_PF0_ENTRY_RSVD0_3 C_PF0_ENTRY_RSVD0_4 C_PF0_ENTRY_RSVD0_5 C_PF0_ENTRY_RSVD0_6 C_PF0_ENTRY_RSVD0_7 C_PF0_ENTRY_RSVD0_8 C_PF0_ENTRY_RSVD0_9 C_PF0_ENTRY_RSVD0_10 C_PF0_ENTRY_RSVD0_11 C_PF0_ENTRY_RSVD0_12 C_PF0_ENTRY_RSVD0_13 \ + C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE C_PF1_BAR_INDEX C_PF1_HIGH_OFFSET C_PF1_LOW_OFFSET \ + C_PF1_ENTRY_TYPE_0 C_PF1_ENTRY_TYPE_1 C_PF1_ENTRY_TYPE_2 C_PF1_ENTRY_TYPE_3 C_PF1_ENTRY_TYPE_4 C_PF1_ENTRY_TYPE_5 C_PF1_ENTRY_TYPE_6 C_PF1_ENTRY_TYPE_7 C_PF1_ENTRY_TYPE_8 C_PF1_ENTRY_TYPE_9 C_PF1_ENTRY_TYPE_10 C_PF1_ENTRY_TYPE_11 C_PF1_ENTRY_TYPE_12 C_PF1_ENTRY_TYPE_13 \ + C_PF1_ENTRY_BAR_0 C_PF1_ENTRY_BAR_1 C_PF1_ENTRY_BAR_2 C_PF1_ENTRY_BAR_3 C_PF1_ENTRY_BAR_4 C_PF1_ENTRY_BAR_5 C_PF1_ENTRY_BAR_6 C_PF1_ENTRY_BAR_7 C_PF1_ENTRY_BAR_8 C_PF1_ENTRY_BAR_9 C_PF1_ENTRY_BAR_10 C_PF1_ENTRY_BAR_11 C_PF1_ENTRY_BAR_12 C_PF1_ENTRY_BAR_13 \ + C_PF1_ENTRY_ADDR_0 C_PF1_ENTRY_ADDR_1 C_PF1_ENTRY_ADDR_2 C_PF1_ENTRY_ADDR_3 C_PF1_ENTRY_ADDR_4 C_PF1_ENTRY_ADDR_5 C_PF1_ENTRY_ADDR_6 C_PF1_ENTRY_ADDR_7 C_PF1_ENTRY_ADDR_8 C_PF1_ENTRY_ADDR_9 C_PF1_ENTRY_ADDR_10 C_PF1_ENTRY_ADDR_11 C_PF1_ENTRY_ADDR_12 C_PF1_ENTRY_ADDR_13 \ + C_PF1_ENTRY_VERSION_TYPE_0 C_PF1_ENTRY_VERSION_TYPE_1 C_PF1_ENTRY_VERSION_TYPE_2 C_PF1_ENTRY_VERSION_TYPE_3 C_PF1_ENTRY_VERSION_TYPE_4 C_PF1_ENTRY_VERSION_TYPE_5 C_PF1_ENTRY_VERSION_TYPE_6 C_PF1_ENTRY_VERSION_TYPE_7 C_PF1_ENTRY_VERSION_TYPE_8 C_PF1_ENTRY_VERSION_TYPE_9 C_PF1_ENTRY_VERSION_TYPE_10 C_PF1_ENTRY_VERSION_TYPE_11 C_PF1_ENTRY_VERSION_TYPE_12 C_PF1_ENTRY_VERSION_TYPE_13 \ + C_PF1_ENTRY_MAJOR_VERSION_0 C_PF1_ENTRY_MAJOR_VERSION_1 C_PF1_ENTRY_MAJOR_VERSION_2 C_PF1_ENTRY_MAJOR_VERSION_3 C_PF1_ENTRY_MAJOR_VERSION_4 C_PF1_ENTRY_MAJOR_VERSION_5 C_PF1_ENTRY_MAJOR_VERSION_6 C_PF1_ENTRY_MAJOR_VERSION_7 C_PF1_ENTRY_MAJOR_VERSION_8 C_PF1_ENTRY_MAJOR_VERSION_9 C_PF1_ENTRY_MAJOR_VERSION_10 C_PF1_ENTRY_MAJOR_VERSION_11 C_PF1_ENTRY_MAJOR_VERSION_12 C_PF1_ENTRY_MAJOR_VERSION_13 \ + C_PF1_ENTRY_MINOR_VERSION_0 C_PF1_ENTRY_MINOR_VERSION_1 C_PF1_ENTRY_MINOR_VERSION_2 C_PF1_ENTRY_MINOR_VERSION_3 C_PF1_ENTRY_MINOR_VERSION_4 C_PF1_ENTRY_MINOR_VERSION_5 C_PF1_ENTRY_MINOR_VERSION_6 C_PF1_ENTRY_MINOR_VERSION_7 C_PF1_ENTRY_MINOR_VERSION_8 C_PF1_ENTRY_MINOR_VERSION_9 C_PF1_ENTRY_MINOR_VERSION_10 C_PF1_ENTRY_MINOR_VERSION_11 C_PF1_ENTRY_MINOR_VERSION_12 C_PF1_ENTRY_MINOR_VERSION_13 \ + C_PF1_ENTRY_RSVD0_0 C_PF1_ENTRY_RSVD0_1 C_PF1_ENTRY_RSVD0_2 C_PF1_ENTRY_RSVD0_3 C_PF1_ENTRY_RSVD0_4 C_PF1_ENTRY_RSVD0_5 C_PF1_ENTRY_RSVD0_6 C_PF1_ENTRY_RSVD0_7 C_PF1_ENTRY_RSVD0_8 C_PF1_ENTRY_RSVD0_9 C_PF1_ENTRY_RSVD0_10 C_PF1_ENTRY_RSVD0_11 C_PF1_ENTRY_RSVD0_12 C_PF1_ENTRY_RSVD0_13 \ + C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE C_PF2_BAR_INDEX C_PF2_HIGH_OFFSET C_PF2_LOW_OFFSET \ + C_PF2_ENTRY_TYPE_0 C_PF2_ENTRY_TYPE_1 C_PF2_ENTRY_TYPE_2 C_PF2_ENTRY_TYPE_3 C_PF2_ENTRY_TYPE_4 C_PF2_ENTRY_TYPE_5 C_PF2_ENTRY_TYPE_6 C_PF2_ENTRY_TYPE_7 C_PF2_ENTRY_TYPE_8 C_PF2_ENTRY_TYPE_9 C_PF2_ENTRY_TYPE_10 C_PF2_ENTRY_TYPE_11 C_PF2_ENTRY_TYPE_12 C_PF2_ENTRY_TYPE_13 \ + C_PF2_ENTRY_BAR_0 C_PF2_ENTRY_BAR_1 C_PF2_ENTRY_BAR_2 C_PF2_ENTRY_BAR_3 C_PF2_ENTRY_BAR_4 C_PF2_ENTRY_BAR_5 C_PF2_ENTRY_BAR_6 C_PF2_ENTRY_BAR_7 C_PF2_ENTRY_BAR_8 C_PF2_ENTRY_BAR_9 C_PF2_ENTRY_BAR_10 C_PF2_ENTRY_BAR_11 C_PF2_ENTRY_BAR_12 C_PF2_ENTRY_BAR_13 \ + C_PF2_ENTRY_ADDR_0 C_PF2_ENTRY_ADDR_1 C_PF2_ENTRY_ADDR_2 C_PF2_ENTRY_ADDR_3 C_PF2_ENTRY_ADDR_4 C_PF2_ENTRY_ADDR_5 C_PF2_ENTRY_ADDR_6 C_PF2_ENTRY_ADDR_7 C_PF2_ENTRY_ADDR_8 C_PF2_ENTRY_ADDR_9 C_PF2_ENTRY_ADDR_10 C_PF2_ENTRY_ADDR_11 C_PF2_ENTRY_ADDR_12 C_PF2_ENTRY_ADDR_13 \ + C_PF2_ENTRY_VERSION_TYPE_0 C_PF2_ENTRY_VERSION_TYPE_1 C_PF2_ENTRY_VERSION_TYPE_2 C_PF2_ENTRY_VERSION_TYPE_3 C_PF2_ENTRY_VERSION_TYPE_4 C_PF2_ENTRY_VERSION_TYPE_5 C_PF2_ENTRY_VERSION_TYPE_6 C_PF2_ENTRY_VERSION_TYPE_7 C_PF2_ENTRY_VERSION_TYPE_8 C_PF2_ENTRY_VERSION_TYPE_9 C_PF2_ENTRY_VERSION_TYPE_10 C_PF2_ENTRY_VERSION_TYPE_11 C_PF2_ENTRY_VERSION_TYPE_12 C_PF2_ENTRY_VERSION_TYPE_13 \ + C_PF2_ENTRY_MAJOR_VERSION_0 C_PF2_ENTRY_MAJOR_VERSION_1 C_PF2_ENTRY_MAJOR_VERSION_2 C_PF2_ENTRY_MAJOR_VERSION_3 C_PF2_ENTRY_MAJOR_VERSION_4 C_PF2_ENTRY_MAJOR_VERSION_5 C_PF2_ENTRY_MAJOR_VERSION_6 C_PF2_ENTRY_MAJOR_VERSION_7 C_PF2_ENTRY_MAJOR_VERSION_8 C_PF2_ENTRY_MAJOR_VERSION_9 C_PF2_ENTRY_MAJOR_VERSION_10 C_PF2_ENTRY_MAJOR_VERSION_11 C_PF2_ENTRY_MAJOR_VERSION_12 C_PF2_ENTRY_MAJOR_VERSION_13 \ + C_PF2_ENTRY_MINOR_VERSION_0 C_PF2_ENTRY_MINOR_VERSION_1 C_PF2_ENTRY_MINOR_VERSION_2 C_PF2_ENTRY_MINOR_VERSION_3 C_PF2_ENTRY_MINOR_VERSION_4 C_PF2_ENTRY_MINOR_VERSION_5 C_PF2_ENTRY_MINOR_VERSION_6 C_PF2_ENTRY_MINOR_VERSION_7 C_PF2_ENTRY_MINOR_VERSION_8 C_PF2_ENTRY_MINOR_VERSION_9 C_PF2_ENTRY_MINOR_VERSION_10 C_PF2_ENTRY_MINOR_VERSION_11 C_PF2_ENTRY_MINOR_VERSION_12 C_PF2_ENTRY_MINOR_VERSION_13 \ + C_PF2_ENTRY_RSVD0_0 C_PF2_ENTRY_RSVD0_1 C_PF2_ENTRY_RSVD0_2 C_PF2_ENTRY_RSVD0_3 C_PF2_ENTRY_RSVD0_4 C_PF2_ENTRY_RSVD0_5 C_PF2_ENTRY_RSVD0_6 C_PF2_ENTRY_RSVD0_7 C_PF2_ENTRY_RSVD0_8 C_PF2_ENTRY_RSVD0_9 C_PF2_ENTRY_RSVD0_10 C_PF2_ENTRY_RSVD0_11 C_PF2_ENTRY_RSVD0_12 C_PF2_ENTRY_RSVD0_13 \ + C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE C_PF3_BAR_INDEX C_PF3_HIGH_OFFSET C_PF3_LOW_OFFSET \ + C_PF3_ENTRY_TYPE_0 C_PF3_ENTRY_TYPE_1 C_PF3_ENTRY_TYPE_2 C_PF3_ENTRY_TYPE_3 C_PF3_ENTRY_TYPE_4 C_PF3_ENTRY_TYPE_5 C_PF3_ENTRY_TYPE_6 C_PF3_ENTRY_TYPE_7 C_PF3_ENTRY_TYPE_8 C_PF3_ENTRY_TYPE_9 C_PF3_ENTRY_TYPE_10 C_PF3_ENTRY_TYPE_11 C_PF3_ENTRY_TYPE_12 C_PF3_ENTRY_TYPE_13 \ + C_PF3_ENTRY_BAR_0 C_PF3_ENTRY_BAR_1 C_PF3_ENTRY_BAR_2 C_PF3_ENTRY_BAR_3 C_PF3_ENTRY_BAR_4 C_PF3_ENTRY_BAR_5 C_PF3_ENTRY_BAR_6 C_PF3_ENTRY_BAR_7 C_PF3_ENTRY_BAR_8 C_PF3_ENTRY_BAR_9 C_PF3_ENTRY_BAR_10 C_PF3_ENTRY_BAR_11 C_PF3_ENTRY_BAR_12 C_PF3_ENTRY_BAR_13 \ + C_PF3_ENTRY_ADDR_0 C_PF3_ENTRY_ADDR_1 C_PF3_ENTRY_ADDR_2 C_PF3_ENTRY_ADDR_3 C_PF3_ENTRY_ADDR_4 C_PF3_ENTRY_ADDR_5 C_PF3_ENTRY_ADDR_6 C_PF3_ENTRY_ADDR_7 C_PF3_ENTRY_ADDR_8 C_PF3_ENTRY_ADDR_9 C_PF3_ENTRY_ADDR_10 C_PF3_ENTRY_ADDR_11 C_PF3_ENTRY_ADDR_12 C_PF3_ENTRY_ADDR_13 \ + C_PF3_ENTRY_VERSION_TYPE_0 C_PF3_ENTRY_VERSION_TYPE_1 C_PF3_ENTRY_VERSION_TYPE_2 C_PF3_ENTRY_VERSION_TYPE_3 C_PF3_ENTRY_VERSION_TYPE_4 C_PF3_ENTRY_VERSION_TYPE_5 C_PF3_ENTRY_VERSION_TYPE_6 C_PF3_ENTRY_VERSION_TYPE_7 C_PF3_ENTRY_VERSION_TYPE_8 C_PF3_ENTRY_VERSION_TYPE_9 C_PF3_ENTRY_VERSION_TYPE_10 C_PF3_ENTRY_VERSION_TYPE_11 C_PF3_ENTRY_VERSION_TYPE_12 C_PF3_ENTRY_VERSION_TYPE_13 \ + C_PF3_ENTRY_MAJOR_VERSION_0 C_PF3_ENTRY_MAJOR_VERSION_1 C_PF3_ENTRY_MAJOR_VERSION_2 C_PF3_ENTRY_MAJOR_VERSION_3 C_PF3_ENTRY_MAJOR_VERSION_4 C_PF3_ENTRY_MAJOR_VERSION_5 C_PF3_ENTRY_MAJOR_VERSION_6 C_PF3_ENTRY_MAJOR_VERSION_7 C_PF3_ENTRY_MAJOR_VERSION_8 C_PF3_ENTRY_MAJOR_VERSION_9 C_PF3_ENTRY_MAJOR_VERSION_10 C_PF3_ENTRY_MAJOR_VERSION_11 C_PF3_ENTRY_MAJOR_VERSION_12 C_PF3_ENTRY_MAJOR_VERSION_13 \ + C_PF3_ENTRY_MINOR_VERSION_0 C_PF3_ENTRY_MINOR_VERSION_1 C_PF3_ENTRY_MINOR_VERSION_2 C_PF3_ENTRY_MINOR_VERSION_3 C_PF3_ENTRY_MINOR_VERSION_4 C_PF3_ENTRY_MINOR_VERSION_5 C_PF3_ENTRY_MINOR_VERSION_6 C_PF3_ENTRY_MINOR_VERSION_7 C_PF3_ENTRY_MINOR_VERSION_8 C_PF3_ENTRY_MINOR_VERSION_9 C_PF3_ENTRY_MINOR_VERSION_10 C_PF3_ENTRY_MINOR_VERSION_11 C_PF3_ENTRY_MINOR_VERSION_12 C_PF3_ENTRY_MINOR_VERSION_13 \ + C_PF3_ENTRY_RSVD0_0 C_PF3_ENTRY_RSVD0_1 C_PF3_ENTRY_RSVD0_2 C_PF3_ENTRY_RSVD0_3 C_PF3_ENTRY_RSVD0_4 C_PF3_ENTRY_RSVD0_5 C_PF3_ENTRY_RSVD0_6 C_PF3_ENTRY_RSVD0_7 C_PF3_ENTRY_RSVD0_8 C_PF3_ENTRY_RSVD0_9 C_PF3_ENTRY_RSVD0_10 C_PF3_ENTRY_RSVD0_11 C_PF3_ENTRY_RSVD0_12 C_PF3_ENTRY_RSVD0_13] + set cell [get_bd_cells $cellpath] + puts "\[VSEC-BAR\] Cell: ${cellpath}" + if {[get_property CONFIG.C_MANUAL $cell] == 0} { + set dflt [dict create] + foreach p $props { + dict set dflt CONFIG.${p}.VALUE_SRC DEFAULT + } + set_property -dict $dflt $cell + + if {[llength [get_property CONFIG.C_INJECT_ENDPOINTS $cell]] > 1} { + set inject 1 + puts "\[VSEC-BAR\] ${cell} : Injecting PCIE Mapping Info from C_INJECT_ENDPOINTS" + } elseif {([llength [namespace which vitis::get_pcie_mapping_for]] == 0 || [llength [namespace which vitis::get_endpoints_for_pcie_bar]] == 0)} { + error "\[VSEC-BAR\] Cell ${cell} is configured for auto configuration, but necessary procedures to auto configure are not present." + return + } else { + set inject 0 + puts "\[VSEC-BAR\] ${cell} is being automatically configured." + } + } else { + puts "\[VSEC-BAR\] ${cell} is manually configured, and is skipping automatic configuration." + return + } + + set prop_vals [dict create] + set num_pfs [get_property CONFIG.C_NUM_PFS [get_bd_cells $cellpath]] + puts "\[VSEC-BAR\] ${cell} : Number of PFs = ${num_pfs}" + + if {$inject == 0} { + if {[llength [vitis::get_pcie_mapping_info]] > 0} { + puts "\[VSEC-BAR\] ${cell} : Getting PCIE Mapping Info" + foreach {pcie_info} [vitis::get_pcie_mapping_info] { + set pf [dict get $pcie_info physical_function] + set bar [dict get $pcie_info bar] + puts "\[VSEC-BAR\] ${cell} : Physical Function = ${pf}" + puts "\[VSEC-BAR\] ${cell} : BAR = ${bar}" + foreach {endpoint} [vitis::get_endpoints_for_pcie_bar $pf $bar "ALL"] { + puts "\[VSEC-BAR\] ${cell} : Endpoint = ${endpoint}" + set bar_cell [bd::utils::get_parent [dict get $endpoint intf]] + if {[string match "xilinx.com:ip:hw_discovery:*" [get_property VLNV $bar_cell]]} { + set bar_high_addr [format 0x%08X [expr [dict get $endpoint offset] >> 32]] + set bar_low_addr [format 0x%07X [expr ([dict get $endpoint offset] & 0xFFFFFFFF) / 16]] + dict set prop_vals CONFIG.C_PF${pf}_BAR_INDEX $bar + dict set prop_vals CONFIG.C_PF${pf}_HIGH_OFFSET $bar_high_addr + dict set prop_vals CONFIG.C_PF${pf}_LOW_OFFSET $bar_low_addr + puts "\[VSEC\] Setting $cell bar reference to [dict get $endpoint intf], @ high $bar_high_addr, low $bar_low_addr" + } + } + } + } else { + error "\[VSEC-BAR\] ${cell} : No PCIE Mapping Info found" + } + } else { + set pcie_mapping_info [dict get [get_property CONFIG.C_INJECT_ENDPOINTS $cell] pcie_mapping_info] + foreach {pcie_info} ${pcie_mapping_info} { + puts "\[VSEC-BAR\] ${cell} : PCIE Info: $pcie_info" + set pf [dict get $pcie_info physical_function] + set bar [dict get $pcie_info bar] + puts "\[VSEC-BAR\] ${cell} : Physical Function = ${pf}" + puts "\[VSEC-BAR\] ${cell} : BAR = ${bar}" + set endpoints_for_pcie_bar [dict get [get_property CONFIG.C_INJECT_ENDPOINTS $cell] endpoints_for_pcie_bar $pf $bar] + foreach {endpoint} ${endpoints_for_pcie_bar} { + puts "\[VSEC-BAR\] ${cell} : Endpoint = ${endpoint}" + set bar_cell [bd::utils::get_parent [dict get $endpoint intf]] + if {[llength $bar_cell] > 0} { + if {[string match "xilinx.com:ip:hw_discovery:*" [get_property VLNV $bar_cell]]} { + set bar_high_addr [format 0x%08X [expr [dict get ${endpoint} offset] >> 32]] + set bar_low_addr [format 0x%07X [expr ([dict get ${endpoint} offset] & 0xFFFFFFFF) / 16]] + dict set prop_vals CONFIG.C_PF${pf}_BAR_INDEX $bar + dict set prop_vals CONFIG.C_PF${pf}_HIGH_OFFSET $bar_high_addr + dict set prop_vals CONFIG.C_PF${pf}_LOW_OFFSET $bar_low_addr + puts "\[VSEC\] Setting $cell bar reference to [dict get ${endpoint} intf], @ high $bar_high_addr, low $bar_low_addr" + } + } + } + } + } + + for {set i 0} {$i < $num_pfs} {incr i } { + set bar_info [list] + if {$inject == 0} { + puts "\[VSEC-BAR\] ${cell} : Getting PCIe Mapping Info for ${cell}/s_axi_ctrl_pf${i}" + set bar_info [vitis::get_pcie_mapping_for [get_bd_intf_pins $cell/s_axi_ctrl_pf${i}]] + } else { + puts "\[VSEC-BAR\] ${cell} : Injecting PCIe Mapping Info for ${cell}/s_axi_ctrl_pf${i}" + if {[dict exist [get_property CONFIG.C_INJECT_ENDPOINTS $cell] pcie_mapping_for [get_bd_intf_pins $cell/s_axi_ctrl_pf${i}]]} { + set bar_info [dict get [get_property CONFIG.C_INJECT_ENDPOINTS $cell] pcie_mapping_for [get_bd_intf_pins $cell/s_axi_ctrl_pf${i}]] + } + } + + if {[llength $bar_info] == 0} { + error "\[VSEC-BAR\] ${cell} Could not find a PCIe mapped BAR address" + return + } + set first_bar [lindex $bar_info 0] + set pf [dict get $first_bar physical_function] + set bar [dict get $first_bar bar] + set ep_filter [get_property CONFIG.C_PF${pf}_ENDPOINT_NAMES $cell] + if {[llength [dict keys $ep_filter]] == 0} { + error "\[VSEC-BAR\] ${cell} Unrecognized BAR layout for Physical Function $pf" + } else { + puts "\[VSEC-BAR\] ${cell} Setting BAR layout for Physical Function $pf" + } + set index 0 + dict set prop_vals CONFIG.C_PF${pf}_NUM_SLOTS_BAR_LAYOUT_TABLE $index + if {$inject == 0} { + set endpoints [vitis::get_endpoints_for_pcie_bar $pf $bar] + } else { + set endpoints [dict get [get_property CONFIG.C_INJECT_ENDPOINTS $cell] endpoints_for_pcie_bar $pf $bar] + } + foreach {pcie_peer} ${endpoints} { + puts "\[VSEC-BAR\] ${cell} : PCIe Peer = ${pcie_peer}" + if {[dict exists $ep_filter [dict get $pcie_peer xrt_endpoint_name]]} { + set vlnv_list [split [dict get $pcie_peer reg_abs] ":"] + set vlnv_version_list [split [lindex $vlnv_list 3] "."] + set ep_info [dict get $ep_filter [dict get $pcie_peer xrt_endpoint_name]] + dict unset ep_filter [dict get $pcie_peer xrt_endpoint_name] + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_ADDR_${index} [format 0x%012X [dict get $pcie_peer offset]] + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_BAR_${index} $bar + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_MAJOR_VERSION_${index} [lindex $vlnv_version_list 0] + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_MINOR_VERSION_${index} [lindex $vlnv_version_list 1] + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_TYPE_${index} [dict get $ep_info type] + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_RSVD0_${index} [dict get $ep_info reserve] + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_VERSION_TYPE_${index} 0x1 + + puts "\[VSEC-BAR\] Adding record to ${cell} for [dict get $pcie_peer xrt_endpoint_name] for endpoint [dict get $pcie_peer intf] at address [format 0x%012X [dict get $pcie_peer offset]]" + incr index + dict set prop_vals CONFIG.C_PF${pf}_NUM_SLOTS_BAR_LAYOUT_TABLE $index + } + } + set err 0 + foreach {ep x} ${ep_filter} { + puts "\[VSEC-BAR\] Expected to find ${ep} on physical function ${pf} bar ${bar}, but failed to find any such endpoint" + set err 1 + } + if {$err == 1} { + error "\[VSEC-BAR\] Aborting BAR layout table configuration due to being malformed" + return + } + } + puts "\[VSEC-BAR\] Configuring $cell with $prop_vals" + set_property -dict $prop_vals $cell +} diff --git a/linker/resources/base/iprepo/hw_discovery_v1_0/component.xml b/linker/resources/base/iprepo/hw_discovery_v1_0/component.xml new file mode 100644 index 00000000..c57fc84e --- /dev/null +++ b/linker/resources/base/iprepo/hw_discovery_v1_0/component.xml @@ -0,0 +1,13406 @@ + + + xilinx.com + ip + hw_discovery + 1.0 + + + s_pcie4_cfg_ext + + + + + + + function_number + + + s_pcie4_cfg_ext_function_number + + + + + read_data + + + s_pcie4_cfg_ext_read_data + + + + + read_data_valid + + + s_pcie4_cfg_ext_read_data_valid + + + + + read_received + + + s_pcie4_cfg_ext_read_received + + + + + register_number + + + s_pcie4_cfg_ext_register_number + + + + + write_byte_enable + + + s_pcie4_cfg_ext_write_byte_enable + + + + + write_data + + + s_pcie4_cfg_ext_write_data + + + + + write_received + + + s_pcie4_cfg_ext_write_received + + + + + + m_pcie4_cfg_ext + + + + + + + function_number + + + m_pcie4_cfg_ext_function_number + + + + + read_data + + + m_pcie4_cfg_ext_read_data + + + + + read_data_valid + + + m_pcie4_cfg_ext_read_data_valid + + + + + read_received + + + m_pcie4_cfg_ext_read_received + + + + + register_number + + + m_pcie4_cfg_ext_register_number + + + + + write_byte_enable + + + m_pcie4_cfg_ext_write_byte_enable + + + + + write_data + + + m_pcie4_cfg_ext_write_data + + + + + write_received + + + m_pcie4_cfg_ext_write_received + + + + + + + false + + + + + + s_axi_ctrl_pf0 + + + + + + + + + ARADDR + + + s_axi_ctrl_pf0_araddr + + + + + ARREADY + + + s_axi_ctrl_pf0_arready + + + + + ARVALID + + + s_axi_ctrl_pf0_arvalid + + + + + AWADDR + + + s_axi_ctrl_pf0_awaddr + + + + + AWREADY + + + s_axi_ctrl_pf0_awready + + + + + AWVALID + + + s_axi_ctrl_pf0_awvalid + + + + + BREADY + + + s_axi_ctrl_pf0_bready + + + + + BRESP + + + s_axi_ctrl_pf0_bresp + + + + + BVALID + + + s_axi_ctrl_pf0_bvalid + + + + + RDATA + + + s_axi_ctrl_pf0_rdata + + + + + RREADY + + + s_axi_ctrl_pf0_rready + + + + + RRESP + + + s_axi_ctrl_pf0_rresp + + + + + RVALID + + + s_axi_ctrl_pf0_rvalid + + + + + WDATA + + + s_axi_ctrl_pf0_wdata + + + + + WREADY + + + s_axi_ctrl_pf0_wready + + + + + WSTRB + + + s_axi_ctrl_pf0_wstrb + + + + + WVALID + + + s_axi_ctrl_pf0_wvalid + + + + + + s_axi_ctrl_pf1 + + + + + + + + + ARADDR + + + s_axi_ctrl_pf1_araddr + + + + + ARREADY + + + s_axi_ctrl_pf1_arready + + + + + ARVALID + + + s_axi_ctrl_pf1_arvalid + + + + + AWADDR + + + s_axi_ctrl_pf1_awaddr + + + + + AWREADY + + + s_axi_ctrl_pf1_awready + + + + + AWVALID + + + s_axi_ctrl_pf1_awvalid + + + + + BREADY + + + s_axi_ctrl_pf1_bready + + + + + BRESP + + + s_axi_ctrl_pf1_bresp + + + + + BVALID + + + s_axi_ctrl_pf1_bvalid + + + + + RDATA + + + s_axi_ctrl_pf1_rdata + + + + + RREADY + + + s_axi_ctrl_pf1_rready + + + + + RRESP + + + s_axi_ctrl_pf1_rresp + + + + + RVALID + + + s_axi_ctrl_pf1_rvalid + + + + + WDATA + + + s_axi_ctrl_pf1_wdata + + + + + WREADY + + + s_axi_ctrl_pf1_wready + + + + + WSTRB + + + s_axi_ctrl_pf1_wstrb + + + + + WVALID + + + s_axi_ctrl_pf1_wvalid + + + + + + + false + + + + + + s_axi_ctrl_pf2 + + + + + + + + + ARADDR + + + s_axi_ctrl_pf2_araddr + + + + + ARREADY + + + s_axi_ctrl_pf2_arready + + + + + ARVALID + + + s_axi_ctrl_pf2_arvalid + + + + + AWADDR + + + s_axi_ctrl_pf2_awaddr + + + + + AWREADY + + + s_axi_ctrl_pf2_awready + + + + + AWVALID + + + s_axi_ctrl_pf2_awvalid + + + + + BREADY + + + s_axi_ctrl_pf2_bready + + + + + BRESP + + + s_axi_ctrl_pf2_bresp + + + + + BVALID + + + s_axi_ctrl_pf2_bvalid + + + + + RDATA + + + s_axi_ctrl_pf2_rdata + + + + + RREADY + + + s_axi_ctrl_pf2_rready + + + + + RRESP + + + s_axi_ctrl_pf2_rresp + + + + + RVALID + + + s_axi_ctrl_pf2_rvalid + + + + + WDATA + + + s_axi_ctrl_pf2_wdata + + + + + WREADY + + + s_axi_ctrl_pf2_wready + + + + + WSTRB + + + s_axi_ctrl_pf2_wstrb + + + + + WVALID + + + s_axi_ctrl_pf2_wvalid + + + + + + + false + + + + + + s_axi_ctrl_pf3 + + + + + + + + + ARADDR + + + s_axi_ctrl_pf3_araddr + + + + + ARREADY + + + s_axi_ctrl_pf3_arready + + + + + ARVALID + + + s_axi_ctrl_pf3_arvalid + + + + + AWADDR + + + s_axi_ctrl_pf3_awaddr + + + + + AWREADY + + + s_axi_ctrl_pf3_awready + + + + + AWVALID + + + s_axi_ctrl_pf3_awvalid + + + + + BREADY + + + s_axi_ctrl_pf3_bready + + + + + BRESP + + + s_axi_ctrl_pf3_bresp + + + + + BVALID + + + s_axi_ctrl_pf3_bvalid + + + + + RDATA + + + s_axi_ctrl_pf3_rdata + + + + + RREADY + + + s_axi_ctrl_pf3_rready + + + + + RRESP + + + s_axi_ctrl_pf3_rresp + + + + + RVALID + + + s_axi_ctrl_pf3_rvalid + + + + + WDATA + + + s_axi_ctrl_pf3_wdata + + + + + WREADY + + + s_axi_ctrl_pf3_wready + + + + + WSTRB + + + s_axi_ctrl_pf3_wstrb + + + + + WVALID + + + s_axi_ctrl_pf3_wvalid + + + + + + + false + + + + + + aresetn_pcie + + + + + + + RST + + + aresetn_pcie + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk_pcie + + + + + + + CLK + + + aclk_pcie + + + + + + ASSOCIATED_BUSIF + s_pcie4_cfg_ext:m_pcie4_cfg_ext + + + ASSOCIATED_RESET + aresetn_pcie + + + FREQ_HZ + aclk_pcie frequency + aclk_pcie frequency + 250000000 + + + + + aresetn_ctrl + + + + + + + RST + + + aresetn_ctrl + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk_ctrl + + + + + + + CLK + + + aclk_ctrl + + + + + + ASSOCIATED_BUSIF + s_axi_ctrl_pf0:s_axi_ctrl_pf1:s_axi_ctrl_pf2:s_axi_ctrl_pf3 + + + ASSOCIATED_RESET + aresetn_ctrl + + + FREQ_HZ + S_AXI_ACLK frequency + S_AXI_ACLK frequency + 250000000 + + + + + + + s_axi_ctrl_pf0 + BAR Layout Table for PF0 + + reg0 + 0 + 4294967296 + 32 + register + read-only + + Header Reg0 + 0x00 + 1 + read-only + + HEADER_RESERVED + 29 + 3 + read-only + + 0 + 0 + + false + + + HEADER_LAST_CAP + 28 + 1 + read-only + + 0 + 0 + + false + + + HEADER_REV + 20 + 8 + read-only + + 0 + 0 + + false + + + HEADER_FORMAT + 0 + 20 + read-only + + 0 + 0 + + false + + + + Header Reg1 + 0x04 + 1 + read-only + + HEADER_LENGTH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Header Reg2 + 0x08 + 1 + read-only + + FORMAT_ENTRY_SIZE + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot00 Reg0 + 0x10 + 1 + read-only + + C_ENTRY_ADDR_00_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_00 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_00 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot00 Reg1 + 0x14 + 1 + read-only + + C_ENTRY_ADDR_00_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot00 Reg2 + 0x18 + 1 + read-only + + C_ENTRY_RSVD0_00 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_00 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_00 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_00 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot01 Reg0 + 0x20 + 1 + read-only + + C_ENTRY_ADDR_01_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_01 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_01 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot01 Reg1 + 0x24 + 1 + read-only + + C_ENTRY_ADDR_01_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot01 Reg2 + 0x28 + 1 + read-only + + C_ENTRY_RSVD0_01 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_01 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_01 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_01 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot02 Reg0 + 0x30 + 1 + read-only + + C_ENTRY_ADDR_02_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_02 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_02 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot02 Reg1 + 0x34 + 1 + read-only + + C_ENTRY_ADDR_02_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot02 Reg2 + 0x38 + 1 + read-only + + C_ENTRY_RSVD0_02 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_02 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_02 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_02 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot03 Reg0 + 0x40 + 1 + read-only + + C_ENTRY_ADDR_03_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_03 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_03 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot03 Reg1 + 0x44 + 1 + read-only + + C_ENTRY_ADDR_03_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot03 Reg2 + 0x48 + 1 + read-only + + C_ENTRY_RSVD0_03 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_03 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_03 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_03 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot04 Reg0 + 0x50 + 1 + read-only + + C_ENTRY_ADDR_04_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_04 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_04 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot04 Reg1 + 0x54 + 1 + read-only + + C_ENTRY_ADDR_04_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot04 Reg2 + 0x58 + 1 + read-only + + C_ENTRY_RSVD0_04 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_04 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_04 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_04 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot05 Reg0 + 0x60 + 1 + read-only + + C_ENTRY_ADDR_05_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_05 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_05 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot05 Reg1 + 0x64 + 1 + read-only + + C_ENTRY_ADDR_05_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot05 Reg2 + 0x68 + 1 + read-only + + C_ENTRY_RSVD0_05 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_05 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_05 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_05 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot06 Reg0 + 0x70 + 1 + read-only + + C_ENTRY_ADDR_06_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_06 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_06 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot06 Reg1 + 0x74 + 1 + read-only + + C_ENTRY_ADDR_06_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot06 Reg2 + 0x78 + 1 + read-only + + C_ENTRY_RSVD0_06 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_06 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_06 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_06 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot07 Reg0 + 0x80 + 1 + read-only + + C_ENTRY_ADDR_07_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_07 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_07 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot07 Reg1 + 0x84 + 1 + read-only + + C_ENTRY_ADDR_07_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot07 Reg2 + 0x88 + 1 + read-only + + C_ENTRY_RSVD0_07 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_07 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_07 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_07 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot08 Reg0 + 0x90 + 1 + read-only + + C_ENTRY_ADDR_08_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_08 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_08 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot08 Reg1 + 0x94 + 1 + read-only + + C_ENTRY_ADDR_08_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot08 Reg2 + 0x98 + 1 + read-only + + C_ENTRY_RSVD0_08 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_08 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_08 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_08 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot09 Reg0 + 0xA0 + 1 + read-only + + C_ENTRY_ADDR_09_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_09 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_09 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot09 Reg1 + 0xA4 + 1 + read-only + + C_ENTRY_ADDR_09_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot09 Reg2 + 0xA8 + 1 + read-only + + C_ENTRY_RSVD0_09 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_09 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_09 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_09 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot10 Reg0 + 0xB0 + 1 + read-only + + C_ENTRY_ADDR_10_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_10 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_10 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot10 Reg1 + 0xB4 + 1 + read-only + + C_ENTRY_ADDR_10_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot10 Reg2 + 0xB8 + 1 + read-only + + C_ENTRY_RSVD0_10 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_10 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_10 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_10 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot11 Reg0 + 0xC0 + 1 + read-only + + C_ENTRY_ADDR_11_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_11 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_11 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot11 Reg1 + 0xC4 + 1 + read-only + + C_ENTRY_ADDR_11_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot11 Reg2 + 0xC8 + 1 + read-only + + C_ENTRY_RSVD0_11 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_11 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_11 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_11 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot12 Reg0 + 0xD0 + 1 + read-only + + C_ENTRY_ADDR_12_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_12 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_12 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot12 Reg1 + 0xD4 + 1 + read-only + + C_ENTRY_ADDR_12_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot12 Reg2 + 0xD8 + 1 + read-only + + C_ENTRY_RSVD0_12 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_12 + 16 + 8 + read-only + + 0 + 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Entry 9 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_10 + PF1 Table Entry 10 Type + 0x00 + + + C_PF1_ENTRY_BAR_10 + PF1 Table Entry 10 BAR + 0 + + + C_PF1_ENTRY_ADDR_10 + PF1 Table Entry 10 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_10 + PF1 Table Entry 10 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_10 + PF1 Table Entry 10 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_10 + PF1 Table Entry 10 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_10 + PF1 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_11 + PF1 Table Entry 11 Type + 0x00 + + + C_PF1_ENTRY_BAR_11 + PF1 Table Entry 11 BAR + 0 + + + C_PF1_ENTRY_ADDR_11 + PF1 Table Entry 11 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_11 + PF1 Table Entry 11 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_11 + PF1 Table Entry 11 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_11 + PF1 Table Entry 11 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_11 + PF1 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_12 + PF1 Table Entry 12 Type + 0x00 + + + C_PF1_ENTRY_BAR_12 + PF1 Table Entry 12 BAR + 0 + + + C_PF1_ENTRY_ADDR_12 + PF1 Table Entry 12 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_12 + PF1 Table Entry 12 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_12 + PF1 Table Entry 12 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_12 + PF1 Table Entry 12 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_12 + PF1 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_13 + PF1 Table Entry 13 Type + 0x00 + + + C_PF1_ENTRY_BAR_13 + PF1 Table Entry 13 BAR + 0 + + + C_PF1_ENTRY_ADDR_13 + PF1 Table Entry 13 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_13 + PF1 Table Entry 13 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_13 + PF1 Table Entry 13 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_13 + PF1 Table Entry 13 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_13 + PF1 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF1_S_AXI_ADDR_WIDTH + PF1 AXI Interface Address Width + 32 + + + + false + + + + + + C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF2 + 1 + + + C_PF2_BAR_INDEX + PF2 BAR Index + 0 + + + C_PF2_LOW_OFFSET + PF2 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF2_HIGH_OFFSET + PF2 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF2_ENTRY_TYPE_0 + PF2 Table Entry 0 Type + 0x00 + + + C_PF2_ENTRY_BAR_0 + PF2 Table Entry 0 BAR + 0 + + + C_PF2_ENTRY_ADDR_0 + PF2 Table Entry 0 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_0 + PF2 Table Entry 0 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_0 + PF2 Table Entry 0 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_0 + PF2 Table Entry 0 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_0 + PF2 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_1 + PF2 Table Entry 1 Type + 0x00 + + + C_PF2_ENTRY_BAR_1 + PF2 Table Entry 1 BAR + 0 + + + C_PF2_ENTRY_ADDR_1 + PF2 Table Entry 1 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_1 + PF2 Table Entry 1 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_1 + PF2 Table Entry 1 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_1 + PF2 Table Entry 1 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_1 + PF2 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_2 + PF2 Table Entry 2 Type + 0x00 + + + C_PF2_ENTRY_BAR_2 + PF2 Table Entry 2 BAR + 0 + + + C_PF2_ENTRY_ADDR_2 + PF2 Table Entry 2 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_2 + PF2 Table Entry 2 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_2 + PF2 Table Entry 2 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_2 + PF2 Table Entry 2 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_2 + PF2 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_3 + PF2 Table Entry 3 Type + 0x00 + + + C_PF2_ENTRY_BAR_3 + PF2 Table Entry 3 BAR + 0 + + + C_PF2_ENTRY_ADDR_3 + PF2 Table Entry 3 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_3 + PF2 Table Entry 3 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_3 + PF2 Table Entry 3 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_3 + PF2 Table Entry 3 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_3 + PF2 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_4 + PF2 Table Entry 4 Type + 0x00 + + + C_PF2_ENTRY_BAR_4 + PF2 Table Entry 4 BAR + 0 + + + C_PF2_ENTRY_ADDR_4 + PF2 Table Entry 4 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_4 + PF2 Table Entry 4 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_4 + PF2 Table Entry 4 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_4 + PF2 Table Entry 4 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_5 + PF2 Table Entry 5 Type + 0x00 + + + C_PF2_ENTRY_BAR_5 + PF2 Table Entry 5 BAR + 0 + + + C_PF2_ENTRY_ADDR_5 + PF2 Table Entry 5 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_5 + PF2 Table Entry 5 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_5 + PF2 Table Entry 5 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_5 + PF2 Table Entry 5 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_5 + PF2 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_6 + PF2 Table Entry 6 Type + 0x00 + + + C_PF2_ENTRY_BAR_6 + PF2 Table Entry 6 BAR + 0 + + + C_PF2_ENTRY_ADDR_6 + PF2 Table Entry 6 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_6 + PF2 Table Entry 6 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_6 + PF2 Table Entry 6 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_6 + PF2 Table Entry 6 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_6 + PF2 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_7 + PF2 Table Entry 7 Type + 0x00 + + + C_PF2_ENTRY_BAR_7 + PF2 Table Entry 7 BAR + 0 + + + C_PF2_ENTRY_ADDR_7 + PF2 Table Entry 7 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_7 + PF2 Table Entry 7 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_7 + PF2 Table Entry 7 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_7 + PF2 Table Entry 7 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_7 + PF2 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_8 + PF2 Table Entry 8 Type + 0x00 + + + C_PF2_ENTRY_BAR_8 + PF2 Table Entry 8 BAR + 0 + + + C_PF2_ENTRY_ADDR_8 + PF2 Table Entry 8 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_8 + PF2 Table Entry 8 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_8 + PF2 Table Entry 8 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_8 + PF2 Table Entry 8 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_8 + PF2 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_9 + PF2 Table Entry 9 Type + 0x00 + + + C_PF2_ENTRY_BAR_9 + PF2 Table Entry 9 BAR + 0 + + + C_PF2_ENTRY_ADDR_9 + PF2 Table Entry 9 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_9 + PF2 Table Entry 9 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_9 + PF2 Table Entry 9 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_9 + PF2 Table Entry 9 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_9 + PF2 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_10 + PF2 Table Entry 10 Type + 0x00 + + + C_PF2_ENTRY_BAR_10 + PF2 Table Entry 10 BAR + 0 + + + C_PF2_ENTRY_ADDR_10 + PF2 Table Entry 10 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_10 + PF2 Table Entry 10 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_10 + PF2 Table Entry 10 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_10 + PF2 Table Entry 10 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_10 + PF2 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_11 + PF2 Table Entry 11 Type + 0x00 + + + C_PF2_ENTRY_BAR_11 + PF2 Table Entry 11 BAR + 0 + + + C_PF2_ENTRY_ADDR_11 + PF2 Table Entry 11 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_11 + PF2 Table Entry 11 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_11 + PF2 Table Entry 11 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_11 + PF2 Table Entry 11 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_11 + PF2 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_12 + PF2 Table Entry 12 Type + 0x00 + + + C_PF2_ENTRY_BAR_12 + PF2 Table Entry 12 BAR + 0 + + + C_PF2_ENTRY_ADDR_12 + PF2 Table Entry 12 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_12 + PF2 Table Entry 12 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_12 + PF2 Table Entry 12 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_12 + PF2 Table Entry 12 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_12 + PF2 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_13 + PF2 Table Entry 13 Type + 0x00 + + + C_PF2_ENTRY_BAR_13 + PF2 Table Entry 13 BAR + 0 + + + C_PF2_ENTRY_ADDR_13 + PF2 Table Entry 13 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_13 + PF2 Table Entry 13 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_13 + PF2 Table Entry 13 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_13 + PF2 Table Entry 13 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_13 + PF2 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF2_S_AXI_ADDR_WIDTH + PF2 AXI Interface Address Width + 32 + + + + false + + + + + + C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF3 + 1 + + + C_PF3_BAR_INDEX + PF3 BAR Index + 0 + + + C_PF3_LOW_OFFSET + PF3 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF3_HIGH_OFFSET + PF3 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF3_ENTRY_TYPE_0 + PF3 Table Entry 0 Type + 0x00 + + + C_PF3_ENTRY_BAR_0 + PF3 Table Entry 0 BAR + 0 + + + C_PF3_ENTRY_ADDR_0 + PF3 Table Entry 0 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_0 + PF3 Table Entry 0 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_0 + PF3 Table Entry 0 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_0 + PF3 Table Entry 0 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_0 + PF3 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_1 + PF3 Table Entry 1 Type + 0x00 + + + C_PF3_ENTRY_BAR_1 + PF3 Table Entry 1 BAR + 0 + + + C_PF3_ENTRY_ADDR_1 + PF3 Table Entry 1 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_1 + PF3 Table Entry 1 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_1 + PF3 Table Entry 1 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_1 + PF3 Table Entry 1 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_1 + PF3 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_2 + PF3 Table Entry 2 Type + 0x00 + + + C_PF3_ENTRY_BAR_2 + PF3 Table Entry 2 BAR + 0 + + + C_PF3_ENTRY_ADDR_2 + PF3 Table Entry 2 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_2 + PF3 Table Entry 2 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_2 + PF3 Table Entry 2 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_2 + PF3 Table Entry 2 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_2 + PF3 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_3 + PF3 Table Entry 3 Type + 0x00 + + + C_PF3_ENTRY_BAR_3 + PF3 Table Entry 3 BAR + 0 + + + C_PF3_ENTRY_ADDR_3 + PF3 Table Entry 3 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_3 + PF3 Table Entry 3 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_3 + PF3 Table Entry 3 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_3 + PF3 Table Entry 3 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_3 + PF3 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_4 + PF3 Table Entry 4 Type + 0x00 + + + C_PF3_ENTRY_BAR_4 + PF3 Table Entry 4 BAR + 0 + + + C_PF3_ENTRY_ADDR_4 + PF3 Table Entry 4 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_4 + PF3 Table Entry 4 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_4 + PF3 Table Entry 4 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_4 + PF3 Table Entry 4 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_5 + PF3 Table Entry 5 Type + 0x00 + + + C_PF3_ENTRY_BAR_5 + PF3 Table Entry 5 BAR + 0 + + + C_PF3_ENTRY_ADDR_5 + PF3 Table Entry 5 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_5 + PF3 Table Entry 5 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_5 + PF3 Table Entry 5 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_5 + PF3 Table Entry 5 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_5 + PF3 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_6 + PF3 Table Entry 6 Type + 0x00 + + + C_PF3_ENTRY_BAR_6 + PF3 Table Entry 6 BAR + 0 + + + C_PF3_ENTRY_ADDR_6 + PF3 Table Entry 6 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_6 + PF3 Table Entry 6 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_6 + PF3 Table Entry 6 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_6 + PF3 Table Entry 6 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_6 + PF3 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_7 + PF3 Table Entry 7 Type + 0x00 + + + C_PF3_ENTRY_BAR_7 + PF3 Table Entry 7 BAR + 0 + + + C_PF3_ENTRY_ADDR_7 + PF3 Table Entry 7 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_7 + PF3 Table Entry 7 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_7 + PF3 Table Entry 7 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_7 + PF3 Table Entry 7 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_7 + PF3 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_8 + PF3 Table Entry 8 Type + 0x00 + + + C_PF3_ENTRY_BAR_8 + PF3 Table Entry 8 BAR + 0 + + + C_PF3_ENTRY_ADDR_8 + PF3 Table Entry 8 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_8 + PF3 Table Entry 8 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_8 + PF3 Table Entry 8 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_8 + PF3 Table Entry 8 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_8 + PF3 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_9 + PF3 Table Entry 9 Type + 0x00 + + + C_PF3_ENTRY_BAR_9 + PF3 Table Entry 9 BAR + 0 + + + C_PF3_ENTRY_ADDR_9 + PF3 Table Entry 9 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_9 + PF3 Table Entry 9 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_9 + PF3 Table Entry 9 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_9 + PF3 Table Entry 9 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_9 + PF3 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_10 + PF3 Table Entry 10 Type + 0x00 + + + C_PF3_ENTRY_BAR_10 + PF3 Table Entry 10 BAR + 0 + + + C_PF3_ENTRY_ADDR_10 + PF3 Table Entry 10 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_10 + PF3 Table Entry 10 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_10 + PF3 Table Entry 10 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_10 + PF3 Table Entry 10 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_10 + PF3 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_11 + PF3 Table Entry 11 Type + 0x00 + + + C_PF3_ENTRY_BAR_11 + PF3 Table Entry 11 BAR + 0 + + + C_PF3_ENTRY_ADDR_11 + PF3 Table Entry 11 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_11 + PF3 Table Entry 11 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_11 + PF3 Table Entry 11 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_11 + PF3 Table Entry 11 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_11 + PF3 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_12 + PF3 Table Entry 12 Type + 0x00 + + + C_PF3_ENTRY_BAR_12 + PF3 Table Entry 12 BAR + 0 + + + C_PF3_ENTRY_ADDR_12 + PF3 Table Entry 12 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_12 + PF3 Table Entry 12 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_12 + PF3 Table Entry 12 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_12 + PF3 Table Entry 12 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_12 + PF3 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_13 + PF3 Table Entry 13 Type + 0x00 + + + C_PF3_ENTRY_BAR_13 + PF3 Table Entry 13 BAR + 0 + + + C_PF3_ENTRY_ADDR_13 + PF3 Table Entry 13 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_13 + PF3 Table Entry 13 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_13 + PF3 Table Entry 13 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_13 + PF3 Table Entry 13 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_13 + PF3 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF3_S_AXI_ADDR_WIDTH + PF3 AXI Interface Address Width + 32 + + + + false + + + + + + C_XDEVICEFAMILY + no_family + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + hw_discovery_v1_0_0 + + + + xilinx_examples_view_fileset + + ttcl/example_wrapper_sv.xit + xit + hw_discovery_v1_0_0 + + + + xilinx_examplesscriptext_view_fileset + + ttcl/example_scriptext.tcl + tclSource + hw_discovery_v1_0_0 + + + + xilinx_examplesscriptext_xilinx_com_ip_axi_vip_1_1__ref_view_fileset + + + + + + + + + + xilinx_examplessimulation_view_fileset + + ttcl/example_tb_sv.xit + xit + + + + xilinx_xpgui_view_fileset + + xgui/hw_discovery_v1_0.tcl + tclSource + XGUI_VERSION_2 + hw_discovery_v1_0_0 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/pcie_vsec.vhd + vhdlSource + USED_IN_ipstatic + hw_discovery_v1_0_0 + + + hdl/bar_layout_table.vhd + vhdlSource + USED_IN_ipstatic + hw_discovery_v1_0_0 + + + hdl/hw_disc.vhd + vhdlSource + USED_IN_ipstatic + hw_discovery_v1_0_0 + + + hdl/hw_discovery.v + verilogSource + USED_IN_ipstatic + hw_discovery_v1_0_0 + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/pcie_vsec.vhd + vhdlSource + hw_discovery_v1_0_0 + + + hdl/bar_layout_table.vhd + vhdlSource + hw_discovery_v1_0_0 + + + hdl/hw_disc.vhd + vhdlSource + hw_discovery_v1_0_0 + + + hdl/hw_discovery.v + verilogSource + CHECKSUM_dd4357f8 + hw_discovery_v1_0_0 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + + + + + + + + xilinx_versioninformation_view_fileset + + doc/hw_discovery_v1_0_changelog.txt + text + hw_discovery_v1_0_0 + + + + The HW Discovery IP provides PCIe VSEC supporting Xilinx ALF and Bar Layout table. + + + Component_Name + hw_discovery_0 + + + C_MANUAL + Manually Configure + 1 + + + C_NUM_PFS + NUMBER OF PFs + 1 + + + C_INJECT_ENDPOINTS + Inject Endpoint Info for Test + 0 + + + C_PF0_ENDPOINT_NAMES + PF0 List of Endpoint Names + 0 + + + C_PF1_ENDPOINT_NAMES + PF1 List of Endpoint Names + 0 + + + + false + + + + + + C_PF2_ENDPOINT_NAMES + PF2 List of Endpoint Names + 0 + + + + false + + + + + + C_PF3_ENDPOINT_NAMES + PF3 List of Endpoint Names + 0 + + + + false + + + + + + C_CAP_BASE_ADDR + PCIe Extended Capability Base Address + 0x000 + + + C_NEXT_CAP_ADDR + Next Capability Pointer + 0x000 + + + C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF0 + 1 + + + C_PF0_BAR_INDEX + PF0 BAR Index + 0 + + + C_PF0_LOW_OFFSET + PF0 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF0_HIGH_OFFSET + PF0 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF0_S_AXI_ADDR_WIDTH + PF0 AXI Interface Address Width + 32 + + + C_PF0_ENTRY_TYPE_0 + PF0 Table Entry 0 Type + 0x00 + + + C_PF0_ENTRY_BAR_0 + PF0 Table Entry 0 BAR + 0 + + + C_PF0_ENTRY_ADDR_0 + PF0 Table Entry 0 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_0 + PF0 Table Entry 0 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_0 + PF0 Table Entry 0 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_0 + PF0 Table Entry 0 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_0 + PF0 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_1 + PF0 Table Entry 1 Type + 0x00 + + + C_PF0_ENTRY_BAR_1 + PF0 Table Entry 1 BAR + 0 + + + C_PF0_ENTRY_ADDR_1 + PF0 Table Entry 1 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_1 + PF0 Table Entry 1 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_1 + PF0 Table Entry 1 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_1 + PF0 Table Entry 1 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_1 + PF0 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_2 + PF0 Table Entry 2 Type + 0x00 + + + C_PF0_ENTRY_BAR_2 + PF0 Table Entry 2 BAR + 0 + + + C_PF0_ENTRY_ADDR_2 + PF0 Table Entry 2 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_2 + PF0 Table Entry 2 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_2 + PF0 Table Entry 2 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_2 + PF0 Table Entry 2 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_2 + PF0 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_3 + PF0 Table Entry 3 Type + 0x00 + + + C_PF0_ENTRY_BAR_3 + PF0 Table Entry 3 BAR + 0 + + + C_PF0_ENTRY_ADDR_3 + PF0 Table Entry 3 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_3 + PF0 Table Entry 3 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_3 + PF0 Table Entry 3 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_3 + PF0 Table Entry 3 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_3 + PF0 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_4 + PF0 Table Entry 4 Type + 0x00 + + + C_PF0_ENTRY_BAR_4 + PF0 Table Entry 4 BAR + 0 + + + C_PF0_ENTRY_ADDR_4 + PF0 Table Entry 4 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_4 + PF0 Table Entry 4 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_4 + PF0 Table Entry 4 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_4 + PF0 Table Entry 4 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_5 + PF0 Table Entry 5 Type + 0x00 + + + C_PF0_ENTRY_BAR_5 + PF0 Table Entry 5 BAR + 0 + + + C_PF0_ENTRY_ADDR_5 + PF0 Table Entry 5 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_5 + PF0 Table Entry 5 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_5 + PF0 Table Entry 5 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_5 + PF0 Table Entry 5 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_5 + PF0 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_6 + PF0 Table Entry 6 Type + 0x00 + + + C_PF0_ENTRY_BAR_6 + PF0 Table Entry 6 BAR + 0 + + + C_PF0_ENTRY_ADDR_6 + PF0 Table Entry 6 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_6 + PF0 Table Entry 6 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_6 + PF0 Table Entry 6 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_6 + PF0 Table Entry 6 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_6 + PF0 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_7 + PF0 Table Entry 7 Type + 0x00 + + + C_PF0_ENTRY_BAR_7 + PF0 Table Entry 7 BAR + 0 + + + C_PF0_ENTRY_ADDR_7 + PF0 Table Entry 7 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_7 + PF0 Table Entry 7 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_7 + PF0 Table Entry 7 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_7 + PF0 Table Entry 7 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_7 + PF0 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_8 + PF0 Table Entry 8 Type + 0x00 + + + C_PF0_ENTRY_BAR_8 + PF0 Table Entry 8 BAR + 0 + + + C_PF0_ENTRY_ADDR_8 + PF0 Table Entry 8 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_8 + PF0 Table Entry 8 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_8 + PF0 Table Entry 8 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_8 + PF0 Table Entry 8 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_8 + PF0 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_9 + PF0 Table Entry 9 Type + 0x00 + + + C_PF0_ENTRY_BAR_9 + PF0 Table Entry 9 BAR + 0 + + + C_PF0_ENTRY_ADDR_9 + PF0 Table Entry 9 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_9 + PF0 Table Entry 9 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_9 + PF0 Table Entry 9 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_9 + PF0 Table Entry 9 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_9 + PF0 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_10 + PF0 Table Entry 10 Type + 0x00 + + + C_PF0_ENTRY_BAR_10 + PF0 Table Entry 10 BAR + 0 + + + C_PF0_ENTRY_ADDR_10 + PF0 Table Entry 10 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_10 + PF0 Table Entry 10 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_10 + PF0 Table Entry 10 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_10 + PF0 Table Entry 10 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_10 + PF0 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_11 + PF0 Table Entry 11 Type + 0x00 + + + C_PF0_ENTRY_BAR_11 + PF0 Table Entry 11 BAR + 0 + + + C_PF0_ENTRY_ADDR_11 + PF0 Table Entry 11 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_11 + PF0 Table Entry 11 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_11 + PF0 Table Entry 11 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_11 + PF0 Table Entry 11 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_11 + PF0 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_12 + PF0 Table Entry 12 Type + 0x00 + + + C_PF0_ENTRY_BAR_12 + PF0 Table Entry 12 BAR + 0 + + + C_PF0_ENTRY_ADDR_12 + PF0 Table Entry 12 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_12 + PF0 Table Entry 12 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_12 + PF0 Table Entry 12 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_12 + PF0 Table Entry 12 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_12 + PF0 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_13 + PF0 Table Entry 13 Type + 0x00 + + + C_PF0_ENTRY_BAR_13 + PF0 Table Entry 13 BAR + 0 + + + C_PF0_ENTRY_ADDR_13 + PF0 Table Entry 13 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_13 + PF0 Table Entry 13 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_13 + PF0 Table Entry 13 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_13 + PF0 Table Entry 13 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_13 + PF0 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF1 + 1 + + + C_PF1_BAR_INDEX + PF1 BAR Index + 0 + + + C_PF1_LOW_OFFSET + PF1 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF1_HIGH_OFFSET + PF1 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF1_S_AXI_ADDR_WIDTH + PF1 AXI Interface Address Width + 32 + + + + false + + + + + + C_PF1_ENTRY_TYPE_0 + PF1 Table Entry 0 Type + 0x00 + + + C_PF1_ENTRY_BAR_0 + PF1 Table Entry 0 BAR + 0 + + + C_PF1_ENTRY_ADDR_0 + PF1 Table Entry 0 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_0 + PF1 Table Entry 0 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_0 + PF1 Table Entry 0 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_0 + PF1 Table Entry 0 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_0 + PF1 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_1 + PF1 Table Entry 1 Type + 0x00 + + + C_PF1_ENTRY_BAR_1 + PF1 Table Entry 1 BAR + 0 + + + C_PF1_ENTRY_ADDR_1 + PF1 Table Entry 1 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_1 + PF1 Table Entry 1 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_1 + PF1 Table Entry 1 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_1 + PF1 Table Entry 1 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_1 + PF1 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_2 + PF1 Table Entry 2 Type + 0x00 + + + C_PF1_ENTRY_BAR_2 + PF1 Table Entry 2 BAR + 0 + + + C_PF1_ENTRY_ADDR_2 + PF1 Table Entry 2 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_2 + PF1 Table Entry 2 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_2 + PF1 Table Entry 2 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_2 + PF1 Table Entry 2 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_2 + PF1 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_3 + PF1 Table Entry 3 Type + 0x00 + + + C_PF1_ENTRY_BAR_3 + PF1 Table Entry 3 BAR + 0 + + + C_PF1_ENTRY_ADDR_3 + PF1 Table Entry 3 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_3 + PF1 Table Entry 3 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_3 + PF1 Table Entry 3 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_3 + PF1 Table Entry 3 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_3 + PF1 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_4 + PF1 Table Entry 4 Type + 0x00 + + + C_PF1_ENTRY_BAR_4 + PF1 Table Entry 4 BAR + 0 + + + C_PF1_ENTRY_ADDR_4 + PF1 Table Entry 4 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_4 + PF1 Table Entry 4 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_4 + PF1 Table Entry 4 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_4 + PF1 Table Entry 4 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_5 + PF1 Table Entry 5 Type + 0x00 + + + C_PF1_ENTRY_BAR_5 + PF1 Table Entry 5 BAR + 0 + + + C_PF1_ENTRY_ADDR_5 + PF1 Table Entry 5 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_5 + PF1 Table Entry 5 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_5 + PF1 Table Entry 5 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_5 + PF1 Table Entry 5 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_5 + PF1 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_6 + PF1 Table Entry 6 Type + 0x00 + + + C_PF1_ENTRY_BAR_6 + PF1 Table Entry 6 BAR + 0 + + + C_PF1_ENTRY_ADDR_6 + PF1 Table Entry 6 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_6 + PF1 Table Entry 6 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_6 + PF1 Table Entry 6 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_6 + PF1 Table Entry 6 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_6 + PF1 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_7 + PF1 Table Entry 7 Type + 0x00 + + + C_PF1_ENTRY_BAR_7 + PF1 Table Entry 7 BAR + 0 + + + C_PF1_ENTRY_ADDR_7 + PF1 Table Entry 7 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_7 + PF1 Table Entry 7 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_7 + PF1 Table Entry 7 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_7 + PF1 Table Entry 7 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_7 + PF1 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_8 + PF1 Table Entry 8 Type + 0x00 + + + C_PF1_ENTRY_BAR_8 + PF1 Table Entry 8 BAR + 0 + + + C_PF1_ENTRY_ADDR_8 + PF1 Table Entry 8 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_8 + PF1 Table Entry 8 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_8 + PF1 Table Entry 8 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_8 + PF1 Table Entry 8 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_8 + PF1 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_9 + PF1 Table Entry 9 Type + 0x00 + + + C_PF1_ENTRY_BAR_9 + PF1 Table Entry 9 BAR + 0 + + + C_PF1_ENTRY_ADDR_9 + PF1 Table Entry 9 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_9 + PF1 Table Entry 9 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_9 + PF1 Table Entry 9 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_9 + PF1 Table Entry 9 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_9 + PF1 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_10 + PF1 Table Entry 10 Type + 0x00 + + + C_PF1_ENTRY_BAR_10 + PF1 Table Entry 10 BAR + 0 + + + C_PF1_ENTRY_ADDR_10 + PF1 Table Entry 10 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_10 + PF1 Table Entry 10 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_10 + PF1 Table Entry 10 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_10 + PF1 Table Entry 10 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_10 + PF1 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_11 + PF1 Table Entry 11 Type + 0x00 + + + C_PF1_ENTRY_BAR_11 + PF1 Table Entry 11 BAR + 0 + + + C_PF1_ENTRY_ADDR_11 + PF1 Table Entry 11 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_11 + PF1 Table Entry 11 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_11 + PF1 Table Entry 11 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_11 + PF1 Table Entry 11 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_11 + PF1 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_12 + PF1 Table Entry 12 Type + 0x00 + + + C_PF1_ENTRY_BAR_12 + PF1 Table Entry 12 BAR + 0 + + + C_PF1_ENTRY_ADDR_12 + PF1 Table Entry 12 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_12 + PF1 Table Entry 12 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_12 + PF1 Table Entry 12 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_12 + PF1 Table Entry 12 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_12 + PF1 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_13 + PF1 Table Entry 13 Type + 0x00 + + + C_PF1_ENTRY_BAR_13 + PF1 Table Entry 13 BAR + 0 + + + C_PF1_ENTRY_ADDR_13 + PF1 Table Entry 13 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_13 + PF1 Table Entry 13 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_13 + PF1 Table Entry 13 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_13 + PF1 Table Entry 13 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_13 + PF1 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF2 + 1 + + + C_PF2_BAR_INDEX + PF2 BAR Index + 0 + + + C_PF2_LOW_OFFSET + PF2 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF2_HIGH_OFFSET + PF2 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF2_S_AXI_ADDR_WIDTH + PF2 AXI Interface Address Width + 32 + + + + false + + + + + + C_PF2_ENTRY_TYPE_0 + PF2 Table Entry 0 Type + 0x00 + + + C_PF2_ENTRY_BAR_0 + PF2 Table Entry 0 BAR + 0 + + + C_PF2_ENTRY_ADDR_0 + PF2 Table Entry 0 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_0 + PF2 Table Entry 0 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_0 + PF2 Table Entry 0 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_0 + PF2 Table Entry 0 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_0 + PF2 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_1 + PF2 Table Entry 1 Type + 0x00 + + + C_PF2_ENTRY_BAR_1 + PF2 Table Entry 1 BAR + 0 + + + C_PF2_ENTRY_ADDR_1 + PF2 Table Entry 1 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_1 + PF2 Table Entry 1 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_1 + PF2 Table Entry 1 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_1 + PF2 Table Entry 1 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_1 + PF2 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_2 + PF2 Table Entry 2 Type + 0x00 + + + C_PF2_ENTRY_BAR_2 + PF2 Table Entry 2 BAR + 0 + + + C_PF2_ENTRY_ADDR_2 + PF2 Table Entry 2 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_2 + PF2 Table Entry 2 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_2 + PF2 Table Entry 2 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_2 + PF2 Table Entry 2 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_2 + PF2 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_3 + PF2 Table Entry 3 Type + 0x00 + + + C_PF2_ENTRY_BAR_3 + PF2 Table Entry 3 BAR + 0 + + + C_PF2_ENTRY_ADDR_3 + PF2 Table Entry 3 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_3 + PF2 Table Entry 3 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_3 + PF2 Table Entry 3 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_3 + PF2 Table Entry 3 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_3 + PF2 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_4 + PF2 Table Entry 4 Type + 0x00 + + + C_PF2_ENTRY_BAR_4 + PF2 Table Entry 4 BAR + 0 + + + C_PF2_ENTRY_ADDR_4 + PF2 Table Entry 4 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_4 + PF2 Table Entry 4 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_4 + PF2 Table Entry 4 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_4 + PF2 Table Entry 4 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_5 + PF2 Table Entry 5 Type + 0x00 + + + C_PF2_ENTRY_BAR_5 + PF2 Table Entry 5 BAR + 0 + + + C_PF2_ENTRY_ADDR_5 + PF2 Table Entry 5 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_5 + PF2 Table Entry 5 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_5 + PF2 Table Entry 5 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_5 + PF2 Table Entry 5 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_5 + PF2 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_6 + PF2 Table Entry 6 Type + 0x00 + + + C_PF2_ENTRY_BAR_6 + PF2 Table Entry 6 BAR + 0 + + + C_PF2_ENTRY_ADDR_6 + PF2 Table Entry 6 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_6 + PF2 Table Entry 6 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_6 + PF2 Table Entry 6 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_6 + PF2 Table Entry 6 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_6 + PF2 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_7 + PF2 Table Entry 7 Type + 0x00 + + + C_PF2_ENTRY_BAR_7 + PF2 Table Entry 7 BAR + 0 + + + C_PF2_ENTRY_ADDR_7 + PF2 Table Entry 7 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_7 + PF2 Table Entry 7 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_7 + PF2 Table Entry 7 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_7 + PF2 Table Entry 7 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_7 + PF2 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_8 + PF2 Table Entry 8 Type + 0x00 + + + C_PF2_ENTRY_BAR_8 + PF2 Table Entry 8 BAR + 0 + + + C_PF2_ENTRY_ADDR_8 + PF2 Table Entry 8 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_8 + PF2 Table Entry 8 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_8 + PF2 Table Entry 8 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_8 + PF2 Table Entry 8 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_8 + PF2 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_9 + PF2 Table Entry 9 Type + 0x00 + + + C_PF2_ENTRY_BAR_9 + PF2 Table Entry 9 BAR + 0 + + + C_PF2_ENTRY_ADDR_9 + PF2 Table Entry 9 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_9 + PF2 Table Entry 9 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_9 + PF2 Table Entry 9 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_9 + PF2 Table Entry 9 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_9 + PF2 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_10 + PF2 Table Entry 10 Type + 0x00 + + + C_PF2_ENTRY_BAR_10 + PF2 Table Entry 10 BAR + 0 + + + C_PF2_ENTRY_ADDR_10 + PF2 Table Entry 10 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_10 + PF2 Table Entry 10 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_10 + PF2 Table Entry 10 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_10 + PF2 Table Entry 10 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_10 + PF2 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_11 + PF2 Table Entry 11 Type + 0x00 + + + C_PF2_ENTRY_BAR_11 + PF2 Table Entry 11 BAR + 0 + + + C_PF2_ENTRY_ADDR_11 + PF2 Table Entry 11 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_11 + PF2 Table Entry 11 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_11 + PF2 Table Entry 11 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_11 + PF2 Table Entry 11 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_11 + PF2 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_12 + PF2 Table Entry 12 Type + 0x00 + + + C_PF2_ENTRY_BAR_12 + PF2 Table Entry 12 BAR + 0 + + + C_PF2_ENTRY_ADDR_12 + PF2 Table Entry 12 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_12 + PF2 Table Entry 12 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_12 + PF2 Table Entry 12 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_12 + PF2 Table Entry 12 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_12 + PF2 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_13 + PF2 Table Entry 13 Type + 0x00 + + + C_PF2_ENTRY_BAR_13 + PF2 Table Entry 13 BAR + 0 + + + C_PF2_ENTRY_ADDR_13 + PF2 Table Entry 13 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_13 + PF2 Table Entry 13 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_13 + PF2 Table Entry 13 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_13 + PF2 Table Entry 13 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_13 + PF2 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF3 + 1 + + + C_PF3_BAR_INDEX + PF3 BAR Index + 0 + + + C_PF3_LOW_OFFSET + PF3 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF3_HIGH_OFFSET + PF3 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF3_S_AXI_ADDR_WIDTH + PF3 AXI Interface Address Width + 32 + + + + false + + + + + + C_PF3_ENTRY_TYPE_0 + PF3 Table Entry 0 Type + 0x00 + + + C_PF3_ENTRY_BAR_0 + PF3 Table Entry 0 BAR + 0 + + + C_PF3_ENTRY_ADDR_0 + PF3 Table Entry 0 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_0 + PF3 Table Entry 0 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_0 + PF3 Table Entry 0 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_0 + PF3 Table Entry 0 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_0 + PF3 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_1 + PF3 Table Entry 1 Type + 0x00 + + + C_PF3_ENTRY_BAR_1 + PF3 Table Entry 1 BAR + 0 + + + C_PF3_ENTRY_ADDR_1 + PF3 Table Entry 1 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_1 + PF3 Table Entry 1 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_1 + PF3 Table Entry 1 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_1 + PF3 Table Entry 1 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_1 + PF3 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_2 + PF3 Table Entry 2 Type + 0x00 + + + C_PF3_ENTRY_BAR_2 + PF3 Table Entry 2 BAR + 0 + + + C_PF3_ENTRY_ADDR_2 + PF3 Table Entry 2 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_2 + PF3 Table Entry 2 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_2 + PF3 Table Entry 2 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_2 + PF3 Table Entry 2 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_2 + PF3 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_3 + PF3 Table Entry 3 Type + 0x00 + + + C_PF3_ENTRY_BAR_3 + PF3 Table Entry 3 BAR + 0 + + + C_PF3_ENTRY_ADDR_3 + PF3 Table Entry 3 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_3 + PF3 Table Entry 3 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_3 + PF3 Table Entry 3 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_3 + PF3 Table Entry 3 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_3 + PF3 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_4 + PF3 Table Entry 4 Type + 0x00 + + + C_PF3_ENTRY_BAR_4 + PF3 Table Entry 4 BAR + 0 + + + C_PF3_ENTRY_ADDR_4 + PF3 Table Entry 4 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_4 + PF3 Table Entry 4 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_4 + PF3 Table Entry 4 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_4 + PF3 Table Entry 4 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_5 + PF3 Table Entry 5 Type + 0x00 + + + C_PF3_ENTRY_BAR_5 + PF3 Table Entry 5 BAR + 0 + + + C_PF3_ENTRY_ADDR_5 + PF3 Table Entry 5 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_5 + PF3 Table Entry 5 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_5 + PF3 Table Entry 5 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_5 + PF3 Table Entry 5 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_5 + PF3 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_6 + PF3 Table Entry 6 Type + 0x00 + + + C_PF3_ENTRY_BAR_6 + PF3 Table Entry 6 BAR + 0 + + + C_PF3_ENTRY_ADDR_6 + PF3 Table Entry 6 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_6 + PF3 Table Entry 6 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_6 + PF3 Table Entry 6 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_6 + PF3 Table Entry 6 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_6 + PF3 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_7 + PF3 Table Entry 7 Type + 0x00 + + + C_PF3_ENTRY_BAR_7 + PF3 Table Entry 7 BAR + 0 + + + C_PF3_ENTRY_ADDR_7 + PF3 Table Entry 7 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_7 + PF3 Table Entry 7 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_7 + PF3 Table Entry 7 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_7 + PF3 Table Entry 7 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_7 + PF3 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_8 + PF3 Table Entry 8 Type + 0x00 + + + C_PF3_ENTRY_BAR_8 + PF3 Table Entry 8 BAR + 0 + + + C_PF3_ENTRY_ADDR_8 + PF3 Table Entry 8 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_8 + PF3 Table Entry 8 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_8 + PF3 Table Entry 8 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_8 + PF3 Table Entry 8 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_8 + PF3 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_9 + PF3 Table Entry 9 Type + 0x00 + + + C_PF3_ENTRY_BAR_9 + PF3 Table Entry 9 BAR + 0 + + + C_PF3_ENTRY_ADDR_9 + PF3 Table Entry 9 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_9 + PF3 Table Entry 9 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_9 + PF3 Table Entry 9 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_9 + PF3 Table Entry 9 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_9 + PF3 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_10 + PF3 Table Entry 10 Type + 0x00 + + + C_PF3_ENTRY_BAR_10 + PF3 Table Entry 10 BAR + 0 + + + C_PF3_ENTRY_ADDR_10 + PF3 Table Entry 10 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_10 + PF3 Table Entry 10 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_10 + PF3 Table Entry 10 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_10 + PF3 Table Entry 10 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_10 + PF3 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_11 + PF3 Table Entry 11 Type + 0x00 + + + C_PF3_ENTRY_BAR_11 + PF3 Table Entry 11 BAR + 0 + + + C_PF3_ENTRY_ADDR_11 + PF3 Table Entry 11 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_11 + PF3 Table Entry 11 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_11 + PF3 Table Entry 11 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_11 + PF3 Table Entry 11 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_11 + PF3 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_12 + PF3 Table Entry 12 Type + 0x00 + + + C_PF3_ENTRY_BAR_12 + PF3 Table Entry 12 BAR + 0 + + + C_PF3_ENTRY_ADDR_12 + PF3 Table Entry 12 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_12 + PF3 Table Entry 12 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_12 + PF3 Table Entry 12 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_12 + PF3 Table Entry 12 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_12 + PF3 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_13 + PF3 Table Entry 13 Type + 0x00 + + + C_PF3_ENTRY_BAR_13 + PF3 Table Entry 13 BAR + 0 + + + C_PF3_ENTRY_ADDR_13 + PF3 Table Entry 13 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_13 + PF3 Table Entry 13 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_13 + PF3 Table Entry 13 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_13 + PF3 Table Entry 13 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_13 + PF3 Table Entry 13 Reserved Field 0 + 0x0 + + + + + + /Shell_Subsystems + + HW Discovery + level_beta + (GENERIC_FAMILY = versal) + + XPM_MEMORY + + + IPI + + http://www.xilinx.com/ + 0 + 2023-10-11T08:39:15Z + + + 2023.1 + + + + + + + + + diff --git a/linker/resources/base/iprepo/hw_discovery_v1_0/doc/hw_discovery_v1_0_changelog.txt b/linker/resources/base/iprepo/hw_discovery_v1_0/doc/hw_discovery_v1_0_changelog.txt new file mode 100644 index 00000000..d0029c28 --- /dev/null +++ b/linker/resources/base/iprepo/hw_discovery_v1_0/doc/hw_discovery_v1_0_changelog.txt @@ -0,0 +1,9 @@ +2023.2: + * Version 1.0 (Rev. 1) + * Bug Fix: Upgraded warning to error when required endpoint metadata not found + * Bug Fix: Ports pcie*_cfg_ext function_number width increased to 16 to match cips + +2023.1: + * Version 1.0 + * New Feature: Initial Release + diff --git a/linker/resources/base/iprepo/hw_discovery_v1_0/hdl/bar_layout_table.vhd b/linker/resources/base/iprepo/hw_discovery_v1_0/hdl/bar_layout_table.vhd new file mode 100644 index 00000000..c06a188c --- /dev/null +++ b/linker/resources/base/iprepo/hw_discovery_v1_0/hdl/bar_layout_table.vhd @@ -0,0 +1,457 @@ +-- (c) Copyright 2022, Advanced Micro Devices, Inc. +-- +-- Permission is hereby granted, free of charge, to any person obtaining a +-- copy of this software and associated documentation files (the "Software"), +-- to deal in the Software without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Software, and to permit persons to whom the +-- Software is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Software. +-- +-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +-- DEALINGS IN THE SOFTWARE. +------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library axi_lite_ipif_v3_0_4; + use axi_lite_ipif_v3_0_4.ipif_pkg.all; + +library hw_discovery_v1_0_0; + +entity hw_discovery_v1_0_0_bar_layout_table is + generic ( + C_NUM_SLOTS_BAR_LAYOUT_TABLE : integer range 1 to 16 := 1; + C_ENTRY_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_0 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_0 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_0 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_0 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_0 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_1 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_1 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_1 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_1 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_1 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_2 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_2 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_2 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_2 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_2 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_3 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_3 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_3 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_3 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_3 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_4 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_4 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_4 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_4 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_4 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_5 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_5 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_5 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_5 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_5 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_6 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_6 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_6 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_6 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_6 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_7 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_7 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_7 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_7 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_7 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_8 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_8 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_8 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_8 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_8 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_9 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_9 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_9 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_9 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_9 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_10 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_10 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_10 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_10 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_10 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_11 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_11 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_11 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_11 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_11 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_12 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_12 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_12 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_12 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_12 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_13 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_13 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_13 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_13 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_13 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_14 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_14 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_14 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_14 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_14 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_15 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_15 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_15 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_15 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_15 : std_logic_vector(3 downto 0) := (others => '0'); + C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_S_AXI_ADDR_WIDTH : integer range 1 to 64 := 32; + C_XDEVICEFAMILY : string := "no_family" + ); + port ( + + ----------------------------------------------------------------------- + -- Processor AXI Interface (S_AXI_ACLK) + ----------------------------------------------------------------------- + + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_awvalid : in std_logic; + s_axi_awready : out std_logic; + s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_wvalid : in std_logic; + s_axi_wready : out std_logic; + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_bready : in std_logic; + s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_arvalid : in std_logic; + s_axi_arready : out std_logic; + s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_rready : in std_logic + ); + +end hw_discovery_v1_0_0_bar_layout_table; + + +architecture top of hw_discovery_v1_0_0_bar_layout_table is + + + ------------------------------------------------------------------------------- + -- Constant Declarations + ------------------------------------------------------------------------------- + + constant ZEROES : std_logic_vector(0 to 31) := X"00000000"; + + constant C_FAMILY : string := C_XDEVICEFAMILY; + + constant REG_BASEADDR : std_logic_vector := X"00000000"; + + impure function makemask (Width: INTEGER) return std_logic_vector is + variable retv: std_logic_vector (31 downto 0) := (others => '0'); + begin + for i in (Width - 1) downto 0 loop + retv(i) := '1'; + end loop; + return retv; + end function; + + constant REG_HIGHADDR : std_logic_vector(0 to 31) := makemask(C_S_AXI_ADDR_WIDTH); + + constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( + ZEROES & REG_BASEADDR, + ZEROES & REG_HIGHADDR + ); + + constant C_ARD_IDX_REGS : integer := 0; + + constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( + C_ARD_IDX_REGS => 1 + ); + + constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) := makemask(C_S_AXI_ADDR_WIDTH); + + constant C_USE_WSTRB : integer := 0; + + constant C_DPHASE_TIMEOUT : integer := 12; + + subtype IIC_CE_RNG is integer range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0) to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0) + C_ARD_NUM_CE_ARRAY(0) - 1; + + attribute ram_style : string; + + -- BAR Layout Table ROM type + type bar_layout_rom_type is array (0 to 63) of std_logic_vector(31 downto 0); + type rom_header_type is array (0 to 3) of std_logic_vector(31 downto 0); + type rom_entry_type is array (0 to 63) of std_logic_vector(31 downto 0); + + -- Field Constants + constant HEADER_FORMAT : std_logic_vector(19 downto 0) := x"00001"; + constant HEADER_REV : std_logic_vector(7 downto 0) := x"00"; + constant HEADER_LAST_CAP : std_logic := '1'; + constant HEADER_RESERVED : std_logic_vector(2 downto 0) := "000"; + constant HEADER_LENGTH : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned((C_NUM_SLOTS_BAR_LAYOUT_TABLE * 16) + 32, 32)); + constant FORMAT_ENTRY_SIZE : std_logic_vector(7 downto 0) := x"10"; + constant ENTRY_REVISION : std_logic_vector(4 downto 0) := (others => '0'); + constant ENTRY_END_OF_TABLE : std_logic_vector(7 downto 0) := (others => '1'); + + constant ROM_HEADER : rom_header_type := (0 => (HEADER_RESERVED & HEADER_LAST_CAP & HEADER_REV & HEADER_FORMAT), + 1 => HEADER_LENGTH, + 2 => (x"000000" & FORMAT_ENTRY_SIZE), + 3 => (others => '0')); + + constant ROM_ENTRIES : rom_entry_type := (0 => (C_ENTRY_ADDR_0(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_0, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_0), + 1 => C_ENTRY_ADDR_0(47 downto 16), + 2 => x"0" & C_ENTRY_RSVD0_0 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_0, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_0, 8)) & C_ENTRY_VERSION_TYPE_0, + 3 => x"00000000", + 4 => (C_ENTRY_ADDR_1(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_1, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_1), + 5 => C_ENTRY_ADDR_1(47 downto 16), + 6 => x"0" & C_ENTRY_RSVD0_1 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_1, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_1, 8)) & C_ENTRY_VERSION_TYPE_1, + 7 => x"00000000", + 8 => (C_ENTRY_ADDR_2(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_2, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_2), + 9 => C_ENTRY_ADDR_2(47 downto 16), + 10 => x"0" & C_ENTRY_RSVD0_2 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_2, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_2, 8)) & C_ENTRY_VERSION_TYPE_2, + 11 => x"00000000", + 12 => (C_ENTRY_ADDR_3(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_3, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_3), + 13 => C_ENTRY_ADDR_3(47 downto 16), + 14 => x"0" & C_ENTRY_RSVD0_3 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_3, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_3, 8)) & C_ENTRY_VERSION_TYPE_3, + 15 => x"00000000", + 16 => (C_ENTRY_ADDR_4(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_4, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_4), + 17 => C_ENTRY_ADDR_4(47 downto 16), + 18 => x"0" & C_ENTRY_RSVD0_4 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_4, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_4, 8)) & C_ENTRY_VERSION_TYPE_4, + 19 => x"00000000", + 20 => (C_ENTRY_ADDR_5(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_5, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_5), + 21 => C_ENTRY_ADDR_5(47 downto 16), + 22 => x"0" & C_ENTRY_RSVD0_5 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_5, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_5, 8)) & C_ENTRY_VERSION_TYPE_5, + 23 => x"00000000", + 24 => (C_ENTRY_ADDR_6(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_6, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_6), + 25 => C_ENTRY_ADDR_6(47 downto 16), + 26 => x"0" & C_ENTRY_RSVD0_6 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_6, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_6, 8)) & C_ENTRY_VERSION_TYPE_6, + 27 => x"00000000", + 28 => (C_ENTRY_ADDR_7(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_7, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_7), + 29 => C_ENTRY_ADDR_7(47 downto 16), + 30 => x"0" & C_ENTRY_RSVD0_7 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_7, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_7, 8)) & C_ENTRY_VERSION_TYPE_7, + 31 => x"00000000", + 32 => (C_ENTRY_ADDR_8(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_8, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_8), + 33 => C_ENTRY_ADDR_8(47 downto 16), + 34 => x"0" & C_ENTRY_RSVD0_8 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_8, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_8, 8)) & C_ENTRY_VERSION_TYPE_8, + 35 => x"00000000", + 36 => (C_ENTRY_ADDR_9(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_9, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_9), + 37 => C_ENTRY_ADDR_9(47 downto 16), + 38 => x"0" & C_ENTRY_RSVD0_9 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_9, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_9, 8)) & C_ENTRY_VERSION_TYPE_9, + 39 => x"00000000", + 40 => (C_ENTRY_ADDR_10(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_10, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_10), + 41 => C_ENTRY_ADDR_10(47 downto 16), + 42 => x"0" & C_ENTRY_RSVD0_10 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_10, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_10, 8)) & C_ENTRY_VERSION_TYPE_10, + 43 => x"00000000", + 44 => (C_ENTRY_ADDR_11(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_11, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_11), + 45 => C_ENTRY_ADDR_11(47 downto 16), + 46 => x"0" & C_ENTRY_RSVD0_11 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_11, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_11, 8)) & C_ENTRY_VERSION_TYPE_11, + 47 => x"00000000", + 48 => (C_ENTRY_ADDR_12(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_12, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_12), + 49 => C_ENTRY_ADDR_12(47 downto 16), + 50 => x"0" & C_ENTRY_RSVD0_12 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_12, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_12, 8)) & C_ENTRY_VERSION_TYPE_12, + 51 => x"00000000", + 52 => (C_ENTRY_ADDR_13(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_13, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_13), + 53 => C_ENTRY_ADDR_13(47 downto 16), + 54 => x"0" & C_ENTRY_RSVD0_13 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_13, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_13, 8)) & C_ENTRY_VERSION_TYPE_13, + 55 => x"00000000", + 56 => (C_ENTRY_ADDR_14(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_14, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_14), + 57 => C_ENTRY_ADDR_14(47 downto 16), + 58 => x"0" & C_ENTRY_RSVD0_14 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_14, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_14, 8)) & C_ENTRY_VERSION_TYPE_14, + 59 => x"00000000", + 60 => (C_ENTRY_ADDR_15(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_15, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_15), + 61 => C_ENTRY_ADDR_15(47 downto 16), + 62 => x"0" & C_ENTRY_RSVD0_15 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_15, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_15, 8)) & C_ENTRY_VERSION_TYPE_15, + 63 => x"00000000"); + + ------------------------------------------------------------------------------- + -- Function Declarations + ------------------------------------------------------------------------------- + + function fn_rom_init return bar_layout_rom_type is + + variable rom : bar_layout_rom_type := (others => (others => '0')); + variable j : integer := 0; + + begin + + -- Insert the ROM Header & Format Fields + for i in rom_header_type'RANGE loop + + rom(i) := ROM_HEADER(i); + + end loop; + + -- Insert the configured table entries + j := 0; + + for i in 4 to (C_NUM_SLOTS_BAR_LAYOUT_TABLE * 4 + 3) loop + + rom(i) := ROM_ENTRIES(j); + j := j + 1; + + end loop; + + -- Insert the end of table entry + rom((C_NUM_SLOTS_BAR_LAYOUT_TABLE * 4 + 4)) := x"000000" & ENTRY_END_OF_TABLE; + + return rom; + + end function; + + ------------------------------------------------------------------------------- + -- Signal Declarations + ------------------------------------------------------------------------------- + + signal Bus2IP_Clk : std_logic := '0'; + signal Bus2IP_Resetn : std_logic := '0'; + signal Bus2IP_Addr : std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0) := (others => '0'); + signal Bus2IP_RNW : std_logic := '0'; + signal Bus2IP_BE : std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0) := (others => '0'); + signal Bus2IP_CS : std_logic_vector(((C_ARD_ADDR_RANGE_ARRAY'length)/2-1) downto 0) := (others => '0'); + signal Bus2IP_RdCE : std_logic_vector((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0) := (others => '0'); + signal Bus2IP_WrCE : std_logic_vector((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0) := (others => '0'); + signal Bus2IP_Data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0'); + signal IP2Bus_Data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0'); + signal IP2Bus_WrAck : std_logic := '0'; + signal IP2Bus_RdAck : std_logic := '0'; + signal IP2Bus_Error : std_logic := '0'; + signal IP2Bus_Ack : std_logic_vector(1 to 4) := (others => '0'); + signal BAR_Layout_ROM : bar_layout_rom_type := fn_rom_init; + + attribute ram_style of BAR_Layout_ROM : signal is "distributed"; + +begin + + axi_lite_ipif_1 : entity axi_lite_ipif_v3_0_4.axi_lite_ipif + generic map + ( + C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, + C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, + C_USE_WSTRB => C_USE_WSTRB, + C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, + C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, + C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, + C_FAMILY => C_FAMILY + ) + port map ( + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_awready => s_axi_awready, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_bready => s_axi_bready, + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_rready => s_axi_rready, + Bus2IP_Clk => Bus2IP_Clk, + Bus2IP_Resetn => Bus2IP_Resetn, + Bus2IP_Addr => Bus2IP_Addr, + Bus2IP_RNW => Bus2IP_RNW, + Bus2IP_BE => Bus2IP_BE, + Bus2IP_CS => Bus2IP_CS, + Bus2IP_RdCE => Bus2IP_RdCE, + Bus2IP_WrCE => Bus2IP_WrCE, + Bus2IP_Data => Bus2IP_Data, + IP2Bus_Data => IP2Bus_Data, + IP2Bus_WrAck => IP2Bus_WrAck, + IP2Bus_RdAck => IP2Bus_RdAck, + IP2Bus_Error => IP2Bus_Error + ); + + axi_dec : process(Bus2IP_Clk) + + variable Addr_Slice1 : std_logic_vector(7 downto 2) := (others => '0'); + + begin + + if rising_edge(Bus2IP_Clk) then + + -- Default assignments + IP2Bus_Data <= (others => '0'); + IP2Bus_Ack <= (others => '0'); + IP2Bus_WrAck <= '0'; + IP2Bus_RdAck <= '0'; + + if (Bus2IP_CS(0) = '1') then + + Addr_Slice1 := Bus2IP_Addr(Addr_Slice1'RANGE); + + -- Read the BAR Layout Table ROM + IP2Bus_Data <= BAR_Layout_ROM(to_integer(unsigned(Addr_Slice1))); + + -- Generate the Ack shift reg + IP2Bus_Ack <= '1' & IP2Bus_Ack(1 to IP2Bus_Ack'HIGH-1); + + end if; + + -- Single cycle Rd/Wr Ack to IPIF + if ((IP2Bus_Ack(3) = '1') and (IP2Bus_Ack(4) = '0')) then + + IP2Bus_WrAck <= '1'; + IP2Bus_RdAck <= '1'; + + end if; + + end if; + + end process axi_dec; + + IP2Bus_Error <= '0'; + + +end top; diff --git a/linker/resources/base/iprepo/hw_discovery_v1_0/hdl/hw_disc.vhd b/linker/resources/base/iprepo/hw_discovery_v1_0/hdl/hw_disc.vhd new file mode 100644 index 00000000..468c2eb8 --- /dev/null +++ b/linker/resources/base/iprepo/hw_discovery_v1_0/hdl/hw_disc.vhd @@ -0,0 +1,1285 @@ +-- (c) Copyright 2022, Advanced Micro Devices, Inc. +-- +-- Permission is hereby granted, free of charge, to any person obtaining a +-- copy of this software and associated documentation files (the "Software"), +-- to deal in the Software without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Software, and to permit persons to whom the +-- Software is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Software. +-- +-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +-- DEALINGS IN THE SOFTWARE. +------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_misc.all; + use ieee.numeric_std.all; + +library axi_lite_ipif_v3_0_4; + use axi_lite_ipif_v3_0_4.ipif_pkg.all; + +library xpm; + use xpm.vcomponents.all; + +library hw_discovery_v1_0_0; + +entity hw_discovery_v1_0_0_hw_disc is + generic ( + C_NUM_PFS : integer range 1 to 4 := 1; + C_CAP_BASE_ADDR : std_logic_vector(11 downto 0) := x"480"; -- 0x480 default for PCIE4 + C_NEXT_CAP_ADDR : std_logic_vector(11 downto 0) := (others => '0'); + C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE : integer range 1 to 16 := 1; + C_PF0_BAR_INDEX : integer range 0 to 6 := 0; + C_PF0_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF0_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_0 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_0 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_0 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_1 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_1 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_1 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_2 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_2 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_2 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_3 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_3 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_3 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_4 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_4 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_4 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_5 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_5 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_5 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_6 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_6 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_6 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_7 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_7 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_7 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_8 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_8 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_8 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_9 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_9 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_9 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_10 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_10 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_10 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_11 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_11 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_11 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_12 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_12 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_12 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_13 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_13 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_13 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_14 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_14 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_14 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_15 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_15 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_15 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_PF0_S_AXI_ADDR_WIDTH : integer range 1 to 64 := 32; + C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE : integer range 1 to 16 := 1; + C_PF1_BAR_INDEX : integer range 0 to 6 := 0; + C_PF1_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF1_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_0 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_0 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_0 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_1 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_1 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_1 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_2 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_2 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_2 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_3 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_3 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_3 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_4 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_4 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_4 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_5 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_5 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_5 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_6 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_6 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_6 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_7 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_7 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_7 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_8 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_8 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_8 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_9 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_9 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_9 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_10 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_10 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_10 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_11 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_11 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_11 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_12 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_12 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_12 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_13 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_13 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_13 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_14 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_14 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_14 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_15 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_15 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_15 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_PF1_S_AXI_ADDR_WIDTH : integer range 1 to 64 := 32; + C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE : integer range 1 to 16 := 1; + C_PF2_BAR_INDEX : integer range 0 to 6 := 0; + C_PF2_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF2_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_0 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_0 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_0 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_1 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_1 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_1 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_2 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_2 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_2 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_3 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_3 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_3 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_4 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_4 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_4 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_5 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_5 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_5 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_6 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_6 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_6 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_7 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_7 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_7 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_8 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_8 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_8 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_9 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_9 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_9 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_10 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_10 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_10 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_11 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_11 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_11 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_12 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_12 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_12 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_13 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_13 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_13 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_14 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_14 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_14 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_15 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_15 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_15 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_PF2_S_AXI_ADDR_WIDTH : integer range 1 to 64 := 32; + C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE : integer range 1 to 16 := 1; + C_PF3_BAR_INDEX : integer range 0 to 6 := 0; + C_PF3_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF3_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_0 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_0 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_0 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_1 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_1 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_1 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_2 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_2 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_2 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_3 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_3 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_3 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_4 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_4 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_4 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_5 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_5 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_5 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_6 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_6 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_6 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_7 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_7 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_7 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_8 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_8 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_8 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_9 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_9 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_9 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_10 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_10 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_10 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_11 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_11 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_11 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_12 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_12 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_12 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_13 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_13 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_13 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_14 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_14 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_14 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_15 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_15 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_15 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_PF3_S_AXI_ADDR_WIDTH : integer range 1 to 64 := 32; + C_XDEVICEFAMILY : string := "no_family" + ); + port ( + ----------------------------------------------------------------------- + -- Clocks & Resets + ----------------------------------------------------------------------- + + aclk_pcie : in std_logic; + aresetn_pcie : in std_logic; + + aclk_ctrl : in std_logic; + aresetn_ctrl : in std_logic; + + ----------------------------------------------------------------------- + -- slave pcie4_cfg_ext Interface (aclk_pcie) + ----------------------------------------------------------------------- + + s_pcie4_cfg_ext_function_number : in std_logic_vector(15 downto 0); + s_pcie4_cfg_ext_read_data : out std_logic_vector(31 downto 0); + s_pcie4_cfg_ext_read_data_valid : out std_logic; + s_pcie4_cfg_ext_read_received : in std_logic; + s_pcie4_cfg_ext_register_number : in std_logic_vector(9 downto 0); + s_pcie4_cfg_ext_write_byte_enable : in std_logic_vector(3 downto 0); + s_pcie4_cfg_ext_write_data : in std_logic_vector(31 downto 0); + s_pcie4_cfg_ext_write_received : in std_logic; + + ----------------------------------------------------------------------- + -- master pcie4_cfg_ext Interface (aclk_pcie) + ----------------------------------------------------------------------- + + m_pcie4_cfg_ext_function_number : out std_logic_vector(15 downto 0); + m_pcie4_cfg_ext_read_data : in std_logic_vector(31 downto 0); + m_pcie4_cfg_ext_read_data_valid : in std_logic; + m_pcie4_cfg_ext_read_received : out std_logic; + m_pcie4_cfg_ext_register_number : out std_logic_vector(9 downto 0); + m_pcie4_cfg_ext_write_byte_enable : out std_logic_vector(3 downto 0); + m_pcie4_cfg_ext_write_data : out std_logic_vector(31 downto 0); + m_pcie4_cfg_ext_write_received : out std_logic; + + ----------------------------------------------------------------------- + -- AXI Interface (aclk_ctrl) for PF0 + ----------------------------------------------------------------------- + + s_axi_ctrl_pf0_awaddr : in std_logic_vector(C_PF0_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf0_awvalid : in std_logic; + s_axi_ctrl_pf0_awready : out std_logic; + s_axi_ctrl_pf0_wdata : in std_logic_vector(C_PF0_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf0_wstrb : in std_logic_vector((C_PF0_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_ctrl_pf0_wvalid : in std_logic; + s_axi_ctrl_pf0_wready : out std_logic; + s_axi_ctrl_pf0_bresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf0_bvalid : out std_logic; + s_axi_ctrl_pf0_bready : in std_logic; + s_axi_ctrl_pf0_araddr : in std_logic_vector(C_PF0_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf0_arvalid : in std_logic; + s_axi_ctrl_pf0_arready : out std_logic; + s_axi_ctrl_pf0_rdata : out std_logic_vector(C_PF0_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf0_rresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf0_rvalid : out std_logic; + s_axi_ctrl_pf0_rready : in std_logic; + + ----------------------------------------------------------------------- + -- AXI Interface (aclk_ctrl) for PF1 + ----------------------------------------------------------------------- + + s_axi_ctrl_pf1_awaddr : in std_logic_vector(C_PF1_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf1_awvalid : in std_logic; + s_axi_ctrl_pf1_awready : out std_logic; + s_axi_ctrl_pf1_wdata : in std_logic_vector(C_PF1_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf1_wstrb : in std_logic_vector((C_PF1_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_ctrl_pf1_wvalid : in std_logic; + s_axi_ctrl_pf1_wready : out std_logic; + s_axi_ctrl_pf1_bresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf1_bvalid : out std_logic; + s_axi_ctrl_pf1_bready : in std_logic; + s_axi_ctrl_pf1_araddr : in std_logic_vector(C_PF1_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf1_arvalid : in std_logic; + s_axi_ctrl_pf1_arready : out std_logic; + s_axi_ctrl_pf1_rdata : out std_logic_vector(C_PF1_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf1_rresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf1_rvalid : out std_logic; + s_axi_ctrl_pf1_rready : in std_logic; + + ----------------------------------------------------------------------- + -- AXI Interface (aclk_ctrl) for PF2 + ----------------------------------------------------------------------- + + s_axi_ctrl_pf2_awaddr : in std_logic_vector(C_PF2_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf2_awvalid : in std_logic; + s_axi_ctrl_pf2_awready : out std_logic; + s_axi_ctrl_pf2_wdata : in std_logic_vector(C_PF2_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf2_wstrb : in std_logic_vector((C_PF2_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_ctrl_pf2_wvalid : in std_logic; + s_axi_ctrl_pf2_wready : out std_logic; + s_axi_ctrl_pf2_bresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf2_bvalid : out std_logic; + s_axi_ctrl_pf2_bready : in std_logic; + s_axi_ctrl_pf2_araddr : in std_logic_vector(C_PF2_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf2_arvalid : in std_logic; + s_axi_ctrl_pf2_arready : out std_logic; + s_axi_ctrl_pf2_rdata : out std_logic_vector(C_PF2_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf2_rresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf2_rvalid : out std_logic; + s_axi_ctrl_pf2_rready : in std_logic; + + ----------------------------------------------------------------------- + -- AXI Interface (aclk_ctrl) for PF3 + ----------------------------------------------------------------------- + + s_axi_ctrl_pf3_awaddr : in std_logic_vector(C_PF3_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf3_awvalid : in std_logic; + s_axi_ctrl_pf3_awready : out std_logic; + s_axi_ctrl_pf3_wdata : in std_logic_vector(C_PF3_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf3_wstrb : in std_logic_vector((C_PF3_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_ctrl_pf3_wvalid : in std_logic; + s_axi_ctrl_pf3_wready : out std_logic; + s_axi_ctrl_pf3_bresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf3_bvalid : out std_logic; + s_axi_ctrl_pf3_bready : in std_logic; + s_axi_ctrl_pf3_araddr : in std_logic_vector(C_PF3_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf3_arvalid : in std_logic; + s_axi_ctrl_pf3_arready : out std_logic; + s_axi_ctrl_pf3_rdata : out std_logic_vector(C_PF3_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf3_rresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf3_rvalid : out std_logic; + s_axi_ctrl_pf3_rready : in std_logic + + ); + +end hw_discovery_v1_0_0_hw_disc; + +architecture rtl of hw_discovery_v1_0_0_hw_disc is + + ------------------------------------------------------------------------------- + -- Constant Declarations + ------------------------------------------------------------------------------- + + -- Constants for AXI4-Lite. + constant ZEROES : std_logic_vector(0 to 31) := (others => '0'); + constant ONES : std_logic_vector(0 to 31) := (others => '1'); + + constant C_FAMILY : string := C_XDEVICEFAMILY; + +begin + + pcie_vsec_inst : entity hw_discovery_v1_0_0.hw_discovery_v1_0_0_pcie_vsec + generic map ( + C_NUM_PFS => C_NUM_PFS, + C_CAP_BASE_ADDR => C_CAP_BASE_ADDR, + C_NEXT_CAP_ADDR => C_NEXT_CAP_ADDR, + C_PF0_BAR_INDEX => C_PF0_BAR_INDEX, + C_PF0_LOW_OFFSET => C_PF0_LOW_OFFSET, + C_PF0_HIGH_OFFSET => C_PF0_HIGH_OFFSET, + C_PF1_BAR_INDEX => C_PF1_BAR_INDEX, + C_PF1_LOW_OFFSET => C_PF1_LOW_OFFSET, + C_PF1_HIGH_OFFSET => C_PF1_HIGH_OFFSET, + C_PF2_BAR_INDEX => C_PF2_BAR_INDEX, + C_PF2_LOW_OFFSET => C_PF2_LOW_OFFSET, + C_PF2_HIGH_OFFSET => C_PF2_HIGH_OFFSET, + C_PF3_BAR_INDEX => C_PF3_BAR_INDEX, + C_PF3_LOW_OFFSET => C_PF3_LOW_OFFSET, + C_PF3_HIGH_OFFSET => C_PF3_HIGH_OFFSET, + C_XDEVICEFAMILY => C_XDEVICEFAMILY + ) + port map ( + aclk_pcie => aclk_pcie, + aresetn_pcie => aresetn_pcie, + s_pcie4_cfg_ext_function_number => s_pcie4_cfg_ext_function_number, + s_pcie4_cfg_ext_read_data => s_pcie4_cfg_ext_read_data, + s_pcie4_cfg_ext_read_data_valid => s_pcie4_cfg_ext_read_data_valid, + s_pcie4_cfg_ext_read_received => s_pcie4_cfg_ext_read_received, + s_pcie4_cfg_ext_register_number => s_pcie4_cfg_ext_register_number, + s_pcie4_cfg_ext_write_byte_enable => s_pcie4_cfg_ext_write_byte_enable, + s_pcie4_cfg_ext_write_data => s_pcie4_cfg_ext_write_data, + s_pcie4_cfg_ext_write_received => s_pcie4_cfg_ext_write_received, + m_pcie4_cfg_ext_function_number => m_pcie4_cfg_ext_function_number, + m_pcie4_cfg_ext_read_data => m_pcie4_cfg_ext_read_data, + m_pcie4_cfg_ext_read_data_valid => m_pcie4_cfg_ext_read_data_valid, + m_pcie4_cfg_ext_read_received => m_pcie4_cfg_ext_read_received, + m_pcie4_cfg_ext_register_number => m_pcie4_cfg_ext_register_number, + m_pcie4_cfg_ext_write_byte_enable => m_pcie4_cfg_ext_write_byte_enable, + m_pcie4_cfg_ext_write_data => m_pcie4_cfg_ext_write_data, + m_pcie4_cfg_ext_write_received => m_pcie4_cfg_ext_write_received + ); + + G_GENERATE: for i in 0 to C_NUM_PFS-1 generate + + G_GENERATE_PF0 : if (i = 0) generate + + -- Instantiate BAR Layout table + BAR_LAYOUT_TABLE_inst_0 : entity hw_discovery_v1_0_0.hw_discovery_v1_0_0_bar_layout_table + generic map ( + C_NUM_SLOTS_BAR_LAYOUT_TABLE => C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE, + C_ENTRY_TYPE_0 => C_PF0_ENTRY_TYPE_0, + C_ENTRY_BAR_0 => C_PF0_ENTRY_BAR_0, + C_ENTRY_ADDR_0 => C_PF0_ENTRY_ADDR_0, + C_ENTRY_MAJOR_VERSION_0 => C_PF0_ENTRY_MAJOR_VERSION_0, + C_ENTRY_MINOR_VERSION_0 => C_PF0_ENTRY_MINOR_VERSION_0, + C_ENTRY_VERSION_TYPE_0 => C_PF0_ENTRY_VERSION_TYPE_0, + C_ENTRY_RSVD0_0 => C_PF0_ENTRY_RSVD0_0, + C_ENTRY_TYPE_1 => C_PF0_ENTRY_TYPE_1, + C_ENTRY_BAR_1 => C_PF0_ENTRY_BAR_1, + C_ENTRY_ADDR_1 => C_PF0_ENTRY_ADDR_1, + C_ENTRY_MAJOR_VERSION_1 => C_PF0_ENTRY_MAJOR_VERSION_1, + C_ENTRY_MINOR_VERSION_1 => C_PF0_ENTRY_MINOR_VERSION_1, + C_ENTRY_VERSION_TYPE_1 => C_PF0_ENTRY_VERSION_TYPE_1, + C_ENTRY_RSVD0_1 => C_PF0_ENTRY_RSVD0_1, + C_ENTRY_TYPE_2 => C_PF0_ENTRY_TYPE_2, + C_ENTRY_BAR_2 => C_PF0_ENTRY_BAR_2, + C_ENTRY_ADDR_2 => C_PF0_ENTRY_ADDR_2, + C_ENTRY_MAJOR_VERSION_2 => C_PF0_ENTRY_MAJOR_VERSION_2, + C_ENTRY_MINOR_VERSION_2 => C_PF0_ENTRY_MINOR_VERSION_2, + C_ENTRY_VERSION_TYPE_2 => C_PF0_ENTRY_VERSION_TYPE_2, + C_ENTRY_RSVD0_2 => C_PF0_ENTRY_RSVD0_2, + C_ENTRY_TYPE_3 => C_PF0_ENTRY_TYPE_3, + C_ENTRY_BAR_3 => C_PF0_ENTRY_BAR_3, + C_ENTRY_ADDR_3 => C_PF0_ENTRY_ADDR_3, + C_ENTRY_MAJOR_VERSION_3 => C_PF0_ENTRY_MAJOR_VERSION_3, + C_ENTRY_MINOR_VERSION_3 => C_PF0_ENTRY_MINOR_VERSION_3, + C_ENTRY_VERSION_TYPE_3 => C_PF0_ENTRY_VERSION_TYPE_3, + C_ENTRY_RSVD0_3 => C_PF0_ENTRY_RSVD0_3, + C_ENTRY_TYPE_4 => C_PF0_ENTRY_TYPE_4, + C_ENTRY_BAR_4 => C_PF0_ENTRY_BAR_4, + C_ENTRY_ADDR_4 => C_PF0_ENTRY_ADDR_4, + C_ENTRY_MAJOR_VERSION_4 => C_PF0_ENTRY_MAJOR_VERSION_4, + C_ENTRY_MINOR_VERSION_4 => C_PF0_ENTRY_MINOR_VERSION_4, + C_ENTRY_VERSION_TYPE_4 => C_PF0_ENTRY_VERSION_TYPE_4, + C_ENTRY_RSVD0_4 => C_PF0_ENTRY_RSVD0_4, + C_ENTRY_TYPE_5 => C_PF0_ENTRY_TYPE_5, + C_ENTRY_BAR_5 => C_PF0_ENTRY_BAR_5, + C_ENTRY_ADDR_5 => C_PF0_ENTRY_ADDR_5, + C_ENTRY_MAJOR_VERSION_5 => C_PF0_ENTRY_MAJOR_VERSION_5, + C_ENTRY_MINOR_VERSION_5 => C_PF0_ENTRY_MINOR_VERSION_5, + C_ENTRY_VERSION_TYPE_5 => C_PF0_ENTRY_VERSION_TYPE_5, + C_ENTRY_RSVD0_5 => C_PF0_ENTRY_RSVD0_5, + C_ENTRY_TYPE_6 => C_PF0_ENTRY_TYPE_6, + C_ENTRY_BAR_6 => C_PF0_ENTRY_BAR_6, + C_ENTRY_ADDR_6 => C_PF0_ENTRY_ADDR_6, + C_ENTRY_MAJOR_VERSION_6 => C_PF0_ENTRY_MAJOR_VERSION_6, + C_ENTRY_MINOR_VERSION_6 => C_PF0_ENTRY_MINOR_VERSION_6, + C_ENTRY_VERSION_TYPE_6 => C_PF0_ENTRY_VERSION_TYPE_6, + C_ENTRY_RSVD0_6 => C_PF0_ENTRY_RSVD0_6, + C_ENTRY_TYPE_7 => C_PF0_ENTRY_TYPE_7, + C_ENTRY_BAR_7 => C_PF0_ENTRY_BAR_7, + C_ENTRY_ADDR_7 => C_PF0_ENTRY_ADDR_7, + C_ENTRY_MAJOR_VERSION_7 => C_PF0_ENTRY_MAJOR_VERSION_7, + C_ENTRY_MINOR_VERSION_7 => C_PF0_ENTRY_MINOR_VERSION_7, + C_ENTRY_VERSION_TYPE_7 => C_PF0_ENTRY_VERSION_TYPE_7, + C_ENTRY_RSVD0_7 => C_PF0_ENTRY_RSVD0_7, + C_ENTRY_TYPE_8 => C_PF0_ENTRY_TYPE_8, + C_ENTRY_BAR_8 => C_PF0_ENTRY_BAR_8, + C_ENTRY_ADDR_8 => C_PF0_ENTRY_ADDR_8, + C_ENTRY_MAJOR_VERSION_8 => C_PF0_ENTRY_MAJOR_VERSION_8, + C_ENTRY_MINOR_VERSION_8 => C_PF0_ENTRY_MINOR_VERSION_8, + C_ENTRY_VERSION_TYPE_8 => C_PF0_ENTRY_VERSION_TYPE_8, + C_ENTRY_RSVD0_8 => C_PF0_ENTRY_RSVD0_8, + C_ENTRY_TYPE_9 => C_PF0_ENTRY_TYPE_9, + C_ENTRY_BAR_9 => C_PF0_ENTRY_BAR_9, + C_ENTRY_ADDR_9 => C_PF0_ENTRY_ADDR_9, + C_ENTRY_MAJOR_VERSION_9 => C_PF0_ENTRY_MAJOR_VERSION_9, + C_ENTRY_MINOR_VERSION_9 => C_PF0_ENTRY_MINOR_VERSION_9, + C_ENTRY_VERSION_TYPE_9 => C_PF0_ENTRY_VERSION_TYPE_9, + C_ENTRY_RSVD0_9 => C_PF0_ENTRY_RSVD0_9, + C_ENTRY_TYPE_10 => C_PF0_ENTRY_TYPE_10, + C_ENTRY_BAR_10 => C_PF0_ENTRY_BAR_10, + C_ENTRY_ADDR_10 => C_PF0_ENTRY_ADDR_10, + C_ENTRY_MAJOR_VERSION_10 => C_PF0_ENTRY_MAJOR_VERSION_10, + C_ENTRY_MINOR_VERSION_10 => C_PF0_ENTRY_MINOR_VERSION_10, + C_ENTRY_VERSION_TYPE_10 => C_PF0_ENTRY_VERSION_TYPE_10, + C_ENTRY_RSVD0_10 => C_PF0_ENTRY_RSVD0_10, + C_ENTRY_TYPE_11 => C_PF0_ENTRY_TYPE_11, + C_ENTRY_BAR_11 => C_PF0_ENTRY_BAR_11, + C_ENTRY_ADDR_11 => C_PF0_ENTRY_ADDR_11, + C_ENTRY_MAJOR_VERSION_11 => C_PF0_ENTRY_MAJOR_VERSION_11, + C_ENTRY_MINOR_VERSION_11 => C_PF0_ENTRY_MINOR_VERSION_11, + C_ENTRY_VERSION_TYPE_11 => C_PF0_ENTRY_VERSION_TYPE_11, + C_ENTRY_RSVD0_11 => C_PF0_ENTRY_RSVD0_11, + C_ENTRY_TYPE_12 => C_PF0_ENTRY_TYPE_12, + C_ENTRY_BAR_12 => C_PF0_ENTRY_BAR_12, + C_ENTRY_ADDR_12 => C_PF0_ENTRY_ADDR_12, + C_ENTRY_MAJOR_VERSION_12 => C_PF0_ENTRY_MAJOR_VERSION_12, + C_ENTRY_MINOR_VERSION_12 => C_PF0_ENTRY_MINOR_VERSION_12, + C_ENTRY_VERSION_TYPE_12 => C_PF0_ENTRY_VERSION_TYPE_12, + C_ENTRY_RSVD0_12 => C_PF0_ENTRY_RSVD0_12, + C_ENTRY_TYPE_13 => C_PF0_ENTRY_TYPE_13, + C_ENTRY_BAR_13 => C_PF0_ENTRY_BAR_13, + C_ENTRY_ADDR_13 => C_PF0_ENTRY_ADDR_13, + C_ENTRY_MAJOR_VERSION_13 => C_PF0_ENTRY_MAJOR_VERSION_13, + C_ENTRY_MINOR_VERSION_13 => C_PF0_ENTRY_MINOR_VERSION_13, + C_ENTRY_VERSION_TYPE_13 => C_PF0_ENTRY_VERSION_TYPE_13, + C_ENTRY_RSVD0_13 => C_PF0_ENTRY_RSVD0_13, + C_ENTRY_TYPE_14 => C_PF0_ENTRY_TYPE_14, + C_ENTRY_BAR_14 => C_PF0_ENTRY_BAR_14, + C_ENTRY_ADDR_14 => C_PF0_ENTRY_ADDR_14, + C_ENTRY_MAJOR_VERSION_14 => C_PF0_ENTRY_MAJOR_VERSION_14, + C_ENTRY_MINOR_VERSION_14 => C_PF0_ENTRY_MINOR_VERSION_14, + C_ENTRY_VERSION_TYPE_14 => C_PF0_ENTRY_VERSION_TYPE_14, + C_ENTRY_RSVD0_14 => C_PF0_ENTRY_RSVD0_14, + C_ENTRY_TYPE_15 => C_PF0_ENTRY_TYPE_15, + C_ENTRY_BAR_15 => C_PF0_ENTRY_BAR_15, + C_ENTRY_ADDR_15 => C_PF0_ENTRY_ADDR_15, + C_ENTRY_MAJOR_VERSION_15 => C_PF0_ENTRY_MAJOR_VERSION_15, + C_ENTRY_MINOR_VERSION_15 => C_PF0_ENTRY_MINOR_VERSION_15, + C_ENTRY_VERSION_TYPE_15 => C_PF0_ENTRY_VERSION_TYPE_15, + C_ENTRY_RSVD0_15 => C_PF0_ENTRY_RSVD0_15, + C_S_AXI_DATA_WIDTH => C_PF0_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_PF0_S_AXI_ADDR_WIDTH, + C_XDEVICEFAMILY => C_XDEVICEFAMILY + ) + port map ( + s_axi_aclk => aclk_ctrl, + s_axi_aresetn => aresetn_ctrl, + s_axi_awaddr => s_axi_ctrl_pf0_awaddr, + s_axi_awvalid => s_axi_ctrl_pf0_awvalid, + s_axi_awready => s_axi_ctrl_pf0_awready, + s_axi_wdata => s_axi_ctrl_pf0_wdata, + s_axi_wstrb => s_axi_ctrl_pf0_wstrb, + s_axi_wvalid => s_axi_ctrl_pf0_wvalid, + s_axi_wready => s_axi_ctrl_pf0_wready, + s_axi_bresp => s_axi_ctrl_pf0_bresp, + s_axi_bvalid => s_axi_ctrl_pf0_bvalid, + s_axi_bready => s_axi_ctrl_pf0_bready, + s_axi_araddr => s_axi_ctrl_pf0_araddr, + s_axi_arvalid => s_axi_ctrl_pf0_arvalid, + s_axi_arready => s_axi_ctrl_pf0_arready, + s_axi_rdata => s_axi_ctrl_pf0_rdata, + s_axi_rresp => s_axi_ctrl_pf0_rresp, + s_axi_rvalid => s_axi_ctrl_pf0_rvalid, + s_axi_rready => s_axi_ctrl_pf0_rready + ); + + end generate G_GENERATE_PF0; + + G_GENERATE_PF1 : if (i = 1) generate + + -- Instantiate BAR Layout table + BAR_LAYOUT_TABLE_inst_1 : entity hw_discovery_v1_0_0.hw_discovery_v1_0_0_bar_layout_table + generic map ( + C_NUM_SLOTS_BAR_LAYOUT_TABLE => C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE, + C_ENTRY_TYPE_0 => C_PF1_ENTRY_TYPE_0, + C_ENTRY_BAR_0 => C_PF1_ENTRY_BAR_0, + C_ENTRY_ADDR_0 => C_PF1_ENTRY_ADDR_0, + C_ENTRY_MAJOR_VERSION_0 => C_PF1_ENTRY_MAJOR_VERSION_0, + C_ENTRY_MINOR_VERSION_0 => C_PF1_ENTRY_MINOR_VERSION_0, + C_ENTRY_VERSION_TYPE_0 => C_PF1_ENTRY_VERSION_TYPE_0, + C_ENTRY_RSVD0_0 => C_PF1_ENTRY_RSVD0_0, + C_ENTRY_TYPE_1 => C_PF1_ENTRY_TYPE_1, + C_ENTRY_BAR_1 => C_PF1_ENTRY_BAR_1, + C_ENTRY_ADDR_1 => C_PF1_ENTRY_ADDR_1, + C_ENTRY_MAJOR_VERSION_1 => C_PF1_ENTRY_MAJOR_VERSION_1, + C_ENTRY_MINOR_VERSION_1 => C_PF1_ENTRY_MINOR_VERSION_1, + C_ENTRY_VERSION_TYPE_1 => C_PF1_ENTRY_VERSION_TYPE_1, + C_ENTRY_RSVD0_1 => C_PF1_ENTRY_RSVD0_1, + C_ENTRY_TYPE_2 => C_PF1_ENTRY_TYPE_2, + C_ENTRY_BAR_2 => C_PF1_ENTRY_BAR_2, + C_ENTRY_ADDR_2 => C_PF1_ENTRY_ADDR_2, + C_ENTRY_MAJOR_VERSION_2 => C_PF1_ENTRY_MAJOR_VERSION_2, + C_ENTRY_MINOR_VERSION_2 => C_PF1_ENTRY_MINOR_VERSION_2, + C_ENTRY_VERSION_TYPE_2 => C_PF1_ENTRY_VERSION_TYPE_2, + C_ENTRY_RSVD0_2 => C_PF1_ENTRY_RSVD0_2, + C_ENTRY_TYPE_3 => C_PF1_ENTRY_TYPE_3, + C_ENTRY_BAR_3 => C_PF1_ENTRY_BAR_3, + C_ENTRY_ADDR_3 => C_PF1_ENTRY_ADDR_3, + C_ENTRY_MAJOR_VERSION_3 => C_PF1_ENTRY_MAJOR_VERSION_3, + C_ENTRY_MINOR_VERSION_3 => C_PF1_ENTRY_MINOR_VERSION_3, + C_ENTRY_VERSION_TYPE_3 => C_PF1_ENTRY_VERSION_TYPE_3, + C_ENTRY_RSVD0_3 => C_PF1_ENTRY_RSVD0_3, + C_ENTRY_TYPE_4 => C_PF1_ENTRY_TYPE_4, + C_ENTRY_BAR_4 => C_PF1_ENTRY_BAR_4, + C_ENTRY_ADDR_4 => C_PF1_ENTRY_ADDR_4, + C_ENTRY_MAJOR_VERSION_4 => C_PF1_ENTRY_MAJOR_VERSION_4, + C_ENTRY_MINOR_VERSION_4 => C_PF1_ENTRY_MINOR_VERSION_4, + C_ENTRY_VERSION_TYPE_4 => C_PF1_ENTRY_VERSION_TYPE_4, + C_ENTRY_RSVD0_4 => C_PF1_ENTRY_RSVD0_4, + C_ENTRY_TYPE_5 => C_PF1_ENTRY_TYPE_5, + C_ENTRY_BAR_5 => C_PF1_ENTRY_BAR_5, + C_ENTRY_ADDR_5 => C_PF1_ENTRY_ADDR_5, + C_ENTRY_MAJOR_VERSION_5 => C_PF1_ENTRY_MAJOR_VERSION_5, + C_ENTRY_MINOR_VERSION_5 => C_PF1_ENTRY_MINOR_VERSION_5, + C_ENTRY_VERSION_TYPE_5 => C_PF1_ENTRY_VERSION_TYPE_5, + C_ENTRY_RSVD0_5 => C_PF1_ENTRY_RSVD0_5, + C_ENTRY_TYPE_6 => C_PF1_ENTRY_TYPE_6, + C_ENTRY_BAR_6 => C_PF1_ENTRY_BAR_6, + C_ENTRY_ADDR_6 => C_PF1_ENTRY_ADDR_6, + C_ENTRY_MAJOR_VERSION_6 => C_PF1_ENTRY_MAJOR_VERSION_6, + C_ENTRY_MINOR_VERSION_6 => C_PF1_ENTRY_MINOR_VERSION_6, + C_ENTRY_VERSION_TYPE_6 => C_PF1_ENTRY_VERSION_TYPE_6, + C_ENTRY_RSVD0_6 => C_PF1_ENTRY_RSVD0_6, + C_ENTRY_TYPE_7 => C_PF1_ENTRY_TYPE_7, + C_ENTRY_BAR_7 => C_PF1_ENTRY_BAR_7, + C_ENTRY_ADDR_7 => C_PF1_ENTRY_ADDR_7, + C_ENTRY_MAJOR_VERSION_7 => C_PF1_ENTRY_MAJOR_VERSION_7, + C_ENTRY_MINOR_VERSION_7 => C_PF1_ENTRY_MINOR_VERSION_7, + C_ENTRY_VERSION_TYPE_7 => C_PF1_ENTRY_VERSION_TYPE_7, + C_ENTRY_RSVD0_7 => C_PF1_ENTRY_RSVD0_7, + C_ENTRY_TYPE_8 => C_PF1_ENTRY_TYPE_8, + C_ENTRY_BAR_8 => C_PF1_ENTRY_BAR_8, + C_ENTRY_ADDR_8 => C_PF1_ENTRY_ADDR_8, + C_ENTRY_MAJOR_VERSION_8 => C_PF1_ENTRY_MAJOR_VERSION_8, + C_ENTRY_MINOR_VERSION_8 => C_PF1_ENTRY_MINOR_VERSION_8, + C_ENTRY_VERSION_TYPE_8 => C_PF1_ENTRY_VERSION_TYPE_8, + C_ENTRY_RSVD0_8 => C_PF1_ENTRY_RSVD0_8, + C_ENTRY_TYPE_9 => C_PF1_ENTRY_TYPE_9, + C_ENTRY_BAR_9 => C_PF1_ENTRY_BAR_9, + C_ENTRY_ADDR_9 => C_PF1_ENTRY_ADDR_9, + C_ENTRY_MAJOR_VERSION_9 => C_PF1_ENTRY_MAJOR_VERSION_9, + C_ENTRY_MINOR_VERSION_9 => C_PF1_ENTRY_MINOR_VERSION_9, + C_ENTRY_VERSION_TYPE_9 => C_PF1_ENTRY_VERSION_TYPE_9, + C_ENTRY_RSVD0_9 => C_PF1_ENTRY_RSVD0_9, + C_ENTRY_TYPE_10 => C_PF1_ENTRY_TYPE_10, + C_ENTRY_BAR_10 => C_PF1_ENTRY_BAR_10, + C_ENTRY_ADDR_10 => C_PF1_ENTRY_ADDR_10, + C_ENTRY_MAJOR_VERSION_10 => C_PF1_ENTRY_MAJOR_VERSION_10, + C_ENTRY_MINOR_VERSION_10 => C_PF1_ENTRY_MINOR_VERSION_10, + C_ENTRY_VERSION_TYPE_10 => C_PF1_ENTRY_VERSION_TYPE_10, + C_ENTRY_RSVD0_10 => C_PF1_ENTRY_RSVD0_10, + C_ENTRY_TYPE_11 => C_PF1_ENTRY_TYPE_11, + C_ENTRY_BAR_11 => C_PF1_ENTRY_BAR_11, + C_ENTRY_ADDR_11 => C_PF1_ENTRY_ADDR_11, + C_ENTRY_MAJOR_VERSION_11 => C_PF1_ENTRY_MAJOR_VERSION_11, + C_ENTRY_MINOR_VERSION_11 => C_PF1_ENTRY_MINOR_VERSION_11, + C_ENTRY_VERSION_TYPE_11 => C_PF1_ENTRY_VERSION_TYPE_11, + C_ENTRY_RSVD0_11 => C_PF1_ENTRY_RSVD0_11, + C_ENTRY_TYPE_12 => C_PF1_ENTRY_TYPE_12, + C_ENTRY_BAR_12 => C_PF1_ENTRY_BAR_12, + C_ENTRY_ADDR_12 => C_PF1_ENTRY_ADDR_12, + C_ENTRY_MAJOR_VERSION_12 => C_PF1_ENTRY_MAJOR_VERSION_12, + C_ENTRY_MINOR_VERSION_12 => C_PF1_ENTRY_MINOR_VERSION_12, + C_ENTRY_VERSION_TYPE_12 => C_PF1_ENTRY_VERSION_TYPE_12, + C_ENTRY_RSVD0_12 => C_PF1_ENTRY_RSVD0_12, + C_ENTRY_TYPE_13 => C_PF1_ENTRY_TYPE_13, + C_ENTRY_BAR_13 => C_PF1_ENTRY_BAR_13, + C_ENTRY_ADDR_13 => C_PF1_ENTRY_ADDR_13, + C_ENTRY_MAJOR_VERSION_13 => C_PF1_ENTRY_MAJOR_VERSION_13, + C_ENTRY_MINOR_VERSION_13 => C_PF1_ENTRY_MINOR_VERSION_13, + C_ENTRY_VERSION_TYPE_13 => C_PF1_ENTRY_VERSION_TYPE_13, + C_ENTRY_RSVD0_13 => C_PF1_ENTRY_RSVD0_13, + C_ENTRY_TYPE_14 => C_PF1_ENTRY_TYPE_14, + C_ENTRY_BAR_14 => C_PF1_ENTRY_BAR_14, + C_ENTRY_ADDR_14 => C_PF1_ENTRY_ADDR_14, + C_ENTRY_MAJOR_VERSION_14 => C_PF1_ENTRY_MAJOR_VERSION_14, + C_ENTRY_MINOR_VERSION_14 => C_PF1_ENTRY_MINOR_VERSION_14, + C_ENTRY_VERSION_TYPE_14 => C_PF1_ENTRY_VERSION_TYPE_14, + C_ENTRY_RSVD0_14 => C_PF1_ENTRY_RSVD0_14, + C_ENTRY_TYPE_15 => C_PF1_ENTRY_TYPE_15, + C_ENTRY_BAR_15 => C_PF1_ENTRY_BAR_15, + C_ENTRY_ADDR_15 => C_PF1_ENTRY_ADDR_15, + C_ENTRY_MAJOR_VERSION_15 => C_PF1_ENTRY_MAJOR_VERSION_15, + C_ENTRY_MINOR_VERSION_15 => C_PF1_ENTRY_MINOR_VERSION_15, + C_ENTRY_VERSION_TYPE_15 => C_PF1_ENTRY_VERSION_TYPE_15, + C_ENTRY_RSVD0_15 => C_PF1_ENTRY_RSVD0_15, + C_S_AXI_DATA_WIDTH => C_PF1_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_PF1_S_AXI_ADDR_WIDTH, + C_XDEVICEFAMILY => C_XDEVICEFAMILY + ) + port map ( + s_axi_aclk => aclk_ctrl, + s_axi_aresetn => aresetn_ctrl, + s_axi_awaddr => s_axi_ctrl_pf1_awaddr, + s_axi_awvalid => s_axi_ctrl_pf1_awvalid, + s_axi_awready => s_axi_ctrl_pf1_awready, + s_axi_wdata => s_axi_ctrl_pf1_wdata, + s_axi_wstrb => s_axi_ctrl_pf1_wstrb, + s_axi_wvalid => s_axi_ctrl_pf1_wvalid, + s_axi_wready => s_axi_ctrl_pf1_wready, + s_axi_bresp => s_axi_ctrl_pf1_bresp, + s_axi_bvalid => s_axi_ctrl_pf1_bvalid, + s_axi_bready => s_axi_ctrl_pf1_bready, + s_axi_araddr => s_axi_ctrl_pf1_araddr, + s_axi_arvalid => s_axi_ctrl_pf1_arvalid, + s_axi_arready => s_axi_ctrl_pf1_arready, + s_axi_rdata => s_axi_ctrl_pf1_rdata, + s_axi_rresp => s_axi_ctrl_pf1_rresp, + s_axi_rvalid => s_axi_ctrl_pf1_rvalid, + s_axi_rready => s_axi_ctrl_pf1_rready + ); + + end generate G_GENERATE_PF1; + + G_GENERATE_PF2: if (i = 2) generate + + -- Instantiate BAR Layout table + BAR_LAYOUT_TABLE_inst_2 : entity hw_discovery_v1_0_0.hw_discovery_v1_0_0_bar_layout_table + generic map ( + C_NUM_SLOTS_BAR_LAYOUT_TABLE => C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE, + C_ENTRY_TYPE_0 => C_PF2_ENTRY_TYPE_0, + C_ENTRY_BAR_0 => C_PF2_ENTRY_BAR_0, + C_ENTRY_ADDR_0 => C_PF2_ENTRY_ADDR_0, + C_ENTRY_MAJOR_VERSION_0 => C_PF2_ENTRY_MAJOR_VERSION_0, + C_ENTRY_MINOR_VERSION_0 => C_PF2_ENTRY_MINOR_VERSION_0, + C_ENTRY_VERSION_TYPE_0 => C_PF2_ENTRY_VERSION_TYPE_0, + C_ENTRY_RSVD0_0 => C_PF2_ENTRY_RSVD0_0, + C_ENTRY_TYPE_1 => C_PF2_ENTRY_TYPE_1, + C_ENTRY_BAR_1 => C_PF2_ENTRY_BAR_1, + C_ENTRY_ADDR_1 => C_PF2_ENTRY_ADDR_1, + C_ENTRY_MAJOR_VERSION_1 => C_PF2_ENTRY_MAJOR_VERSION_1, + C_ENTRY_MINOR_VERSION_1 => C_PF2_ENTRY_MINOR_VERSION_1, + C_ENTRY_VERSION_TYPE_1 => C_PF2_ENTRY_VERSION_TYPE_1, + C_ENTRY_RSVD0_1 => C_PF2_ENTRY_RSVD0_1, + C_ENTRY_TYPE_2 => C_PF2_ENTRY_TYPE_2, + C_ENTRY_BAR_2 => C_PF2_ENTRY_BAR_2, + C_ENTRY_ADDR_2 => C_PF2_ENTRY_ADDR_2, + C_ENTRY_MAJOR_VERSION_2 => C_PF2_ENTRY_MAJOR_VERSION_2, + C_ENTRY_MINOR_VERSION_2 => C_PF2_ENTRY_MINOR_VERSION_2, + C_ENTRY_VERSION_TYPE_2 => C_PF2_ENTRY_VERSION_TYPE_2, + C_ENTRY_RSVD0_2 => C_PF2_ENTRY_RSVD0_2, + C_ENTRY_TYPE_3 => C_PF2_ENTRY_TYPE_3, + C_ENTRY_BAR_3 => C_PF2_ENTRY_BAR_3, + C_ENTRY_ADDR_3 => C_PF2_ENTRY_ADDR_3, + C_ENTRY_MAJOR_VERSION_3 => C_PF2_ENTRY_MAJOR_VERSION_3, + C_ENTRY_MINOR_VERSION_3 => C_PF2_ENTRY_MINOR_VERSION_3, + C_ENTRY_VERSION_TYPE_3 => C_PF2_ENTRY_VERSION_TYPE_3, + C_ENTRY_RSVD0_3 => C_PF2_ENTRY_RSVD0_3, + C_ENTRY_TYPE_4 => C_PF2_ENTRY_TYPE_4, + C_ENTRY_BAR_4 => C_PF2_ENTRY_BAR_4, + C_ENTRY_ADDR_4 => C_PF2_ENTRY_ADDR_4, + C_ENTRY_MAJOR_VERSION_4 => C_PF2_ENTRY_MAJOR_VERSION_4, + C_ENTRY_MINOR_VERSION_4 => C_PF2_ENTRY_MINOR_VERSION_4, + C_ENTRY_VERSION_TYPE_4 => C_PF2_ENTRY_VERSION_TYPE_4, + C_ENTRY_RSVD0_4 => C_PF2_ENTRY_RSVD0_4, + C_ENTRY_TYPE_5 => C_PF2_ENTRY_TYPE_5, + C_ENTRY_BAR_5 => C_PF2_ENTRY_BAR_5, + C_ENTRY_ADDR_5 => C_PF2_ENTRY_ADDR_5, + C_ENTRY_MAJOR_VERSION_5 => C_PF2_ENTRY_MAJOR_VERSION_5, + C_ENTRY_MINOR_VERSION_5 => C_PF2_ENTRY_MINOR_VERSION_5, + C_ENTRY_VERSION_TYPE_5 => C_PF2_ENTRY_VERSION_TYPE_5, + C_ENTRY_RSVD0_5 => C_PF2_ENTRY_RSVD0_5, + C_ENTRY_TYPE_6 => C_PF2_ENTRY_TYPE_6, + C_ENTRY_BAR_6 => C_PF2_ENTRY_BAR_6, + C_ENTRY_ADDR_6 => C_PF2_ENTRY_ADDR_6, + C_ENTRY_MAJOR_VERSION_6 => C_PF2_ENTRY_MAJOR_VERSION_6, + C_ENTRY_MINOR_VERSION_6 => C_PF2_ENTRY_MINOR_VERSION_6, + C_ENTRY_VERSION_TYPE_6 => C_PF2_ENTRY_VERSION_TYPE_6, + C_ENTRY_RSVD0_6 => C_PF2_ENTRY_RSVD0_6, + C_ENTRY_TYPE_7 => C_PF2_ENTRY_TYPE_7, + C_ENTRY_BAR_7 => C_PF2_ENTRY_BAR_7, + C_ENTRY_ADDR_7 => C_PF2_ENTRY_ADDR_7, + C_ENTRY_MAJOR_VERSION_7 => C_PF2_ENTRY_MAJOR_VERSION_7, + C_ENTRY_MINOR_VERSION_7 => C_PF2_ENTRY_MINOR_VERSION_7, + C_ENTRY_VERSION_TYPE_7 => C_PF2_ENTRY_VERSION_TYPE_7, + C_ENTRY_RSVD0_7 => C_PF2_ENTRY_RSVD0_7, + C_ENTRY_TYPE_8 => C_PF2_ENTRY_TYPE_8, + C_ENTRY_BAR_8 => C_PF2_ENTRY_BAR_8, + C_ENTRY_ADDR_8 => C_PF2_ENTRY_ADDR_8, + C_ENTRY_MAJOR_VERSION_8 => C_PF2_ENTRY_MAJOR_VERSION_8, + C_ENTRY_MINOR_VERSION_8 => C_PF2_ENTRY_MINOR_VERSION_8, + C_ENTRY_VERSION_TYPE_8 => C_PF2_ENTRY_VERSION_TYPE_8, + C_ENTRY_RSVD0_8 => C_PF2_ENTRY_RSVD0_8, + C_ENTRY_TYPE_9 => C_PF2_ENTRY_TYPE_9, + C_ENTRY_BAR_9 => C_PF2_ENTRY_BAR_9, + C_ENTRY_ADDR_9 => C_PF2_ENTRY_ADDR_9, + C_ENTRY_MAJOR_VERSION_9 => C_PF2_ENTRY_MAJOR_VERSION_9, + C_ENTRY_MINOR_VERSION_9 => C_PF2_ENTRY_MINOR_VERSION_9, + C_ENTRY_VERSION_TYPE_9 => C_PF2_ENTRY_VERSION_TYPE_9, + C_ENTRY_RSVD0_9 => C_PF2_ENTRY_RSVD0_9, + C_ENTRY_TYPE_10 => C_PF2_ENTRY_TYPE_10, + C_ENTRY_BAR_10 => C_PF2_ENTRY_BAR_10, + C_ENTRY_ADDR_10 => C_PF2_ENTRY_ADDR_10, + C_ENTRY_MAJOR_VERSION_10 => C_PF2_ENTRY_MAJOR_VERSION_10, + C_ENTRY_MINOR_VERSION_10 => C_PF2_ENTRY_MINOR_VERSION_10, + C_ENTRY_VERSION_TYPE_10 => C_PF2_ENTRY_VERSION_TYPE_10, + C_ENTRY_RSVD0_10 => C_PF2_ENTRY_RSVD0_10, + C_ENTRY_TYPE_11 => C_PF2_ENTRY_TYPE_11, + C_ENTRY_BAR_11 => C_PF2_ENTRY_BAR_11, + C_ENTRY_ADDR_11 => C_PF2_ENTRY_ADDR_11, + C_ENTRY_MAJOR_VERSION_11 => C_PF2_ENTRY_MAJOR_VERSION_11, + C_ENTRY_MINOR_VERSION_11 => C_PF2_ENTRY_MINOR_VERSION_11, + C_ENTRY_VERSION_TYPE_11 => C_PF2_ENTRY_VERSION_TYPE_11, + C_ENTRY_RSVD0_11 => C_PF2_ENTRY_RSVD0_11, + C_ENTRY_TYPE_12 => C_PF2_ENTRY_TYPE_12, + C_ENTRY_BAR_12 => C_PF2_ENTRY_BAR_12, + C_ENTRY_ADDR_12 => C_PF2_ENTRY_ADDR_12, + C_ENTRY_MAJOR_VERSION_12 => C_PF2_ENTRY_MAJOR_VERSION_12, + C_ENTRY_MINOR_VERSION_12 => C_PF2_ENTRY_MINOR_VERSION_12, + C_ENTRY_VERSION_TYPE_12 => C_PF2_ENTRY_VERSION_TYPE_12, + C_ENTRY_RSVD0_12 => C_PF2_ENTRY_RSVD0_12, + C_ENTRY_TYPE_13 => C_PF2_ENTRY_TYPE_13, + C_ENTRY_BAR_13 => C_PF2_ENTRY_BAR_13, + C_ENTRY_ADDR_13 => C_PF2_ENTRY_ADDR_13, + C_ENTRY_MAJOR_VERSION_13 => C_PF2_ENTRY_MAJOR_VERSION_13, + C_ENTRY_MINOR_VERSION_13 => C_PF2_ENTRY_MINOR_VERSION_13, + C_ENTRY_VERSION_TYPE_13 => C_PF2_ENTRY_VERSION_TYPE_13, + C_ENTRY_RSVD0_13 => C_PF2_ENTRY_RSVD0_13, + C_ENTRY_TYPE_14 => C_PF2_ENTRY_TYPE_14, + C_ENTRY_BAR_14 => C_PF2_ENTRY_BAR_14, + C_ENTRY_ADDR_14 => C_PF2_ENTRY_ADDR_14, + C_ENTRY_MAJOR_VERSION_14 => C_PF2_ENTRY_MAJOR_VERSION_14, + C_ENTRY_MINOR_VERSION_14 => C_PF2_ENTRY_MINOR_VERSION_14, + C_ENTRY_VERSION_TYPE_14 => C_PF2_ENTRY_VERSION_TYPE_14, + C_ENTRY_RSVD0_14 => C_PF2_ENTRY_RSVD0_14, + C_ENTRY_TYPE_15 => C_PF2_ENTRY_TYPE_15, + C_ENTRY_BAR_15 => C_PF2_ENTRY_BAR_15, + C_ENTRY_ADDR_15 => C_PF2_ENTRY_ADDR_15, + C_ENTRY_MAJOR_VERSION_15 => C_PF2_ENTRY_MAJOR_VERSION_15, + C_ENTRY_MINOR_VERSION_15 => C_PF2_ENTRY_MINOR_VERSION_15, + C_ENTRY_VERSION_TYPE_15 => C_PF2_ENTRY_VERSION_TYPE_15, + C_ENTRY_RSVD0_15 => C_PF2_ENTRY_RSVD0_15, + C_S_AXI_DATA_WIDTH => C_PF2_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_PF2_S_AXI_ADDR_WIDTH, + C_XDEVICEFAMILY => C_XDEVICEFAMILY + ) + port map ( + s_axi_aclk => aclk_ctrl, + s_axi_aresetn => aresetn_ctrl, + s_axi_awaddr => s_axi_ctrl_pf2_awaddr, + s_axi_awvalid => s_axi_ctrl_pf2_awvalid, + s_axi_awready => s_axi_ctrl_pf2_awready, + s_axi_wdata => s_axi_ctrl_pf2_wdata, + s_axi_wstrb => s_axi_ctrl_pf2_wstrb, + s_axi_wvalid => s_axi_ctrl_pf2_wvalid, + s_axi_wready => s_axi_ctrl_pf2_wready, + s_axi_bresp => s_axi_ctrl_pf2_bresp, + s_axi_bvalid => s_axi_ctrl_pf2_bvalid, + s_axi_bready => s_axi_ctrl_pf2_bready, + s_axi_araddr => s_axi_ctrl_pf2_araddr, + s_axi_arvalid => s_axi_ctrl_pf2_arvalid, + s_axi_arready => s_axi_ctrl_pf2_arready, + s_axi_rdata => s_axi_ctrl_pf2_rdata, + s_axi_rresp => s_axi_ctrl_pf2_rresp, + s_axi_rvalid => s_axi_ctrl_pf2_rvalid, + s_axi_rready => s_axi_ctrl_pf2_rready + ); + + end generate G_GENERATE_PF2; + + G_GENERATE_PF3 : if (i = 3) generate + + -- Instantiate BAR Layout table + BAR_LAYOUT_TABLE_inst_3 : entity hw_discovery_v1_0_0.hw_discovery_v1_0_0_bar_layout_table + generic map ( + C_NUM_SLOTS_BAR_LAYOUT_TABLE => C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE, + C_ENTRY_TYPE_0 => C_PF3_ENTRY_TYPE_0, + C_ENTRY_BAR_0 => C_PF3_ENTRY_BAR_0, + C_ENTRY_ADDR_0 => C_PF3_ENTRY_ADDR_0, + C_ENTRY_MAJOR_VERSION_0 => C_PF3_ENTRY_MAJOR_VERSION_0, + C_ENTRY_MINOR_VERSION_0 => C_PF3_ENTRY_MINOR_VERSION_0, + C_ENTRY_VERSION_TYPE_0 => C_PF3_ENTRY_VERSION_TYPE_0, + C_ENTRY_RSVD0_0 => C_PF3_ENTRY_RSVD0_0, + C_ENTRY_TYPE_1 => C_PF3_ENTRY_TYPE_1, + C_ENTRY_BAR_1 => C_PF3_ENTRY_BAR_1, + C_ENTRY_ADDR_1 => C_PF3_ENTRY_ADDR_1, + C_ENTRY_MAJOR_VERSION_1 => C_PF3_ENTRY_MAJOR_VERSION_1, + C_ENTRY_MINOR_VERSION_1 => C_PF3_ENTRY_MINOR_VERSION_1, + C_ENTRY_VERSION_TYPE_1 => C_PF3_ENTRY_VERSION_TYPE_1, + C_ENTRY_RSVD0_1 => C_PF3_ENTRY_RSVD0_1, + C_ENTRY_TYPE_2 => C_PF3_ENTRY_TYPE_2, + C_ENTRY_BAR_2 => C_PF3_ENTRY_BAR_2, + C_ENTRY_ADDR_2 => C_PF3_ENTRY_ADDR_2, + C_ENTRY_MAJOR_VERSION_2 => C_PF3_ENTRY_MAJOR_VERSION_2, + C_ENTRY_MINOR_VERSION_2 => C_PF3_ENTRY_MINOR_VERSION_2, + C_ENTRY_VERSION_TYPE_2 => C_PF3_ENTRY_VERSION_TYPE_2, + C_ENTRY_RSVD0_2 => C_PF3_ENTRY_RSVD0_2, + C_ENTRY_TYPE_3 => C_PF3_ENTRY_TYPE_3, + C_ENTRY_BAR_3 => C_PF3_ENTRY_BAR_3, + C_ENTRY_ADDR_3 => C_PF3_ENTRY_ADDR_3, + C_ENTRY_MAJOR_VERSION_3 => C_PF3_ENTRY_MAJOR_VERSION_3, + C_ENTRY_MINOR_VERSION_3 => C_PF3_ENTRY_MINOR_VERSION_3, + C_ENTRY_VERSION_TYPE_3 => C_PF3_ENTRY_VERSION_TYPE_3, + C_ENTRY_RSVD0_3 => C_PF3_ENTRY_RSVD0_3, + C_ENTRY_TYPE_4 => C_PF3_ENTRY_TYPE_4, + C_ENTRY_BAR_4 => C_PF3_ENTRY_BAR_4, + C_ENTRY_ADDR_4 => C_PF3_ENTRY_ADDR_4, + C_ENTRY_MAJOR_VERSION_4 => C_PF3_ENTRY_MAJOR_VERSION_4, + C_ENTRY_MINOR_VERSION_4 => C_PF3_ENTRY_MINOR_VERSION_4, + C_ENTRY_VERSION_TYPE_4 => C_PF3_ENTRY_VERSION_TYPE_4, + C_ENTRY_RSVD0_4 => C_PF3_ENTRY_RSVD0_4, + C_ENTRY_TYPE_5 => C_PF3_ENTRY_TYPE_5, + C_ENTRY_BAR_5 => C_PF3_ENTRY_BAR_5, + C_ENTRY_ADDR_5 => C_PF3_ENTRY_ADDR_5, + C_ENTRY_MAJOR_VERSION_5 => C_PF3_ENTRY_MAJOR_VERSION_5, + C_ENTRY_MINOR_VERSION_5 => C_PF3_ENTRY_MINOR_VERSION_5, + C_ENTRY_VERSION_TYPE_5 => C_PF3_ENTRY_VERSION_TYPE_5, + C_ENTRY_RSVD0_5 => C_PF3_ENTRY_RSVD0_5, + C_ENTRY_TYPE_6 => C_PF3_ENTRY_TYPE_6, + C_ENTRY_BAR_6 => C_PF3_ENTRY_BAR_6, + C_ENTRY_ADDR_6 => C_PF3_ENTRY_ADDR_6, + C_ENTRY_MAJOR_VERSION_6 => C_PF3_ENTRY_MAJOR_VERSION_6, + C_ENTRY_MINOR_VERSION_6 => C_PF3_ENTRY_MINOR_VERSION_6, + C_ENTRY_VERSION_TYPE_6 => C_PF3_ENTRY_VERSION_TYPE_6, + C_ENTRY_RSVD0_6 => C_PF3_ENTRY_RSVD0_6, + C_ENTRY_TYPE_7 => C_PF3_ENTRY_TYPE_7, + C_ENTRY_BAR_7 => C_PF3_ENTRY_BAR_7, + C_ENTRY_ADDR_7 => C_PF3_ENTRY_ADDR_7, + C_ENTRY_MAJOR_VERSION_7 => C_PF3_ENTRY_MAJOR_VERSION_7, + C_ENTRY_MINOR_VERSION_7 => C_PF3_ENTRY_MINOR_VERSION_7, + C_ENTRY_VERSION_TYPE_7 => C_PF3_ENTRY_VERSION_TYPE_7, + C_ENTRY_RSVD0_7 => C_PF3_ENTRY_RSVD0_7, + C_ENTRY_TYPE_8 => C_PF3_ENTRY_TYPE_8, + C_ENTRY_BAR_8 => C_PF3_ENTRY_BAR_8, + C_ENTRY_ADDR_8 => C_PF3_ENTRY_ADDR_8, + C_ENTRY_MAJOR_VERSION_8 => C_PF3_ENTRY_MAJOR_VERSION_8, + C_ENTRY_MINOR_VERSION_8 => C_PF3_ENTRY_MINOR_VERSION_8, + C_ENTRY_VERSION_TYPE_8 => C_PF3_ENTRY_VERSION_TYPE_8, + C_ENTRY_RSVD0_8 => C_PF3_ENTRY_RSVD0_8, + C_ENTRY_TYPE_9 => C_PF3_ENTRY_TYPE_9, + C_ENTRY_BAR_9 => C_PF3_ENTRY_BAR_9, + C_ENTRY_ADDR_9 => C_PF3_ENTRY_ADDR_9, + C_ENTRY_MAJOR_VERSION_9 => C_PF3_ENTRY_MAJOR_VERSION_9, + C_ENTRY_MINOR_VERSION_9 => C_PF3_ENTRY_MINOR_VERSION_9, + C_ENTRY_VERSION_TYPE_9 => C_PF3_ENTRY_VERSION_TYPE_9, + C_ENTRY_RSVD0_9 => C_PF3_ENTRY_RSVD0_9, + C_ENTRY_TYPE_10 => C_PF3_ENTRY_TYPE_10, + C_ENTRY_BAR_10 => C_PF3_ENTRY_BAR_10, + C_ENTRY_ADDR_10 => C_PF3_ENTRY_ADDR_10, + C_ENTRY_MAJOR_VERSION_10 => C_PF3_ENTRY_MAJOR_VERSION_10, + C_ENTRY_MINOR_VERSION_10 => C_PF3_ENTRY_MINOR_VERSION_10, + C_ENTRY_VERSION_TYPE_10 => C_PF3_ENTRY_VERSION_TYPE_10, + C_ENTRY_RSVD0_10 => C_PF3_ENTRY_RSVD0_10, + C_ENTRY_TYPE_11 => C_PF3_ENTRY_TYPE_11, + C_ENTRY_BAR_11 => C_PF3_ENTRY_BAR_11, + C_ENTRY_ADDR_11 => C_PF3_ENTRY_ADDR_11, + C_ENTRY_MAJOR_VERSION_11 => C_PF3_ENTRY_MAJOR_VERSION_11, + C_ENTRY_MINOR_VERSION_11 => C_PF3_ENTRY_MINOR_VERSION_11, + C_ENTRY_VERSION_TYPE_11 => C_PF3_ENTRY_VERSION_TYPE_11, + C_ENTRY_RSVD0_11 => C_PF3_ENTRY_RSVD0_11, + C_ENTRY_TYPE_12 => C_PF3_ENTRY_TYPE_12, + C_ENTRY_BAR_12 => C_PF3_ENTRY_BAR_12, + C_ENTRY_ADDR_12 => C_PF3_ENTRY_ADDR_12, + C_ENTRY_MAJOR_VERSION_12 => C_PF3_ENTRY_MAJOR_VERSION_12, + C_ENTRY_MINOR_VERSION_12 => C_PF3_ENTRY_MINOR_VERSION_12, + C_ENTRY_VERSION_TYPE_12 => C_PF3_ENTRY_VERSION_TYPE_12, + C_ENTRY_RSVD0_12 => C_PF3_ENTRY_RSVD0_12, + C_ENTRY_TYPE_13 => C_PF3_ENTRY_TYPE_13, + C_ENTRY_BAR_13 => C_PF3_ENTRY_BAR_13, + C_ENTRY_ADDR_13 => C_PF3_ENTRY_ADDR_13, + C_ENTRY_MAJOR_VERSION_13 => C_PF3_ENTRY_MAJOR_VERSION_13, + C_ENTRY_MINOR_VERSION_13 => C_PF3_ENTRY_MINOR_VERSION_13, + C_ENTRY_VERSION_TYPE_13 => C_PF3_ENTRY_VERSION_TYPE_13, + C_ENTRY_RSVD0_13 => C_PF3_ENTRY_RSVD0_13, + C_ENTRY_TYPE_14 => C_PF3_ENTRY_TYPE_14, + C_ENTRY_BAR_14 => C_PF3_ENTRY_BAR_14, + C_ENTRY_ADDR_14 => C_PF3_ENTRY_ADDR_14, + C_ENTRY_MAJOR_VERSION_14 => C_PF3_ENTRY_MAJOR_VERSION_14, + C_ENTRY_MINOR_VERSION_14 => C_PF3_ENTRY_MINOR_VERSION_14, + C_ENTRY_VERSION_TYPE_14 => C_PF3_ENTRY_VERSION_TYPE_14, + C_ENTRY_RSVD0_14 => C_PF3_ENTRY_RSVD0_14, + C_ENTRY_TYPE_15 => C_PF3_ENTRY_TYPE_15, + C_ENTRY_BAR_15 => C_PF3_ENTRY_BAR_15, + C_ENTRY_ADDR_15 => C_PF3_ENTRY_ADDR_15, + C_ENTRY_MAJOR_VERSION_15 => C_PF3_ENTRY_MAJOR_VERSION_15, + C_ENTRY_MINOR_VERSION_15 => C_PF3_ENTRY_MINOR_VERSION_15, + C_ENTRY_VERSION_TYPE_15 => C_PF3_ENTRY_VERSION_TYPE_15, + C_ENTRY_RSVD0_15 => C_PF3_ENTRY_RSVD0_15, + C_S_AXI_DATA_WIDTH => C_PF3_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_PF3_S_AXI_ADDR_WIDTH, + C_XDEVICEFAMILY => C_XDEVICEFAMILY + ) + port map ( + s_axi_aclk => aclk_ctrl, + s_axi_aresetn => aresetn_ctrl, + s_axi_awaddr => s_axi_ctrl_pf3_awaddr, + s_axi_awvalid => s_axi_ctrl_pf3_awvalid, + s_axi_awready => s_axi_ctrl_pf3_awready, + s_axi_wdata => s_axi_ctrl_pf3_wdata, + s_axi_wstrb => s_axi_ctrl_pf3_wstrb, + s_axi_wvalid => s_axi_ctrl_pf3_wvalid, + s_axi_wready => s_axi_ctrl_pf3_wready, + s_axi_bresp => s_axi_ctrl_pf3_bresp, + s_axi_bvalid => s_axi_ctrl_pf3_bvalid, + s_axi_bready => s_axi_ctrl_pf3_bready, + s_axi_araddr => s_axi_ctrl_pf3_araddr, + s_axi_arvalid => s_axi_ctrl_pf3_arvalid, + s_axi_arready => s_axi_ctrl_pf3_arready, + s_axi_rdata => s_axi_ctrl_pf3_rdata, + s_axi_rresp => s_axi_ctrl_pf3_rresp, + s_axi_rvalid => s_axi_ctrl_pf3_rvalid, + s_axi_rready => s_axi_ctrl_pf3_rready + ); + + end generate G_GENERATE_PF3; + + end generate G_GENERATE; + +end architecture rtl; diff --git a/linker/resources/base/iprepo/hw_discovery_v1_0/hdl/hw_discovery.v b/linker/resources/base/iprepo/hw_discovery_v1_0/hdl/hw_discovery.v new file mode 100644 index 00000000..88d32f60 --- /dev/null +++ b/linker/resources/base/iprepo/hw_discovery_v1_0/hdl/hw_discovery.v @@ -0,0 +1,1054 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//-------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module hw_discovery_v1_0_0_hw_discovery #( + parameter integer C_NUM_PFS = 1, + parameter [11:0] C_CAP_BASE_ADDR = 12'h0, + parameter [11:0] C_NEXT_CAP_ADDR = 12'h0, + parameter integer C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE = 1, + parameter integer C_PF0_BAR_INDEX = 0, + parameter [27:0] C_PF0_LOW_OFFSET = 28'h0, + parameter [31:0] C_PF0_HIGH_OFFSET = 32'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_0 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_0 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_0 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_0 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_0 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_0 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_0 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_1 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_1 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_1 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_1 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_1 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_1 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_1 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_2 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_2 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_2 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_2 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_2 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_2 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_2 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_3 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_3 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_3 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_3 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_3 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_3 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_3 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_4 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_4 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_4 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_4 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_4 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_4 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_4 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_5 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_5 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_5 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_5 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_5 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_5 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_5 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_6 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_6 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_6 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_6 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_6 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_6 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_6 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_7 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_7 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_7 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_7 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_7 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_7 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_7 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_8 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_8 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_8 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_8 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_8 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_8 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_8 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_9 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_9 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_9 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_9 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_9 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_9 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_9 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_10 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_10 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_10 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_10 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_10 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_10 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_10 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_11 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_11 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_11 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_11 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_11 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_11 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_11 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_12 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_12 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_12 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_12 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_12 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_12 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_12 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_13 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_13 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_13 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_13 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_13 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_13 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_13 = 4'h0, + parameter integer C_PF0_S_AXI_ADDR_WIDTH = 32, + parameter integer C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE = 1, + parameter integer C_PF1_BAR_INDEX = 0, + parameter [27:0] C_PF1_LOW_OFFSET = 28'h0, + parameter [31:0] C_PF1_HIGH_OFFSET = 32'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_0 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_0 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_0 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_0 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_0 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_0 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_0 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_1 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_1 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_1 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_1 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_1 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_1 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_1 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_2 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_2 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_2 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_2 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_2 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_2 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_2 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_3 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_3 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_3 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_3 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_3 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_3 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_3 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_4 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_4 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_4 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_4 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_4 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_4 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_4 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_5 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_5 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_5 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_5 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_5 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_5 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_5 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_6 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_6 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_6 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_6 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_6 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_6 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_6 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_7 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_7 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_7 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_7 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_7 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_7 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_7 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_8 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_8 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_8 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_8 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_8 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_8 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_8 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_9 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_9 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_9 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_9 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_9 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_9 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_9 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_10 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_10 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_10 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_10 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_10 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_10 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_10 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_11 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_11 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_11 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_11 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_11 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_11 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_11 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_12 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_12 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_12 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_12 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_12 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_12 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_12 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_13 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_13 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_13 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_13 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_13 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_13 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_13 = 4'h0, + parameter integer C_PF1_S_AXI_ADDR_WIDTH = 32, + parameter integer C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE = 1, + parameter integer C_PF2_BAR_INDEX = 0, + parameter [27:0] C_PF2_LOW_OFFSET = 28'h0, + parameter [31:0] C_PF2_HIGH_OFFSET = 32'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_0 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_0 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_0 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_0 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_0 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_0 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_0 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_1 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_1 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_1 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_1 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_1 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_1 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_1 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_2 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_2 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_2 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_2 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_2 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_2 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_2 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_3 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_3 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_3 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_3 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_3 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_3 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_3 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_4 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_4 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_4 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_4 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_4 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_4 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_4 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_5 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_5 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_5 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_5 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_5 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_5 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_5 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_6 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_6 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_6 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_6 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_6 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_6 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_6 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_7 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_7 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_7 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_7 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_7 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_7 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_7 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_8 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_8 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_8 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_8 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_8 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_8 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_8 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_9 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_9 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_9 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_9 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_9 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_9 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_9 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_10 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_10 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_10 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_10 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_10 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_10 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_10 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_11 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_11 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_11 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_11 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_11 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_11 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_11 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_12 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_12 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_12 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_12 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_12 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_12 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_12 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_13 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_13 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_13 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_13 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_13 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_13 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_13 = 4'h0, + parameter integer C_PF2_S_AXI_ADDR_WIDTH = 32, + parameter integer C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE = 1, + parameter integer C_PF3_BAR_INDEX = 0, + parameter [27:0] C_PF3_LOW_OFFSET = 28'h0, + parameter [31:0] C_PF3_HIGH_OFFSET = 32'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_0 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_0 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_0 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_0 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_0 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_0 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_0 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_1 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_1 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_1 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_1 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_1 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_1 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_1 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_2 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_2 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_2 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_2 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_2 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_2 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_2 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_3 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_3 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_3 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_3 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_3 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_3 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_3 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_4 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_4 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_4 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_4 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_4 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_4 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_4 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_5 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_5 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_5 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_5 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_5 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_5 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_5 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_6 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_6 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_6 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_6 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_6 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_6 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_6 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_7 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_7 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_7 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_7 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_7 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_7 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_7 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_8 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_8 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_8 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_8 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_8 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_8 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_8 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_9 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_9 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_9 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_9 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_9 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_9 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_9 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_10 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_10 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_10 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_10 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_10 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_10 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_10 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_11 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_11 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_11 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_11 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_11 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_11 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_11 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_12 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_12 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_12 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_12 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_12 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_12 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_12 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_13 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_13 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_13 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_13 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_13 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_13 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_13 = 4'h0, + parameter integer C_PF3_S_AXI_ADDR_WIDTH = 32, + parameter C_XDEVICEFAMILY = "no_family" + ) + ( + // Clocks & Resets + input wire aclk_pcie, + input wire aresetn_pcie, + input wire aclk_ctrl, + input wire aresetn_ctrl, + + // slave pcie4_cfg_ext Interface (aclk_pcie) + input wire [15:0] s_pcie4_cfg_ext_function_number, + output wire [31:0] s_pcie4_cfg_ext_read_data, + output wire s_pcie4_cfg_ext_read_data_valid, + input wire s_pcie4_cfg_ext_read_received, + input wire [9:0] s_pcie4_cfg_ext_register_number, + input wire [3:0] s_pcie4_cfg_ext_write_byte_enable, + input wire [31:0] s_pcie4_cfg_ext_write_data, + input wire s_pcie4_cfg_ext_write_received, + + // slave pcie4_cfg_ext Interface (aclk_pcie) + output wire [15:0] m_pcie4_cfg_ext_function_number, + input wire [31:0] m_pcie4_cfg_ext_read_data, + input wire m_pcie4_cfg_ext_read_data_valid, + output wire m_pcie4_cfg_ext_read_received, + output wire [9:0] m_pcie4_cfg_ext_register_number, + output wire [3:0] m_pcie4_cfg_ext_write_byte_enable, + output wire [31:0] m_pcie4_cfg_ext_write_data, + output wire m_pcie4_cfg_ext_write_received, + + // AXI Interface (aclk_ctrl) for PF0 + input wire [C_PF0_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf0_awaddr, + input wire s_axi_ctrl_pf0_awvalid, + output wire s_axi_ctrl_pf0_awready, + input wire [32-1:0] s_axi_ctrl_pf0_wdata, + input wire [32/8-1:0] s_axi_ctrl_pf0_wstrb, + input wire s_axi_ctrl_pf0_wvalid, + output wire s_axi_ctrl_pf0_wready, + output wire [1:0] s_axi_ctrl_pf0_bresp, + output wire s_axi_ctrl_pf0_bvalid, + input wire s_axi_ctrl_pf0_bready, + input wire [C_PF0_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf0_araddr, + input wire s_axi_ctrl_pf0_arvalid, + output wire s_axi_ctrl_pf0_arready, + output wire [32-1:0] s_axi_ctrl_pf0_rdata, + output wire [1:0] s_axi_ctrl_pf0_rresp, + output wire s_axi_ctrl_pf0_rvalid, + input wire s_axi_ctrl_pf0_rready, + + // AXI Interface (aclk_ctrl) for PF1 + input wire [C_PF1_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf1_awaddr, + input wire s_axi_ctrl_pf1_awvalid, + output wire s_axi_ctrl_pf1_awready, + input wire [32-1:0] s_axi_ctrl_pf1_wdata, + input wire [32/8-1:0] s_axi_ctrl_pf1_wstrb, + input wire s_axi_ctrl_pf1_wvalid, + output wire s_axi_ctrl_pf1_wready, + output wire [1:0] s_axi_ctrl_pf1_bresp, + output wire s_axi_ctrl_pf1_bvalid, + input wire s_axi_ctrl_pf1_bready, + input wire [C_PF1_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf1_araddr, + input wire s_axi_ctrl_pf1_arvalid, + output wire s_axi_ctrl_pf1_arready, + output wire [32-1:0] s_axi_ctrl_pf1_rdata, + output wire [1:0] s_axi_ctrl_pf1_rresp, + output wire s_axi_ctrl_pf1_rvalid, + input wire s_axi_ctrl_pf1_rready, + + // AXI Interface (aclk_ctrl) for PF2 + input wire [C_PF2_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf2_awaddr, + input wire s_axi_ctrl_pf2_awvalid, + output wire s_axi_ctrl_pf2_awready, + input wire [32-1:0] s_axi_ctrl_pf2_wdata, + input wire [32/8-1:0] s_axi_ctrl_pf2_wstrb, + input wire s_axi_ctrl_pf2_wvalid, + output wire s_axi_ctrl_pf2_wready, + output wire [1:0] s_axi_ctrl_pf2_bresp, + output wire s_axi_ctrl_pf2_bvalid, + input wire s_axi_ctrl_pf2_bready, + input wire [C_PF2_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf2_araddr, + input wire s_axi_ctrl_pf2_arvalid, + output wire s_axi_ctrl_pf2_arready, + output wire [32-1:0] s_axi_ctrl_pf2_rdata, + output wire [1:0] s_axi_ctrl_pf2_rresp, + output wire s_axi_ctrl_pf2_rvalid, + input wire s_axi_ctrl_pf2_rready, + + // AXI Interface (aclk_ctrl) for PF3 + input wire [C_PF3_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf3_awaddr, + input wire s_axi_ctrl_pf3_awvalid, + output wire s_axi_ctrl_pf3_awready, + input wire [32-1:0] s_axi_ctrl_pf3_wdata, + input wire [32/8-1:0] s_axi_ctrl_pf3_wstrb, + input wire s_axi_ctrl_pf3_wvalid, + output wire s_axi_ctrl_pf3_wready, + output wire [1:0] s_axi_ctrl_pf3_bresp, + output wire s_axi_ctrl_pf3_bvalid, + input wire s_axi_ctrl_pf3_bready, + input wire [C_PF3_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf3_araddr, + input wire s_axi_ctrl_pf3_arvalid, + output wire s_axi_ctrl_pf3_arready, + output wire [32-1:0] s_axi_ctrl_pf3_rdata, + output wire [1:0] s_axi_ctrl_pf3_rresp, + output wire s_axi_ctrl_pf3_rvalid, + input wire s_axi_ctrl_pf3_rready + ); + + hw_discovery_v1_0_0_hw_disc #( + .C_NUM_PFS (C_NUM_PFS ), + .C_CAP_BASE_ADDR (C_CAP_BASE_ADDR ), + .C_NEXT_CAP_ADDR (C_NEXT_CAP_ADDR ), + .C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE (C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE ), + .C_PF0_BAR_INDEX (C_PF0_BAR_INDEX ), + .C_PF0_LOW_OFFSET (C_PF0_LOW_OFFSET ), + .C_PF0_HIGH_OFFSET (C_PF0_HIGH_OFFSET ), + .C_PF0_ENTRY_TYPE_0 (C_PF0_ENTRY_TYPE_0 ), + .C_PF0_ENTRY_BAR_0 (C_PF0_ENTRY_BAR_0 ), + .C_PF0_ENTRY_ADDR_0 (C_PF0_ENTRY_ADDR_0 ), + .C_PF0_ENTRY_MAJOR_VERSION_0 (C_PF0_ENTRY_MAJOR_VERSION_0 ), + .C_PF0_ENTRY_MINOR_VERSION_0 (C_PF0_ENTRY_MINOR_VERSION_0 ), + .C_PF0_ENTRY_VERSION_TYPE_0 (C_PF0_ENTRY_VERSION_TYPE_0 ), + .C_PF0_ENTRY_RSVD0_0 (C_PF0_ENTRY_RSVD0_0 ), + .C_PF0_ENTRY_TYPE_1 (C_PF0_ENTRY_TYPE_1 ), + .C_PF0_ENTRY_BAR_1 (C_PF0_ENTRY_BAR_1 ), + .C_PF0_ENTRY_ADDR_1 (C_PF0_ENTRY_ADDR_1 ), + .C_PF0_ENTRY_MAJOR_VERSION_1 (C_PF0_ENTRY_MAJOR_VERSION_1 ), + .C_PF0_ENTRY_MINOR_VERSION_1 (C_PF0_ENTRY_MINOR_VERSION_1 ), + .C_PF0_ENTRY_VERSION_TYPE_1 (C_PF0_ENTRY_VERSION_TYPE_1 ), + .C_PF0_ENTRY_RSVD0_1 (C_PF0_ENTRY_RSVD0_1 ), + .C_PF0_ENTRY_TYPE_2 (C_PF0_ENTRY_TYPE_2 ), + .C_PF0_ENTRY_BAR_2 (C_PF0_ENTRY_BAR_2 ), + .C_PF0_ENTRY_ADDR_2 (C_PF0_ENTRY_ADDR_2 ), + .C_PF0_ENTRY_MAJOR_VERSION_2 (C_PF0_ENTRY_MAJOR_VERSION_2 ), + .C_PF0_ENTRY_MINOR_VERSION_2 (C_PF0_ENTRY_MINOR_VERSION_2 ), + .C_PF0_ENTRY_VERSION_TYPE_2 (C_PF0_ENTRY_VERSION_TYPE_2 ), + .C_PF0_ENTRY_RSVD0_2 (C_PF0_ENTRY_RSVD0_2 ), + .C_PF0_ENTRY_TYPE_3 (C_PF0_ENTRY_TYPE_3 ), + .C_PF0_ENTRY_BAR_3 (C_PF0_ENTRY_BAR_3 ), + .C_PF0_ENTRY_ADDR_3 (C_PF0_ENTRY_ADDR_3 ), + .C_PF0_ENTRY_MAJOR_VERSION_3 (C_PF0_ENTRY_MAJOR_VERSION_3 ), + .C_PF0_ENTRY_MINOR_VERSION_3 (C_PF0_ENTRY_MINOR_VERSION_3 ), + .C_PF0_ENTRY_VERSION_TYPE_3 (C_PF0_ENTRY_VERSION_TYPE_3 ), + .C_PF0_ENTRY_RSVD0_3 (C_PF0_ENTRY_RSVD0_3 ), + .C_PF0_ENTRY_TYPE_4 (C_PF0_ENTRY_TYPE_4 ), + .C_PF0_ENTRY_BAR_4 (C_PF0_ENTRY_BAR_4 ), + .C_PF0_ENTRY_ADDR_4 (C_PF0_ENTRY_ADDR_4 ), + .C_PF0_ENTRY_MAJOR_VERSION_4 (C_PF0_ENTRY_MAJOR_VERSION_4 ), + .C_PF0_ENTRY_MINOR_VERSION_4 (C_PF0_ENTRY_MINOR_VERSION_4 ), + .C_PF0_ENTRY_VERSION_TYPE_4 (C_PF0_ENTRY_VERSION_TYPE_4 ), + .C_PF0_ENTRY_RSVD0_4 (C_PF0_ENTRY_RSVD0_4 ), + .C_PF0_ENTRY_TYPE_5 (C_PF0_ENTRY_TYPE_5 ), + .C_PF0_ENTRY_BAR_5 (C_PF0_ENTRY_BAR_5 ), + .C_PF0_ENTRY_ADDR_5 (C_PF0_ENTRY_ADDR_5 ), + .C_PF0_ENTRY_MAJOR_VERSION_5 (C_PF0_ENTRY_MAJOR_VERSION_5 ), + .C_PF0_ENTRY_MINOR_VERSION_5 (C_PF0_ENTRY_MINOR_VERSION_5 ), + .C_PF0_ENTRY_VERSION_TYPE_5 (C_PF0_ENTRY_VERSION_TYPE_5 ), + .C_PF0_ENTRY_RSVD0_5 (C_PF0_ENTRY_RSVD0_5 ), + .C_PF0_ENTRY_TYPE_6 (C_PF0_ENTRY_TYPE_6 ), + .C_PF0_ENTRY_BAR_6 (C_PF0_ENTRY_BAR_6 ), + .C_PF0_ENTRY_ADDR_6 (C_PF0_ENTRY_ADDR_6 ), + .C_PF0_ENTRY_MAJOR_VERSION_6 (C_PF0_ENTRY_MAJOR_VERSION_6 ), + .C_PF0_ENTRY_MINOR_VERSION_6 (C_PF0_ENTRY_MINOR_VERSION_6 ), + .C_PF0_ENTRY_VERSION_TYPE_6 (C_PF0_ENTRY_VERSION_TYPE_6 ), + .C_PF0_ENTRY_RSVD0_6 (C_PF0_ENTRY_RSVD0_6 ), + .C_PF0_ENTRY_TYPE_7 (C_PF0_ENTRY_TYPE_7 ), + .C_PF0_ENTRY_BAR_7 (C_PF0_ENTRY_BAR_7 ), + .C_PF0_ENTRY_ADDR_7 (C_PF0_ENTRY_ADDR_7 ), + .C_PF0_ENTRY_MAJOR_VERSION_7 (C_PF0_ENTRY_MAJOR_VERSION_7 ), + .C_PF0_ENTRY_MINOR_VERSION_7 (C_PF0_ENTRY_MINOR_VERSION_7 ), + .C_PF0_ENTRY_VERSION_TYPE_7 (C_PF0_ENTRY_VERSION_TYPE_7 ), + .C_PF0_ENTRY_RSVD0_7 (C_PF0_ENTRY_RSVD0_7 ), + .C_PF0_ENTRY_TYPE_8 (C_PF0_ENTRY_TYPE_8 ), + .C_PF0_ENTRY_BAR_8 (C_PF0_ENTRY_BAR_8 ), + .C_PF0_ENTRY_ADDR_8 (C_PF0_ENTRY_ADDR_8 ), + .C_PF0_ENTRY_MAJOR_VERSION_8 (C_PF0_ENTRY_MAJOR_VERSION_8 ), + .C_PF0_ENTRY_MINOR_VERSION_8 (C_PF0_ENTRY_MINOR_VERSION_8 ), + .C_PF0_ENTRY_VERSION_TYPE_8 (C_PF0_ENTRY_VERSION_TYPE_8 ), + .C_PF0_ENTRY_RSVD0_8 (C_PF0_ENTRY_RSVD0_8 ), + .C_PF0_ENTRY_TYPE_9 (C_PF0_ENTRY_TYPE_9 ), + .C_PF0_ENTRY_BAR_9 (C_PF0_ENTRY_BAR_9 ), + .C_PF0_ENTRY_ADDR_9 (C_PF0_ENTRY_ADDR_9 ), + .C_PF0_ENTRY_MAJOR_VERSION_9 (C_PF0_ENTRY_MAJOR_VERSION_9 ), + .C_PF0_ENTRY_MINOR_VERSION_9 (C_PF0_ENTRY_MINOR_VERSION_9 ), + .C_PF0_ENTRY_VERSION_TYPE_9 (C_PF0_ENTRY_VERSION_TYPE_9 ), + .C_PF0_ENTRY_RSVD0_9 (C_PF0_ENTRY_RSVD0_9 ), + .C_PF0_ENTRY_TYPE_10 (C_PF0_ENTRY_TYPE_10 ), + .C_PF0_ENTRY_BAR_10 (C_PF0_ENTRY_BAR_10 ), + .C_PF0_ENTRY_ADDR_10 (C_PF0_ENTRY_ADDR_10 ), + .C_PF0_ENTRY_MAJOR_VERSION_10 (C_PF0_ENTRY_MAJOR_VERSION_10 ), + .C_PF0_ENTRY_MINOR_VERSION_10 (C_PF0_ENTRY_MINOR_VERSION_10 ), + .C_PF0_ENTRY_VERSION_TYPE_10 (C_PF0_ENTRY_VERSION_TYPE_10 ), + .C_PF0_ENTRY_RSVD0_10 (C_PF0_ENTRY_RSVD0_10 ), + .C_PF0_ENTRY_TYPE_11 (C_PF0_ENTRY_TYPE_11 ), + .C_PF0_ENTRY_BAR_11 (C_PF0_ENTRY_BAR_11 ), + .C_PF0_ENTRY_ADDR_11 (C_PF0_ENTRY_ADDR_11 ), + .C_PF0_ENTRY_MAJOR_VERSION_11 (C_PF0_ENTRY_MAJOR_VERSION_11 ), + .C_PF0_ENTRY_MINOR_VERSION_11 (C_PF0_ENTRY_MINOR_VERSION_11 ), + .C_PF0_ENTRY_VERSION_TYPE_11 (C_PF0_ENTRY_VERSION_TYPE_11 ), + .C_PF0_ENTRY_RSVD0_11 (C_PF0_ENTRY_RSVD0_11 ), + .C_PF0_ENTRY_TYPE_12 (C_PF0_ENTRY_TYPE_12 ), + .C_PF0_ENTRY_BAR_12 (C_PF0_ENTRY_BAR_12 ), + .C_PF0_ENTRY_ADDR_12 (C_PF0_ENTRY_ADDR_12 ), + .C_PF0_ENTRY_MAJOR_VERSION_12 (C_PF0_ENTRY_MAJOR_VERSION_12 ), + .C_PF0_ENTRY_MINOR_VERSION_12 (C_PF0_ENTRY_MINOR_VERSION_12 ), + .C_PF0_ENTRY_VERSION_TYPE_12 (C_PF0_ENTRY_VERSION_TYPE_12 ), + .C_PF0_ENTRY_RSVD0_12 (C_PF0_ENTRY_RSVD0_12 ), + .C_PF0_ENTRY_TYPE_13 (C_PF0_ENTRY_TYPE_13 ), + .C_PF0_ENTRY_BAR_13 (C_PF0_ENTRY_BAR_13 ), + .C_PF0_ENTRY_ADDR_13 (C_PF0_ENTRY_ADDR_13 ), + .C_PF0_ENTRY_MAJOR_VERSION_13 (C_PF0_ENTRY_MAJOR_VERSION_13 ), + .C_PF0_ENTRY_MINOR_VERSION_13 (C_PF0_ENTRY_MINOR_VERSION_13 ), + .C_PF0_ENTRY_VERSION_TYPE_13 (C_PF0_ENTRY_VERSION_TYPE_13 ), + .C_PF0_ENTRY_RSVD0_13 (C_PF0_ENTRY_RSVD0_13 ), + .C_PF0_S_AXI_ADDR_WIDTH (C_PF0_S_AXI_ADDR_WIDTH ), + .C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE (C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE ), + .C_PF1_BAR_INDEX (C_PF1_BAR_INDEX ), + .C_PF1_LOW_OFFSET (C_PF1_LOW_OFFSET ), + .C_PF1_HIGH_OFFSET (C_PF1_HIGH_OFFSET ), + .C_PF1_ENTRY_TYPE_0 (C_PF1_ENTRY_TYPE_0 ), + .C_PF1_ENTRY_BAR_0 (C_PF1_ENTRY_BAR_0 ), + .C_PF1_ENTRY_ADDR_0 (C_PF1_ENTRY_ADDR_0 ), + .C_PF1_ENTRY_MAJOR_VERSION_0 (C_PF1_ENTRY_MAJOR_VERSION_0 ), + .C_PF1_ENTRY_MINOR_VERSION_0 (C_PF1_ENTRY_MINOR_VERSION_0 ), + .C_PF1_ENTRY_VERSION_TYPE_0 (C_PF1_ENTRY_VERSION_TYPE_0 ), + .C_PF1_ENTRY_RSVD0_0 (C_PF1_ENTRY_RSVD0_0 ), + .C_PF1_ENTRY_TYPE_1 (C_PF1_ENTRY_TYPE_1 ), + .C_PF1_ENTRY_BAR_1 (C_PF1_ENTRY_BAR_1 ), + .C_PF1_ENTRY_ADDR_1 (C_PF1_ENTRY_ADDR_1 ), + .C_PF1_ENTRY_MAJOR_VERSION_1 (C_PF1_ENTRY_MAJOR_VERSION_1 ), + .C_PF1_ENTRY_MINOR_VERSION_1 (C_PF1_ENTRY_MINOR_VERSION_1 ), + .C_PF1_ENTRY_VERSION_TYPE_1 (C_PF1_ENTRY_VERSION_TYPE_1 ), + .C_PF1_ENTRY_RSVD0_1 (C_PF1_ENTRY_RSVD0_1 ), + .C_PF1_ENTRY_TYPE_2 (C_PF1_ENTRY_TYPE_2 ), + .C_PF1_ENTRY_BAR_2 (C_PF1_ENTRY_BAR_2 ), + .C_PF1_ENTRY_ADDR_2 (C_PF1_ENTRY_ADDR_2 ), + .C_PF1_ENTRY_MAJOR_VERSION_2 (C_PF1_ENTRY_MAJOR_VERSION_2 ), + .C_PF1_ENTRY_MINOR_VERSION_2 (C_PF1_ENTRY_MINOR_VERSION_2 ), + .C_PF1_ENTRY_VERSION_TYPE_2 (C_PF1_ENTRY_VERSION_TYPE_2 ), + .C_PF1_ENTRY_RSVD0_2 (C_PF1_ENTRY_RSVD0_2 ), + .C_PF1_ENTRY_TYPE_3 (C_PF1_ENTRY_TYPE_3 ), + .C_PF1_ENTRY_BAR_3 (C_PF1_ENTRY_BAR_3 ), + .C_PF1_ENTRY_ADDR_3 (C_PF1_ENTRY_ADDR_3 ), + .C_PF1_ENTRY_MAJOR_VERSION_3 (C_PF1_ENTRY_MAJOR_VERSION_3 ), + .C_PF1_ENTRY_MINOR_VERSION_3 (C_PF1_ENTRY_MINOR_VERSION_3 ), + .C_PF1_ENTRY_VERSION_TYPE_3 (C_PF1_ENTRY_VERSION_TYPE_3 ), + .C_PF1_ENTRY_RSVD0_3 (C_PF1_ENTRY_RSVD0_3 ), + .C_PF1_ENTRY_TYPE_4 (C_PF1_ENTRY_TYPE_4 ), + .C_PF1_ENTRY_BAR_4 (C_PF1_ENTRY_BAR_4 ), + .C_PF1_ENTRY_ADDR_4 (C_PF1_ENTRY_ADDR_4 ), + .C_PF1_ENTRY_MAJOR_VERSION_4 (C_PF1_ENTRY_MAJOR_VERSION_4 ), + .C_PF1_ENTRY_MINOR_VERSION_4 (C_PF1_ENTRY_MINOR_VERSION_4 ), + .C_PF1_ENTRY_VERSION_TYPE_4 (C_PF1_ENTRY_VERSION_TYPE_4 ), + .C_PF1_ENTRY_RSVD0_4 (C_PF1_ENTRY_RSVD0_4 ), + .C_PF1_ENTRY_TYPE_5 (C_PF1_ENTRY_TYPE_5 ), + .C_PF1_ENTRY_BAR_5 (C_PF1_ENTRY_BAR_5 ), + .C_PF1_ENTRY_ADDR_5 (C_PF1_ENTRY_ADDR_5 ), + .C_PF1_ENTRY_MAJOR_VERSION_5 (C_PF1_ENTRY_MAJOR_VERSION_5 ), + .C_PF1_ENTRY_MINOR_VERSION_5 (C_PF1_ENTRY_MINOR_VERSION_5 ), + .C_PF1_ENTRY_VERSION_TYPE_5 (C_PF1_ENTRY_VERSION_TYPE_5 ), + .C_PF1_ENTRY_RSVD0_5 (C_PF1_ENTRY_RSVD0_5 ), + .C_PF1_ENTRY_TYPE_6 (C_PF1_ENTRY_TYPE_6 ), + .C_PF1_ENTRY_BAR_6 (C_PF1_ENTRY_BAR_6 ), + .C_PF1_ENTRY_ADDR_6 (C_PF1_ENTRY_ADDR_6 ), + .C_PF1_ENTRY_MAJOR_VERSION_6 (C_PF1_ENTRY_MAJOR_VERSION_6 ), + .C_PF1_ENTRY_MINOR_VERSION_6 (C_PF1_ENTRY_MINOR_VERSION_6 ), + .C_PF1_ENTRY_VERSION_TYPE_6 (C_PF1_ENTRY_VERSION_TYPE_6 ), + .C_PF1_ENTRY_RSVD0_6 (C_PF1_ENTRY_RSVD0_6 ), + .C_PF1_ENTRY_TYPE_7 (C_PF1_ENTRY_TYPE_7 ), + .C_PF1_ENTRY_BAR_7 (C_PF1_ENTRY_BAR_7 ), + .C_PF1_ENTRY_ADDR_7 (C_PF1_ENTRY_ADDR_7 ), + .C_PF1_ENTRY_MAJOR_VERSION_7 (C_PF1_ENTRY_MAJOR_VERSION_7 ), + .C_PF1_ENTRY_MINOR_VERSION_7 (C_PF1_ENTRY_MINOR_VERSION_7 ), + .C_PF1_ENTRY_VERSION_TYPE_7 (C_PF1_ENTRY_VERSION_TYPE_7 ), + .C_PF1_ENTRY_RSVD0_7 (C_PF1_ENTRY_RSVD0_7 ), + .C_PF1_ENTRY_TYPE_8 (C_PF1_ENTRY_TYPE_8 ), + .C_PF1_ENTRY_BAR_8 (C_PF1_ENTRY_BAR_8 ), + .C_PF1_ENTRY_ADDR_8 (C_PF1_ENTRY_ADDR_8 ), + .C_PF1_ENTRY_MAJOR_VERSION_8 (C_PF1_ENTRY_MAJOR_VERSION_8 ), + .C_PF1_ENTRY_MINOR_VERSION_8 (C_PF1_ENTRY_MINOR_VERSION_8 ), + .C_PF1_ENTRY_VERSION_TYPE_8 (C_PF1_ENTRY_VERSION_TYPE_8 ), + .C_PF1_ENTRY_RSVD0_8 (C_PF1_ENTRY_RSVD0_8 ), + .C_PF1_ENTRY_TYPE_9 (C_PF1_ENTRY_TYPE_9 ), + .C_PF1_ENTRY_BAR_9 (C_PF1_ENTRY_BAR_9 ), + .C_PF1_ENTRY_ADDR_9 (C_PF1_ENTRY_ADDR_9 ), + .C_PF1_ENTRY_MAJOR_VERSION_9 (C_PF1_ENTRY_MAJOR_VERSION_9 ), + .C_PF1_ENTRY_MINOR_VERSION_9 (C_PF1_ENTRY_MINOR_VERSION_9 ), + .C_PF1_ENTRY_VERSION_TYPE_9 (C_PF1_ENTRY_VERSION_TYPE_9 ), + .C_PF1_ENTRY_RSVD0_9 (C_PF1_ENTRY_RSVD0_9 ), + .C_PF1_ENTRY_TYPE_10 (C_PF1_ENTRY_TYPE_10 ), + .C_PF1_ENTRY_BAR_10 (C_PF1_ENTRY_BAR_10 ), + .C_PF1_ENTRY_ADDR_10 (C_PF1_ENTRY_ADDR_10 ), + .C_PF1_ENTRY_MAJOR_VERSION_10 (C_PF1_ENTRY_MAJOR_VERSION_10 ), + .C_PF1_ENTRY_MINOR_VERSION_10 (C_PF1_ENTRY_MINOR_VERSION_10 ), + .C_PF1_ENTRY_VERSION_TYPE_10 (C_PF1_ENTRY_VERSION_TYPE_10 ), + .C_PF1_ENTRY_RSVD0_10 (C_PF1_ENTRY_RSVD0_10 ), + .C_PF1_ENTRY_TYPE_11 (C_PF1_ENTRY_TYPE_11 ), + .C_PF1_ENTRY_BAR_11 (C_PF1_ENTRY_BAR_11 ), + .C_PF1_ENTRY_ADDR_11 (C_PF1_ENTRY_ADDR_11 ), + .C_PF1_ENTRY_MAJOR_VERSION_11 (C_PF1_ENTRY_MAJOR_VERSION_11 ), + .C_PF1_ENTRY_MINOR_VERSION_11 (C_PF1_ENTRY_MINOR_VERSION_11 ), + .C_PF1_ENTRY_VERSION_TYPE_11 (C_PF1_ENTRY_VERSION_TYPE_11 ), + .C_PF1_ENTRY_RSVD0_11 (C_PF1_ENTRY_RSVD0_11 ), + .C_PF1_ENTRY_TYPE_12 (C_PF1_ENTRY_TYPE_12 ), + .C_PF1_ENTRY_BAR_12 (C_PF1_ENTRY_BAR_12 ), + .C_PF1_ENTRY_ADDR_12 (C_PF1_ENTRY_ADDR_12 ), + .C_PF1_ENTRY_MAJOR_VERSION_12 (C_PF1_ENTRY_MAJOR_VERSION_12 ), + .C_PF1_ENTRY_MINOR_VERSION_12 (C_PF1_ENTRY_MINOR_VERSION_12 ), + .C_PF1_ENTRY_VERSION_TYPE_12 (C_PF1_ENTRY_VERSION_TYPE_12 ), + .C_PF1_ENTRY_RSVD0_12 (C_PF1_ENTRY_RSVD0_12 ), + .C_PF1_ENTRY_TYPE_13 (C_PF1_ENTRY_TYPE_13 ), + .C_PF1_ENTRY_BAR_13 (C_PF1_ENTRY_BAR_13 ), + .C_PF1_ENTRY_ADDR_13 (C_PF1_ENTRY_ADDR_13 ), + .C_PF1_ENTRY_MAJOR_VERSION_13 (C_PF1_ENTRY_MAJOR_VERSION_13 ), + .C_PF1_ENTRY_MINOR_VERSION_13 (C_PF1_ENTRY_MINOR_VERSION_13 ), + .C_PF1_ENTRY_VERSION_TYPE_13 (C_PF1_ENTRY_VERSION_TYPE_13 ), + .C_PF1_ENTRY_RSVD0_13 (C_PF1_ENTRY_RSVD0_13 ), + .C_PF1_S_AXI_ADDR_WIDTH (C_PF1_S_AXI_ADDR_WIDTH ), + .C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE (C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE ), + .C_PF2_BAR_INDEX (C_PF2_BAR_INDEX ), + .C_PF2_LOW_OFFSET (C_PF2_LOW_OFFSET ), + .C_PF2_HIGH_OFFSET (C_PF2_HIGH_OFFSET ), + .C_PF2_ENTRY_TYPE_0 (C_PF2_ENTRY_TYPE_0 ), + .C_PF2_ENTRY_BAR_0 (C_PF2_ENTRY_BAR_0 ), + .C_PF2_ENTRY_ADDR_0 (C_PF2_ENTRY_ADDR_0 ), + .C_PF2_ENTRY_MAJOR_VERSION_0 (C_PF2_ENTRY_MAJOR_VERSION_0 ), + .C_PF2_ENTRY_MINOR_VERSION_0 (C_PF2_ENTRY_MINOR_VERSION_0 ), + .C_PF2_ENTRY_VERSION_TYPE_0 (C_PF2_ENTRY_VERSION_TYPE_0 ), + .C_PF2_ENTRY_RSVD0_0 (C_PF2_ENTRY_RSVD0_0 ), + .C_PF2_ENTRY_TYPE_1 (C_PF2_ENTRY_TYPE_1 ), + .C_PF2_ENTRY_BAR_1 (C_PF2_ENTRY_BAR_1 ), + .C_PF2_ENTRY_ADDR_1 (C_PF2_ENTRY_ADDR_1 ), + .C_PF2_ENTRY_MAJOR_VERSION_1 (C_PF2_ENTRY_MAJOR_VERSION_1 ), + .C_PF2_ENTRY_MINOR_VERSION_1 (C_PF2_ENTRY_MINOR_VERSION_1 ), + .C_PF2_ENTRY_VERSION_TYPE_1 (C_PF2_ENTRY_VERSION_TYPE_1 ), + .C_PF2_ENTRY_RSVD0_1 (C_PF2_ENTRY_RSVD0_1 ), + .C_PF2_ENTRY_TYPE_2 (C_PF2_ENTRY_TYPE_2 ), + .C_PF2_ENTRY_BAR_2 (C_PF2_ENTRY_BAR_2 ), + .C_PF2_ENTRY_ADDR_2 (C_PF2_ENTRY_ADDR_2 ), + .C_PF2_ENTRY_MAJOR_VERSION_2 (C_PF2_ENTRY_MAJOR_VERSION_2 ), + .C_PF2_ENTRY_MINOR_VERSION_2 (C_PF2_ENTRY_MINOR_VERSION_2 ), + .C_PF2_ENTRY_VERSION_TYPE_2 (C_PF2_ENTRY_VERSION_TYPE_2 ), + .C_PF2_ENTRY_RSVD0_2 (C_PF2_ENTRY_RSVD0_2 ), + .C_PF2_ENTRY_TYPE_3 (C_PF2_ENTRY_TYPE_3 ), + .C_PF2_ENTRY_BAR_3 (C_PF2_ENTRY_BAR_3 ), + .C_PF2_ENTRY_ADDR_3 (C_PF2_ENTRY_ADDR_3 ), + .C_PF2_ENTRY_MAJOR_VERSION_3 (C_PF2_ENTRY_MAJOR_VERSION_3 ), + .C_PF2_ENTRY_MINOR_VERSION_3 (C_PF2_ENTRY_MINOR_VERSION_3 ), + .C_PF2_ENTRY_VERSION_TYPE_3 (C_PF2_ENTRY_VERSION_TYPE_3 ), + .C_PF2_ENTRY_RSVD0_3 (C_PF2_ENTRY_RSVD0_3 ), + .C_PF2_ENTRY_TYPE_4 (C_PF2_ENTRY_TYPE_4 ), + .C_PF2_ENTRY_BAR_4 (C_PF2_ENTRY_BAR_4 ), + .C_PF2_ENTRY_ADDR_4 (C_PF2_ENTRY_ADDR_4 ), + .C_PF2_ENTRY_MAJOR_VERSION_4 (C_PF2_ENTRY_MAJOR_VERSION_4 ), + .C_PF2_ENTRY_MINOR_VERSION_4 (C_PF2_ENTRY_MINOR_VERSION_4 ), + .C_PF2_ENTRY_VERSION_TYPE_4 (C_PF2_ENTRY_VERSION_TYPE_4 ), + .C_PF2_ENTRY_RSVD0_4 (C_PF2_ENTRY_RSVD0_4 ), + .C_PF2_ENTRY_TYPE_5 (C_PF2_ENTRY_TYPE_5 ), + .C_PF2_ENTRY_BAR_5 (C_PF2_ENTRY_BAR_5 ), + .C_PF2_ENTRY_ADDR_5 (C_PF2_ENTRY_ADDR_5 ), + .C_PF2_ENTRY_MAJOR_VERSION_5 (C_PF2_ENTRY_MAJOR_VERSION_5 ), + .C_PF2_ENTRY_MINOR_VERSION_5 (C_PF2_ENTRY_MINOR_VERSION_5 ), + .C_PF2_ENTRY_VERSION_TYPE_5 (C_PF2_ENTRY_VERSION_TYPE_5 ), + .C_PF2_ENTRY_RSVD0_5 (C_PF2_ENTRY_RSVD0_5 ), + .C_PF2_ENTRY_TYPE_6 (C_PF2_ENTRY_TYPE_6 ), + .C_PF2_ENTRY_BAR_6 (C_PF2_ENTRY_BAR_6 ), + .C_PF2_ENTRY_ADDR_6 (C_PF2_ENTRY_ADDR_6 ), + .C_PF2_ENTRY_MAJOR_VERSION_6 (C_PF2_ENTRY_MAJOR_VERSION_6 ), + .C_PF2_ENTRY_MINOR_VERSION_6 (C_PF2_ENTRY_MINOR_VERSION_6 ), + .C_PF2_ENTRY_VERSION_TYPE_6 (C_PF2_ENTRY_VERSION_TYPE_6 ), + .C_PF2_ENTRY_RSVD0_6 (C_PF2_ENTRY_RSVD0_6 ), + .C_PF2_ENTRY_TYPE_7 (C_PF2_ENTRY_TYPE_7 ), + .C_PF2_ENTRY_BAR_7 (C_PF2_ENTRY_BAR_7 ), + .C_PF2_ENTRY_ADDR_7 (C_PF2_ENTRY_ADDR_7 ), + .C_PF2_ENTRY_MAJOR_VERSION_7 (C_PF2_ENTRY_MAJOR_VERSION_7 ), + .C_PF2_ENTRY_MINOR_VERSION_7 (C_PF2_ENTRY_MINOR_VERSION_7 ), + .C_PF2_ENTRY_VERSION_TYPE_7 (C_PF2_ENTRY_VERSION_TYPE_7 ), + .C_PF2_ENTRY_RSVD0_7 (C_PF2_ENTRY_RSVD0_7 ), + .C_PF2_ENTRY_TYPE_8 (C_PF2_ENTRY_TYPE_8 ), + .C_PF2_ENTRY_BAR_8 (C_PF2_ENTRY_BAR_8 ), + .C_PF2_ENTRY_ADDR_8 (C_PF2_ENTRY_ADDR_8 ), + .C_PF2_ENTRY_MAJOR_VERSION_8 (C_PF2_ENTRY_MAJOR_VERSION_8 ), + .C_PF2_ENTRY_MINOR_VERSION_8 (C_PF2_ENTRY_MINOR_VERSION_8 ), + .C_PF2_ENTRY_VERSION_TYPE_8 (C_PF2_ENTRY_VERSION_TYPE_8 ), + .C_PF2_ENTRY_RSVD0_8 (C_PF2_ENTRY_RSVD0_8 ), + .C_PF2_ENTRY_TYPE_9 (C_PF2_ENTRY_TYPE_9 ), + .C_PF2_ENTRY_BAR_9 (C_PF2_ENTRY_BAR_9 ), + .C_PF2_ENTRY_ADDR_9 (C_PF2_ENTRY_ADDR_9 ), + .C_PF2_ENTRY_MAJOR_VERSION_9 (C_PF2_ENTRY_MAJOR_VERSION_9 ), + .C_PF2_ENTRY_MINOR_VERSION_9 (C_PF2_ENTRY_MINOR_VERSION_9 ), + .C_PF2_ENTRY_VERSION_TYPE_9 (C_PF2_ENTRY_VERSION_TYPE_9 ), + .C_PF2_ENTRY_RSVD0_9 (C_PF2_ENTRY_RSVD0_9 ), + .C_PF2_ENTRY_TYPE_10 (C_PF2_ENTRY_TYPE_10 ), + .C_PF2_ENTRY_BAR_10 (C_PF2_ENTRY_BAR_10 ), + .C_PF2_ENTRY_ADDR_10 (C_PF2_ENTRY_ADDR_10 ), + .C_PF2_ENTRY_MAJOR_VERSION_10 (C_PF2_ENTRY_MAJOR_VERSION_10 ), + .C_PF2_ENTRY_MINOR_VERSION_10 (C_PF2_ENTRY_MINOR_VERSION_10 ), + .C_PF2_ENTRY_VERSION_TYPE_10 (C_PF2_ENTRY_VERSION_TYPE_10 ), + .C_PF2_ENTRY_RSVD0_10 (C_PF2_ENTRY_RSVD0_10 ), + .C_PF2_ENTRY_TYPE_11 (C_PF2_ENTRY_TYPE_11 ), + .C_PF2_ENTRY_BAR_11 (C_PF2_ENTRY_BAR_11 ), + .C_PF2_ENTRY_ADDR_11 (C_PF2_ENTRY_ADDR_11 ), + .C_PF2_ENTRY_MAJOR_VERSION_11 (C_PF2_ENTRY_MAJOR_VERSION_11 ), + .C_PF2_ENTRY_MINOR_VERSION_11 (C_PF2_ENTRY_MINOR_VERSION_11 ), + .C_PF2_ENTRY_VERSION_TYPE_11 (C_PF2_ENTRY_VERSION_TYPE_11 ), + .C_PF2_ENTRY_RSVD0_11 (C_PF2_ENTRY_RSVD0_11 ), + .C_PF2_ENTRY_TYPE_12 (C_PF2_ENTRY_TYPE_12 ), + .C_PF2_ENTRY_BAR_12 (C_PF2_ENTRY_BAR_12 ), + .C_PF2_ENTRY_ADDR_12 (C_PF2_ENTRY_ADDR_12 ), + .C_PF2_ENTRY_MAJOR_VERSION_12 (C_PF2_ENTRY_MAJOR_VERSION_12 ), + .C_PF2_ENTRY_MINOR_VERSION_12 (C_PF2_ENTRY_MINOR_VERSION_12 ), + .C_PF2_ENTRY_VERSION_TYPE_12 (C_PF2_ENTRY_VERSION_TYPE_12 ), + .C_PF2_ENTRY_RSVD0_12 (C_PF2_ENTRY_RSVD0_12 ), + .C_PF2_ENTRY_TYPE_13 (C_PF2_ENTRY_TYPE_13 ), + .C_PF2_ENTRY_BAR_13 (C_PF2_ENTRY_BAR_13 ), + .C_PF2_ENTRY_ADDR_13 (C_PF2_ENTRY_ADDR_13 ), + .C_PF2_ENTRY_MAJOR_VERSION_13 (C_PF2_ENTRY_MAJOR_VERSION_13 ), + .C_PF2_ENTRY_MINOR_VERSION_13 (C_PF2_ENTRY_MINOR_VERSION_13 ), + .C_PF2_ENTRY_VERSION_TYPE_13 (C_PF2_ENTRY_VERSION_TYPE_13 ), + .C_PF2_ENTRY_RSVD0_13 (C_PF2_ENTRY_RSVD0_13 ), + .C_PF2_S_AXI_ADDR_WIDTH (C_PF2_S_AXI_ADDR_WIDTH ), + .C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE (C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE ), + .C_PF3_BAR_INDEX (C_PF3_BAR_INDEX ), + .C_PF3_LOW_OFFSET (C_PF3_LOW_OFFSET ), + .C_PF3_HIGH_OFFSET (C_PF3_HIGH_OFFSET ), + .C_PF3_ENTRY_TYPE_0 (C_PF3_ENTRY_TYPE_0 ), + .C_PF3_ENTRY_BAR_0 (C_PF3_ENTRY_BAR_0 ), + .C_PF3_ENTRY_ADDR_0 (C_PF3_ENTRY_ADDR_0 ), + .C_PF3_ENTRY_MAJOR_VERSION_0 (C_PF3_ENTRY_MAJOR_VERSION_0 ), + .C_PF3_ENTRY_MINOR_VERSION_0 (C_PF3_ENTRY_MINOR_VERSION_0 ), + .C_PF3_ENTRY_VERSION_TYPE_0 (C_PF3_ENTRY_VERSION_TYPE_0 ), + .C_PF3_ENTRY_RSVD0_0 (C_PF3_ENTRY_RSVD0_0 ), + .C_PF3_ENTRY_TYPE_1 (C_PF3_ENTRY_TYPE_1 ), + .C_PF3_ENTRY_BAR_1 (C_PF3_ENTRY_BAR_1 ), + .C_PF3_ENTRY_ADDR_1 (C_PF3_ENTRY_ADDR_1 ), + .C_PF3_ENTRY_MAJOR_VERSION_1 (C_PF3_ENTRY_MAJOR_VERSION_1 ), + .C_PF3_ENTRY_MINOR_VERSION_1 (C_PF3_ENTRY_MINOR_VERSION_1 ), + .C_PF3_ENTRY_VERSION_TYPE_1 (C_PF3_ENTRY_VERSION_TYPE_1 ), + .C_PF3_ENTRY_RSVD0_1 (C_PF3_ENTRY_RSVD0_1 ), + .C_PF3_ENTRY_TYPE_2 (C_PF3_ENTRY_TYPE_2 ), + .C_PF3_ENTRY_BAR_2 (C_PF3_ENTRY_BAR_2 ), + .C_PF3_ENTRY_ADDR_2 (C_PF3_ENTRY_ADDR_2 ), + .C_PF3_ENTRY_MAJOR_VERSION_2 (C_PF3_ENTRY_MAJOR_VERSION_2 ), + .C_PF3_ENTRY_MINOR_VERSION_2 (C_PF3_ENTRY_MINOR_VERSION_2 ), + .C_PF3_ENTRY_VERSION_TYPE_2 (C_PF3_ENTRY_VERSION_TYPE_2 ), + .C_PF3_ENTRY_RSVD0_2 (C_PF3_ENTRY_RSVD0_2 ), + .C_PF3_ENTRY_TYPE_3 (C_PF3_ENTRY_TYPE_3 ), + .C_PF3_ENTRY_BAR_3 (C_PF3_ENTRY_BAR_3 ), + .C_PF3_ENTRY_ADDR_3 (C_PF3_ENTRY_ADDR_3 ), + .C_PF3_ENTRY_MAJOR_VERSION_3 (C_PF3_ENTRY_MAJOR_VERSION_3 ), + .C_PF3_ENTRY_MINOR_VERSION_3 (C_PF3_ENTRY_MINOR_VERSION_3 ), + .C_PF3_ENTRY_VERSION_TYPE_3 (C_PF3_ENTRY_VERSION_TYPE_3 ), + .C_PF3_ENTRY_RSVD0_3 (C_PF3_ENTRY_RSVD0_3 ), + .C_PF3_ENTRY_TYPE_4 (C_PF3_ENTRY_TYPE_4 ), + .C_PF3_ENTRY_BAR_4 (C_PF3_ENTRY_BAR_4 ), + .C_PF3_ENTRY_ADDR_4 (C_PF3_ENTRY_ADDR_4 ), + .C_PF3_ENTRY_MAJOR_VERSION_4 (C_PF3_ENTRY_MAJOR_VERSION_4 ), + .C_PF3_ENTRY_MINOR_VERSION_4 (C_PF3_ENTRY_MINOR_VERSION_4 ), + .C_PF3_ENTRY_VERSION_TYPE_4 (C_PF3_ENTRY_VERSION_TYPE_4 ), + .C_PF3_ENTRY_RSVD0_4 (C_PF3_ENTRY_RSVD0_4 ), + .C_PF3_ENTRY_TYPE_5 (C_PF3_ENTRY_TYPE_5 ), + .C_PF3_ENTRY_BAR_5 (C_PF3_ENTRY_BAR_5 ), + .C_PF3_ENTRY_ADDR_5 (C_PF3_ENTRY_ADDR_5 ), + .C_PF3_ENTRY_MAJOR_VERSION_5 (C_PF3_ENTRY_MAJOR_VERSION_5 ), + .C_PF3_ENTRY_MINOR_VERSION_5 (C_PF3_ENTRY_MINOR_VERSION_5 ), + .C_PF3_ENTRY_VERSION_TYPE_5 (C_PF3_ENTRY_VERSION_TYPE_5 ), + .C_PF3_ENTRY_RSVD0_5 (C_PF3_ENTRY_RSVD0_5 ), + .C_PF3_ENTRY_TYPE_6 (C_PF3_ENTRY_TYPE_6 ), + .C_PF3_ENTRY_BAR_6 (C_PF3_ENTRY_BAR_6 ), + .C_PF3_ENTRY_ADDR_6 (C_PF3_ENTRY_ADDR_6 ), + .C_PF3_ENTRY_MAJOR_VERSION_6 (C_PF3_ENTRY_MAJOR_VERSION_6 ), + .C_PF3_ENTRY_MINOR_VERSION_6 (C_PF3_ENTRY_MINOR_VERSION_6 ), + .C_PF3_ENTRY_VERSION_TYPE_6 (C_PF3_ENTRY_VERSION_TYPE_6 ), + .C_PF3_ENTRY_RSVD0_6 (C_PF3_ENTRY_RSVD0_6 ), + .C_PF3_ENTRY_TYPE_7 (C_PF3_ENTRY_TYPE_7 ), + .C_PF3_ENTRY_BAR_7 (C_PF3_ENTRY_BAR_7 ), + .C_PF3_ENTRY_ADDR_7 (C_PF3_ENTRY_ADDR_7 ), + .C_PF3_ENTRY_MAJOR_VERSION_7 (C_PF3_ENTRY_MAJOR_VERSION_7 ), + .C_PF3_ENTRY_MINOR_VERSION_7 (C_PF3_ENTRY_MINOR_VERSION_7 ), + .C_PF3_ENTRY_VERSION_TYPE_7 (C_PF3_ENTRY_VERSION_TYPE_7 ), + .C_PF3_ENTRY_RSVD0_7 (C_PF3_ENTRY_RSVD0_7 ), + .C_PF3_ENTRY_TYPE_8 (C_PF3_ENTRY_TYPE_8 ), + .C_PF3_ENTRY_BAR_8 (C_PF3_ENTRY_BAR_8 ), + .C_PF3_ENTRY_ADDR_8 (C_PF3_ENTRY_ADDR_8 ), + .C_PF3_ENTRY_MAJOR_VERSION_8 (C_PF3_ENTRY_MAJOR_VERSION_8 ), + .C_PF3_ENTRY_MINOR_VERSION_8 (C_PF3_ENTRY_MINOR_VERSION_8 ), + .C_PF3_ENTRY_VERSION_TYPE_8 (C_PF3_ENTRY_VERSION_TYPE_8 ), + .C_PF3_ENTRY_RSVD0_8 (C_PF3_ENTRY_RSVD0_8 ), + .C_PF3_ENTRY_TYPE_9 (C_PF3_ENTRY_TYPE_9 ), + .C_PF3_ENTRY_BAR_9 (C_PF3_ENTRY_BAR_9 ), + .C_PF3_ENTRY_ADDR_9 (C_PF3_ENTRY_ADDR_9 ), + .C_PF3_ENTRY_MAJOR_VERSION_9 (C_PF3_ENTRY_MAJOR_VERSION_9 ), + .C_PF3_ENTRY_MINOR_VERSION_9 (C_PF3_ENTRY_MINOR_VERSION_9 ), + .C_PF3_ENTRY_VERSION_TYPE_9 (C_PF3_ENTRY_VERSION_TYPE_9 ), + .C_PF3_ENTRY_RSVD0_9 (C_PF3_ENTRY_RSVD0_9 ), + .C_PF3_ENTRY_TYPE_10 (C_PF3_ENTRY_TYPE_10 ), + .C_PF3_ENTRY_BAR_10 (C_PF3_ENTRY_BAR_10 ), + .C_PF3_ENTRY_ADDR_10 (C_PF3_ENTRY_ADDR_10 ), + .C_PF3_ENTRY_MAJOR_VERSION_10 (C_PF3_ENTRY_MAJOR_VERSION_10 ), + .C_PF3_ENTRY_MINOR_VERSION_10 (C_PF3_ENTRY_MINOR_VERSION_10 ), + .C_PF3_ENTRY_VERSION_TYPE_10 (C_PF3_ENTRY_VERSION_TYPE_10 ), + .C_PF3_ENTRY_RSVD0_10 (C_PF3_ENTRY_RSVD0_10 ), + .C_PF3_ENTRY_TYPE_11 (C_PF3_ENTRY_TYPE_11 ), + .C_PF3_ENTRY_BAR_11 (C_PF3_ENTRY_BAR_11 ), + .C_PF3_ENTRY_ADDR_11 (C_PF3_ENTRY_ADDR_11 ), + .C_PF3_ENTRY_MAJOR_VERSION_11 (C_PF3_ENTRY_MAJOR_VERSION_11 ), + .C_PF3_ENTRY_MINOR_VERSION_11 (C_PF3_ENTRY_MINOR_VERSION_11 ), + .C_PF3_ENTRY_VERSION_TYPE_11 (C_PF3_ENTRY_VERSION_TYPE_11 ), + .C_PF3_ENTRY_RSVD0_11 (C_PF3_ENTRY_RSVD0_11 ), + .C_PF3_ENTRY_TYPE_12 (C_PF3_ENTRY_TYPE_12 ), + .C_PF3_ENTRY_BAR_12 (C_PF3_ENTRY_BAR_12 ), + .C_PF3_ENTRY_ADDR_12 (C_PF3_ENTRY_ADDR_12 ), + .C_PF3_ENTRY_MAJOR_VERSION_12 (C_PF3_ENTRY_MAJOR_VERSION_12 ), + .C_PF3_ENTRY_MINOR_VERSION_12 (C_PF3_ENTRY_MINOR_VERSION_12 ), + .C_PF3_ENTRY_VERSION_TYPE_12 (C_PF3_ENTRY_VERSION_TYPE_12 ), + .C_PF3_ENTRY_RSVD0_12 (C_PF3_ENTRY_RSVD0_12 ), + .C_PF3_ENTRY_TYPE_13 (C_PF3_ENTRY_TYPE_13 ), + .C_PF3_ENTRY_BAR_13 (C_PF3_ENTRY_BAR_13 ), + .C_PF3_ENTRY_ADDR_13 (C_PF3_ENTRY_ADDR_13 ), + .C_PF3_ENTRY_MAJOR_VERSION_13 (C_PF3_ENTRY_MAJOR_VERSION_13 ), + .C_PF3_ENTRY_MINOR_VERSION_13 (C_PF3_ENTRY_MINOR_VERSION_13 ), + .C_PF3_ENTRY_VERSION_TYPE_13 (C_PF3_ENTRY_VERSION_TYPE_13 ), + .C_PF3_ENTRY_RSVD0_13 (C_PF3_ENTRY_RSVD0_13 ), + .C_PF3_S_AXI_ADDR_WIDTH (C_PF3_S_AXI_ADDR_WIDTH ), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY ) + ) hw_disc_inst ( + .aclk_pcie (aclk_pcie ), + .aresetn_pcie (aresetn_pcie ), + .aclk_ctrl (aclk_ctrl ), + .aresetn_ctrl (aresetn_ctrl ), + .s_pcie4_cfg_ext_function_number (s_pcie4_cfg_ext_function_number ), + .s_pcie4_cfg_ext_read_data (s_pcie4_cfg_ext_read_data ), + .s_pcie4_cfg_ext_read_data_valid (s_pcie4_cfg_ext_read_data_valid ), + .s_pcie4_cfg_ext_read_received (s_pcie4_cfg_ext_read_received ), + .s_pcie4_cfg_ext_register_number (s_pcie4_cfg_ext_register_number ), + .s_pcie4_cfg_ext_write_byte_enable (s_pcie4_cfg_ext_write_byte_enable ), + .s_pcie4_cfg_ext_write_data (s_pcie4_cfg_ext_write_data ), + .s_pcie4_cfg_ext_write_received (s_pcie4_cfg_ext_write_received ), + .m_pcie4_cfg_ext_function_number (m_pcie4_cfg_ext_function_number ), + .m_pcie4_cfg_ext_read_data (m_pcie4_cfg_ext_read_data ), + .m_pcie4_cfg_ext_read_data_valid (m_pcie4_cfg_ext_read_data_valid ), + .m_pcie4_cfg_ext_read_received (m_pcie4_cfg_ext_read_received ), + .m_pcie4_cfg_ext_register_number (m_pcie4_cfg_ext_register_number ), + .m_pcie4_cfg_ext_write_byte_enable (m_pcie4_cfg_ext_write_byte_enable ), + .m_pcie4_cfg_ext_write_data (m_pcie4_cfg_ext_write_data ), + .m_pcie4_cfg_ext_write_received (m_pcie4_cfg_ext_write_received ), + .s_axi_ctrl_pf0_awaddr (s_axi_ctrl_pf0_awaddr ), + .s_axi_ctrl_pf0_awvalid (s_axi_ctrl_pf0_awvalid ), + .s_axi_ctrl_pf0_awready (s_axi_ctrl_pf0_awready ), + .s_axi_ctrl_pf0_wdata (s_axi_ctrl_pf0_wdata ), + .s_axi_ctrl_pf0_wstrb (s_axi_ctrl_pf0_wstrb ), + .s_axi_ctrl_pf0_wvalid (s_axi_ctrl_pf0_wvalid ), + .s_axi_ctrl_pf0_wready (s_axi_ctrl_pf0_wready ), + .s_axi_ctrl_pf0_bresp (s_axi_ctrl_pf0_bresp ), + .s_axi_ctrl_pf0_bvalid (s_axi_ctrl_pf0_bvalid ), + .s_axi_ctrl_pf0_bready (s_axi_ctrl_pf0_bready ), + .s_axi_ctrl_pf0_araddr (s_axi_ctrl_pf0_araddr ), + .s_axi_ctrl_pf0_arvalid (s_axi_ctrl_pf0_arvalid ), + .s_axi_ctrl_pf0_arready (s_axi_ctrl_pf0_arready ), + .s_axi_ctrl_pf0_rdata (s_axi_ctrl_pf0_rdata ), + .s_axi_ctrl_pf0_rresp (s_axi_ctrl_pf0_rresp ), + .s_axi_ctrl_pf0_rvalid (s_axi_ctrl_pf0_rvalid ), + .s_axi_ctrl_pf0_rready (s_axi_ctrl_pf0_rready ), + .s_axi_ctrl_pf1_awaddr (s_axi_ctrl_pf1_awaddr ), + .s_axi_ctrl_pf1_awvalid (s_axi_ctrl_pf1_awvalid ), + .s_axi_ctrl_pf1_awready (s_axi_ctrl_pf1_awready ), + .s_axi_ctrl_pf1_wdata (s_axi_ctrl_pf1_wdata ), + .s_axi_ctrl_pf1_wstrb (s_axi_ctrl_pf1_wstrb ), + .s_axi_ctrl_pf1_wvalid (s_axi_ctrl_pf1_wvalid ), + .s_axi_ctrl_pf1_wready (s_axi_ctrl_pf1_wready ), + .s_axi_ctrl_pf1_bresp (s_axi_ctrl_pf1_bresp ), + .s_axi_ctrl_pf1_bvalid (s_axi_ctrl_pf1_bvalid ), + .s_axi_ctrl_pf1_bready (s_axi_ctrl_pf1_bready ), + .s_axi_ctrl_pf1_araddr (s_axi_ctrl_pf1_araddr ), + .s_axi_ctrl_pf1_arvalid (s_axi_ctrl_pf1_arvalid ), + .s_axi_ctrl_pf1_arready (s_axi_ctrl_pf1_arready ), + .s_axi_ctrl_pf1_rdata (s_axi_ctrl_pf1_rdata ), + .s_axi_ctrl_pf1_rresp (s_axi_ctrl_pf1_rresp ), + .s_axi_ctrl_pf1_rvalid (s_axi_ctrl_pf1_rvalid ), + .s_axi_ctrl_pf1_rready (s_axi_ctrl_pf1_rready ), + .s_axi_ctrl_pf2_awaddr (s_axi_ctrl_pf2_awaddr ), + .s_axi_ctrl_pf2_awvalid (s_axi_ctrl_pf2_awvalid ), + .s_axi_ctrl_pf2_awready (s_axi_ctrl_pf2_awready ), + .s_axi_ctrl_pf2_wdata (s_axi_ctrl_pf2_wdata ), + .s_axi_ctrl_pf2_wstrb (s_axi_ctrl_pf2_wstrb ), + .s_axi_ctrl_pf2_wvalid (s_axi_ctrl_pf2_wvalid ), + .s_axi_ctrl_pf2_wready (s_axi_ctrl_pf2_wready ), + .s_axi_ctrl_pf2_bresp (s_axi_ctrl_pf2_bresp ), + .s_axi_ctrl_pf2_bvalid (s_axi_ctrl_pf2_bvalid ), + .s_axi_ctrl_pf2_bready (s_axi_ctrl_pf2_bready ), + .s_axi_ctrl_pf2_araddr (s_axi_ctrl_pf2_araddr ), + .s_axi_ctrl_pf2_arvalid (s_axi_ctrl_pf2_arvalid ), + .s_axi_ctrl_pf2_arready (s_axi_ctrl_pf2_arready ), + .s_axi_ctrl_pf2_rdata (s_axi_ctrl_pf2_rdata ), + .s_axi_ctrl_pf2_rresp (s_axi_ctrl_pf2_rresp ), + .s_axi_ctrl_pf2_rvalid (s_axi_ctrl_pf2_rvalid ), + .s_axi_ctrl_pf2_rready (s_axi_ctrl_pf2_rready ), + .s_axi_ctrl_pf3_awaddr (s_axi_ctrl_pf3_awaddr ), + .s_axi_ctrl_pf3_awvalid (s_axi_ctrl_pf3_awvalid ), + .s_axi_ctrl_pf3_awready (s_axi_ctrl_pf3_awready ), + .s_axi_ctrl_pf3_wdata (s_axi_ctrl_pf3_wdata ), + .s_axi_ctrl_pf3_wstrb (s_axi_ctrl_pf3_wstrb ), + .s_axi_ctrl_pf3_wvalid (s_axi_ctrl_pf3_wvalid ), + .s_axi_ctrl_pf3_wready (s_axi_ctrl_pf3_wready ), + .s_axi_ctrl_pf3_bresp (s_axi_ctrl_pf3_bresp ), + .s_axi_ctrl_pf3_bvalid (s_axi_ctrl_pf3_bvalid ), + .s_axi_ctrl_pf3_bready (s_axi_ctrl_pf3_bready ), + .s_axi_ctrl_pf3_araddr (s_axi_ctrl_pf3_araddr ), + .s_axi_ctrl_pf3_arvalid (s_axi_ctrl_pf3_arvalid ), + .s_axi_ctrl_pf3_arready (s_axi_ctrl_pf3_arready ), + .s_axi_ctrl_pf3_rdata (s_axi_ctrl_pf3_rdata ), + .s_axi_ctrl_pf3_rresp (s_axi_ctrl_pf3_rresp ), + .s_axi_ctrl_pf3_rvalid (s_axi_ctrl_pf3_rvalid ), + .s_axi_ctrl_pf3_rready (s_axi_ctrl_pf3_rready ) + ); + +endmodule diff --git a/linker/resources/base/iprepo/hw_discovery_v1_0/hdl/pcie_vsec.vhd b/linker/resources/base/iprepo/hw_discovery_v1_0/hdl/pcie_vsec.vhd new file mode 100644 index 00000000..6e5ac270 --- /dev/null +++ b/linker/resources/base/iprepo/hw_discovery_v1_0/hdl/pcie_vsec.vhd @@ -0,0 +1,381 @@ +-- (c) Copyright 2022, Advanced Micro Devices, Inc. +-- +-- Permission is hereby granted, free of charge, to any person obtaining a +-- copy of this software and associated documentation files (the "Software"), +-- to deal in the Software without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Software, and to permit persons to whom the +-- Software is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Software. +-- +-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +-- DEALINGS IN THE SOFTWARE. +------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_misc.all; + use ieee.numeric_std.all; + +library hw_discovery_v1_0_0; + +entity hw_discovery_v1_0_0_pcie_vsec is + generic( + C_NUM_PFS : integer range 1 to 4 := 1; + C_CAP_BASE_ADDR : std_logic_vector(11 downto 0) := x"480"; -- 0x480 default for PCIE4 + C_NEXT_CAP_ADDR : std_logic_vector(11 downto 0) := (others => '0'); + C_PF0_BAR_INDEX : integer range 0 to 6 := 0; + C_PF0_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF0_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF1_BAR_INDEX : integer range 0 to 6 := 0; + C_PF1_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF1_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF2_BAR_INDEX : integer range 0 to 6 := 0; + C_PF2_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF2_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF3_BAR_INDEX : integer range 0 to 6 := 0; + C_PF3_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF3_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_XDEVICEFAMILY : string := "no_family" + ); + port( + + ----------------------------------------------------------------------- + -- Clocks & Resets + ----------------------------------------------------------------------- + + aclk_pcie : in std_logic; + aresetn_pcie : in std_logic; + + ----------------------------------------------------------------------- + -- pcie4_cfg_ext Interface (aclk_pcie) + ----------------------------------------------------------------------- + + s_pcie4_cfg_ext_function_number : in std_logic_vector(15 downto 0); + s_pcie4_cfg_ext_read_data : out std_logic_vector(31 downto 0); + s_pcie4_cfg_ext_read_data_valid : out std_logic; + s_pcie4_cfg_ext_read_received : in std_logic; + s_pcie4_cfg_ext_register_number : in std_logic_vector(9 downto 0); + s_pcie4_cfg_ext_write_byte_enable : in std_logic_vector(3 downto 0); + s_pcie4_cfg_ext_write_data : in std_logic_vector(31 downto 0); + s_pcie4_cfg_ext_write_received : in std_logic; + + ----------------------------------------------------------------------- + -- pcie4_cfg_ext Interface (aclk_pcie) + ----------------------------------------------------------------------- + + m_pcie4_cfg_ext_function_number : out std_logic_vector(15 downto 0); + m_pcie4_cfg_ext_read_data : in std_logic_vector(31 downto 0); + m_pcie4_cfg_ext_read_data_valid : in std_logic; + m_pcie4_cfg_ext_read_received : out std_logic; + m_pcie4_cfg_ext_register_number : out std_logic_vector(9 downto 0); + m_pcie4_cfg_ext_write_byte_enable : out std_logic_vector(3 downto 0); + m_pcie4_cfg_ext_write_data : out std_logic_vector(31 downto 0); + m_pcie4_cfg_ext_write_received : out std_logic + + ); +end entity hw_discovery_v1_0_0_pcie_vsec; + +architecture rtl of hw_discovery_v1_0_0_pcie_vsec is + +------------------------------------------------------------------------------- +-- +-- CONSTANTS +-- +------------------------------------------------------------------------------- + +constant CAP_ID : std_logic_vector(15 downto 0) := x"000B"; +constant CAP_VERSION : std_logic_vector(3 downto 0) := x"1"; +constant VSEC_ID : std_logic_vector(15 downto 0) := x"0020"; +constant VSEC_REV : std_logic_vector(3 downto 0) := x"0"; +constant VSEC_LENGTH : std_logic_vector(11 downto 0) := x"010"; +constant NEXT_CAP_BASE_ADDR : integer := (to_integer(unsigned(C_CAP_BASE_ADDR)) + 16); +constant NEXT_CAP_CONFIG_ADDR : integer := (to_integer(unsigned(C_NEXT_CAP_ADDR))); +constant CAP_BASE_BYTE_ADDR : integer := (to_integer(unsigned(C_CAP_BASE_ADDR)) / 4); +constant CAP_BASE_ADDR : integer := (to_integer(unsigned(C_CAP_BASE_ADDR)) / 16); +constant ALF_VSEC_NXT_REG : std_logic_vector(11 downto 0) := std_logic_vector(to_unsigned(NEXT_CAP_BASE_ADDR, 12)); +constant ALF_VSEC_CONFIG_NXT : std_logic_vector(11 downto 0) := std_logic_vector(to_unsigned(NEXT_CAP_CONFIG_ADDR, 12)); +constant ALF_VSEC_BASE_REG : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(CAP_BASE_ADDR, 8)); +constant ALF_VSEC_REG_0 : std_logic_vector(s_pcie4_cfg_ext_register_number'RANGE) := std_logic_vector(to_unsigned(CAP_BASE_BYTE_ADDR, s_pcie4_cfg_ext_register_number'LENGTH)); +constant ALF_VSEC_REG_1 : std_logic_vector(s_pcie4_cfg_ext_register_number'RANGE) := std_logic_vector(to_unsigned((CAP_BASE_BYTE_ADDR + 1), s_pcie4_cfg_ext_register_number'LENGTH)); +constant ALF_VSEC_REG_2 : std_logic_vector(s_pcie4_cfg_ext_register_number'RANGE) := std_logic_vector(to_unsigned((CAP_BASE_BYTE_ADDR + 2), s_pcie4_cfg_ext_register_number'LENGTH)); +constant ALF_VSEC_REG_3 : std_logic_vector(s_pcie4_cfg_ext_register_number'RANGE) := std_logic_vector(to_unsigned((CAP_BASE_BYTE_ADDR + 3), s_pcie4_cfg_ext_register_number'LENGTH)); +constant PF0_BAR_INDEX : std_logic_vector(2 downto 0) := std_logic_vector(to_unsigned(C_PF0_BAR_INDEX, 3)); +constant PF1_BAR_INDEX : std_logic_vector(2 downto 0) := std_logic_vector(to_unsigned(C_PF1_BAR_INDEX, 3)); +constant PF2_BAR_INDEX : std_logic_vector(2 downto 0) := std_logic_vector(to_unsigned(C_PF2_BAR_INDEX, 3)); +constant PF3_BAR_INDEX : std_logic_vector(2 downto 0) := std_logic_vector(to_unsigned(C_PF3_BAR_INDEX, 3)); +constant NUM_PFS : std_logic_vector(1 downto 0) := std_logic_vector(to_unsigned((C_NUM_PFS - 1), 2)); + +------------------------------------------------------------------------------- +-- +-- SIGNALS +-- +------------------------------------------------------------------------------- + +signal cfg_ext_read_data : std_logic_vector(31 downto 0) := (others => '0'); +signal cfg_ext_read_data_valid : std_logic := '0'; + +signal enable_m_cfg_ext : std_logic := '0'; + +begin + + G_GENERATE_M_PCIE4_NXT_CFG_EXT : if (NEXT_CAP_CONFIG_ADDR >= NEXT_CAP_BASE_ADDR) generate + + CF: + process(aclk_pcie) + + begin + + if (rising_edge(aclk_pcie)) then + + m_pcie4_cfg_ext_function_number <= s_pcie4_cfg_ext_function_number; + m_pcie4_cfg_ext_read_received <= s_pcie4_cfg_ext_read_received; + m_pcie4_cfg_ext_register_number <= s_pcie4_cfg_ext_register_number; + m_pcie4_cfg_ext_write_byte_enable <= s_pcie4_cfg_ext_write_byte_enable; + m_pcie4_cfg_ext_write_data <= s_pcie4_cfg_ext_write_data; + m_pcie4_cfg_ext_write_received <= s_pcie4_cfg_ext_write_received; + + if (enable_m_cfg_ext = '1') then + s_pcie4_cfg_ext_read_data <= m_pcie4_cfg_ext_read_data; + s_pcie4_cfg_ext_read_data_valid <= m_pcie4_cfg_ext_read_data_valid; + else + s_pcie4_cfg_ext_read_data <= cfg_ext_read_data; + s_pcie4_cfg_ext_read_data_valid <= cfg_ext_read_data_valid; + end if; + + end if; + + end process; + + end generate G_GENERATE_M_PCIE4_NXT_CFG_EXT; + + G_GENERATE_M_PCIE4_CFG_EXT : if (NEXT_CAP_CONFIG_ADDR < NEXT_CAP_BASE_ADDR) generate + + CF: + process(aclk_pcie) + + begin + + if (rising_edge(aclk_pcie)) then + + s_pcie4_cfg_ext_read_data <= cfg_ext_read_data; + s_pcie4_cfg_ext_read_data_valid <= cfg_ext_read_data_valid; + + m_pcie4_cfg_ext_function_number <= (others => '0'); + m_pcie4_cfg_ext_read_received <= '0'; + m_pcie4_cfg_ext_register_number <= (others => '0'); + m_pcie4_cfg_ext_write_byte_enable <= (others => '0'); + m_pcie4_cfg_ext_write_data <= (others => '0'); + m_pcie4_cfg_ext_write_received <= '0'; + + end if; + + end process; + + end generate G_GENERATE_M_PCIE4_CFG_EXT; + + RD: + process(aclk_pcie) + + variable func_num_var : std_logic_vector(1 downto 0); + variable reg_num_var : std_logic_vector(1 downto 0); + + begin + + if (rising_edge(aclk_pcie)) then + + if (aresetn_pcie = '0') then + cfg_ext_read_data_valid <= '0'; + cfg_ext_read_data <= (others => '0'); + func_num_var := s_pcie4_cfg_ext_function_number(1 downto 0); + reg_num_var := s_pcie4_cfg_ext_register_number(1 downto 0); + enable_m_cfg_ext <= '0'; + cfg_ext_read_data_valid <= '0'; + cfg_ext_read_data <= (others => '0'); + + else + + -- default assignment + cfg_ext_read_data_valid <= '0'; + cfg_ext_read_data <= (others => '0'); + func_num_var := s_pcie4_cfg_ext_function_number(1 downto 0); + reg_num_var := s_pcie4_cfg_ext_register_number(1 downto 0); + + if (s_pcie4_cfg_ext_read_received = '1') then + + enable_m_cfg_ext <= '0'; + if (s_pcie4_cfg_ext_register_number(9 downto 2) = ALF_VSEC_BASE_REG) then + + -- default read response + cfg_ext_read_data_valid <= '1'; + cfg_ext_read_data <= (others => '0'); + + case func_num_var is + + when "00" => -- PF0 + + case reg_num_var is + + when "00" => + + -- PF0 Extended Capability Header + + cfg_ext_read_data <= C_NEXT_CAP_ADDR & CAP_VERSION & CAP_ID; + + when "01" => + + -- VSEC Header - Identifies as Xilinx Additional List of Features (ALF) + + cfg_ext_read_data <= VSEC_LENGTH & VSEC_REV & VSEC_ID; + + when "10" => + + -- ALF Field 1 (BAR Index & Low Offset) + + cfg_ext_read_data <= C_PF0_LOW_OFFSET & '0' & PF0_BAR_INDEX; + + when others => + + -- ALF Field 2 (High Offset) + + cfg_ext_read_data <= C_PF0_HIGH_OFFSET; + + end case; + + when "01" => -- PF2 + + if (NUM_PFS > "00") then + + case reg_num_var is + + when "00" => + + -- PF1 Extended Capability Header + + cfg_ext_read_data <= C_NEXT_CAP_ADDR & CAP_VERSION & CAP_ID; + + when "01" => + + -- VSEC Header - Identifies as Xilinx Additional List of Features (ALF) + + cfg_ext_read_data <= VSEC_LENGTH & VSEC_REV & VSEC_ID; + + when "10" => + + -- ALF Field 1 (BAR Index & Low Offset) + + cfg_ext_read_data <= C_PF1_LOW_OFFSET & '0' & PF1_BAR_INDEX; + + when others => + + -- ALF Field 2 (High Offset) + + cfg_ext_read_data <= C_PF1_HIGH_OFFSET; + + end case; + + end if; + + when "10" => -- PF2 + + if (NUM_PFS(1) = '1') then + + case reg_num_var is + + when "00" => + + -- PF0 Extended Capability Header + + cfg_ext_read_data <= C_NEXT_CAP_ADDR & CAP_VERSION & CAP_ID; + + when "01" => + + -- VSEC Header - Identifies as Xilinx Additional List of Features (ALF) + + cfg_ext_read_data <= VSEC_LENGTH & VSEC_REV & VSEC_ID; + + when "10" => + + -- ALF Field 1 (BAR Index & Low Offset) + + cfg_ext_read_data <= C_PF2_LOW_OFFSET & '0' & PF2_BAR_INDEX; + + when others => + + -- ALF Field 2 (High Offset) + + cfg_ext_read_data <= C_PF2_HIGH_OFFSET; + + end case; + + end if; + + when others => -- PF3 + + if (NUM_PFS = "11") then + + case reg_num_var is + + when "00" => + + -- PF0 Extended Capability Header + + cfg_ext_read_data <= C_NEXT_CAP_ADDR & CAP_VERSION & CAP_ID; + + when "01" => + + -- VSEC Header - Identifies as Xilinx Additional List of Features (ALF) + + cfg_ext_read_data <= VSEC_LENGTH & VSEC_REV & VSEC_ID; + + when "10" => + + -- ALF Field 1 (BAR Index & Low Offset) + + cfg_ext_read_data <= C_PF3_LOW_OFFSET & '0' & PF3_BAR_INDEX; + + when others => + + -- ALF Field 2 (High Offset) + + cfg_ext_read_data <= C_PF3_HIGH_OFFSET; + + end case; + + end if; + + end case; + + elsif (NEXT_CAP_CONFIG_ADDR < NEXT_CAP_BASE_ADDR) then + + cfg_ext_read_data_valid <= '1'; + cfg_ext_read_data <= (others => '0'); + + elsif (s_pcie4_cfg_ext_register_number(9 downto 2) >= ALF_VSEC_CONFIG_NXT(11 downto 4)) then + + enable_m_cfg_ext <= '1'; + cfg_ext_read_data_valid <= '0'; + cfg_ext_read_data <= (others => '0'); + + else + + cfg_ext_read_data_valid <= '1'; + cfg_ext_read_data <= (others => '0'); + + end if; + + end if; + end if; + + end if; + + end process; + +end architecture rtl; diff --git a/linker/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_scriptext.tcl b/linker/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_scriptext.tcl new file mode 100644 index 00000000..95c7d800 --- /dev/null +++ b/linker/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_scriptext.tcl @@ -0,0 +1,74 @@ +# (c) Copyright 2023, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ +set core [get_ips] +#set core [ipx::get_cores -from project] +set CompName [get_property NAME $core] +set ipdef [get_property IPDEF $core] + +create_bd_design ${CompName}_testbd +set dut [ create_bd_cell -type ip -vlnv $ipdef $CompName ] + + set orig [dict create] + foreach p [list_property $core CONFIG.*] { + if {$p != "CONFIG.Component_Name" && [llength [get_property $p $dut]] > 0} { + dict set orig $p [get_property $p $core] + dict set orig $p.VALUE_SRC [get_property $p.VALUE_SRC $core] + } + } + + set_property -dict $orig $dut + + # Create ports + set aresetn_0 [ create_bd_port -dir I -type rst aresetn_0 ] + set aclk_0 [ create_bd_port -dir I -type clk -freq_hz 100000000 aclk_0 ] + set_property CONFIG.ASSOCIATED_RESET {aresetn_0} $aclk_0 + connect_bd_net -net aclk_0_net [get_bd_ports aclk_0] [get_bd_pins $CompName/aclk_pcie] [get_bd_pins $CompName/aclk_ctrl] + connect_bd_net -net aresetn_0_net [get_bd_ports aresetn_0] [get_bd_pins $CompName/aresetn_pcie] [get_bd_pins $CompName/aresetn_ctrl] + make_bd_intf_pins_external [get_bd_intf_pins $CompName/s_pcie4_cfg_ext] + + # Create instances of axi_vip + set num_pfs [get_property CONFIG.C_NUM_PFS $dut] + for {set pf 0} {$pf < $num_pfs} {incr pf} { + set addr_wid [get_property CONFIG.C_PF${pf}_S_AXI_ADDR_WIDTH $dut] + create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip:* vip_${pf} + set_property -dict [ list \ + CONFIG.ADDR_WIDTH $addr_wid \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.INTERFACE_MODE {MASTER} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] [get_bd_cells vip_${pf}] + connect_bd_net -net aclk_0_net [get_bd_pins vip_${pf}/aclk] + connect_bd_net -net aresetn_0_net [get_bd_pins vip_${pf}/aresetn] + connect_bd_intf_net -intf_net vip_${pf}_net [get_bd_intf_pins vip_${pf}/M_AXI] [get_bd_intf_pins $CompName/s_axi_ctrl_pf${pf}] + } + + # Create address segments + create_bd_addr_seg -offset 0x00000000 -range 0x00010000 [get_bd_addr_spaces vip_0/Master_AXI] [get_bd_addr_segs $CompName/s_axi_ctrl_pf0/reg0] seg_s_axi_ctrl_pf0 + if {$num_pfs > 1} {create_bd_addr_seg -offset 0x00000000 -range 0x00010000 [get_bd_addr_spaces vip_1/Master_AXI] [get_bd_addr_segs $CompName/s_axi_ctrl_pf1/reg0] seg_s_axi_ctrl_pf1} + if {$num_pfs > 2} {create_bd_addr_seg -offset 0x00000000 -range 0x00010000 [get_bd_addr_spaces vip_2/Master_AXI] [get_bd_addr_segs $CompName/s_axi_ctrl_pf2/reg0] seg_s_axi_ctrl_pf2} + if {$num_pfs > 3} {create_bd_addr_seg -offset 0x00000000 -range 0x00010000 [get_bd_addr_spaces vip_3/Master_AXI] [get_bd_addr_segs $CompName/s_axi_ctrl_pf3/reg0] seg_s_axi_ctrl_pf3} + +validate_bd_design +save_bd_design diff --git a/linker/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_tb_sv.xit b/linker/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_tb_sv.xit new file mode 100644 index 00000000..67f83440 --- /dev/null +++ b/linker/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_tb_sv.xit @@ -0,0 +1,197 @@ +# (c) Copyright 2023, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ +set CompName [get_property PARAM_VALUE.Component_Name] +set TBName ${CompName}_testtb +set DesignName ${CompName}_testbd +set WrapperName ${DesignName}_wrapper +set FILEPATH "simulation/${TBName}.sv" +set fid [add_ipfile ${FILEPATH}] +set num_pfs [get_property PARAM_VALUE.C_NUM_PFS] +puts_ipfile $fid "`timescale 1ps / 1ps" +puts_ipfile $fid "" +puts_ipfile $fid "module $TBName;" +puts_ipfile $fid " localparam CLK_PERIOD = 10000; //ps" +puts_ipfile $fid " localparam RESET_PULSE = 20; // cycles" +puts_ipfile $fid " localparam TIMEOUT = 100000; // cycles" +puts_ipfile $fid " reg aclk;" +puts_ipfile $fid " reg aresetn;" +puts_ipfile $fid " reg done = 0;" +puts_ipfile $fid "" +puts_ipfile $fid " initial begin" +puts_ipfile $fid " aclk = 1'b1;" +puts_ipfile $fid " forever #(CLK_PERIOD / 2) begin" +puts_ipfile $fid " aclk = ~aclk;" +puts_ipfile $fid " end" +puts_ipfile $fid " end" +puts_ipfile $fid "" +puts_ipfile $fid " initial begin" +puts_ipfile $fid " \$display(\"%t: %m: Starting testbench\", \$time);" +puts_ipfile $fid " aresetn = 1'b0;" +puts_ipfile $fid " #(CLK_PERIOD * RESET_PULSE) aresetn = 1'b1;" +puts_ipfile $fid " #(CLK_PERIOD * RESET_PULSE) mst_start_stimulus();" +puts_ipfile $fid " end" +puts_ipfile $fid "" +puts_ipfile $fid " $WrapperName exdes_top" +puts_ipfile $fid " (" +puts_ipfile $fid " .aclk_0(aclk)," +puts_ipfile $fid " .aresetn_0(aresetn)" +puts_ipfile $fid " );" +puts_ipfile $fid "" +puts_ipfile $fid " always @(posedge aclk) begin" +puts_ipfile $fid " if (done) begin" +puts_ipfile $fid " #(CLK_PERIOD * 10) \$display(\"%t: %m: SIMULATION PASSED\", \$time);" +puts_ipfile $fid " \$display(\"%t: %m: Test Completed Successfully\", \$time);" +puts_ipfile $fid " \$stop;" +puts_ipfile $fid " end" +puts_ipfile $fid " end" +puts_ipfile $fid "" +puts_ipfile $fid " initial begin" +puts_ipfile $fid " #(CLK_PERIOD * TIMEOUT) \$display(\"%t: %m: ERROR - Test timed out.\", \$time);" +puts_ipfile $fid " \$stop;" +puts_ipfile $fid " end" +puts_ipfile $fid "" + +set expect [dict create] +set inject [get_property PARAM_VALUE.C_INJECT_ENDPOINTS] +for {set pf 0} {$pf < $num_pfs} {incr pf} { + if {[llength $inject] > 1} { + set index 0 + set ep_filter [get_property PARAM_VALUE.C_PF${pf}_ENDPOINT_NAMES] + set bar_info [dict get $inject pcie_mapping_for /$CompName/s_axi_ctrl_pf${pf}] + set first_bar [lindex $bar_info 0] + set bar [dict get $first_bar bar] + set endpoints [dict get $inject endpoints_for_pcie_bar $pf $bar] + foreach {endpoint} $endpoints { + set endpoint_name [dict get $endpoint xrt_endpoint_name] + if {[dict exists $ep_filter $endpoint_name]} { + dict set expect ${pf} ${index} name $endpoint_name + dict set expect ${pf} ${index} offset [dict get $endpoint offset] + dict set expect ${pf} ${index} bar $bar + set vlnv_list [split [dict get $endpoint reg_abs] ":"] + set vlnv_version_list [split [lindex $vlnv_list 3] "."] + dict set expect ${pf} ${index} major [lindex $vlnv_version_list 0] + dict set expect ${pf} ${index} minor [lindex $vlnv_version_list 1] + dict set expect ${pf} ${index} etype [format %0d [dict get $ep_filter $endpoint_name type]] + dict set expect ${pf} ${index} reserve [format %0d [dict get $ep_filter $endpoint_name reserve]] + dict set expect ${pf} ${index} vtype 1 + incr index + } + } + lappend pf_slots $index + } else { + set num_slots [get_property PARAM_VALUE.C_PF${pf}_NUM_SLOTS_BAR_LAYOUT_TABLE] + lappend pf_slots $num_slots + for {set index 0} {$index < $num_slots} {incr index} { + dict set expect ${pf} ${index} offset [get_property PARAM_VALUE.C_PF${pf}_ENTRY_ADDR_${index}] + dict set expect ${pf} ${index} bar [get_property PARAM_VALUE.C_PF${pf}_ENTRY_BAR_${index}] + dict set expect ${pf} ${index} major [get_property PARAM_VALUE.C_PF${pf}_ENTRY_MAJOR_VERSION_${index}] + dict set expect ${pf} ${index} minor [get_property PARAM_VALUE.C_PF${pf}_ENTRY_MINOR_VERSION_${index}] + dict set expect ${pf} ${index} etype [format %0d [get_property PARAM_VALUE.C_PF${pf}_ENTRY_TYPE_${index}]] + dict set expect ${pf} ${index} reserve [format %0d [get_property PARAM_VALUE.C_PF${pf}_ENTRY_RSVD0_${index}]] + dict set expect ${pf} ${index} vtype [format %0d [get_property PARAM_VALUE.C_PF${pf}_ENTRY_VERSION_TYPE_${index}]] + } + } +} + +puts_ipfile $fid "reg \[31:0\] rdata;" +puts_ipfile $fid "reg \[47:0\] entry_addr;" +puts_ipfile $fid "reg \[2:0\] bar;" +puts_ipfile $fid "reg \[7:0\] major;" +puts_ipfile $fid "reg \[7:0\] minor;" +puts_ipfile $fid "reg \[7:0\] etype;" +puts_ipfile $fid "reg \[3:0\] reserve;" +puts_ipfile $fid "reg \[7:0\] vtype;" +puts_ipfile $fid "import axi_vip_pkg::*;" +for {set pf 0} {$pf < $num_pfs} {incr pf} { + puts_ipfile $fid "import ${DesignName}_vip_${pf}_0_pkg::*;" + puts_ipfile $fid "${DesignName}_vip_${pf}_0_mst_t mst_agent_${pf};" +} +puts_ipfile $fid "axi_transaction rd_trans;" +puts_ipfile $fid "" +puts_ipfile $fid "task mst_start_stimulus();" +for {set pf 0} {$pf < $num_pfs} {incr pf} { + puts_ipfile $fid " mst_agent_${pf} = new(\"master vip agent\",exdes_top.${DesignName}_i.vip_${pf}.inst.IF);" + puts_ipfile $fid " mst_agent_${pf}.start_master();" + puts_ipfile $fid "" + for {set index 0} {$index < [lindex $pf_slots $pf]} {incr index} { + set addr0 [expr 16 * $index + 16] + set addr1 [expr $addr0 + 4] + set addr2 [expr $addr0 + 8] + set bar [dict get $expect ${pf} ${index} bar] + regsub "0x" [format %x [dict get $expect ${pf} ${index} offset]] "" offset + regsub "0x" [format %x [dict get $expect ${pf} ${index} major]] "" major + regsub "0x" [format %x [dict get $expect ${pf} ${index} minor]] "" minor + regsub "0x" [format %x [dict get $expect ${pf} ${index} etype]] "" etype + regsub "0x" [format %x [dict get $expect ${pf} ${index} reserve]] "" reserve + regsub "0x" [format %x [dict get $expect ${pf} ${index} vtype]] "" vtype + puts_ipfile $fid " rd_trans = mst_agent_${pf}.rd_driver.create_transaction(\"read_ctrl_${pf}_${index}_0\");" + puts_ipfile $fid " RD_TRANSACTION_FAIL_${pf}_${index}a:assert(rd_trans.randomize());" + puts_ipfile $fid " rd_trans.set_driver_return_item_policy(XIL_AXI_PAYLOAD_RETURN);" + puts_ipfile $fid " rd_trans.set_read_cmd(${addr0},XIL_AXI_BURST_TYPE_INCR,0,0,xil_axi_size_t'(2));" + puts_ipfile $fid " mst_agent_${pf}.rd_driver.send(rd_trans); " + puts_ipfile $fid " mst_agent_${pf}.rd_driver.wait_rsp(rd_trans);" + puts_ipfile $fid " rdata = rd_trans.get_data_beat(0);" + puts_ipfile $fid " etype = rdata\[7:0\];" + puts_ipfile $fid " bar = rdata\[15:13\];" + puts_ipfile $fid " entry_addr = rdata\[31:16\];" + puts_ipfile $fid "" + puts_ipfile $fid " rd_trans = mst_agent_${pf}.rd_driver.create_transaction(\"read_ctrl_${pf}_${index}_1\");" + puts_ipfile $fid " RD_TRANSACTION_FAIL_${pf}_${index}b:assert(rd_trans.randomize());" + puts_ipfile $fid " rd_trans.set_driver_return_item_policy(XIL_AXI_PAYLOAD_RETURN);" + puts_ipfile $fid " rd_trans.set_read_cmd(${addr1},XIL_AXI_BURST_TYPE_INCR,0,0,xil_axi_size_t'(2));" + puts_ipfile $fid " mst_agent_${pf}.rd_driver.send(rd_trans); " + puts_ipfile $fid " mst_agent_${pf}.rd_driver.wait_rsp(rd_trans);" + puts_ipfile $fid " rdata = rd_trans.get_data_beat(0);" + puts_ipfile $fid " entry_addr\[47:16\] = rdata;" + puts_ipfile $fid "" + puts_ipfile $fid " rd_trans = mst_agent_${pf}.rd_driver.create_transaction(\"read_ctrl_${pf}_${index}_2\");" + puts_ipfile $fid " RD_TRANSACTION_FAIL_${pf}_${index}c:assert(rd_trans.randomize());" + puts_ipfile $fid " rd_trans.set_driver_return_item_policy(XIL_AXI_PAYLOAD_RETURN);" + puts_ipfile $fid " rd_trans.set_read_cmd(${addr2},XIL_AXI_BURST_TYPE_INCR,0,0,xil_axi_size_t'(2));" + puts_ipfile $fid " mst_agent_${pf}.rd_driver.send(rd_trans); " + puts_ipfile $fid " mst_agent_${pf}.rd_driver.wait_rsp(rd_trans);" + puts_ipfile $fid " rdata = rd_trans.get_data_beat(0);" + puts_ipfile $fid " vtype = rdata\[7:0\];" + puts_ipfile $fid " minor = rdata\[15:8\];" + puts_ipfile $fid " major = rdata\[23:16\];" + puts_ipfile $fid " reserve = rdata\[27:24\];" + puts_ipfile $fid "" + if {[dict exists $expect ${pf} ${index} name]} { + set name [dict get $expect ${pf} ${index} name] + puts_ipfile $fid " \$info (\"PF${pf}, INDEX ${index}, ENDPOINT: ${name}\");" + } else { + puts_ipfile $fid " \$info (\"PF${pf}, INDEX ${index}\");" + } + puts_ipfile $fid " assert (entry_addr == 48'h${offset}) \$info (\"C_PF${pf}_ENTRY_ADDR_${index} = %0X.\", entry_addr); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_ADDR_${index} = %0X, expected ${offset}.\", entry_addr);" + puts_ipfile $fid " assert (bar == 3'h${bar}) \$info (\"C_PF${pf}_ENTRY_BAR_${index} = %0X.\", bar); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_BAR_${index} = %0X, expected ${bar}.\", bar);" + puts_ipfile $fid " assert (major == 8'h${major}) \$info (\"C_PF${pf}_ENTRY_MAJOR_VERSION_${index} = %0X.\", major); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_MAJOR_VERSION_${index} = %0X, expected ${major}.\", major);" + puts_ipfile $fid " assert (minor == 8'h${minor}) \$info (\"C_PF${pf}_ENTRY_MINOR_VERSION_${index} = %0X.\", minor); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_MINOR_VERSION_${index} = %0X, expected ${minor}.\", minor);" + puts_ipfile $fid " assert (etype == 8'h${etype}) \$info (\"C_PF${pf}_ENTRY_TYPE_${index} = %0X.\", etype); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_TYPE_${index} = %0X, expected ${etype}.\", etype);" + puts_ipfile $fid " assert (reserve == 4'h${reserve}) \$info (\"C_PF${pf}_ENTRY_RSVD0_${index} = %0X.\", reserve); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_RSVD0_${index} = %0X, expected ${reserve}.\", reserve);" + puts_ipfile $fid " assert (vtype == 8'h${vtype}) \$info (\"C_PF${pf}_ENTRY_VERSION_TYPE_${index} = %0X.\", vtype); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_VERSION_TYPE_${index} = %0X, expected ${vtype}.\", vtype);" + puts_ipfile $fid "" + } +} +puts_ipfile $fid "done = 1;" +puts_ipfile $fid "endtask" +puts_ipfile $fid "" +puts_ipfile $fid "endmodule" +close_ipfile $fid diff --git a/linker/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_wrapper_sv.xit b/linker/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_wrapper_sv.xit new file mode 100644 index 00000000..08c6620e --- /dev/null +++ b/linker/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_wrapper_sv.xit @@ -0,0 +1,47 @@ +# (c) Copyright 2023, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ +set CompName [get_property PARAM_VALUE.Component_Name] +set TBName ${CompName}_testtb +set DesignName ${CompName}_testbd +set WrapperName ${DesignName}_wrapper +set FILEPATH "simulation/${WrapperName}.sv" +set fid [add_ipfile ${FILEPATH}] +puts_ipfile $fid "`timescale 1 ps / 1 ps " +puts_ipfile $fid "module $WrapperName " +puts_ipfile $fid " (aclk_0, " +puts_ipfile $fid " aresetn_0); " +puts_ipfile $fid " input aclk_0; " +puts_ipfile $fid " input aresetn_0; " +puts_ipfile $fid " wire aclk_0; " +puts_ipfile $fid " wire aresetn_0; " +puts_ipfile $fid " $DesignName ${DesignName}_i " +puts_ipfile $fid " (.aclk_0(aclk_0), " +puts_ipfile $fid " .aresetn_0(aresetn_0), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_function_number(0), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_read_data(), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_read_data_valid(), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_read_received(1'b0), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_register_number(0), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_write_byte_enable(0), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_write_data(0), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_write_received(1'b0)); " +puts_ipfile $fid "endmodule " +close_ipfile $fid diff --git a/linker/resources/base/iprepo/hw_discovery_v1_0/xgui/hw_discovery_v1_0.tcl b/linker/resources/base/iprepo/hw_discovery_v1_0/xgui/hw_discovery_v1_0.tcl new file mode 100644 index 00000000..381636e8 --- /dev/null +++ b/linker/resources/base/iprepo/hw_discovery_v1_0/xgui/hw_discovery_v1_0.tcl @@ -0,0 +1,4719 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +proc init_gui { IPINST } { + set Component_Name [ ipgui::add_param $IPINST -parent $IPINST -name Component_Name ] + set General_Config [ipgui::add_page $IPINST -name "General Config"] + set C_MANUAL [ipgui::add_param $IPINST -name C_MANUAL -widget comboBox -parent $General_Config] + set_property tooltip "C_MANUAL: Manually configure all bar layout parameters (disables automatic propagation of endpoint metadata)" $C_MANUAL + set C_NUM_PFS [ipgui::add_param $IPINST -name C_NUM_PFS -widget comboBox -parent $General_Config] + set_property tooltip "C_NUM_PFS: Set the number of PFs" $C_NUM_PFS + set C_CAP_BASE_ADDR [ipgui::add_param $IPINST -name C_CAP_BASE_ADDR -parent $General_Config] + set_property tooltip "C_CAP_BASE_ADDR: Set the PCIe Extended Capability Base Address" $C_CAP_BASE_ADDR + set C_NEXT_CAP_ADDR [ipgui::add_param $IPINST -name C_NEXT_CAP_ADDR -parent $General_Config] + set_property tooltip "C_NEXT_CAP_ADDR: Set the Next Capability Pointer. Leave at 0x000 if this is the last capability. Valid range is from (C_CAP_BASE_ADDR + 0x010) - 0xFFF" $C_NEXT_CAP_ADDR + set C_PF0_ENDPOINT_NAMES [ipgui::add_param $IPINST -name C_PF0_ENDPOINT_NAMES -parent $General_Config] + set_property tooltip "C_PF0_ENDPOINT_NAMES: Dictionary of endpoint names for PF0" $C_PF0_ENDPOINT_NAMES + set C_PF1_ENDPOINT_NAMES [ipgui::add_param $IPINST -name C_PF1_ENDPOINT_NAMES -parent $General_Config] + set_property tooltip "C_PF1_ENDPOINT_NAMES: Dictionary of endpoint names for PF1" $C_PF1_ENDPOINT_NAMES + set C_PF2_ENDPOINT_NAMES [ipgui::add_param $IPINST -name C_PF2_ENDPOINT_NAMES -parent $General_Config] + set_property tooltip "C_PF2_ENDPOINT_NAMES: Dictionary of endpoint names for PF2" $C_PF2_ENDPOINT_NAMES + set C_PF3_ENDPOINT_NAMES [ipgui::add_param $IPINST -name C_PF3_ENDPOINT_NAMES -parent $General_Config] + set_property tooltip "C_PF3_ENDPOINT_NAMES: Dictionary of endpoint names for PF3" $C_PF3_ENDPOINT_NAMES + set C_INJECT_ENDPOINTS [ipgui::add_param $IPINST -name C_INJECT_ENDPOINTS -parent $General_Config] + set_property tooltip "C_INJECT_ENDPOINTS: Endpoint properties dictionary to inject in place of vitis metadata for test (used only if vitis call returns empty string)" $C_INJECT_ENDPOINTS + + set AXI_Group [ipgui::add_group $IPINST -name "AXI Configuration" -parent $General_Config] + set C_PF0_S_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name C_PF0_S_AXI_ADDR_WIDTH -parent $AXI_Group] + set_property tooltip "C_PF0_S_AXI_ADDR_WIDTH: Set the AXI address width for PF0 AXI inteface" $C_PF0_S_AXI_ADDR_WIDTH + set C_PF1_S_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name C_PF1_S_AXI_ADDR_WIDTH -parent $AXI_Group] + set_property tooltip "C_PF1_S_AXI_ADDR_WIDTH: Set the AXI address width for PF1 AXI inteface" $C_PF1_S_AXI_ADDR_WIDTH + set C_PF2_S_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name C_PF2_S_AXI_ADDR_WIDTH -parent $AXI_Group] + set_property tooltip "C_PF2_S_AXI_ADDR_WIDTH: Set the AXI address width for PF2 AXI inteface" $C_PF2_S_AXI_ADDR_WIDTH + set C_PF3_S_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name C_PF3_S_AXI_ADDR_WIDTH -parent $AXI_Group] + set_property tooltip "C_PF3_S_AXI_ADDR_WIDTH: Set the AXI address width for PF3 AXI inteface" $C_PF3_S_AXI_ADDR_WIDTH + + set PF0_Config [ipgui::add_page $IPINST -name "PF0 Configuration"] + set PF0_Group [ipgui::add_group $IPINST -name "PF0 - General Configuration" -parent $PF0_Config] + set C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_param $IPINST -name C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $PF0_Group] + set_property tooltip "C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE: Set the number of Table Entries to be implemented for PF0 (excluding the End of Table identifier)" $C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE + set C_PF0_BAR_INDEX [ipgui::add_param $IPINST -name C_PF0_BAR_INDEX -parent $PF0_Group] + set_property tooltip "C_PF0_BAR_INDEX: Set the BAR Index for PF0" $C_PF0_BAR_INDEX + set C_PF0_LOW_OFFSET [ipgui::add_param $IPINST -name C_PF0_LOW_OFFSET -parent $PF0_Group] + set_property tooltip "C_PF0_LOW_OFFSET: Set the Low Address Offset for PF0" $C_PF0_LOW_OFFSET + set C_PF0_HIGH_OFFSET [ipgui::add_param $IPINST -name C_PF0_HIGH_OFFSET -parent $PF0_Group] + set_property tooltip "C_PF0_HIGH_OFFSET: Set the High Address Offset for PF0" $C_PF0_HIGH_OFFSET + + set PF0_Table_0_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 0 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_0: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_0 + set C_PF0_ENTRY_BAR_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_BAR_0: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_0 + set C_PF0_ENTRY_ADDR_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_0: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_0 + set C_PF0_ENTRY_VERSION_TYPE_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_0: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_0 + set C_PF0_ENTRY_MAJOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_0: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_0 + set C_PF0_ENTRY_MINOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_0: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_0 + set C_PF0_ENTRY_RSVD0_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_0: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_0 + + set PF0_Table_1_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 1 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_1: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_1 + set C_PF0_ENTRY_BAR_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_BAR_1: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_1 + set C_PF0_ENTRY_ADDR_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_1: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_1 + set C_PF0_ENTRY_VERSION_TYPE_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_1: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_1 + set C_PF0_ENTRY_MAJOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_1: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_1 + set C_PF0_ENTRY_MINOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_1: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_1 + set C_PF0_ENTRY_RSVD0_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_1: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_1 + + set PF0_Table_2_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 2 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_2: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_2 + set C_PF0_ENTRY_BAR_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_BAR_2: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_2 + set C_PF0_ENTRY_ADDR_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_2: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_2 + set C_PF0_ENTRY_VERSION_TYPE_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_2: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_2 + set C_PF0_ENTRY_MAJOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_2: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_2 + set C_PF0_ENTRY_MINOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_2: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_2 + set C_PF0_ENTRY_RSVD0_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_2: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_2 + + set PF0_Table_3_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 3 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_3: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_3 + set C_PF0_ENTRY_BAR_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_BAR_3: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_3 + set C_PF0_ENTRY_ADDR_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_3: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_3 + set C_PF0_ENTRY_VERSION_TYPE_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_3: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_3 + set C_PF0_ENTRY_MAJOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_3: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_3 + set C_PF0_ENTRY_MINOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_3: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_3 + set C_PF0_ENTRY_RSVD0_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_3: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_3 + + set PF0_Table_4_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 4 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_4: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_4 + set C_PF0_ENTRY_BAR_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_BAR_4: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_4 + set C_PF0_ENTRY_ADDR_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_4: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_4 + set C_PF0_ENTRY_VERSION_TYPE_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_4: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_4 + set C_PF0_ENTRY_MAJOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_4: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_4 + set C_PF0_ENTRY_MINOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_4: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_4 + set C_PF0_ENTRY_RSVD0_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_4: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_4 + + set PF0_Table_5_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 5 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_5: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_5 + set C_PF0_ENTRY_BAR_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_BAR_5: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_5 + set C_PF0_ENTRY_ADDR_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_5: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_5 + set C_PF0_ENTRY_VERSION_TYPE_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_5: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_5 + set C_PF0_ENTRY_MAJOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_5: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_5 + set C_PF0_ENTRY_MINOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_5: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_5 + set C_PF0_ENTRY_RSVD0_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_5: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_5 + + set PF0_Table_6_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 6 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_6: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_6 + set C_PF0_ENTRY_BAR_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_BAR_6: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_6 + set C_PF0_ENTRY_ADDR_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_6: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_6 + set C_PF0_ENTRY_VERSION_TYPE_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_6: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_6 + set C_PF0_ENTRY_MAJOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_6: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_6 + set C_PF0_ENTRY_MINOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_6: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_6 + set C_PF0_ENTRY_RSVD0_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_6: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_6 + + set PF0_Table_7_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 7 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_7: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_7 + set C_PF0_ENTRY_BAR_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_BAR_7: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_7 + set C_PF0_ENTRY_ADDR_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_7: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_7 + set C_PF0_ENTRY_VERSION_TYPE_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_7: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_7 + set C_PF0_ENTRY_MAJOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_7: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_7 + set C_PF0_ENTRY_MINOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_7: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_7 + set C_PF0_ENTRY_RSVD0_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_7: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_7 + + set PF0_Table_8_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 8 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_8: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_8 + set C_PF0_ENTRY_BAR_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_BAR_8: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_8 + set C_PF0_ENTRY_ADDR_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_8: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_8 + set C_PF0_ENTRY_VERSION_TYPE_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_8: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_8 + set C_PF0_ENTRY_MAJOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_8: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_8 + set C_PF0_ENTRY_MINOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_8: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_8 + set C_PF0_ENTRY_RSVD0_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_8: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_8 + + set PF0_Table_9_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 9 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_9: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_9 + set C_PF0_ENTRY_BAR_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_BAR_9: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_9 + set C_PF0_ENTRY_ADDR_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_9: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_9 + set C_PF0_ENTRY_VERSION_TYPE_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_9: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_9 + set C_PF0_ENTRY_MAJOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_9: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_9 + set C_PF0_ENTRY_MINOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_9: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_9 + set C_PF0_ENTRY_RSVD0_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_9: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_9 + + set PF0_Table_10_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 10 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_10: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_10 + set C_PF0_ENTRY_BAR_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_BAR_10: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_10 + set C_PF0_ENTRY_ADDR_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_10: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_10 + set C_PF0_ENTRY_VERSION_TYPE_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_10: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_10 + set C_PF0_ENTRY_MAJOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_10: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_10 + set C_PF0_ENTRY_MINOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_10: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_10 + set C_PF0_ENTRY_RSVD0_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_10: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_10 + + set PF0_Table_11_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 11 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_11: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_11 + set C_PF0_ENTRY_BAR_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_BAR_11: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_11 + set C_PF0_ENTRY_ADDR_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_11: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_11 + set C_PF0_ENTRY_VERSION_TYPE_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_11: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_11 + set C_PF0_ENTRY_MAJOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_11: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_11 + set C_PF0_ENTRY_MINOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_11: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_11 + set C_PF0_ENTRY_RSVD0_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_11: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_11 + + set PF0_Table_12_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 12 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_12: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_12 + set C_PF0_ENTRY_BAR_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_BAR_12: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_12 + set C_PF0_ENTRY_ADDR_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_12: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_12 + set C_PF0_ENTRY_VERSION_TYPE_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_12: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_12 + set C_PF0_ENTRY_MAJOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_12: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_12 + set C_PF0_ENTRY_MINOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_12: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_12 + set C_PF0_ENTRY_RSVD0_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_12: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_12 + + set PF0_Table_13_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 13 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_13: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_13 + set C_PF0_ENTRY_BAR_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_BAR_13: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_13 + set C_PF0_ENTRY_ADDR_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_13: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_13 + set C_PF0_ENTRY_VERSION_TYPE_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_13: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_13 + set C_PF0_ENTRY_MAJOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_13: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_13 + set C_PF0_ENTRY_MINOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_13: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_13 + set C_PF0_ENTRY_RSVD0_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_13: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_13 + + set PF1_Config [ipgui::add_page $IPINST -name "PF1 Configuration"] + set PF1_Group [ipgui::add_group $IPINST -name "PF1 - General Configuration" -parent $PF1_Config] + set C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_param $IPINST -name C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $PF1_Group] + set_property tooltip "C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE: Set the number of Table Entries to be implemented for PF1 (excluding the End of Table identifier)" $C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE + set C_PF1_BAR_INDEX [ipgui::add_param $IPINST -name C_PF1_BAR_INDEX -parent $PF1_Group] + set_property tooltip "C_PF1_BAR_INDEX: Set the BAR Index for PF1" $C_PF1_BAR_INDEX + set C_PF1_LOW_OFFSET [ipgui::add_param $IPINST -name C_PF1_LOW_OFFSET -parent $PF1_Group] + set_property tooltip "C_PF1_LOW_OFFSET: Set the Low Address Offset for PF1" $C_PF1_LOW_OFFSET + set C_PF1_HIGH_OFFSET [ipgui::add_param $IPINST -name C_PF1_HIGH_OFFSET -parent $PF1_Group] + set_property tooltip "C_PF1_HIGH_OFFSET: Set the High Address Offset for PF1" $C_PF1_HIGH_OFFSET + + set PF1_Table_0_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 0 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_0: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_0 + set C_PF1_ENTRY_BAR_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_BAR_0: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_0 + set C_PF1_ENTRY_ADDR_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_0: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_0 + set C_PF1_ENTRY_VERSION_TYPE_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_0: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_0 + set C_PF1_ENTRY_MAJOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_0: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_0 + set C_PF1_ENTRY_MINOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_0: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_0 + set C_PF1_ENTRY_RSVD0_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_0: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_0 + + set PF1_Table_1_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 1 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_1: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_1 + set C_PF1_ENTRY_BAR_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_BAR_1: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_1 + set C_PF1_ENTRY_ADDR_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_1: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_1 + set C_PF1_ENTRY_VERSION_TYPE_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_1: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_1 + set C_PF1_ENTRY_MAJOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_1: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_1 + set C_PF1_ENTRY_MINOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_1: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_1 + set C_PF1_ENTRY_RSVD0_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_1: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_1 + + set PF1_Table_2_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 2 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_2: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_2 + set C_PF1_ENTRY_BAR_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_BAR_2: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_2 + set C_PF1_ENTRY_ADDR_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_2: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_2 + set C_PF1_ENTRY_VERSION_TYPE_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_2: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_2 + set C_PF1_ENTRY_MAJOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_2: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_2 + set C_PF1_ENTRY_MINOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_2: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_2 + set C_PF1_ENTRY_RSVD0_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_2: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_2 + + set PF1_Table_3_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 3 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_3: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_3 + set C_PF1_ENTRY_BAR_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_BAR_3: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_3 + set C_PF1_ENTRY_ADDR_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_3: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_3 + set C_PF1_ENTRY_VERSION_TYPE_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_3: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_3 + set C_PF1_ENTRY_MAJOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_3: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_3 + set C_PF1_ENTRY_MINOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_3: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_3 + set C_PF1_ENTRY_RSVD0_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_3: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_3 + + set PF1_Table_4_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 4 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_4: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_4 + set C_PF1_ENTRY_BAR_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_BAR_4: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_4 + set C_PF1_ENTRY_ADDR_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_4: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_4 + set C_PF1_ENTRY_VERSION_TYPE_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_4: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_4 + set C_PF1_ENTRY_MAJOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_4: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_4 + set C_PF1_ENTRY_MINOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_4: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_4 + set C_PF1_ENTRY_RSVD0_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_4: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_4 + + set PF1_Table_5_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 5 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_5: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_5 + set C_PF1_ENTRY_BAR_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_BAR_5: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_5 + set C_PF1_ENTRY_ADDR_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_5: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_5 + set C_PF1_ENTRY_VERSION_TYPE_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_5: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_5 + set C_PF1_ENTRY_MAJOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_5: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_5 + set C_PF1_ENTRY_MINOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_5: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_5 + set C_PF1_ENTRY_RSVD0_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_5: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_5 + + set PF1_Table_6_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 6 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_6: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_6 + set C_PF1_ENTRY_BAR_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_BAR_6: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_6 + set C_PF1_ENTRY_ADDR_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_6: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_6 + set C_PF1_ENTRY_VERSION_TYPE_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_6: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_6 + set C_PF1_ENTRY_MAJOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_6: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_6 + set C_PF1_ENTRY_MINOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_6: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_6 + set C_PF1_ENTRY_RSVD0_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_6: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_6 + + set PF1_Table_7_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 7 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_7: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_7 + set C_PF1_ENTRY_BAR_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_BAR_7: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_7 + set C_PF1_ENTRY_ADDR_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_7: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_7 + set C_PF1_ENTRY_VERSION_TYPE_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_7: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_7 + set C_PF1_ENTRY_MAJOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_7: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_7 + set C_PF1_ENTRY_MINOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_7: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_7 + set C_PF1_ENTRY_RSVD0_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_7: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_7 + + set PF1_Table_8_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 8 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_8: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_8 + set C_PF1_ENTRY_BAR_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_BAR_8: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_8 + set C_PF1_ENTRY_ADDR_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_8: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_8 + set C_PF1_ENTRY_VERSION_TYPE_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_8: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_8 + set C_PF1_ENTRY_MAJOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_8: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_8 + set C_PF1_ENTRY_MINOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_8: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_8 + set C_PF1_ENTRY_RSVD0_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_8: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_8 + + set PF1_Table_9_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 9 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_9: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_9 + set C_PF1_ENTRY_BAR_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_BAR_9: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_9 + set C_PF1_ENTRY_ADDR_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_9: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_9 + set C_PF1_ENTRY_VERSION_TYPE_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_9: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_9 + set C_PF1_ENTRY_MAJOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_9: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_9 + set C_PF1_ENTRY_MINOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_9: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_9 + set C_PF1_ENTRY_RSVD0_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_9: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_9 + + set PF1_Table_10_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 10 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_10: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_10 + set C_PF1_ENTRY_BAR_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_BAR_10: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_10 + set C_PF1_ENTRY_ADDR_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_10: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_10 + set C_PF1_ENTRY_VERSION_TYPE_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_10: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_10 + set C_PF1_ENTRY_MAJOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_10: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_10 + set C_PF1_ENTRY_MINOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_10: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_10 + set C_PF1_ENTRY_RSVD0_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_10: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_10 + + set PF1_Table_11_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 11 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_11: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_11 + set C_PF1_ENTRY_BAR_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_BAR_11: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_11 + set C_PF1_ENTRY_ADDR_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_11: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_11 + set C_PF1_ENTRY_VERSION_TYPE_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_11: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_11 + set C_PF1_ENTRY_MAJOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_11: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_11 + set C_PF1_ENTRY_MINOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_11: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_11 + set C_PF1_ENTRY_RSVD0_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_11: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_11 + + set PF1_Table_12_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 12 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_12: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_12 + set C_PF1_ENTRY_BAR_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_BAR_12: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_12 + set C_PF1_ENTRY_ADDR_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_12: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_12 + set C_PF1_ENTRY_VERSION_TYPE_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_12: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_12 + set C_PF1_ENTRY_MAJOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_12: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_12 + set C_PF1_ENTRY_MINOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_12: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_12 + set C_PF1_ENTRY_RSVD0_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_12: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_12 + + set PF1_Table_13_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 13 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_13: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_13 + set C_PF1_ENTRY_BAR_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_BAR_13: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_13 + set C_PF1_ENTRY_ADDR_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_13: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_13 + set C_PF1_ENTRY_VERSION_TYPE_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_13: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_13 + set C_PF1_ENTRY_MAJOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_13: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_13 + set C_PF1_ENTRY_MINOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_13: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_13 + set C_PF1_ENTRY_RSVD0_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_13: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_13 + + set PF2_Config [ipgui::add_page $IPINST -name "PF2 Configuration"] + set PF2_Group [ipgui::add_group $IPINST -name "PF2 - General Configuration" -parent $PF2_Config] + set C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_param $IPINST -name C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $PF2_Group] + set_property tooltip "C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE: Set the number of Table Entries to be implemented for PF2 (excluding the End of Table identifier)" $C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE + set C_PF2_BAR_INDEX [ipgui::add_param $IPINST -name C_PF2_BAR_INDEX -parent $PF2_Group] + set_property tooltip "C_PF2_BAR_INDEX: Set the BAR Index for PF2" $C_PF2_BAR_INDEX + set C_PF2_LOW_OFFSET [ipgui::add_param $IPINST -name C_PF2_LOW_OFFSET -parent $PF2_Group] + set_property tooltip "C_PF2_LOW_OFFSET: Set the Low Address Offset for PF2" $C_PF2_LOW_OFFSET + set C_PF2_HIGH_OFFSET [ipgui::add_param $IPINST -name C_PF2_HIGH_OFFSET -parent $PF2_Group] + set_property tooltip "C_PF2_HIGH_OFFSET: Set the High Address Offset for PF2" $C_PF2_HIGH_OFFSET + + set PF2_Table_0_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 0 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_0: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_0 + set C_PF2_ENTRY_BAR_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_BAR_0: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_0 + set C_PF2_ENTRY_ADDR_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_0: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_0 + set C_PF2_ENTRY_VERSION_TYPE_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_0: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_0 + set C_PF2_ENTRY_MAJOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_0: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_0 + set C_PF2_ENTRY_MINOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_0: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_0 + set C_PF2_ENTRY_RSVD0_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_0: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_0 + + set PF2_Table_1_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 1 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_1: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_1 + set C_PF2_ENTRY_BAR_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_BAR_1: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_1 + set C_PF2_ENTRY_ADDR_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_1: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_1 + set C_PF2_ENTRY_VERSION_TYPE_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_1: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_1 + set C_PF2_ENTRY_MAJOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_1: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_1 + set C_PF2_ENTRY_MINOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_1: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_1 + set C_PF2_ENTRY_RSVD0_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_1: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_1 + + set PF2_Table_2_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 2 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_2: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_2 + set C_PF2_ENTRY_BAR_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_BAR_2: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_2 + set C_PF2_ENTRY_ADDR_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_2: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_2 + set C_PF2_ENTRY_VERSION_TYPE_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_2: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_2 + set C_PF2_ENTRY_MAJOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_2: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_2 + set C_PF2_ENTRY_MINOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_2: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_2 + set C_PF2_ENTRY_RSVD0_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_2: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_2 + + set PF2_Table_3_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 3 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_3: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_3 + set C_PF2_ENTRY_BAR_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_BAR_3: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_3 + set C_PF2_ENTRY_ADDR_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_3: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_3 + set C_PF2_ENTRY_VERSION_TYPE_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_3: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_3 + set C_PF2_ENTRY_MAJOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_3: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_3 + set C_PF2_ENTRY_MINOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_3: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_3 + set C_PF2_ENTRY_RSVD0_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_3: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_3 + + set PF2_Table_4_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 4 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_4: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_4 + set C_PF2_ENTRY_BAR_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_BAR_4: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_4 + set C_PF2_ENTRY_ADDR_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_4: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_4 + set C_PF2_ENTRY_VERSION_TYPE_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_4: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_4 + set C_PF2_ENTRY_MAJOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_4: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_4 + set C_PF2_ENTRY_MINOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_4: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_4 + set C_PF2_ENTRY_RSVD0_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_4: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_4 + + set PF2_Table_5_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 5 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_5: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_5 + set C_PF2_ENTRY_BAR_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_BAR_5: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_5 + set C_PF2_ENTRY_ADDR_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_5: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_5 + set C_PF2_ENTRY_VERSION_TYPE_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_5: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_5 + set C_PF2_ENTRY_MAJOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_5: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_5 + set C_PF2_ENTRY_MINOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_5: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_5 + set C_PF2_ENTRY_RSVD0_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_5: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_5 + + set PF2_Table_6_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 6 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_6: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_6 + set C_PF2_ENTRY_BAR_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_BAR_6: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_6 + set C_PF2_ENTRY_ADDR_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_6: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_6 + set C_PF2_ENTRY_VERSION_TYPE_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_6: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_6 + set C_PF2_ENTRY_MAJOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_6: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_6 + set C_PF2_ENTRY_MINOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_6: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_6 + set C_PF2_ENTRY_RSVD0_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_6: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_6 + + set PF2_Table_7_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 7 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_7: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_7 + set C_PF2_ENTRY_BAR_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_BAR_7: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_7 + set C_PF2_ENTRY_ADDR_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_7: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_7 + set C_PF2_ENTRY_VERSION_TYPE_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_7: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_7 + set C_PF2_ENTRY_MAJOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_7: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_7 + set C_PF2_ENTRY_MINOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_7: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_7 + set C_PF2_ENTRY_RSVD0_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_7: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_7 + + set PF2_Table_8_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 8 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_8: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_8 + set C_PF2_ENTRY_BAR_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_BAR_8: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_8 + set C_PF2_ENTRY_ADDR_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_8: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_8 + set C_PF2_ENTRY_VERSION_TYPE_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_8: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_8 + set C_PF2_ENTRY_MAJOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_8: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_8 + set C_PF2_ENTRY_MINOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_8: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_8 + set C_PF2_ENTRY_RSVD0_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_8: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_8 + + set PF2_Table_9_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 9 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_9: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_9 + set C_PF2_ENTRY_BAR_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_BAR_9: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_9 + set C_PF2_ENTRY_ADDR_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_9: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_9 + set C_PF2_ENTRY_VERSION_TYPE_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_9: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_9 + set C_PF2_ENTRY_MAJOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_9: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_9 + set C_PF2_ENTRY_MINOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_9: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_9 + set C_PF2_ENTRY_RSVD0_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_9: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_9 + + set PF2_Table_10_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 10 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_10: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_10 + set C_PF2_ENTRY_BAR_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_BAR_10: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_10 + set C_PF2_ENTRY_ADDR_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_10: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_10 + set C_PF2_ENTRY_VERSION_TYPE_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_10: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_10 + set C_PF2_ENTRY_MAJOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_10: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_10 + set C_PF2_ENTRY_MINOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_10: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_10 + set C_PF2_ENTRY_RSVD0_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_10: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_10 + + set PF2_Table_11_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 11 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_11: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_11 + set C_PF2_ENTRY_BAR_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_BAR_11: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_11 + set C_PF2_ENTRY_ADDR_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_11: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_11 + set C_PF2_ENTRY_VERSION_TYPE_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_11: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_11 + set C_PF2_ENTRY_MAJOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_11: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_11 + set C_PF2_ENTRY_MINOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_11: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_11 + set C_PF2_ENTRY_RSVD0_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_11: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_11 + + set PF2_Table_12_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 12 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_12: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_12 + set C_PF2_ENTRY_BAR_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_BAR_12: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_12 + set C_PF2_ENTRY_ADDR_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_12: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_12 + set C_PF2_ENTRY_VERSION_TYPE_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_12: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_12 + set C_PF2_ENTRY_MAJOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_12: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_12 + set C_PF2_ENTRY_MINOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_12: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_12 + set C_PF2_ENTRY_RSVD0_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_12: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_12 + + set PF2_Table_13_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 13 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_13: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_13 + set C_PF2_ENTRY_BAR_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_BAR_13: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_13 + set C_PF2_ENTRY_ADDR_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_13: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_13 + set C_PF2_ENTRY_VERSION_TYPE_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_13: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_13 + set C_PF2_ENTRY_MAJOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_13: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_13 + set C_PF2_ENTRY_MINOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_13: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_13 + set C_PF2_ENTRY_RSVD0_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_13: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_13 + + set PF3_Config [ipgui::add_page $IPINST -name "PF3 Configuration"] + set PF3_Group [ipgui::add_group $IPINST -name "PF3 - General Configuration" -parent $PF3_Config] + set C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_param $IPINST -name C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $PF3_Group] + set_property tooltip "C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE: Set the number of Table Entries to be implemented for PF3 (excluding the End of Table identifier)" $C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE + set C_PF3_BAR_INDEX [ipgui::add_param $IPINST -name C_PF3_BAR_INDEX -parent $PF3_Group] + set_property tooltip "C_PF3_BAR_INDEX: Set the BAR Index for PF3" $C_PF3_BAR_INDEX + set C_PF3_LOW_OFFSET [ipgui::add_param $IPINST -name C_PF3_LOW_OFFSET -parent $PF3_Group] + set_property tooltip "C_PF3_LOW_OFFSET: Set the Low Address Offset for PF3" $C_PF3_LOW_OFFSET + set C_PF3_HIGH_OFFSET [ipgui::add_param $IPINST -name C_PF3_HIGH_OFFSET -parent $PF3_Group] + set_property tooltip "C_PF3_HIGH_OFFSET: Set the High Address Offset for PF3" $C_PF3_HIGH_OFFSET + + set PF3_Table_0_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 0 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_0: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_0 + set C_PF3_ENTRY_BAR_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_BAR_0: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_0 + set C_PF3_ENTRY_ADDR_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_0: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_0 + set C_PF3_ENTRY_VERSION_TYPE_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_0: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_0 + set C_PF3_ENTRY_MAJOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_0: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_0 + set C_PF3_ENTRY_MINOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_0: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_0 + set C_PF3_ENTRY_RSVD0_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_0: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_0 + + set PF3_Table_1_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 1 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_1: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_1 + set C_PF3_ENTRY_BAR_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_BAR_1: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_1 + set C_PF3_ENTRY_ADDR_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_1: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_1 + set C_PF3_ENTRY_VERSION_TYPE_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_1: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_1 + set C_PF3_ENTRY_MAJOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_1: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_1 + set C_PF3_ENTRY_MINOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_1: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_1 + set C_PF3_ENTRY_RSVD0_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_1: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_1 + + set PF3_Table_2_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 2 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_2: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_2 + set C_PF3_ENTRY_BAR_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_BAR_2: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_2 + set C_PF3_ENTRY_ADDR_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_2: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_2 + set C_PF3_ENTRY_VERSION_TYPE_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_2: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_2 + set C_PF3_ENTRY_MAJOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_2: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_2 + set C_PF3_ENTRY_MINOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_2: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_2 + set C_PF3_ENTRY_RSVD0_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_2: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_2 + + set PF3_Table_3_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 3 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_3: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_3 + set C_PF3_ENTRY_BAR_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_BAR_3: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_3 + set C_PF3_ENTRY_ADDR_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_3: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_3 + set C_PF3_ENTRY_VERSION_TYPE_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_3: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_3 + set C_PF3_ENTRY_MAJOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_3: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_3 + set C_PF3_ENTRY_MINOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_3: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_3 + set C_PF3_ENTRY_RSVD0_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_3: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_3 + + set PF3_Table_4_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 4 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_4: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_4 + set C_PF3_ENTRY_BAR_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_BAR_4: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_4 + set C_PF3_ENTRY_ADDR_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_4: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_4 + set C_PF3_ENTRY_VERSION_TYPE_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_4: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_4 + set C_PF3_ENTRY_MAJOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_4: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_4 + set C_PF3_ENTRY_MINOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_4: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_4 + set C_PF3_ENTRY_RSVD0_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_4: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_4 + + set PF3_Table_5_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 5 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_5: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_5 + set C_PF3_ENTRY_BAR_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_BAR_5: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_5 + set C_PF3_ENTRY_ADDR_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_5: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_5 + set C_PF3_ENTRY_VERSION_TYPE_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_5: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_5 + set C_PF3_ENTRY_MAJOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_5: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_5 + set C_PF3_ENTRY_MINOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_5: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_5 + set C_PF3_ENTRY_RSVD0_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_5: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_5 + + set PF3_Table_6_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 6 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_6: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_6 + set C_PF3_ENTRY_BAR_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_BAR_6: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_6 + set C_PF3_ENTRY_ADDR_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_6: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_6 + set C_PF3_ENTRY_VERSION_TYPE_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_6: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_6 + set C_PF3_ENTRY_MAJOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_6: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_6 + set C_PF3_ENTRY_MINOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_6: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_6 + set C_PF3_ENTRY_RSVD0_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_6: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_6 + + set PF3_Table_7_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 7 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_7: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_7 + set C_PF3_ENTRY_BAR_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_BAR_7: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_7 + set C_PF3_ENTRY_ADDR_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_7: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_7 + set C_PF3_ENTRY_VERSION_TYPE_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_7: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_7 + set C_PF3_ENTRY_MAJOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_7: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_7 + set C_PF3_ENTRY_MINOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_7: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_7 + set C_PF3_ENTRY_RSVD0_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_7: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_7 + + set PF3_Table_8_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 8 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_8: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_8 + set C_PF3_ENTRY_BAR_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_BAR_8: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_8 + set C_PF3_ENTRY_ADDR_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_8: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_8 + set C_PF3_ENTRY_VERSION_TYPE_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_8: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_8 + set C_PF3_ENTRY_MAJOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_8: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_8 + set C_PF3_ENTRY_MINOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_8: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_8 + set C_PF3_ENTRY_RSVD0_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_8: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_8 + + set PF3_Table_9_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 9 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_9: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_9 + set C_PF3_ENTRY_BAR_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_BAR_9: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_9 + set C_PF3_ENTRY_ADDR_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_9: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_9 + set C_PF3_ENTRY_VERSION_TYPE_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_9: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_9 + set C_PF3_ENTRY_MAJOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_9: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_9 + set C_PF3_ENTRY_MINOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_9: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_9 + set C_PF3_ENTRY_RSVD0_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_9: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_9 + + set PF3_Table_10_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 10 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_10: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_10 + set C_PF3_ENTRY_BAR_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_BAR_10: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_10 + set C_PF3_ENTRY_ADDR_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_10: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_10 + set C_PF3_ENTRY_VERSION_TYPE_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_10: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_10 + set C_PF3_ENTRY_MAJOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_10: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_10 + set C_PF3_ENTRY_MINOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_10: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_10 + set C_PF3_ENTRY_RSVD0_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_10: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_10 + + set PF3_Table_11_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 11 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_11: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_11 + set C_PF3_ENTRY_BAR_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_BAR_11: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_11 + set C_PF3_ENTRY_ADDR_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_11: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_11 + set C_PF3_ENTRY_VERSION_TYPE_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_11: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_11 + set C_PF3_ENTRY_MAJOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_11: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_11 + set C_PF3_ENTRY_MINOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_11: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_11 + set C_PF3_ENTRY_RSVD0_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_11: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_11 + + set PF3_Table_12_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 12 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_12: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_12 + set C_PF3_ENTRY_BAR_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_BAR_12: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_12 + set C_PF3_ENTRY_ADDR_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_12: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_12 + set C_PF3_ENTRY_VERSION_TYPE_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_12: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_12 + set C_PF3_ENTRY_MAJOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_12: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_12 + set C_PF3_ENTRY_MINOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_12: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_12 + set C_PF3_ENTRY_RSVD0_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_12: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_12 + + set PF3_Table_13_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 13 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_13: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_13 + set C_PF3_ENTRY_BAR_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_BAR_13: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_13 + set C_PF3_ENTRY_ADDR_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_13: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_13 + set C_PF3_ENTRY_VERSION_TYPE_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_13: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_13 + set C_PF3_ENTRY_MAJOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_13: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_13 + set C_PF3_ENTRY_MINOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_13: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_13 + set C_PF3_ENTRY_RSVD0_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_13: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_13 + + set PF0_Values [ipgui::add_page $IPINST -name "PF0 Values"] + set PF0_Values_General [ipgui::add_group $IPINST -name "PF0 - General Values" -parent $PF0_Values] + set T_PF0_GENERAL [ipgui::add_table $IPINST -name T_PF0_GENERAL -rows 4 -columns 2 -parent $PF0_Values_General] + set L_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_static_text $IPINST -name L_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE -text "C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE" -parent $T_PF0_GENERAL] + set L_PF0_BAR_INDEX [ipgui::add_static_text $IPINST -name L_PF0_BAR_INDEX -text "C_PF0_BAR_INDEX " -parent $T_PF0_GENERAL] + set L_PF0_LOW_OFFSET [ipgui::add_static_text $IPINST -name L_PF0_LOW_OFFSET -text "C_PF0_LOW_OFFSET " -parent $T_PF0_GENERAL] + set L_PF0_HIGH_OFFSET [ipgui::add_static_text $IPINST -name L_PF0_HIGH_OFFSET -text "C_PF0_HIGH_OFFSET " -parent $T_PF0_GENERAL] + set V_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_dynamic_text $IPINST -name V_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE -tclproc VAL_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $T_PF0_GENERAL] + set V_PF0_BAR_INDEX [ipgui::add_dynamic_text $IPINST -name V_PF0_BAR_INDEX -tclproc VAL_PF0_BAR_INDEX -parent $T_PF0_GENERAL] + set V_PF0_LOW_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF0_LOW_OFFSET -tclproc VAL_PF0_LOW_OFFSET -parent $T_PF0_GENERAL] + set V_PF0_HIGH_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF0_HIGH_OFFSET -tclproc VAL_PF0_HIGH_OFFSET -parent $T_PF0_GENERAL] + set_property cell_location 0,0 $L_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,0 $L_PF0_BAR_INDEX + set_property cell_location 2,0 $L_PF0_LOW_OFFSET + set_property cell_location 3,0 $L_PF0_HIGH_OFFSET + set_property cell_location 0,1 $V_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,1 $V_PF0_BAR_INDEX + set_property cell_location 2,1 $V_PF0_LOW_OFFSET + set_property cell_location 3,1 $V_PF0_HIGH_OFFSET + set_property obj_color "192,192,192" $V_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property obj_color "192,192,192" $V_PF0_BAR_INDEX + set_property obj_color "192,192,192" $V_PF0_LOW_OFFSET + set_property obj_color "192,192,192" $V_PF0_HIGH_OFFSET + + set PF0_Values_0 [ipgui::add_group $IPINST -name "PF0 - Table Entry 0 Values" -parent $PF0_Values] + set T_PF0_0 [ipgui::add_table $IPINST -name T_PF0_0 -rows 7 -columns 2 -parent $PF0_Values_0] + set L_PF0_ENTRY_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_0 -text "C_PF0_ENTRY_TYPE_0 " -parent $T_PF0_0] + set L_PF0_ENTRY_BAR_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_0 -text "C_PF0_ENTRY_BAR_0 " -parent $T_PF0_0] + set L_PF0_ENTRY_ADDR_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_0 -text "C_PF0_ENTRY_ADDR_0 " -parent $T_PF0_0] + set L_PF0_ENTRY_VERSION_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_0 -text "C_PF0_ENTRY_VERSION_TYPE_0 " -parent $T_PF0_0] + set L_PF0_ENTRY_MAJOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_0 -text "C_PF0_ENTRY_MAJOR_VERSION_0" -parent $T_PF0_0] + set L_PF0_ENTRY_MINOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_0 -text "C_PF0_ENTRY_MINOR_VERSION_0" -parent $T_PF0_0] + set L_PF0_ENTRY_RSVD0_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_0 -text "C_PF0_ENTRY_RSVD0_0 " -parent $T_PF0_0] + set V_PF0_ENTRY_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_0 -tclproc VAL_PF0_ENTRY_TYPE_0 -parent $T_PF0_0] + set V_PF0_ENTRY_BAR_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_0 -tclproc VAL_PF0_ENTRY_BAR_0 -parent $T_PF0_0] + set V_PF0_ENTRY_ADDR_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_0 -tclproc VAL_PF0_ENTRY_ADDR_0 -parent $T_PF0_0] + set V_PF0_ENTRY_VERSION_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_0 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_0 -parent $T_PF0_0] + set V_PF0_ENTRY_MAJOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_0 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_0 -parent $T_PF0_0] + set V_PF0_ENTRY_MINOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_0 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_0 -parent $T_PF0_0] + set V_PF0_ENTRY_RSVD0_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_0 -tclproc VAL_PF0_ENTRY_RSVD0_0 -parent $T_PF0_0] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_0 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_0 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_0 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_0 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_0 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_0 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_0 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_0 + + set PF0_Values_1 [ipgui::add_group $IPINST -name "PF0 - Table Entry 1 Values" -parent $PF0_Values] + set T_PF0_1 [ipgui::add_table $IPINST -name T_PF0_1 -rows 7 -columns 2 -parent $PF0_Values_1] + set L_PF0_ENTRY_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_1 -text "C_PF0_ENTRY_TYPE_1 " -parent $T_PF0_1] + set L_PF0_ENTRY_BAR_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_1 -text "C_PF0_ENTRY_BAR_1 " -parent $T_PF0_1] + set L_PF0_ENTRY_ADDR_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_1 -text "C_PF0_ENTRY_ADDR_1 " -parent $T_PF0_1] + set L_PF0_ENTRY_VERSION_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_1 -text "C_PF0_ENTRY_VERSION_TYPE_1 " -parent $T_PF0_1] + set L_PF0_ENTRY_MAJOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_1 -text "C_PF0_ENTRY_MAJOR_VERSION_1" -parent $T_PF0_1] + set L_PF0_ENTRY_MINOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_1 -text "C_PF0_ENTRY_MINOR_VERSION_1" -parent $T_PF0_1] + set L_PF0_ENTRY_RSVD0_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_1 -text "C_PF0_ENTRY_RSVD0_1 " -parent $T_PF0_1] + set V_PF0_ENTRY_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_1 -tclproc VAL_PF0_ENTRY_TYPE_1 -parent $T_PF0_1] + set V_PF0_ENTRY_BAR_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_1 -tclproc VAL_PF0_ENTRY_BAR_1 -parent $T_PF0_1] + set V_PF0_ENTRY_ADDR_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_1 -tclproc VAL_PF0_ENTRY_ADDR_1 -parent $T_PF0_1] + set V_PF0_ENTRY_VERSION_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_1 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_1 -parent $T_PF0_1] + set V_PF0_ENTRY_MAJOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_1 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_1 -parent $T_PF0_1] + set V_PF0_ENTRY_MINOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_1 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_1 -parent $T_PF0_1] + set V_PF0_ENTRY_RSVD0_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_1 -tclproc VAL_PF0_ENTRY_RSVD0_1 -parent $T_PF0_1] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_1 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_1 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_1 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_1 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_1 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_1 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_1 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_1 + + set PF0_Values_2 [ipgui::add_group $IPINST -name "PF0 - Table Entry 2 Values" -parent $PF0_Values] + set T_PF0_2 [ipgui::add_table $IPINST -name T_PF0_2 -rows 7 -columns 2 -parent $PF0_Values_2] + set L_PF0_ENTRY_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_2 -text "C_PF0_ENTRY_TYPE_2 " -parent $T_PF0_2] + set L_PF0_ENTRY_BAR_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_2 -text "C_PF0_ENTRY_BAR_2 " -parent $T_PF0_2] + set L_PF0_ENTRY_ADDR_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_2 -text "C_PF0_ENTRY_ADDR_2 " -parent $T_PF0_2] + set L_PF0_ENTRY_VERSION_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_2 -text "C_PF0_ENTRY_VERSION_TYPE_2 " -parent $T_PF0_2] + set L_PF0_ENTRY_MAJOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_2 -text "C_PF0_ENTRY_MAJOR_VERSION_2" -parent $T_PF0_2] + set L_PF0_ENTRY_MINOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_2 -text "C_PF0_ENTRY_MINOR_VERSION_2" -parent $T_PF0_2] + set L_PF0_ENTRY_RSVD0_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_2 -text "C_PF0_ENTRY_RSVD0_2 " -parent $T_PF0_2] + set V_PF0_ENTRY_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_2 -tclproc VAL_PF0_ENTRY_TYPE_2 -parent $T_PF0_2] + set V_PF0_ENTRY_BAR_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_2 -tclproc VAL_PF0_ENTRY_BAR_2 -parent $T_PF0_2] + set V_PF0_ENTRY_ADDR_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_2 -tclproc VAL_PF0_ENTRY_ADDR_2 -parent $T_PF0_2] + set V_PF0_ENTRY_VERSION_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_2 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_2 -parent $T_PF0_2] + set V_PF0_ENTRY_MAJOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_2 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_2 -parent $T_PF0_2] + set V_PF0_ENTRY_MINOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_2 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_2 -parent $T_PF0_2] + set V_PF0_ENTRY_RSVD0_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_2 -tclproc VAL_PF0_ENTRY_RSVD0_2 -parent $T_PF0_2] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_2 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_2 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_2 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_2 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_2 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_2 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_2 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_2 + + set PF0_Values_3 [ipgui::add_group $IPINST -name "PF0 - Table Entry 3 Values" -parent $PF0_Values] + set T_PF0_3 [ipgui::add_table $IPINST -name T_PF0_3 -rows 7 -columns 2 -parent $PF0_Values_3] + set L_PF0_ENTRY_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_3 -text "C_PF0_ENTRY_TYPE_3 " -parent $T_PF0_3] + set L_PF0_ENTRY_BAR_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_3 -text "C_PF0_ENTRY_BAR_3 " -parent $T_PF0_3] + set L_PF0_ENTRY_ADDR_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_3 -text "C_PF0_ENTRY_ADDR_3 " -parent $T_PF0_3] + set L_PF0_ENTRY_VERSION_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_3 -text "C_PF0_ENTRY_VERSION_TYPE_3 " -parent $T_PF0_3] + set L_PF0_ENTRY_MAJOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_3 -text "C_PF0_ENTRY_MAJOR_VERSION_3" -parent $T_PF0_3] + set L_PF0_ENTRY_MINOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_3 -text "C_PF0_ENTRY_MINOR_VERSION_3" -parent $T_PF0_3] + set L_PF0_ENTRY_RSVD0_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_3 -text "C_PF0_ENTRY_RSVD0_3 " -parent $T_PF0_3] + set V_PF0_ENTRY_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_3 -tclproc VAL_PF0_ENTRY_TYPE_3 -parent $T_PF0_3] + set V_PF0_ENTRY_BAR_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_3 -tclproc VAL_PF0_ENTRY_BAR_3 -parent $T_PF0_3] + set V_PF0_ENTRY_ADDR_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_3 -tclproc VAL_PF0_ENTRY_ADDR_3 -parent $T_PF0_3] + set V_PF0_ENTRY_VERSION_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_3 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_3 -parent $T_PF0_3] + set V_PF0_ENTRY_MAJOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_3 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_3 -parent $T_PF0_3] + set V_PF0_ENTRY_MINOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_3 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_3 -parent $T_PF0_3] + set V_PF0_ENTRY_RSVD0_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_3 -tclproc VAL_PF0_ENTRY_RSVD0_3 -parent $T_PF0_3] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_3 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_3 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_3 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_3 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_3 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_3 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_3 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_3 + + set PF0_Values_4 [ipgui::add_group $IPINST -name "PF0 - Table Entry 4 Values" -parent $PF0_Values] + set T_PF0_4 [ipgui::add_table $IPINST -name T_PF0_4 -rows 7 -columns 2 -parent $PF0_Values_4] + set L_PF0_ENTRY_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_4 -text "C_PF0_ENTRY_TYPE_4 " -parent $T_PF0_4] + set L_PF0_ENTRY_BAR_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_4 -text "C_PF0_ENTRY_BAR_4 " -parent $T_PF0_4] + set L_PF0_ENTRY_ADDR_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_4 -text "C_PF0_ENTRY_ADDR_4 " -parent $T_PF0_4] + set L_PF0_ENTRY_VERSION_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_4 -text "C_PF0_ENTRY_VERSION_TYPE_4 " -parent $T_PF0_4] + set L_PF0_ENTRY_MAJOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_4 -text "C_PF0_ENTRY_MAJOR_VERSION_4" -parent $T_PF0_4] + set L_PF0_ENTRY_MINOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_4 -text "C_PF0_ENTRY_MINOR_VERSION_4" -parent $T_PF0_4] + set L_PF0_ENTRY_RSVD0_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_4 -text "C_PF0_ENTRY_RSVD0_4 " -parent $T_PF0_4] + set V_PF0_ENTRY_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_4 -tclproc VAL_PF0_ENTRY_TYPE_4 -parent $T_PF0_4] + set V_PF0_ENTRY_BAR_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_4 -tclproc VAL_PF0_ENTRY_BAR_4 -parent $T_PF0_4] + set V_PF0_ENTRY_ADDR_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_4 -tclproc VAL_PF0_ENTRY_ADDR_4 -parent $T_PF0_4] + set V_PF0_ENTRY_VERSION_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_4 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_4 -parent $T_PF0_4] + set V_PF0_ENTRY_MAJOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_4 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_4 -parent $T_PF0_4] + set V_PF0_ENTRY_MINOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_4 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_4 -parent $T_PF0_4] + set V_PF0_ENTRY_RSVD0_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_4 -tclproc VAL_PF0_ENTRY_RSVD0_4 -parent $T_PF0_4] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_4 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_4 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_4 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_4 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_4 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_4 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_4 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_4 + + set PF0_Values_5 [ipgui::add_group $IPINST -name "PF0 - Table Entry 5 Values" -parent $PF0_Values] + set T_PF0_5 [ipgui::add_table $IPINST -name T_PF0_5 -rows 7 -columns 2 -parent $PF0_Values_5] + set L_PF0_ENTRY_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_5 -text "C_PF0_ENTRY_TYPE_5 " -parent $T_PF0_5] + set L_PF0_ENTRY_BAR_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_5 -text "C_PF0_ENTRY_BAR_5 " -parent $T_PF0_5] + set L_PF0_ENTRY_ADDR_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_5 -text "C_PF0_ENTRY_ADDR_5 " -parent $T_PF0_5] + set L_PF0_ENTRY_VERSION_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_5 -text "C_PF0_ENTRY_VERSION_TYPE_5 " -parent $T_PF0_5] + set L_PF0_ENTRY_MAJOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_5 -text "C_PF0_ENTRY_MAJOR_VERSION_5" -parent $T_PF0_5] + set L_PF0_ENTRY_MINOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_5 -text "C_PF0_ENTRY_MINOR_VERSION_5" -parent $T_PF0_5] + set L_PF0_ENTRY_RSVD0_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_5 -text "C_PF0_ENTRY_RSVD0_5 " -parent $T_PF0_5] + set V_PF0_ENTRY_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_5 -tclproc VAL_PF0_ENTRY_TYPE_5 -parent $T_PF0_5] + set V_PF0_ENTRY_BAR_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_5 -tclproc VAL_PF0_ENTRY_BAR_5 -parent $T_PF0_5] + set V_PF0_ENTRY_ADDR_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_5 -tclproc VAL_PF0_ENTRY_ADDR_5 -parent $T_PF0_5] + set V_PF0_ENTRY_VERSION_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_5 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_5 -parent $T_PF0_5] + set V_PF0_ENTRY_MAJOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_5 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_5 -parent $T_PF0_5] + set V_PF0_ENTRY_MINOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_5 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_5 -parent $T_PF0_5] + set V_PF0_ENTRY_RSVD0_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_5 -tclproc VAL_PF0_ENTRY_RSVD0_5 -parent $T_PF0_5] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_5 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_5 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_5 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_5 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_5 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_5 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_5 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_5 + + set PF0_Values_6 [ipgui::add_group $IPINST -name "PF0 - Table Entry 6 Values" -parent $PF0_Values] + set T_PF0_6 [ipgui::add_table $IPINST -name T_PF0_6 -rows 7 -columns 2 -parent $PF0_Values_6] + set L_PF0_ENTRY_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_6 -text "C_PF0_ENTRY_TYPE_6 " -parent $T_PF0_6] + set L_PF0_ENTRY_BAR_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_6 -text "C_PF0_ENTRY_BAR_6 " -parent $T_PF0_6] + set L_PF0_ENTRY_ADDR_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_6 -text "C_PF0_ENTRY_ADDR_6 " -parent $T_PF0_6] + set L_PF0_ENTRY_VERSION_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_6 -text "C_PF0_ENTRY_VERSION_TYPE_6 " -parent $T_PF0_6] + set L_PF0_ENTRY_MAJOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_6 -text "C_PF0_ENTRY_MAJOR_VERSION_6" -parent $T_PF0_6] + set L_PF0_ENTRY_MINOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_6 -text "C_PF0_ENTRY_MINOR_VERSION_6" -parent $T_PF0_6] + set L_PF0_ENTRY_RSVD0_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_6 -text "C_PF0_ENTRY_RSVD0_6 " -parent $T_PF0_6] + set V_PF0_ENTRY_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_6 -tclproc VAL_PF0_ENTRY_TYPE_6 -parent $T_PF0_6] + set V_PF0_ENTRY_BAR_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_6 -tclproc VAL_PF0_ENTRY_BAR_6 -parent $T_PF0_6] + set V_PF0_ENTRY_ADDR_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_6 -tclproc VAL_PF0_ENTRY_ADDR_6 -parent $T_PF0_6] + set V_PF0_ENTRY_VERSION_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_6 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_6 -parent $T_PF0_6] + set V_PF0_ENTRY_MAJOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_6 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_6 -parent $T_PF0_6] + set V_PF0_ENTRY_MINOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_6 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_6 -parent $T_PF0_6] + set V_PF0_ENTRY_RSVD0_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_6 -tclproc VAL_PF0_ENTRY_RSVD0_6 -parent $T_PF0_6] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_6 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_6 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_6 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_6 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_6 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_6 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_6 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_6 + + set PF0_Values_7 [ipgui::add_group $IPINST -name "PF0 - Table Entry 7 Values" -parent $PF0_Values] + set T_PF0_7 [ipgui::add_table $IPINST -name T_PF0_7 -rows 7 -columns 2 -parent $PF0_Values_7] + set L_PF0_ENTRY_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_7 -text "C_PF0_ENTRY_TYPE_7 " -parent $T_PF0_7] + set L_PF0_ENTRY_BAR_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_7 -text "C_PF0_ENTRY_BAR_7 " -parent $T_PF0_7] + set L_PF0_ENTRY_ADDR_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_7 -text "C_PF0_ENTRY_ADDR_7 " -parent $T_PF0_7] + set L_PF0_ENTRY_VERSION_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_7 -text "C_PF0_ENTRY_VERSION_TYPE_7 " -parent $T_PF0_7] + set L_PF0_ENTRY_MAJOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_7 -text "C_PF0_ENTRY_MAJOR_VERSION_7" -parent $T_PF0_7] + set L_PF0_ENTRY_MINOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_7 -text "C_PF0_ENTRY_MINOR_VERSION_7" -parent $T_PF0_7] + set L_PF0_ENTRY_RSVD0_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_7 -text "C_PF0_ENTRY_RSVD0_7 " -parent $T_PF0_7] + set V_PF0_ENTRY_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_7 -tclproc VAL_PF0_ENTRY_TYPE_7 -parent $T_PF0_7] + set V_PF0_ENTRY_BAR_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_7 -tclproc VAL_PF0_ENTRY_BAR_7 -parent $T_PF0_7] + set V_PF0_ENTRY_ADDR_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_7 -tclproc VAL_PF0_ENTRY_ADDR_7 -parent $T_PF0_7] + set V_PF0_ENTRY_VERSION_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_7 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_7 -parent $T_PF0_7] + set V_PF0_ENTRY_MAJOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_7 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_7 -parent $T_PF0_7] + set V_PF0_ENTRY_MINOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_7 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_7 -parent $T_PF0_7] + set V_PF0_ENTRY_RSVD0_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_7 -tclproc VAL_PF0_ENTRY_RSVD0_7 -parent $T_PF0_7] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_7 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_7 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_7 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_7 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_7 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_7 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_7 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_7 + + set PF0_Values_8 [ipgui::add_group $IPINST -name "PF0 - Table Entry 8 Values" -parent $PF0_Values] + set T_PF0_8 [ipgui::add_table $IPINST -name T_PF0_8 -rows 7 -columns 2 -parent $PF0_Values_8] + set L_PF0_ENTRY_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_8 -text "C_PF0_ENTRY_TYPE_8 " -parent $T_PF0_8] + set L_PF0_ENTRY_BAR_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_8 -text "C_PF0_ENTRY_BAR_8 " -parent $T_PF0_8] + set L_PF0_ENTRY_ADDR_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_8 -text "C_PF0_ENTRY_ADDR_8 " -parent $T_PF0_8] + set L_PF0_ENTRY_VERSION_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_8 -text "C_PF0_ENTRY_VERSION_TYPE_8 " -parent $T_PF0_8] + set L_PF0_ENTRY_MAJOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_8 -text "C_PF0_ENTRY_MAJOR_VERSION_8" -parent $T_PF0_8] + set L_PF0_ENTRY_MINOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_8 -text "C_PF0_ENTRY_MINOR_VERSION_8" -parent $T_PF0_8] + set L_PF0_ENTRY_RSVD0_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_8 -text "C_PF0_ENTRY_RSVD0_8 " -parent $T_PF0_8] + set V_PF0_ENTRY_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_8 -tclproc VAL_PF0_ENTRY_TYPE_8 -parent $T_PF0_8] + set V_PF0_ENTRY_BAR_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_8 -tclproc VAL_PF0_ENTRY_BAR_8 -parent $T_PF0_8] + set V_PF0_ENTRY_ADDR_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_8 -tclproc VAL_PF0_ENTRY_ADDR_8 -parent $T_PF0_8] + set V_PF0_ENTRY_VERSION_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_8 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_8 -parent $T_PF0_8] + set V_PF0_ENTRY_MAJOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_8 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_8 -parent $T_PF0_8] + set V_PF0_ENTRY_MINOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_8 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_8 -parent $T_PF0_8] + set V_PF0_ENTRY_RSVD0_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_8 -tclproc VAL_PF0_ENTRY_RSVD0_8 -parent $T_PF0_8] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_8 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_8 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_8 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_8 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_8 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_8 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_8 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_8 + + set PF0_Values_9 [ipgui::add_group $IPINST -name "PF0 - Table Entry 9 Values" -parent $PF0_Values] + set T_PF0_9 [ipgui::add_table $IPINST -name T_PF0_9 -rows 7 -columns 2 -parent $PF0_Values_9] + set L_PF0_ENTRY_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_9 -text "C_PF0_ENTRY_TYPE_9 " -parent $T_PF0_9] + set L_PF0_ENTRY_BAR_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_9 -text "C_PF0_ENTRY_BAR_9 " -parent $T_PF0_9] + set L_PF0_ENTRY_ADDR_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_9 -text "C_PF0_ENTRY_ADDR_9 " -parent $T_PF0_9] + set L_PF0_ENTRY_VERSION_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_9 -text "C_PF0_ENTRY_VERSION_TYPE_9 " -parent $T_PF0_9] + set L_PF0_ENTRY_MAJOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_9 -text "C_PF0_ENTRY_MAJOR_VERSION_9" -parent $T_PF0_9] + set L_PF0_ENTRY_MINOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_9 -text "C_PF0_ENTRY_MINOR_VERSION_9" -parent $T_PF0_9] + set L_PF0_ENTRY_RSVD0_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_9 -text "C_PF0_ENTRY_RSVD0_9 " -parent $T_PF0_9] + set V_PF0_ENTRY_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_9 -tclproc VAL_PF0_ENTRY_TYPE_9 -parent $T_PF0_9] + set V_PF0_ENTRY_BAR_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_9 -tclproc VAL_PF0_ENTRY_BAR_9 -parent $T_PF0_9] + set V_PF0_ENTRY_ADDR_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_9 -tclproc VAL_PF0_ENTRY_ADDR_9 -parent $T_PF0_9] + set V_PF0_ENTRY_VERSION_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_9 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_9 -parent $T_PF0_9] + set V_PF0_ENTRY_MAJOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_9 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_9 -parent $T_PF0_9] + set V_PF0_ENTRY_MINOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_9 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_9 -parent $T_PF0_9] + set V_PF0_ENTRY_RSVD0_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_9 -tclproc VAL_PF0_ENTRY_RSVD0_9 -parent $T_PF0_9] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_9 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_9 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_9 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_9 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_9 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_9 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_9 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_9 + + set PF0_Values_10 [ipgui::add_group $IPINST -name "PF0 - Table Entry 10 Values" -parent $PF0_Values] + set T_PF0_10 [ipgui::add_table $IPINST -name T_PF0_10 -rows 7 -columns 2 -parent $PF0_Values_10] + set L_PF0_ENTRY_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_10 -text "C_PF0_ENTRY_TYPE_10 " -parent $T_PF0_10] + set L_PF0_ENTRY_BAR_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_10 -text "C_PF0_ENTRY_BAR_10 " -parent $T_PF0_10] + set L_PF0_ENTRY_ADDR_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_10 -text "C_PF0_ENTRY_ADDR_10 " -parent $T_PF0_10] + set L_PF0_ENTRY_VERSION_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_10 -text "C_PF0_ENTRY_VERSION_TYPE_10 " -parent $T_PF0_10] + set L_PF0_ENTRY_MAJOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_10 -text "C_PF0_ENTRY_MAJOR_VERSION_10" -parent $T_PF0_10] + set L_PF0_ENTRY_MINOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_10 -text "C_PF0_ENTRY_MINOR_VERSION_10" -parent $T_PF0_10] + set L_PF0_ENTRY_RSVD0_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_10 -text "C_PF0_ENTRY_RSVD0_10 " -parent $T_PF0_10] + set V_PF0_ENTRY_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_10 -tclproc VAL_PF0_ENTRY_TYPE_10 -parent $T_PF0_10] + set V_PF0_ENTRY_BAR_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_10 -tclproc VAL_PF0_ENTRY_BAR_10 -parent $T_PF0_10] + set V_PF0_ENTRY_ADDR_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_10 -tclproc VAL_PF0_ENTRY_ADDR_10 -parent $T_PF0_10] + set V_PF0_ENTRY_VERSION_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_10 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_10 -parent $T_PF0_10] + set V_PF0_ENTRY_MAJOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_10 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_10 -parent $T_PF0_10] + set V_PF0_ENTRY_MINOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_10 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_10 -parent $T_PF0_10] + set V_PF0_ENTRY_RSVD0_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_10 -tclproc VAL_PF0_ENTRY_RSVD0_10 -parent $T_PF0_10] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_10 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_10 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_10 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_10 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_10 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_10 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_10 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_10 + + set PF0_Values_11 [ipgui::add_group $IPINST -name "PF0 - Table Entry 11 Values" -parent $PF0_Values] + set T_PF0_11 [ipgui::add_table $IPINST -name T_PF0_11 -rows 7 -columns 2 -parent $PF0_Values_11] + set L_PF0_ENTRY_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_11 -text "C_PF0_ENTRY_TYPE_11 " -parent $T_PF0_11] + set L_PF0_ENTRY_BAR_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_11 -text "C_PF0_ENTRY_BAR_11 " -parent $T_PF0_11] + set L_PF0_ENTRY_ADDR_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_11 -text "C_PF0_ENTRY_ADDR_11 " -parent $T_PF0_11] + set L_PF0_ENTRY_VERSION_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_11 -text "C_PF0_ENTRY_VERSION_TYPE_11 " -parent $T_PF0_11] + set L_PF0_ENTRY_MAJOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_11 -text "C_PF0_ENTRY_MAJOR_VERSION_11" -parent $T_PF0_11] + set L_PF0_ENTRY_MINOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_11 -text "C_PF0_ENTRY_MINOR_VERSION_11" -parent $T_PF0_11] + set L_PF0_ENTRY_RSVD0_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_11 -text "C_PF0_ENTRY_RSVD0_11 " -parent $T_PF0_11] + set V_PF0_ENTRY_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_11 -tclproc VAL_PF0_ENTRY_TYPE_11 -parent $T_PF0_11] + set V_PF0_ENTRY_BAR_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_11 -tclproc VAL_PF0_ENTRY_BAR_11 -parent $T_PF0_11] + set V_PF0_ENTRY_ADDR_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_11 -tclproc VAL_PF0_ENTRY_ADDR_11 -parent $T_PF0_11] + set V_PF0_ENTRY_VERSION_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_11 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_11 -parent $T_PF0_11] + set V_PF0_ENTRY_MAJOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_11 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_11 -parent $T_PF0_11] + set V_PF0_ENTRY_MINOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_11 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_11 -parent $T_PF0_11] + set V_PF0_ENTRY_RSVD0_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_11 -tclproc VAL_PF0_ENTRY_RSVD0_11 -parent $T_PF0_11] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_11 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_11 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_11 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_11 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_11 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_11 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_11 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_11 + + set PF0_Values_12 [ipgui::add_group $IPINST -name "PF0 - Table Entry 12 Values" -parent $PF0_Values] + set T_PF0_12 [ipgui::add_table $IPINST -name T_PF0_12 -rows 7 -columns 2 -parent $PF0_Values_12] + set L_PF0_ENTRY_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_12 -text "C_PF0_ENTRY_TYPE_12 " -parent $T_PF0_12] + set L_PF0_ENTRY_BAR_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_12 -text "C_PF0_ENTRY_BAR_12 " -parent $T_PF0_12] + set L_PF0_ENTRY_ADDR_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_12 -text "C_PF0_ENTRY_ADDR_12 " -parent $T_PF0_12] + set L_PF0_ENTRY_VERSION_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_12 -text "C_PF0_ENTRY_VERSION_TYPE_12 " -parent $T_PF0_12] + set L_PF0_ENTRY_MAJOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_12 -text "C_PF0_ENTRY_MAJOR_VERSION_12" -parent $T_PF0_12] + set L_PF0_ENTRY_MINOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_12 -text "C_PF0_ENTRY_MINOR_VERSION_12" -parent $T_PF0_12] + set L_PF0_ENTRY_RSVD0_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_12 -text "C_PF0_ENTRY_RSVD0_12 " -parent $T_PF0_12] + set V_PF0_ENTRY_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_12 -tclproc VAL_PF0_ENTRY_TYPE_12 -parent $T_PF0_12] + set V_PF0_ENTRY_BAR_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_12 -tclproc VAL_PF0_ENTRY_BAR_12 -parent $T_PF0_12] + set V_PF0_ENTRY_ADDR_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_12 -tclproc VAL_PF0_ENTRY_ADDR_12 -parent $T_PF0_12] + set V_PF0_ENTRY_VERSION_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_12 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_12 -parent $T_PF0_12] + set V_PF0_ENTRY_MAJOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_12 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_12 -parent $T_PF0_12] + set V_PF0_ENTRY_MINOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_12 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_12 -parent $T_PF0_12] + set V_PF0_ENTRY_RSVD0_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_12 -tclproc VAL_PF0_ENTRY_RSVD0_12 -parent $T_PF0_12] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_12 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_12 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_12 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_12 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_12 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_12 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_12 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_12 + + set PF0_Values_13 [ipgui::add_group $IPINST -name "PF0 - Table Entry 13 Values" -parent $PF0_Values] + set T_PF0_13 [ipgui::add_table $IPINST -name T_PF0_13 -rows 7 -columns 2 -parent $PF0_Values_13] + set L_PF0_ENTRY_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_13 -text "C_PF0_ENTRY_TYPE_13 " -parent $T_PF0_13] + set L_PF0_ENTRY_BAR_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_13 -text "C_PF0_ENTRY_BAR_13 " -parent $T_PF0_13] + set L_PF0_ENTRY_ADDR_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_13 -text "C_PF0_ENTRY_ADDR_13 " -parent $T_PF0_13] + set L_PF0_ENTRY_VERSION_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_13 -text "C_PF0_ENTRY_VERSION_TYPE_13 " -parent $T_PF0_13] + set L_PF0_ENTRY_MAJOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_13 -text "C_PF0_ENTRY_MAJOR_VERSION_13" -parent $T_PF0_13] + set L_PF0_ENTRY_MINOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_13 -text "C_PF0_ENTRY_MINOR_VERSION_13" -parent $T_PF0_13] + set L_PF0_ENTRY_RSVD0_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_13 -text "C_PF0_ENTRY_RSVD0_13 " -parent $T_PF0_13] + set V_PF0_ENTRY_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_13 -tclproc VAL_PF0_ENTRY_TYPE_13 -parent $T_PF0_13] + set V_PF0_ENTRY_BAR_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_13 -tclproc VAL_PF0_ENTRY_BAR_13 -parent $T_PF0_13] + set V_PF0_ENTRY_ADDR_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_13 -tclproc VAL_PF0_ENTRY_ADDR_13 -parent $T_PF0_13] + set V_PF0_ENTRY_VERSION_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_13 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_13 -parent $T_PF0_13] + set V_PF0_ENTRY_MAJOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_13 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_13 -parent $T_PF0_13] + set V_PF0_ENTRY_MINOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_13 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_13 -parent $T_PF0_13] + set V_PF0_ENTRY_RSVD0_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_13 -tclproc VAL_PF0_ENTRY_RSVD0_13 -parent $T_PF0_13] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_13 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_13 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_13 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_13 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_13 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_13 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_13 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_13 + + set PF1_Values [ipgui::add_page $IPINST -name "PF1 Values"] + set PF1_Values_General [ipgui::add_group $IPINST -name "PF1 - General Values" -parent $PF1_Values] + set T_PF1_GENERAL [ipgui::add_table $IPINST -name T_PF1_GENERAL -rows 4 -columns 2 -parent $PF1_Values_General] + set L_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_static_text $IPINST -name L_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE -text "C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE" -parent $T_PF1_GENERAL] + set L_PF1_BAR_INDEX [ipgui::add_static_text $IPINST -name L_PF1_BAR_INDEX -text "C_PF1_BAR_INDEX " -parent $T_PF1_GENERAL] + set L_PF1_LOW_OFFSET [ipgui::add_static_text $IPINST -name L_PF1_LOW_OFFSET -text "C_PF1_LOW_OFFSET " -parent $T_PF1_GENERAL] + set L_PF1_HIGH_OFFSET [ipgui::add_static_text $IPINST -name L_PF1_HIGH_OFFSET -text "C_PF1_HIGH_OFFSET " -parent $T_PF1_GENERAL] + set V_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_dynamic_text $IPINST -name V_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE -tclproc VAL_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $T_PF1_GENERAL] + set V_PF1_BAR_INDEX [ipgui::add_dynamic_text $IPINST -name V_PF1_BAR_INDEX -tclproc VAL_PF1_BAR_INDEX -parent $T_PF1_GENERAL] + set V_PF1_LOW_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF1_LOW_OFFSET -tclproc VAL_PF1_LOW_OFFSET -parent $T_PF1_GENERAL] + set V_PF1_HIGH_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF1_HIGH_OFFSET -tclproc VAL_PF1_HIGH_OFFSET -parent $T_PF1_GENERAL] + set_property cell_location 0,0 $L_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,0 $L_PF1_BAR_INDEX + set_property cell_location 2,0 $L_PF1_LOW_OFFSET + set_property cell_location 3,0 $L_PF1_HIGH_OFFSET + set_property cell_location 0,1 $V_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,1 $V_PF1_BAR_INDEX + set_property cell_location 2,1 $V_PF1_LOW_OFFSET + set_property cell_location 3,1 $V_PF1_HIGH_OFFSET + set_property obj_color "192,192,192" $V_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property obj_color "192,192,192" $V_PF1_BAR_INDEX + set_property obj_color "192,192,192" $V_PF1_LOW_OFFSET + set_property obj_color "192,192,192" $V_PF1_HIGH_OFFSET + + set PF1_Values_0 [ipgui::add_group $IPINST -name "PF1 - Table Entry 0 Values" -parent $PF1_Values] + set T_PF1_0 [ipgui::add_table $IPINST -name T_PF1_0 -rows 7 -columns 2 -parent $PF1_Values_0] + set L_PF1_ENTRY_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_0 -text "C_PF1_ENTRY_TYPE_0 " -parent $T_PF1_0] + set L_PF1_ENTRY_BAR_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_0 -text "C_PF1_ENTRY_BAR_0 " -parent $T_PF1_0] + set L_PF1_ENTRY_ADDR_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_0 -text "C_PF1_ENTRY_ADDR_0 " -parent $T_PF1_0] + set L_PF1_ENTRY_VERSION_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_0 -text "C_PF1_ENTRY_VERSION_TYPE_0 " -parent $T_PF1_0] + set L_PF1_ENTRY_MAJOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_0 -text "C_PF1_ENTRY_MAJOR_VERSION_0" -parent $T_PF1_0] + set L_PF1_ENTRY_MINOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_0 -text "C_PF1_ENTRY_MINOR_VERSION_0" -parent $T_PF1_0] + set L_PF1_ENTRY_RSVD0_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_0 -text "C_PF1_ENTRY_RSVD0_0 " -parent $T_PF1_0] + set V_PF1_ENTRY_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_0 -tclproc VAL_PF1_ENTRY_TYPE_0 -parent $T_PF1_0] + set V_PF1_ENTRY_BAR_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_0 -tclproc VAL_PF1_ENTRY_BAR_0 -parent $T_PF1_0] + set V_PF1_ENTRY_ADDR_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_0 -tclproc VAL_PF1_ENTRY_ADDR_0 -parent $T_PF1_0] + set V_PF1_ENTRY_VERSION_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_0 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_0 -parent $T_PF1_0] + set V_PF1_ENTRY_MAJOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_0 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_0 -parent $T_PF1_0] + set V_PF1_ENTRY_MINOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_0 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_0 -parent $T_PF1_0] + set V_PF1_ENTRY_RSVD0_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_0 -tclproc VAL_PF1_ENTRY_RSVD0_0 -parent $T_PF1_0] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_0 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_0 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_0 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_0 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_0 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_0 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_0 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_0 + + set PF1_Values_1 [ipgui::add_group $IPINST -name "PF1 - Table Entry 1 Values" -parent $PF1_Values] + set T_PF1_1 [ipgui::add_table $IPINST -name T_PF1_1 -rows 7 -columns 2 -parent $PF1_Values_1] + set L_PF1_ENTRY_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_1 -text "C_PF1_ENTRY_TYPE_1 " -parent $T_PF1_1] + set L_PF1_ENTRY_BAR_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_1 -text "C_PF1_ENTRY_BAR_1 " -parent $T_PF1_1] + set L_PF1_ENTRY_ADDR_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_1 -text "C_PF1_ENTRY_ADDR_1 " -parent $T_PF1_1] + set L_PF1_ENTRY_VERSION_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_1 -text "C_PF1_ENTRY_VERSION_TYPE_1 " -parent $T_PF1_1] + set L_PF1_ENTRY_MAJOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_1 -text "C_PF1_ENTRY_MAJOR_VERSION_1" -parent $T_PF1_1] + set L_PF1_ENTRY_MINOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_1 -text "C_PF1_ENTRY_MINOR_VERSION_1" -parent $T_PF1_1] + set L_PF1_ENTRY_RSVD0_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_1 -text "C_PF1_ENTRY_RSVD0_1 " -parent $T_PF1_1] + set V_PF1_ENTRY_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_1 -tclproc VAL_PF1_ENTRY_TYPE_1 -parent $T_PF1_1] + set V_PF1_ENTRY_BAR_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_1 -tclproc VAL_PF1_ENTRY_BAR_1 -parent $T_PF1_1] + set V_PF1_ENTRY_ADDR_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_1 -tclproc VAL_PF1_ENTRY_ADDR_1 -parent $T_PF1_1] + set V_PF1_ENTRY_VERSION_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_1 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_1 -parent $T_PF1_1] + set V_PF1_ENTRY_MAJOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_1 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_1 -parent $T_PF1_1] + set V_PF1_ENTRY_MINOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_1 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_1 -parent $T_PF1_1] + set V_PF1_ENTRY_RSVD0_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_1 -tclproc VAL_PF1_ENTRY_RSVD0_1 -parent $T_PF1_1] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_1 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_1 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_1 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_1 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_1 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_1 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_1 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_1 + + set PF1_Values_2 [ipgui::add_group $IPINST -name "PF1 - Table Entry 2 Values" -parent $PF1_Values] + set T_PF1_2 [ipgui::add_table $IPINST -name T_PF1_2 -rows 7 -columns 2 -parent $PF1_Values_2] + set L_PF1_ENTRY_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_2 -text "C_PF1_ENTRY_TYPE_2 " -parent $T_PF1_2] + set L_PF1_ENTRY_BAR_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_2 -text "C_PF1_ENTRY_BAR_2 " -parent $T_PF1_2] + set L_PF1_ENTRY_ADDR_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_2 -text "C_PF1_ENTRY_ADDR_2 " -parent $T_PF1_2] + set L_PF1_ENTRY_VERSION_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_2 -text "C_PF1_ENTRY_VERSION_TYPE_2 " -parent $T_PF1_2] + set L_PF1_ENTRY_MAJOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_2 -text "C_PF1_ENTRY_MAJOR_VERSION_2" -parent $T_PF1_2] + set L_PF1_ENTRY_MINOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_2 -text "C_PF1_ENTRY_MINOR_VERSION_2" -parent $T_PF1_2] + set L_PF1_ENTRY_RSVD0_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_2 -text "C_PF1_ENTRY_RSVD0_2 " -parent $T_PF1_2] + set V_PF1_ENTRY_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_2 -tclproc VAL_PF1_ENTRY_TYPE_2 -parent $T_PF1_2] + set V_PF1_ENTRY_BAR_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_2 -tclproc VAL_PF1_ENTRY_BAR_2 -parent $T_PF1_2] + set V_PF1_ENTRY_ADDR_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_2 -tclproc VAL_PF1_ENTRY_ADDR_2 -parent $T_PF1_2] + set V_PF1_ENTRY_VERSION_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_2 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_2 -parent $T_PF1_2] + set V_PF1_ENTRY_MAJOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_2 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_2 -parent $T_PF1_2] + set V_PF1_ENTRY_MINOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_2 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_2 -parent $T_PF1_2] + set V_PF1_ENTRY_RSVD0_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_2 -tclproc VAL_PF1_ENTRY_RSVD0_2 -parent $T_PF1_2] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_2 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_2 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_2 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_2 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_2 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_2 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_2 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_2 + + set PF1_Values_3 [ipgui::add_group $IPINST -name "PF1 - Table Entry 3 Values" -parent $PF1_Values] + set T_PF1_3 [ipgui::add_table $IPINST -name T_PF1_3 -rows 7 -columns 2 -parent $PF1_Values_3] + set L_PF1_ENTRY_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_3 -text "C_PF1_ENTRY_TYPE_3 " -parent $T_PF1_3] + set L_PF1_ENTRY_BAR_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_3 -text "C_PF1_ENTRY_BAR_3 " -parent $T_PF1_3] + set L_PF1_ENTRY_ADDR_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_3 -text "C_PF1_ENTRY_ADDR_3 " -parent $T_PF1_3] + set L_PF1_ENTRY_VERSION_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_3 -text "C_PF1_ENTRY_VERSION_TYPE_3 " -parent $T_PF1_3] + set L_PF1_ENTRY_MAJOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_3 -text "C_PF1_ENTRY_MAJOR_VERSION_3" -parent $T_PF1_3] + set L_PF1_ENTRY_MINOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_3 -text "C_PF1_ENTRY_MINOR_VERSION_3" -parent $T_PF1_3] + set L_PF1_ENTRY_RSVD0_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_3 -text "C_PF1_ENTRY_RSVD0_3 " -parent $T_PF1_3] + set V_PF1_ENTRY_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_3 -tclproc VAL_PF1_ENTRY_TYPE_3 -parent $T_PF1_3] + set V_PF1_ENTRY_BAR_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_3 -tclproc VAL_PF1_ENTRY_BAR_3 -parent $T_PF1_3] + set V_PF1_ENTRY_ADDR_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_3 -tclproc VAL_PF1_ENTRY_ADDR_3 -parent $T_PF1_3] + set V_PF1_ENTRY_VERSION_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_3 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_3 -parent $T_PF1_3] + set V_PF1_ENTRY_MAJOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_3 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_3 -parent $T_PF1_3] + set V_PF1_ENTRY_MINOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_3 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_3 -parent $T_PF1_3] + set V_PF1_ENTRY_RSVD0_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_3 -tclproc VAL_PF1_ENTRY_RSVD0_3 -parent $T_PF1_3] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_3 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_3 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_3 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_3 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_3 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_3 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_3 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_3 + + set PF1_Values_4 [ipgui::add_group $IPINST -name "PF1 - Table Entry 4 Values" -parent $PF1_Values] + set T_PF1_4 [ipgui::add_table $IPINST -name T_PF1_4 -rows 7 -columns 2 -parent $PF1_Values_4] + set L_PF1_ENTRY_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_4 -text "C_PF1_ENTRY_TYPE_4 " -parent $T_PF1_4] + set L_PF1_ENTRY_BAR_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_4 -text "C_PF1_ENTRY_BAR_4 " -parent $T_PF1_4] + set L_PF1_ENTRY_ADDR_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_4 -text "C_PF1_ENTRY_ADDR_4 " -parent $T_PF1_4] + set L_PF1_ENTRY_VERSION_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_4 -text "C_PF1_ENTRY_VERSION_TYPE_4 " -parent $T_PF1_4] + set L_PF1_ENTRY_MAJOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_4 -text "C_PF1_ENTRY_MAJOR_VERSION_4" -parent $T_PF1_4] + set L_PF1_ENTRY_MINOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_4 -text "C_PF1_ENTRY_MINOR_VERSION_4" -parent $T_PF1_4] + set L_PF1_ENTRY_RSVD0_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_4 -text "C_PF1_ENTRY_RSVD0_4 " -parent $T_PF1_4] + set V_PF1_ENTRY_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_4 -tclproc VAL_PF1_ENTRY_TYPE_4 -parent $T_PF1_4] + set V_PF1_ENTRY_BAR_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_4 -tclproc VAL_PF1_ENTRY_BAR_4 -parent $T_PF1_4] + set V_PF1_ENTRY_ADDR_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_4 -tclproc VAL_PF1_ENTRY_ADDR_4 -parent $T_PF1_4] + set V_PF1_ENTRY_VERSION_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_4 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_4 -parent $T_PF1_4] + set V_PF1_ENTRY_MAJOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_4 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_4 -parent $T_PF1_4] + set V_PF1_ENTRY_MINOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_4 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_4 -parent $T_PF1_4] + set V_PF1_ENTRY_RSVD0_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_4 -tclproc VAL_PF1_ENTRY_RSVD0_4 -parent $T_PF1_4] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_4 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_4 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_4 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_4 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_4 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_4 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_4 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_4 + + set PF1_Values_5 [ipgui::add_group $IPINST -name "PF1 - Table Entry 5 Values" -parent $PF1_Values] + set T_PF1_5 [ipgui::add_table $IPINST -name T_PF1_5 -rows 7 -columns 2 -parent $PF1_Values_5] + set L_PF1_ENTRY_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_5 -text "C_PF1_ENTRY_TYPE_5 " -parent $T_PF1_5] + set L_PF1_ENTRY_BAR_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_5 -text "C_PF1_ENTRY_BAR_5 " -parent $T_PF1_5] + set L_PF1_ENTRY_ADDR_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_5 -text "C_PF1_ENTRY_ADDR_5 " -parent $T_PF1_5] + set L_PF1_ENTRY_VERSION_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_5 -text "C_PF1_ENTRY_VERSION_TYPE_5 " -parent $T_PF1_5] + set L_PF1_ENTRY_MAJOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_5 -text "C_PF1_ENTRY_MAJOR_VERSION_5" -parent $T_PF1_5] + set L_PF1_ENTRY_MINOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_5 -text "C_PF1_ENTRY_MINOR_VERSION_5" -parent $T_PF1_5] + set L_PF1_ENTRY_RSVD0_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_5 -text "C_PF1_ENTRY_RSVD0_5 " -parent $T_PF1_5] + set V_PF1_ENTRY_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_5 -tclproc VAL_PF1_ENTRY_TYPE_5 -parent $T_PF1_5] + set V_PF1_ENTRY_BAR_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_5 -tclproc VAL_PF1_ENTRY_BAR_5 -parent $T_PF1_5] + set V_PF1_ENTRY_ADDR_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_5 -tclproc VAL_PF1_ENTRY_ADDR_5 -parent $T_PF1_5] + set V_PF1_ENTRY_VERSION_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_5 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_5 -parent $T_PF1_5] + set V_PF1_ENTRY_MAJOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_5 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_5 -parent $T_PF1_5] + set V_PF1_ENTRY_MINOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_5 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_5 -parent $T_PF1_5] + set V_PF1_ENTRY_RSVD0_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_5 -tclproc VAL_PF1_ENTRY_RSVD0_5 -parent $T_PF1_5] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_5 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_5 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_5 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_5 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_5 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_5 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_5 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_5 + + set PF1_Values_6 [ipgui::add_group $IPINST -name "PF1 - Table Entry 6 Values" -parent $PF1_Values] + set T_PF1_6 [ipgui::add_table $IPINST -name T_PF1_6 -rows 7 -columns 2 -parent $PF1_Values_6] + set L_PF1_ENTRY_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_6 -text "C_PF1_ENTRY_TYPE_6 " -parent $T_PF1_6] + set L_PF1_ENTRY_BAR_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_6 -text "C_PF1_ENTRY_BAR_6 " -parent $T_PF1_6] + set L_PF1_ENTRY_ADDR_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_6 -text "C_PF1_ENTRY_ADDR_6 " -parent $T_PF1_6] + set L_PF1_ENTRY_VERSION_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_6 -text "C_PF1_ENTRY_VERSION_TYPE_6 " -parent $T_PF1_6] + set L_PF1_ENTRY_MAJOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_6 -text "C_PF1_ENTRY_MAJOR_VERSION_6" -parent $T_PF1_6] + set L_PF1_ENTRY_MINOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_6 -text "C_PF1_ENTRY_MINOR_VERSION_6" -parent $T_PF1_6] + set L_PF1_ENTRY_RSVD0_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_6 -text "C_PF1_ENTRY_RSVD0_6 " -parent $T_PF1_6] + set V_PF1_ENTRY_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_6 -tclproc VAL_PF1_ENTRY_TYPE_6 -parent $T_PF1_6] + set V_PF1_ENTRY_BAR_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_6 -tclproc VAL_PF1_ENTRY_BAR_6 -parent $T_PF1_6] + set V_PF1_ENTRY_ADDR_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_6 -tclproc VAL_PF1_ENTRY_ADDR_6 -parent $T_PF1_6] + set V_PF1_ENTRY_VERSION_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_6 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_6 -parent $T_PF1_6] + set V_PF1_ENTRY_MAJOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_6 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_6 -parent $T_PF1_6] + set V_PF1_ENTRY_MINOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_6 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_6 -parent $T_PF1_6] + set V_PF1_ENTRY_RSVD0_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_6 -tclproc VAL_PF1_ENTRY_RSVD0_6 -parent $T_PF1_6] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_6 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_6 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_6 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_6 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_6 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_6 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_6 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_6 + + set PF1_Values_7 [ipgui::add_group $IPINST -name "PF1 - Table Entry 7 Values" -parent $PF1_Values] + set T_PF1_7 [ipgui::add_table $IPINST -name T_PF1_7 -rows 7 -columns 2 -parent $PF1_Values_7] + set L_PF1_ENTRY_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_7 -text "C_PF1_ENTRY_TYPE_7 " -parent $T_PF1_7] + set L_PF1_ENTRY_BAR_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_7 -text "C_PF1_ENTRY_BAR_7 " -parent $T_PF1_7] + set L_PF1_ENTRY_ADDR_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_7 -text "C_PF1_ENTRY_ADDR_7 " -parent $T_PF1_7] + set L_PF1_ENTRY_VERSION_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_7 -text "C_PF1_ENTRY_VERSION_TYPE_7 " -parent $T_PF1_7] + set L_PF1_ENTRY_MAJOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_7 -text "C_PF1_ENTRY_MAJOR_VERSION_7" -parent $T_PF1_7] + set L_PF1_ENTRY_MINOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_7 -text "C_PF1_ENTRY_MINOR_VERSION_7" -parent $T_PF1_7] + set L_PF1_ENTRY_RSVD0_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_7 -text "C_PF1_ENTRY_RSVD0_7 " -parent $T_PF1_7] + set V_PF1_ENTRY_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_7 -tclproc VAL_PF1_ENTRY_TYPE_7 -parent $T_PF1_7] + set V_PF1_ENTRY_BAR_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_7 -tclproc VAL_PF1_ENTRY_BAR_7 -parent $T_PF1_7] + set V_PF1_ENTRY_ADDR_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_7 -tclproc VAL_PF1_ENTRY_ADDR_7 -parent $T_PF1_7] + set V_PF1_ENTRY_VERSION_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_7 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_7 -parent $T_PF1_7] + set V_PF1_ENTRY_MAJOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_7 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_7 -parent $T_PF1_7] + set V_PF1_ENTRY_MINOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_7 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_7 -parent $T_PF1_7] + set V_PF1_ENTRY_RSVD0_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_7 -tclproc VAL_PF1_ENTRY_RSVD0_7 -parent $T_PF1_7] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_7 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_7 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_7 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_7 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_7 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_7 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_7 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_7 + + set PF1_Values_8 [ipgui::add_group $IPINST -name "PF1 - Table Entry 8 Values" -parent $PF1_Values] + set T_PF1_8 [ipgui::add_table $IPINST -name T_PF1_8 -rows 7 -columns 2 -parent $PF1_Values_8] + set L_PF1_ENTRY_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_8 -text "C_PF1_ENTRY_TYPE_8 " -parent $T_PF1_8] + set L_PF1_ENTRY_BAR_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_8 -text "C_PF1_ENTRY_BAR_8 " -parent $T_PF1_8] + set L_PF1_ENTRY_ADDR_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_8 -text "C_PF1_ENTRY_ADDR_8 " -parent $T_PF1_8] + set L_PF1_ENTRY_VERSION_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_8 -text "C_PF1_ENTRY_VERSION_TYPE_8 " -parent $T_PF1_8] + set L_PF1_ENTRY_MAJOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_8 -text "C_PF1_ENTRY_MAJOR_VERSION_8" -parent $T_PF1_8] + set L_PF1_ENTRY_MINOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_8 -text "C_PF1_ENTRY_MINOR_VERSION_8" -parent $T_PF1_8] + set L_PF1_ENTRY_RSVD0_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_8 -text "C_PF1_ENTRY_RSVD0_8 " -parent $T_PF1_8] + set V_PF1_ENTRY_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_8 -tclproc VAL_PF1_ENTRY_TYPE_8 -parent $T_PF1_8] + set V_PF1_ENTRY_BAR_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_8 -tclproc VAL_PF1_ENTRY_BAR_8 -parent $T_PF1_8] + set V_PF1_ENTRY_ADDR_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_8 -tclproc VAL_PF1_ENTRY_ADDR_8 -parent $T_PF1_8] + set V_PF1_ENTRY_VERSION_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_8 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_8 -parent $T_PF1_8] + set V_PF1_ENTRY_MAJOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_8 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_8 -parent $T_PF1_8] + set V_PF1_ENTRY_MINOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_8 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_8 -parent $T_PF1_8] + set V_PF1_ENTRY_RSVD0_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_8 -tclproc VAL_PF1_ENTRY_RSVD0_8 -parent $T_PF1_8] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_8 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_8 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_8 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_8 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_8 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_8 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_8 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_8 + + set PF1_Values_9 [ipgui::add_group $IPINST -name "PF1 - Table Entry 9 Values" -parent $PF1_Values] + set T_PF1_9 [ipgui::add_table $IPINST -name T_PF1_9 -rows 7 -columns 2 -parent $PF1_Values_9] + set L_PF1_ENTRY_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_9 -text "C_PF1_ENTRY_TYPE_9 " -parent $T_PF1_9] + set L_PF1_ENTRY_BAR_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_9 -text "C_PF1_ENTRY_BAR_9 " -parent $T_PF1_9] + set L_PF1_ENTRY_ADDR_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_9 -text "C_PF1_ENTRY_ADDR_9 " -parent $T_PF1_9] + set L_PF1_ENTRY_VERSION_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_9 -text "C_PF1_ENTRY_VERSION_TYPE_9 " -parent $T_PF1_9] + set L_PF1_ENTRY_MAJOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_9 -text "C_PF1_ENTRY_MAJOR_VERSION_9" -parent $T_PF1_9] + set L_PF1_ENTRY_MINOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_9 -text "C_PF1_ENTRY_MINOR_VERSION_9" -parent $T_PF1_9] + set L_PF1_ENTRY_RSVD0_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_9 -text "C_PF1_ENTRY_RSVD0_9 " -parent $T_PF1_9] + set V_PF1_ENTRY_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_9 -tclproc VAL_PF1_ENTRY_TYPE_9 -parent $T_PF1_9] + set V_PF1_ENTRY_BAR_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_9 -tclproc VAL_PF1_ENTRY_BAR_9 -parent $T_PF1_9] + set V_PF1_ENTRY_ADDR_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_9 -tclproc VAL_PF1_ENTRY_ADDR_9 -parent $T_PF1_9] + set V_PF1_ENTRY_VERSION_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_9 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_9 -parent $T_PF1_9] + set V_PF1_ENTRY_MAJOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_9 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_9 -parent $T_PF1_9] + set V_PF1_ENTRY_MINOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_9 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_9 -parent $T_PF1_9] + set V_PF1_ENTRY_RSVD0_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_9 -tclproc VAL_PF1_ENTRY_RSVD0_9 -parent $T_PF1_9] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_9 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_9 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_9 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_9 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_9 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_9 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_9 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_9 + + set PF1_Values_10 [ipgui::add_group $IPINST -name "PF1 - Table Entry 10 Values" -parent $PF1_Values] + set T_PF1_10 [ipgui::add_table $IPINST -name T_PF1_10 -rows 7 -columns 2 -parent $PF1_Values_10] + set L_PF1_ENTRY_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_10 -text "C_PF1_ENTRY_TYPE_10 " -parent $T_PF1_10] + set L_PF1_ENTRY_BAR_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_10 -text "C_PF1_ENTRY_BAR_10 " -parent $T_PF1_10] + set L_PF1_ENTRY_ADDR_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_10 -text "C_PF1_ENTRY_ADDR_10 " -parent $T_PF1_10] + set L_PF1_ENTRY_VERSION_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_10 -text "C_PF1_ENTRY_VERSION_TYPE_10 " -parent $T_PF1_10] + set L_PF1_ENTRY_MAJOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_10 -text "C_PF1_ENTRY_MAJOR_VERSION_10" -parent $T_PF1_10] + set L_PF1_ENTRY_MINOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_10 -text "C_PF1_ENTRY_MINOR_VERSION_10" -parent $T_PF1_10] + set L_PF1_ENTRY_RSVD0_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_10 -text "C_PF1_ENTRY_RSVD0_10 " -parent $T_PF1_10] + set V_PF1_ENTRY_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_10 -tclproc VAL_PF1_ENTRY_TYPE_10 -parent $T_PF1_10] + set V_PF1_ENTRY_BAR_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_10 -tclproc VAL_PF1_ENTRY_BAR_10 -parent $T_PF1_10] + set V_PF1_ENTRY_ADDR_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_10 -tclproc VAL_PF1_ENTRY_ADDR_10 -parent $T_PF1_10] + set V_PF1_ENTRY_VERSION_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_10 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_10 -parent $T_PF1_10] + set V_PF1_ENTRY_MAJOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_10 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_10 -parent $T_PF1_10] + set V_PF1_ENTRY_MINOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_10 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_10 -parent $T_PF1_10] + set V_PF1_ENTRY_RSVD0_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_10 -tclproc VAL_PF1_ENTRY_RSVD0_10 -parent $T_PF1_10] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_10 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_10 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_10 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_10 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_10 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_10 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_10 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_10 + + set PF1_Values_11 [ipgui::add_group $IPINST -name "PF1 - Table Entry 11 Values" -parent $PF1_Values] + set T_PF1_11 [ipgui::add_table $IPINST -name T_PF1_11 -rows 7 -columns 2 -parent $PF1_Values_11] + set L_PF1_ENTRY_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_11 -text "C_PF1_ENTRY_TYPE_11 " -parent $T_PF1_11] + set L_PF1_ENTRY_BAR_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_11 -text "C_PF1_ENTRY_BAR_11 " -parent $T_PF1_11] + set L_PF1_ENTRY_ADDR_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_11 -text "C_PF1_ENTRY_ADDR_11 " -parent $T_PF1_11] + set L_PF1_ENTRY_VERSION_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_11 -text "C_PF1_ENTRY_VERSION_TYPE_11 " -parent $T_PF1_11] + set L_PF1_ENTRY_MAJOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_11 -text "C_PF1_ENTRY_MAJOR_VERSION_11" -parent $T_PF1_11] + set L_PF1_ENTRY_MINOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_11 -text "C_PF1_ENTRY_MINOR_VERSION_11" -parent $T_PF1_11] + set L_PF1_ENTRY_RSVD0_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_11 -text "C_PF1_ENTRY_RSVD0_11 " -parent $T_PF1_11] + set V_PF1_ENTRY_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_11 -tclproc VAL_PF1_ENTRY_TYPE_11 -parent $T_PF1_11] + set V_PF1_ENTRY_BAR_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_11 -tclproc VAL_PF1_ENTRY_BAR_11 -parent $T_PF1_11] + set V_PF1_ENTRY_ADDR_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_11 -tclproc VAL_PF1_ENTRY_ADDR_11 -parent $T_PF1_11] + set V_PF1_ENTRY_VERSION_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_11 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_11 -parent $T_PF1_11] + set V_PF1_ENTRY_MAJOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_11 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_11 -parent $T_PF1_11] + set V_PF1_ENTRY_MINOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_11 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_11 -parent $T_PF1_11] + set V_PF1_ENTRY_RSVD0_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_11 -tclproc VAL_PF1_ENTRY_RSVD0_11 -parent $T_PF1_11] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_11 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_11 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_11 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_11 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_11 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_11 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_11 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_11 + + set PF1_Values_12 [ipgui::add_group $IPINST -name "PF1 - Table Entry 12 Values" -parent $PF1_Values] + set T_PF1_12 [ipgui::add_table $IPINST -name T_PF1_12 -rows 7 -columns 2 -parent $PF1_Values_12] + set L_PF1_ENTRY_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_12 -text "C_PF1_ENTRY_TYPE_12 " -parent $T_PF1_12] + set L_PF1_ENTRY_BAR_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_12 -text "C_PF1_ENTRY_BAR_12 " -parent $T_PF1_12] + set L_PF1_ENTRY_ADDR_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_12 -text "C_PF1_ENTRY_ADDR_12 " -parent $T_PF1_12] + set L_PF1_ENTRY_VERSION_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_12 -text "C_PF1_ENTRY_VERSION_TYPE_12 " -parent $T_PF1_12] + set L_PF1_ENTRY_MAJOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_12 -text "C_PF1_ENTRY_MAJOR_VERSION_12" -parent $T_PF1_12] + set L_PF1_ENTRY_MINOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_12 -text "C_PF1_ENTRY_MINOR_VERSION_12" -parent $T_PF1_12] + set L_PF1_ENTRY_RSVD0_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_12 -text "C_PF1_ENTRY_RSVD0_12 " -parent $T_PF1_12] + set V_PF1_ENTRY_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_12 -tclproc VAL_PF1_ENTRY_TYPE_12 -parent $T_PF1_12] + set V_PF1_ENTRY_BAR_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_12 -tclproc VAL_PF1_ENTRY_BAR_12 -parent $T_PF1_12] + set V_PF1_ENTRY_ADDR_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_12 -tclproc VAL_PF1_ENTRY_ADDR_12 -parent $T_PF1_12] + set V_PF1_ENTRY_VERSION_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_12 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_12 -parent $T_PF1_12] + set V_PF1_ENTRY_MAJOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_12 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_12 -parent $T_PF1_12] + set V_PF1_ENTRY_MINOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_12 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_12 -parent $T_PF1_12] + set V_PF1_ENTRY_RSVD0_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_12 -tclproc VAL_PF1_ENTRY_RSVD0_12 -parent $T_PF1_12] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_12 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_12 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_12 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_12 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_12 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_12 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_12 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_12 + + set PF1_Values_13 [ipgui::add_group $IPINST -name "PF1 - Table Entry 13 Values" -parent $PF1_Values] + set T_PF1_13 [ipgui::add_table $IPINST -name T_PF1_13 -rows 7 -columns 2 -parent $PF1_Values_13] + set L_PF1_ENTRY_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_13 -text "C_PF1_ENTRY_TYPE_13 " -parent $T_PF1_13] + set L_PF1_ENTRY_BAR_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_13 -text "C_PF1_ENTRY_BAR_13 " -parent $T_PF1_13] + set L_PF1_ENTRY_ADDR_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_13 -text "C_PF1_ENTRY_ADDR_13 " -parent $T_PF1_13] + set L_PF1_ENTRY_VERSION_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_13 -text "C_PF1_ENTRY_VERSION_TYPE_13 " -parent $T_PF1_13] + set L_PF1_ENTRY_MAJOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_13 -text "C_PF1_ENTRY_MAJOR_VERSION_13" -parent $T_PF1_13] + set L_PF1_ENTRY_MINOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_13 -text "C_PF1_ENTRY_MINOR_VERSION_13" -parent $T_PF1_13] + set L_PF1_ENTRY_RSVD0_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_13 -text "C_PF1_ENTRY_RSVD0_13 " -parent $T_PF1_13] + set V_PF1_ENTRY_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_13 -tclproc VAL_PF1_ENTRY_TYPE_13 -parent $T_PF1_13] + set V_PF1_ENTRY_BAR_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_13 -tclproc VAL_PF1_ENTRY_BAR_13 -parent $T_PF1_13] + set V_PF1_ENTRY_ADDR_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_13 -tclproc VAL_PF1_ENTRY_ADDR_13 -parent $T_PF1_13] + set V_PF1_ENTRY_VERSION_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_13 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_13 -parent $T_PF1_13] + set V_PF1_ENTRY_MAJOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_13 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_13 -parent $T_PF1_13] + set V_PF1_ENTRY_MINOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_13 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_13 -parent $T_PF1_13] + set V_PF1_ENTRY_RSVD0_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_13 -tclproc VAL_PF1_ENTRY_RSVD0_13 -parent $T_PF1_13] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_13 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_13 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_13 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_13 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_13 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_13 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_13 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_13 + + set PF2_Values [ipgui::add_page $IPINST -name "PF2 Values"] + set PF2_Values_General [ipgui::add_group $IPINST -name "PF2 - General Values" -parent $PF2_Values] + set T_PF2_GENERAL [ipgui::add_table $IPINST -name T_PF2_GENERAL -rows 4 -columns 2 -parent $PF2_Values_General] + set L_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_static_text $IPINST -name L_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE -text "C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE" -parent $T_PF2_GENERAL] + set L_PF2_BAR_INDEX [ipgui::add_static_text $IPINST -name L_PF2_BAR_INDEX -text "C_PF2_BAR_INDEX " -parent $T_PF2_GENERAL] + set L_PF2_LOW_OFFSET [ipgui::add_static_text $IPINST -name L_PF2_LOW_OFFSET -text "C_PF2_LOW_OFFSET " -parent $T_PF2_GENERAL] + set L_PF2_HIGH_OFFSET [ipgui::add_static_text $IPINST -name L_PF2_HIGH_OFFSET -text "C_PF2_HIGH_OFFSET " -parent $T_PF2_GENERAL] + set V_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_dynamic_text $IPINST -name V_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE -tclproc VAL_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $T_PF2_GENERAL] + set V_PF2_BAR_INDEX [ipgui::add_dynamic_text $IPINST -name V_PF2_BAR_INDEX -tclproc VAL_PF2_BAR_INDEX -parent $T_PF2_GENERAL] + set V_PF2_LOW_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF2_LOW_OFFSET -tclproc VAL_PF2_LOW_OFFSET -parent $T_PF2_GENERAL] + set V_PF2_HIGH_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF2_HIGH_OFFSET -tclproc VAL_PF2_HIGH_OFFSET -parent $T_PF2_GENERAL] + set_property cell_location 0,0 $L_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,0 $L_PF2_BAR_INDEX + set_property cell_location 2,0 $L_PF2_LOW_OFFSET + set_property cell_location 3,0 $L_PF2_HIGH_OFFSET + set_property cell_location 0,1 $V_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,1 $V_PF2_BAR_INDEX + set_property cell_location 2,1 $V_PF2_LOW_OFFSET + set_property cell_location 3,1 $V_PF2_HIGH_OFFSET + set_property obj_color "192,192,192" $V_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property obj_color "192,192,192" $V_PF2_BAR_INDEX + set_property obj_color "192,192,192" $V_PF2_LOW_OFFSET + set_property obj_color "192,192,192" $V_PF2_HIGH_OFFSET + + set PF2_Values_0 [ipgui::add_group $IPINST -name "PF2 - Table Entry 0 Values" -parent $PF2_Values] + set T_PF2_0 [ipgui::add_table $IPINST -name T_PF2_0 -rows 7 -columns 2 -parent $PF2_Values_0] + set L_PF2_ENTRY_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_0 -text "C_PF2_ENTRY_TYPE_0 " -parent $T_PF2_0] + set L_PF2_ENTRY_BAR_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_0 -text "C_PF2_ENTRY_BAR_0 " -parent $T_PF2_0] + set L_PF2_ENTRY_ADDR_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_0 -text "C_PF2_ENTRY_ADDR_0 " -parent $T_PF2_0] + set L_PF2_ENTRY_VERSION_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_0 -text "C_PF2_ENTRY_VERSION_TYPE_0 " -parent $T_PF2_0] + set L_PF2_ENTRY_MAJOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_0 -text "C_PF2_ENTRY_MAJOR_VERSION_0" -parent $T_PF2_0] + set L_PF2_ENTRY_MINOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_0 -text "C_PF2_ENTRY_MINOR_VERSION_0" -parent $T_PF2_0] + set L_PF2_ENTRY_RSVD0_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_0 -text "C_PF2_ENTRY_RSVD0_0 " -parent $T_PF2_0] + set V_PF2_ENTRY_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_0 -tclproc VAL_PF2_ENTRY_TYPE_0 -parent $T_PF2_0] + set V_PF2_ENTRY_BAR_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_0 -tclproc VAL_PF2_ENTRY_BAR_0 -parent $T_PF2_0] + set V_PF2_ENTRY_ADDR_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_0 -tclproc VAL_PF2_ENTRY_ADDR_0 -parent $T_PF2_0] + set V_PF2_ENTRY_VERSION_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_0 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_0 -parent $T_PF2_0] + set V_PF2_ENTRY_MAJOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_0 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_0 -parent $T_PF2_0] + set V_PF2_ENTRY_MINOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_0 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_0 -parent $T_PF2_0] + set V_PF2_ENTRY_RSVD0_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_0 -tclproc VAL_PF2_ENTRY_RSVD0_0 -parent $T_PF2_0] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_0 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_0 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_0 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_0 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_0 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_0 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_0 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_0 + + set PF2_Values_1 [ipgui::add_group $IPINST -name "PF2 - Table Entry 1 Values" -parent $PF2_Values] + set T_PF2_1 [ipgui::add_table $IPINST -name T_PF2_1 -rows 7 -columns 2 -parent $PF2_Values_1] + set L_PF2_ENTRY_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_1 -text "C_PF2_ENTRY_TYPE_1 " -parent $T_PF2_1] + set L_PF2_ENTRY_BAR_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_1 -text "C_PF2_ENTRY_BAR_1 " -parent $T_PF2_1] + set L_PF2_ENTRY_ADDR_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_1 -text "C_PF2_ENTRY_ADDR_1 " -parent $T_PF2_1] + set L_PF2_ENTRY_VERSION_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_1 -text "C_PF2_ENTRY_VERSION_TYPE_1 " -parent $T_PF2_1] + set L_PF2_ENTRY_MAJOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_1 -text "C_PF2_ENTRY_MAJOR_VERSION_1" -parent $T_PF2_1] + set L_PF2_ENTRY_MINOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_1 -text "C_PF2_ENTRY_MINOR_VERSION_1" -parent $T_PF2_1] + set L_PF2_ENTRY_RSVD0_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_1 -text "C_PF2_ENTRY_RSVD0_1 " -parent $T_PF2_1] + set V_PF2_ENTRY_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_1 -tclproc VAL_PF2_ENTRY_TYPE_1 -parent $T_PF2_1] + set V_PF2_ENTRY_BAR_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_1 -tclproc VAL_PF2_ENTRY_BAR_1 -parent $T_PF2_1] + set V_PF2_ENTRY_ADDR_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_1 -tclproc VAL_PF2_ENTRY_ADDR_1 -parent $T_PF2_1] + set V_PF2_ENTRY_VERSION_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_1 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_1 -parent $T_PF2_1] + set V_PF2_ENTRY_MAJOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_1 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_1 -parent $T_PF2_1] + set V_PF2_ENTRY_MINOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_1 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_1 -parent $T_PF2_1] + set V_PF2_ENTRY_RSVD0_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_1 -tclproc VAL_PF2_ENTRY_RSVD0_1 -parent $T_PF2_1] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_1 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_1 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_1 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_1 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_1 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_1 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_1 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_1 + + set PF2_Values_2 [ipgui::add_group $IPINST -name "PF2 - Table Entry 2 Values" -parent $PF2_Values] + set T_PF2_2 [ipgui::add_table $IPINST -name T_PF2_2 -rows 7 -columns 2 -parent $PF2_Values_2] + set L_PF2_ENTRY_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_2 -text "C_PF2_ENTRY_TYPE_2 " -parent $T_PF2_2] + set L_PF2_ENTRY_BAR_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_2 -text "C_PF2_ENTRY_BAR_2 " -parent $T_PF2_2] + set L_PF2_ENTRY_ADDR_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_2 -text "C_PF2_ENTRY_ADDR_2 " -parent $T_PF2_2] + set L_PF2_ENTRY_VERSION_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_2 -text "C_PF2_ENTRY_VERSION_TYPE_2 " -parent $T_PF2_2] + set L_PF2_ENTRY_MAJOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_2 -text "C_PF2_ENTRY_MAJOR_VERSION_2" -parent $T_PF2_2] + set L_PF2_ENTRY_MINOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_2 -text "C_PF2_ENTRY_MINOR_VERSION_2" -parent $T_PF2_2] + set L_PF2_ENTRY_RSVD0_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_2 -text "C_PF2_ENTRY_RSVD0_2 " -parent $T_PF2_2] + set V_PF2_ENTRY_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_2 -tclproc VAL_PF2_ENTRY_TYPE_2 -parent $T_PF2_2] + set V_PF2_ENTRY_BAR_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_2 -tclproc VAL_PF2_ENTRY_BAR_2 -parent $T_PF2_2] + set V_PF2_ENTRY_ADDR_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_2 -tclproc VAL_PF2_ENTRY_ADDR_2 -parent $T_PF2_2] + set V_PF2_ENTRY_VERSION_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_2 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_2 -parent $T_PF2_2] + set V_PF2_ENTRY_MAJOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_2 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_2 -parent $T_PF2_2] + set V_PF2_ENTRY_MINOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_2 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_2 -parent $T_PF2_2] + set V_PF2_ENTRY_RSVD0_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_2 -tclproc VAL_PF2_ENTRY_RSVD0_2 -parent $T_PF2_2] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_2 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_2 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_2 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_2 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_2 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_2 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_2 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_2 + + set PF2_Values_3 [ipgui::add_group $IPINST -name "PF2 - Table Entry 3 Values" -parent $PF2_Values] + set T_PF2_3 [ipgui::add_table $IPINST -name T_PF2_3 -rows 7 -columns 2 -parent $PF2_Values_3] + set L_PF2_ENTRY_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_3 -text "C_PF2_ENTRY_TYPE_3 " -parent $T_PF2_3] + set L_PF2_ENTRY_BAR_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_3 -text "C_PF2_ENTRY_BAR_3 " -parent $T_PF2_3] + set L_PF2_ENTRY_ADDR_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_3 -text "C_PF2_ENTRY_ADDR_3 " -parent $T_PF2_3] + set L_PF2_ENTRY_VERSION_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_3 -text "C_PF2_ENTRY_VERSION_TYPE_3 " -parent $T_PF2_3] + set L_PF2_ENTRY_MAJOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_3 -text "C_PF2_ENTRY_MAJOR_VERSION_3" -parent $T_PF2_3] + set L_PF2_ENTRY_MINOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_3 -text "C_PF2_ENTRY_MINOR_VERSION_3" -parent $T_PF2_3] + set L_PF2_ENTRY_RSVD0_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_3 -text "C_PF2_ENTRY_RSVD0_3 " -parent $T_PF2_3] + set V_PF2_ENTRY_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_3 -tclproc VAL_PF2_ENTRY_TYPE_3 -parent $T_PF2_3] + set V_PF2_ENTRY_BAR_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_3 -tclproc VAL_PF2_ENTRY_BAR_3 -parent $T_PF2_3] + set V_PF2_ENTRY_ADDR_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_3 -tclproc VAL_PF2_ENTRY_ADDR_3 -parent $T_PF2_3] + set V_PF2_ENTRY_VERSION_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_3 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_3 -parent $T_PF2_3] + set V_PF2_ENTRY_MAJOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_3 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_3 -parent $T_PF2_3] + set V_PF2_ENTRY_MINOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_3 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_3 -parent $T_PF2_3] + set V_PF2_ENTRY_RSVD0_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_3 -tclproc VAL_PF2_ENTRY_RSVD0_3 -parent $T_PF2_3] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_3 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_3 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_3 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_3 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_3 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_3 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_3 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_3 + + set PF2_Values_4 [ipgui::add_group $IPINST -name "PF2 - Table Entry 4 Values" -parent $PF2_Values] + set T_PF2_4 [ipgui::add_table $IPINST -name T_PF2_4 -rows 7 -columns 2 -parent $PF2_Values_4] + set L_PF2_ENTRY_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_4 -text "C_PF2_ENTRY_TYPE_4 " -parent $T_PF2_4] + set L_PF2_ENTRY_BAR_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_4 -text "C_PF2_ENTRY_BAR_4 " -parent $T_PF2_4] + set L_PF2_ENTRY_ADDR_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_4 -text "C_PF2_ENTRY_ADDR_4 " -parent $T_PF2_4] + set L_PF2_ENTRY_VERSION_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_4 -text "C_PF2_ENTRY_VERSION_TYPE_4 " -parent $T_PF2_4] + set L_PF2_ENTRY_MAJOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_4 -text "C_PF2_ENTRY_MAJOR_VERSION_4" -parent $T_PF2_4] + set L_PF2_ENTRY_MINOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_4 -text "C_PF2_ENTRY_MINOR_VERSION_4" -parent $T_PF2_4] + set L_PF2_ENTRY_RSVD0_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_4 -text "C_PF2_ENTRY_RSVD0_4 " -parent $T_PF2_4] + set V_PF2_ENTRY_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_4 -tclproc VAL_PF2_ENTRY_TYPE_4 -parent $T_PF2_4] + set V_PF2_ENTRY_BAR_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_4 -tclproc VAL_PF2_ENTRY_BAR_4 -parent $T_PF2_4] + set V_PF2_ENTRY_ADDR_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_4 -tclproc VAL_PF2_ENTRY_ADDR_4 -parent $T_PF2_4] + set V_PF2_ENTRY_VERSION_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_4 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_4 -parent $T_PF2_4] + set V_PF2_ENTRY_MAJOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_4 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_4 -parent $T_PF2_4] + set V_PF2_ENTRY_MINOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_4 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_4 -parent $T_PF2_4] + set V_PF2_ENTRY_RSVD0_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_4 -tclproc VAL_PF2_ENTRY_RSVD0_4 -parent $T_PF2_4] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_4 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_4 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_4 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_4 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_4 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_4 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_4 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_4 + + set PF2_Values_5 [ipgui::add_group $IPINST -name "PF2 - Table Entry 5 Values" -parent $PF2_Values] + set T_PF2_5 [ipgui::add_table $IPINST -name T_PF2_5 -rows 7 -columns 2 -parent $PF2_Values_5] + set L_PF2_ENTRY_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_5 -text "C_PF2_ENTRY_TYPE_5 " -parent $T_PF2_5] + set L_PF2_ENTRY_BAR_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_5 -text "C_PF2_ENTRY_BAR_5 " -parent $T_PF2_5] + set L_PF2_ENTRY_ADDR_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_5 -text "C_PF2_ENTRY_ADDR_5 " -parent $T_PF2_5] + set L_PF2_ENTRY_VERSION_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_5 -text "C_PF2_ENTRY_VERSION_TYPE_5 " -parent $T_PF2_5] + set L_PF2_ENTRY_MAJOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_5 -text "C_PF2_ENTRY_MAJOR_VERSION_5" -parent $T_PF2_5] + set L_PF2_ENTRY_MINOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_5 -text "C_PF2_ENTRY_MINOR_VERSION_5" -parent $T_PF2_5] + set L_PF2_ENTRY_RSVD0_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_5 -text "C_PF2_ENTRY_RSVD0_5 " -parent $T_PF2_5] + set V_PF2_ENTRY_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_5 -tclproc VAL_PF2_ENTRY_TYPE_5 -parent $T_PF2_5] + set V_PF2_ENTRY_BAR_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_5 -tclproc VAL_PF2_ENTRY_BAR_5 -parent $T_PF2_5] + set V_PF2_ENTRY_ADDR_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_5 -tclproc VAL_PF2_ENTRY_ADDR_5 -parent $T_PF2_5] + set V_PF2_ENTRY_VERSION_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_5 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_5 -parent $T_PF2_5] + set V_PF2_ENTRY_MAJOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_5 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_5 -parent $T_PF2_5] + set V_PF2_ENTRY_MINOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_5 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_5 -parent $T_PF2_5] + set V_PF2_ENTRY_RSVD0_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_5 -tclproc VAL_PF2_ENTRY_RSVD0_5 -parent $T_PF2_5] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_5 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_5 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_5 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_5 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_5 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_5 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_5 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_5 + + set PF2_Values_6 [ipgui::add_group $IPINST -name "PF2 - Table Entry 6 Values" -parent $PF2_Values] + set T_PF2_6 [ipgui::add_table $IPINST -name T_PF2_6 -rows 7 -columns 2 -parent $PF2_Values_6] + set L_PF2_ENTRY_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_6 -text "C_PF2_ENTRY_TYPE_6 " -parent $T_PF2_6] + set L_PF2_ENTRY_BAR_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_6 -text "C_PF2_ENTRY_BAR_6 " -parent $T_PF2_6] + set L_PF2_ENTRY_ADDR_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_6 -text "C_PF2_ENTRY_ADDR_6 " -parent $T_PF2_6] + set L_PF2_ENTRY_VERSION_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_6 -text "C_PF2_ENTRY_VERSION_TYPE_6 " -parent $T_PF2_6] + set L_PF2_ENTRY_MAJOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_6 -text "C_PF2_ENTRY_MAJOR_VERSION_6" -parent $T_PF2_6] + set L_PF2_ENTRY_MINOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_6 -text "C_PF2_ENTRY_MINOR_VERSION_6" -parent $T_PF2_6] + set L_PF2_ENTRY_RSVD0_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_6 -text "C_PF2_ENTRY_RSVD0_6 " -parent $T_PF2_6] + set V_PF2_ENTRY_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_6 -tclproc VAL_PF2_ENTRY_TYPE_6 -parent $T_PF2_6] + set V_PF2_ENTRY_BAR_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_6 -tclproc VAL_PF2_ENTRY_BAR_6 -parent $T_PF2_6] + set V_PF2_ENTRY_ADDR_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_6 -tclproc VAL_PF2_ENTRY_ADDR_6 -parent $T_PF2_6] + set V_PF2_ENTRY_VERSION_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_6 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_6 -parent $T_PF2_6] + set V_PF2_ENTRY_MAJOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_6 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_6 -parent $T_PF2_6] + set V_PF2_ENTRY_MINOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_6 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_6 -parent $T_PF2_6] + set V_PF2_ENTRY_RSVD0_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_6 -tclproc VAL_PF2_ENTRY_RSVD0_6 -parent $T_PF2_6] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_6 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_6 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_6 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_6 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_6 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_6 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_6 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_6 + + set PF2_Values_7 [ipgui::add_group $IPINST -name "PF2 - Table Entry 7 Values" -parent $PF2_Values] + set T_PF2_7 [ipgui::add_table $IPINST -name T_PF2_7 -rows 7 -columns 2 -parent $PF2_Values_7] + set L_PF2_ENTRY_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_7 -text "C_PF2_ENTRY_TYPE_7 " -parent $T_PF2_7] + set L_PF2_ENTRY_BAR_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_7 -text "C_PF2_ENTRY_BAR_7 " -parent $T_PF2_7] + set L_PF2_ENTRY_ADDR_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_7 -text "C_PF2_ENTRY_ADDR_7 " -parent $T_PF2_7] + set L_PF2_ENTRY_VERSION_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_7 -text "C_PF2_ENTRY_VERSION_TYPE_7 " -parent $T_PF2_7] + set L_PF2_ENTRY_MAJOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_7 -text "C_PF2_ENTRY_MAJOR_VERSION_7" -parent $T_PF2_7] + set L_PF2_ENTRY_MINOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_7 -text "C_PF2_ENTRY_MINOR_VERSION_7" -parent $T_PF2_7] + set L_PF2_ENTRY_RSVD0_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_7 -text "C_PF2_ENTRY_RSVD0_7 " -parent $T_PF2_7] + set V_PF2_ENTRY_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_7 -tclproc VAL_PF2_ENTRY_TYPE_7 -parent $T_PF2_7] + set V_PF2_ENTRY_BAR_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_7 -tclproc VAL_PF2_ENTRY_BAR_7 -parent $T_PF2_7] + set V_PF2_ENTRY_ADDR_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_7 -tclproc VAL_PF2_ENTRY_ADDR_7 -parent $T_PF2_7] + set V_PF2_ENTRY_VERSION_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_7 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_7 -parent $T_PF2_7] + set V_PF2_ENTRY_MAJOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_7 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_7 -parent $T_PF2_7] + set V_PF2_ENTRY_MINOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_7 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_7 -parent $T_PF2_7] + set V_PF2_ENTRY_RSVD0_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_7 -tclproc VAL_PF2_ENTRY_RSVD0_7 -parent $T_PF2_7] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_7 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_7 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_7 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_7 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_7 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_7 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_7 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_7 + + set PF2_Values_8 [ipgui::add_group $IPINST -name "PF2 - Table Entry 8 Values" -parent $PF2_Values] + set T_PF2_8 [ipgui::add_table $IPINST -name T_PF2_8 -rows 7 -columns 2 -parent $PF2_Values_8] + set L_PF2_ENTRY_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_8 -text "C_PF2_ENTRY_TYPE_8 " -parent $T_PF2_8] + set L_PF2_ENTRY_BAR_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_8 -text "C_PF2_ENTRY_BAR_8 " -parent $T_PF2_8] + set L_PF2_ENTRY_ADDR_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_8 -text "C_PF2_ENTRY_ADDR_8 " -parent $T_PF2_8] + set L_PF2_ENTRY_VERSION_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_8 -text "C_PF2_ENTRY_VERSION_TYPE_8 " -parent $T_PF2_8] + set L_PF2_ENTRY_MAJOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_8 -text "C_PF2_ENTRY_MAJOR_VERSION_8" -parent $T_PF2_8] + set L_PF2_ENTRY_MINOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_8 -text "C_PF2_ENTRY_MINOR_VERSION_8" -parent $T_PF2_8] + set L_PF2_ENTRY_RSVD0_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_8 -text "C_PF2_ENTRY_RSVD0_8 " -parent $T_PF2_8] + set V_PF2_ENTRY_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_8 -tclproc VAL_PF2_ENTRY_TYPE_8 -parent $T_PF2_8] + set V_PF2_ENTRY_BAR_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_8 -tclproc VAL_PF2_ENTRY_BAR_8 -parent $T_PF2_8] + set V_PF2_ENTRY_ADDR_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_8 -tclproc VAL_PF2_ENTRY_ADDR_8 -parent $T_PF2_8] + set V_PF2_ENTRY_VERSION_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_8 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_8 -parent $T_PF2_8] + set V_PF2_ENTRY_MAJOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_8 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_8 -parent $T_PF2_8] + set V_PF2_ENTRY_MINOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_8 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_8 -parent $T_PF2_8] + set V_PF2_ENTRY_RSVD0_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_8 -tclproc VAL_PF2_ENTRY_RSVD0_8 -parent $T_PF2_8] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_8 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_8 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_8 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_8 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_8 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_8 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_8 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_8 + + set PF2_Values_9 [ipgui::add_group $IPINST -name "PF2 - Table Entry 9 Values" -parent $PF2_Values] + set T_PF2_9 [ipgui::add_table $IPINST -name T_PF2_9 -rows 7 -columns 2 -parent $PF2_Values_9] + set L_PF2_ENTRY_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_9 -text "C_PF2_ENTRY_TYPE_9 " -parent $T_PF2_9] + set L_PF2_ENTRY_BAR_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_9 -text "C_PF2_ENTRY_BAR_9 " -parent $T_PF2_9] + set L_PF2_ENTRY_ADDR_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_9 -text "C_PF2_ENTRY_ADDR_9 " -parent $T_PF2_9] + set L_PF2_ENTRY_VERSION_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_9 -text "C_PF2_ENTRY_VERSION_TYPE_9 " -parent $T_PF2_9] + set L_PF2_ENTRY_MAJOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_9 -text "C_PF2_ENTRY_MAJOR_VERSION_9" -parent $T_PF2_9] + set L_PF2_ENTRY_MINOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_9 -text "C_PF2_ENTRY_MINOR_VERSION_9" -parent $T_PF2_9] + set L_PF2_ENTRY_RSVD0_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_9 -text "C_PF2_ENTRY_RSVD0_9 " -parent $T_PF2_9] + set V_PF2_ENTRY_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_9 -tclproc VAL_PF2_ENTRY_TYPE_9 -parent $T_PF2_9] + set V_PF2_ENTRY_BAR_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_9 -tclproc VAL_PF2_ENTRY_BAR_9 -parent $T_PF2_9] + set V_PF2_ENTRY_ADDR_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_9 -tclproc VAL_PF2_ENTRY_ADDR_9 -parent $T_PF2_9] + set V_PF2_ENTRY_VERSION_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_9 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_9 -parent $T_PF2_9] + set V_PF2_ENTRY_MAJOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_9 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_9 -parent $T_PF2_9] + set V_PF2_ENTRY_MINOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_9 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_9 -parent $T_PF2_9] + set V_PF2_ENTRY_RSVD0_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_9 -tclproc VAL_PF2_ENTRY_RSVD0_9 -parent $T_PF2_9] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_9 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_9 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_9 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_9 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_9 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_9 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_9 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_9 + + set PF2_Values_10 [ipgui::add_group $IPINST -name "PF2 - Table Entry 10 Values" -parent $PF2_Values] + set T_PF2_10 [ipgui::add_table $IPINST -name T_PF2_10 -rows 7 -columns 2 -parent $PF2_Values_10] + set L_PF2_ENTRY_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_10 -text "C_PF2_ENTRY_TYPE_10 " -parent $T_PF2_10] + set L_PF2_ENTRY_BAR_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_10 -text "C_PF2_ENTRY_BAR_10 " -parent $T_PF2_10] + set L_PF2_ENTRY_ADDR_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_10 -text "C_PF2_ENTRY_ADDR_10 " -parent $T_PF2_10] + set L_PF2_ENTRY_VERSION_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_10 -text "C_PF2_ENTRY_VERSION_TYPE_10 " -parent $T_PF2_10] + set L_PF2_ENTRY_MAJOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_10 -text "C_PF2_ENTRY_MAJOR_VERSION_10" -parent $T_PF2_10] + set L_PF2_ENTRY_MINOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_10 -text "C_PF2_ENTRY_MINOR_VERSION_10" -parent $T_PF2_10] + set L_PF2_ENTRY_RSVD0_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_10 -text "C_PF2_ENTRY_RSVD0_10 " -parent $T_PF2_10] + set V_PF2_ENTRY_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_10 -tclproc VAL_PF2_ENTRY_TYPE_10 -parent $T_PF2_10] + set V_PF2_ENTRY_BAR_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_10 -tclproc VAL_PF2_ENTRY_BAR_10 -parent $T_PF2_10] + set V_PF2_ENTRY_ADDR_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_10 -tclproc VAL_PF2_ENTRY_ADDR_10 -parent $T_PF2_10] + set V_PF2_ENTRY_VERSION_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_10 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_10 -parent $T_PF2_10] + set V_PF2_ENTRY_MAJOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_10 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_10 -parent $T_PF2_10] + set V_PF2_ENTRY_MINOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_10 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_10 -parent $T_PF2_10] + set V_PF2_ENTRY_RSVD0_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_10 -tclproc VAL_PF2_ENTRY_RSVD0_10 -parent $T_PF2_10] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_10 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_10 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_10 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_10 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_10 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_10 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_10 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_10 + + set PF2_Values_11 [ipgui::add_group $IPINST -name "PF2 - Table Entry 11 Values" -parent $PF2_Values] + set T_PF2_11 [ipgui::add_table $IPINST -name T_PF2_11 -rows 7 -columns 2 -parent $PF2_Values_11] + set L_PF2_ENTRY_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_11 -text "C_PF2_ENTRY_TYPE_11 " -parent $T_PF2_11] + set L_PF2_ENTRY_BAR_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_11 -text "C_PF2_ENTRY_BAR_11 " -parent $T_PF2_11] + set L_PF2_ENTRY_ADDR_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_11 -text "C_PF2_ENTRY_ADDR_11 " -parent $T_PF2_11] + set L_PF2_ENTRY_VERSION_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_11 -text "C_PF2_ENTRY_VERSION_TYPE_11 " -parent $T_PF2_11] + set L_PF2_ENTRY_MAJOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_11 -text "C_PF2_ENTRY_MAJOR_VERSION_11" -parent $T_PF2_11] + set L_PF2_ENTRY_MINOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_11 -text "C_PF2_ENTRY_MINOR_VERSION_11" -parent $T_PF2_11] + set L_PF2_ENTRY_RSVD0_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_11 -text "C_PF2_ENTRY_RSVD0_11 " -parent $T_PF2_11] + set V_PF2_ENTRY_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_11 -tclproc VAL_PF2_ENTRY_TYPE_11 -parent $T_PF2_11] + set V_PF2_ENTRY_BAR_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_11 -tclproc VAL_PF2_ENTRY_BAR_11 -parent $T_PF2_11] + set V_PF2_ENTRY_ADDR_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_11 -tclproc VAL_PF2_ENTRY_ADDR_11 -parent $T_PF2_11] + set V_PF2_ENTRY_VERSION_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_11 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_11 -parent $T_PF2_11] + set V_PF2_ENTRY_MAJOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_11 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_11 -parent $T_PF2_11] + set V_PF2_ENTRY_MINOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_11 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_11 -parent $T_PF2_11] + set V_PF2_ENTRY_RSVD0_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_11 -tclproc VAL_PF2_ENTRY_RSVD0_11 -parent $T_PF2_11] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_11 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_11 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_11 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_11 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_11 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_11 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_11 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_11 + + set PF2_Values_12 [ipgui::add_group $IPINST -name "PF2 - Table Entry 12 Values" -parent $PF2_Values] + set T_PF2_12 [ipgui::add_table $IPINST -name T_PF2_12 -rows 7 -columns 2 -parent $PF2_Values_12] + set L_PF2_ENTRY_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_12 -text "C_PF2_ENTRY_TYPE_12 " -parent $T_PF2_12] + set L_PF2_ENTRY_BAR_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_12 -text "C_PF2_ENTRY_BAR_12 " -parent $T_PF2_12] + set L_PF2_ENTRY_ADDR_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_12 -text "C_PF2_ENTRY_ADDR_12 " -parent $T_PF2_12] + set L_PF2_ENTRY_VERSION_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_12 -text "C_PF2_ENTRY_VERSION_TYPE_12 " -parent $T_PF2_12] + set L_PF2_ENTRY_MAJOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_12 -text "C_PF2_ENTRY_MAJOR_VERSION_12" -parent $T_PF2_12] + set L_PF2_ENTRY_MINOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_12 -text "C_PF2_ENTRY_MINOR_VERSION_12" -parent $T_PF2_12] + set L_PF2_ENTRY_RSVD0_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_12 -text "C_PF2_ENTRY_RSVD0_12 " -parent $T_PF2_12] + set V_PF2_ENTRY_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_12 -tclproc VAL_PF2_ENTRY_TYPE_12 -parent $T_PF2_12] + set V_PF2_ENTRY_BAR_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_12 -tclproc VAL_PF2_ENTRY_BAR_12 -parent $T_PF2_12] + set V_PF2_ENTRY_ADDR_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_12 -tclproc VAL_PF2_ENTRY_ADDR_12 -parent $T_PF2_12] + set V_PF2_ENTRY_VERSION_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_12 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_12 -parent $T_PF2_12] + set V_PF2_ENTRY_MAJOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_12 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_12 -parent $T_PF2_12] + set V_PF2_ENTRY_MINOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_12 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_12 -parent $T_PF2_12] + set V_PF2_ENTRY_RSVD0_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_12 -tclproc VAL_PF2_ENTRY_RSVD0_12 -parent $T_PF2_12] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_12 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_12 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_12 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_12 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_12 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_12 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_12 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_12 + + set PF2_Values_13 [ipgui::add_group $IPINST -name "PF2 - Table Entry 13 Values" -parent $PF2_Values] + set T_PF2_13 [ipgui::add_table $IPINST -name T_PF2_13 -rows 7 -columns 2 -parent $PF2_Values_13] + set L_PF2_ENTRY_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_13 -text "C_PF2_ENTRY_TYPE_13 " -parent $T_PF2_13] + set L_PF2_ENTRY_BAR_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_13 -text "C_PF2_ENTRY_BAR_13 " -parent $T_PF2_13] + set L_PF2_ENTRY_ADDR_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_13 -text "C_PF2_ENTRY_ADDR_13 " -parent $T_PF2_13] + set L_PF2_ENTRY_VERSION_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_13 -text "C_PF2_ENTRY_VERSION_TYPE_13 " -parent $T_PF2_13] + set L_PF2_ENTRY_MAJOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_13 -text "C_PF2_ENTRY_MAJOR_VERSION_13" -parent $T_PF2_13] + set L_PF2_ENTRY_MINOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_13 -text "C_PF2_ENTRY_MINOR_VERSION_13" -parent $T_PF2_13] + set L_PF2_ENTRY_RSVD0_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_13 -text "C_PF2_ENTRY_RSVD0_13 " -parent $T_PF2_13] + set V_PF2_ENTRY_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_13 -tclproc VAL_PF2_ENTRY_TYPE_13 -parent $T_PF2_13] + set V_PF2_ENTRY_BAR_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_13 -tclproc VAL_PF2_ENTRY_BAR_13 -parent $T_PF2_13] + set V_PF2_ENTRY_ADDR_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_13 -tclproc VAL_PF2_ENTRY_ADDR_13 -parent $T_PF2_13] + set V_PF2_ENTRY_VERSION_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_13 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_13 -parent $T_PF2_13] + set V_PF2_ENTRY_MAJOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_13 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_13 -parent $T_PF2_13] + set V_PF2_ENTRY_MINOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_13 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_13 -parent $T_PF2_13] + set V_PF2_ENTRY_RSVD0_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_13 -tclproc VAL_PF2_ENTRY_RSVD0_13 -parent $T_PF2_13] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_13 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_13 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_13 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_13 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_13 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_13 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_13 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_13 + + set PF3_Values [ipgui::add_page $IPINST -name "PF3 Values"] + set PF3_Values_General [ipgui::add_group $IPINST -name "PF3 - General Values" -parent $PF3_Values] + set T_PF3_GENERAL [ipgui::add_table $IPINST -name T_PF3_GENERAL -rows 4 -columns 2 -parent $PF3_Values_General] + set L_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_static_text $IPINST -name L_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE -text "C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE" -parent $T_PF3_GENERAL] + set L_PF3_BAR_INDEX [ipgui::add_static_text $IPINST -name L_PF3_BAR_INDEX -text "C_PF3_BAR_INDEX " -parent $T_PF3_GENERAL] + set L_PF3_LOW_OFFSET [ipgui::add_static_text $IPINST -name L_PF3_LOW_OFFSET -text "C_PF3_LOW_OFFSET " -parent $T_PF3_GENERAL] + set L_PF3_HIGH_OFFSET [ipgui::add_static_text $IPINST -name L_PF3_HIGH_OFFSET -text "C_PF3_HIGH_OFFSET " -parent $T_PF3_GENERAL] + set V_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_dynamic_text $IPINST -name V_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE -tclproc VAL_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $T_PF3_GENERAL] + set V_PF3_BAR_INDEX [ipgui::add_dynamic_text $IPINST -name V_PF3_BAR_INDEX -tclproc VAL_PF3_BAR_INDEX -parent $T_PF3_GENERAL] + set V_PF3_LOW_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF3_LOW_OFFSET -tclproc VAL_PF3_LOW_OFFSET -parent $T_PF3_GENERAL] + set V_PF3_HIGH_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF3_HIGH_OFFSET -tclproc VAL_PF3_HIGH_OFFSET -parent $T_PF3_GENERAL] + set_property cell_location 0,0 $L_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,0 $L_PF3_BAR_INDEX + set_property cell_location 2,0 $L_PF3_LOW_OFFSET + set_property cell_location 3,0 $L_PF3_HIGH_OFFSET + set_property cell_location 0,1 $V_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,1 $V_PF3_BAR_INDEX + set_property cell_location 2,1 $V_PF3_LOW_OFFSET + set_property cell_location 3,1 $V_PF3_HIGH_OFFSET + set_property obj_color "192,192,192" $V_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property obj_color "192,192,192" $V_PF3_BAR_INDEX + set_property obj_color "192,192,192" $V_PF3_LOW_OFFSET + set_property obj_color "192,192,192" $V_PF3_HIGH_OFFSET + + set PF3_Values_0 [ipgui::add_group $IPINST -name "PF3 - Table Entry 0 Values" -parent $PF3_Values] + set T_PF3_0 [ipgui::add_table $IPINST -name T_PF3_0 -rows 7 -columns 2 -parent $PF3_Values_0] + set L_PF3_ENTRY_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_0 -text "C_PF3_ENTRY_TYPE_0 " -parent $T_PF3_0] + set L_PF3_ENTRY_BAR_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_0 -text "C_PF3_ENTRY_BAR_0 " -parent $T_PF3_0] + set L_PF3_ENTRY_ADDR_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_0 -text "C_PF3_ENTRY_ADDR_0 " -parent $T_PF3_0] + set L_PF3_ENTRY_VERSION_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_0 -text "C_PF3_ENTRY_VERSION_TYPE_0 " -parent $T_PF3_0] + set L_PF3_ENTRY_MAJOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_0 -text "C_PF3_ENTRY_MAJOR_VERSION_0" -parent $T_PF3_0] + set L_PF3_ENTRY_MINOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_0 -text "C_PF3_ENTRY_MINOR_VERSION_0" -parent $T_PF3_0] + set L_PF3_ENTRY_RSVD0_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_0 -text "C_PF3_ENTRY_RSVD0_0 " -parent $T_PF3_0] + set V_PF3_ENTRY_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_0 -tclproc VAL_PF3_ENTRY_TYPE_0 -parent $T_PF3_0] + set V_PF3_ENTRY_BAR_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_0 -tclproc VAL_PF3_ENTRY_BAR_0 -parent $T_PF3_0] + set V_PF3_ENTRY_ADDR_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_0 -tclproc VAL_PF3_ENTRY_ADDR_0 -parent $T_PF3_0] + set V_PF3_ENTRY_VERSION_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_0 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_0 -parent $T_PF3_0] + set V_PF3_ENTRY_MAJOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_0 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_0 -parent $T_PF3_0] + set V_PF3_ENTRY_MINOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_0 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_0 -parent $T_PF3_0] + set V_PF3_ENTRY_RSVD0_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_0 -tclproc VAL_PF3_ENTRY_RSVD0_0 -parent $T_PF3_0] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_0 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_0 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_0 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_0 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_0 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_0 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_0 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_0 + + set PF3_Values_1 [ipgui::add_group $IPINST -name "PF3 - Table Entry 1 Values" -parent $PF3_Values] + set T_PF3_1 [ipgui::add_table $IPINST -name T_PF3_1 -rows 7 -columns 2 -parent $PF3_Values_1] + set L_PF3_ENTRY_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_1 -text "C_PF3_ENTRY_TYPE_1 " -parent $T_PF3_1] + set L_PF3_ENTRY_BAR_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_1 -text "C_PF3_ENTRY_BAR_1 " -parent $T_PF3_1] + set L_PF3_ENTRY_ADDR_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_1 -text "C_PF3_ENTRY_ADDR_1 " -parent $T_PF3_1] + set L_PF3_ENTRY_VERSION_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_1 -text "C_PF3_ENTRY_VERSION_TYPE_1 " -parent $T_PF3_1] + set L_PF3_ENTRY_MAJOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_1 -text "C_PF3_ENTRY_MAJOR_VERSION_1" -parent $T_PF3_1] + set L_PF3_ENTRY_MINOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_1 -text "C_PF3_ENTRY_MINOR_VERSION_1" -parent $T_PF3_1] + set L_PF3_ENTRY_RSVD0_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_1 -text "C_PF3_ENTRY_RSVD0_1 " -parent $T_PF3_1] + set V_PF3_ENTRY_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_1 -tclproc VAL_PF3_ENTRY_TYPE_1 -parent $T_PF3_1] + set V_PF3_ENTRY_BAR_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_1 -tclproc VAL_PF3_ENTRY_BAR_1 -parent $T_PF3_1] + set V_PF3_ENTRY_ADDR_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_1 -tclproc VAL_PF3_ENTRY_ADDR_1 -parent $T_PF3_1] + set V_PF3_ENTRY_VERSION_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_1 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_1 -parent $T_PF3_1] + set V_PF3_ENTRY_MAJOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_1 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_1 -parent $T_PF3_1] + set V_PF3_ENTRY_MINOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_1 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_1 -parent $T_PF3_1] + set V_PF3_ENTRY_RSVD0_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_1 -tclproc VAL_PF3_ENTRY_RSVD0_1 -parent $T_PF3_1] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_1 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_1 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_1 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_1 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_1 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_1 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_1 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_1 + + set PF3_Values_2 [ipgui::add_group $IPINST -name "PF3 - Table Entry 2 Values" -parent $PF3_Values] + set T_PF3_2 [ipgui::add_table $IPINST -name T_PF3_2 -rows 7 -columns 2 -parent $PF3_Values_2] + set L_PF3_ENTRY_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_2 -text "C_PF3_ENTRY_TYPE_2 " -parent $T_PF3_2] + set L_PF3_ENTRY_BAR_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_2 -text "C_PF3_ENTRY_BAR_2 " -parent $T_PF3_2] + set L_PF3_ENTRY_ADDR_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_2 -text "C_PF3_ENTRY_ADDR_2 " -parent $T_PF3_2] + set L_PF3_ENTRY_VERSION_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_2 -text "C_PF3_ENTRY_VERSION_TYPE_2 " -parent $T_PF3_2] + set L_PF3_ENTRY_MAJOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_2 -text "C_PF3_ENTRY_MAJOR_VERSION_2" -parent $T_PF3_2] + set L_PF3_ENTRY_MINOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_2 -text "C_PF3_ENTRY_MINOR_VERSION_2" -parent $T_PF3_2] + set L_PF3_ENTRY_RSVD0_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_2 -text "C_PF3_ENTRY_RSVD0_2 " -parent $T_PF3_2] + set V_PF3_ENTRY_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_2 -tclproc VAL_PF3_ENTRY_TYPE_2 -parent $T_PF3_2] + set V_PF3_ENTRY_BAR_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_2 -tclproc VAL_PF3_ENTRY_BAR_2 -parent $T_PF3_2] + set V_PF3_ENTRY_ADDR_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_2 -tclproc VAL_PF3_ENTRY_ADDR_2 -parent $T_PF3_2] + set V_PF3_ENTRY_VERSION_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_2 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_2 -parent $T_PF3_2] + set V_PF3_ENTRY_MAJOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_2 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_2 -parent $T_PF3_2] + set V_PF3_ENTRY_MINOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_2 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_2 -parent $T_PF3_2] + set V_PF3_ENTRY_RSVD0_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_2 -tclproc VAL_PF3_ENTRY_RSVD0_2 -parent $T_PF3_2] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_2 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_2 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_2 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_2 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_2 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_2 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_2 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_2 + + set PF3_Values_3 [ipgui::add_group $IPINST -name "PF3 - Table Entry 3 Values" -parent $PF3_Values] + set T_PF3_3 [ipgui::add_table $IPINST -name T_PF3_3 -rows 7 -columns 2 -parent $PF3_Values_3] + set L_PF3_ENTRY_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_3 -text "C_PF3_ENTRY_TYPE_3 " -parent $T_PF3_3] + set L_PF3_ENTRY_BAR_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_3 -text "C_PF3_ENTRY_BAR_3 " -parent $T_PF3_3] + set L_PF3_ENTRY_ADDR_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_3 -text "C_PF3_ENTRY_ADDR_3 " -parent $T_PF3_3] + set L_PF3_ENTRY_VERSION_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_3 -text "C_PF3_ENTRY_VERSION_TYPE_3 " -parent $T_PF3_3] + set L_PF3_ENTRY_MAJOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_3 -text "C_PF3_ENTRY_MAJOR_VERSION_3" -parent $T_PF3_3] + set L_PF3_ENTRY_MINOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_3 -text "C_PF3_ENTRY_MINOR_VERSION_3" -parent $T_PF3_3] + set L_PF3_ENTRY_RSVD0_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_3 -text "C_PF3_ENTRY_RSVD0_3 " -parent $T_PF3_3] + set V_PF3_ENTRY_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_3 -tclproc VAL_PF3_ENTRY_TYPE_3 -parent $T_PF3_3] + set V_PF3_ENTRY_BAR_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_3 -tclproc VAL_PF3_ENTRY_BAR_3 -parent $T_PF3_3] + set V_PF3_ENTRY_ADDR_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_3 -tclproc VAL_PF3_ENTRY_ADDR_3 -parent $T_PF3_3] + set V_PF3_ENTRY_VERSION_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_3 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_3 -parent $T_PF3_3] + set V_PF3_ENTRY_MAJOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_3 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_3 -parent $T_PF3_3] + set V_PF3_ENTRY_MINOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_3 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_3 -parent $T_PF3_3] + set V_PF3_ENTRY_RSVD0_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_3 -tclproc VAL_PF3_ENTRY_RSVD0_3 -parent $T_PF3_3] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_3 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_3 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_3 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_3 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_3 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_3 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_3 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_3 + + set PF3_Values_4 [ipgui::add_group $IPINST -name "PF3 - Table Entry 4 Values" -parent $PF3_Values] + set T_PF3_4 [ipgui::add_table $IPINST -name T_PF3_4 -rows 7 -columns 2 -parent $PF3_Values_4] + set L_PF3_ENTRY_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_4 -text "C_PF3_ENTRY_TYPE_4 " -parent $T_PF3_4] + set L_PF3_ENTRY_BAR_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_4 -text "C_PF3_ENTRY_BAR_4 " -parent $T_PF3_4] + set L_PF3_ENTRY_ADDR_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_4 -text "C_PF3_ENTRY_ADDR_4 " -parent $T_PF3_4] + set L_PF3_ENTRY_VERSION_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_4 -text "C_PF3_ENTRY_VERSION_TYPE_4 " -parent $T_PF3_4] + set L_PF3_ENTRY_MAJOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_4 -text "C_PF3_ENTRY_MAJOR_VERSION_4" -parent $T_PF3_4] + set L_PF3_ENTRY_MINOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_4 -text "C_PF3_ENTRY_MINOR_VERSION_4" -parent $T_PF3_4] + set L_PF3_ENTRY_RSVD0_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_4 -text "C_PF3_ENTRY_RSVD0_4 " -parent $T_PF3_4] + set V_PF3_ENTRY_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_4 -tclproc VAL_PF3_ENTRY_TYPE_4 -parent $T_PF3_4] + set V_PF3_ENTRY_BAR_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_4 -tclproc VAL_PF3_ENTRY_BAR_4 -parent $T_PF3_4] + set V_PF3_ENTRY_ADDR_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_4 -tclproc VAL_PF3_ENTRY_ADDR_4 -parent $T_PF3_4] + set V_PF3_ENTRY_VERSION_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_4 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_4 -parent $T_PF3_4] + set V_PF3_ENTRY_MAJOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_4 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_4 -parent $T_PF3_4] + set V_PF3_ENTRY_MINOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_4 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_4 -parent $T_PF3_4] + set V_PF3_ENTRY_RSVD0_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_4 -tclproc VAL_PF3_ENTRY_RSVD0_4 -parent $T_PF3_4] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_4 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_4 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_4 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_4 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_4 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_4 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_4 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_4 + + set PF3_Values_5 [ipgui::add_group $IPINST -name "PF3 - Table Entry 5 Values" -parent $PF3_Values] + set T_PF3_5 [ipgui::add_table $IPINST -name T_PF3_5 -rows 7 -columns 2 -parent $PF3_Values_5] + set L_PF3_ENTRY_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_5 -text "C_PF3_ENTRY_TYPE_5 " -parent $T_PF3_5] + set L_PF3_ENTRY_BAR_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_5 -text "C_PF3_ENTRY_BAR_5 " -parent $T_PF3_5] + set L_PF3_ENTRY_ADDR_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_5 -text "C_PF3_ENTRY_ADDR_5 " -parent $T_PF3_5] + set L_PF3_ENTRY_VERSION_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_5 -text "C_PF3_ENTRY_VERSION_TYPE_5 " -parent $T_PF3_5] + set L_PF3_ENTRY_MAJOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_5 -text "C_PF3_ENTRY_MAJOR_VERSION_5" -parent $T_PF3_5] + set L_PF3_ENTRY_MINOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_5 -text "C_PF3_ENTRY_MINOR_VERSION_5" -parent $T_PF3_5] + set L_PF3_ENTRY_RSVD0_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_5 -text "C_PF3_ENTRY_RSVD0_5 " -parent $T_PF3_5] + set V_PF3_ENTRY_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_5 -tclproc VAL_PF3_ENTRY_TYPE_5 -parent $T_PF3_5] + set V_PF3_ENTRY_BAR_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_5 -tclproc VAL_PF3_ENTRY_BAR_5 -parent $T_PF3_5] + set V_PF3_ENTRY_ADDR_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_5 -tclproc VAL_PF3_ENTRY_ADDR_5 -parent $T_PF3_5] + set V_PF3_ENTRY_VERSION_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_5 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_5 -parent $T_PF3_5] + set V_PF3_ENTRY_MAJOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_5 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_5 -parent $T_PF3_5] + set V_PF3_ENTRY_MINOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_5 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_5 -parent $T_PF3_5] + set V_PF3_ENTRY_RSVD0_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_5 -tclproc VAL_PF3_ENTRY_RSVD0_5 -parent $T_PF3_5] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_5 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_5 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_5 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_5 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_5 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_5 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_5 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_5 + + set PF3_Values_6 [ipgui::add_group $IPINST -name "PF3 - Table Entry 6 Values" -parent $PF3_Values] + set T_PF3_6 [ipgui::add_table $IPINST -name T_PF3_6 -rows 7 -columns 2 -parent $PF3_Values_6] + set L_PF3_ENTRY_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_6 -text "C_PF3_ENTRY_TYPE_6 " -parent $T_PF3_6] + set L_PF3_ENTRY_BAR_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_6 -text "C_PF3_ENTRY_BAR_6 " -parent $T_PF3_6] + set L_PF3_ENTRY_ADDR_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_6 -text "C_PF3_ENTRY_ADDR_6 " -parent $T_PF3_6] + set L_PF3_ENTRY_VERSION_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_6 -text "C_PF3_ENTRY_VERSION_TYPE_6 " -parent $T_PF3_6] + set L_PF3_ENTRY_MAJOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_6 -text "C_PF3_ENTRY_MAJOR_VERSION_6" -parent $T_PF3_6] + set L_PF3_ENTRY_MINOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_6 -text "C_PF3_ENTRY_MINOR_VERSION_6" -parent $T_PF3_6] + set L_PF3_ENTRY_RSVD0_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_6 -text "C_PF3_ENTRY_RSVD0_6 " -parent $T_PF3_6] + set V_PF3_ENTRY_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_6 -tclproc VAL_PF3_ENTRY_TYPE_6 -parent $T_PF3_6] + set V_PF3_ENTRY_BAR_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_6 -tclproc VAL_PF3_ENTRY_BAR_6 -parent $T_PF3_6] + set V_PF3_ENTRY_ADDR_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_6 -tclproc VAL_PF3_ENTRY_ADDR_6 -parent $T_PF3_6] + set V_PF3_ENTRY_VERSION_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_6 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_6 -parent $T_PF3_6] + set V_PF3_ENTRY_MAJOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_6 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_6 -parent $T_PF3_6] + set V_PF3_ENTRY_MINOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_6 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_6 -parent $T_PF3_6] + set V_PF3_ENTRY_RSVD0_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_6 -tclproc VAL_PF3_ENTRY_RSVD0_6 -parent $T_PF3_6] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_6 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_6 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_6 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_6 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_6 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_6 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_6 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_6 + + set PF3_Values_7 [ipgui::add_group $IPINST -name "PF3 - Table Entry 7 Values" -parent $PF3_Values] + set T_PF3_7 [ipgui::add_table $IPINST -name T_PF3_7 -rows 7 -columns 2 -parent $PF3_Values_7] + set L_PF3_ENTRY_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_7 -text "C_PF3_ENTRY_TYPE_7 " -parent $T_PF3_7] + set L_PF3_ENTRY_BAR_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_7 -text "C_PF3_ENTRY_BAR_7 " -parent $T_PF3_7] + set L_PF3_ENTRY_ADDR_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_7 -text "C_PF3_ENTRY_ADDR_7 " -parent $T_PF3_7] + set L_PF3_ENTRY_VERSION_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_7 -text "C_PF3_ENTRY_VERSION_TYPE_7 " -parent $T_PF3_7] + set L_PF3_ENTRY_MAJOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_7 -text "C_PF3_ENTRY_MAJOR_VERSION_7" -parent $T_PF3_7] + set L_PF3_ENTRY_MINOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_7 -text "C_PF3_ENTRY_MINOR_VERSION_7" -parent $T_PF3_7] + set L_PF3_ENTRY_RSVD0_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_7 -text "C_PF3_ENTRY_RSVD0_7 " -parent $T_PF3_7] + set V_PF3_ENTRY_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_7 -tclproc VAL_PF3_ENTRY_TYPE_7 -parent $T_PF3_7] + set V_PF3_ENTRY_BAR_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_7 -tclproc VAL_PF3_ENTRY_BAR_7 -parent $T_PF3_7] + set V_PF3_ENTRY_ADDR_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_7 -tclproc VAL_PF3_ENTRY_ADDR_7 -parent $T_PF3_7] + set V_PF3_ENTRY_VERSION_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_7 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_7 -parent $T_PF3_7] + set V_PF3_ENTRY_MAJOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_7 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_7 -parent $T_PF3_7] + set V_PF3_ENTRY_MINOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_7 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_7 -parent $T_PF3_7] + set V_PF3_ENTRY_RSVD0_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_7 -tclproc VAL_PF3_ENTRY_RSVD0_7 -parent $T_PF3_7] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_7 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_7 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_7 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_7 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_7 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_7 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_7 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_7 + + set PF3_Values_8 [ipgui::add_group $IPINST -name "PF3 - Table Entry 8 Values" -parent $PF3_Values] + set T_PF3_8 [ipgui::add_table $IPINST -name T_PF3_8 -rows 7 -columns 2 -parent $PF3_Values_8] + set L_PF3_ENTRY_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_8 -text "C_PF3_ENTRY_TYPE_8 " -parent $T_PF3_8] + set L_PF3_ENTRY_BAR_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_8 -text "C_PF3_ENTRY_BAR_8 " -parent $T_PF3_8] + set L_PF3_ENTRY_ADDR_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_8 -text "C_PF3_ENTRY_ADDR_8 " -parent $T_PF3_8] + set L_PF3_ENTRY_VERSION_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_8 -text "C_PF3_ENTRY_VERSION_TYPE_8 " -parent $T_PF3_8] + set L_PF3_ENTRY_MAJOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_8 -text "C_PF3_ENTRY_MAJOR_VERSION_8" -parent $T_PF3_8] + set L_PF3_ENTRY_MINOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_8 -text "C_PF3_ENTRY_MINOR_VERSION_8" -parent $T_PF3_8] + set L_PF3_ENTRY_RSVD0_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_8 -text "C_PF3_ENTRY_RSVD0_8 " -parent $T_PF3_8] + set V_PF3_ENTRY_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_8 -tclproc VAL_PF3_ENTRY_TYPE_8 -parent $T_PF3_8] + set V_PF3_ENTRY_BAR_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_8 -tclproc VAL_PF3_ENTRY_BAR_8 -parent $T_PF3_8] + set V_PF3_ENTRY_ADDR_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_8 -tclproc VAL_PF3_ENTRY_ADDR_8 -parent $T_PF3_8] + set V_PF3_ENTRY_VERSION_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_8 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_8 -parent $T_PF3_8] + set V_PF3_ENTRY_MAJOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_8 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_8 -parent $T_PF3_8] + set V_PF3_ENTRY_MINOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_8 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_8 -parent $T_PF3_8] + set V_PF3_ENTRY_RSVD0_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_8 -tclproc VAL_PF3_ENTRY_RSVD0_8 -parent $T_PF3_8] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_8 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_8 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_8 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_8 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_8 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_8 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_8 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_8 + + set PF3_Values_9 [ipgui::add_group $IPINST -name "PF3 - Table Entry 9 Values" -parent $PF3_Values] + set T_PF3_9 [ipgui::add_table $IPINST -name T_PF3_9 -rows 7 -columns 2 -parent $PF3_Values_9] + set L_PF3_ENTRY_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_9 -text "C_PF3_ENTRY_TYPE_9 " -parent $T_PF3_9] + set L_PF3_ENTRY_BAR_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_9 -text "C_PF3_ENTRY_BAR_9 " -parent $T_PF3_9] + set L_PF3_ENTRY_ADDR_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_9 -text "C_PF3_ENTRY_ADDR_9 " -parent $T_PF3_9] + set L_PF3_ENTRY_VERSION_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_9 -text "C_PF3_ENTRY_VERSION_TYPE_9 " -parent $T_PF3_9] + set L_PF3_ENTRY_MAJOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_9 -text "C_PF3_ENTRY_MAJOR_VERSION_9" -parent $T_PF3_9] + set L_PF3_ENTRY_MINOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_9 -text "C_PF3_ENTRY_MINOR_VERSION_9" -parent $T_PF3_9] + set L_PF3_ENTRY_RSVD0_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_9 -text "C_PF3_ENTRY_RSVD0_9 " -parent $T_PF3_9] + set V_PF3_ENTRY_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_9 -tclproc VAL_PF3_ENTRY_TYPE_9 -parent $T_PF3_9] + set V_PF3_ENTRY_BAR_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_9 -tclproc VAL_PF3_ENTRY_BAR_9 -parent $T_PF3_9] + set V_PF3_ENTRY_ADDR_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_9 -tclproc VAL_PF3_ENTRY_ADDR_9 -parent $T_PF3_9] + set V_PF3_ENTRY_VERSION_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_9 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_9 -parent $T_PF3_9] + set V_PF3_ENTRY_MAJOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_9 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_9 -parent $T_PF3_9] + set V_PF3_ENTRY_MINOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_9 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_9 -parent $T_PF3_9] + set V_PF3_ENTRY_RSVD0_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_9 -tclproc VAL_PF3_ENTRY_RSVD0_9 -parent $T_PF3_9] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_9 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_9 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_9 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_9 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_9 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_9 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_9 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_9 + + set PF3_Values_10 [ipgui::add_group $IPINST -name "PF3 - Table Entry 10 Values" -parent $PF3_Values] + set T_PF3_10 [ipgui::add_table $IPINST -name T_PF3_10 -rows 7 -columns 2 -parent $PF3_Values_10] + set L_PF3_ENTRY_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_10 -text "C_PF3_ENTRY_TYPE_10 " -parent $T_PF3_10] + set L_PF3_ENTRY_BAR_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_10 -text "C_PF3_ENTRY_BAR_10 " -parent $T_PF3_10] + set L_PF3_ENTRY_ADDR_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_10 -text "C_PF3_ENTRY_ADDR_10 " -parent $T_PF3_10] + set L_PF3_ENTRY_VERSION_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_10 -text "C_PF3_ENTRY_VERSION_TYPE_10 " -parent $T_PF3_10] + set L_PF3_ENTRY_MAJOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_10 -text "C_PF3_ENTRY_MAJOR_VERSION_10" -parent $T_PF3_10] + set L_PF3_ENTRY_MINOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_10 -text "C_PF3_ENTRY_MINOR_VERSION_10" -parent $T_PF3_10] + set L_PF3_ENTRY_RSVD0_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_10 -text "C_PF3_ENTRY_RSVD0_10 " -parent $T_PF3_10] + set V_PF3_ENTRY_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_10 -tclproc VAL_PF3_ENTRY_TYPE_10 -parent $T_PF3_10] + set V_PF3_ENTRY_BAR_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_10 -tclproc VAL_PF3_ENTRY_BAR_10 -parent $T_PF3_10] + set V_PF3_ENTRY_ADDR_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_10 -tclproc VAL_PF3_ENTRY_ADDR_10 -parent $T_PF3_10] + set V_PF3_ENTRY_VERSION_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_10 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_10 -parent $T_PF3_10] + set V_PF3_ENTRY_MAJOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_10 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_10 -parent $T_PF3_10] + set V_PF3_ENTRY_MINOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_10 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_10 -parent $T_PF3_10] + set V_PF3_ENTRY_RSVD0_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_10 -tclproc VAL_PF3_ENTRY_RSVD0_10 -parent $T_PF3_10] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_10 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_10 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_10 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_10 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_10 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_10 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_10 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_10 + + set PF3_Values_11 [ipgui::add_group $IPINST -name "PF3 - Table Entry 11 Values" -parent $PF3_Values] + set T_PF3_11 [ipgui::add_table $IPINST -name T_PF3_11 -rows 7 -columns 2 -parent $PF3_Values_11] + set L_PF3_ENTRY_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_11 -text "C_PF3_ENTRY_TYPE_11 " -parent $T_PF3_11] + set L_PF3_ENTRY_BAR_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_11 -text "C_PF3_ENTRY_BAR_11 " -parent $T_PF3_11] + set L_PF3_ENTRY_ADDR_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_11 -text "C_PF3_ENTRY_ADDR_11 " -parent $T_PF3_11] + set L_PF3_ENTRY_VERSION_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_11 -text "C_PF3_ENTRY_VERSION_TYPE_11 " -parent $T_PF3_11] + set L_PF3_ENTRY_MAJOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_11 -text "C_PF3_ENTRY_MAJOR_VERSION_11" -parent $T_PF3_11] + set L_PF3_ENTRY_MINOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_11 -text "C_PF3_ENTRY_MINOR_VERSION_11" -parent $T_PF3_11] + set L_PF3_ENTRY_RSVD0_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_11 -text "C_PF3_ENTRY_RSVD0_11 " -parent $T_PF3_11] + set V_PF3_ENTRY_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_11 -tclproc VAL_PF3_ENTRY_TYPE_11 -parent $T_PF3_11] + set V_PF3_ENTRY_BAR_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_11 -tclproc VAL_PF3_ENTRY_BAR_11 -parent $T_PF3_11] + set V_PF3_ENTRY_ADDR_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_11 -tclproc VAL_PF3_ENTRY_ADDR_11 -parent $T_PF3_11] + set V_PF3_ENTRY_VERSION_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_11 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_11 -parent $T_PF3_11] + set V_PF3_ENTRY_MAJOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_11 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_11 -parent $T_PF3_11] + set V_PF3_ENTRY_MINOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_11 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_11 -parent $T_PF3_11] + set V_PF3_ENTRY_RSVD0_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_11 -tclproc VAL_PF3_ENTRY_RSVD0_11 -parent $T_PF3_11] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_11 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_11 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_11 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_11 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_11 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_11 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_11 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_11 + + set PF3_Values_12 [ipgui::add_group $IPINST -name "PF3 - Table Entry 12 Values" -parent $PF3_Values] + set T_PF3_12 [ipgui::add_table $IPINST -name T_PF3_12 -rows 7 -columns 2 -parent $PF3_Values_12] + set L_PF3_ENTRY_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_12 -text "C_PF3_ENTRY_TYPE_12 " -parent $T_PF3_12] + set L_PF3_ENTRY_BAR_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_12 -text "C_PF3_ENTRY_BAR_12 " -parent $T_PF3_12] + set L_PF3_ENTRY_ADDR_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_12 -text "C_PF3_ENTRY_ADDR_12 " -parent $T_PF3_12] + set L_PF3_ENTRY_VERSION_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_12 -text "C_PF3_ENTRY_VERSION_TYPE_12 " -parent $T_PF3_12] + set L_PF3_ENTRY_MAJOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_12 -text "C_PF3_ENTRY_MAJOR_VERSION_12" -parent $T_PF3_12] + set L_PF3_ENTRY_MINOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_12 -text "C_PF3_ENTRY_MINOR_VERSION_12" -parent $T_PF3_12] + set L_PF3_ENTRY_RSVD0_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_12 -text "C_PF3_ENTRY_RSVD0_12 " -parent $T_PF3_12] + set V_PF3_ENTRY_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_12 -tclproc VAL_PF3_ENTRY_TYPE_12 -parent $T_PF3_12] + set V_PF3_ENTRY_BAR_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_12 -tclproc VAL_PF3_ENTRY_BAR_12 -parent $T_PF3_12] + set V_PF3_ENTRY_ADDR_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_12 -tclproc VAL_PF3_ENTRY_ADDR_12 -parent $T_PF3_12] + set V_PF3_ENTRY_VERSION_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_12 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_12 -parent $T_PF3_12] + set V_PF3_ENTRY_MAJOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_12 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_12 -parent $T_PF3_12] + set V_PF3_ENTRY_MINOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_12 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_12 -parent $T_PF3_12] + set V_PF3_ENTRY_RSVD0_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_12 -tclproc VAL_PF3_ENTRY_RSVD0_12 -parent $T_PF3_12] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_12 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_12 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_12 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_12 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_12 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_12 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_12 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_12 + + set PF3_Values_13 [ipgui::add_group $IPINST -name "PF3 - Table Entry 13 Values" -parent $PF3_Values] + set T_PF3_13 [ipgui::add_table $IPINST -name T_PF3_13 -rows 7 -columns 2 -parent $PF3_Values_13] + set L_PF3_ENTRY_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_13 -text "C_PF3_ENTRY_TYPE_13 " -parent $T_PF3_13] + set L_PF3_ENTRY_BAR_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_13 -text "C_PF3_ENTRY_BAR_13 " -parent $T_PF3_13] + set L_PF3_ENTRY_ADDR_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_13 -text "C_PF3_ENTRY_ADDR_13 " -parent $T_PF3_13] + set L_PF3_ENTRY_VERSION_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_13 -text "C_PF3_ENTRY_VERSION_TYPE_13 " -parent $T_PF3_13] + set L_PF3_ENTRY_MAJOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_13 -text "C_PF3_ENTRY_MAJOR_VERSION_13" -parent $T_PF3_13] + set L_PF3_ENTRY_MINOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_13 -text "C_PF3_ENTRY_MINOR_VERSION_13" -parent $T_PF3_13] + set L_PF3_ENTRY_RSVD0_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_13 -text "C_PF3_ENTRY_RSVD0_13 " -parent $T_PF3_13] + set V_PF3_ENTRY_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_13 -tclproc VAL_PF3_ENTRY_TYPE_13 -parent $T_PF3_13] + set V_PF3_ENTRY_BAR_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_13 -tclproc VAL_PF3_ENTRY_BAR_13 -parent $T_PF3_13] + set V_PF3_ENTRY_ADDR_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_13 -tclproc VAL_PF3_ENTRY_ADDR_13 -parent $T_PF3_13] + set V_PF3_ENTRY_VERSION_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_13 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_13 -parent $T_PF3_13] + set V_PF3_ENTRY_MAJOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_13 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_13 -parent $T_PF3_13] + set V_PF3_ENTRY_MINOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_13 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_13 -parent $T_PF3_13] + set V_PF3_ENTRY_RSVD0_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_13 -tclproc VAL_PF3_ENTRY_RSVD0_13 -parent $T_PF3_13] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_13 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_13 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_13 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_13 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_13 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_13 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_13 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_13 +} + +proc update_PARAM_VALUE.C_PF1_ENDPOINT_NAMES { PARAM_VALUE.C_PF1_ENDPOINT_NAMES PARAM_VALUE.C_NUM_PFS} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + if {$num_pfs > 1} { + set_property enabled true ${PARAM_VALUE.C_PF1_ENDPOINT_NAMES} + } else { + set_property enabled false ${PARAM_VALUE.C_PF1_ENDPOINT_NAMES} + } +} + +proc update_PARAM_VALUE.C_PF2_ENDPOINT_NAMES { PARAM_VALUE.C_PF2_ENDPOINT_NAMES PARAM_VALUE.C_NUM_PFS} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + if {$num_pfs >2} { + set_property enabled true ${PARAM_VALUE.C_PF2_ENDPOINT_NAMES} + } else { + set_property enabled false ${PARAM_VALUE.C_PF2_ENDPOINT_NAMES} + } +} + +proc update_PARAM_VALUE.C_PF3_ENDPOINT_NAMES { PARAM_VALUE.C_PF3_ENDPOINT_NAMES PARAM_VALUE.C_NUM_PFS} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + if {$num_pfs >3} { + set_property enabled true ${PARAM_VALUE.C_PF3_ENDPOINT_NAMES} + } else { + set_property enabled false ${PARAM_VALUE.C_PF3_ENDPOINT_NAMES} + } +} + +proc update_PARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH PARAM_VALUE.C_NUM_PFS} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + if {$num_pfs >1} { + set_property enabled true ${PARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH} + } else { + set_property enabled false ${PARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH} + } +} + +proc update_PARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH PARAM_VALUE.C_NUM_PFS} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + if {$num_pfs >2} { + set_property enabled true ${PARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH} + } else { + set_property enabled false ${PARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH} + } +} + +proc update_PARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH PARAM_VALUE.C_NUM_PFS} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + if {$num_pfs >3} { + set_property enabled true ${PARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH} + } else { + set_property enabled false ${PARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH} + } +} + +proc update_MODELPARAM_VALUE.C_NUM_PFS { MODELPARAM_VALUE.C_NUM_PFS PARAM_VALUE.C_NUM_PFS} { + set_property value [get_property value ${PARAM_VALUE.C_NUM_PFS}] ${MODELPARAM_VALUE.C_NUM_PFS} +} + +proc update_MODELPARAM_VALUE.C_CAP_BASE_ADDR { MODELPARAM_VALUE.C_CAP_BASE_ADDR PARAM_VALUE.C_CAP_BASE_ADDR} { + set_property value [get_property value ${PARAM_VALUE.C_CAP_BASE_ADDR}] ${MODELPARAM_VALUE.C_CAP_BASE_ADDR} +} + +proc validate_PARAM_VALUE.C_CAP_BASE_ADDR { PARAM_VALUE.C_CAP_BASE_ADDR IPINST} { + set cap_base_addr [get_property value ${PARAM_VALUE.C_CAP_BASE_ADDR}] + if {[expr $cap_base_addr & 0x00F] == 0x000} { + return true + } else { + set_property errmsg "C_CAP_BASE_ADDR must be a multiple of 0x10." [ipgui::get_paramspec -name C_CAP_BASE_ADDR -of $IPINST ] + return false + } +} + +proc update_MODELPARAM_VALUE.C_NEXT_CAP_ADDR { MODELPARAM_VALUE.C_NEXT_CAP_ADDR PARAM_VALUE.C_NEXT_CAP_ADDR} { + set_property value [get_property value ${PARAM_VALUE.C_NEXT_CAP_ADDR}] ${MODELPARAM_VALUE.C_NEXT_CAP_ADDR} +} + +proc validate_PARAM_VALUE.C_NEXT_CAP_ADDR {PARAM_VALUE.C_CAP_BASE_ADDR PARAM_VALUE.C_NEXT_CAP_ADDR IPINST} { + set cap_base_addr [get_property value ${PARAM_VALUE.C_CAP_BASE_ADDR}] + set calc_cap_base_addr [ expr {$cap_base_addr + 0x010} ] + set nxt_cap_base_addr [get_property value ${PARAM_VALUE.C_NEXT_CAP_ADDR}] + if { $nxt_cap_base_addr == 0x000} { + return true + } elseif {[expr $nxt_cap_base_addr & 0x00F] != 0x000} { + set_property errmsg "C_NEXT_CAP_ADDR must be a multiple of 0x10." [ipgui::get_paramspec -name C_NEXT_CAP_ADDR -of $IPINST ] + return false + } elseif {$nxt_cap_base_addr >= $calc_cap_base_addr} { + return true + } else { + set_property errmsg "C_NEXT_CAP_ADDR must be at least 0x010 above C_CAP_BASE_ADDR." [ipgui::get_paramspec -name C_NEXT_CAP_ADDR -of $IPINST ] + return false + } +} + +proc update_MODELPARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE { MODELPARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set_property value [get_property value ${PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE}] ${MODELPARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE} +} +proc update_MODELPARAM_VALUE.C_PF0_BAR_INDEX { MODELPARAM_VALUE.C_PF0_BAR_INDEX PARAM_VALUE.C_PF0_BAR_INDEX} { + set_property value [get_property value ${PARAM_VALUE.C_PF0_BAR_INDEX}] ${MODELPARAM_VALUE.C_PF0_BAR_INDEX} +} +proc update_MODELPARAM_VALUE.C_PF0_LOW_OFFSET { MODELPARAM_VALUE.C_PF0_LOW_OFFSET PARAM_VALUE.C_PF0_LOW_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF0_LOW_OFFSET}] ${MODELPARAM_VALUE.C_PF0_LOW_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF0_HIGH_OFFSET { MODELPARAM_VALUE.C_PF0_HIGH_OFFSET PARAM_VALUE.C_PF0_HIGH_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF0_HIGH_OFFSET}] ${MODELPARAM_VALUE.C_PF0_HIGH_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF0_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_PF0_S_AXI_ADDR_WIDTH PARAM_VALUE.C_PF0_S_AXI_ADDR_WIDTH} { + set_property value [get_property value ${PARAM_VALUE.C_PF0_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_PF0_S_AXI_ADDR_WIDTH} +} +proc update_MODELPARAM_VALUE.C_PF0_ENDPOINT_NAMES { MODELPARAM_VALUE.C_PF0_ENDPOINT_NAMES PARAM_VALUE.C_PF0_ENDPOINT_NAMES} { + set_property value [get_property value ${PARAM_VALUE.C_PF0_ENDPOINT_NAMES}] ${MODELPARAM_VALUE.C_PF0_ENDPOINT_NAMES} +} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_0 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_0 PARAM_VALUE.C_PF0_ENTRY_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_1 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_1 PARAM_VALUE.C_PF0_ENTRY_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_2 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_2 PARAM_VALUE.C_PF0_ENTRY_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_3 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_3 PARAM_VALUE.C_PF0_ENTRY_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_4 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_4 PARAM_VALUE.C_PF0_ENTRY_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_5 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_5 PARAM_VALUE.C_PF0_ENTRY_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_6 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_6 PARAM_VALUE.C_PF0_ENTRY_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_7 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_7 PARAM_VALUE.C_PF0_ENTRY_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_8 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_8 PARAM_VALUE.C_PF0_ENTRY_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_9 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_9 PARAM_VALUE.C_PF0_ENTRY_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_10 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_10 PARAM_VALUE.C_PF0_ENTRY_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_11 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_11 PARAM_VALUE.C_PF0_ENTRY_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_12 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_12 PARAM_VALUE.C_PF0_ENTRY_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_13 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_13 PARAM_VALUE.C_PF0_ENTRY_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_0 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_0 PARAM_VALUE.C_PF0_ENTRY_BAR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_1 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_1 PARAM_VALUE.C_PF0_ENTRY_BAR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_2 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_2 PARAM_VALUE.C_PF0_ENTRY_BAR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_3 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_3 PARAM_VALUE.C_PF0_ENTRY_BAR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_4 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_4 PARAM_VALUE.C_PF0_ENTRY_BAR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_5 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_5 PARAM_VALUE.C_PF0_ENTRY_BAR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_6 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_6 PARAM_VALUE.C_PF0_ENTRY_BAR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_7 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_7 PARAM_VALUE.C_PF0_ENTRY_BAR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_8 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_8 PARAM_VALUE.C_PF0_ENTRY_BAR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_9 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_9 PARAM_VALUE.C_PF0_ENTRY_BAR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_10 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_10 PARAM_VALUE.C_PF0_ENTRY_BAR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_11 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_11 PARAM_VALUE.C_PF0_ENTRY_BAR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_12 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_12 PARAM_VALUE.C_PF0_ENTRY_BAR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_13 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_13 PARAM_VALUE.C_PF0_ENTRY_BAR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_13}} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_0 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_0 PARAM_VALUE.C_PF0_ENTRY_ADDR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_1 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_1 PARAM_VALUE.C_PF0_ENTRY_ADDR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_2 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_2 PARAM_VALUE.C_PF0_ENTRY_ADDR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_3 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_3 PARAM_VALUE.C_PF0_ENTRY_ADDR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_4 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_4 PARAM_VALUE.C_PF0_ENTRY_ADDR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_5 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_5 PARAM_VALUE.C_PF0_ENTRY_ADDR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_6 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_6 PARAM_VALUE.C_PF0_ENTRY_ADDR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_7 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_7 PARAM_VALUE.C_PF0_ENTRY_ADDR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_8 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_8 PARAM_VALUE.C_PF0_ENTRY_ADDR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_9 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_9 PARAM_VALUE.C_PF0_ENTRY_ADDR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_10 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_10 PARAM_VALUE.C_PF0_ENTRY_ADDR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_11 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_11 PARAM_VALUE.C_PF0_ENTRY_ADDR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_12 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_12 PARAM_VALUE.C_PF0_ENTRY_ADDR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_13 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_13 PARAM_VALUE.C_PF0_ENTRY_ADDR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_13}} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_0 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_0 PARAM_VALUE.C_PF0_ENTRY_RSVD0_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_1 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_1 PARAM_VALUE.C_PF0_ENTRY_RSVD0_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_2 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_2 PARAM_VALUE.C_PF0_ENTRY_RSVD0_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_3 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_3 PARAM_VALUE.C_PF0_ENTRY_RSVD0_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_4 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_4 PARAM_VALUE.C_PF0_ENTRY_RSVD0_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_5 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_5 PARAM_VALUE.C_PF0_ENTRY_RSVD0_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_6 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_6 PARAM_VALUE.C_PF0_ENTRY_RSVD0_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_7 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_7 PARAM_VALUE.C_PF0_ENTRY_RSVD0_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_8 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_8 PARAM_VALUE.C_PF0_ENTRY_RSVD0_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_9 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_9 PARAM_VALUE.C_PF0_ENTRY_RSVD0_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_10 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_10 PARAM_VALUE.C_PF0_ENTRY_RSVD0_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_11 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_11 PARAM_VALUE.C_PF0_ENTRY_RSVD0_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_12 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_12 PARAM_VALUE.C_PF0_ENTRY_RSVD0_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_13 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_13 PARAM_VALUE.C_PF0_ENTRY_RSVD0_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_13}} + +proc update_MODELPARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE { MODELPARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set_property value [get_property value ${PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE}] ${MODELPARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE} +} +proc update_MODELPARAM_VALUE.C_PF1_BAR_INDEX { MODELPARAM_VALUE.C_PF1_BAR_INDEX PARAM_VALUE.C_PF1_BAR_INDEX} { + set_property value [get_property value ${PARAM_VALUE.C_PF1_BAR_INDEX}] ${MODELPARAM_VALUE.C_PF1_BAR_INDEX} +} +proc update_MODELPARAM_VALUE.C_PF1_LOW_OFFSET { MODELPARAM_VALUE.C_PF1_LOW_OFFSET PARAM_VALUE.C_PF1_LOW_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF1_LOW_OFFSET}] ${MODELPARAM_VALUE.C_PF1_LOW_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF1_HIGH_OFFSET { MODELPARAM_VALUE.C_PF1_HIGH_OFFSET PARAM_VALUE.C_PF1_HIGH_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF1_HIGH_OFFSET}] ${MODELPARAM_VALUE.C_PF1_HIGH_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH PARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH} { + set_property value [get_property value ${PARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH} +} +proc update_MODELPARAM_VALUE.C_PF1_ENDPOINT_NAMES { MODELPARAM_VALUE.C_PF1_ENDPOINT_NAMES PARAM_VALUE.C_PF1_ENDPOINT_NAMES} { + set_property value [get_property value ${PARAM_VALUE.C_PF1_ENDPOINT_NAMES}] ${MODELPARAM_VALUE.C_PF1_ENDPOINT_NAMES} +} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_0 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_0 PARAM_VALUE.C_PF1_ENTRY_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_1 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_1 PARAM_VALUE.C_PF1_ENTRY_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_2 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_2 PARAM_VALUE.C_PF1_ENTRY_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_3 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_3 PARAM_VALUE.C_PF1_ENTRY_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_4 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_4 PARAM_VALUE.C_PF1_ENTRY_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_5 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_5 PARAM_VALUE.C_PF1_ENTRY_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_6 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_6 PARAM_VALUE.C_PF1_ENTRY_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_7 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_7 PARAM_VALUE.C_PF1_ENTRY_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_8 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_8 PARAM_VALUE.C_PF1_ENTRY_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_9 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_9 PARAM_VALUE.C_PF1_ENTRY_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_10 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_10 PARAM_VALUE.C_PF1_ENTRY_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_11 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_11 PARAM_VALUE.C_PF1_ENTRY_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_12 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_12 PARAM_VALUE.C_PF1_ENTRY_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_13 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_13 PARAM_VALUE.C_PF1_ENTRY_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_0 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_0 PARAM_VALUE.C_PF1_ENTRY_BAR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_1 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_1 PARAM_VALUE.C_PF1_ENTRY_BAR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_2 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_2 PARAM_VALUE.C_PF1_ENTRY_BAR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_3 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_3 PARAM_VALUE.C_PF1_ENTRY_BAR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_4 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_4 PARAM_VALUE.C_PF1_ENTRY_BAR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_5 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_5 PARAM_VALUE.C_PF1_ENTRY_BAR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_6 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_6 PARAM_VALUE.C_PF1_ENTRY_BAR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_7 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_7 PARAM_VALUE.C_PF1_ENTRY_BAR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_8 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_8 PARAM_VALUE.C_PF1_ENTRY_BAR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_9 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_9 PARAM_VALUE.C_PF1_ENTRY_BAR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_10 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_10 PARAM_VALUE.C_PF1_ENTRY_BAR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_11 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_11 PARAM_VALUE.C_PF1_ENTRY_BAR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_12 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_12 PARAM_VALUE.C_PF1_ENTRY_BAR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_13 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_13 PARAM_VALUE.C_PF1_ENTRY_BAR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_13}} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_0 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_0 PARAM_VALUE.C_PF1_ENTRY_ADDR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_1 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_1 PARAM_VALUE.C_PF1_ENTRY_ADDR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_2 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_2 PARAM_VALUE.C_PF1_ENTRY_ADDR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_3 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_3 PARAM_VALUE.C_PF1_ENTRY_ADDR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_4 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_4 PARAM_VALUE.C_PF1_ENTRY_ADDR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_5 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_5 PARAM_VALUE.C_PF1_ENTRY_ADDR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_6 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_6 PARAM_VALUE.C_PF1_ENTRY_ADDR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_7 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_7 PARAM_VALUE.C_PF1_ENTRY_ADDR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_8 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_8 PARAM_VALUE.C_PF1_ENTRY_ADDR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_9 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_9 PARAM_VALUE.C_PF1_ENTRY_ADDR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_10 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_10 PARAM_VALUE.C_PF1_ENTRY_ADDR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_11 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_11 PARAM_VALUE.C_PF1_ENTRY_ADDR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_12 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_12 PARAM_VALUE.C_PF1_ENTRY_ADDR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_13 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_13 PARAM_VALUE.C_PF1_ENTRY_ADDR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_13}} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_0 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_0 PARAM_VALUE.C_PF1_ENTRY_RSVD0_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_1 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_1 PARAM_VALUE.C_PF1_ENTRY_RSVD0_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_2 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_2 PARAM_VALUE.C_PF1_ENTRY_RSVD0_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_3 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_3 PARAM_VALUE.C_PF1_ENTRY_RSVD0_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_4 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_4 PARAM_VALUE.C_PF1_ENTRY_RSVD0_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_5 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_5 PARAM_VALUE.C_PF1_ENTRY_RSVD0_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_6 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_6 PARAM_VALUE.C_PF1_ENTRY_RSVD0_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_7 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_7 PARAM_VALUE.C_PF1_ENTRY_RSVD0_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_8 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_8 PARAM_VALUE.C_PF1_ENTRY_RSVD0_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_9 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_9 PARAM_VALUE.C_PF1_ENTRY_RSVD0_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_10 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_10 PARAM_VALUE.C_PF1_ENTRY_RSVD0_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_11 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_11 PARAM_VALUE.C_PF1_ENTRY_RSVD0_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_12 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_12 PARAM_VALUE.C_PF1_ENTRY_RSVD0_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_13 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_13 PARAM_VALUE.C_PF1_ENTRY_RSVD0_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_13}} + +proc update_MODELPARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE { MODELPARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set_property value [get_property value ${PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE}] ${MODELPARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE} +} +proc update_MODELPARAM_VALUE.C_PF2_BAR_INDEX { MODELPARAM_VALUE.C_PF2_BAR_INDEX PARAM_VALUE.C_PF2_BAR_INDEX} { + set_property value [get_property value ${PARAM_VALUE.C_PF2_BAR_INDEX}] ${MODELPARAM_VALUE.C_PF2_BAR_INDEX} +} +proc update_MODELPARAM_VALUE.C_PF2_LOW_OFFSET { MODELPARAM_VALUE.C_PF2_LOW_OFFSET PARAM_VALUE.C_PF2_LOW_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF2_LOW_OFFSET}] ${MODELPARAM_VALUE.C_PF2_LOW_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF2_HIGH_OFFSET { MODELPARAM_VALUE.C_PF2_HIGH_OFFSET PARAM_VALUE.C_PF2_HIGH_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF2_HIGH_OFFSET}] ${MODELPARAM_VALUE.C_PF2_HIGH_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH PARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH} { + set_property value [get_property value ${PARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH} +} +proc update_MODELPARAM_VALUE.C_PF2_ENDPOINT_NAMES { MODELPARAM_VALUE.C_PF2_ENDPOINT_NAMES PARAM_VALUE.C_PF2_ENDPOINT_NAMES} { + set_property value [get_property value ${PARAM_VALUE.C_PF2_ENDPOINT_NAMES}] ${MODELPARAM_VALUE.C_PF2_ENDPOINT_NAMES} +} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_0 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_0 PARAM_VALUE.C_PF2_ENTRY_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_1 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_1 PARAM_VALUE.C_PF2_ENTRY_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_2 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_2 PARAM_VALUE.C_PF2_ENTRY_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_3 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_3 PARAM_VALUE.C_PF2_ENTRY_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_4 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_4 PARAM_VALUE.C_PF2_ENTRY_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_5 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_5 PARAM_VALUE.C_PF2_ENTRY_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_6 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_6 PARAM_VALUE.C_PF2_ENTRY_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_7 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_7 PARAM_VALUE.C_PF2_ENTRY_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_8 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_8 PARAM_VALUE.C_PF2_ENTRY_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_9 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_9 PARAM_VALUE.C_PF2_ENTRY_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_10 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_10 PARAM_VALUE.C_PF2_ENTRY_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_11 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_11 PARAM_VALUE.C_PF2_ENTRY_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_12 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_12 PARAM_VALUE.C_PF2_ENTRY_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_13 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_13 PARAM_VALUE.C_PF2_ENTRY_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_0 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_0 PARAM_VALUE.C_PF2_ENTRY_BAR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_1 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_1 PARAM_VALUE.C_PF2_ENTRY_BAR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_2 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_2 PARAM_VALUE.C_PF2_ENTRY_BAR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_3 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_3 PARAM_VALUE.C_PF2_ENTRY_BAR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_4 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_4 PARAM_VALUE.C_PF2_ENTRY_BAR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_5 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_5 PARAM_VALUE.C_PF2_ENTRY_BAR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_6 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_6 PARAM_VALUE.C_PF2_ENTRY_BAR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_7 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_7 PARAM_VALUE.C_PF2_ENTRY_BAR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_8 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_8 PARAM_VALUE.C_PF2_ENTRY_BAR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_9 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_9 PARAM_VALUE.C_PF2_ENTRY_BAR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_10 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_10 PARAM_VALUE.C_PF2_ENTRY_BAR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_11 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_11 PARAM_VALUE.C_PF2_ENTRY_BAR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_12 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_12 PARAM_VALUE.C_PF2_ENTRY_BAR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_13 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_13 PARAM_VALUE.C_PF2_ENTRY_BAR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_13}} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_0 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_0 PARAM_VALUE.C_PF2_ENTRY_ADDR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_1 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_1 PARAM_VALUE.C_PF2_ENTRY_ADDR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_2 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_2 PARAM_VALUE.C_PF2_ENTRY_ADDR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_3 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_3 PARAM_VALUE.C_PF2_ENTRY_ADDR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_4 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_4 PARAM_VALUE.C_PF2_ENTRY_ADDR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_5 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_5 PARAM_VALUE.C_PF2_ENTRY_ADDR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_6 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_6 PARAM_VALUE.C_PF2_ENTRY_ADDR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_7 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_7 PARAM_VALUE.C_PF2_ENTRY_ADDR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_8 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_8 PARAM_VALUE.C_PF2_ENTRY_ADDR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_9 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_9 PARAM_VALUE.C_PF2_ENTRY_ADDR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_10 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_10 PARAM_VALUE.C_PF2_ENTRY_ADDR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_11 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_11 PARAM_VALUE.C_PF2_ENTRY_ADDR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_12 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_12 PARAM_VALUE.C_PF2_ENTRY_ADDR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_13 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_13 PARAM_VALUE.C_PF2_ENTRY_ADDR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_13}} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_0 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_0 PARAM_VALUE.C_PF2_ENTRY_RSVD0_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_1 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_1 PARAM_VALUE.C_PF2_ENTRY_RSVD0_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_2 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_2 PARAM_VALUE.C_PF2_ENTRY_RSVD0_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_3 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_3 PARAM_VALUE.C_PF2_ENTRY_RSVD0_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_4 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_4 PARAM_VALUE.C_PF2_ENTRY_RSVD0_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_5 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_5 PARAM_VALUE.C_PF2_ENTRY_RSVD0_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_6 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_6 PARAM_VALUE.C_PF2_ENTRY_RSVD0_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_7 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_7 PARAM_VALUE.C_PF2_ENTRY_RSVD0_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_8 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_8 PARAM_VALUE.C_PF2_ENTRY_RSVD0_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_9 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_9 PARAM_VALUE.C_PF2_ENTRY_RSVD0_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_10 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_10 PARAM_VALUE.C_PF2_ENTRY_RSVD0_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_11 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_11 PARAM_VALUE.C_PF2_ENTRY_RSVD0_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_12 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_12 PARAM_VALUE.C_PF2_ENTRY_RSVD0_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_13 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_13 PARAM_VALUE.C_PF2_ENTRY_RSVD0_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_13}} + +proc update_MODELPARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE { MODELPARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set_property value [get_property value ${PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE}] ${MODELPARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE} +} +proc update_MODELPARAM_VALUE.C_PF3_BAR_INDEX { MODELPARAM_VALUE.C_PF3_BAR_INDEX PARAM_VALUE.C_PF3_BAR_INDEX} { + set_property value [get_property value ${PARAM_VALUE.C_PF3_BAR_INDEX}] ${MODELPARAM_VALUE.C_PF3_BAR_INDEX} +} +proc update_MODELPARAM_VALUE.C_PF3_LOW_OFFSET { MODELPARAM_VALUE.C_PF3_LOW_OFFSET PARAM_VALUE.C_PF3_LOW_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF3_LOW_OFFSET}] ${MODELPARAM_VALUE.C_PF3_LOW_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF3_HIGH_OFFSET { MODELPARAM_VALUE.C_PF3_HIGH_OFFSET PARAM_VALUE.C_PF3_HIGH_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF3_HIGH_OFFSET}] ${MODELPARAM_VALUE.C_PF3_HIGH_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH PARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH} { + set_property value [get_property value ${PARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH} +} +proc update_MODELPARAM_VALUE.C_PF3_ENDPOINT_NAMES { MODELPARAM_VALUE.C_PF3_ENDPOINT_NAMES PARAM_VALUE.C_PF3_ENDPOINT_NAMES} { + set_property value [get_property value ${PARAM_VALUE.C_PF3_ENDPOINT_NAMES}] ${MODELPARAM_VALUE.C_PF3_ENDPOINT_NAMES} +} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_0 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_0 PARAM_VALUE.C_PF3_ENTRY_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_1 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_1 PARAM_VALUE.C_PF3_ENTRY_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_2 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_2 PARAM_VALUE.C_PF3_ENTRY_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_3 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_3 PARAM_VALUE.C_PF3_ENTRY_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_4 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_4 PARAM_VALUE.C_PF3_ENTRY_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_5 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_5 PARAM_VALUE.C_PF3_ENTRY_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_6 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_6 PARAM_VALUE.C_PF3_ENTRY_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_7 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_7 PARAM_VALUE.C_PF3_ENTRY_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_8 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_8 PARAM_VALUE.C_PF3_ENTRY_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_9 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_9 PARAM_VALUE.C_PF3_ENTRY_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_10 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_10 PARAM_VALUE.C_PF3_ENTRY_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_11 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_11 PARAM_VALUE.C_PF3_ENTRY_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_12 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_12 PARAM_VALUE.C_PF3_ENTRY_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_13 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_13 PARAM_VALUE.C_PF3_ENTRY_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_0 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_0 PARAM_VALUE.C_PF3_ENTRY_BAR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_1 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_1 PARAM_VALUE.C_PF3_ENTRY_BAR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_2 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_2 PARAM_VALUE.C_PF3_ENTRY_BAR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_3 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_3 PARAM_VALUE.C_PF3_ENTRY_BAR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_4 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_4 PARAM_VALUE.C_PF3_ENTRY_BAR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_5 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_5 PARAM_VALUE.C_PF3_ENTRY_BAR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_6 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_6 PARAM_VALUE.C_PF3_ENTRY_BAR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_7 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_7 PARAM_VALUE.C_PF3_ENTRY_BAR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_8 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_8 PARAM_VALUE.C_PF3_ENTRY_BAR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_9 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_9 PARAM_VALUE.C_PF3_ENTRY_BAR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_10 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_10 PARAM_VALUE.C_PF3_ENTRY_BAR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_11 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_11 PARAM_VALUE.C_PF3_ENTRY_BAR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_12 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_12 PARAM_VALUE.C_PF3_ENTRY_BAR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_13 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_13 PARAM_VALUE.C_PF3_ENTRY_BAR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_13}} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_0 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_0 PARAM_VALUE.C_PF3_ENTRY_ADDR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_1 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_1 PARAM_VALUE.C_PF3_ENTRY_ADDR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_2 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_2 PARAM_VALUE.C_PF3_ENTRY_ADDR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_3 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_3 PARAM_VALUE.C_PF3_ENTRY_ADDR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_4 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_4 PARAM_VALUE.C_PF3_ENTRY_ADDR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_5 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_5 PARAM_VALUE.C_PF3_ENTRY_ADDR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_6 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_6 PARAM_VALUE.C_PF3_ENTRY_ADDR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_7 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_7 PARAM_VALUE.C_PF3_ENTRY_ADDR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_8 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_8 PARAM_VALUE.C_PF3_ENTRY_ADDR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_9 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_9 PARAM_VALUE.C_PF3_ENTRY_ADDR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_10 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_10 PARAM_VALUE.C_PF3_ENTRY_ADDR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_11 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_11 PARAM_VALUE.C_PF3_ENTRY_ADDR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_12 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_12 PARAM_VALUE.C_PF3_ENTRY_ADDR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_13 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_13 PARAM_VALUE.C_PF3_ENTRY_ADDR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_13}} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_0 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_0 PARAM_VALUE.C_PF3_ENTRY_RSVD0_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_1 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_1 PARAM_VALUE.C_PF3_ENTRY_RSVD0_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_2 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_2 PARAM_VALUE.C_PF3_ENTRY_RSVD0_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_3 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_3 PARAM_VALUE.C_PF3_ENTRY_RSVD0_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_4 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_4 PARAM_VALUE.C_PF3_ENTRY_RSVD0_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_5 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_5 PARAM_VALUE.C_PF3_ENTRY_RSVD0_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_6 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_6 PARAM_VALUE.C_PF3_ENTRY_RSVD0_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_7 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_7 PARAM_VALUE.C_PF3_ENTRY_RSVD0_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_8 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_8 PARAM_VALUE.C_PF3_ENTRY_RSVD0_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_9 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_9 PARAM_VALUE.C_PF3_ENTRY_RSVD0_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_10 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_10 PARAM_VALUE.C_PF3_ENTRY_RSVD0_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_11 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_11 PARAM_VALUE.C_PF3_ENTRY_RSVD0_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_12 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_12 PARAM_VALUE.C_PF3_ENTRY_RSVD0_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_13 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_13 PARAM_VALUE.C_PF3_ENTRY_RSVD0_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_13}} + +proc VAL_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE { PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE} {return "[get_property value ${PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE}]"} +proc VAL_PF0_BAR_INDEX { PARAM_VALUE.C_PF0_BAR_INDEX } {return "[get_property value ${PARAM_VALUE.C_PF0_BAR_INDEX}]"} +proc VAL_PF0_LOW_OFFSET { PARAM_VALUE.C_PF0_LOW_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF0_LOW_OFFSET}]"} +proc VAL_PF0_HIGH_OFFSET { PARAM_VALUE.C_PF0_HIGH_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF0_HIGH_OFFSET}]"} + +proc VAL_PF0_ENTRY_TYPE_0 { PARAM_VALUE.C_PF0_ENTRY_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_0} ]"} +proc VAL_PF0_ENTRY_TYPE_1 { PARAM_VALUE.C_PF0_ENTRY_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_1} ]"} +proc VAL_PF0_ENTRY_TYPE_2 { PARAM_VALUE.C_PF0_ENTRY_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_2} ]"} +proc VAL_PF0_ENTRY_TYPE_3 { PARAM_VALUE.C_PF0_ENTRY_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_3} ]"} +proc VAL_PF0_ENTRY_TYPE_4 { PARAM_VALUE.C_PF0_ENTRY_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_4} ]"} +proc VAL_PF0_ENTRY_TYPE_5 { PARAM_VALUE.C_PF0_ENTRY_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_5} ]"} +proc VAL_PF0_ENTRY_TYPE_6 { PARAM_VALUE.C_PF0_ENTRY_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_6} ]"} +proc VAL_PF0_ENTRY_TYPE_7 { PARAM_VALUE.C_PF0_ENTRY_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_7} ]"} +proc VAL_PF0_ENTRY_TYPE_8 { PARAM_VALUE.C_PF0_ENTRY_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_8} ]"} +proc VAL_PF0_ENTRY_TYPE_9 { PARAM_VALUE.C_PF0_ENTRY_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_9} ]"} +proc VAL_PF0_ENTRY_TYPE_10 { PARAM_VALUE.C_PF0_ENTRY_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_10}]"} +proc VAL_PF0_ENTRY_TYPE_11 { PARAM_VALUE.C_PF0_ENTRY_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_11}]"} +proc VAL_PF0_ENTRY_TYPE_12 { PARAM_VALUE.C_PF0_ENTRY_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_12}]"} +proc VAL_PF0_ENTRY_TYPE_13 { PARAM_VALUE.C_PF0_ENTRY_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_13}]"} + +proc VAL_PF0_ENTRY_BAR_0 { PARAM_VALUE.C_PF0_ENTRY_BAR_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_0} ]"} +proc VAL_PF0_ENTRY_BAR_1 { PARAM_VALUE.C_PF0_ENTRY_BAR_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_1} ]"} +proc VAL_PF0_ENTRY_BAR_2 { PARAM_VALUE.C_PF0_ENTRY_BAR_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_2} ]"} +proc VAL_PF0_ENTRY_BAR_3 { PARAM_VALUE.C_PF0_ENTRY_BAR_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_3} ]"} +proc VAL_PF0_ENTRY_BAR_4 { PARAM_VALUE.C_PF0_ENTRY_BAR_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_4} ]"} +proc VAL_PF0_ENTRY_BAR_5 { PARAM_VALUE.C_PF0_ENTRY_BAR_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_5} ]"} +proc VAL_PF0_ENTRY_BAR_6 { PARAM_VALUE.C_PF0_ENTRY_BAR_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_6} ]"} +proc VAL_PF0_ENTRY_BAR_7 { PARAM_VALUE.C_PF0_ENTRY_BAR_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_7} ]"} +proc VAL_PF0_ENTRY_BAR_8 { PARAM_VALUE.C_PF0_ENTRY_BAR_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_8} ]"} +proc VAL_PF0_ENTRY_BAR_9 { PARAM_VALUE.C_PF0_ENTRY_BAR_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_9} ]"} +proc VAL_PF0_ENTRY_BAR_10 { PARAM_VALUE.C_PF0_ENTRY_BAR_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_10} ]"} +proc VAL_PF0_ENTRY_BAR_11 { PARAM_VALUE.C_PF0_ENTRY_BAR_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_11} ]"} +proc VAL_PF0_ENTRY_BAR_12 { PARAM_VALUE.C_PF0_ENTRY_BAR_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_12} ]"} +proc VAL_PF0_ENTRY_BAR_13 { PARAM_VALUE.C_PF0_ENTRY_BAR_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_13} ]"} + +proc VAL_PF0_ENTRY_ADDR_0 { PARAM_VALUE.C_PF0_ENTRY_ADDR_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_0} ]"} +proc VAL_PF0_ENTRY_ADDR_1 { PARAM_VALUE.C_PF0_ENTRY_ADDR_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_1} ]"} +proc VAL_PF0_ENTRY_ADDR_2 { PARAM_VALUE.C_PF0_ENTRY_ADDR_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_2} ]"} +proc VAL_PF0_ENTRY_ADDR_3 { PARAM_VALUE.C_PF0_ENTRY_ADDR_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_3} ]"} +proc VAL_PF0_ENTRY_ADDR_4 { PARAM_VALUE.C_PF0_ENTRY_ADDR_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_4} ]"} +proc VAL_PF0_ENTRY_ADDR_5 { PARAM_VALUE.C_PF0_ENTRY_ADDR_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_5} ]"} +proc VAL_PF0_ENTRY_ADDR_6 { PARAM_VALUE.C_PF0_ENTRY_ADDR_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_6} ]"} +proc VAL_PF0_ENTRY_ADDR_7 { PARAM_VALUE.C_PF0_ENTRY_ADDR_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_7} ]"} +proc VAL_PF0_ENTRY_ADDR_8 { PARAM_VALUE.C_PF0_ENTRY_ADDR_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_8} ]"} +proc VAL_PF0_ENTRY_ADDR_9 { PARAM_VALUE.C_PF0_ENTRY_ADDR_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_9} ]"} +proc VAL_PF0_ENTRY_ADDR_10 { PARAM_VALUE.C_PF0_ENTRY_ADDR_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_10} ]"} +proc VAL_PF0_ENTRY_ADDR_11 { PARAM_VALUE.C_PF0_ENTRY_ADDR_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_11} ]"} +proc VAL_PF0_ENTRY_ADDR_12 { PARAM_VALUE.C_PF0_ENTRY_ADDR_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_12} ]"} +proc VAL_PF0_ENTRY_ADDR_13 { PARAM_VALUE.C_PF0_ENTRY_ADDR_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_13} ]"} + +proc VAL_PF0_ENTRY_VERSION_TYPE_0 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_1 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_2 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_3 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_4 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_5 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_6 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_7 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_8 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_9 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_10 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_11 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_12 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_13 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13} ]"} + +proc VAL_PF0_ENTRY_MAJOR_VERSION_0 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_1 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_2 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_3 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_4 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_5 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_6 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_7 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_8 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_9 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_10 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10}]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_11 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11}]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_12 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12}]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_13 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13}]"} + +proc VAL_PF0_ENTRY_MINOR_VERSION_0 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_1 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_2 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_3 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_4 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_5 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_6 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_7 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_8 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_9 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_10 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10}]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_11 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11}]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_12 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12}]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_13 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13}]"} + +proc VAL_PF0_ENTRY_RSVD0_0 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_0} ]"} +proc VAL_PF0_ENTRY_RSVD0_1 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_1} ]"} +proc VAL_PF0_ENTRY_RSVD0_2 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_2} ]"} +proc VAL_PF0_ENTRY_RSVD0_3 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_3} ]"} +proc VAL_PF0_ENTRY_RSVD0_4 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_4} ]"} +proc VAL_PF0_ENTRY_RSVD0_5 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_5} ]"} +proc VAL_PF0_ENTRY_RSVD0_6 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_6} ]"} +proc VAL_PF0_ENTRY_RSVD0_7 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_7} ]"} +proc VAL_PF0_ENTRY_RSVD0_8 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_8} ]"} +proc VAL_PF0_ENTRY_RSVD0_9 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_9} ]"} +proc VAL_PF0_ENTRY_RSVD0_10 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_10} ]"} +proc VAL_PF0_ENTRY_RSVD0_11 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_11} ]"} +proc VAL_PF0_ENTRY_RSVD0_12 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_12} ]"} +proc VAL_PF0_ENTRY_RSVD0_13 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_13} ]"} + +proc VAL_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE { PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE} {return "[get_property value ${PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE}]"} +proc VAL_PF1_BAR_INDEX { PARAM_VALUE.C_PF1_BAR_INDEX } {return "[get_property value ${PARAM_VALUE.C_PF1_BAR_INDEX}]"} +proc VAL_PF1_LOW_OFFSET { PARAM_VALUE.C_PF1_LOW_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF1_LOW_OFFSET}]"} +proc VAL_PF1_HIGH_OFFSET { PARAM_VALUE.C_PF1_HIGH_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF1_HIGH_OFFSET}]"} + +proc VAL_PF1_ENTRY_TYPE_0 { PARAM_VALUE.C_PF1_ENTRY_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_0} ]"} +proc VAL_PF1_ENTRY_TYPE_1 { PARAM_VALUE.C_PF1_ENTRY_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_1} ]"} +proc VAL_PF1_ENTRY_TYPE_2 { PARAM_VALUE.C_PF1_ENTRY_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_2} ]"} +proc VAL_PF1_ENTRY_TYPE_3 { PARAM_VALUE.C_PF1_ENTRY_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_3} ]"} +proc VAL_PF1_ENTRY_TYPE_4 { PARAM_VALUE.C_PF1_ENTRY_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_4} ]"} +proc VAL_PF1_ENTRY_TYPE_5 { PARAM_VALUE.C_PF1_ENTRY_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_5} ]"} +proc VAL_PF1_ENTRY_TYPE_6 { PARAM_VALUE.C_PF1_ENTRY_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_6} ]"} +proc VAL_PF1_ENTRY_TYPE_7 { PARAM_VALUE.C_PF1_ENTRY_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_7} ]"} +proc VAL_PF1_ENTRY_TYPE_8 { PARAM_VALUE.C_PF1_ENTRY_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_8} ]"} +proc VAL_PF1_ENTRY_TYPE_9 { PARAM_VALUE.C_PF1_ENTRY_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_9} ]"} +proc VAL_PF1_ENTRY_TYPE_10 { PARAM_VALUE.C_PF1_ENTRY_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_10}]"} +proc VAL_PF1_ENTRY_TYPE_11 { PARAM_VALUE.C_PF1_ENTRY_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_11}]"} +proc VAL_PF1_ENTRY_TYPE_12 { PARAM_VALUE.C_PF1_ENTRY_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_12}]"} +proc VAL_PF1_ENTRY_TYPE_13 { PARAM_VALUE.C_PF1_ENTRY_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_13}]"} + +proc VAL_PF1_ENTRY_BAR_0 { PARAM_VALUE.C_PF1_ENTRY_BAR_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_0} ]"} +proc VAL_PF1_ENTRY_BAR_1 { PARAM_VALUE.C_PF1_ENTRY_BAR_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_1} ]"} +proc VAL_PF1_ENTRY_BAR_2 { PARAM_VALUE.C_PF1_ENTRY_BAR_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_2} ]"} +proc VAL_PF1_ENTRY_BAR_3 { PARAM_VALUE.C_PF1_ENTRY_BAR_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_3} ]"} +proc VAL_PF1_ENTRY_BAR_4 { PARAM_VALUE.C_PF1_ENTRY_BAR_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_4} ]"} +proc VAL_PF1_ENTRY_BAR_5 { PARAM_VALUE.C_PF1_ENTRY_BAR_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_5} ]"} +proc VAL_PF1_ENTRY_BAR_6 { PARAM_VALUE.C_PF1_ENTRY_BAR_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_6} ]"} +proc VAL_PF1_ENTRY_BAR_7 { PARAM_VALUE.C_PF1_ENTRY_BAR_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_7} ]"} +proc VAL_PF1_ENTRY_BAR_8 { PARAM_VALUE.C_PF1_ENTRY_BAR_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_8} ]"} +proc VAL_PF1_ENTRY_BAR_9 { PARAM_VALUE.C_PF1_ENTRY_BAR_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_9} ]"} +proc VAL_PF1_ENTRY_BAR_10 { PARAM_VALUE.C_PF1_ENTRY_BAR_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_10} ]"} +proc VAL_PF1_ENTRY_BAR_11 { PARAM_VALUE.C_PF1_ENTRY_BAR_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_11} ]"} +proc VAL_PF1_ENTRY_BAR_12 { PARAM_VALUE.C_PF1_ENTRY_BAR_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_12} ]"} +proc VAL_PF1_ENTRY_BAR_13 { PARAM_VALUE.C_PF1_ENTRY_BAR_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_13} ]"} + +proc VAL_PF1_ENTRY_ADDR_0 { PARAM_VALUE.C_PF1_ENTRY_ADDR_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_0} ]"} +proc VAL_PF1_ENTRY_ADDR_1 { PARAM_VALUE.C_PF1_ENTRY_ADDR_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_1} ]"} +proc VAL_PF1_ENTRY_ADDR_2 { PARAM_VALUE.C_PF1_ENTRY_ADDR_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_2} ]"} +proc VAL_PF1_ENTRY_ADDR_3 { PARAM_VALUE.C_PF1_ENTRY_ADDR_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_3} ]"} +proc VAL_PF1_ENTRY_ADDR_4 { PARAM_VALUE.C_PF1_ENTRY_ADDR_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_4} ]"} +proc VAL_PF1_ENTRY_ADDR_5 { PARAM_VALUE.C_PF1_ENTRY_ADDR_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_5} ]"} +proc VAL_PF1_ENTRY_ADDR_6 { PARAM_VALUE.C_PF1_ENTRY_ADDR_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_6} ]"} +proc VAL_PF1_ENTRY_ADDR_7 { PARAM_VALUE.C_PF1_ENTRY_ADDR_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_7} ]"} +proc VAL_PF1_ENTRY_ADDR_8 { PARAM_VALUE.C_PF1_ENTRY_ADDR_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_8} ]"} +proc VAL_PF1_ENTRY_ADDR_9 { PARAM_VALUE.C_PF1_ENTRY_ADDR_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_9} ]"} +proc VAL_PF1_ENTRY_ADDR_10 { PARAM_VALUE.C_PF1_ENTRY_ADDR_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_10} ]"} +proc VAL_PF1_ENTRY_ADDR_11 { PARAM_VALUE.C_PF1_ENTRY_ADDR_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_11} ]"} +proc VAL_PF1_ENTRY_ADDR_12 { PARAM_VALUE.C_PF1_ENTRY_ADDR_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_12} ]"} +proc VAL_PF1_ENTRY_ADDR_13 { PARAM_VALUE.C_PF1_ENTRY_ADDR_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_13} ]"} + +proc VAL_PF1_ENTRY_VERSION_TYPE_0 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_1 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_2 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_3 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_4 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_5 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_6 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_7 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_8 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_9 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_10 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_11 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_12 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_13 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13} ]"} + +proc VAL_PF1_ENTRY_MAJOR_VERSION_0 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_1 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_2 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_3 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_4 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_5 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_6 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_7 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_8 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_9 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_10 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10}]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_11 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11}]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_12 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12}]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_13 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13}]"} + +proc VAL_PF1_ENTRY_MINOR_VERSION_0 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_1 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_2 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_3 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_4 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_5 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_6 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_7 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_8 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_9 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_10 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10}]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_11 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11}]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_12 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12}]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_13 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13}]"} + +proc VAL_PF1_ENTRY_RSVD0_0 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_0} ]"} +proc VAL_PF1_ENTRY_RSVD0_1 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_1} ]"} +proc VAL_PF1_ENTRY_RSVD0_2 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_2} ]"} +proc VAL_PF1_ENTRY_RSVD0_3 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_3} ]"} +proc VAL_PF1_ENTRY_RSVD0_4 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_4} ]"} +proc VAL_PF1_ENTRY_RSVD0_5 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_5} ]"} +proc VAL_PF1_ENTRY_RSVD0_6 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_6} ]"} +proc VAL_PF1_ENTRY_RSVD0_7 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_7} ]"} +proc VAL_PF1_ENTRY_RSVD0_8 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_8} ]"} +proc VAL_PF1_ENTRY_RSVD0_9 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_9} ]"} +proc VAL_PF1_ENTRY_RSVD0_10 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_10} ]"} +proc VAL_PF1_ENTRY_RSVD0_11 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_11} ]"} +proc VAL_PF1_ENTRY_RSVD0_12 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_12} ]"} +proc VAL_PF1_ENTRY_RSVD0_13 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_13} ]"} + +proc VAL_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE { PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE} {return "[get_property value ${PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE}]"} +proc VAL_PF2_BAR_INDEX { PARAM_VALUE.C_PF2_BAR_INDEX } {return "[get_property value ${PARAM_VALUE.C_PF2_BAR_INDEX}]"} +proc VAL_PF2_LOW_OFFSET { PARAM_VALUE.C_PF2_LOW_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF2_LOW_OFFSET}]"} +proc VAL_PF2_HIGH_OFFSET { PARAM_VALUE.C_PF2_HIGH_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF2_HIGH_OFFSET}]"} + +proc VAL_PF2_ENTRY_TYPE_0 { PARAM_VALUE.C_PF2_ENTRY_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_0} ]"} +proc VAL_PF2_ENTRY_TYPE_1 { PARAM_VALUE.C_PF2_ENTRY_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_1} ]"} +proc VAL_PF2_ENTRY_TYPE_2 { PARAM_VALUE.C_PF2_ENTRY_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_2} ]"} +proc VAL_PF2_ENTRY_TYPE_3 { PARAM_VALUE.C_PF2_ENTRY_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_3} ]"} +proc VAL_PF2_ENTRY_TYPE_4 { PARAM_VALUE.C_PF2_ENTRY_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_4} ]"} +proc VAL_PF2_ENTRY_TYPE_5 { PARAM_VALUE.C_PF2_ENTRY_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_5} ]"} +proc VAL_PF2_ENTRY_TYPE_6 { PARAM_VALUE.C_PF2_ENTRY_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_6} ]"} +proc VAL_PF2_ENTRY_TYPE_7 { PARAM_VALUE.C_PF2_ENTRY_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_7} ]"} +proc VAL_PF2_ENTRY_TYPE_8 { PARAM_VALUE.C_PF2_ENTRY_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_8} ]"} +proc VAL_PF2_ENTRY_TYPE_9 { PARAM_VALUE.C_PF2_ENTRY_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_9} ]"} +proc VAL_PF2_ENTRY_TYPE_10 { PARAM_VALUE.C_PF2_ENTRY_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_10}]"} +proc VAL_PF2_ENTRY_TYPE_11 { PARAM_VALUE.C_PF2_ENTRY_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_11}]"} +proc VAL_PF2_ENTRY_TYPE_12 { PARAM_VALUE.C_PF2_ENTRY_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_12}]"} +proc VAL_PF2_ENTRY_TYPE_13 { PARAM_VALUE.C_PF2_ENTRY_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_13}]"} + +proc VAL_PF2_ENTRY_BAR_0 { PARAM_VALUE.C_PF2_ENTRY_BAR_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_0} ]"} +proc VAL_PF2_ENTRY_BAR_1 { PARAM_VALUE.C_PF2_ENTRY_BAR_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_1} ]"} +proc VAL_PF2_ENTRY_BAR_2 { PARAM_VALUE.C_PF2_ENTRY_BAR_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_2} ]"} +proc VAL_PF2_ENTRY_BAR_3 { PARAM_VALUE.C_PF2_ENTRY_BAR_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_3} ]"} +proc VAL_PF2_ENTRY_BAR_4 { PARAM_VALUE.C_PF2_ENTRY_BAR_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_4} ]"} +proc VAL_PF2_ENTRY_BAR_5 { PARAM_VALUE.C_PF2_ENTRY_BAR_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_5} ]"} +proc VAL_PF2_ENTRY_BAR_6 { PARAM_VALUE.C_PF2_ENTRY_BAR_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_6} ]"} +proc VAL_PF2_ENTRY_BAR_7 { PARAM_VALUE.C_PF2_ENTRY_BAR_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_7} ]"} +proc VAL_PF2_ENTRY_BAR_8 { PARAM_VALUE.C_PF2_ENTRY_BAR_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_8} ]"} +proc VAL_PF2_ENTRY_BAR_9 { PARAM_VALUE.C_PF2_ENTRY_BAR_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_9} ]"} +proc VAL_PF2_ENTRY_BAR_10 { PARAM_VALUE.C_PF2_ENTRY_BAR_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_10} ]"} +proc VAL_PF2_ENTRY_BAR_11 { PARAM_VALUE.C_PF2_ENTRY_BAR_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_11} ]"} +proc VAL_PF2_ENTRY_BAR_12 { PARAM_VALUE.C_PF2_ENTRY_BAR_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_12} ]"} +proc VAL_PF2_ENTRY_BAR_13 { PARAM_VALUE.C_PF2_ENTRY_BAR_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_13} ]"} + +proc VAL_PF2_ENTRY_ADDR_0 { PARAM_VALUE.C_PF2_ENTRY_ADDR_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_0} ]"} +proc VAL_PF2_ENTRY_ADDR_1 { PARAM_VALUE.C_PF2_ENTRY_ADDR_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_1} ]"} +proc VAL_PF2_ENTRY_ADDR_2 { PARAM_VALUE.C_PF2_ENTRY_ADDR_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_2} ]"} +proc VAL_PF2_ENTRY_ADDR_3 { PARAM_VALUE.C_PF2_ENTRY_ADDR_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_3} ]"} +proc VAL_PF2_ENTRY_ADDR_4 { PARAM_VALUE.C_PF2_ENTRY_ADDR_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_4} ]"} +proc VAL_PF2_ENTRY_ADDR_5 { PARAM_VALUE.C_PF2_ENTRY_ADDR_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_5} ]"} +proc VAL_PF2_ENTRY_ADDR_6 { PARAM_VALUE.C_PF2_ENTRY_ADDR_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_6} ]"} +proc VAL_PF2_ENTRY_ADDR_7 { PARAM_VALUE.C_PF2_ENTRY_ADDR_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_7} ]"} +proc VAL_PF2_ENTRY_ADDR_8 { PARAM_VALUE.C_PF2_ENTRY_ADDR_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_8} ]"} +proc VAL_PF2_ENTRY_ADDR_9 { PARAM_VALUE.C_PF2_ENTRY_ADDR_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_9} ]"} +proc VAL_PF2_ENTRY_ADDR_10 { PARAM_VALUE.C_PF2_ENTRY_ADDR_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_10} ]"} +proc VAL_PF2_ENTRY_ADDR_11 { PARAM_VALUE.C_PF2_ENTRY_ADDR_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_11} ]"} +proc VAL_PF2_ENTRY_ADDR_12 { PARAM_VALUE.C_PF2_ENTRY_ADDR_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_12} ]"} +proc VAL_PF2_ENTRY_ADDR_13 { PARAM_VALUE.C_PF2_ENTRY_ADDR_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_13} ]"} + +proc VAL_PF2_ENTRY_VERSION_TYPE_0 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_1 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_2 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_3 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_4 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_5 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_6 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_7 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_8 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_9 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_10 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_11 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_12 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_13 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13} ]"} + +proc VAL_PF2_ENTRY_MAJOR_VERSION_0 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_1 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_2 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_3 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_4 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_5 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_6 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_7 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_8 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_9 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_10 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10}]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_11 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11}]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_12 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12}]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_13 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13}]"} + +proc VAL_PF2_ENTRY_MINOR_VERSION_0 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_1 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_2 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_3 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_4 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_5 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_6 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_7 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_8 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_9 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_10 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10}]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_11 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11}]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_12 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12}]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_13 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13}]"} + +proc VAL_PF2_ENTRY_RSVD0_0 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_0} ]"} +proc VAL_PF2_ENTRY_RSVD0_1 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_1} ]"} +proc VAL_PF2_ENTRY_RSVD0_2 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_2} ]"} +proc VAL_PF2_ENTRY_RSVD0_3 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_3} ]"} +proc VAL_PF2_ENTRY_RSVD0_4 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_4} ]"} +proc VAL_PF2_ENTRY_RSVD0_5 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_5} ]"} +proc VAL_PF2_ENTRY_RSVD0_6 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_6} ]"} +proc VAL_PF2_ENTRY_RSVD0_7 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_7} ]"} +proc VAL_PF2_ENTRY_RSVD0_8 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_8} ]"} +proc VAL_PF2_ENTRY_RSVD0_9 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_9} ]"} +proc VAL_PF2_ENTRY_RSVD0_10 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_10} ]"} +proc VAL_PF2_ENTRY_RSVD0_11 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_11} ]"} +proc VAL_PF2_ENTRY_RSVD0_12 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_12} ]"} +proc VAL_PF2_ENTRY_RSVD0_13 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_13} ]"} + +proc VAL_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE { PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE} {return "[get_property value ${PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE}]"} +proc VAL_PF3_BAR_INDEX { PARAM_VALUE.C_PF3_BAR_INDEX } {return "[get_property value ${PARAM_VALUE.C_PF3_BAR_INDEX}]"} +proc VAL_PF3_LOW_OFFSET { PARAM_VALUE.C_PF3_LOW_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF3_LOW_OFFSET}]"} +proc VAL_PF3_HIGH_OFFSET { PARAM_VALUE.C_PF3_HIGH_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF3_HIGH_OFFSET}]"} + +proc VAL_PF3_ENTRY_TYPE_0 { PARAM_VALUE.C_PF3_ENTRY_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_0} ]"} +proc VAL_PF3_ENTRY_TYPE_1 { PARAM_VALUE.C_PF3_ENTRY_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_1} ]"} +proc VAL_PF3_ENTRY_TYPE_2 { PARAM_VALUE.C_PF3_ENTRY_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_2} ]"} +proc VAL_PF3_ENTRY_TYPE_3 { PARAM_VALUE.C_PF3_ENTRY_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_3} ]"} +proc VAL_PF3_ENTRY_TYPE_4 { PARAM_VALUE.C_PF3_ENTRY_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_4} ]"} +proc VAL_PF3_ENTRY_TYPE_5 { PARAM_VALUE.C_PF3_ENTRY_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_5} ]"} +proc VAL_PF3_ENTRY_TYPE_6 { PARAM_VALUE.C_PF3_ENTRY_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_6} ]"} +proc VAL_PF3_ENTRY_TYPE_7 { PARAM_VALUE.C_PF3_ENTRY_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_7} ]"} +proc VAL_PF3_ENTRY_TYPE_8 { PARAM_VALUE.C_PF3_ENTRY_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_8} ]"} +proc VAL_PF3_ENTRY_TYPE_9 { PARAM_VALUE.C_PF3_ENTRY_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_9} ]"} +proc VAL_PF3_ENTRY_TYPE_10 { PARAM_VALUE.C_PF3_ENTRY_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_10}]"} +proc VAL_PF3_ENTRY_TYPE_11 { PARAM_VALUE.C_PF3_ENTRY_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_11}]"} +proc VAL_PF3_ENTRY_TYPE_12 { PARAM_VALUE.C_PF3_ENTRY_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_12}]"} +proc VAL_PF3_ENTRY_TYPE_13 { PARAM_VALUE.C_PF3_ENTRY_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_13}]"} + +proc VAL_PF3_ENTRY_BAR_0 { PARAM_VALUE.C_PF3_ENTRY_BAR_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_0} ]"} +proc VAL_PF3_ENTRY_BAR_1 { PARAM_VALUE.C_PF3_ENTRY_BAR_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_1} ]"} +proc VAL_PF3_ENTRY_BAR_2 { PARAM_VALUE.C_PF3_ENTRY_BAR_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_2} ]"} +proc VAL_PF3_ENTRY_BAR_3 { PARAM_VALUE.C_PF3_ENTRY_BAR_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_3} ]"} +proc VAL_PF3_ENTRY_BAR_4 { PARAM_VALUE.C_PF3_ENTRY_BAR_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_4} ]"} +proc VAL_PF3_ENTRY_BAR_5 { PARAM_VALUE.C_PF3_ENTRY_BAR_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_5} ]"} +proc VAL_PF3_ENTRY_BAR_6 { PARAM_VALUE.C_PF3_ENTRY_BAR_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_6} ]"} +proc VAL_PF3_ENTRY_BAR_7 { PARAM_VALUE.C_PF3_ENTRY_BAR_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_7} ]"} +proc VAL_PF3_ENTRY_BAR_8 { PARAM_VALUE.C_PF3_ENTRY_BAR_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_8} ]"} +proc VAL_PF3_ENTRY_BAR_9 { PARAM_VALUE.C_PF3_ENTRY_BAR_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_9} ]"} +proc VAL_PF3_ENTRY_BAR_10 { PARAM_VALUE.C_PF3_ENTRY_BAR_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_10} ]"} +proc VAL_PF3_ENTRY_BAR_11 { PARAM_VALUE.C_PF3_ENTRY_BAR_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_11} ]"} +proc VAL_PF3_ENTRY_BAR_12 { PARAM_VALUE.C_PF3_ENTRY_BAR_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_12} ]"} +proc VAL_PF3_ENTRY_BAR_13 { PARAM_VALUE.C_PF3_ENTRY_BAR_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_13} ]"} + +proc VAL_PF3_ENTRY_ADDR_0 { PARAM_VALUE.C_PF3_ENTRY_ADDR_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_0} ]"} +proc VAL_PF3_ENTRY_ADDR_1 { PARAM_VALUE.C_PF3_ENTRY_ADDR_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_1} ]"} +proc VAL_PF3_ENTRY_ADDR_2 { PARAM_VALUE.C_PF3_ENTRY_ADDR_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_2} ]"} +proc VAL_PF3_ENTRY_ADDR_3 { PARAM_VALUE.C_PF3_ENTRY_ADDR_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_3} ]"} +proc VAL_PF3_ENTRY_ADDR_4 { PARAM_VALUE.C_PF3_ENTRY_ADDR_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_4} ]"} +proc VAL_PF3_ENTRY_ADDR_5 { PARAM_VALUE.C_PF3_ENTRY_ADDR_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_5} ]"} +proc VAL_PF3_ENTRY_ADDR_6 { PARAM_VALUE.C_PF3_ENTRY_ADDR_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_6} ]"} +proc VAL_PF3_ENTRY_ADDR_7 { PARAM_VALUE.C_PF3_ENTRY_ADDR_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_7} ]"} +proc VAL_PF3_ENTRY_ADDR_8 { PARAM_VALUE.C_PF3_ENTRY_ADDR_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_8} ]"} +proc VAL_PF3_ENTRY_ADDR_9 { PARAM_VALUE.C_PF3_ENTRY_ADDR_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_9} ]"} +proc VAL_PF3_ENTRY_ADDR_10 { PARAM_VALUE.C_PF3_ENTRY_ADDR_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_10} ]"} +proc VAL_PF3_ENTRY_ADDR_11 { PARAM_VALUE.C_PF3_ENTRY_ADDR_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_11} ]"} +proc VAL_PF3_ENTRY_ADDR_12 { PARAM_VALUE.C_PF3_ENTRY_ADDR_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_12} ]"} +proc VAL_PF3_ENTRY_ADDR_13 { PARAM_VALUE.C_PF3_ENTRY_ADDR_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_13} ]"} + +proc VAL_PF3_ENTRY_VERSION_TYPE_0 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_1 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_2 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_3 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_4 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_5 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_6 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_7 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_8 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_9 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_10 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_11 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_12 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_13 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13} ]"} + +proc VAL_PF3_ENTRY_MAJOR_VERSION_0 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_1 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_2 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_3 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_4 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_5 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_6 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_7 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_8 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_9 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_10 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10}]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_11 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11}]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_12 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12}]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_13 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13}]"} + +proc VAL_PF3_ENTRY_MINOR_VERSION_0 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_1 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_2 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_3 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_4 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_5 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_6 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_7 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_8 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_9 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_10 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10}]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_11 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11}]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_12 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12}]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_13 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13}]"} + +proc VAL_PF3_ENTRY_RSVD0_0 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_0} ]"} +proc VAL_PF3_ENTRY_RSVD0_1 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_1} ]"} +proc VAL_PF3_ENTRY_RSVD0_2 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_2} ]"} +proc VAL_PF3_ENTRY_RSVD0_3 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_3} ]"} +proc VAL_PF3_ENTRY_RSVD0_4 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_4} ]"} +proc VAL_PF3_ENTRY_RSVD0_5 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_5} ]"} +proc VAL_PF3_ENTRY_RSVD0_6 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_6} ]"} +proc VAL_PF3_ENTRY_RSVD0_7 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_7} ]"} +proc VAL_PF3_ENTRY_RSVD0_8 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_8} ]"} +proc VAL_PF3_ENTRY_RSVD0_9 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_9} ]"} +proc VAL_PF3_ENTRY_RSVD0_10 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_10} ]"} +proc VAL_PF3_ENTRY_RSVD0_11 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_11} ]"} +proc VAL_PF3_ENTRY_RSVD0_12 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_12} ]"} +proc VAL_PF3_ENTRY_RSVD0_13 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_13} ]"} + +proc update_gui_for_PARAM_VALUE.C_NUM_PFS {IPINST PARAM_VALUE.C_NUM_PFS PARAM_VALUE.C_MANUAL} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + set manual [get_property value ${PARAM_VALUE.C_MANUAL}] + if {$manual == 1} { + set_property visible true [ipgui::get_pagespec -name "PF0 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF0 Configuration" -of $IPINST] + } + if {$manual == 1 && $num_pfs > 1} { + set_property visible true [ipgui::get_pagespec -name "PF1 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF1 Configuration" -of $IPINST] + } + if {$manual == 1 && $num_pfs > 2} { + set_property visible true [ipgui::get_pagespec -name "PF2 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF2 Configuration" -of $IPINST] + } + if {$manual == 1 && $num_pfs > 3} { + set_property visible true [ipgui::get_pagespec -name "PF3 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF3 Configuration" -of $IPINST] + } + + if {$manual == 0} { + set_property visible true [ipgui::get_pagespec -name "PF0 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF0 Values" -of $IPINST] + } + if {$manual == 0 && $num_pfs > 1} { + set_property visible true [ipgui::get_pagespec -name "PF1 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF1 Values" -of $IPINST] + } + if {$manual == 0 && $num_pfs > 2} { + set_property visible true [ipgui::get_pagespec -name "PF2 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF2 Values" -of $IPINST] + } + if {$manual == 0 && $num_pfs > 3} { + set_property visible true [ipgui::get_pagespec -name "PF3 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF3 Values" -of $IPINST] + } +} + +proc update_gui_for_PARAM_VALUE.C_MANUAL {IPINST PARAM_VALUE.C_NUM_PFS PARAM_VALUE.C_MANUAL} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + set manual [get_property value ${PARAM_VALUE.C_MANUAL}] + if {$manual == 1} { + set_property visible true [ipgui::get_pagespec -name "PF0 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF0 Configuration" -of $IPINST] + } + if {$manual == 1 && $num_pfs > 1} { + set_property visible true [ipgui::get_pagespec -name "PF1 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF1 Configuration" -of $IPINST] + } + if {$manual == 1 && $num_pfs > 2} { + set_property visible true [ipgui::get_pagespec -name "PF2 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF2 Configuration" -of $IPINST] + } + if {$manual == 1 && $num_pfs > 3} { + set_property visible true [ipgui::get_pagespec -name "PF3 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF3 Configuration" -of $IPINST] + } + + if {$manual == 0} { + set_property visible true [ipgui::get_pagespec -name "PF0 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF0 Values" -of $IPINST] + } + if {$manual == 0 && $num_pfs > 1} { + set_property visible true [ipgui::get_pagespec -name "PF1 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF1 Values" -of $IPINST] + } + if {$manual == 0 && $num_pfs > 2} { + set_property visible true [ipgui::get_pagespec -name "PF2 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF2 Values" -of $IPINST] + } + if {$manual == 0 && $num_pfs > 3} { + set_property visible true [ipgui::get_pagespec -name "PF3 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF3 Values" -of $IPINST] + } +} + +proc update_gui_for_PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE {IPINST PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set pf0_num_slots [get_property value ${PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE}] + if {$pf0_num_slots > 1} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 1 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 1 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 1 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 1 Values" -of $IPINST] + } + if {$pf0_num_slots > 2} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 2 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 2 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 2 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 2 Values" -of $IPINST] + } + if {$pf0_num_slots > 3} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 3 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 3 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 3 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 3 Values" -of $IPINST] + } + if {$pf0_num_slots > 4} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 4 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 4 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 4 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 4 Values" -of $IPINST] + } + if {$pf0_num_slots > 5} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 5 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 5 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 5 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 5 Values" -of $IPINST] + } + if {$pf0_num_slots > 6} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 6 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 6 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 6 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 6 Values" -of $IPINST] + } + if {$pf0_num_slots > 7} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 7 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 7 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 7 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 7 Values" -of $IPINST] + } + if {$pf0_num_slots > 8} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 8 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 8 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 8 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 8 Values" -of $IPINST] + } + if {$pf0_num_slots > 9} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 9 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 9 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 9 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 9 Values" -of $IPINST] + } + if {$pf0_num_slots > 10} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 10 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 10 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 10 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 10 Values" -of $IPINST] + } + if {$pf0_num_slots > 11} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 11 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 11 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 11 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 11 Values" -of $IPINST] + } + if {$pf0_num_slots > 12} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 12 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 12 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 12 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 12 Values" -of $IPINST] + } + if {$pf0_num_slots > 13} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 13 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 13 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 13 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 13 Values" -of $IPINST] + } +} + +proc update_gui_for_PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE {IPINST PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set pf1_num_slots [get_property value ${PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE}] + if {$pf1_num_slots > 1} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 1 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 1 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 1 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 1 Values" -of $IPINST] + } + if {$pf1_num_slots > 2} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 2 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 2 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 2 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 2 Values" -of $IPINST] + } + if {$pf1_num_slots > 3} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 3 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 3 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 3 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 3 Values" -of $IPINST] + } + if {$pf1_num_slots > 4} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 4 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 4 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 4 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 4 Values" -of $IPINST] + } + if {$pf1_num_slots > 5} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 5 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 5 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 5 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 5 Values" -of $IPINST] + } + if {$pf1_num_slots > 6} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 6 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 6 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 6 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 6 Values" -of $IPINST] + } + if {$pf1_num_slots > 7} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 7 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 7 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 7 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 7 Values" -of $IPINST] + } + if {$pf1_num_slots > 8} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 8 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 8 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 8 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 8 Values" -of $IPINST] + } + if {$pf1_num_slots > 9} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 9 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 9 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 9 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 9 Values" -of $IPINST] + } + if {$pf1_num_slots > 10} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 10 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 10 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 10 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 10 Values" -of $IPINST] + } + if {$pf1_num_slots > 11} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 11 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 11 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 11 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 11 Values" -of $IPINST] + } + if {$pf1_num_slots > 12} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 12 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 12 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 12 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 12 Values" -of $IPINST] + } + if {$pf1_num_slots > 13} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 13 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 13 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 13 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 13 Values" -of $IPINST] + } +} + +proc update_gui_for_PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE {IPINST PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set pf2_num_slots [get_property value ${PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE}] + if {$pf2_num_slots > 1} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 1 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 1 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 1 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 1 Values" -of $IPINST] + } + if {$pf2_num_slots > 2} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 2 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 2 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 2 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 2 Values" -of $IPINST] + } + if {$pf2_num_slots > 3} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 3 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 3 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 3 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 3 Values" -of $IPINST] + } + if {$pf2_num_slots > 4} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 4 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 4 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 4 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 4 Values" -of $IPINST] + } + if {$pf2_num_slots > 5} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 5 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 5 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 5 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 5 Values" -of $IPINST] + } + if {$pf2_num_slots > 6} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 6 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 6 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 6 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 6 Values" -of $IPINST] + } + if {$pf2_num_slots > 7} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 7 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 7 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 7 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 7 Values" -of $IPINST] + } + if {$pf2_num_slots > 8} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 8 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 8 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 8 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 8 Values" -of $IPINST] + } + if {$pf2_num_slots > 9} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 9 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 9 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 9 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 9 Values" -of $IPINST] + } + if {$pf2_num_slots > 10} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 10 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 10 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 10 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 10 Values" -of $IPINST] + } + if {$pf2_num_slots > 11} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 11 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 11 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 11 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 11 Values" -of $IPINST] + } + if {$pf2_num_slots > 12} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 12 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 12 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 12 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 12 Values" -of $IPINST] + } + if {$pf2_num_slots > 13} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 13 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 13 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 13 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 13 Values" -of $IPINST] + } +} + +proc update_gui_for_PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE {IPINST PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set pf3_num_slots [get_property value ${PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE}] + if {$pf3_num_slots > 1} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 1 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 1 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 1 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 1 Values" -of $IPINST] + } + if {$pf3_num_slots > 2} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 2 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 2 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 2 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 2 Values" -of $IPINST] + } + if {$pf3_num_slots > 3} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 3 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 3 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 3 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 3 Values" -of $IPINST] + } + if {$pf3_num_slots > 4} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 4 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 4 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 4 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 4 Values" -of $IPINST] + } + if {$pf3_num_slots > 5} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 5 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 5 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 5 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 5 Values" -of $IPINST] + } + if {$pf3_num_slots > 6} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 6 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 6 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 6 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 6 Values" -of $IPINST] + } + if {$pf3_num_slots > 7} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 7 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 7 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 7 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 7 Values" -of $IPINST] + } + if {$pf3_num_slots > 8} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 8 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 8 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 8 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 8 Values" -of $IPINST] + } + if {$pf3_num_slots > 9} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 9 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 9 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 9 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 9 Values" -of $IPINST] + } + if {$pf3_num_slots > 10} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 10 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 10 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 10 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 10 Values" -of $IPINST] + } + if {$pf3_num_slots > 11} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 11 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 11 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 11 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 11 Values" -of $IPINST] + } + if {$pf3_num_slots > 12} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 12 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 12 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 12 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 12 Values" -of $IPINST] + } + if {$pf3_num_slots > 13} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 13 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 13 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 13 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 13 Values" -of $IPINST] + } +} + diff --git a/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/bd/bd.tcl b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/bd/bd.tcl new file mode 100644 index 00000000..76b1672e --- /dev/null +++ b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/bd/bd.tcl @@ -0,0 +1,34 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +#==============================================================================# +# Post IP Configuration Procedure +#==============================================================================# + +proc post_config_ip { cell args } { + set ip [get_bd_cells $cell] + set s_axi_intf [get_bd_intf_pins $ip/S_AXI] + + # Set interface as READ_ONLY + set_property CONFIG.READ_WRITE_MODE READ_ONLY $s_axi_intf + set_property CONFIG.READ_WRITE_MODE.VALUE_SRC CONSTANT $s_axi_intf + +} diff --git a/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/component.xml b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/component.xml new file mode 100644 index 00000000..7aee78d6 --- /dev/null +++ b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/component.xml @@ -0,0 +1,530 @@ + + + xilinx.com + ip + shell_utils_uuid_rom + 2.0 + + + S_AXI + + + + + + + + + ARADDR + + + S_AXI_ARADDR + + + + + ARREADY + + + S_AXI_ARREADY + + + + + ARVALID + + + S_AXI_ARVALID + + + + + RDATA + + + S_AXI_RDATA + + + + + RREADY + + + S_AXI_RREADY + + + + + RRESP + + + S_AXI_RRESP + + + + + RVALID + + + S_AXI_RVALID + + + + + + S_AXI_signal_reset + + + + + + + RST + + + S_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + S_AXI_signal_clock + + + + + + + CLK + + + S_AXI_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI + + + ASSOCIATED_RESET + S_AXI_ARESETN + + + FREQ_HZ + 250000000 + + + + + + + S_AXI + + reg0 + 0 + 16 + 32 + register + + + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + viewChecksum + 83d8451f + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + d40d867a + + + + + xilinx_miscfiles + Miscellaneous + :vivado.xilinx.com:misc.files + + xilinx_miscfiles_view_fileset + + + + viewChecksum + a3b49e2c + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + d40ac7ba + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + shell_utils_uuid_rom + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 5f2ab460 + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + shell_utils_uuid_rom + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 5f2ab460 + + + + + + + S_AXI_ACLK + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXI_ARESETN + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + S_AXI_ARADDR + + in + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + S_AXI_ARVALID + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + S_AXI_ARREADY + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXI_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXI_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXI_RVALID + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXI_RREADY + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + + C_S_AXI_DATA_WIDTH + 32 + + + C_S_AXI_ADDR_WIDTH + 4 + + + C_MEMORY_INIT + 0 + + + C_XDEVICEFAMILY + no_family + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_xpgui_view_fileset + + xgui/shell_utils_uuid_rom_v2_0.tcl + tclSource + XGUI_VERSION_2 + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_miscfiles_view_fileset + + yml/uuid_rom_csr_reg.yml + unknown + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_utilityxitfiles_view_fileset + + tcl/update_uuid_rom.tcl + tclSource + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_versioninformation_view_fileset + + doc/shell_utils_uuid_rom_v2_0_changelog.txt + text + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/shell_utils_uuid_rom_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/shell_utils_uuid_rom_v2_0_vh_rfs.vhd + vhdlSource + CHECKSUM_5f2ab460 + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + + + + + + + + Shell Utility UUID ROM + + + Component_Name + shell_utils_uuid_rom_v2_0 + + + C_INITIAL_UUID + UUID initialization value (128-bit hex string) + 00000000000000000000000000000000 + + + + + + /Shell_Subsystems + + Shell Utility UUID ROM + level_2 + + XPM_MEMORY + + http://www.xilinx.com + 0 + 2023-10-11T08:40:40Z + + + 2023.1 + + + + + + + + + diff --git a/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/doc/shell_utils_uuid_rom_v2_0_changelog.txt b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/doc/shell_utils_uuid_rom_v2_0_changelog.txt new file mode 100644 index 00000000..f123aada --- /dev/null +++ b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/doc/shell_utils_uuid_rom_v2_0_changelog.txt @@ -0,0 +1,84 @@ +2023.1: + * Version 2.0 + * No changes + +2022.2.2: + * Version 2.0 + * No changes + +2022.2.1: + * Version 2.0 + * No changes + +2022.2: + * Version 2.0 + * No changes + +2022.1.2: + * Version 2.0 + * No changes + +2022.1.1: + * Version 2.0 + * No changes + +2022.1: + * Version 2.0 + * No changes + +2021.2.2: + * Version 2.0 + * No changes + +2021.2.1: + * Version 2.0 + * No changes + +2021.2: + * Version 2.0 + * No changes + +2021.1.1: + * Version 2.0 + * No changes + +2021.1: + * Version 2.0 + * No changes + +2020.3: + * Version 2.0 + * No changes + +2020.2.2: + * Version 2.0 + * No changes + +2020.2.1: + * Version 2.0 + * No changes + +2020.2: + * Version 2.0 + * No changes + +2020.1.1: + * Version 2.0 + * No changes + +2020.1: + * Version 2.0 + * S_AXI interface supports READ_ONLY, updates to work with 2020.1 tools + +2019.2.2: + * Version 1.0 + * No changes + +2019.2.1: + * Version 1.0 + * No changes + +2019.2: + * Version 1.0 + * Initial Release + diff --git a/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/hdl/shell_utils_uuid_rom_v2_0_vh_rfs.vhd b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/hdl/shell_utils_uuid_rom_v2_0_vh_rfs.vhd new file mode 100644 index 00000000..02dfb4db --- /dev/null +++ b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/hdl/shell_utils_uuid_rom_v2_0_vh_rfs.vhd @@ -0,0 +1,209 @@ +-- (c) Copyright 2022, Advanced Micro Devices, Inc. +-- +-- Permission is hereby granted, free of charge, to any person obtaining a +-- copy of this software and associated documentation files (the "Software"), +-- to deal in the Software without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Software, and to permit persons to whom the +-- Software is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Software. +-- +-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +-- DEALINGS IN THE SOFTWARE. +------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + +library axi_lite_ipif_v3_0_4; + use axi_lite_ipif_v3_0_4.ipif_pkg.all; + +library xpm; + use xpm.vcomponents.all; + +entity shell_utils_uuid_rom is + generic ( + ------------------------------------------------------------------------ + C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_S_AXI_ADDR_WIDTH : integer range 3 to 9 := 4; + C_MEMORY_INIT : string := "0"; + C_XDEVICEFAMILY : string := "no_family" + ------------------------------------------------------------------------ + ); + port ( + ------------------------------------------------------------------------ + -- Processor AXI Interface + ------------------------------------------------------------------------ + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic + ); + +end shell_utils_uuid_rom; + +architecture rtl of shell_utils_uuid_rom is + + ------------------------------------------------------------------------------- + -- Constant Declarations + ------------------------------------------------------------------------------- + + -- Constants for AXI4-Lite. + constant ZEROES : std_logic_vector(0 to 31) := (others => '0'); + constant ONES : std_logic_vector(0 to 31) := (others => '1'); + + constant C_FAMILY : string := C_XDEVICEFAMILY; + + constant REG_BASEADDR : std_logic_vector := X"00000000"; + + impure function makemask (Width: INTEGER) return std_logic_vector is + variable retv: std_logic_vector (31 downto 0) := (others => '0'); + begin + for i in (Width - 1) downto 0 loop + retv(i) := '1'; + end loop; + return retv; + end function; + + constant REG_HIGHADDR : std_logic_vector(0 to 31) := makemask(C_S_AXI_ADDR_WIDTH); + + constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( + ZEROES(0 to 31) & REG_BASEADDR, + ZEROES(0 to 31) & REG_HIGHADDR + ); + + constant C_ARD_IDX_REGS : integer := 0; + + constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( + C_ARD_IDX_REGS => 1 + ); + + constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) := makemask(C_S_AXI_ADDR_WIDTH); + + constant C_USE_WSTRB : integer := 0; + + constant C_DPHASE_TIMEOUT : integer := 3; + + constant XPM_ADDR_WIDTH : integer := C_S_AXI_ADDR_WIDTH - 2; + constant XPM_MEMORY_SIZE : integer := (2 ** XPM_ADDR_WIDTH) * C_S_AXI_DATA_WIDTH; + + attribute DONT_TOUCH : string; + attribute DONT_TOUCH of xpm_memory_spram_inst: label is "TRUE"; + + ------------------------------------------------------------------------------- + -- SIGNALS + ------------------------------------------------------------------------------- + signal Bus2IP_Clk : std_logic := '0'; + signal Bus2IP_Resetn : std_logic; + signal Bus2IP_Addr : std_logic_vector((C_S_AXI_ADDR_WIDTH - 1) downto 0); + signal Bus2IP_RNW : std_logic; + signal Bus2IP_BE : std_logic_vector(((C_S_AXI_DATA_WIDTH / 8) - 1) downto 0); + signal Bus2IP_CS : std_logic_vector(((C_ARD_ADDR_RANGE_ARRAY'length) / 2 - 1) downto 0); + signal Bus2IP_RdCE : std_logic_vector((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); + signal Bus2IP_WrCE : std_logic_vector((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); + signal Bus2IP_Data : std_logic_vector((C_S_AXI_DATA_WIDTH - 1) downto 0); + signal IP2Bus_Data : std_logic_vector((C_S_AXI_DATA_WIDTH - 1) downto 0); + signal IP2Bus_WrAck : std_logic := '0'; + signal IP2Bus_RdAck : std_logic := '0'; + signal IP2Bus_Error : std_logic := '0'; + +begin + +axi_lite_ipif_1 : entity axi_lite_ipif_v3_0_4.axi_lite_ipif + generic map( + C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, + C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, + C_USE_WSTRB => C_USE_WSTRB, + C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, + C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, + C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, + C_FAMILY => C_FAMILY) + port map( + S_AXI_ACLK => S_AXI_ACLK, + S_AXI_ARESETN => S_AXI_ARESETN, + S_AXI_AWADDR => (others => '0'), + S_AXI_AWVALID => '0', + S_AXI_AWREADY => open, + S_AXI_WDATA => (others => '0'), + S_AXI_WSTRB => (others => '0'), + S_AXI_WVALID => '0', + S_AXI_WREADY => open, + S_AXI_BRESP => open, + S_AXI_BVALID => open, + S_AXI_BREADY => '0', + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + Bus2IP_Clk => Bus2IP_Clk, + Bus2IP_Resetn => Bus2IP_Resetn, + Bus2IP_Addr => Bus2IP_Addr, + Bus2IP_RNW => Bus2IP_RNW, + Bus2IP_BE => Bus2IP_BE, + Bus2IP_CS => Bus2IP_CS, + Bus2IP_RdCE => Bus2IP_RdCE, + Bus2IP_WrCE => Bus2IP_WrCE, + Bus2IP_Data => Bus2IP_Data, + IP2Bus_Data => IP2Bus_Data, + IP2Bus_WrAck => IP2Bus_WrAck, + IP2Bus_RdAck => IP2Bus_RdAck, + IP2Bus_Error => IP2Bus_Error); + +xpm_memory_spram_inst : xpm_memory_spram + generic map ( + ADDR_WIDTH_A => XPM_ADDR_WIDTH, + AUTO_SLEEP_TIME => 0, + BYTE_WRITE_WIDTH_A => C_S_AXI_DATA_WIDTH, + CASCADE_HEIGHT => 0, + ECC_MODE => "no_ecc", + MEMORY_INIT_FILE => "none", + MEMORY_INIT_PARAM => C_MEMORY_INIT, + MEMORY_OPTIMIZATION => "true", + MEMORY_PRIMITIVE => "distributed", + MEMORY_SIZE => XPM_MEMORY_SIZE, + MESSAGE_CONTROL => 0, + READ_DATA_WIDTH_A => C_S_AXI_DATA_WIDTH, + READ_LATENCY_A => 1, + READ_RESET_VALUE_A => "0", + RST_MODE_A => "SYNC", + SIM_ASSERT_CHK => 0, + USE_MEM_INIT => 1, + WAKEUP_TIME => "disable_sleep", + WRITE_DATA_WIDTH_A => C_S_AXI_DATA_WIDTH, + WRITE_MODE_A => "read_first" + ) + port map ( + dbiterra => open, + douta => IP2Bus_Data, + sbiterra => open, + addra => Bus2IP_Addr(C_S_AXI_ADDR_WIDTH-1 downto 2), + clka => Bus2IP_Clk, + ena => Bus2IP_CS(0), + injectdbiterra => '0', + injectsbiterra => '0', + regcea => '0', + rsta => '0', + sleep => '0', + wea => Bus2IP_WrCE(0 downto 0), + dina => Bus2IP_Data + ); + +end architecture rtl; + + diff --git a/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/tcl/update_uuid_rom.tcl b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/tcl/update_uuid_rom.tcl new file mode 100644 index 00000000..54fa2194 --- /dev/null +++ b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/tcl/update_uuid_rom.tcl @@ -0,0 +1,231 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +proc conv_hex_bin { s } { + binary scan [binary format H* $s] B* x + return $x +} + +proc conv_bin_hex { s } { + binary scan [binary format B4 $s] H1 x + return $x +} + +proc update_uuid_rom {uuid cell} { + + puts "\nINFO: Updaing UUID ROM with UUID: ${uuid}" + puts "INFO: Updating UUID ROM cell: ${cell}\n" + + # validate UUID format + if {![string is xdigit ${uuid}]} { + + puts "ERROR: UUID should be a 128 bit hex value" + puts " Found ${uuid}" + puts "Aborting UUID update" + return 1 + + } + + # validate UUID length + set uuid_length [string length ${uuid}] + + if {${uuid_length} != 32} { + + puts "ERROR: UUID should be 128 bits. Found [expr 4 * ${uuid_length}] bits" + puts " ${uuid}" + puts "Aborting UUID update" + return 1 + + } + + # validate cell name + if {[get_cells -quiet ${cell}] eq ""} { + + puts "ERROR: Specified UUID cell does not exist in the design" + puts " ${cell}" + puts "Aborting UUID update" + return 1 + + } + + # get path to base of the UUID memory element + set filter "PRIMITIVE_TYPE == CLB.LUTRAM.RAM32X1S && PRIMITIVE_LEVEL == \"MACRO\" && NAME =~ ${cell}*0_0" + set uuid_rom_cell_base [string trimright [get_cells -hierarchical -filter ${filter}] 0_] + + if {${uuid_rom_cell_base} eq ""} { + + puts "ERROR: Correct UUID ROM structure not detected. Please check the CLB.LUTRAM.RAM32X1S memory elements exist in the implemented design" + puts "Aborting UUID update" + return 1 + + } + + # split uuid into 4x32 bit hex strings + set uuid_split_hex {} + for {set i 0} {$i < 4} {incr i} { + lappend uuid_split_hex [string range ${uuid} [expr 8 * ${i}] [expr (8 * ${i}) + 7 ]] + } + + + # convert to 4x32 bit binary strings + set uuid_split_bin {} + foreach uuid_split_hex_item ${uuid_split_hex} { + + lappend uuid_split_bin [conv_hex_bin ${uuid_split_hex_item}] + + } + + # produce the muxed 32x4 bit binary string from the input 4x32 bit string + set uuid_muxed_bin {} + for {set j 0} {$j < 32} {incr j} { + + set temp "" + for {set k 0} {$k < 4} {incr k} { + + append temp [string index [lindex ${uuid_split_bin} $k] [expr 31 - $j]] + + } + lappend uuid_muxed_bin ${temp} + } + + # convert to 32x4 bit hex strings + set uuid_muxed_hex {} + foreach uuid_muxed_bin_item ${uuid_muxed_bin} { + + lappend uuid_muxed_hex [conv_bin_hex ${uuid_muxed_bin_item}] + + } + + #puts "DEBUG: UUID length (chars): ${uuid_length}" + #puts "DEBUG: UUID split (hex): ${uuid_split_hex}" + #puts "DEBUG: UUID split (bin): ${uuid_split_bin}" + #puts "DEBUG: UUID muxed (bin): ${uuid_muxed_bin}" + #puts "DEBUG: UUID muxed (hex): ${uuid_muxed_hex}" + #puts "DEBUG: UUID cell base: ${uuid_rom_cell_base}" + + # update INIT properties on the UUID ROM sub-memories + set m 0 + foreach uuid_muxed_hex_item ${uuid_muxed_hex} { + + set uuid_rom_sub_cell [get_cells ${uuid_rom_cell_base}_${m}_${m}] + if {${uuid_rom_sub_cell} eq ""} { + + puts "ERROR: UUID ROM sub-cell not found. Please check it exists in the implemented design" + puts " ${uuid_rom_cell_base}_${m}_${m}" + puts "Aborting UUID update" + return 1 + + } + + puts "INFO: Setting INIT=000000${uuid_muxed_hex_item} on cell ${uuid_rom_sub_cell}" + set_property INIT 32'h00000000${uuid_muxed_hex_item} ${uuid_rom_sub_cell} + incr m + + } + puts "\nINFO: UUID ROM successfully updated\n" + return 0 + +} + +proc read_uuid_rom {cell} { + + puts "\nINFO: Reading UUID ROM cell: ${cell}\n" + + # validate cell name + if {[get_cells -quiet ${cell}] eq ""} { + + puts "ERROR: Specified UUID cell does not exist in the design" + puts " ${cell}" + puts "Aborting UUID read" + return -code error "ERROR: Specified UUID cell does not exist in the design" + + } + + # get path to base of the UUID memory element + set filter "PRIMITIVE_TYPE == CLB.LUTRAM.RAM32X1S && PRIMITIVE_LEVEL == \"MACRO\" && NAME =~ ${cell}*0_0" + set uuid_rom_cell_base [string trimright [get_cells -hierarchical -filter ${filter}] 0_] + + if {${uuid_rom_cell_base} eq ""} { + + puts "ERROR: Correct UUID ROM structure not detected. Please check the CLB.LUTRAM.RAM32X1S memory elements exist in the implemented design" + puts "Aborting UUID read" + return -code error "ERROR: Correct UUID ROM structure not detected. Please check the CLB.LUTRAM.RAM32X1S memory elements exist in the implemented design" + + } + + # read INIT properties from the UUID ROM sub-memories + for {set i 0} {$i < 32} {incr i} { + + set uuid_rom_sub_cell [get_cells ${uuid_rom_cell_base}_${i}_${i}] + if {${uuid_rom_sub_cell} eq ""} { + + puts "ERROR: UUID ROM sub-cell not found. Please check it exists in the implemented design" + puts " ${uuid_rom_cell_base}_${i}_${i}" + puts "Aborting UUID read" + return -code error "ERROR: UUID ROM sub-cell not found. Please check it exists in the implemented design" + + } + + set sub_cell_init [get_property INIT ${uuid_rom_sub_cell}] + puts "INFO: Read INIT=${sub_cell_init} on cell ${uuid_rom_sub_cell}" + lappend uuid_inits $sub_cell_init + + } + + # construct the binary representation of each dword + for {set i 0} {$i < 32} {incr i} { + + set hex_per_bit [string range [lindex $uuid_inits $i] 10 11] + set bin_per_bit [conv_hex_bin $hex_per_bit] + + lappend dw0 [string index $bin_per_bit 7] + lappend dw1 [string index $bin_per_bit 6] + lappend dw2 [string index $bin_per_bit 5] + lappend dw3 [string index $bin_per_bit 4] + + } + + lappend bin_dwords $dw3 $dw2 $dw1 $dw0 + + # construct the hex representation of each dword - bit slice and rotate + foreach dword $bin_dwords { + set dw_hex "" + for {set i 7} {$i >= 0} {incr i -1} { + set nibble "" + for {set j 3} {$j >= 0} {incr j -1} { + append nibble [lindex $dword [expr $i * 4 + $j]] + } + append dw_hex [conv_bin_hex $nibble] + } + lappend hex_dwords $dw_hex + } + + # construct the final hex representation of the full UUID + set uuid "" + foreach dword $hex_dwords { + append uuid $dword + } + + puts "\nINFO: Read UUID ROM value: ${uuid}\n" + + return $uuid + +} diff --git a/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/xgui/shell_utils_uuid_rom_v2_0.tcl b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/xgui/shell_utils_uuid_rom_v2_0.tcl new file mode 100644 index 00000000..5f3a70b7 --- /dev/null +++ b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/xgui/shell_utils_uuid_rom_v2_0.tcl @@ -0,0 +1,114 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +# Definitional proc to organize widgets for parameters. + +proc init_gui { IPINST } { + + ipgui::add_param $IPINST -name "Component_Name" + + #---> Adding Page -----------------------------------------------------------------------------------------------------------------------# + + set General_Config [ipgui::add_page $IPINST -name "General Configuration"] + + set C_INITIAL_UUID [ipgui::add_param $IPINST -name C_INITIAL_UUID -parent $General_Config] + set_property tooltip "Set a default 128-bit UUID to be initialized in the ROM during synthesis" $C_INITIAL_UUID + +} + +#==========================================================================================================================================# +# Parameter Validation Procedures +#==========================================================================================================================================# + +# Validate the entered UUID + +proc validate_PARAM_VALUE.C_INITIAL_UUID {PARAM_VALUE.C_INITIAL_UUID IPINST} { + + # Verify the UUID string is 32 characters in length + set uuid_length [string length [get_property value ${PARAM_VALUE.C_INITIAL_UUID}]] + + if {[expr $uuid_length != 32]} { + set_property errmsg "UUID string length of $uuid_length is not equal to 32" [ipgui::get_paramspec -name C_INITIAL_UUID -of $IPINST ] + return false + } + + # Verify the UUID string is valid hexadecimal + return [RangeCheck4HexDec C_INITIAL_UUID [get_property value ${PARAM_VALUE.C_INITIAL_UUID}] 00000000000000000000000000000000 FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF $IPINST] + +} + +#==========================================================================================================================================# +# Parameter Update Procedures +#==========================================================================================================================================# + +proc update_MODELPARAM_VALUE.C_MEMORY_INIT { MODELPARAM_VALUE.C_MEMORY_INIT PARAM_VALUE.C_INITIAL_UUID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + + set uuid "" + set uuid_chars [split [get_property value ${PARAM_VALUE.C_INITIAL_UUID}] {}] + + # Split the UUID into dword's and rotate to match the XPM_MEM string init format + for {set dw 3} {$dw >= 0} {incr dw -1} { + set dword "" + for {set n 0} {$n < 8} {incr n} { + append dword [lindex $uuid_chars [expr $dw * 8 + $n]] + } + if {[expr $dw == 3]} { + append uuid $dword + } else { + append uuid "," $dword + } + } + set_property value $uuid ${MODELPARAM_VALUE.C_MEMORY_INIT} + +} + +#==========================================================================================================================================# +# Helper Procedures +#==========================================================================================================================================# + +# Proc to validate that the entered Hex string value is within the correct range +proc RangeCheck4HexDec {param paramValue MinValue MaxValue IPINST} { + + if { [regexp -all {[a-fA-F0-9]} $paramValue] != [ string length $paramValue ]} { + + set_property errmsg "Entered invalid Hexadecimal value $paramValue" [ipgui::get_paramspec -name $param -of $IPINST ] + return false + + } + + if {$paramValue == ""} { + + set_property errmsg "Entered invalid Hexadecimal value $paramValue" [ipgui::get_paramspec -name $param -of $IPINST ] + return false + + } + + if {[expr 0x$MaxValue ] < [expr 0x$paramValue ] || [expr 0x$paramValue ] < [expr 0x$MinValue]} { + + set_property errmsg "Entered Hexadecimal value $paramValue is out of range." [ipgui::get_paramspec -name $param -of $IPINST ] + return false + + } + + return true + +} diff --git a/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/yml/uuid_rom_csr_reg.yml b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/yml/uuid_rom_csr_reg.yml new file mode 100644 index 00000000..3d40a8d7 --- /dev/null +++ b/linker/resources/base/iprepo/shell_utils_uuid_rom_v2_0/yml/uuid_rom_csr_reg.yml @@ -0,0 +1,55 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +# ------------------------------------------------------------------- +# UUID ROM IP - Register Definition File +# ------------------------------------------------------------------- +# +# This file defines the discrete registers that are instantiated in +# the UUID ROM RTL module. +# +--- +blockdef: uuid_rom_csr_reg +width: 32 +registers: +################ UUID Registers ################ + +- reg: UUID[4] @ 0x0 + summary: UUID Registers + access: RO + step: 4 + i: UUID ROM + fields: + - field: UUID[31:0] + i: | + This register table contains the 128-bit UUID + UUID_0: Index 0 of UUID + Data[31:0] - UUID[31:0] + + UUID_1: Index 1 of UUID + Data[31:0] - UUID[63:32] + + UUID_2: Index 2 of UUID + Data[31:0] - UUID[95:64] + + UUID_3: Index 3 of UUID + Data[31:0] - UUID[127:96] + diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/i2c_application_apis.md b/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/i2c_application_apis.md new file mode 100755 index 00000000..c04585fe --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/i2c_application_apis.md @@ -0,0 +1,184 @@ +# I2C Application APIs (For debug only) +## Defines + +```sh +#define I2C_SUCCESS ( 0 ) +#define I2C_ERROR ( -1 ) +#define I2C_MAX_BUFFER_LEN ( 256 ) +#define I2C_READ_DATA_SIZE_MIN ( 1 ) +``` + +## Typedefs +```sh +/* + * @typedef I2C_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE + * @brief This callback updates the initialiser with new data + * + * @param pucData pointer to the new data read + * @param pusDataSize number of bytes in pucData + * + * @return void + */ +typedef void ( *I2C_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE )( uint8_t* pucData, uint16_t* pusDataSize ); + +/* + * @typedef I2C_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE + * @brief This callback retrieves data from the initialiser to write + * + * @param pucData pointer to the new data to write + * @param usDataSize number of bytes in pucData + * + * @return void + */ +typedef void ( *I2C_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE )( uint8_t* pucData, uint16_t usDataSize ); + +/* + * @typedef I2C_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE + * @brief This callback updates the initialiser when a command is complete + * + * @param ulStatus is the status of the command + * + * @return void + */ +typedef void ( *I2C_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE )( uint32_t ulStatus ); + +/* + * @typedef I2C_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR + * @brief This callback updates the initialiser when there is an i2 Error + * + * @param ucError is the error that was raised + * + * @return void + */ +typedef void ( *I2C_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR )( uint8_t ucError ); + +/* + * @typedef I2C_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING + * + * @brief This callback updates the initialiser when there is an i2c Warning + * + * @param ucWarning is the warning that was raised + * + * @return void + */ +typedef void ( *I2C_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING )( uint8_t ucWarning ); +``` + +## Driver External APIs +### Create / Destroy an I2C instance +```sh +/******************************************************************************/ +/*! + * @brief Creates an i2c device to act as both a master and a slave + * + * @param pxI2cProfile Handler to the SMBus profile structure (see smbus.h) + * @param ucAddr Slave address that this device will respond to. + * @param pFnGetData Callback called when new data arrives at the device. + * @param pFnWriteData Callback called when the device has to respond with data. + * @param pFnAnnounceResult Callback called when a write/read command is complete. + * @param pFnBusError Callback called when an error occurs + * + * @return The ID of the device (0 to 6) + * Returns I2C_ERROR if the call is unsuccessful + * + * @note [1] This device will be created along with any SMBus instances; + * therefore, it requires availability in the SMBus instance pool. + * See ucCreateSMBusInstance() in smbus.h for more information. + * xInitSMBus() must have been successfully called before this. + */ +/******************************************************************************/ +uint8_t ucI2CCreateDevice( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucAddr, + I2C_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE pFnGetData, + I2C_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE pFnWriteData, + I2C_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE pFnAnnounceResult, + I2C_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR pFnBusError, + I2C_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING pFnBusWarning ); + + +/******************************************************************************/ +/*! + * @brief Destroys a previously created i2c device + * + * @param pxI2cProfile Handler to the SMBus profile structure (see smbus.h) + * @param ucDeviceId ID of the device to destroy + * + * @return I2C_SUCCESS - the device has been successfully destroyed + * I2C_ERROR - the device has not been destroyed + * + * @note None + */ +/******************************************************************************/ +uint8_t ucI2CDestroyDevice( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucDeviceId ); +``` +### Initiate an I2C Write command +```sh +/******************************************************************************/ +/*! + * @brief Writes data to a remote slave as a master + * + * @param pxI2cProfile Handler to the i2c profile structure + * @param ucDeviceId Device to use as a master + * @param ucAddr Address of remote slave to write to + * @param pucData Data buffer to write (must be at least usNumBytes bytes) + * @param usNumBytes Number of bytes to write + * + * @return I2C_SUCCESS - data successfully written + * I2C_ERROR - an error occurred attempting to write + * + */ +/******************************************************************************/ +uint8_t ucI2CWriteData( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucDeviceId, + uint8_t ucAddr, + uint8_t* pucData, + uint16_t usNumBytes ); +``` +### Initiate an I2C Read command +```sh +/******************************************************************************/ +/*! + * @brief Reads data from a remote slave as a master + * + * @param pxI2cProfile Handler to the i2c profile structure + * @param ucDeviceId Device to use as a master + * @param ucAddr Address of remote slave to read from + * @param pusNumBytes Maximum number of bytes to read + * - Cannot be larger than I2C_MAX_BUFFER_LEN + * + * @return I2C_SUCCESS - data successfully read + * I2C_ERROR - an error occurred attempting to read + * + */ +/******************************************************************************/ +uint8_t ucI2CReadData( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucDeviceId, + uint8_t ucAddr, + uint16_t usNumBytes ); +``` +### Initiate an I2C Write-Read command +```sh +/******************************************************************************/ +/*! + * @brief Writes data to a remote slave as a master and then reads from it + * + * @param pxI2cProfile Handler to the i2c profile structure + * @param ucDeviceId Device to use as a master + * @param ucAddr Address of remote slave to write to + * @param pucWriteData Data buffer to write (must be at least usNumBytes bytes) + * @param usNumWriteBytes Number of bytes to write + * @param usNumReadBytes Maximum number of bytes to read + * + * @return I2C_SUCCESS - data successfully written + * I2C_ERROR - an error occurred attempting to write + * + */ +/******************************************************************************/ +uint8_t ucI2CWriteReadData( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucDeviceId, + uint8_t ucAddr, + uint8_t* pucWriteData, + uint16_t usNumWriteBytes, + uint16_t usNumReadBytes ); +``` diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/images/smbus_application.svg b/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/images/smbus_application.svg new file mode 100755 index 00000000..5884d915 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/images/smbus_application.svg @@ -0,0 +1,4 @@ + + + +
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AXI-Lite
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IRQ
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PCIe Add-In Card
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PCIe
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MIOText is not SVG - cannot display \ No newline at end of file diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/images/smbus_architecture.svg b/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/images/smbus_architecture.svg new file mode 100755 index 00000000..933ce7e6 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/images/smbus_architecture.svg @@ -0,0 +1,4 @@ + + + +
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Target Receive FIFOText is not SVG - cannot display \ No newline at end of file diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/smbus_application_api_usage_examples.md b/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/smbus_application_api_usage_examples.md new file mode 100755 index 00000000..b83ec0d7 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/smbus_application_api_usage_examples.md @@ -0,0 +1,753 @@ +# SMBus Application API Usage Examples + +## Introduction +The SMBus driver allows application software to send and receive SMBus commands using the SMBus FPGA IP block. +This can be done using the supplied API functions listed in the smbus.h file. +The driver will allow up to 7 SMBus instances to be created. All of these instances can be used as both as an SMBus target or controller. +All the instances will behave as if they are separate devices on the SMBus. +The instances can be initialized as fixed addresses or be ARP capable and can be initialized to support PEC or not. + +The SMBus driver operates as an event driven state machine. The events are generated from interrupts triggered from the the SMBus hardware IP block. + +It is essential that the correct interrupt is attached by application code and the SMBus driver's interrupt handler called when the interrupt is fired.  + +Detailed examples of how to use the driver APIs can be found below: + +## Memory Assignment + +The SMBus driver will create a copy of the profile it uses internally and pass a pointer to that to application from the xInitSMBus(). +Application will be required to store the pointer for accessing further SMBus APIs. + +```sh +/* Application code will be passed a pointer to the SMBus profile from xInitSMBus() */ +struct SMBUS_PROFILE_TYPE* pxSMBusProfile = NULL; +``` + + + +## Interrupt Code + +Application code will attach the correct hardware interrupt to the interrupt servicing code and associate the SMBus driver's handler vSMBusInterruptHandler with this interrupt + +```sh +/* Application code will attach the correct hardware interrupt to the interrupt servicing code and associate the SMBus driver's handler vSMBusInterruptHandler with this interrupt */ + +/* Example for an ARM core. For Microblaze a different function would be required */ + +#define INTC_INTERRUPT XPAR_FABRIC_BLP_BLP_LOGIC_AXI_SMBUS_RPU_IP2INTC_IRPT_INTR /* This value may be found in the xparameters.h file */ +#define INTC XScuGic +#define INTC_HANDLER XScuGic_InterruptHandler +#define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID /* = 0 */ + + +static int ulSMBusSetupInterruptSystem( ) +{ +    int result = XST_FAILURE; +    XScuGic *pxIntcInstancePtr = &Intc; +    XScuGic_Config *pxIntcConfig = NULL; +    pxIntcConfig = XScuGic_LookupConfig( INTC_DEVICE_ID ); +    if( pxIntcConfig == NULL ) +    { +        return XST_FAILURE; +    } +     +    result = XScuGic_CfgInitialize( pxIntcInstancePtr, pxIntcConfig, pxIntcConfig->CpuBaseAddress ); +    if( result != XST_SUCCESS ) +    { +        return XST_FAILURE; +    } +     +    /* Connect the interrupt handler */ +    result = XScuGic_Connect( pxIntcInstancePtr, INTC_INTERRUPT,( Xil_ExceptionHandler )vSMBusInterruptHandler, pxSMBusProfile ); +    if( result != XST_SUCCESS )  +    { +        return result; +    } +     +    /* Enable the interrupt for the IP */ +    XScuGic_Enable( pxIntcInstancePtr, INTC_INTERRUPT ); +    Xil_ExceptionInit( ); +    Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_INT, +       ( Xil_ExceptionHandler )INTC_HANDLER, pxIntcInstancePtr ); +    Xil_ExceptionEnable( );    /* Enable non-critical exceptions */ +    return XST_SUCCESS; +} +``` + + + + + + +## Callback Functions +Several callback functions need to be implemented by application software and passed to the driver on creation of each instance. +NOTE: The callback functions may be called from within an interrupt context so it is important that they complete quickly + + + + +### Given Command Get Protocol Callback + +This callback will be called when an SMBus Target has received a command byte from an SMBus Controller. +In order for the driver to know how to interpret the bytes following the command it needs to know what SMBus protocol +the command uses. + +```sh +/* This callback function must be created. It will map a received command byte to an SMBus Protocol +     This allows the driver to understand how to interpret the SMBus message */ +void  GivenCommandGetProtocolCallback( uint8_t ucCommand, SMBus_Command_Protocol_Type* pxProtocol ) +{ +    if( NULL != pxProtocol ) +    { +        switch( ucCommand ) +        { +        case 5: +            *pxProtocol = SMBUS_PROTOCOL_WRITE_BYTE; +            break; +        case 6: +            *pxProtocol = SMBUS_PROTOCOL_WRITE_WORD; +            break; +        case 7: +            *pxProtocol = SMBUS_PROTOCOL_READ_BYTE; +            break; +        case 8: +            *pxProtocol = SMBUS_PROTOCOL_READ_WORD; +            break; +        case 9: +            *pxProtocol = SMBUS_PROTOCOL_PROCESS_CALL; +            break; +        case 10: +            *pxProtocol = SMBUS_PROTOCOL_BLOCK_WRITE; +            break; +        case 11: +            *pxProtocol = SMBUS_PROTOCOL_BLOCK_READ; +            break; +        case 12: +            *pxProtocol = SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL; +            break; +        case 13: +            *pxProtocol = SMBUS_PROTOCOL_HOST_NOTIFY; +            break; +        case 14: +            *pxProtocol = SMBUS_PROTOCOL_WRITE_32; +            break; +        case 15: +            *pxProtocol = SMBUS_PROTOCOL_READ_32; +            break; +        case 16: +            *pxProtocol = SMBUS_PROTOCOL_WRITE_64; +            break; +        case 17: +            *pxProtocol = SMBUS_PROTOCOL_READ_64; +            break; + +        default: +            *pxProtocol = SMBUS_PROTOCOL_NONE; +            break; +        } +    } +} +``` + + + +### Read Data Callback +This callback will be called when an SMBus Target has received a read protocol message from an SMBus Controller. +The target must have the data immediately available. +Note - the pusDataSize will be overwritten with the correct values for RECEIVE_BYTE (1), READ_BYTE (1), READ_WORD (2), READ_32 (4), READ_64 (8), and PROCESS_CALL (2), regardless of what value is set in the callback. + +```sh +/* This callback function must be created. It will be called when an SMBus target is required to return data  +     for any read protocol */ +void  ReadDataCallback( uint8_t ucCommand, uint8_t* pucData, uint16_t* pusDataSize ) +{ +    int i = 0; +     +    if( ( NULL != pusDataSize ) && +        ( NULL != pucData ) ) +    { +        switch( ucCommand ) +        { + +        case 7: + /* Byte Read */            +            *pusDataSize = 1; +            pucData[0] = ReadByteData; +            break; + +        case 8:   + /* Word Read */              +            *pusDataSize = 2; +            pucData[0] = ReadWordData[0]; +            pucData[1] = ReadWordData[1]; +            break; + + +        case 9:   + /* Process Call */           +            *pusDataSize = 2; +            pucData[0] = ProcessCallReadData[0]; +            pucData[1] = ProcessCallReadData[1];; +            break; + +        case 11:     + /* Block Read */ + /* +1 as we need to count the block size byte also */ +            *pusDataSize = BlockReadSize+1; + +            pucData[0] = BlockReadSize; +            for( i = 1; i <= BlockReadSize; i++ ) +            { +                pucData[i] = BlockReadData[i]; +            } +            break; + +        case 12:               +   /* Block Write Block Read Process Call */ + /* +1 as we need to count the block size byte also */ +            *pusDataSize = BlockWriteBlockReadSize+1; + +            pucData[0] = BlockWriteBlockReadSize; +            for( i = 1; i <= BlockWriteBlockReadSize; i++ ) +            { +                pucData[i] = BlockWriteBlockReadData[i]; + +            break; + +        case 15: + /* Read 32 */          +            *pusDataSize = 4; +            pucData[0] = Read32Data[0]; +            pucData[1] = Read32Data[1]; +            pucData[2] = Read32Data[2]; +            pucData[3] = Read32Data[3]; +            break; + +        case 17:               + /* Read 64 */ +            *pusDataSize = 8; +            pucData[0] = Read64Data[0]; +            pucData[1] = Read64Data[1]; +            pucData[2] = Read64Data[2]; +            pucData[3] = Read64Data[3]; +            pucData[4] = Read64Data[4]; +            pucData[5] = Read64Data[5]; +            pucData[6] = Read64Data[6]; +            pucData[7] = Read64Data[7]; +            break; + +        default: +            *pusDataSize = 0; +            break; +        } +    } +} +``` + +### Write Data Callback +This callback will be called when an SMBus Target has received data from an SMBus Controller as part of one of the write protocol messages or +it will be called by an SMBus Controller when it has received data back from an SMBus Target as part of one of the read protocol messages. + +```sh +/* This callback function must be created. It will be called when an SMBus target has been sent data +as part of any write protocol */ +void  WriteDataCallback( uint8_t ucCommand, uint8_t* pucData, uint16_t usDataSize ) +{ +    ucTargetCommand = ucCommand; +    usTargetDataSize = usDataSize; +     +    if( ( SMBUS_DATA_SIZE_MAX >= usDataSize ) && +        ( NULL != pucData ) ) +    { +        memcpy( ucTargetData, pucData, usDataSize ); +        ucTargetWriteCallback = SMBUS_TRUE; +    } +} +``` + + + +### Announce Result Callback +This callback will be called when an SMBus transaction completes. +If its an SMBus transaction on an SMBus Target the Transaction ID will be 0. +If its an SMBus transaction initiated on an SMBus Controller then the Transaction ID will be the ID returned by the xSMBusControllerInitiateCommand(). + +```sh +/* This callback function must be created. It will be called when an SMBus transaction has finished  */ +void AnnounceResultCallback(uint8_t ucCommand, uint32_t ulTransactionID, uint32_t ulResult) +{ + /* Application software may act on SMBus transaction completion */ +    SMBusTransactionComplete(ucCommand, ulTransactionID, ulResult); +} +``` + + + + + + +### ARP Address Change Callback +```sh +/* This callback function must be created for all ARP capable instances. +It will be called when an ARP Assign Address message has been sent to the instance   */ +void AnnounceARPAddressChangeCallback(uint8_t ucNewAddress) +{ +    StoreInstaneAddress(ucNewAddress ); +    ucArpAddressChangeCallback = SMBUS_TRUE; + +} +``` + + + +### Error Callback +```sh +/* This callback is optional. If created it will be called if an error interrupt has been received */ +void AnnounceErrorCallback(uint8_t ucCommand, uint8_t  ucError) +{ +    ActOnSMBusError(ucError); + } + ``` + + + +### Warning Callback +```sh +/* This callback is optional. If created it will be called if a warning interrupt has been received */ +void AnnounceWarningCallback(uint8_t ucCommand, uint8_t  ucWarning) +{ +    ActOnSMBusWarning(ucWarning); +} +``` + +## SMBus Driver Initialization and Instance Creation Example Code + +```sh +/* Example application code to intialize the SMBus Driver, create a single SMBus instance and attach and enable interrupts to drive the SMBus driver */ + +uint8_t ucTargetUDID0[16] = { 0x10, 0xFF, 0xFF, 0xFF, 0xF0, 0x0F, 0x0F, 0xF0, 0x07, 0x00, 0xFF, 0xFF, 0xEE, 0x10, 0x0F, 0x40 }; //ARP CAPABLE + +int main( void ) +{ + SMBus_Error_Type xReturnCode = SMBUS_ERROR; + uint8_t ucSMBusAddress = 0; + uint8_t ucUDID[SMBUS_UDID_LENGTH] = { 0 }; + SMBus_ARP_Capability xARPCapability = SMBUS_ARP_CAPABILITY_UNKNOWN; + SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_PROTOCOL_TYPE pFnGetProtocol = NULL; + SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE pFnGetData = NULL; + SMBUS_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE pFnWriteData = NULL; + SMBUS_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE pFnAnnounceResult = NULL; + SMBUS_USER_SUPPLIED_ENVIRONMENT_ARP_ADRRESS_CHANGE pFnArpAddressChange = NULL; + SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR pFnBusError = NULL; + SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING pFnBusWarning = NULL; + uint8_t ucSimpleDevice = 0; + + /* Initialize the SMBus Driver passing in: + a pointer to it's memory profile, + the frequency class to be used 100KHz, 400KHz or 1MHz, + the base address of the SMBus IP's register set, found in xparameters.h + the level of log detail required and + a pointer to a get tick count function for logs */ + + xReturnCode = xInitSMBus( &pxSMBusProfile, SMBUS_FREQ_1MHZ,( void* )XPAR_SMBUS_0_BASEADDR, SMBUS_LOG_LEVEL_DEBUG, + ( SMBUS_USER_SUPPLIED_ENVIRONMENT_READ_TICKS )&vGetTicksFromApplication ); + + if( SMBUS_SUCCESS == xReturnCode ) + { + /* Get ready to create an SMBus Instance + Several parameters are required to be set before an instance can be created */ + + /* ARP Cabability: The SMBus instance can be created with one of 4 ARP capabilities: + SMBUS_ARP_CAPABLE, + SMBUS_ARP_FIXED_AND_DISCOVERABLE, + SMBUS_ARP_FIXED_NOT_DISCOVERABLE, + SMBUS_ARP_NON_ARP_CAPABLE + The required capability must be set on creation of the instance */ + xARPCapability = SMBUS_ARP_CAPABLE; + + /* SMBus Address: If the Instance is to be ARP capable then no address is required otherwise + a fixed address must be set */ + ucSMBusAddress = 0x2A; + + /* SMBus UDID: A 16 byte UDID is required for the SMBus Instance and must be set on creation + THe UDID will also determine if this SMBus instance can accept PEC */ + for( i = 0; i < SMBUS_UDID_LENGTH; i++ ) + { + ucUDID[i] = ucTargetUDID0[i]; + } + + /* SMBus Callback Functions: Separate callback functions for each instance must be created in the application software and + attached to the instance on creation + See above for examples of these callback functions */ + pFnGetProtocol =( SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_PROTOCOL_TYPE )&GivenCommandGetProtocolCallback; + pFnGetData =( SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE )&ReadDataCallback; + pFnWriteData =( SMBUS_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE )&WriteDataCallback; + pFnAnnounceResult =( SMBUS_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE )&AnnounceResultCallback; + pFnArpAddressChange =( SMBUS_USER_SUPPLIED_ENVIRONMENT_ARP_ADRRESS_CHANGE )&AnnounceARPAddressChangeCallback; + pFnBusError =( SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR )&AnnounceErrorCallback; + pFnBusWarning =( SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING )&AnnounceWarningCallback; + + /* SMBus Simple Device: An instance can be created as a Simple Device. + If ucSimpleDevice = 1 the instance will ONLY accept SEND BYTE and RECEIVE BYTE protocols */ + ucSimpleDevice = 0; + + /* Now create the instance, the instance number 0 - 6 will be returned */ + uint8_t ucInstanceId = ucCreateSMBusInstance( pxSMBusProfile, ucSMBusAddress, ucUDID, xARPCapability, + pFnGetProtocol, pFnGetData, pFnWriteData, pFnAnnounceResult, + pFnArpAddressChange, pFnBusError, pFnBusWarning, ucSimpleDevice ); + + /* NOTE: The ucCreateSMBusInstance() function can be called to create up to 7 unique SMBus Instances + each with a different ARP capabilities, SMBUs Address and UDID by repeating the steps in lines 25 - 63 above */ + + /* Disable and clear all SMBus interrupts */ + if(SMBUS_SUCCESS == xSMBusInterruptDisableAndClearInterrupts( pxSMBusProfile )) + { + /* Attach the SMBus hardware interrupt to the interrupt system and + associate the SMBus Interrupt Handler function with the interrupt */ + if( XST_SUCCESS == ulSMBusSetupInterruptSystem( ) ) + { + /* Enable SMBus Interrupts */ + if(SMBUS_SUCCESS == xSMBusInterruptEnableInterrupts( pxSMBusProfile )) + { + /* SMBus driver is now ready to accept SMBus messages */ + } + } + } + } +} +``` + +## Operation as an SMBus Controller +Any instance that has been created can be used to initiate an SMBus transaction as a controller. +The application software needs simply to call the xSMBusControllerInitiateCommand() with the necessary parameters. + +An example of a Write64 is shown below +```sh + uint8_t ucSMBusInstance = 0; + uint8_t ucTargetAddress = 0; + uint8_t ucCommand = 0; + SMBus_Command_Protocol_Type xProtocol = SMBUS_PROTOCOL_NONE; + uint8_t ucPECRequired = SMBUS_FALSE; + uint32_t ulTransactionID = 0; + uint8_t ucControllerDataToSend[MAX_DATA] = { 0 }; + uint16_t usControllerDataToSendSize = 0; + uint8_t ucBlockSize = 0; + uint8_t       ucInitialValue = 0; + + /* Assign values to all the parameters */ + ucSMBusInstance = 0; /* This will be a value 0 - 6 which will have been returned by ucCreateSMBusInstance() function */ + ucTargetAddress = 0x6A; /* The address of the the SMBus Target the message is to be sent to */ + ucCommand = 16; /* The command byte to be sent. The SMBus Target must know what protocol this command maps to */ + xProtocol = SMBUS_PROTOCOL_WRITE_64; /* The protocol to be used for this SMBus message */ + ucPECRequired = SMBUS_FALSE; /* Is the SMBus Target expecting a PEC byte to be sent */ + + /* Write Data of 8 bytes for a Write64 Protocol */ + ucControllerDataToSend[0] = 29; + ucControllerDataToSend[1] = 250; + ucControllerDataToSend[2] = 35; + ucControllerDataToSend[3] = 14; + ucControllerDataToSend[4] = 55; + ucControllerDataToSend[5] = 86; + ucControllerDataToSend[6] = 127; + ucControllerDataToSend[7] = 48; + + ucControllerDataToSendSize = 8; + + if( SMBUS_SUCCESS == xSMBusControllerInitiateCommand( pxSMBusProfile, ucSMBusInstance, ucTargetAddress, ucCommand, xProtocol, + ucControllerDataToSendSize, ucControllerDataToSend, ucPECRequired, &ulTransactionID ) ) + { + /* Write 64 Initiated */ + /* This function may return before the asynchronous transaction has completed */ + } +``` + + + + +An example of a Block Write - Block Read Process Call is shown below +```sh + uint8_t ucSMBusInstance = 0; + uint8_t ucTargetAddress = 0; + uint8_t ucCommand = 0; + SMBus_Command_Protocol_Type xProtocol = SMBUS_PROTOCOL_NONE; + uint8_t ucPECRequired = SMBUS_FALSE; + uint32_t ulTransactionID = 0; + int i = 0; + uint8_t ucControllerDataToSend[MAX_DATA] = { 0 }; + uint16_t usControllerDataToSendSize = 0; + uint8_t ucBlockSize = 0; + uint8_t       ucInitialValue = 0; + + /* Assign values to all the parameters */ + ucSMBusInstance = 0; /* This will be a value 0 - 6 which will have been returned by ucCreateSMBusInstance() function */ + ucTargetAddress = 0x6A; /* The address of the the SMBus Target the message is to be sent to */ + ucCommand = 12; /* The command byte to be sent. The SMBus Target must know what protocol this command maps to */ + xProtocol = SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL; /* The protocol to be used for this SMBus message */ + ucPECRequired = false; /* Is the SMBus Target expecting a PEC byte to be sent */ + + + /* Write Data - For block transactions the block size needs to be added as the first byte of the data supplied to the function + So for a block size of 125, 126 bytes will be supplied to the function, the first byte being the value 125 and the + SendSize parameter will be 126 */ + ucBlockSize = 125; + ucControllerDataToSend[0] = ucBlockSize; + ucControllerDataToSend[1] = 0; + ucInitialValue = 0x1; + for( i = 1; i <= ucBlockSize; i++ ) + { + ucControllerDataToSend[i] = ucInitialValue++; + } + ucControllerDataToSendSize = ucBlockSize + 1; + +     if( SMBUS_SUCCESS == xSMBusControllerInitiateCommand( pxSMBusProfile, ucSMBusInstance, ucTargetAddress, ucCommand, xProtocol, + ucControllerDataToSendSize, ucControllerDataToSend, ucPECRequired, &ulTransactionID ) ) + { + /* Block Write - Block Read Process Call Initiated */ + /* This function may return before the asynchronous transaction has completed */ + } +``` + +## ARP Operation + +If any of the SMBus Instances have been created as ARP capable then they will respond to any ARP command sent from an ARP Controller to the SMBus Device Default Address . + +ARP commands include: +Prepare to ARP +Reset device (general) +Get UDID (general) +Assign address +Get UDID (directed) +Reset device ARP (directed) +Notify ARP Controller + +Only after an ARP capable instance has been given an address by an ARP Assign Address command will it be ready to receive any standard SMBus commands. +On receiving an ARP Assign Address command the instance receiving the change will call it's ARP Address Change Callback function to notify the application of the assigned address. + +(Note: Unlike ARP capable instances, fixed address instances are ready to receive any standard SMBus commands as soon as they are created.) + +  + +## Logging +Event logs are written to a 5000 entry deep circular buffer. +Various levels of logging can be set ranging from SMBUS_LOG_LEVEL_NONE to SMBUS_LOG_LEVEL_DEBUG level logging. +Logs can be retreived using the xSMBusGetLog() function which automatically formats the log events into a text string. +Logs can be cleared using the xSMBusLogReset() function. + +```sh +void vPostTestPrintLog( void ) +{ + char cLogBuffer[LOGSIZE] = { 0 }; + uint32_t ulLogSize = 0; + /********************************** LOG **********************************/ + xil_printf( "Log\n\r" ); + cLogBuffer[0] = '\0'; + ulLogSize = 0; + xSMBusGetLog( pxSMBusProfile, cLogBuffer, &ulLogSize ); + xil_printf( "%s\n\r", cLogBuffer ); + +} +``` + + + +An example log for an SMBus Controller (Instance 0) sending a  Write64 command to SMBus Target (Instance 1 ) is shown below: +```sh +0000 3793799 HW_WRITE 88 0x00000a08 0x80000000 +0001 3793799 HW_WRITE 88 0x00000a10 0x80000000 +0002 3793799 HW_WRITE 88 0x00000020 0x00000000 +0003 3793799 FSM 0 SMBUS_STATE_INITIAL E_SEND_NEXT_BYTE +0004 3793799 DEBUG 0 0x00000024 line 3623 +0005 3793800 HW_READ 88 0x00000830 0x00000001 +0006 3793800 DEBUG 0 0x00000001 line 662 +0007 3793800 HW_READ 88 0x00000a1c 0x00000001 +0008 3793800 DEBUG 0 0x00000001 line 665 +0009 3793800 DEBUG 0 0x0000006a line 701 +0010 3793800 HW_READ 88 0x00000a0c 0x00000003 +0011 3793800 HW_WRITE 88 0x00000a08 0x000000d4 +0012 3793800 FSM 0 SMBUS_STATE_CONTROLLER_SEND_COMMAND E_SEND_NEXT_BYTE +0013 3793800 DEBUG 0 0x00000024 line 3623 +0014 3793801 HW_READ 88 0x00000a0c 0x00000102 +0015 3793801 HW_WRITE 88 0x00000a08 0x00000210 +0016 3793801 FSM 0 SMBUS_STATE_CONTROLLER_WRITE_BYTE E_SEND_NEXT_BYTE +0017 3793801 DEBUG 0 0x00000024 line 3623 +0018 3793801 DEBUG 0 0x00000008 line 2615 +0019 3793801 HW_READ 88 0x00000a0c 0x00000200 +0020 3793801 HW_WRITE 88 0x00000a08 0x0000021d +0021 3793801 HW_WRITE 88 0x00000a08 0x000002fa +0022 3793801 HW_WRITE 88 0x00000a08 0x00000223 +0023 3793802 HW_WRITE 88 0x00000a08 0x0000020e +0024 3793802 HW_WRITE 88 0x00000a08 0x00000237 +0025 3793802 HW_WRITE 88 0x00000a08 0x00000256 +0026 3793802 HW_WRITE 88 0x00000a08 0x0000027f +0027 3793802 HW_WRITE 88 0x00000a00 0x00000001 +0028 3793803 HW_WRITE 88 0x00000024 0x0000dfef +0029 3793803 HW_WRITE 88 0x00000020 0x00000001 +0030 3793803 HW_WRITE 88 0x00000020 0x00000000 +0031 3793803 HW_READ 88 0x00000028 0x00000080 +0032 3793804 HW_READ 88 0x00000024 0x0000dfef +0033 3793804 INTERRUPT 88 0x00067f94 0x00000080 +0034 3793804 HW_READ 88 0x00000600 0x000001d4 +0035 3793804 FSM 1 SMBUS_STATE_INITIAL E_TARGET_WRITE_IRQ +0036 3793804 DEBUG 1 0x00000001 line 3623 +0037 3793804 HW_WRITE 88 0x00000030 0x00000000 +0038 3793805 HW_WRITE 88 0x00000028 0x00000080 +0039 3793805 HW_WRITE 88 0x00000020 0x00000001 +0040 3793805 HW_WRITE 88 0x00000020 0x00000000 +0041 3793805 HW_READ 88 0x00000028 0x00000130 +0042 3793805 HW_READ 88 0x00000024 0x0000dfef +0043 3793805 INTERRUPT 88 0x00067f94 0x00000130 +0044 3793805 FSM 1 SMBUS_STATE_AWAITING_COMMAND_BYTE E_TARGET_DATA_IRQ +0045 3793805 DEBUG 1 0x00000003 line 3623 +0046 3793805 DEBUG 1 0x0000006a line 831 +0047 3793806 HW_READ 88 0x00000610 0x00040102 +0048 3793806 HW_READ 88 0x0000060c 0x00000010 +0049 3793806 PROTOCOL 1 0x00000010 SMBUS_PROTOCOL_WRITE_64 +0050 3793806 HW_WRITE 88 0x00000614 0x00000008 +0051 3793806 HW_READ 88 0x00000608 0x00000003 +0052 3793806 HW_WRITE 88 0x00000604 0x00000000 +0053 3793806 HW_READ 88 0x00000608 0x00000003 +0054 3793806 HW_WRITE 88 0x00000604 0x00000000 +0055 3793807 HW_READ 88 0x00000608 0x00000102 +0056 3793807 HW_WRITE 88 0x00000604 0x00000000 +0057 3793807 HW_READ 88 0x00000608 0x00000200 +0058 3793807 HW_WRITE 88 0x00000604 0x00000000 +0059 3793807 HW_READ 88 0x00000608 0x00000300 +0060 3793807 HW_WRITE 88 0x00000604 0x00000000 +0061 3793807 HW_READ 88 0x00000608 0x00000300 +0062 3793807 HW_WRITE 88 0x00000604 0x00000000 +0063 3793807 HW_READ 88 0x00000608 0x00000400 +0064 3793807 HW_WRITE 88 0x00000604 0x00000000 +0065 3793808 HW_READ 88 0x00000608 0x00000500 +0066 3793808 HW_WRITE 88 0x00000604 0x00000000 +0067 3793808 HW_READ 88 0x00000608 0x00000600 +0068 3793808 HW_WRITE 88 0x00000604 0x00000000 +0069 3793808 HW_READ 88 0x00000610 0x00040102 +0070 3793808 FSM 1 SMBUS_STATE_AWAITING_DATA E_DESC_FIFO_ALMOST_EMPTY_IRQ +0071 3793808 DEBUG 1 0x00000026 line 3623 +0072 3793808 HW_READ 88 0x00000608 0x00000600 +0073 3793809 FSM 1 SMBUS_STATE_AWAITING_DATA E_TARGET_DATA_IRQ +0074 3793809 DEBUG 1 0x00000003 line 3623 +0075 3793809 HW_READ 88 0x00000610 0x00040200 +0076 3793809 HW_READ 88 0x0000060c 0x0000001d +0077 3793809 HW_READ 88 0x0000060c 0x000000fa +0078 3793809 HW_WRITE 88 0x00000614 0x00000001 +0079 3793809 HW_WRITE 88 0x00000030 0x00000000 +0080 3793809 HW_WRITE 88 0x00000028 0x00000130 +0081 3793810 HW_WRITE 88 0x00000020 0x00000001 +0082 3793810 HW_WRITE 88 0x00000020 0x00000000 +0083 3793810 HW_READ 88 0x00000028 0x00000020 +0084 3793810 HW_READ 88 0x00000024 0x0000dfef +0085 3793810 INTERRUPT 88 0x00067f94 0x00000020 +0086 3793810 FSM 1 SMBUS_STATE_AWAITING_DATA E_TARGET_DATA_IRQ +0087 3793810 DEBUG 1 0x00000003 line 3623 +0088 3793810 HW_READ 88 0x00000610 0x00040200 +0089 3793810 HW_READ 88 0x0000060c 0x00000023 +0090 3793811 HW_READ 88 0x0000060c 0x0000000e +0091 3793811 HW_WRITE 88 0x00000614 0x00000001 +0092 3793811 HW_WRITE 88 0x00000030 0x00000000 +0093 3793811 HW_WRITE 88 0x00000028 0x00000020 +0094 3793811 HW_WRITE 88 0x00000020 0x00000001 +0095 3793811 HW_WRITE 88 0x00000020 0x00000000 +0096 3793811 HW_READ 88 0x00000028 0x00000020 +0097 3793811 HW_READ 88 0x00000024 0x0000dfef +0098 3793811 INTERRUPT 88 0x00067f94 0x00000020 +0099 3793812 FSM 1 SMBUS_STATE_AWAITING_DATA E_TARGET_DATA_IRQ +0100 3793812 DEBUG 1 0x00000003 line 3623 +0101 3793812 HW_READ 88 0x00000610 0x00040102 +0102 3793812 HW_READ 88 0x0000060c 0x00000037 +0103 3793812 HW_WRITE 88 0x00000614 0x00000001 +0104 3793812 HW_WRITE 88 0x00000030 0x00000000 +0105 3793812 HW_WRITE 88 0x00000028 0x00000020 +0106 3793812 HW_WRITE 88 0x00000020 0x00000001 +0107 3793812 HW_WRITE 88 0x00000020 0x00000000 +0108 3793813 HW_READ 88 0x00000028 0x00008020 +0109 3793813 HW_READ 88 0x00000024 0x0000dfef +0110 3793813 INTERRUPT 88 0x00067f94 0x00008020 +0111 3793813 FSM 1 SMBUS_STATE_AWAITING_DATA E_TARGET_DATA_IRQ +0112 3793813 DEBUG 1 0x00000003 line 3623 +0113 3793813 HW_READ 88 0x00000610 0x00040200 +0114 3793813 HW_READ 88 0x0000060c 0x00000056 +0115 3793813 HW_READ 88 0x0000060c 0x0000007f +0116 3793813 HW_WRITE 88 0x00000614 0x00000001 +0117 3793814 FSM 0 SMBUS_STATE_CONTROLLER_WRITE_BYTE E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ +0118 3793814 DEBUG 0 0x00000017 line 3623 +0119 3793814 DEBUG 0 0x00000001 line 2615 +0120 3793814 DEBUG 0 0x00000001 line 2643 +0121 3793814 DEBUG 0 0x00000001 line 2664 +0122 3793814 DEBUG 0 0x00000000 line 2683 +0123 3793814 HW_READ 88 0x00000a0c 0x00000003 +0124 3793814 HW_WRITE 88 0x00000a08 0x00000330 +0125 3793814 HW_WRITE 88 0x00000a00 0x00000001 +0126 3793815 HW_WRITE 88 0x00000030 0x00000000 +0127 3793815 HW_WRITE 88 0x00000028 0x00008020 +0128 3793815 HW_WRITE 88 0x00000020 0x00000001 +0129 3793815 HW_WRITE 88 0x00000020 0x00000000 +0130 3793815 HW_READ 88 0x00000028 0x00002120 +0131 3793815 HW_READ 88 0x00000024 0x0000dfef +0132 3793815 INTERRUPT 88 0x00067f94 0x00002120 +0133 3793816 FSM 1 SMBUS_STATE_AWAITING_DATA E_TARGET_DATA_IRQ +0134 3793816 DEBUG 1 0x00000003 line 3623 +0135 3793816 HW_READ 88 0x00000610 0x00040102 +0136 3793816 HW_READ 88 0x0000060c 0x00000030 +0137 3793816 HW_WRITE 88 0x00000614 0x00000001 +0138 3793816 FSM 1 SMBUS_STATE_AWAITING_DONE E_DESC_FIFO_ALMOST_EMPTY_IRQ +0139 3793816 DEBUG 1 0x00000026 line 3623 +0140 3793816 DEBUG 1 0x00000009 line 1654 +0141 3793816 DEBUG 1 0x00000008 line 1657 +0142 3793816 DEBUG 1 0x00000008 line 1660 +0143 3793817 HW_READ 88 0x00000608 0x00000003 +0144 3793817 HW_WRITE 88 0x00000030 0x00000000 +0145 3793817 HW_WRITE 88 0x00000028 0x00002120 +0146 3793817 HW_WRITE 88 0x00000020 0x00000001 +0147 3793817 HW_WRITE 88 0x00000020 0x00000000 +0148 3793817 HW_READ 88 0x00000028 0x00001008 +0149 3793818 HW_READ 88 0x00000024 0x0000dfef +0150 3793818 INTERRUPT 88 0x00067f94 0x00001008 +0151 3793818 FSM 1 SMBUS_STATE_AWAITING_DONE E_TARGET_DONE_IRQ +0152 3793818 DEBUG 1 0x00000004 line 3623 +0153 3793818 DEBUG 1 0x00000010 line 1773 +0154 3793818 DEBUG 1 0x00000008 line 1776 +0155 3793818 DEBUG 1 0x00000001 line 68 +0156 3793818 HW_READ 88 0x00000610 0x00040003 +0157 3793818 HW_WRITE 88 0x0000060c 0x80000000 +0158 3793819 FSM 0 SMBUS_STATE_AWAITING_DONE E_CONTROLLER_DONE_IRQ +0159 3793819 DEBUG 0 0x00000016 line 3623 +0160 3793819 DEBUG 0 0x00000000 line 68 +0161 3793819 HW_READ 88 0x00000a14 0x00120003 +0162 3793819 HW_WRITE 88 0x00000a10 0x80000000 +0163 3793819 HW_WRITE 88 0x00000a08 0x80000000 +0164 3793820 HW_WRITE 88 0x00000030 0x00000000 +0165 3793820 HW_WRITE 88 0x00000028 0x00001008 +0166 3793820 HW_WRITE 88 0x00000024 0x000001ef +0167 3793820 HW_WRITE 88 0x00000020 0x00000001 +``` + +## Simple Target +An SMBus instance may be created as a "Simple" target. +This can be done by setting xInstance.ucSimpleDevice = 1 when the creating the instance. +When this is done the instance will ONLY accept SEND BYTE and RECEIVE BYTE protocols. + + + + +## SMBus Address +The SMBus Address is a 7-bit value. When using the ucCreateSMBusInstance(), the value set in the ucSMBusAddress field of the Instance parameter should occupy the 7 least significant bits (bits 6 - 0). +When this address is transmitted on the SMBus it may be seen bit shifted to the left by a single bit. The 7 bits of the address now become the 7 most significant bits (bits 7 - 1) and bit 0 is used as the READ/WRITE bit. + +When an ARP Controller assigns a new address via the ARP ASSIGN ADDRESS command, the new 7-bit assigned address must be added to the payload already pre-shifted to the 7 most significant bits (bits 7 - 1) and bit 0 is ignored. + + + + +## Dynamic and Persistent Addresses +If an SMBus instance is created as ARP-Capable and its address is Dynamic and Persistent  (ie. Address Type bits 7:6 of the Device Capabilities Field of the instance's UDID are set to be Dynamic and Persistent [01] ) +In this situation: +ucCreateSMBusInstance() could be creating the instance with an invalid temporary address and awaiting a new address to be assigned by ARP +or + ucCreateSMBusInstance() could be creating the instance with an address it had previously been assigned (ie a Persistent Address) + +In order to determine which, the ucCreateSMBusInstance() function will check bit 7 of the ucSMBusAddress field in the Instance parameter. + + - If this is set it will treat the address as an invalid temporary address, will clear the AR flag and wait on a new address to be assigned by ARP Assign Address. + - If the bit is clear,  it will treat the address as a dynamic and persistent address, will set the AR flag and allow add the address onto the bus. + \ No newline at end of file diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/smbus_application_apis.md b/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/smbus_application_apis.md new file mode 100755 index 00000000..0173c5fe --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/smbus_application_apis.md @@ -0,0 +1,493 @@ +# SMBus Application APIs +## Defines + + + +```sh +#define SMBUS_DATA_SIZE_MIN ( 0 ) +#define SMBUS_DATA_SIZE_MAX ( 256 ) /* 255 bytes of data + 1 byte block size */ +#define SMBUS_UDID_LENGTH ( 16 ) +#define SMBUS_MAX_CIRCULAR_LOG_ENTRIES ( 5000 ) +#define SMBUS_NUMBER_OF_SMBUS_INSTANCES ( 8 ) +#define SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES ( 7 ) +#define SMBUS_INVALID_INSTANCE ( 99 ) +#define SMBUS_MAX_EVENT_ELEMENTS ( 300 ) +``` + + + +## Enums +```sh +/* + * @enum SMBus_Freq_Class_Type + * @brief Enumeration of SMBUS frequency values + */ +typedef enum SMBus_Freq_Class_Type +{ +    SMBUS_FREQ_100KHZ = 0, +    SMBUS_FREQ_400KHZ, +    SMBUS_FREQ_1MHZ, +    SMBUS_FREQ_MAX + +} SMBus_Freq_Class_Type; + +/* + * @enum SMBus_Error_Type + * @brief Enumeration of SMBUS return values + */ +typedef enum SMBus_Error_Type +{ +    SMBUS_SUCCESS = 0, +    SMBUS_ERROR + +} SMBus_Error_Type; + +/* + * @enum SMBus_ARP_Capability + * @brief Enumeration of SMBUS ARP settings + */ +typedef enum SMBus_ARP_Capability +{ +    SMBUS_ARP_CAPABILITY_UNKNOWN = 0, +    SMBUS_ARP_CAPABLE, +    SMBUS_ARP_FIXED_AND_DISCOVERABLE, +    SMBUS_ARP_FIXED_NOT_DISCOVERABLE, +    SMBUS_ARP_NON_ARP_CAPABLE + +} SMBus_ARP_Capability; + +/* + * @enum SMBus_Command_Protocol_Type + * @brief Enumeration of SMBUS command protocols + */ +typedef enum SMBus_Command_Protocol_Type +{ +    SMBUS_PROTOCOL_QUICK_COMMAND_LO = 0, +    SMBUS_PROTOCOL_QUICK_COMMAND_HI, +    SMBUS_PROTOCOL_SEND_BYTE, +    SMBUS_PROTOCOL_RECEIVE_BYTE, +    SMBUS_PROTOCOL_WRITE_BYTE, +    SMBUS_PROTOCOL_WRITE_WORD, +    SMBUS_PROTOCOL_READ_BYTE, +    SMBUS_PROTOCOL_READ_WORD, +    SMBUS_PROTOCOL_PROCESS_CALL, +    SMBUS_PROTOCOL_BLOCK_WRITE, +    SMBUS_PROTOCOL_BLOCK_READ, +    SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL, +    SMBUS_PROTOCOL_HOST_NOTIFY, +    SMBUS_PROTOCOL_WRITE_32, +    SMBUS_PROTOCOL_READ_32, +    SMBUS_PROTOCOL_WRITE_64, +    SMBUS_PROTOCOL_READ_64, +    SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP, +    SMBUS_ARP_PROTOCOL_RESET_DEVICE, +    SMBUS_ARP_PROTOCOL_GET_UDID, +    SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS, +    SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED, +    SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED, +    SMBUS_PROTOCOL_NONE + +} SMBus_Command_Protocol_Type; + +/* + * @enum SMBUS_LOG_EVENT_TYPE + * @brief Enumeration of SMBus logging types + */ +typedef enum SMBUS_LOG_EVENT_TYPE +{ +    SMBUS_LOG_EVENT_INTERRUPT_EVENT = 1, +    SMBUS_LOG_EVENT_FSM_EVENT, +    SMBUS_LOG_EVENT_ERROR, +    SMBUS_LOG_EVENT_HW_READ, +    SMBUS_LOG_EVENT_HW_WRITE, +    SMBUS_LOG_EVENT_PROTOCOL, +    SMBUS_LOG_EVENT_DEBUG, +    SMBUS_LOG_EVENT_TRYREAD, +    SMBUS_LOG_EVENT_TRYWRITE + +} SMBUS_LOG_EVENT_TYPE; + +/* + * @enum SMBUS_LOG_LEVEL_TYPE + * @brief Enumeration of SMBUS logging levels + */ +typedef enum SMBUS_LOG_LEVEL_TYPE +{ +    SMBUS_LOG_LEVEL_NONE = 0, +    SMBUS_LOG_LEVEL_ERROR, +    SMBUS_LOG_LEVEL_WARNING, +    SMBUS_LOG_LEVEL_INFO, +    SMBUS_LOG_LEVEL_DEBUG, +    SMBUS_LOG_LEVEL_MAX + +} SMBUS_LOG_LEVEL_TYPE; +``` +## Typedefs +```sh +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_PROTOCOL_TYPE + * + * @brief   This callback retrieves the protocol for a command + * @param   ucCommand is the command under inspection + * @param   xProtocol is a pointer for the protocol to be stored in + * + * @return  void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_PROTOCOL_TYPE )( uint8_t ucCommand,  +                SMBus_Command_Protocol_Type* xProtocol ); +                +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE + * + * @brief   This callback updates the initialiser with new data + * @param   ucCommand is the SMBus command + * @param   pucData is a pointer to the new data read + * @param   Data_Size is the number of bytes in pucData + * + * @return  void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE )( uint8_t ucCommand, uint8_t* pucData,  +                uint16_t* Data_Size ); +                +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE + * + * @brief   This callback retrieves data from the initialiser to write + * @param   ucCommand is the SMBus command + * @param   pucData is a pointer to the new data to write + * @param   Data_Size is the number of bytes in pucData + * @param   ulTransactonID is the transaction ID of the message + * + * @return  void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE )( uint8_t ucCommand, uint8_t* pucData,  +                uint16_t Data_Size, uint32_t ulTransactionID ); +                +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE + * + * @brief   This callback updates the initialiser when a command is complete + * @param   ucCommand is the SMBus command + * @param   ulTransactionID is the transaction ID of the completed command + * @param   Status is the status of the command + * + * @return  void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE )( uint8_t ucCommand, uint32_t ulTransactionID,  +                uint32_t Status ); +                +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_ARP_ADDRESS_CHANGE + * + * @brief   This callback updates the initialiser when an address is changed + * @param   ucNewAddress is the next SMBus address + * + * @return  void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_ARP_ADRRESS_CHANGE )( uint8_t ucNewAddress ); + +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR + * + * @brief   This callback updates the initialiser when there is an SMBus Error + * @param   ucError is the error that was raised + * + * @return  void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR )( uint8_t ucError ); + +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING + * + * @brief   This callback updates the initialiser when there is an SMBus Warning + * @param   ucWarning is the warning that was raised + * + * @return  void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING )( uint8_t ucWarning ); + +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_READ_TICKS + * + * @brief   This callback retrieves the current tick count from the initialiser + * @param   pulTicks is a a pointer to store the tick count + * + * @return  void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_READ_TICKS )( uint32_t* pulTicks ); +``` +## Structs +```sh +/* + * @struct SMBUS_LOG_TYPE + * @brief  Structure to hold SMBus message logging information + */ +typedef struct SMBUS_LOG_TYPE +{ +    uint32_t   ulMessagesComplete[SMBUS_PROTOCOL_NONE]; +    uint32_t ulMessagesInitiated[SMBUS_PROTOCOL_NONE]; +} SMBUS_LOG_TYPE; + +/* + * @struct SMBUS_VERSION_TYPE + * @brief  Structure to hold the SMBus driver version information + */ +typedef struct SMBUS_VERSION_TYPE +{ +    uint16_t usIpVerMajor; +    uint16_t    usIpVerMinor; +    uint8_t     ucSwVerMajor; +    uint8_t     ucSwVerMinor; +    uint8_t     ucSwVerPatch; +    uint8_t     ucSwDevBuild; +    uint8_t     ucSwTestBuild; +} SMBUS_VERSION_TYPE; +``` +## Driver External APIs +### Initialise the SMBus +```sh +/******************************************************************************* +* +* @brief Checks hardware is present at the supplied base address +* Sets up hardware registers for the frequency class supplied +* initializes software structures, sets up log and event queues +* +* @param ppxSMBusProfile is a pointer to the SMBus profile structure handle. +* @param xFrequencyClass is an enum of type Freq_Class_Type which can be +* 100KHz, 400KHz or 1MHz. +* @param pvBaseAddress is the address of the SMBus IP block +* @param xLogLevel is the level of logging detail required +* @param pFnReadTicks is an optional function pointer that supplies a tick count for logging purposes +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*****************************************************************************/ +SMBus_Error_Type xInitSMBus( struct SMBUS_PROFILE_TYPE** ppxSMBusProfile, + SMBus_Freq_Class_Type xFrequencyClass, + void * pvBaseAddress, + SMBUS_LOG_LEVEL_TYPE xLogLevel, + SMBUS_USER_SUPPLIED_ENVIRONMENT_READ_TICKS pFnReadTicks ); +``` +### Deinitialise the SMBus +```sh +/******************************************************************************* +* +* @brief Checks all instances have already been removed +* If so sets Profile structure to default values +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure handle. +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*****************************************************************************/ +SMBus_Error_Type xDeinitSMBus( struct SMBUS_PROFILE_TYPE** ppxSMBusProfile ); +``` + +### Create / Destroy an SMBus instance +```sh +/******************************************************************************* +* +* @brief Checks that a free instance slot is available and if so stores the +* supplied data associated with the instance and enables the hardware +* to send or receive SMBus messages for the supplied instance +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucSMBusAddress is the 7-bit SMBUs address to asscociate with this instance +* @param ucUDID is the 16 byte UDID to asscociate with this instance +* @param xARPCapability is the ARP capabaility of the instance +* @param pFnGetProtocol ia a pointer to a function to convert coammand byte to an SMBus protocol +* @param pFnGetData ia a pointer to a function to get data to be returned +* @param pFnWriteData ia a pointer to a function to write data received +* @param pFnAnnounceResult ia a pointer to a function to announce the result of a transaction +* @param pFnArpAddressChange ia a pointer to a function to call if the address is changed +* @param pFnBusError ia a pointer to a function to report SMBus errors +* @param pFnBusWarning ia a pointer to a function to report SMBus warnings +* @param ucSimpleDevice is a flag to allow instance to understand only simple +* send and receive byte commands +* +* @return - SMBUS_INVALID_INSTANCE ID ( 99 ) if error +* - Instance ID ( 0 - 6 ) if successful +* +* @note None. +* +*******************************************************************************/ +uint8_t ucCreateSMBusInstance( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, + uint8_t ucSMBusAddress, + uint8_t ucUDID[SMBUS_UDID_LENGTH], + SMBus_ARP_Capability xARPCapability, + SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_PROTOCOL_TYPE pFnGetProtocol, + SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE pFnGetData, + SMBUS_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE pFnWriteData, + SMBUS_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE pFnAnnounceResult, + SMBUS_USER_SUPPLIED_ENVIRONMENT_ARP_ADRRESS_CHANGE pFnArpAddressChange, + SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR pFnBusError, + SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING pFnBusWarning, + uint8_t ucSimpleDevice ); + + + + +/****************************************************************************** +* +* @brief Checks that the supplied instance is present and attempts to remove +* it. If the instance being removed is the only instance then the ARP +* instance is also removed +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucSMBusInstanceID is the SMBus instance ID of the instance to be +* removed +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*****************************************************************************/ +SMBus_Error_Type xDestroySMBusInstance( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, + uint8_t ucSMBusInstanceID ); +``` +### Initiate an SMBus command +```sh +/******************************************************************************* +* +* @brief Will initiate an SMBus message from the supplied intance as a controller +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucSMBusInstanceID is the SMBus instance ID of the instance to use as the controller +* @param ucSMBusDestinationAddress is the address of the target SMBUs device +* @param ucCommand is the Command byte of the message +* @param xProtocol is the SMBUs Protocol type of the message being sent +* @param usDataSize is the Size of data being sent ( if tranaction protocol is a send type ) +* @param pucData is a pointer to the data to send ( if tranaction protocol is a send type ) +* @param ucPecRequiredForTransaction is an integer to set if a PEC is required to be sent or not +* @param ulTransactionID is a pointer to the unique ID assigned to this transaction +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusControllerInitiateCommand( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, + uint8_t ucSMBusInstance, + uint8_t ucSMBusDestinationAddress, + uint8_t ucCommand, + SMBus_Command_Protocol_Type xProtocol, + uint16_t usDataSize, + uint8_t* pucData, + uint8_t ucPecRequiredForTransaction, + uint32_t* pulTransactionID ); +``` +### Retrieve / Reset SMBus Driver log +```sh +/******************************************************************************* +* +* @brief Retrieves SMBus log that is stored as a circular buffer in profile struct +* as ASCII char array +* +* @param SMBUS_PROFILE_TYPE is the context to poll log on +* @param pcLogBuffer is the array to put log data must be more than TBD driver events string +* separated by '\n' +* @param pusLogSizeBytes is a pointer to the number of bytes that are in the log +* (NOTE NOT NULL TERMINATED. THIS SHOULD BE USED FOR MEMCPY ETC) +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusGetLog( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, + char* pcLogBuffer, + uint32_t* pulLogSizeBytes ); + + + + +/******************************************************************************* +* +* @brief Resets SMBus Driver Log +* +* @param SMBUS_PROFILE_TYPE is the context with log to clear +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusLogReset( struct SMBUS_PROFILE_TYPE* pxSMBusProfile ); +``` +### Disable / Enable Interrupts +```sh +/******************************************************************************* +* +* @brief Disables and then clears all SMBUs interrupts +* +* @param pxSMBusProfile is the pointer to the SMBus profile. +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusInterruptDisableAndClearInterrupts( struct SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief enables all necessary SMBUs interrupts +* +* @param pxSMBusProfile is the pointer to the SMBus profile. +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusInterruptEnableInterrupts( struct SMBUS_PROFILE_TYPE* pxSMBusProfile ); +``` +### Interrupt Handler +```sh +/******************************************************************************* +* +* @brief Function will be a callback called from the interrupt handler +* It will determine what interrupts are present from those add +* events on the event queue and then trigger the handling of the +* events by the state machine +* +* @param pvCallBackRef is the reference to the SMBus profile. +* +* @return void +* +* @note None. +* +*******************************************************************************/ +void vSMBusInterruptHandler( void* pvCallBackRef ); +``` +### Retrieve SMBus Driver version +```sh +/******************************************************************************* +* +* @brief Retrieves the SMBus driver version +* +* @param pxSMBusProfile is the pointer to the SMBUS profile +* +* @param pxSMBusVersion is the pointer to the SMBus version (to be filled). +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusGetVersion( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, + SMBUS_VERSION_TYPE* pxSMBusVersion ); +``` diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/smbus_ip_product_guide.rst b/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/smbus_ip_product_guide.rst new file mode 100755 index 00000000..b397b13f --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/doc/smbus_ip_product_guide.rst @@ -0,0 +1,2343 @@ +============= +SMBus IP v1.1 +============= + + +Overview +======== + +The SMBus IP provides a mechanism through which a Versal ACAP based system may interact with +external devices that are compliant to the `System Management Bus (SMBus) v3.2 Specification`_. +SMBus is a two-wire open-drain interface based on the principles of operation defined by the `I2C +Bus Specification`_. It provides a standardized control path that enables devices to pass system +and power management related messages. + +The SMBus IP is designed to be implemented within the PL region of a Versal ACAP and requires +connection to I/O Buffers located within an appropriate HDIO bank, these IOBs must be configured to +meet the electrical requirements outlined in the SMBus Specification. The IP implements an +AXI4-Lite Subordinate memory mapped control interface to enable a processor to interact with other +external SMBus devices, the IP supports operation as both a Controller and a multi-device Target to +enable multiple management protocols to be implemented simultaneously. + +.. _`System Management Bus (SMBus) v3.2 Specification`: http://smbus.org/specs/SMBus_3_2_20220112.pdf +.. _`I2C Bus Specification`: https://www.nxp.com/docs/en/user-guide/UM10204.pdf + +Features +======== + +- Controller operation +- Target operation supporting up to 8 devices +- Support for 100KHz, 400KHz or 1MHz operation +- Packet Error Correction (PEC) Generation and Checking +- Loss of Arbitration detection as a Controller-transmitter +- Loss of Arbitration detection as a Target-transmitter +- Controller clock synchronization +- Controller clock stretching +- Target clock stretching +- Descriptor based event sequence control +- Interrupt driven operation +- SMBCLK low timeout detection +- SMBDAT low timeout detection +- SMBCLK/SMBDAT glitch suppression +- SMBCLK stretching timeout detection (Tlow:TEXT/CEXT) + +Applications +============ + +The diagram below outlines a typical use case for the SMBus IP as deployed within a Versal based +PCIe add-in accelerator card. The SMBus IP provides a mechanism for the card management software +in conjunction with the SMBus IP Driver running on the RPU to communicate with the host server BMC. + +.. image:: images/smbus_application.svg + +Standards +========= + +The SMBus IP when implemented in conjunction with the SMBus IP Driver is compliant to the System +Management Bus Specification, version 3.2, January 2022 with the following exceptions: + +- The Quick Command bus protocol is not supported by the SMBus IP for Target device operation. + +Architecture Overview +===================== + +The block diagram below gives a high level overview of the logical structure of the SMBus IP. + +.. image:: images/smbus_architecture.svg + +AXI4-Lite Interface +------------------- + +The SMBus IP implements a 32-bit AXI4-Lite Subordinate interface that provides an external +processor with memory mapped access to internal register space. The Descriptor/Receive FIFOs and +control/status registers that are present within the IP are all accessed via this interface. + +Controller Receive FIFO +----------------------- + +The Controller Receive FIFO stores bytes that are received by the SMBus IP during Controller Read +operations until the processor is ready to read and process theses bytes. The FIFO is arranged as +8-bits x 64 and incorporates a processor programmable fill threshold interrupt that may be +configured in order to regulate the rate at which the processor is notified about available data. + +Controller Descriptor FIFO +-------------------------- + +The Controller Descriptor FIFO is used to store the sequence descriptors that are written via the +processor interface until they can be executed by the Controller Sequence Control function. Each +sequence descriptor instructs the IP to execute a portion of an SMBus packet and may be combined +to form any of the Bus Protocols defined in the SMBus Specification. + +Controller CSR and Interrupt Control +------------------------------------ + +The Controller Control and Status Registers (CSR) implements the internal control/status registers +associated with the Controller Sequence Control function. Relevant semi-static control registers +are configured in this function, whereas dynamic control is performed using the sequence +descriptors. Interrupt configuration for the interrupt sources generated by the Controller +Sequence Control function are also managed within this function. + +Controller Sequence Control +--------------------------- + +The Controller Sequence Control function operates as an SMBus Controller and works in tandem with +the SMBus PHY in order to generate the SMBus packet as directed in the received sequence +descriptors. The primary functions performed within the Controller Sequence Control function +includes: + +- Reading the Controller Descriptor FIFO and processing the sequence descriptor +- Instructing the PHY on when to transmit START/REPEATED-START/STOP conditions on the SMBus +- Providing the PHY with transmit bytes during the Controller Write sequences +- Reading the assembled received bytes from the PHY during a Controller Read sequence and writing + into the Receive FIFO +- Performing PEC byte generation and insertion during Controller Write sequences +- Performing PEC byte integrity checking on received packets during Controller Read sequences +- Status interrupt generation based on events occurring during Read/Write sequences + +Target Receive FIFO +------------------- + +The Target Receive FIFO stores bytes that are received by the SMBus IP during Target Write +operations until the processor is ready to read and process theses bytes. The FIFO is arranged as +8-bits x 64 and incorporates a processor programmable fill threshold interrupt that may be +configured in order to regulate the rate at which the processor is notified about available data. + +Target Descriptor FIFO +---------------------- + +The Target Descriptor FIFO is used to store the sequence descriptors that are written via the +processor interface until they can be executed by the Target Sequence Control function. Each +sequence descriptor instructs the IP on how to respond during a Read or Write initiated by an +external Controller. + +Target CSR and Interrupt Control +-------------------------------- + +The Target Control and Status Registers (CSR) implements the internal control/status registers +associated with the Target Sequence Control function. Relevant semi-static control registers are +configured in this function, whereas dynamic control is performed using the sequence descriptors. +Interrupt configuration for the interrupt sources generated by the Target Sequence Control +function are also managed within this function. + +Target Sequence Control +----------------------- + +The Target Sequence Control function operates as a multi-device SMBus Target that supports +operation as up to 8 different devices, each target device address is run time configurable by the +processor via the AXI4-Lite interface. The primary functions performed within the Target Sequence +Control function includes: + +- Performing a comparison check on the address received by the PHY following a START condition, + against the configured target addresses of interest +- Reading the Target Descriptor FIFO and processing the sequence descriptor +- Instructing the PHY whether to ACK or NACK a receive byte during a Target Write sequence based + on the descriptor +- Writing received bytes from the PHY into the Receive FIFO +- Providing the PHY with transmit bytes during Target Read sequences based on the payload byte + contained in the sequence descriptor +- Performing PEC byte integrity checking on received packets during Target Write sequences +- Performing PEC byte generation and insertion during Target Read sequences +- Status interrupt generation based on events occurring during Read/Write sequences + +SMBus PHY +--------- + +The SMBus PHY provides the physical layer interfacing to the SMBus when connected via Input/Output +Buffers in an appropriately configured HDIO bank. The primary functions performed within the SMBus +PHY includes: + +- SMBCLK/SMBDAT input retiming onto the s_axi_aclk domain and noise suppression for glitches <50ns + period +- SMBCLK/SMBDAT input low timeout and bus idle detection +- SMBCLK/SMBDAT output/tri-state control +- SMBCLK output low force +- Tracking of SMBus state in conjunction with the Target Sequence Control function +- Performing SMBCLK clock stretching as a Target when awaiting instruction from the Target Sequence + Control function +- Transmission of ACK/NACK as a Target-transmitter in accordance with the SMBus AC Specifications +- Assembly of receive bytes during Target-receiver operation and forwarding to the Target Sequence + Control function for processing +- Transmission of read data bytes as a Target-transmitter in accordance with the SMBus AC + Specifications +- Loss of arbitration detection during Target-transmitter operation +- Clock generation and synchronization during Controller operation +- START/REPEATED-START/STOP condition transmission as a Controller-transmitter +- Transmission of write data bytes as a Controller-transmitter in accordance with the SMBus AC + Specifications +- Assembly of receive bytes during Controller-receiver operation and forwarding to the Controller + Sequence Control function for processing +- Loss of arbitration detection during Controller-transmitter operation +- Controller Tlow:TEXT timeout detection and Tlow:CEXT measurement +- Target Tlow:TEXT measurement + +Sequence Descriptors +-------------------- + +The SMBus IP is primarily controlled using a set of descriptors, these descriptor sets are +independent for both the Target and Controller f unctions, however the high level behavior is +similar. A descriptor consists of a 4-bit ID that instructs the IP on what action to take on the +SMBus, along with a payload byte that must be supplied when operating as a transmitter. + +Descriptors must be written in the order in which they are to be executed via the AXI4-Lite +processor interface to either the Target or Controller Descriptor FIFOs. When the SMBus IP is +active for either Target or Controller operation, then it will read and process each descriptor at +the appropriate time during either transmission or reception of a SMBus packet. While the IP waits +for descriptors, it will perform smbclk clock stretching in order to back-pressure the SMBus until +such time that software has determined the next steps and provided the next descriptor. + +For scenarios where data on the SMBus must be processed on a byte by byte basis (e.g. Target ARP), +then typically only a single descriptor would be supplied at any one time. The IP would execute the +descriptor, notify any required response via interrupt, write received data into the Receive FIFO +(if applicable) and then begin to clock stretch until software has processed the response and +supplied another descriptor. + +In other scenarios the sequence of events is known in advance by software, for this the set of +descriptors can be written to the Descriptor FIFOs and the IP will process each descriptor without +performing any clock stretching. This approach attempts to minimize the amount of software +involvement during packet transmission/reception and in turn reduces the amount of clock stretching +necessary and the associated risk of exceeding the various clock low extension timeouts outlined in +the SMBus Specification e.g. tTIMEOUT, tLOW:TEXT, tLOW:CEXT. + +Resource Use +============ + +The table below contains resource utilization data for several configurations of the SMBus IP core. +Each row within the table describes a test case. The columns are divided into test parameters and +results. The test parameters include the part information and the core-specific configuration +parameters. Any configuration parameters that are not listed have their default values; any +parameters with a blank value are disabled or set automatically by the IP core. + +- Resource figures are taken from the utilization report issued at the end of implementation using + the Out-of-Context flow in Vivado Design Suite. +- The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct + hold timing closure: these properties are enabled using the Tcl command: + set_param ips.includeClockLocationConstraints true +- The frequencies used for clock inputs are stated for each test case. +- LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory. +- Default Vivado Design Suite 2023.2 settings were used. You may be able to improve on these + figures using different settings. Because surrounding circuitry will affect placement and timing, + no guarantee can be given that these figures will be repeatable in a larger design. + +.. csv-table:: SMBus IP Resource Usage + :header: Vivado Release,Family,Device,Package,Speedgrade,Configuration Name,NUM_TARGET_DEVICES,SMBUS_DEV_CLASS,FREQ_HZ_AXI_ACLK,Fixed clocks,LUT,FF,DSP,RAMB36,RAMB18 + :widths: auto + + 2023.2,versal,xcv80,lsva4737,2MHP,"config_0",8,0,95000000,s_axi_aclk=95,1411,16468,0,0,0 + 2023.2,versal,xcv80,lsva4737,2MHP,"config_1",1,0,95000000,s_axi_aclk=95,1360,1605,0,0,0 + 2023.2,versal,xcv80,lsva4737,2MHP,"config_2",8,0,500000000,s_axi_aclk=500,1659,1643,0,0,0 + 2023.2,versal,xcv80,lsva4737,2MHP,"config_3",8,2,500000000,s_axi_aclk=500,1651,1645,0,0,0 + +Interface Descriptions +====================== + +.. list-table:: Interface Descriptions + :header-rows: 1 + :widths: auto + + * - Interface + - Signal + - Direction + - Range + - Clock + - Enablement Dependency + - Description + * - S_AXI + - s_axi_araddr + - Input + - 11:0 + - s_axi_aclk + - true + - AXI4-Lite read address + * - S_AXI + - s_axi_arready + - Output + - scalar + - s_axi_aclk + - true + - AXI4-Lite read address ready + * - S_AXI + - s_axi_arvalid + - Input + - scalar + - s_axi_aclk + - true + - AXI4-Lite read address valid + * - S_AXI + - s_axi_awaddr + - Input + - 11:0 + - s_axi_aclk + - true + - AXI4-Lite write address + * - S_AXI + - s_axi_awready + - Output + - scalar + - s_axi_aclk + - true + - AXI4-Lite write address ready + * - S_AXI + - s_axi_awvalid + - Input + - scalar + - s_axi_aclk + - true + - AXI4-Lite write address valid + * - S_AXI + - s_axi_bready + - Input + - scalar + - s_axi_aclk + - true + - AXI4-Lite write response ready + * - S_AXI + - s_axi_bresp + - Output + - 1:0 + - s_axi_aclk + - true + - AXI4-Lite write response + * - S_AXI + - s_axi_bvalid + - Output + - scalar + - s_axi_aclk + - true + - AXI4-Lite write response valid + * - S_AXI + - s_axi_rdata + - Output + - 31:0 + - s_axi_aclk + - true + - AXI4-Lite read data + * - S_AXI + - s_axi_rready + - Input + - scalar + - s_axi_aclk + - true + - AXI4-Lite read ready + * - S_AXI + - s_axi_rresp + - Output + - 1:0 + - s_axi_aclk + - true + - AXI4-Lite read response + * - S_AXI + - s_axi_rvalid + - Output + - scalar + - s_axi_aclk + - true + - AXI4-Lite read valid + * - S_AXI + - s_axi_wdata + - Input + - 31:0 + - s_axi_aclk + - true + - AXI4-Lite write data + * - S_AXI + - s_axi_wready + - Output + - scalar + - s_axi_aclk + - true + - AXI4-Lite write data ready + * - S_AXI + - s_axi_wstrb + - Input + - 3:0 + - s_axi_aclk + - true + - AXI4-Lite write strobes + * - S_AXI + - s_axi_wvalid + - Input + - scalar + - s_axi_aclk + - true + - AXI4-Lite write data valid + * - s_axi_aclk + - s_axi_aclk + - Input + - scalar + - + - true + - Clock associated with the S_AXI interface + * - s_axi_aresetn + - s_axi_aresetn + - Input + - scalar + - s_axi_aclk + - true + - Active-Low reset associated with the S_AXI interface + * - ip2intc_irpt + - ip2intc_irpt + - Output + - scalar + - s_axi_aclk + - true + - Level High Interrupt + * - SMBUS + - smbclk_i + - Input + - scalar + - Asynchronous + - true + - SMBus clock input + * - SMBUS + - smbclk_o + - Output + - scalar + - s_axi_aclk + - true + - SMBus clock output + * - SMBUS + - smbclk_t + - Output + - scalar + - s_axi_aclk + - true + - SMBus clock output tri-state control + * - SMBUS + - smbdat_i + - Input + - scalar + - Asynchronous + - true + - SMBus data input + * - SMBUS + - smbdat_o + - Output + - scalar + - s_axi_aclk + - true + - SMBus data output + * - SMBUS + - smbdat_t + - Output + - scalar + - s_axi_aclk + - true + - SMBus data output tri-state control + +Clocking +======== + +The SMBus IP operates on the s_axi_aclk clock domain, the smbclk_i/smbdat_i asynchronous inputs are +retimed onto this clock domain internal to the IP. + +The table below outlines the clock frequency ranges supported by the IP. + +.. list-table:: Clock Support + :header-rows: 1 + :widths: auto + + * - Clock Domain + - Min (MHz) + - Max (MHz) + - Description + * - s_axi_aclk + - 95 + - 500 + - Clock used for S_AXI interface and internal core operation. + +Resets +====== + +The SMBus IP is reset on assertion of the s_axi_aresetn active low reset input, this input must be +synchronous to the s_axi_aclk. + +When this reset is asserted, all internal registers are reset to their default values and the +Target/Controller logic is brought back to an idle state. Any active SMBus transactions in progress +by the IP are aborted. + +Interrupts +========== + +The SMBus IP operation is interrupt driven so that control information written via the processor +interface is sufficiently responsive in order to comply with the timeout limits specified in the +SMBus Specification. + +Refer to IRQ_IER/IRQ_ISR registers detailed in the Register Space section for information on the +SMBus IP interrupt sources. + +Register Space +============== + +The table below outlines the layout and descriptions for the memory mapped register space within +the SMBus IP, these registers are accessible via the AXI4-Lite interface. + +Undocumented bits within registers are reserved and are Read-Only. + +.. list-table:: S_AXI Register Space + :header-rows: 1 + :widths: auto + + * - Register Address Offset + - Register Name + - Field Name + - Bit Index + - Default Value + - Attribute + - Field Description + * - 0x000 + - IP_VERSION + - MAJOR_VERSION + - 31:16 + - 1 + - RO + - | IP Major Version + | Returns the IP Major Version + * - 0x000 + - IP_VERSION + - MINOR_VERSION + - 15:0 + - 0 + - RO + - | IP Minor Version + | Returns the IP Minor Version + * - 0x004 + - IP_REVISION + - CORE_REVISION + - 15:0 + - 0 + - RO + - | IP Core Revision + | Returns the IP Core Revision + * - 0x008 + - IP_MAGIC_NUM + - MAGIC_NUMBER + - 31:0 + - 0x534D4273 + - RO + - | IP Magic Number + | Returns a read-only identifier to assist with debug/bring-up. + * - 0x00C + - IP_BUILD_CONFIG_0 + - FREQ_HZ_AXI_ACLK + - 31:0 + - (Note 1) + - RO + - | Input AXI ACLK Frequency + | Returns the value of the FREQ_HZ_AXI_ACLK parameter as configured at build time. + * - 0x010 + - IP_BUILD_CONFIG_1 + - NUM_TARGET_DEVICES + - 7:4 + - (Note 1) + - RO + - | Number of Target Devices supported + | Returns the value of the NUM_TARGET_DEVICES parameter as configured at build time. + * - 0x010 + - IP_BUILD_CONFIG_1 + - SMBUS_DEV_CLASS + - 1:0 + - (Note 1) + - RO + - | Default SMBus Device Class + | Returns the value of the SMBUS_DEV_CLASS parameter as configured at build time. + * - 0x020 + - IRQ_GIE + - ENABLE + - 0:0 + - 0 + - RW + - | Global Interrupt Enable + | When set, interrupts enabled in the IRQ_IER register can assert the ip2intc_irpt interrupt output. + | 0x0 - Disable the interrupt output + | 0x1 - Enable the interrupt output + * - 0x024 + - IRQ_IER + - CTLR_DESC_FIFO_ALMOST_EMPTY + - 15:15 + - 0 + - RW + - | Controller Descriptor FIFO Almost Empty Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_DESC_FIFO_ALMOST_EMPTY field as set. + | 0x0 - CTLR_DESC_FIFO_ALMOST_EMPTY interrupt disabled + | 0x1 - CTLR_DESC_FIFO_ALMOST_EMPTY interrupt enabled + * - 0x024 + - IRQ_IER + - CTLR_RX_FIFO_FILL_THRESHOLD + - 14:14 + - 0 + - RW + - | Controller Receive FIFO Fill Threshold Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_RX_FIFO_FILL_THRESHOLD field as set. + | 0x0 - CTLR_RX_FIFO_FILL_THRESHOLD interrupt disabled + | 0x1 - CTLR_RX_FIFO_FILL_THRESHOLD interrupt enabled + * - 0x024 + - IRQ_IER + - CTLR_DESC_FIFO_EMPTY + - 13:13 + - 0 + - RW + - | Controller Descriptor FIFO Empty Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_DESC_FIFO_EMPTY field as set. + | 0x0 - CTLR_DESC_FIFO_EMPTY interrupt disabled + | 0x1 - CTLR_DESC_FIFO_EMPTY interrupt enabled + * - 0x024 + - IRQ_IER + - CTLR_DONE + - 12:12 + - 0 + - RW + - | Controller Done Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_DONE field as set. + | 0x0 - CTLR_DONE interrupt disabled + | 0x1 - CTLR_DONE interrupt enabled + * - 0x024 + - IRQ_IER + - CTLR_PEC_ERROR + - 11:11 + - 0 + - RW + - | Controller PEC Error Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_PEC_ERROR field as set. + | 0x0 - CTLR_PEC_ERROR interrupt disabled + | 0x1 - CTLR_PEC_ERROR interrupt enabled + * - 0x024 + - IRQ_IER + - CTLR_NACK_ERROR + - 10:10 + - 0 + - RW + - | Controller NACK Error Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_NACK_ERROR field as set. + | 0x0 - CTLR_NACK_ERROR interrupt disabled + | 0x1 - CTLR_NACK_ERROR interrupt enabled + * - 0x024 + - IRQ_IER + - CTLR_LOA + - 9:9 + - 0 + - RW + - | Controller Loss of Arbitration Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_LOA field as set. + | 0x0 - CTLR_LOA interrupt disabled + | 0x1 - CTLR_LOA interrupt enabled + * - 0x024 + - IRQ_IER + - TGT_DESC_FIFO_ALMOST_EMPTY + - 8:8 + - 0 + - RW + - | Target Descriptor FIFO Almost Empty Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_DESC_FIFO_ALMOST_EMPTY field as set. + | 0x0 - TGT_DESC_FIFO_ALMOST_EMPTY interrupt disabled + | 0x1 - TGT_DESC_FIFO_ALMOST_EMPTY interrupt enabled + * - 0x024 + - IRQ_IER + - TGT_WRITE + - 7:7 + - 0 + - RW + - | Target Write Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_WRITE field as set. + | 0x0 - TGT_WRITE interrupt disabled + | 0x1 - TGT_WRITE interrupt enabled + * - 0x024 + - IRQ_IER + - TGT_READ + - 6:6 + - 0 + - RW + - | Target Read Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_READ field as set. + | 0x0 - TGT_READ interrupt disabled + | 0x1 - TGT_READ interrupt enabled + * - 0x024 + - IRQ_IER + - TGT_RX_FIFO_FILL_THRESHOLD + - 5:5 + - 0 + - RW + - | Target Receive FIFO Fill Threshold Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_RX_FIFO_FILL_THRESHOLD field as set. + | 0x0 - TGT_RX_FIFO_FILL_THRESHOLD interrupt disabled + | 0x1 - TGT_RX_FIFO_FILL_THRESHOLD interrupt enabled + * - 0x024 + - IRQ_IER + - TGT_DESC_FIFO_EMPTY + - 4:4 + - 0 + - RW + - | Target Descriptor FIFO Empty Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_DESC_FIFO_EMPTY field as set. + | 0x0 - TGT_DESC_FIFO_EMPTY interrupt disabled + | 0x1 - TGT_DESC_FIFO_EMPTY interrupt enabled + * - 0x024 + - IRQ_IER + - TGT_DONE + - 3:3 + - 0 + - RW + - | Target Done Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_DONE field as set. + | 0x0 - TGT_DONE interrupt disabled + | 0x1 - TGT_DONE interrupt enabled + * - 0x024 + - IRQ_IER + - TGT_PEC_ERROR + - 2:2 + - 0 + - RW + - | Target PEC Error Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_PEC_ERROR field as set. + | 0x0 - TGT_PEC_ERROR interrupt disabled + | 0x1 - TGT_PEC_ERROR interrupt enabled + * - 0x024 + - IRQ_IER + - TGT_LOA + - 1:1 + - 0 + - RW + - | Target Loss of Arbitration Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_LOA field as set. + | 0x0 - TGT_LOA interrupt disabled + | 0x1 - TGT_LOA interrupt enabled + * - 0x024 + - IRQ_IER + - ERROR_IRQ + - 0:0 + - 0 + - RW + - | Error Interrupt Enable + | When set, an interrupt will be generated when the IRQ_ISR register reports the ERROR_IRQ field as set. + | 0x0 - ERROR_IRQ interrupt disabled + | 0x1 - ERROR_IRQ interrupt enabled + * - 0x028 + - IRQ_ISR + - CTLR_DESC_FIFO_ALMOST_EMPTY + - 15:15 + - 0 + - W1C + - | Controller Descriptor FIFO Almost Empty Interrupt Status + | Set when the Controller has detected only one descriptor in the Descriptor FIFO and a transaction is in progress. + | 0x0 - Controller Descriptor FIFO contains more than one descriptor or no transaction in progress + | 0x1 - Controller Descriptor FIFO only contains one descriptor and a transaction is in progress + * - 0x028 + - IRQ_ISR + - CTLR_RX_FIFO_FILL_THRESHOLD + - 14:14 + - 0 + - W1C + - | Controller Receive FIFO Fill Threshold Interrupt Status + | Set when the Controller Receive FIFO has reached the fill level configured in the CTLR_RX_FIFO_FILL_THRESHOLD register. + | 0x0 - Controller Receive FIFO fill level below configured threshold + | 0x1 - Controller Receive FIFO has reached the configured fill threshold + * - 0x028 + - IRQ_ISR + - CTLR_DESC_FIFO_EMPTY + - 13:13 + - 0 + - W1C + - | Controller Descriptor FIFO Empty Interrupt Status + | Set when the Controller has detected the Descriptor FIFO is empty and another descriptor is required. + | 0x0 - Controller Descriptor FIFO not empty or descriptor not required + | 0x1 - Controller Descriptor FIFO empty and a descriptor is required + * - 0x028 + - IRQ_ISR + - CTLR_DONE + - 12:12 + - 0 + - W1C + - | Controller Done Interrupt Status + | Set when the Controller has successfully completed the transaction. + | 0x0 - Controller transaction not complete or no transaction in progress + | 0x1 - Controller transaction is complete + * - 0x028 + - IRQ_ISR + - CTLR_PEC_ERROR + - 11:11 + - 0 + - W1C + - | Controller PEC Error Interrupt Status + | Set when the Controller has detected a PEC error during a Read transaction with PEC enabled. + | 0x0 - No PEC error + | 0x1 - PEC error detected during Read + * - 0x028 + - IRQ_ISR + - CTLR_NACK_ERROR + - 10:10 + - 0 + - W1C + - | Controller NACK Error Interrupt Status + | Set when the Controller has received a NACK response from the Target following transmission of a byte as Controller-transmitter. + | 0x0 - No NACK response from Target + | 0x1 - Target responded with NACK + * - 0x028 + - IRQ_ISR + - CTLR_LOA + - 9:9 + - 0 + - W1C + - | Controller Loss of Arbitration Interrupt Status + | Set when the Controller has detected loss of arbitration as a Controller-transmitter. + | 0x0 - No loss of arbitration detected + | 0x1 - Loss of arbitration detected + * - 0x028 + - IRQ_ISR + - TGT_DESC_FIFO_ALMOST_EMPTY + - 8:8 + - 0 + - W1C + - | Target Descriptor FIFO Almost Empty Interrupt Status + | Set when the Target has detected only one descriptor in the Descriptor FIFO and a transaction is in progress + | 0x0 - Target Descriptor FIFO contains more than one descriptor or no transaction in progress + | 0x1 - Target Descriptor FIFO only contains one descriptor and a transaction is in progress + * - 0x028 + - IRQ_ISR + - TGT_WRITE + - 7:7 + - 0 + - W1C + - | Target Write Interrupt Status + | Set when the Target has detected a start of write transaction for a Target device enabled in TGT_CONTROL_[7:0] + | 0x0 - No write detected matching an enabled target device + | 0x1 - Start of write detected matching an enabled target device, details available in TGT_STATUS + * - 0x028 + - IRQ_ISR + - TGT_READ + - 6:6 + - 0 + - W1C + - | Target Read Interrupt Status + | Set when the Target has detected a start of read transaction for a Target device enabled in TGT_CONTROL_[7:0] + | 0x0 - No read detected matching an enabled target device + | 0x1 - Start of read detected matching an enabled target device, details available in TGT_STATUS + * - 0x028 + - IRQ_ISR + - TGT_RX_FIFO_FILL_THRESHOLD + - 5:5 + - 0 + - W1C + - | Target Receive FIFO Fill Threshold Interrupt Status + | Set when the Target Receive FIFO has reached the fill level configured in the TGT_RX_FIFO_FILL_THRESHOLD register + | 0x0 - Target Receive FIFO fill level below configured threshold + | 0x1 - Target Receive FIFO has reached the configured fill threshold + * - 0x028 + - IRQ_ISR + - TGT_DESC_FIFO_EMPTY + - 4:4 + - 0 + - W1C + - | Target Descriptor FIFO Empty Interrupt Status + | Set when the Target has detected the Descriptor FIFO is empty and another descriptor is required + | 0x0 - Target Descriptor FIFO not empty or descriptor not required + | 0x1 - Target Descriptor FIFO empty and a descriptor is required + * - 0x028 + - IRQ_ISR + - TGT_DONE + - 3:3 + - 0 + - W1C + - | Target Done Interrupt Status + | Target has detected a STOP condition, transaction is complete and no PEC error detected (if write, if applicable) + | 0x0 - Target transaction not done + | 0x1 - Target transaction done + * - 0x028 + - IRQ_ISR + - TGT_PEC_ERROR + - 2:2 + - 0 + - W1C + - | Target PEC Error Interrupt Status + | Set when the Target has detected a STOP condition, transaction is complete but PEC error detected (only applicable to Writes) + | 0x0 - Target transaction not done + | 0x1 - Target transaction done, but PEC error detected + * - 0x028 + - IRQ_ISR + - TGT_LOA + - 1:1 + - 0 + - W1C + - | Target Loss of Arbitration Interrupt Status + | When set the Target has detected loss of arbitration as a Target-transmitter + | 0x0 - No loss of arbitration detected + | 0x1 - Loss of arbitration detected + * - 0x028 + - IRQ_ISR + - ERROR_IRQ + - 0:0 + - 0 + - W1C + - | Error Interrupt Status + | Set when an error condition has occurred that is both enabled in the ERR_IRQ_IER register and set in the ERR_IRQ_ISR register. + | 0x0 - No error condition detected + | 0x1 - Error condition detected + * - 0x02C + - ERR_IRQ_IER + - PHY_CTLR_CEXT_TIMEOUT + - 19:19 + - 0 + - RW + - | Controller PHY CEXT Timeout Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the PHY_CTLR_CEXT_TIMEOUT field as set. + | 0x0 - PHY_CTLR_CEXT_TIMEOUT interrupt disabled + | 0x1 - PHY_CTLR_CEXT_TIMEOUT interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - PHY_CTLR_TEXT_TIMEOUT + - 18:18 + - 0 + - RW + - | Controller PHY TEXT Timeout Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the PHY_CTLR_TEXT_TIMEOUT field as set. + | 0x0 - PHY_CTLR_TEXT_TIMEOUT interrupt disabled + | 0x1 - PHY_CTLR_TEXT_TIMEOUT interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - CTLR_RX_FIFO_ERROR + - 17:17 + - 0 + - RW + - | Controller Receive FIFO Error Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_RX_FIFO_ERROR field as set. + | 0x0 - CTLR_RX_FIFO_ERROR interrupt disabled + | 0x1 - CTLR_RX_FIFO_ERROR interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - CTLR_RX_FIFO_OVERFLOW + - 16:16 + - 0 + - RW + - | Controller Receive FIFO Overflow Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_RX_FIFO_OVERFLOW field as set. + | 0x0 - CTLR_RX_FIFO_OVERFLOW interrupt disabled + | 0x1 - CTLR_RX_FIFO_OVERFLOW interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - CTLR_RX_FIFO_UNDERFLOW + - 15:15 + - 0 + - RW + - | Controller Receive FIFO Underflow Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_RX_FIFO_UNDERFLOW field as set. + | 0x0 - CTLR_RX_FIFO_UNDERFLOW interrupt disabled + | 0x1 - CTLR_RX_FIFO_UNDERFLOW interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - CTLR_DESC_FIFO_ERROR + - 14:14 + - 0 + - RW + - | Controller Descriptor FIFO Error Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_DESC_FIFO_ERROR field as set. + | 0x0 - CTLR_DESC_FIFO_ERROR interrupt disabled + | 0x1 - CTLR_DESC_FIFO_ERROR interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - CTLR_DESC_FIFO_OVERFLOW + - 13:13 + - 0 + - RW + - | Controller Descriptor FIFO Overflow Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_DESC_FIFO_OVERFLOW field as set. + | 0x0 - CTLR_DESC_FIFO_OVERFLOW interrupt disabled + | 0x1 - CTLR_DESC_FIFO_OVERFLOW interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - CTLR_DESC_FIFO_UNDERFLOW + - 12:12 + - 0 + - RW + - | Controller Descriptor FIFO Underflow Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_DESC_FIFO_UNDERFLOW field as set. + | 0x0 - CTLR_DESC_FIFO_UNDERFLOW interrupt disabled + | 0x1 - CTLR_DESC_FIFO_UNDERFLOW interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - CTLR_DESC_ERROR + - 11:11 + - 0 + - RW + - | Controller Descriptor Error Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_DESC_ERROR field as set. + | 0x0 - CTLR_DESC_ERROR interrupt disabled + | 0x1 - CTLR_DESC_ERROR interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - PHY_TGT_TEXT_TIMEOUT + - 10:10 + - 0 + - RW + - | Target PHY TEXT Timeout Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the PHY_TGT_TEXT_TIMEOUT field as set. + | 0x0 - PHY_TGT_TEXT_TIMEOUT interrupt disabled + | 0x1 - PHY_TGT_TEXT_TIMEOUT interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - TGT_RX_FIFO_ERROR + - 9:9 + - 0 + - RW + - | Target Receive FIFO Error Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_RX_FIFO_ERROR field as set. + | 0x0 - TGT_RX_FIFO_ERROR interrupt disabled + | 0x1 - TGT_RX_FIFO_ERROR interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - TGT_RX_FIFO_OVERFLOW + - 8:8 + - 0 + - RW + - | Target Receive FIFO Overflow Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_RX_FIFO_OVERFLOW field as set. + | 0x0 - TGT_RX_FIFO_OVERFLOW interrupt disabled + | 0x1 - TGT_RX_FIFO_OVERFLOW interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - TGT_RX_FIFO_UNDERFLOW + - 7:7 + - 0 + - RW + - | Target Receive FIFO Underflow Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_RX_FIFO_UNDERFLOW field as set. + | 0x0 - TGT_RX_FIFO_UNDERFLOW interrupt disabled + | 0x1 - TGT_RX_FIFO_UNDERFLOW interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - TGT_DESC_FIFO_ERROR + - 6:6 + - 0 + - RW + - | Target Descriptor FIFO Error Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_DESC_FIFO_ERROR field as set. + | 0x0 - TGT_DESC_FIFO_ERROR interrupt disabled + | 0x1 - TGT_DESC_FIFO_ERROR interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - TGT_DESC_FIFO_OVERFLOW + - 5:5 + - 0 + - RW + - | Target Descriptor FIFO Overflow Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_DESC_FIFO_OVERFLOW field as set. + | 0x0 - TGT_DESC_FIFO_OVERFLOW interrupt disabled + | 0x1 - TGT_DESC_FIFO_OVERFLOW interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - TGT_DESC_FIFO_UNDERFLOW + - 4:4 + - 0 + - RW + - | Target Descriptor FIFO Underflow Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_DESC_FIFO_UNDERFLOW field as set. + | 0x0 - TGT_DESC_FIFO_UNDERFLOW interrupt disabled + | 0x1 - TGT_DESC_FIFO_UNDERFLOW interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - TGT_DESC_ERROR + - 3:3 + - 0 + - RW + - | Target Descriptor Error Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_DESC_ERROR field as set. + | 0x0 - TGT_DESC_ERROR interrupt disabled + | 0x1 - TGT_DESC_ERROR interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - PHY_UNEXPTD_BUS_IDLE + - 2:2 + - 0 + - RW + - | PHY Unexpected Bus Idle Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the PHY_UNEXPTD_BUS_IDLE field as set. + | 0x0 - PHY_UNEXPTD_BUS_IDLE interrupt disabled + | 0x1 - PHY_UNEXPTD_BUS_IDLE interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - PHY_SMBDAT_LOW_TIMEOUT + - 1:1 + - 0 + - RW + - | PHY SMBDAT Low Timeout Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the PHY_SMBDAT_LOW_TIMEOUT field as set. + | 0x0 - PHY_SMBDAT_LOW_TIMEOUT interrupt disabled + | 0x1 - PHY_SMBDAT_LOW_TIMEOUT interrupt enabled + * - 0x02C + - ERR_IRQ_IER + - PHY_SMBCLK_LOW_TIMEOUT + - 0:0 + - 0 + - RW + - | PHY SMBCLK Low Timeout Interrupt Enable + | When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the PHY_SMBCLK_LOW_TIMEOUT field as set. + | 0x0 - PHY_SMBCLK_LOW_TIMEOUT interrupt disabled + | 0x1 - PHY_SMBCLK_LOW_TIMEOUT interrupt enabled + * - 0x030 + - ERR_IRQ_ISR + - PHY_CTLR_CEXT_TIMEOUT + - 19:19 + - 0 + - W1C + - | Controller PHY CEXT Timeout Interrupt Status + | Set when the Controller PHY has detected SMBCLK stretching performed by the Controller function beyond the threshold configured in the PHY_CTLR_CEXT_TIMEOUT register. + | 0x0 - Controller function clock stretching has not exceeded threshold + | 0x1 - Controller function clock stretching has exceeded the threshold + * - 0x030 + - ERR_IRQ_ISR + - PHY_CTLR_TEXT_TIMEOUT + - 18:18 + - 0 + - W1C + - | Controller PHY TEXT Timeout Interrupt Status + | Set when the Controller has detected SMBCLK stretching performed by an external Target beyond the threshold configured in the PHY_CTLR_TEXT_TIMEOUT register. + | 0x0 - Controller function has not detected Target clock stretching that exceeds the threshold + | 0x1 - Controller function has detected Target clock stretching that exceeds the threshold + * - 0x030 + - ERR_IRQ_ISR + - CTLR_RX_FIFO_ERROR + - 17:17 + - 0 + - W1C + - | Controller Receive FIFO Error Interrupt Status + | Set when the Controller has detected that an attempt to read or write to the Receive FIFO while it is in reset has been made. + | 0x0 - No Receive FIFO read/write error detected + | 0x1 - Receive FIFO read/write error detected + * - 0x030 + - ERR_IRQ_ISR + - CTLR_RX_FIFO_OVERFLOW + - 16:16 + - 0 + - W1C + - | Controller Receive FIFO Overflow Interrupt Status + | Set when the Controller has detected the Receive FIFO has overflowed. + | 0x0 - No Receive FIFO overflow detected + | 0x1 - Receive FIFO overflow detected + * - 0x030 + - ERR_IRQ_ISR + - CTLR_RX_FIFO_UNDERFLOW + - 15:15 + - 0 + - W1C + - | Controller Receive FIFO Underflow Interrupt Status + | Set when the Controller has detected the Receive FIFO has underflowed. + | 0x0 - No Receive FIFO underflow detected + | 0x1 - Receive FIFO underflow detected + * - 0x030 + - ERR_IRQ_ISR + - CTLR_DESC_FIFO_ERROR + - 14:14 + - 0 + - W1C + - | Controller Descriptor FIFO Error Interrupt Status + | Set when the Controller has detected that an attempt to write to the Descriptor FIFO while it is in reset has been made. + | 0x0 - No Descriptor FIFO write error detected + | 0x1 - Descriptor FIFO write error detected + * - 0x030 + - ERR_IRQ_ISR + - CTLR_DESC_FIFO_OVERFLOW + - 13:13 + - 0 + - W1C + - | Controller Descriptor FIFO Overflow Interrupt Status + | Set when the Controller has detected the Descriptor FIFO has overflowed. + | 0x0 - No Descriptor FIFO overflow detected + | 0x1 - Descriptor FIFO overflow detected + * - 0x030 + - ERR_IRQ_ISR + - CTLR_DESC_FIFO_UNDERFLOW + - 12:12 + - 0 + - W1C + - | Controller Descriptor FIFO Underflow Interrupt Status + | Set when the Controller has detected the Descriptor FIFO has underflowed. + | 0x0 - No Descriptor FIFO underflow detected + | 0x1 - Descriptor FIFO underflow detected + * - 0x030 + - ERR_IRQ_ISR + - CTLR_DESC_ERROR + - 11:11 + - 0 + - W1C + - | Controller Descriptor Error Interrupt Status + | Set when the Controller has received an invalid descriptor ID via the Descriptor FIFO or the first descriptor in the sequence is not a START descriptor. + | 0x0 - No descriptor error detected + | 0x1 - Descriptor error detected + * - 0x030 + - ERR_IRQ_ISR + - PHY_TGT_TEXT_TIMEOUT + - 10:10 + - 0 + - W1C + - | Target PHY TEXT Timeout Interrupt Status + | Set when the PHY has detected SMBCLK stretching performed by the Target function beyond the threshold configured in the PHY_TGT_TEXT_TIMEOUT register. + | 0x0 - Target function clock stretching has not exceeded threshold + | 0x1 - Target function clock stretching has exceeded the threshold + * - 0x030 + - ERR_IRQ_ISR + - TGT_RX_FIFO_ERROR + - 9:9 + - 0 + - W1C + - | Target Receive FIFO Error Interrupt Status + | Set when the Target has detected that an attempt to read or write to the Receive FIFO whilst it is in reset has been made. + | 0x0 - No Receive FIFO read/write error detected + | 0x1 - Receive FIFO read/write error detected + * - 0x030 + - ERR_IRQ_ISR + - TGT_RX_FIFO_OVERFLOW + - 8:8 + - 0 + - W1C + - | Target Receive FIFO Overflow Interrupt Status + | Set when the Target has detected the Receive FIFO has overflowed + | 0x0 - No Receive FIFO overflow detected + | 0x1 - Receive FIFO overflow detected + * - 0x030 + - ERR_IRQ_ISR + - TGT_RX_FIFO_UNDERFLOW + - 7:7 + - 0 + - W1C + - | Target Receive FIFO Underflow Interrupt Status + | Set when the Target has detected the Receive FIFO has underflowed + | 0x0 - No Receive FIFO underflow detected + | 0x1 - Receive FIFO underflow detected + * - 0x030 + - ERR_IRQ_ISR + - TGT_DESC_FIFO_ERROR + - 6:6 + - 0 + - W1C + - | Target Descriptor FIFO Error Interrupt Status + | Set when the Target has detected that an attempt to write to the Descriptor FIFO whilst it is in reset has been made. + | 0x0 - No Descriptor FIFO write error detected + | 0x1 - Descriptor FIFO write error detected + * - 0x030 + - ERR_IRQ_ISR + - TGT_DESC_FIFO_OVERFLOW + - 5:5 + - 0 + - W1C + - | Target Descriptor FIFO Overflow Interrupt Status + | Set when the Target has detected the Descriptor FIFO has overflowed + | 0x0 - No Descriptor FIFO overflow detected + | 0x1 - Descriptor FIFO overflow detected + * - 0x030 + - ERR_IRQ_ISR + - TGT_DESC_FIFO_UNDERFLOW + - 4:4 + - 0 + - W1C + - | Target Descriptor FIFO Underflow Interrupt Status + | Set when the Target has detected the Descriptor FIFO has underflowed + | 0x0 - No Descriptor FIFO underflow detected + | 0x1 - Descriptor FIFO underflow detected + * - 0x030 + - ERR_IRQ_ISR + - TGT_DESC_ERROR + - 3:3 + - 0 + - W1C + - | Target Descriptor Error Interrupt Status + | Set when the Target has received an invalid descriptor via the Descriptor FIFO. + | This is asserted when either an undefined descriptor ID or unexpected type (e.g. read descriptor during a write) is received. + | 0x0 - No descriptor error detected + | 0x1 - Descriptor error detected + * - 0x030 + - ERR_IRQ_ISR + - PHY_UNEXPTD_BUS_IDLE + - 2:2 + - 0 + - W1C + - | PHY Unexpected Bus Idle Interrupt Status + | Set when the PHY has detected an unexpected bus idle condition by observing SMBCLK/SMBDAT inputs high beyond the threshold configured in the PHY_IDLE_THRESHOLD register, whilst a transaction is in progress (i.e. no STOP condition). + | 0x0 - No unexpected bus idle detected + | 0x1 - Unexpected bus idle condition detected + * - 0x030 + - ERR_IRQ_ISR + - PHY_SMBDAT_LOW_TIMEOUT + - 1:1 + - 0 + - W1C + - | PHY SMBDAT Low Timeout Interrupt Status + | Set when the PHY has detected SMBDAT persistently low following a rising edge on SMBCLK for the timeout value configured in the PHY_TIMEOUT_MAX register. + | 0x0 - No SMBDAT low timeout + | 0x1 - SMBDAT low timeout detected + * - 0x030 + - ERR_IRQ_ISR + - PHY_SMBCLK_LOW_TIMEOUT + - 0:0 + - 0 + - W1C + - | PHY SMBCLK Low Timeout Interrupt Status + | Set when the PHY has detected SMBCLK persistently low for the timeout value configured in the PHY_TIMEOUT_MIN register. + | 0x0 - No SMBCLK low timeout + | 0x1 - SMBCLK low timeout detected + * - 0x034 + - IRQ_ISR_FORCE + - IRQ_ISR_FORCE + - 15:0 + - 0 + - WO + - | Debug IRQ ISR Force + | Debug - When set, the equivalent bit in the IRQ_ISR register is set to '1' in order to force assertion of the interrupt source. + | 0x0 - No forced assertion of the equivalent bit in IRQ_ISR register + | 0x1 - Equivalent bit in the IRQ_ISR register is forced to '1' + * - 0x038 + - ERR_IRQ_ISR_FORCE + - ERR_IRQ_ISR_FORCE + - 19:0 + - 0 + - WO + - | Debug Error IRQ ISR Force + | Debug - When set, the equivalent bit in the ERR_IRQ_ISR register is set to '1' in order to force assertion of the interrupt source. + | 0x0 - No forced assertion of the equivalent bit in ERR_IRQ_ISR register + | 0x1 - Equivalent bit in the ERR_IRQ_ISR register is forced to '1' + * - 0x200 + - PHY_STATUS + - SMBDAT_LOW_TIMEOUT + - 2:2 + - 0 + - RO + - | SMBDAT Low Timeout Status + | Indicates when the SMBus PHY has detected a SMBDAT low timeout in accordance with the threshold configured in the PHY_TIMEOUT_MAX register. + | 0x0 - SMBDAT low timeout not detected + | 0x1 - SMBDAT low timeout detected + * - 0x200 + - PHY_STATUS + - SMBCLK_LOW_TIMEOUT + - 1:1 + - 0 + - RO + - | SMBCLK Low Timeout Status + | Indicates when the SMBus PHY has detected a SMBCLK low timeout in accordance with the threshold configured in the PHY_TIMEOUT_MIN register. + | 0x0 - SMBCLK low timeout not detected + | 0x1 - SMBCLK low timeout detected + * - 0x200 + - PHY_STATUS + - BUS_IDLE + - 0:0 + - 0 + - RO + - | Bus Idle Status + | Indicates when the SMBus PHY has detected the Bus Idle condition + | 0x0 - Bus Idle condition not detected + | 0x1 - Bus is Idle + * - 0x204 + - PHY_FILTER_CONTROL + - ENABLE + - 31:31 + - 1 + - RW + - | Input Glitch Filter Enable + | Enable the SMBCLK/SMBDAT input glitch filter + | 0x0 - Input glitch filter disabled + | 0x1 - Input glitch filter enabled + * - 0x204 + - PHY_FILTER_CONTROL + - DURATION + - 4:0 + - (Note 1) + - RW + - | Input Glitch Filter Duration + | Configure the duration that the SMBCLK or SMBDAT inputs must be stable for before registering as a change in state. + | This value is calculated as Time = s_axi_aclk period x (DURATION + 1) + | This value must be configured to meet tSPIKE:MAX in accordance with the SMBus Specification. + * - 0x208 + - PHY_BUS_FREE_TIME + - BUS_FREE_TIME + - 11:0 + - (Note 1) + - RW + - | Bus Free Time Control + | Configure the amount of time to wait following detection of a STOP condition before declaring a bus idle condition. + | This value is calculated as Time = s_axi_aclk period x (BUS_FREE_TIME + 1) + | This value must be configured to meet tBUF:MIN in accordance with the SMBus Specification. + * - 0x20C + - PHY_IDLE_THRESHOLD + - IDLE_THRESHOLD + - 14:0 + - (Note 1) + - RW + - | Bus Idle Time Control + | Configure the amount of time that both SMBCLK and SMBDAT must be high before declaring a bus idle condition. + | This value is calculated as Time = s_axi_aclk period x (IDLE_THRESHOLD + 1) + | This value must be configured to meet tHIGH:MAX in accordance with the SMBus Specification. + * - 0x210 + - PHY_TIMEOUT_PRESCALER + - TIMEOUT_PRESCALER + - 12:0 + - (Note 1) + - RW + - | Timeout Prescaler Configuration + | Configure the amount of time to wait before incrementing either the PHY_TIMEOUT_MIN or PHY_TIMEOUT_MAX counters. + | This value is calculated as Prescaler_Time = s_axi_aclk period x (TIMEOUT_PRESCALER + 1) + | The Prescaler_Time should be configured for 10us in order to stay within range of the PHY_TIMEOUT_MIN and PHY_TIMEOUT_MAX counters. + * - 0x214 + - PHY_TIMEOUT_MIN + - TIMEOUT_ENABLE + - 31:31 + - 1 + - RW + - | Minimum Timeout Detection Enable + | Enable/disable the SMBCLK low timeout detection and subsequent consequent actions. + | 0x0 - SMBCLK low timeout detection disabled + | 0x1 - SMBCLK low timeout detection enabled + * - 0x214 + - PHY_TIMEOUT_MIN + - TIMEOUT_MIN + - 11:0 + - (Note 1) + - RW + - | Minimum Timeout Configuration + | Configure the threshold used to detect a SMBCLK low timeout and trigger the PHY_SMBCLK_TIMEOUT interrupt. + | This value must be configured to meet tTIMEOUT:MIN in accordance with the SMBus Specification. + | This value is calculated as Timeout_Min_Time = ((TIMEOUT_MIN + 1) x Prescaler_Time) - Prescaler_Time + * - 0x218 + - PHY_TIMEOUT_MAX + - TIMEOUT_MAX + - 11:0 + - (Note 1) + - RW + - | Maximum Timeout Configuration + | Configure the threshold used to detect a SMBDAT low timeout and trigger the PHY_SMBDAT_TIMEOUT interrupt. + | This value must be configured to meet tTIMEOUT:MAX in accordance with the SMBus Specification. + | This value is calculated as Timeout_Max_Time = ((TIMEOUT_MAX + 1) x Prescaler_Time) - Prescaler_Time + * - 0x21C + - PHY_RESET_CONTROL + - SMBCLK_FORCE_TIMEOUT + - 31:31 + - 0 + - WO + - | SMBCLK Timeout Force Control + | Override the SMBCLK low detection to force assertion of this timeout and subsequent consequent actions. + | 0x0 - No SMBCLK low timeout forced assertion + | 0x1 - Force assertion of the SMBCLK low timeout and subsequent consequent actions + * - 0x21C + - PHY_RESET_CONTROL + - SMBCLK_FORCE_LOW + - 11:0 + - 0 + - RW + - | SMBCLK Output Force Control + | Override the PHY control of the SMBCLK and force the output low. + | 0xCFB = SMBCLK force low + | Any other value = SMBCLK under PHY control + * - 0x400 + - PHY_TGT_DATA_SETUP + - TGT_DATA_SETUP + - 9:0 + - (Note 1) + - RW + - | Target PHY Data Setup + | Configure the data setup time when operating as a Target-transmitter post clock stretching. + | This value must be configured to meet tSU:DAT:Min in accordance with the SMBus Specification and account for tR:Max/tF:Max. + | This value is calculated as Setup Time = s_axi_aclk period x (TGT_DATA_SETUP + 1) + * - 0x404 + - PHY_TGT_TEXT_PRESCALER + - TGT_TEXT_PRESCALER + - 8:0 + - (Note 1) + - RW + - | Target PHY TEXT Timeout Prescaler Configuration + | Configure the amount of time to measure before incrementing the PHY_TGT_TEXT_TIMEOUT counter when SMBCLK stretching is active within the Target function. + | This value is calculated as Text_Prescaler_Time = s_axi_aclk period x (TGT_TEXT_PRESCALER+ 1) + | The Text_Prescaler_Time should be configured for 1us in order to stay within range of the PHY_TGT_TEXT_TIMEOUT counter. + * - 0x408 + - PHY_TGT_TEXT_TIMEOUT + - TGT_TEXT_TIMEOUT + - 14:0 + - (Note 1) + - RW + - | Target PHY TEXT Timeout Configuration + | Configure the threshold used to detect that the Target function has exceeded the cumulative clock stretching threshold and trigger the TGT_TEXT_TIMEOUT interrupt. + | This value must be configured to meet tLOW:TEXT in accordance with the SMBus Specification. + | This value is calculated as Text_Timeout_Time = TGT_TEXT_TIMEOUT x Text_Prescaler_Time + * - 0x40C + - PHY_TGT_TEXT_MAX + - TGT_TEXT_MAX + - 14:0 + - 0 + - WC + - | Target PHY TEXT Timeout Max + | Indicates the maximum amount of cumulative time in Text_Prescaler_Time units that the Target function has spent performing SMBCLK stretching during any single transaction (between an initial START and a STOP). + * - 0x410 + - PHY_TGT_DBG_STATE + - DBG_STATE + - 7:0 + - 1 + - RO + - | Target PHY Debug State + | Reports the current Target PHY FSM State to assist with debug. + * - 0x414 + - PHY_TGT_DATA_HOLD + - TGT_DATA_HOLD + - 9:0 + - (Note 1) + - RW + - | Target PHY Data Hold + | Configure the data hold time when operating as a Target-transmitter. + | This value must be configured to meet tHD:DAT:Min in accordance with the SMBus Specification. + | This value is calculated as: + | If PHY_FILTER_CONTROL__ENABLE = 0x1: + | Hold Time = s_axi_aclk period x (TGT_DATA_HOLD + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) + | If PHY_FILTER_CONTROL__ENABLE = 0x0: + | Hold Time = s_axi_aclk period x (TGT_DATA_HOLD + 8) + * - 0x600 + - TGT_STATUS + - ACTIVE + - 8:8 + - 0 + - RO + - | Target Active Status + | Indicates that the Target function has received a transaction that matches an enabled address in TGT_CONTROL_[7:0] + | 0x0 - No active transaction in progress + | 0x1 - Active Target transaction in progress + * - 0x600 + - TGT_STATUS + - ADDRESS + - 7:1 + - 0 + - RO + - | Target Address Status + | Target address for the current transaction, only valid when ACTIVE = 0x1 + * - 0x600 + - TGT_STATUS + - RW + - 0:0 + - 0 + - RO + - | Target Read/Write Status + | Indicates the current transaction type, only valid when ACTIVE = 0x1 + | 0x0 = Write transaction + | 0x1 = Read transaction + * - 0x604 + - TGT_DESC_FIFO + - ID + - 11:8 + - 0 + - WO + - | Target Descriptor ID. Valid IDs are as follows - + | 0x0 - TARGET_WRITE_ACK + | 0x1 - TARGET_WRITE_NACK + | 0x2 - TARGET_WRITE_PEC + | 0x8 - TARGET_READ + | 0x9 - TARGET_READ_PEC + * - 0x604 + - TGT_DESC_FIFO + - PAYLOAD + - 7:0 + - 0 + - WO + - | Target Descriptor Payload + | Data payload for transmission as a Target-transmitter. + | Valid only when ID = 0x8 (TARGET_READ). + * - 0x608 + - TGT_DESC_STATUS + - FILL_LEVEL + - 14:8 + - 0 + - RO + - | Target Descriptor FIFO Fill Level Status + | Indicates the current fill level of the Target Descriptor FIFO. + * - 0x608 + - TGT_DESC_STATUS + - FULL + - 5:5 + - 0 + - RO + - | Target Descriptor FIFO Full Status + | Indicates if the Target Descriptor FIFO is full + | 0x0 - FIFO not full + | 0x1 - FIFO full + * - 0x608 + - TGT_DESC_STATUS + - ALMOST_FULL + - 4:4 + - 0 + - RO + - | Target Descriptor FIFO Almost Full Status + | Indicates if the Target Descriptor FIFO is almost full + | 0x0 - FIFO has space for more than one descriptor + | 0x1 - FIFO only has space for one more descriptor + * - 0x608 + - TGT_DESC_STATUS + - ALMOST_EMPTY + - 1:1 + - 0 + - RO + - | Target Descriptor FIFO Almost Empty Status + | Indicates if the Target Descriptor FIFO is almost empty + | 0x0 - FIFO contains more than one descriptor + | 0x1 - FIFO contains one descriptor or less + * - 0x608 + - TGT_DESC_STATUS + - EMPTY + - 0:0 + - 0 + - RO + - | Target Descriptor FIFO Empty Status + | Indicates if the Target Descriptor FIFO is empty + | 0x0 - FIFO not empty + | 0x1 - FIFO empty + * - 0x60C + - TGT_RX_FIFO + - RESET + - 31:31 + - 0 + - WO + - | Target Receive FIFO Reset Control + | When set the Target Receive FIFO is reset to a known state. + | Poll the RESET_BUSY field in the TGT_RX_FIFO_STATUS register to determine when the reset is complete. + | 0x0 - FIFO not reset + | 0x1 - Reset FIFO + * - 0x60C + - TGT_RX_FIFO + - PAYLOAD + - 7:0 + - 0 + - RC + - | Target Receive Payload Byte + | Reading this register pops a value from the Target Receive FIFO. + * - 0x610 + - TGT_RX_FIFO_STATUS + - MAX_FILL_LEVEL + - 22:16 + - 0 + - W1C + - | Target Receive FIFO Max Fill Level Status + | Indicates the maximum recorded fill level of the Target Receive FIFO. + * - 0x610 + - TGT_RX_FIFO_STATUS + - FILL_LEVEL + - 14:8 + - 0 + - RO + - | Target Receive FIFO Fill Level Status + | Indicates the current fill level of the Target Receive FIFO. + * - 0x610 + - TGT_RX_FIFO_STATUS + - RESET_BUSY + - 6:6 + - 0 + - RO + - | Target Receive FIFO Reset Busy Status + | Indicates if the Target Receive FIFO is currently undergoing a reset and is unavailable for either read or write. + | 0x0 - FIFO not in reset + | 0x1 - FIFO reset in progress + * - 0x610 + - TGT_RX_FIFO_STATUS + - FULL + - 5:5 + - 0 + - RO + - | Target Receive FIFO Full Status + | Indicates if the Target Receive FIFO is full + | 0x0 - FIFO not full + | 0x1 - FIFO full + * - 0x610 + - TGT_RX_FIFO_STATUS + - ALMOST_FULL + - 4:4 + - 0 + - RO + - | Target Receive FIFO Almost Full Status + | Indicates if the Target Receive FIFO is almost full + | 0x0 - FIFO has space for two or more bytes + | 0x1 - FIFO only has space for one more byte + * - 0x610 + - TGT_RX_FIFO_STATUS + - ALMOST_EMPTY + - 1:1 + - 0 + - RO + - | Target Receive FIFO Almost Empty Status + | Indicates if the Target Receive FIFO is almost empty + | 0x0 - FIFO contains more than one byte + | 0x1 - FIFO contains one byte or less + * - 0x610 + - TGT_RX_FIFO_STATUS + - EMPTY + - 0:0 + - 0 + - RO + - | Target Receive FIFO Empty Status + | Indicates if the Target Receive FIFO is empty + | 0x0 - FIFO not empty + | 0x1 - FIFO empty + * - 0x614 + - TGT_RX_FIFO_FILL_THRESHOLD + - FILL_THRESHOLD + - 6:0 + - 1 + - RW + - | Target Receive FIFO Fill Threshold + | Configure the Target Receive FIFO fill threshold that should trigger assertion of the TGT_RX_FIFO_FILL_THRESHOLD interrupt. + * - 0x618 + - TGT_DBG + - FORCE_PEC_ERROR + - 31:31 + - 0 + - RW + - | Target Debug Force PEC Error + | Corrupts the PEC byte generation/checking. When set, writes with PEC enabled will always report an error and the PEC byte transmitted during a read will be corrupted. + | 0x0 - PEC Error insertion disabled + | 0x1 - PEC Error insertion enabled + * - 0x618 + - TGT_DBG + - DBG_STATE + - 6:0 + - 1 + - RO + - | Target Debug State + | Reports the current Target FSM State to assist with debug. + * - 0x620 + - TGT_CONTROL_0 + - ENABLE + - 31:31 + - 0 + - RW + - | Target Device 0 Enable + | Configure the enable for Target Device 0 + | 0x0 - Target Device 0 disabled + | 0x1 - Target Device 0 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + * - 0x620 + - TGT_CONTROL_0 + - ADDRESS + - 7:1 + - 0 + - RW + - | Target Device 0 Address + | Configure the address for Device 0 + * - 0x624 + - TGT_CONTROL_1 + - ENABLE + - 31:31 + - 0 + - RW + - | Target Device 1 Enable + | Configure the enable for Target Device 1 + | 0x0 - Target Device 1 disabled + | 0x1 - Target Device 1 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + * - 0x624 + - TGT_CONTROL_1 + - ADDRESS + - 7:1 + - 0 + - RW + - | Target Device 1 Address + | Configure the address for Device 1 + * - 0x628 + - TGT_CONTROL_2 + - ENABLE + - 31:31 + - 0 + - RW + - | Target Device 2 Enable + | Configure the enable for Target Device 2 + | 0x0 - Target Device 2 disabled + | 0x1 - Target Device 2 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + * - 0x628 + - TGT_CONTROL_2 + - ADDRESS + - 7:1 + - 0 + - RW + - | Target Device 2 Address + | Configure the address for Device 2 + * - 0x62C + - TGT_CONTROL_3 + - ENABLE + - 31:31 + - 0 + - RW + - | Target Device 3 Enable + | Configure the enable for Target Device 3 + | 0x0 - Target Device 3 disabled + | 0x1 - Target Device 3 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + * - 0x62C + - TGT_CONTROL_3 + - ADDRESS + - 7:1 + - 0 + - RW + - | Target Device 3 Address + | Configure the address for Device 3 + * - 0x630 + - TGT_CONTROL_4 + - ENABLE + - 31:31 + - 0 + - RW + - | Target Device 4 Enable + | Configure the enable for Target Device 4 + | 0x0 - Target Device 4 disabled + | 0x1 - Target Device 4 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + * - 0x630 + - TGT_CONTROL_4 + - ADDRESS + - 7:1 + - 0 + - RW + - | Target Device 4 Address + | Configure the address for Device 4 + * - 0x634 + - TGT_CONTROL_5 + - ENABLE + - 31:31 + - 0 + - RW + - | Target Device 5 Enable + | Configure the enable for Target Device 5 + | 0x0 - Target Device 5 disabled + | 0x1 - Target Device 5 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + * - 0x634 + - TGT_CONTROL_5 + - ADDRESS + - 7:1 + - 0 + - RW + - | Target Device 5 Address + | Configure the address for Device 5 + * - 0x638 + - TGT_CONTROL_6 + - ENABLE + - 31:31 + - 0 + - RW + - | Target Device 6 Enable + | Configure the enable for Target Device 6 + | 0x0 - Target Device 6 disabled + | 0x1 - Target Device 6 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + * - 0x638 + - TGT_CONTROL_6 + - ADDRESS + - 7:1 + - 0 + - RW + - | Target Device 6 Address + | Configure the address for Device 6 + * - 0x63C + - TGT_CONTROL_7 + - ENABLE + - 31:31 + - 0 + - RW + - | Target Device 7 Enable + | Configure the enable for Target Device 7 + | 0x0 - Target Device 7 disabled + | 0x1 - Target Device 7 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + * - 0x63C + - TGT_CONTROL_7 + - ADDRESS + - 7:1 + - 0 + - RW + - | Target Device 7 Address + | Configure the address for Device 7 + * - 0x800 + - PHY_CTLR_DATA_HOLD + - CTLR_DATA_HOLD + - 14:0 + - (Note 1) + - RW + - | Controller PHY Data Hold + | Configure the data hold time when operating as a Controller-transmitter. + | This value must be configured to meet tHD:DAT:Min in accordance with the SMBus Specification. + | This value is calculated as - + | If PHY_FILTER_CONTROL__ENABLE = 0x1 + | Hold Time = s_axi_aclk period x (CTLR_DATA_HOLD + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) + | If PHY_FILTER_CONTROL__ENABLE = 0x0 + | Hold Time = s_axi_aclk period x (CTLR_DATA_HOLD + 8) + * - 0x804 + - PHY_CTLR_START_HOLD + - CTLR_START_HOLD + - 14:0 + - (Note 1) + - RW + - | Controller PHY Start Hold + | Configure the START condition hold time. + | This value must be configured to meet tHD:STA:Min in accordance with the SMBus Specification. + | This value is calculated as - + | If PHY_FILTER_CONTROL__ENABLE = 0x1 + | Hold Time = s_axi_aclk period x (CTLR_START_HOLD + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) + | If PHY_FILTER_CONTROL__ENABLE = 0x0 + | Hold Time = s_axi_aclk period x (CTLR_START_HOLD + 8) + * - 0x808 + - PHY_CTLR_START_SETUP + - CTLR_START_SETUP + - 14:0 + - (Note 1) + - RW + - | Controller PHY Start Setup + | Configure the START condition setup time. + | This value must be configured to meet tSU:STA:Min in accordance with the SMBus Specification. + | This value is calculated as - + | If PHY_FILTER_CONTROL__ENABLE = 0x1 + | Setup Time = s_axi_aclk period x (CTLR_START_SETUP + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) + | If PHY_FILTER_CONTROL__ENABLE = 0x0 + | Setup Time = s_axi_aclk period x (CTLR_START_SETUP + 8) + * - 0x80C + - PHY_CTLR_STOP_SETUP + - CTLR_STOP_SETUP + - 14:0 + - (Note 1) + - RW + - | Controller PHY Stop Setup + | Configure the STOP condition setup time. + | This value must be configured to meet tSU:STO:Min in accordance with the SMBus Specification. + | This value is calculated as - + | If PHY_FILTER_CONTROL__ENABLE = 0x1 + | Setup Time = s_axi_aclk period x (CTLR_STOP_SETUP + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) + | If PHY_FILTER_CONTROL__ENABLE = 0x0 + | Setup Time = s_axi_aclk period x (CTLR_STOP_SETUP + 8) + * - 0x810 + - PHY_CTLR_CLK_TLOW + - CTLR_CLK_TLOW + - 14:0 + - (Note 1) + - RW + - | Controller PHY Clock Low + | Configure the SMBCLK low time. + | This value must be configured to meet tLOW:Min in accordance with the SMBus Specification. + | This value is calculated as - + | If PHY_FILTER_CONTROL__ENABLE = 0x1 + | Low Time = s_axi_aclk period x (CTLR_CLK_TLOW + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) + | If PHY_FILTER_CONTROL__ENABLE = 0x0 + | Low Time = s_axi_aclk period x (CTLR_CLK_TLOW + 8) + * - 0x814 + - PHY_CTLR_CLK_THIGH + - CTLR_CLK_THIGH + - 14:0 + - (Note 1) + - RW + - | Controller PHY Clock High + | Configure the SMBCLK high time. + | This value must be configured to meet tHIGH:Min in accordance with the SMBus Specification. + | This value is calculated as - + | If PHY_FILTER_CONTROL__ENABLE = 0x1 + | Low Time = s_axi_aclk period x (CTLR_CLK_THIGH + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) + | If PHY_FILTER_CONTROL__ENABLE = 0x0 + | Low Time = s_axi_aclk period x (CTLR_CLK_THIGH + 8) + * - 0x818 + - PHY_CTLR_TEXT_PRESCALER + - CTLR_TEXT_PRESCALER + - 8:0 + - (Note 1) + - RW + - | Controller PHY TEXT Timeout Prescaler Configuration + | Configure the amount of time to measure before incrementing the PHY_CTLR_TEXT_TIMEOUT counter when external SMBCLK stretching is detected by the Controller function. + | This value is calculated as Text_Prescaler_Time = s_axi_aclk period x (CTLR_TEXT_PRESCALER+ 1) + | The Text_Prescaler_Time should be configured for 1us in order to stay within range of the PHY_CTLR_TEXT_TIMEOUT counter. + * - 0x81C + - PHY_CTLR_TEXT_TIMEOUT + - CTLR_TEXT_TIMEOUT + - 14:0 + - (Note 1) + - RW + - | Controller PHY TEXT Timeout Configuration + | Configure the threshold used to detect that an external Target device(s) has exceeded the cumulative clock stretching threshold and to trigger the CTLR_TEXT_TIMEOUT interrupt. + | This value must be configured to meet tLOW:TEXT in accordance with the SMBus Specification. + | This value is calculated as Text_Timeout_Time = CTLR_TEXT_TIMEOUT x Text_Prescaler_Time + * - 0x820 + - PHY_CTLR_TEXT_MAX + - CTLR_TEXT_MAX + - 14:0 + - (Note 1) + - WC + - | Controller PHY TEXT Timeout Max + | Indicates the maximum amount of cumulative time in Text_Prescaler_Time units that the Controller function has measured external SMBCLK stretching during any single transaction (between an initial START and a STOP). + * - 0x824 + - PHY_CTLR_CEXT_PRESCALER + - CTLR_CEXT_PRESCALER + - 8:0 + - (Note 1) + - RW + - | Controller PHY CEXT Timeout Prescaler Configuration + | Configure the amount of time to measure before incrementing the PHY_CTLR_CEXT_TIMEOUT counter when SMBCLK stretching is active within the Controller function. + | This value is calculated as Cext_Prescaler_Time = s_axi_aclk period x (CTLR_CEXT_PRESCALER+ 1) + | The Cext_Prescaler_Time should be configured for 1us in order to stay within range of the PHY_CTLR_CEXT_TIMEOUT counter. + * - 0x828 + - PHY_CTLR_CEXT_TIMEOUT + - CTLR_CEXT_TIMEOUT + - 13:0 + - (Note 1) + - RW + - | Controller PHY CEXT Timeout Configuration + | Configure the threshold used to detect that the Controller function has exceeded the cumulative clock stretching threshold and to trigger the CTLR_CEXT_TIMEOUT interrupt. + | This value must be configured to meet tLOW:CEXT in accordance with the SMBus Specification. + | This value is calculated as Cext_Timeout_Time = CTLR_CEXT_TIMEOUT x Cext_Prescaler_Time + * - 0x82C + - PHY_CTLR_CEXT_MAX + - CTLR_CEXT_MAX + - 13:0 + - (Note 1) + - WC + - | Controller PHY CEXT Timeout Max + | Indicates the maximum amount of cumulative time in Cext_Prescaler_Time units that the Controller function has performed SMBCLK stretching during any single byte transfer (START-ACK, ACK-ACK, ACK-STOP). + * - 0x830 + - PHY_CTLR_DBG_STATE + - DBG_STATE + - 7:0 + - 1 + - RO + - | Controller PHY Debug State + | Reports the current Controller PHY FSM State to assist with debug. + * - 0xA00 + - CTLR_CONTROL + - ENABLE + - 0:0 + - 0 + - WO + - | Controller Enable Control + | Enable the Controller to begin executing the descriptors in the Descriptor FIFO. + | 0x0 - Controller not enabled + | 0x1 - Controller enabled to execute the descriptors + * - 0xA04 + - CTLR_STATUS + - ENABLE + - 0:0 + - 0 + - RO + - | Controller Enable Status + | 0x0 - Controller is disabled + | 0x1 - Controller is enabled + * - 0xA08 + - CTLR_DESC_FIFO + - RESET + - 31:31 + - 0 + - WO + - | Controller Descriptor FIFO Reset Control + | When set the Controller Descriptor FIFO is reset to a known state. + | Poll the RESET_BUSY field in the CTLR_DESC_STATUS register to determine when the reset is complete. + | 0x1 - Descriptor FIFO reset + | 0x0 - Descriptor FIFO not reset + * - 0xA08 + - CTLR_DESC_FIFO + - ID + - 11:8 + - 0 + - WO + - | Controller Descriptor FIFO ID + | Configure the next Controller Descriptor ID + | Writing this register when the RESET field is 0x0 pushes a value into the Controller Descriptor FIFO + * - 0xA08 + - CTLR_DESC_FIFO + - PAYLOAD + - 7:0 + - 0 + - WO + - | Controller Descriptor FIFO Payload + | Configure the next Controller Descriptor payload + * - 0xA0C + - CTLR_DESC_STATUS + - FILL_LEVEL + - 14:8 + - 0 + - RO + - | Controller Descriptor FIFO Fill Level + | Indicates the current fill level of the Descriptor FIFO + * - 0xA0C + - CTLR_DESC_STATUS + - RESET_BUSY + - 6:6 + - 0 + - RO + - | Controller Descriptor FIFO Reset Busy + | Indicates if the Descriptor FIFO is currently undergoing a reset and is unavailable for either read or write. + | 0x0 - FIFO not in reset + | 0x1 - FIFO reset in progress + * - 0xA0C + - CTLR_DESC_STATUS + - FULL + - 5:5 + - 0 + - RO + - | Controller Descriptor FIFO Full + | Indicates if the Descriptor FIFO is full + | 0x0 - FIFO not full + | 0x1 - FIFO full + * - 0xA0C + - CTLR_DESC_STATUS + - ALMOST_FULL + - 4:4 + - 0 + - RO + - | Controller Descriptor FIFO Almost Full + | Indicates if the Descriptor FIFO is almost full + | 0x0 - FIFO has space for more than one descriptor + | 0x1 - FIFO only has space for one more descriptor + * - 0xA0C + - CTLR_DESC_STATUS + - ALMOST_EMPTY + - 1:1 + - 0 + - RO + - | Controller Descriptor FIFO Almost Empty + | Indicates if the Descriptor FIFO is almost empty + | 0x0 - FIFO contains more than one descriptor + | 0x1 - FIFO contains one descriptor or less + * - 0xA0C + - CTLR_DESC_STATUS + - EMPTY + - 0:0 + - 0 + - RO + - | Controller Descriptor FIFO Empty + | Indicates if the Descriptor FIFO is empty + | 0x0 - FIFO not empty + | 0x1 - FIFO empty + * - 0xA10 + - CTLR_RX_FIFO + - RESET + - 31:31 + - 0 + - WO + - | Controller Receive FIFO Reset Control + | When set the Controller Recieve FIFO is reset to a known state. + | Poll the RESET_BUSY field in the CTLR_RX_FIFO_STATUS register to determine when the reset is complete. + | 0x0 - FIFO not reset + | 0x1 - FIFO reset + * - 0xA10 + - CTLR_RX_FIFO + - PAYLOAD + - 7:0 + - 0 + - RC + - | Controller Receive FIFO Payload + | Receive payload byte for the Controller function. + | Reading this register pops a value from the Controller Receive FIFO. + * - 0xA14 + - CTLR_RX_FIFO_STATUS + - MAX_FILL_LEVEL + - 22:16 + - 0 + - W1C + - | Controller Receive FIFO Max Fill Level Status + | Indicates the maximum recorded fill level of the Controller Receive FIFO. + * - 0xA14 + - CTLR_RX_FIFO_STATUS + - FILL_LEVEL + - 14:8 + - 0 + - RO + - | Controller Receive FIFO Fill Level + | Indicates the current fill level of the Receive FIFO. + * - 0xA14 + - CTLR_RX_FIFO_STATUS + - RESET_BUSY + - 6:6 + - 0 + - RO + - | Controller Receive FIFO Reset Empty + | Indicates if the Receive FIFO is currently undergoing a reset and is unavailable for either read or write. + | 0x0 - FIFO not in reset + | 0x1 - FIFO reset in progress + * - 0xA14 + - CTLR_RX_FIFO_STATUS + - FULL + - 5:5 + - 0 + - RO + - | Controller Receive FIFO Full + | Indicates if the Receive FIFO is full + | 0x0 - FIFO not full + | 0x1 - FIFO full + * - 0xA14 + - CTLR_RX_FIFO_STATUS + - ALMOST_FULL + - 4:4 + - 0 + - RO + - | Controller Receive FIFO Almost Full + | Indicates if the Controller Receive FIFO is almost full + | 0x0 - FIFO has space for two or more bytes + | 0x1 - FIFO has space for only one more byte + * - 0xA14 + - CTLR_RX_FIFO_STATUS + - ALMOST_EMPTY + - 1:1 + - 0 + - RO + - | Controller Receive FIFO Almost Empty + | Indicates if the Controller Receive FIFO is almost empty + | 0x0 - FIFO contains more than one byte + | 0x1 - FIFO contains one byte or less + * - 0xA14 + - CTLR_RX_FIFO_STATUS + - EMPTY + - 0:0 + - 0 + - RO + - | Controller Receive FIFO Empty + | Indicates if the Receive FIFO is empty + | 0x0 - FIFO not empty + | 0x1 - FIFO empty + * - 0xA18 + - CTLR_RX_FIFO_FILL_THRESHOLD + - FILL_THRESHOLD + - 6:0 + - 1 + - RW + - | Controller Receive FIFO Fill Threshold + | Configure the Controller Receive FIFO fill threshold that should assert the CTLR_RX_FIFO_FILL_THRESHOLD interrupt. + * - 0xA1C + - CTLR_DBG + - FORCE_PEC_ERROR + - 31:31 + - 0 + - RW + - | Controller Debug Force PEC Error + | Corrupts the PEC byte generation/checking. When set, reads with PEC enabled will always report an error and the PEC byte transmitted during a write will be corrupted. + | 0x0 - PEC Error insertion disabled + | 0x1 - PEC Error insertion enabled + * - 0xA1C + - CTLR_DBG + - DBG_STATE + - 6:0 + - 0 + - RO + - | Controller Debug State + | Reports the current Controller FSM State to assist with debug. + +**Note 1:** The default value of this field is dependent upon the parameter configuration of the +SMBus IP. + +Customizing and Generating the IP +================================= + +This section includes information about using AMD tools to customize and generate the SMBus IP +using Vivado Design Suite. + +If you are customizing and generating the IP in the Vivado IP integrator, see the *Vivado Design +Suite User Guide: Designing IP Subsystems using IP Integrator* (`UG994`_) for detailed information. + +.. _`UG994`: https://docs.xilinx.com/r/en-US/ug994-vivado-ip-subsystems/Getting-Started-with-Vivado-IP-Integrator + +Importing the IP Repository +--------------------------- + +The SMBus IP is delivered as a standalone IP repository that can be imported for use within Vivado +Design Suite. Refer to the *Vivado Design Suite User Guide: Designing with IP* (`UG896`_) for +detailed information on adding an external IP repository to a project. + +.. _`UG896`: https://docs.xilinx.com/r/en-US/ug896-vivado-ip/IP-Centric-Design-Flow + +Customizing the IP +------------------ + +You can customize the IP for use in your design by specifying values for the various User +Parameters associated with the IP. + +Parameters +---------- + +The table below details the User Parameters that may be configured for the SMBus IP along with +the associated model parameters and default settings. + +.. list-table:: SMBus Parameters + :header-rows: 1 + :widths: auto + + * - Display Name + - User Parameter + - Model Parameter + - Model Parameter Format/Range + - Default + - Description + * - Default SMBus Device Class + - SMBUS_DEV_CLASS + - C_SMBUS_DEV_CLASS + - integer = {0 = 100KHz, 1 = 400KHz, 2 = 1MHz} + - 0 + - | The SMBus IP supports the three device classes specified in the SMBus v3.2 specification, namely the 100KHz Class, 400KHz Class and 1MHz Class. The Device Class user parameter controls the default internal AC timing parameters of the SMBus IP, so that the Controller and Target AC operation complies with the standard. + | When the s_axi_aresetn input is asserted, the SMBus IP internal configuration will be reset to the default device class as selected via this parameter. The device class may be changed at runtime by utilizing features available within the SMBus IP Driver, please refer to the Driver documentation for details on changing the device class from this default. + * - Target Devices + - NUM_TARGET_DEVICES + - C_NUM_TARGET_DEVICES + - integer = {1..8} + - 8 + - The SMBus IP Target functionality can support up to eight internal Target devices. These devices can be used to support use cases that require multiple Target addresses to be implemented on the SMBus, with each address associated to a different protocol or functionality. + * - S_AXI Clock Frequency (Hz) + - FREQ_HZ_AXI_ACLK + - C_FREQ_HZ_AXI_ACLK + - integer = {95000000..500000000} + - 100000000 + - | Configure the input clock frequency of the s_axi_aclk clock in hertz. + | The SMBus IP operates on the s_axi_aclk clock domain. This clock is used for the S_AXI interface, all internal control logic and to generate the SMBCLK/SMBDAT outputs in addition to oversampling the SMBCLK/SMBDAT inputs. The frequency of this clock must be within the supported range and must be specified in order for the SMBus IP to correctly operate its PHY layer in accordance with the SMBus AC timing specifications. + | When used within an IP Integrator context, the clock frequency information is automatically configured within the SMBus IP based upon the frequency of the clock connected to the s_axi_aclk input. If this clock metadata is incorrect or if the IP is being configured outside of an IP Integrator context, then this user parameter must be set accordingly. + +Output Generation +----------------- + +For detailed information on generating IP output products, please refer to the *Vivado Design Suite +User Guide: Designing with IP* (`UG896`_). + +Constraining the IP +=================== + +The SMBUS interface on the IP includes the necessary I/O buffer controls and is intended to be +connected to the design top level ports. When the IP implemented within an IP Integrator block +design context, then the generated BD wrapper will automatically include the required IOB +components and connectivity from the SMBus IP. + +The top level IOB connections must be constrained at the design top level depending upon the IO +bank type to which the SMBus IP is connected. The following constraint properties must be +considered, however the required settings will be dependent upon the connectivity of the IOBs in +the end application: + +- PACKAGE_PIN +- IOSTANDARD +- DRIVE +- SLEW + +Refer to the *Vivado Design Suite User Guide: Using Constraints* (`UG903`_) for detailed +information on defining physical constraints. + +.. _`UG903`: https://docs.xilinx.com/r/en-US/ug903-vivado-using-constraints/Introduction + +Simulation +========== + +For comprehensive information about Vivado simulation components, as well as information about +using supported third-party tools, see the *Vivado Design Suite User Guide: Logic Simulation* +(`UG900`_). + +.. _`UG900`: https://docs.xilinx.com/r/en-US/ug900-vivado-logic-simulation/Overview + +Synthesis and Implementation +============================ + +For details about synthesis and implementation, see the *Vivado Design Suite User Guide: Designing +with IP* (`UG896`_). + +Driver +====== + +The SMBus IP must be used in conjunction with the SMBus IP Driver in order to implement a SMBus +v3.2 compliant solution. + +Example Design +============== + +The SMBus IP does not support generation of an IP example design. Refer to the Alveo V80 AVED +reference design for example usage. diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/i2c.h b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/i2c.h new file mode 100755 index 00000000..6a2a5edd --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/i2c.h @@ -0,0 +1,227 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This header file contains structures, type definitions and function declarations + * for using the SMBus driver as a raw i2c driver. + * + * @file i2c.h + * + * @note [1] This provides a simplified API to use the smbus 3.2 library as a simple + * i2c device. Only the most essential commands are provided. + * @note [2] xInitSMBus must still be called to initialise the Bus control. + * + */ + +#ifndef _I2C_H_ +#define _I2C_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************/ +/* includes */ +/******************************************************************************/ + +#include + + + +/******************************************************************************/ +/* defines */ +/******************************************************************************/ + +#define I2C_SUCCESS ( 0 ) +#define I2C_ERROR ( -1 ) +#define I2C_MAX_BUFFER_LEN ( 256 ) +#define I2C_READ_DATA_SIZE_MIN ( 1 ) + + +/******************************************************************************/ +/* enums */ +/******************************************************************************/ + +/******************************************************************************/ +/* structs */ +/******************************************************************************/ + +/* + * @struct I2C_PROFILE_TYPE + * @brief Forward Declaration of structure to hold a single i2c profile + */ +struct I2C_PROFILE_TYPE; + +/******************************************************************************/ +/* typedefs */ +/******************************************************************************/ + +/* + * @typedef I2C_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE + * @brief This callback updates the initialiser with new data + * + * @param pucData pointer to the new data read + * @param pusDataSize number of bytes in pucData + * + * @return void + */ +typedef void ( *I2C_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE )( uint8_t* pucData, uint16_t* pusDataSize ); + +/* + * @typedef I2C_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE + * @brief This callback retrieves data from the initialiser to write + * + * @param pucData pointer to the new data to write + * @param usDataSize number of bytes in pucData + * + * @return void + */ +typedef void ( *I2C_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE )( uint8_t* pucData, uint16_t usDataSize ); + +/* + * @typedef I2C_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE + * @brief This callback updates the initialiser when a command is complete + * + * @param ulStatus is the status of the command + * + * @return void + */ +typedef void ( *I2C_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE )( uint32_t ulStatus ); + +/* + * @typedef I2C_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR + * @brief This callback updates the initialiser when there is an i2 Error + * + * @param ucError is the error that was raised + * + * @return void + */ +typedef void ( *I2C_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR )( uint8_t ucError ); + +/* + * @typedef I2C_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING + * + * @brief This callback updates the initialiser when there is an i2c Warning + * + * @param ucWarning is the warning that was raised + * + * @return void + */ +typedef void ( *I2C_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING )( uint8_t ucWarning ); + +/******************************************************************************/ +/* function declarations */ +/******************************************************************************/ + +/******************************************************************************/ +/*! + * @brief Creates an i2c device to act as both a master and a slave + * + * @param pxI2cProfile Handler to the SMBus profile structure (see smbus.h) + * @param ucAddr Slave address that this device will respond to. + * @param pFnGetData Callback called when new data arrives at the device. + * @param pFnWriteData Callback called when the device has to respond with data. + * @param pFnAnnounceResult Callback called when a write/read command is complete. + * @param pFnBusError Callback called when an error occurs + * + * @return The ID of the device (0 to 6) + * Returns I2C_ERROR if the call is unsuccessful + * + * @note [1] This device will be created along with any SMBus instances; + * therefore, it requires availability in the SMBus instance pool. + * See ucCreateSMBusInstance() in smbus.h for more information. + * xInitSMBus() must have been successfully called before this. + */ +/******************************************************************************/ +uint8_t ucI2CCreateDevice( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucAddr, + I2C_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE pFnGetData, + I2C_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE pFnWriteData, + I2C_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE pFnAnnounceResult, + I2C_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR pFnBusError, + I2C_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING pFnBusWarning ); + + +/******************************************************************************/ +/*! + * @brief Destroys a previously created i2c device + * + * @param pxI2cProfile Handler to the SMBus profile structure (see smbus.h) + * @param ucDeviceId ID of the device to destroy + * + * @return I2C_SUCCESS - the device has been successfully destroyed + * I2C_ERROR - the device has not been destroyed + * + * @note None + */ +/******************************************************************************/ +uint8_t ucI2CDestroyDevice( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucDeviceId ); + + +/******************************************************************************/ +/*! + * @brief Writes data to a remote slave as a master + * + * @param pxI2cProfile Handler to the i2c profile structure + * @param ucDeviceId Device to use as a master + * @param ucAddr Address of remote slave to write to + * @param pucData Data buffer to write (must be at least usNumBytes bytes) + * @param usNumBytes Number of bytes to write + * + * @return I2C_SUCCESS - data successfully written + * I2C_ERROR - an error occurred attempting to write + * + */ +/******************************************************************************/ +uint8_t ucI2CWriteData( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucDeviceId, + uint8_t ucAddr, + uint8_t* pucData, + uint16_t usNumBytes ); + +/******************************************************************************/ +/*! + * @brief Reads data from a remote slave as a master + * + * @param pxI2cProfile Handler to the i2c profile structure + * @param ucDeviceId Device to use as a master + * @param ucAddr Address of remote slave to read from + * @param pusNumBytes Maximum number of bytes to read + * - Cannot be larger than I2C_MAX_BUFFER_LEN + * + * @return I2C_SUCCESS - data successfully read + * I2C_ERROR - an error occurred attempting to read + * + */ +/******************************************************************************/ +uint8_t ucI2CReadData( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucDeviceId, + uint8_t ucAddr, + uint16_t usNumBytes ); + +/******************************************************************************/ +/*! + * @brief Writes data to a remote slave as a master and then reads from it + * + * @param pxI2cProfile Handler to the i2c profile structure + * @param ucDeviceId Device to use as a master + * @param ucAddr Address of remote slave to write to + * @param pucWriteData Data buffer to write (must be at least usNumBytes bytes) + * @param usNumWriteBytes Number of bytes to write + * @param usNumReadBytes Maximum number of bytes to read + * + * @return I2C_SUCCESS - data successfully written + * I2C_ERROR - an error occurred attempting to write + * + */ +/******************************************************************************/ +uint8_t ucI2CWriteReadData( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucDeviceId, + uint8_t ucAddr, + uint8_t* pucWriteData, + uint16_t usNumWriteBytes, + uint16_t usNumReadBytes ); + +#endif /* _I2C_H_ */ diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus.h b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus.h new file mode 100755 index 00000000..4672816e --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus.h @@ -0,0 +1,533 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This header file contains structures, type definitions and function declarations + * for the SMBus driver. + * + * @file smbus.h + * + */ + +#ifndef _SMBUS_H_ +#define _SMBUS_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/******************************************************************************/ +/* Defines */ +/******************************************************************************/ +#define SMBUS_DATA_SIZE_MIN ( 0 ) +#define SMBUS_DATA_SIZE_MAX ( 256 ) /* 255 bytes of data + 1 byte block size */ +#define SMBUS_UDID_LENGTH ( 16 ) +#define SMBUS_MAX_CIRCULAR_LOG_ENTRIES ( 5000 ) +#define SMBUS_NUMBER_OF_SMBUS_INSTANCES ( 8 ) +#define SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES ( 7 ) +#define SMBUS_INVALID_INSTANCE ( 99 ) +#define SMBUS_MAX_EVENT_ELEMENTS ( 300 ) + +/******************************************************************************/ +/* Enums */ +/******************************************************************************/ + +/* + * @enum SMBus_Freq_Class_Type + * @brief Enumeration of SMBUS frequency values + */ +typedef enum SMBus_Freq_Class_Type +{ + SMBUS_FREQ_100KHZ = 0, + SMBUS_FREQ_400KHZ, + SMBUS_FREQ_1MHZ, + SMBUS_FREQ_MAX + +} SMBus_Freq_Class_Type; + +/* + * @enum SMBus_Error_Type + * @brief Enumeration of SMBUS return values + */ +typedef enum SMBus_Error_Type +{ + SMBUS_SUCCESS = 0, + SMBUS_ERROR + +} SMBus_Error_Type; + +/* + * @enum SMBus_ARP_Capability + * @brief Enumeration of SMBUS ARP settings + */ +typedef enum SMBus_ARP_Capability +{ + SMBUS_ARP_CAPABILITY_UNKNOWN = 0, + SMBUS_ARP_CAPABLE, + SMBUS_ARP_FIXED_AND_DISCOVERABLE, + SMBUS_ARP_FIXED_NOT_DISCOVERABLE, + SMBUS_ARP_NON_ARP_CAPABLE + +} SMBus_ARP_Capability; + + +/* + * @enum SMBus_Command_Protocol_Type + * @brief Enumeration of SMBUS command protocols + */ +typedef enum SMBus_Command_Protocol_Type +{ + SMBUS_PROTOCOL_QUICK_COMMAND_LO = 0, + SMBUS_PROTOCOL_QUICK_COMMAND_HI, + SMBUS_PROTOCOL_SEND_BYTE, + SMBUS_PROTOCOL_RECEIVE_BYTE, + SMBUS_PROTOCOL_WRITE_BYTE, + SMBUS_PROTOCOL_WRITE_WORD, + SMBUS_PROTOCOL_READ_BYTE, + SMBUS_PROTOCOL_READ_WORD, + SMBUS_PROTOCOL_PROCESS_CALL, + SMBUS_PROTOCOL_BLOCK_WRITE, + SMBUS_PROTOCOL_BLOCK_READ, + SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL, + SMBUS_PROTOCOL_HOST_NOTIFY, + SMBUS_PROTOCOL_WRITE_32, + SMBUS_PROTOCOL_READ_32, + SMBUS_PROTOCOL_WRITE_64, + SMBUS_PROTOCOL_READ_64, + SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP, + SMBUS_ARP_PROTOCOL_RESET_DEVICE, + SMBUS_ARP_PROTOCOL_GET_UDID, + SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS, + SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED, + SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED, + SMBUS_PROTOCOL_NONE, + I2C_PROTOCOL_WRITE, + I2C_PROTOCOL_READ, + I2C_PROTOCOL_WRITE_READ, + I2C_PROTOCOL_NONE + +} SMBus_Command_Protocol_Type; + +/* + * @enum SMBUS_LOG_EVENT_TYPE + * @brief Enumeration of SMBus logging types + */ +typedef enum SMBUS_LOG_EVENT_TYPE +{ + SMBUS_LOG_EVENT_INTERRUPT_EVENT = 1, + SMBUS_LOG_EVENT_FSM_EVENT, + SMBUS_LOG_EVENT_ERROR, + SMBUS_LOG_EVENT_HW_READ, + SMBUS_LOG_EVENT_HW_WRITE, + SMBUS_LOG_EVENT_PROTOCOL, + SMBUS_LOG_EVENT_DEBUG, + SMBUS_LOG_EVENT_TRYREAD, + SMBUS_LOG_EVENT_TRYWRITE + +} SMBUS_LOG_EVENT_TYPE; + +/* + * @enum SMBUS_LOG_LEVEL_TYPE + * @brief Enumeration of SMBUS logging levels + */ +typedef enum SMBUS_LOG_LEVEL_TYPE +{ + SMBUS_LOG_LEVEL_NONE = 0, + SMBUS_LOG_LEVEL_ERROR, + SMBUS_LOG_LEVEL_WARNING, + SMBUS_LOG_LEVEL_INFO, + SMBUS_LOG_LEVEL_DEBUG, + SMBUS_LOG_LEVEL_MAX + +} SMBUS_LOG_LEVEL_TYPE; + +/******************************************************************************/ +/* Typedefs */ +/******************************************************************************/ + +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_PROTOCOL_TYPE + * + * @brief This callback retrieves the protocol for a command + * @param pxUserContext is the pointer to SMBusProfile + * @param ucCommand is the command under inspection + * @param xProtocol is a pointer for the protocol to be stored in + * + * @return void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_PROTOCOL_TYPE )( uint8_t ucCommand, + SMBus_Command_Protocol_Type* xProtocol ); + +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE + * + * @brief This callback updates the initialiser with new data + * @param pxUserContext is the pointer to SMBusProfile + * @param ucCommand is the SMBus command + * @param pucData is a pointer to the new data read + * @param Data_Size is the number of bytes in pucData + * + * @return void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE )( uint8_t ucCommand, uint8_t* pucData, + uint16_t* Data_Size ); + +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE + * + * @brief This callback retrieves data from the initialiser to write + * @param pxUserContext is the pointer to SMBusProfile + * @param ucCommand is the SMBus command + * @param pucData is a pointer to the new data to write + * @param Data_Size is the number of bytes in pucData + * @param ulTransactonID is the transaction ID of the message + * + * @return void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE )( uint8_t ucCommand, uint8_t* pucData, + uint16_t Data_Size, uint32_t ulTransactionID ); + +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE + * + * @brief This callback updates the initialiser when a command is complete + * @param pxUserContext is the pointer to SMBusProfile + * @param ucCommand is the SMBus command + * @param ulTransactionID is the transaction ID of the completed command + * @param Status is the status of the command + * + * @return void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE )( uint8_t ucCommand, uint32_t ulTransactionID, + uint32_t Status ); + +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_ARP_ADDRESS_CHANGE + * + * @brief This callback updates the initialiser when an address is changed + * @param pxUserContext is the pointer to SMBusProfile + * @param ucNewAddress is the next SMBus address + * + * @return void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_ARP_ADRRESS_CHANGE )( uint8_t ucNewAddress ); + +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR + * + * @brief This callback updates the initialiser when there is an SMBus Error + * @param pxUserContext is the pointer to SMBusProfile + * @param ucError is the error that was raised + * + * @return void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR )( uint8_t ucError ); + +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING + * + * @brief This callback updates the initialiser when there is an SMBus Warning + * @param pxUserContext is the pointer to SMBusProfile + * @param ucWarning is the warning that was raised + * + * @return void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING )( uint8_t ucWarning ); + +/* + * @typedef SMBUS_USER_SUPPLIED_ENVIRONMENT_READ_TICKS + * + * @brief This callback retrieves the current tick count from the initialiser + * @param pxUserContext is the pointer to SMBusProfile + * @param pulTicks is a a pointer to store the tick count + * + * @return void + */ +typedef void ( *SMBUS_USER_SUPPLIED_ENVIRONMENT_READ_TICKS )( uint32_t* pulTicks ); + +/******************************************************************************/ +/* Structs */ +/******************************************************************************/ + + +/* + * @struct SMBUS_LOG_TYPE + * @brief Structure to hold SMBus message logging information + */ +typedef struct SMBUS_LOG_TYPE +{ + uint32_t ulMessagesComplete[SMBUS_PROTOCOL_NONE]; + uint32_t ulMessagesInitiated[SMBUS_PROTOCOL_NONE]; + +} SMBUS_LOG_TYPE; + + +/* + * @struct SMBUS_VERSION_TYPE + * @brief Structure to hold the SMBus driver version informatin + */ +typedef struct SMBUS_VERSION_TYPE +{ + uint16_t usIpVerMajor; + uint16_t usIpVerMinor; + uint8_t ucSwVerMajor; + uint8_t ucSwVerMinor; + uint8_t ucSwVerPatch; + uint8_t ucSwDevBuild; + uint8_t ucSwTestBuild; + +} SMBUS_VERSION_TYPE; + + +/* + * @struct SMBUS_PROFILE_TYPE + * @brief Forward Declaration of structure to hold a single SMBus profile + */ +struct SMBUS_PROFILE_TYPE; + +/******************************************************************************/ +/* Driver External APIs */ +/******************************************************************************/ + +/******************************************************************************* +* +* @brief Checks hardware is present at the supplied base address +* Sets up hardware registers for the frequency class supplied +* initializes software structures, sets up log and event queues +* +* @param ppxSMBusProfile is a pointer to the SMBus profile structure handle. +* @param xFrequencyClass is an enum of type Freq_Class_Type which can be +* 100KHz, 400KHz or 1MHz. +* @param pvBaseAddress is the address of the SMBus IP block +* @param xLogLevel is the level of logging detail required +* @param pFnReadTicks is an optional function pointer that supplies a tick count for logging purposes +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*****************************************************************************/ +SMBus_Error_Type xInitSMBus( struct SMBUS_PROFILE_TYPE** ppxSMBusProfile, + SMBus_Freq_Class_Type xFrequencyClass, + void * pvBaseAddress, + SMBUS_LOG_LEVEL_TYPE xLogLevel, + SMBUS_USER_SUPPLIED_ENVIRONMENT_READ_TICKS pFnReadTicks ); + + +/******************************************************************************* +* +* @brief Checks all instances have already been removed +* If so sets Profile structure to default values +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure handle. +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*****************************************************************************/ +SMBus_Error_Type xDeinitSMBus( struct SMBUS_PROFILE_TYPE** ppxSMBusProfile ); + + +/******************************************************************************* +* +* @brief Checks that a free instance slot is available and if so stores the +* supplied data associated with the instance and enables the hardware +* to send or receive SMBus messages for the supplied instance +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucSMBusAddress is the 7-bit SMBUs address to asscociate with this instance +* @param ucUDID is the 16 byte UDID to asscociate with this instance +* @param xARPCapability is the ARP capabaility of the instance +* @param pFnGetProtocol ia a pointer to a function to convert coammand byte to an SMBus protocol +* @param pFnGetData ia a pointer to a function to get data to be returned +* @param pFnWriteData ia a pointer to a function to write data received +* @param pFnAnnounceResult ia a pointer to a function to announce the result of a transaction +* @param pFnArpAddressChange ia a pointer to a function to call if the address is changed +* @param pFnBusError ia a pointer to a function to report SMBus errors +* @param pFnBusWarning ia a pointer to a function to report SMBus warnings +* @param ucSimpleDevice is a flag to allow instance to understand only simple +* send and receive byte commands +* +* @return - SMBUS_INVALID_INSTANCE ID ( 99 ) if error +* - Instance ID ( 0 - 6 ) if successful +* +* @note None. +* +*******************************************************************************/ +uint8_t ucCreateSMBusInstance( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, + uint8_t ucSMBusAddress, + uint8_t ucUDID[SMBUS_UDID_LENGTH], + SMBus_ARP_Capability xARPCapability, + SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_PROTOCOL_TYPE pFnGetProtocol, + SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE pFnGetData, + SMBUS_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE pFnWriteData, + SMBUS_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE pFnAnnounceResult, + SMBUS_USER_SUPPLIED_ENVIRONMENT_ARP_ADRRESS_CHANGE pFnArpAddressChange, + SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR pFnBusError, + SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING pFnBusWarning, + uint8_t ucSimpleDevice ); + + +/****************************************************************************** +* +* @brief Checks that the supplied instance is present and attempts to remove +* it. If the instance being removed is the only instance then the ARP +* instance is also removed +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucSMBusInstanceID is the SMBus instance ID of the instance to be +* removed +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*****************************************************************************/ +SMBus_Error_Type xDestroySMBusInstance( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, + uint8_t ucSMBusInstanceID ); + + +/******************************************************************************* +* +* @brief Will initiate an SMBus message from the supplied intance as a controller +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucSMBusInstanceID is the SMBus instance ID of the instance to use as the controller +* @param ucSMBusDestinationAddress is the address of the target SMBUs device +* @param ucCommand is the Command byte of the message +* @param xProtocol is the SMBUs Protocol type of the message being sent +* @param usDataSize is the Size of data being sent ( if tranaction protocol is a send type ) +* @param pucData is a pointer to the data to send ( if tranaction protocol is a send type ) +* @param ucPecRequiredForTransaction is an integer to set if a PEC is required to be sent or not +* @param ulTransactionID is a pointer to the unique ID assigned to this transaction +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusControllerInitiateCommand( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, + uint8_t ucSMBusInstance, + uint8_t ucSMBusDestinationAddress, + uint8_t ucCommand, + SMBus_Command_Protocol_Type xProtocol, + uint16_t usDataSize, + uint8_t* pucData, + uint8_t ucPecRequiredForTransaction, + uint32_t* pulTransactionID ); + + +/******************************************************************************* +* +* @brief Retrieves SMBus log that is stored as a circular buffer in profile struct +* as ASCII char array +* +* @param SMBUS_PROFILE_TYPE is the context to poll log on +* @param pcLogBuffer is the array to put log data must be more than TBD driver events string +* separated by '\n' +* @param pusLogSizeBytes is a pointer to the number of bytes that are in the log +* (NOTE NOT NULL TERMINATED. THIS SHOULD BE USED FOR MEMCPY ETC) +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusGetLog( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, + char* pcLogBuffer, + uint32_t* pulLogSizeBytes ); + + +/******************************************************************************* +* +* @brief Resets SMBus Driver Log +* +* @param SMBUS_PROFILE_TYPE is the context with log to clear +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusLogReset( struct SMBUS_PROFILE_TYPE* pxSMBusProfile ); + + +/******************************************************************************* +* +* @brief Disables and then clears all SMBUs interrupts +* +* @param pxSMBusProfile is the pointer to the SMBus profile. +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusInterruptDisableAndClearInterrupts( struct SMBUS_PROFILE_TYPE* pxSMBusProfile ); + + +/******************************************************************************* +* +* @brief enables all necessary SMBUs interrupts +* +* @param pxSMBusProfile is the pointer to the SMBus profile. +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusInterruptEnableInterrupts( struct SMBUS_PROFILE_TYPE* pxSMBusProfile ); + + +/******************************************************************************* +* +* @brief Function will be a callback called from the interrupt handler +* It will determine what interrupts are present from those add +* events on the event queue and then trigger the handling of the +* events by the state machine +* +* @param pvCallBackRef is the reference to the SMBus profile. +* +* @return void +* +* @note None. +* +*******************************************************************************/ +void vSMBusInterruptHandler( void* pvCallBackRef ); + + +/******************************************************************************* +* +* @brief Retrieves the SMBus driver version +* +* @param pxSMBusProfile is the pointer to the SMBUS profile +* +* @param pxSMBusVersion is the pointer to the SMBus version (to be filled). +* +* @return - SMBUS_ERROR if error +* - SMBUS_SUCCESS if successful +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusGetVersion( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, + SMBUS_VERSION_TYPE* pxSMBusVersion ); + +#ifdef __cplusplus +} +#endif + +#endif /* _SMBUS_H_ */ diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_action.c b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_action.c new file mode 100755 index 00000000..fcb9bb92 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_action.c @@ -0,0 +1,495 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the action functions to either generate new events, determine a protocol + * or read data from application or write data to application + * + * @file smbus_action.c + * + */ + +#include +#include +#include "smbus.h" +#include "smbus_internal.h" +#include "smbus_action.h" +#include "smbus_event.h" +#include "smbus_hardware_access.h" + +/****************************************************************************** +* +* @brief Clears all actions that have been raised against the specified instance. +* +*****************************************************************************/ +void vSMBusClearAction( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + pxSMBusInstance->ulAction = 0; + } +} + +/****************************************************************************** +* +* @brief Sets a specific actions against the specified instance +* +*****************************************************************************/ +void vSMBusAction( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint32_t ulAnyAction ) +{ + if( NULL != pxSMBusInstance ) + { + pxSMBusInstance->ulAction |= ulAnyAction; + } +} + +/****************************************************************************** +* +* @brief Resets all variables used during an SMBus message transaction back +* to their default values +* Resets the IP's Descriptor and RX FIFOs +* +*****************************************************************************/ +void vSMBusHandleActionResetAllData( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + pxSMBusInstance->ucCommand = SMBUS_COMMAND_INVALID; + pxSMBusInstance->xProtocol = SMBUS_PROTOCOL_NONE; + pxSMBusInstance->usSendDataSize = 0; + pxSMBusInstance->usSendIndex = 0; + pxSMBusInstance->usReceiveIndex = 0; + pxSMBusInstance->usExpectedByteCount = 0; + pxSMBusInstance->ucNewDeviceSlaveAddress = 0; + pxSMBusInstance->ucNackSent = SMBUS_FALSE; + pxSMBusInstance->usDescriptorsSent = 0; + pxSMBusInstance->ucPECSent = SMBUS_FALSE; + pxSMBusInstance->ucFifoEmptyWhileInDoneCount = 0; + pxSMBusInstance->ucUDIDMatchedInstance = SMBUS_INVALID_INSTANCE; + + SMBUS_PROFILE_TYPE* pxSMBusProfile = pxSMBusInstance->pxSMBusProfile; + + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + ( uint32_t )pxSMBusInstance->ucThisInstanceNumber, __LINE__ ); + + if( pxSMBusInstance->ucThisInstanceNumber == pxSMBusProfile->ucInstanceInPlay ) /* This is controller */ + { + pxSMBusProfile->ucInstanceInPlay = SMBUS_INVALID_INSTANCE; + + /* Empty any RX queues */ + while( !ulSMBusHWReadCtrlRxFifoStatusEmpty( pxSMBusProfile ) ) + { + ulSMBusHWReadCtrlRxFifoPayload( pxSMBusProfile ); + } + + vSMBusHWWriteCtrlRxFifoReset( pxSMBusProfile, 1 ); + vSMBusHWWriteCtrlDescFifoReset( pxSMBusProfile, 1 ); + } + else /* This is a target */ + { + pxSMBusProfile->ucActiveTargetInstance = SMBUS_INVALID_INSTANCE; + /* Empty any RX queues */ + while( !ulSMBusHWReadTgtRxFifoStatusEmpty( pxSMBusProfile ) ) + { + ulSMBusHWReadTgtRxFifoPayload( pxSMBusProfile ); + } + + vSMBusHWWriteTgtRxFifoReset( pxSMBusProfile, 1 ); + } + } +} + +/****************************************************************************** +* +* @brief Generates an E_IS_PEC_REQUIRED event against the specified instance +* +*****************************************************************************/ +void vSMBusHandleActionCreateEventIsPECRequired( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusGenerateEvent_E_IS_PEC_REQUIRED( pxSMBusInstance ); + } +} + +/****************************************************************************** +* +* @brief Generates an E_SEND_NEXT_BYTE event against the specified instance +* +*****************************************************************************/ +void vSMBusHandleActionCreateEventSendNextByte( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusGenerateEvent_E_SEND_NEXT_BYTE( pxSMBusInstance ); + } +} + +/****************************************************************************** +* +* @brief Reads the command byte from the Target RX FIFO, calls the callback function +* for the specified instance to get the SMBus protocol associated with the +* command byte and stores that protocol in the instance structure +* +*****************************************************************************/ +void vSMBusHandleActionGetProtocol( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + SMBus_Command_Protocol_Type xTempProtocol = SMBUS_PROTOCOL_NONE; + + if( ( NULL != pxSMBusInstance ) && + ( NULL != pxSMBusInstance->pFnGetProtocol ) ) + { + if( SMBUS_RX_FIFO_IS_EMPTY != ulSMBusHWReadTgtRxFifoStatusEmpty( pxSMBusInstance->pxSMBusProfile ) ) + { + uint8_t ucCommand = ulSMBusHWReadTgtRxFifoPayload( pxSMBusInstance->pxSMBusProfile ); + pxSMBusInstance->ucCommand = ucCommand; + pxSMBusInstance->pFnGetProtocol( ucCommand, &xTempProtocol ); + pxSMBusInstance->xProtocol = xTempProtocol; + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_INFO, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_PROTOCOL, + ( uint32_t )ucCommand, ( uint32_t )pxSMBusInstance->xProtocol ); + } + else + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, 0, __LINE__ ); + } + } +} + +/****************************************************************************** +* +* @brief Reads the command byte from the Target RX FIFO for the ARP instance, +* determines the ARP protocol associated with the command byte, +* stores that protocol in the instance structure +* +*****************************************************************************/ +uint8_t ucSMBusHandleActionGetARPProtocol( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + uint8_t ucReturnCode = SMBUS_ACTION_ARP_PROTOCOL_DETERMINED; + uint8_t ucARPCommand = 0; + + if( NULL != pxSMBusInstance ) + { + if( SMBUS_RX_FIFO_IS_EMPTY != ulSMBusHWReadTgtRxFifoStatusEmpty( pxSMBusInstance->pxSMBusProfile ) ) + { + ucARPCommand = ulSMBusHWReadTgtRxFifoPayload( pxSMBusInstance->pxSMBusProfile ); + + pxSMBusInstance->ucCommand = ucARPCommand; + + switch( ucARPCommand ) + { + case 0x01: + pxSMBusInstance->xProtocol = SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP; + break; + + case 0x02: + pxSMBusInstance->xProtocol = SMBUS_ARP_PROTOCOL_RESET_DEVICE; + break; + + case 0x03: + pxSMBusInstance->xProtocol = SMBUS_ARP_PROTOCOL_GET_UDID; + break; + + case 0x04: + pxSMBusInstance->xProtocol = SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS; + break; + + case 0x00: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + case 0x10: + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1a: + case 0x1b: + case 0x1c: + case 0x1d: + case 0x1e: + case 0x1f: + /* Reserved */ + ucReturnCode = SMBUS_ACTION_ARP_PROTOCOL_UNDETERMINED; + break; + + default: + /* Anything else is a directed ARP command */ + if( SMBUS_ARP_UDID_DIRECTED_COMMAND == ( ucARPCommand & SMBUS_ARP_DIRECTED_COMMAND_MASK ) ) + { + pxSMBusInstance->xProtocol = SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED; + } + else + { + pxSMBusInstance->xProtocol = SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED; + } + + pxSMBusInstance->ucMatchedSMBusAddress = ( ucARPCommand & SMBUS_ARP_DIRECTED_COMMAND_ADDRESS_MASK ) >> 1; + break; + } + } + else + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, 0, __LINE__ ); + ucReturnCode = SMBUS_ACTION_ARP_PROTOCOL_UNDETERMINED; + } + } + else + { + ucReturnCode = SMBUS_ACTION_ARP_PROTOCOL_UNDETERMINED; + } + + return( ucReturnCode ); +} + +/****************************************************************************** +* +* @brief Checks if a callback function to read data from the application software +* for the specified instance is present. +* If present it is called for the current SMBus command. +* The callback function must return the data and size of data for the command. +* +*****************************************************************************/ +void vSMBusHandleActionGetDataFromApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + uint8_t ucTempSendData[SMBUS_DATA_SIZE_MAX] = { 0 }; + uint16_t usTempSendDataSize = 0; + + if( ( NULL != pxSMBusInstance ) && + ( NULL != pxSMBusInstance->pFnGetData ) ) + { + pxSMBusInstance->pFnGetData( pxSMBusInstance->ucCommand, ucTempSendData, &usTempSendDataSize ); + + if( SMBUS_DATA_SIZE_MAX >= usTempSendDataSize ) + { + memcpy( pxSMBusInstance->ucSendData, ucTempSendData, usTempSendDataSize ); + + switch( pxSMBusInstance->xProtocol ) + { + case SMBUS_PROTOCOL_READ_64: + pxSMBusInstance->usSendDataSize = 8; + break; + case SMBUS_PROTOCOL_READ_32: + pxSMBusInstance->usSendDataSize = 4; + break; + case SMBUS_PROTOCOL_READ_WORD: + pxSMBusInstance->usSendDataSize = 2; + break; + case SMBUS_PROTOCOL_READ_BYTE: + pxSMBusInstance->usSendDataSize = 1; + break; + case SMBUS_PROTOCOL_PROCESS_CALL: + pxSMBusInstance->usSendDataSize = 2; + break; + case SMBUS_PROTOCOL_RECEIVE_BYTE: + pxSMBusInstance->usSendDataSize = 1; + break; + default: + pxSMBusInstance->usSendDataSize = usTempSendDataSize; + break; + } + } + else + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, 0, __LINE__ ); + } + } +} + +/****************************************************************************** +* +* @brief Checks if a callback function to write data to the application software +* for the specified instance is present. +* If present it is called for the current SMBus command. +* The callback function write the command, data and size of data and transaction ID. +* +*****************************************************************************/ +void vSMBusHandleActionWriteDataToApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucTransactionID ) +{ + SMBUS_PROFILE_TYPE* pxSMBusProfile = NULL; + uint8_t ucTempReceivedData[SMBUS_DATA_SIZE_MAX] = { 0 }; + + if( ( NULL != pxSMBusInstance ) && + ( NULL != pxSMBusInstance->pFnWriteData ) ) + { + pxSMBusProfile = pxSMBusInstance->pxSMBusProfile; + + /* Only return the tranaction ID for Controller */ + if( pxSMBusInstance->ucThisInstanceNumber != pxSMBusProfile->ucInstanceInPlay ) + { + ucTransactionID = 0; + } + + memcpy( ucTempReceivedData, pxSMBusInstance->ucReceivedData, pxSMBusInstance->usExpectedByteCount ); + + pxSMBusInstance->pFnWriteData( pxSMBusInstance->ucCommand, ucTempReceivedData, + pxSMBusInstance->usExpectedByteCount, ucTransactionID ); + } +} + +/****************************************************************************** +* +* @brief Checks if a callback function to announce the result of the SMBus transaction +* for the specified instance is present. +* If present the callback is called. +* The callback function will include the command, transaction ID and the result +* +*****************************************************************************/ +void vSMBusHandleActionAnnounceResultToApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance, + uint8_t ucTransactionID, uint32_t ulStatus ) +{ + SMBUS_PROFILE_TYPE* pxSMBusProfile = NULL; + + if( ( NULL != pxSMBusInstance ) && + ( NULL != pxSMBusInstance->pFnAnnounceResult ) ) + { + pxSMBusProfile = pxSMBusInstance->pxSMBusProfile; + + /* Only return the tranaction ID for Controller */ + if( pxSMBusInstance->ucThisInstanceNumber != pxSMBusProfile->ucInstanceInPlay ) + { + ucTransactionID = 0; + } + pxSMBusInstance->pFnAnnounceResult( pxSMBusInstance->ucCommand, ucTransactionID, ulStatus ); + } +} + +/****************************************************************************** +* +* @brief Checks if a callback function to announce that an ARP Assign Address +* for the specified instance is present. +* If present the callback is called. +* The callback function will include the newly assigned address +* +*****************************************************************************/ +void vSMBusHandleActionNotifyAddressChangeToApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance, + uint8_t ucTransactionID ) +{ + if( ( NULL != pxSMBusInstance ) && + ( NULL != pxSMBusInstance->pFnArpAddressChange ) ) + { + pxSMBusInstance->pFnArpAddressChange( pxSMBusInstance->ucSMBusAddress ); + } +} + +/****************************************************************************** +* +* @brief Checks if a callback function to announce an SMBuss Error +* for the specified instance is present. +* If present the callback is called. +* The callback function will include the error type +* +*****************************************************************************/ +void vSMBusHandleActionBusError( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucError ) +{ + if( ( NULL != pxSMBusInstance ) && + ( NULL != pxSMBusInstance->pFnBusError ) ) + { + pxSMBusInstance->pFnBusError( ucError ); + } +} + +/****************************************************************************** +* +* @brief Checks if a callback function to announce an SMBuss Warning +* for the specified instance is present. +* If present the callback is called. +* The callback function will include the warning type +* +*****************************************************************************/ +void vSMBusHandleActionBusWarning( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucWarning ) +{ + if( ( NULL != pxSMBusInstance ) && + ( NULL != pxSMBusInstance->pFnBusWarning ) ) + { + pxSMBusInstance->pFnBusWarning( ucWarning ); + } +} + +/****************************************************************************** +* +* @brief Checks if a callback function to read data from the application software +* for the specified instance is present. +* If present it is called for the current I2C transaction. +* The callback function must return the data and size of data for the transaction. +* +*****************************************************************************/ +void vSMBusHandleActionGetI2CDataFromApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + uint8_t ucTempSendData[SMBUS_DATA_SIZE_MAX] = { 0 }; + uint16_t usTempSendDataSize = 0; + + if( ( NULL != pxSMBusInstance ) && + ( NULL != pxSMBusInstance->pFnI2CGetData ) ) + { + pxSMBusInstance->pFnI2CGetData( ucTempSendData, &usTempSendDataSize ); + + if( SMBUS_DATA_SIZE_MAX >= usTempSendDataSize ) + { + memcpy( pxSMBusInstance->ucSendData, ucTempSendData, usTempSendDataSize ); + pxSMBusInstance->usSendDataSize = usTempSendDataSize; + } + else + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, 0, __LINE__ ); + } + } +} + +/****************************************************************************** +* +* @brief Checks if a callback function to write data to the application software +* for the specified instance is present. +* If present it is called for the current I2C transaction. +* The callback function write the data and size of data and transaction ID. +* +*****************************************************************************/ +void vSMBusHandleActionWriteI2CDataToApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + uint8_t ucTempReceivedData[SMBUS_DATA_SIZE_MAX] = { 0 }; + + if( ( NULL != pxSMBusInstance ) && + ( NULL != pxSMBusInstance->pFnI2CWriteData ) ) + { + memcpy( ucTempReceivedData, pxSMBusInstance->ucReceivedData, pxSMBusInstance->usReceiveIndex ); + + pxSMBusInstance->pFnI2CWriteData( ucTempReceivedData, + pxSMBusInstance->usReceiveIndex ); + } +} + + +/****************************************************************************** +* +* @brief Checks if a callback function to write data to the application software +* for the specified instance is present. +* If present it is called for the current I2C transaction. +* The callback function write the data and size of data and transaction ID. +* +*****************************************************************************/ +void vSMBusHandleActionAnnounceI2CResultToApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint32_t ulStatus ) +{ + if( ( NULL != pxSMBusInstance ) && + ( NULL != pxSMBusInstance->pFnI2CAnnounceResult ) ) + { + pxSMBusInstance->pFnI2CAnnounceResult( ulStatus ); + } +} diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_action.h b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_action.h new file mode 100755 index 00000000..472d2775 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_action.h @@ -0,0 +1,287 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the function declarations for the action functions + * + * @file smbus_action.h + * + */ + +#ifndef _SMBUS_ACTION_H_ +#define _SMBUS_ACTION_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "smbus.h" + +#define A_SMBUS_NO_ACTION ( 0x00000000 ) +#define A_SMBUS_GET_PROTOCOL ( 0x00000001 ) +#define A_SMBUS_CREATE_EVENT_SEND_NEXT_BYTE ( 0x00000002 ) +#define MAX_SMBUS_ACTIONS ( 3 ) +#define SMBUS_ARP_DIRECTED_COMMAND_MASK ( 0x01 ) +#define SMBUS_ARP_UDID_DIRECTED_COMMAND ( 0x01 ) +#define SMBUS_ARP_DIRECTED_COMMAND_ADDRESS_MASK ( 0xFE ) +#define SMBUS_ACTION_ARP_PROTOCOL_DETERMINED ( 0 ) +#define SMBUS_ACTION_ARP_PROTOCOL_UNDETERMINED ( 1 ) + +/****************************************************************************** +* +* @brief Clears all actions that have been raised against the specified instance. +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusClearAction( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief Sets a specific actions against the specified instance +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ulAnyAction is the new action requested against the specified instance. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusAction( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint32_t ulAnyAction ); + +/****************************************************************************** +* +* @brief Resets all variables used during an SMBus message transaction back +* to their default values +* Resets the IP's Descriptor and RX FIFOs +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionResetAllData( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief Generates an E_IS_PEC_REQUIRED event against the specified instance +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionCreateEventIsPECRequired( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief Generates an E_SEND_NEXT_BYTE event against the specified instance +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionCreateEventSendNextByte( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief Reads the command byte from the Target RX FIFO, calls the callback function +* for the specified instance to get the SMBus protocol associated with the +* command byte and stores that protocol in the instance structure +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionGetProtocol( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief Reads the command byte from the Target RX FIFO for the ARP instance, +* determines the ARP protocol associated with the command byte, +* stores that protocol in the instance structure +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return SMBUS_ACTION_ARP_PROTOCOL_UNDETERMINED - If protocol could not be determined +* SMBUS_ACTION_ARP_PROTOCOL_DETERMINED - If protocol was able to be determined +* +* @note None. +* +*****************************************************************************/ +uint8_t ucSMBusHandleActionGetARPProtocol( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief Checks if a callback function to read data from the application software +* for the specified instance is present. +* If present it is called for the current SMBus command. +* The callback function must return the data and size of data for the command. +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionGetDataFromApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief Checks if a callback function to write data to the application software +* for the specified instance is present. +* If present it is called for the current SMBus command. +* The callback function write the command, data and size of data and transaction ID. +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ulTransactionID is current Controller transaction number. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionWriteDataToApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucTransactionID ); + +/****************************************************************************** +* +* @brief Checks if a callback function to announce the result of the SMBus transaction +* for the specified instance is present. +* If present the callback is called. +* The callback function will include the command, transaction ID and the result +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucTransactionID is current Controller transaction number. +* @param ulStatus is the result of the SMBus transaction +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionAnnounceResultToApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucTransactionID, + uint32_t ulStatus ); + +/****************************************************************************** +* +* @brief Checks if a callback function to announce that an ARP Assign Address +* for the specified instance is present. +* If present the callback is called. +* The callback function will include the newly assigned address +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionNotifyAddressChangeToApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance, + uint8_t ucTransactionID ); + +/****************************************************************************** +* +* @brief Checks if a callback function to announce an SMBuss Error +* for the specified instance is present. +* If present the callback is called. +* The callback function will include the error type +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucError is the error enum +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionBusError( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucError ); + +/****************************************************************************** +* +* @brief Checks if a callback function to announce an SMBuss Warning +* for the specified instance is present. +* If present the callback is called. +* The callback function will include the warning type +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucWarning is the warning enum +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionBusWarning( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucWarning ); + +/****************************************************************************** +* +* @brief Checks if a callback function to read data from the application software +* for the specified instance is present. +* If present it is called for the current I2C transaction. +* The callback function must return the data and size of data for the command. +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionGetI2CDataFromApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief Checks if a callback function to write data to the application software +* for the specified instance is present. +* If present it is called for the current I2C transaction. +* The callback function write the command, data and size of data and transaction ID. +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionWriteI2CDataToApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief Checks if a callback function to announce the result of the I2C transaction +* for the specified instance is present. +* If present the callback is called. +* The callback function will include the command and the result +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ulStatus is the result of the SMBus transaction +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusHandleActionAnnounceI2CResultToApplication( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint32_t ulStatus ); + + +#ifdef __cplusplus +} +#endif + +#endif /* _SMBUS_ACTION_H_ */ diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_circular_log.c b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_circular_log.c new file mode 100755 index 00000000..316b2b79 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_circular_log.c @@ -0,0 +1,276 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains functions to initialize and to add log entries to the SMBus Driver circular log + * for the SMBus driver. + * + * @file smbus_circular_log.c + * + */ + +#include "smbus_internal.h" +#include "smbus.h" +#include "smbus_state.h" +#include "smbus_event.h" + +#define SMBUS_LOG_IS_OCCUPIED ( 0xAAABACAD ) +#define SMBUS_LOG_IS_NOT_OCCUPIED ( 0 ) + +/********************** Static function declarations ***************************/ + +/****************************************************************************** +* +* @brief Is a conversion function from the state machine event to character string +* to be used by logging functions +* +* @param xEvent is any event handled by the state machine +* +* @return A character string +* +* @note None. +* +*****************************************************************************/ +static char* prvpcConvertEventTypeToText( SMBUS_LOG_EVENT_TYPE xEvent ); + +/****************************************************************************** +* +* @brief This function formats a log entry as a text string ready to be displayed +* The format of the string depends on the type of event that was logged +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure +* @param entry is the index of the log entry in the buffer +* @param pcLogBuffer is a char buffer containing the complete log to display +* @param pslLineSize is pointer to the size of the log string being added +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvFormatLine( SMBUS_PROFILE_TYPE* pxSMBusProfile, int entry, char* pcLogBuffer, + int* pslLineSize ); + +/*******************************************************************************/ + +/****************************************************************************** +* +* @brief This function formats a log entry as a text string ready to be displayed +* The format of the string depends on the type of event that was logged +* +*****************************************************************************/ +static char* prvpcConvertEventTypeToText( SMBUS_LOG_EVENT_TYPE xEvent ) +{ + char* pcReturnText = " "; + + if( SMBUS_LOG_EVENT_INTERRUPT_EVENT == xEvent ) + { + pcReturnText = "INTERRUPT"; + } + else if( SMBUS_LOG_EVENT_FSM_EVENT == xEvent ) + { + pcReturnText = "FSM "; + } + else if( SMBUS_LOG_EVENT_ERROR == xEvent ) + { + pcReturnText = "ERROR "; + } + else if( SMBUS_LOG_EVENT_HW_READ == xEvent ) + { + pcReturnText = "HW_READ "; + } + else if( SMBUS_LOG_EVENT_HW_WRITE == xEvent ) + { + pcReturnText = "HW_WRITE "; + } + else if( SMBUS_LOG_EVENT_PROTOCOL == xEvent ) + { + pcReturnText = "PROTOCOL "; + } + else if( SMBUS_LOG_EVENT_DEBUG == xEvent ) + { + pcReturnText = "DEBUG "; + } + else if( SMBUS_LOG_EVENT_TRYREAD == xEvent ) + { + pcReturnText = "TRYREAD "; + } + else if( SMBUS_LOG_EVENT_TRYWRITE == xEvent ) + { + pcReturnText = "TRYWRITE "; + } + + return (pcReturnText); +} + +/****************************************************************************** +* +* @brief This function formats a log entry as a text string ready to be displayed +* The format of the string depends on the type of event that was logged +* +*****************************************************************************/ +static void prvvFormatLine( SMBUS_PROFILE_TYPE* pxSMBusProfile, int entry, char* pcLogBuffer, + int* pslLineSize ) +{ + char* pcState = NULL; + char* pcEvent = NULL; + char* pcProtocol = NULL; + + if( ( NULL != pxSMBusProfile ) && + ( NULL != pcLogBuffer ) && + ( NULL != pslLineSize ) ) + { + switch( pxSMBusProfile->xCircularBuffer[entry].xEvent ) + { + case SMBUS_LOG_EVENT_TRYWRITE: /* Fall through deliberate */ + case SMBUS_LOG_EVENT_TRYREAD: /* Fall through deliberate */ + case SMBUS_LOG_EVENT_DEBUG: + *pslLineSize = sprintf( pcLogBuffer, "%04d %07d %s %2d 0x%08x line %d\r\n", entry, + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulTicks, + prvpcConvertEventTypeToText( pxSMBusProfile->xCircularBuffer[entry].xEvent ), + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulInstance, + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulEntry1, + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulEntry2 ); + break; + + case SMBUS_LOG_EVENT_PROTOCOL: + pcProtocol = pcProtocolToString( pxSMBusProfile->xCircularBuffer[entry].ulEntry2 ); + *pslLineSize = sprintf( pcLogBuffer, "%04d %07d %s %2d 0x%08x %s\r\n", entry, + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulTicks, + prvpcConvertEventTypeToText( pxSMBusProfile->xCircularBuffer[entry].xEvent ), + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulInstance, + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulEntry1, + pcProtocol ); + break; + + case SMBUS_LOG_EVENT_HW_WRITE: /* Fall through deliberate */ + case SMBUS_LOG_EVENT_HW_READ: /* Fall through deliberate */ + case SMBUS_LOG_EVENT_INTERRUPT_EVENT: + *pslLineSize = sprintf( pcLogBuffer, "%04d %07d %s %2d 0x%08x 0x%08x\r\n", entry, + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulTicks, + prvpcConvertEventTypeToText( pxSMBusProfile->xCircularBuffer[entry].xEvent ), + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulInstance, + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulEntry1, + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulEntry2 ); + break; + + case SMBUS_LOG_EVENT_ERROR: /* Fall through deliberate */ + case SMBUS_LOG_EVENT_FSM_EVENT: + pcState = ( char* )pcStateToString( pxSMBusProfile->xCircularBuffer[entry].ulEntry1 ); + pcEvent = ( char* )pcEventToString( pxSMBusProfile->xCircularBuffer[entry].ulEntry2 ); + *pslLineSize = sprintf( pcLogBuffer, "%04d %07d %s %2d %s %s\r\n", entry, + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulTicks, + prvpcConvertEventTypeToText( pxSMBusProfile->xCircularBuffer[entry].xEvent ), + ( unsigned int )pxSMBusProfile->xCircularBuffer[entry].ulInstance, pcState, pcEvent ); + break; + + default: + *pslLineSize = 0; + break; + } + } +} + +/******************************************************************************* +* +* @brief Will retreive the log as a character string +* +*******************************************************************************/ +void vLogDisplayLog( SMBUS_PROFILE_TYPE* pxSMBusProfile, char* pcLogBuffer, uint32_t* usLogSizeBytes ) +{ + int slStart = 0; + int i = 0; + int slLineSize = 0; + uint32_t usLogSize = 0; + + if( ( NULL != pxSMBusProfile ) && + ( NULL != pcLogBuffer ) && + ( NULL != usLogSizeBytes ) ) + { + slStart = pxSMBusProfile->xLogCircularBuffer.ulWrite; + + for( i = slStart; i < SMBUS_MAX_CIRCULAR_LOG_ENTRIES; i++ ) + { + if( SMBUS_LOG_IS_OCCUPIED == pxSMBusProfile->xCircularBuffer[i].ulIsOccupied ) + { + prvvFormatLine( pxSMBusProfile, i, (pcLogBuffer + usLogSize), &slLineSize ); + usLogSize += ( uint32_t )slLineSize; + } + } + + for( i = 0; i < slStart; i++ ) + { + if( SMBUS_LOG_IS_OCCUPIED == pxSMBusProfile->xCircularBuffer[i].ulIsOccupied ) + { + prvvFormatLine( pxSMBusProfile, i, ( pcLogBuffer + usLogSize ), &slLineSize ); + usLogSize += ( uint32_t )slLineSize; + } + } + + *usLogSizeBytes = usLogSize; + } +} + +/******************************************************************************* +* +* @brief Initializes the debug log. Setting its pointer to zero +* +*******************************************************************************/ +void vLogInitialize( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t i = 0; + + if( NULL != pxSMBusProfile ) + { + for( i = 0; i < ( SMBUS_MAX_CIRCULAR_LOG_ENTRIES ); i++ ) + { + pxSMBusProfile->xCircularBuffer[i].ulIsOccupied = SMBUS_LOG_IS_NOT_OCCUPIED; + pxSMBusProfile->xCircularBuffer[i].ulEntry1 = 0x00; + pxSMBusProfile->xCircularBuffer[i].ulEntry2 = 0x00; + pxSMBusProfile->xCircularBuffer[i].ulTicks = 0x00; + } + + pxSMBusProfile->xLogCircularBuffer.ulWrite = 0; + pxSMBusProfile->xLogCircularBuffer.ulRead = 0; + } +} + +/******************************************************************************* +* +* @brief Will add a log entry into the debug log +* +*******************************************************************************/ +void vLogAddEntry( SMBUS_PROFILE_TYPE* pxSMBusProfile, SMBUS_LOG_LEVEL_TYPE xLogLevel, uint32_t ulInstance, + SMBUS_LOG_EVENT_TYPE Log_Event, uint32_t ulEntry1, uint32_t ulEntry2 ) +{ + uint32_t ulTicks = 0; + + if( NULL != pxSMBusProfile ) + { + if( xLogLevel <= pxSMBusProfile->xLogLevel ) + { + if( NULL != pxSMBusProfile->pFnReadTicks ) + { + pxSMBusProfile->pFnReadTicks( &ulTicks ); + } + + pxSMBusProfile->xCircularBuffer[pxSMBusProfile->xLogCircularBuffer.ulWrite].ulTicks = ulTicks; + pxSMBusProfile->xCircularBuffer[pxSMBusProfile->xLogCircularBuffer.ulWrite].xEvent = Log_Event; + pxSMBusProfile->xCircularBuffer[pxSMBusProfile->xLogCircularBuffer.ulWrite].ulInstance = ulInstance; + pxSMBusProfile->xCircularBuffer[pxSMBusProfile->xLogCircularBuffer.ulWrite].ulEntry1 = ulEntry1; + pxSMBusProfile->xCircularBuffer[pxSMBusProfile->xLogCircularBuffer.ulWrite].ulEntry2 = ulEntry2; + pxSMBusProfile->xCircularBuffer[pxSMBusProfile->xLogCircularBuffer.ulWrite].ulIsOccupied = SMBUS_LOG_IS_OCCUPIED; + + if( (SMBUS_MAX_CIRCULAR_LOG_ENTRIES - 1) <= pxSMBusProfile->xLogCircularBuffer.ulWrite ) + { + /* For debug Just write over last log */ + pxSMBusProfile->xLogCircularBuffer.ulWrite = ( SMBUS_MAX_CIRCULAR_LOG_ENTRIES - 1 ); + /* pxSMBusProfile->xLogCircularBuffer.ulWrite = 0; */ + } + else + { + pxSMBusProfile->xLogCircularBuffer.ulWrite++; + } + } + } +} diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_driver.c b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_driver.c new file mode 100755 index 00000000..9ffac64f --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_driver.c @@ -0,0 +1,1623 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the user API definitions + * for the SMBus driver. + * + * @file smbus_driver.c + * + */ +#include +#include "smbus.h" +#include "i2c.h" +#include "smbus_internal.h" +#include "smbus_hardware_access.h" +#include "smbus_event.h" +#include "smbus_event_buffer.h" +#include "smbus_action.h" +#include "smbus_state.h" +#include "smbus_interrupt_handler.h" + +#include "smbus_version.h" + +static SMBUS_PROFILE_TYPE xSMBusProfile = +{ + .pFnReadTicks = 0, + .pvBaseAddress = 0, + .ulTransactionID = 0, + .ulInitialize = 0, + .xLogCircularBuffer = { 0 }, + .xCircularBuffer = { { 0 } }, + .xSMBusInstance = { { 0 } }, + .ucInstanceInPlay = SMBUS_INVALID_INSTANCE, + .ucActiveTargetInstance = SMBUS_INVALID_INSTANCE, + .xLogLevel = 0, + .ucUDIDMatch = { 0 } + }; + +static char* prvpcProtocol_SMBUS_PROTOCOL_QUICK_COMMAND_HI = "SMBUS_PROTOCOL_QUICK_COMMAND_HI"; +static char* prvpcProtocol_SMBUS_PROTOCOL_QUICK_COMMAND_LO = "SMBUS_PROTOCOL_QUICK_COMMAND_LO"; +static char* prvpcProtocol_SMBUS_PROTOCOL_SEND_BYTE = "SMBUS_PROTOCOL_SEND_BYTE"; +static char* prvpcProtocol_SMBUS_PROTOCOL_RECEIVE_BYTE = "SMBUS_PROTOCOL_RECEIVE_BYTE"; +static char* prvpcProtocol_SMBUS_PROTOCOL_WRITE_BYTE = "SMBUS_PROTOCOL_WRITE_BYTE"; +static char* prvpcProtocol_SMBUS_PROTOCOL_WRITE_WORD = "SMBUS_PROTOCOL_WRITE_WORD"; +static char* prvpcProtocol_SMBUS_PROTOCOL_READ_BYTE = "SMBUS_PROTOCOL_READ_BYTE"; +static char* prvpcProtocol_SMBUS_PROTOCOL_READ_WORD = "SMBUS_PROTOCOL_READ_WORD"; +static char* prvpcProtocol_SMBUS_PROTOCOL_PROCESS_CALL = "SMBUS_PROTOCOL_PROCESS_CALL"; +static char* prvpcProtocol_SMBUS_PROTOCOL_BLOCK_WRITE = "SMBUS_PROTOCOL_BLOCK_WRITE"; +static char* prvpcProtocol_SMBUS_PROTOCOL_BLOCK_READ = "SMBUS_PROTOCOL_BLOCK_READ"; +static char* prvpcProtocol_SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL = "SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL"; +static char* prvpcProtocol_SMBUS_PROTOCOL_HOST_NOTIFY = "SMBUS_PROTOCOL_HOST_NOTIFY"; +static char* prvpcProtocol_SMBUS_PROTOCOL_WRITE_32 = "SMBUS_PROTOCOL_WRITE_32"; +static char* prvpcProtocol_SMBUS_PROTOCOL_READ_32 = "SMBUS_PROTOCOL_READ_32"; +static char* prvpcProtocol_SMBUS_PROTOCOL_WRITE_64 = "SMBUS_PROTOCOL_WRITE_64"; +static char* prvpcProtocol_SMBUS_PROTOCOL_READ_64 = "SMBUS_PROTOCOL_READ_64"; +static char* prvpcProtocol_SMBUS_PROTOCOL_NONE = "SMBUS_PROTOCOL_NONE"; +static char* prvpcProtocol_SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP = "SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP"; +static char* prvpcProtocol_SMBUS_ARP_PROTOCOL_RESET_DEVICE = "SMBUS_ARP_PROTOCOL_RESET_DEVICE"; +static char* prvpcProtocol_SMBUS_ARP_PROTOCOL_GET_UDID = "SMBUS_ARP_PROTOCOL_GET_UDID"; +static char* prvpcProtocol_SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS = "SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS"; +static char* prvpcProtocol_SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED = "SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED"; +static char* prvpcProtocol_SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED = "SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED"; +static char* prvpcProtocol_UNKNOWN = "SMBUS_PROTOCOL_UNKNOWN"; + +/* Driver Functions */ + +/******************************************************************************* +* +* @brief Does a ceiling conversion on a floating point number and returns the +* rounded up interger value +* +*******************************************************************************/ +uint32_t ulSMBusCeil( float fNum ) +{ + uint32_t ulNum = ( uint32_t )fNum; + if ( fNum != ( float )ulNum ) + { + ulNum++; + } + + return ( ulNum ); +} + +/******************************************************************************* +* +* @brief Converts a protocol enum value to a text string for logging +* +*******************************************************************************/ +SMBus_Error_Type xSMBusFirewallCheck( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + SMBus_Error_Type xError = SMBUS_SUCCESS; + int i = 0; + + if( NULL != pxSMBusProfile ) + { + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_INSTANCES; i++ ) + { + if( ( SMBUS_FIREWALL1 != pxSMBusProfile->xSMBusInstance[i].ulFirewall1 ) || + ( SMBUS_FIREWALL2 != pxSMBusProfile->xSMBusInstance[i].ulFirewall2 ) || + ( SMBUS_FIREWALL3 != pxSMBusProfile->xSMBusInstance[i].ulFirewall3 ) ) + { + xError = SMBUS_ERROR; + break; + } + } + } + else + { + xError = SMBUS_ERROR; + } + + return xError; +} + +/******************************************************************************* +* +* @brief Will walk through all active instances, check if any events have been +* raised against that instance and call into the state machine for that +* instance with each event found +* +*******************************************************************************/ +void vSMBusEventQueueHandle( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint8_t ucAnyEvent; + int i; + uint32_t ulRead_Position; + + if( NULL != pxSMBusProfile ) + { + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_INSTANCES; i++ ) + { + if( SMBUS_TRUE == pxSMBusProfile->xSMBusInstance[i].ucInstanceInUse ) + { + while( ( ucEventBufferTryRead( &( pxSMBusProfile->xSMBusInstance[i].xEventSourceCircularBuffer ), + &ucAnyEvent, &ulRead_Position ) ) ) + { + vSMBusFSM( &( pxSMBusProfile->xSMBusInstance[i] ), ucAnyEvent ); + } + } + } + } +} + +/******************************************************************************* +* +* @brief Retrieves the SMBus driver version +* +*****************************************************************************/ +SMBus_Error_Type xSMBusGetVersion( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, SMBUS_VERSION_TYPE* pxSMBusVersion ) +{ +#ifdef GIT_TAG + SMBus_Error_Type xError = SMBUS_ERROR; + + if( NULL != pxSMBusVersion ) + { + pxSMBusVersion->ucSwVerMajor = GIT_TAG_VER_MAJOR; + pxSMBusVersion->ucSwVerMinor = GIT_TAG_VER_MINOR; + pxSMBusVersion->ucSwVerPatch = GIT_TAG_VER_PATCH; + pxSMBusVersion->ucSwDevBuild = GIT_TAG_VER_DEV_COMMITS; + pxSMBusVersion->ucSwTestBuild = ( 0 == GIT_STATUS ) ? ( 0 ):( 1 ); + + if( NULL != pxSMBusProfile ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + pxSMBusVersion->usIpVerMajor = 0; + pxSMBusVersion->usIpVerMinor = 0; + } + else + { + uint32_t ulIpVersion = ulSMBusHWReadIPVersion( pxSMBusProfile ); + + pxSMBusVersion->usIpVerMajor = ( uint16_t )( ( ulIpVersion & 0xFFFF0000 ) >> 16 ); + pxSMBusVersion->usIpVerMinor = ( uint16_t )( ulIpVersion & 0x0000FFFF ); + + xError = SMBUS_SUCCESS; + } + } + else + { + pxSMBusVersion->usIpVerMajor = 0; + pxSMBusVersion->usIpVerMinor = 0; + } + } + + return ( xError ); +#endif +} + +/**************************************************************************** +* +* @brief Disables and then clears all SMBus interrupts +* +*****************************************************************************/ +SMBus_Error_Type xSMBusInterruptDisableAndClearInterrupts( struct SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + SMBus_Error_Type xError = SMBUS_ERROR; + + if( NULL != pxSMBusProfile ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + /* Disable all Interrupts */ + vSMBusHWWriteIRQGIEEnable( pxSMBusProfile, 0 ); + vSMBusHWWriteIRQIER( pxSMBusProfile, 0 ); + vSMBusHWWriteERRIRQIER( pxSMBusProfile, 0 ); + + /* Clear Interrupts - Write 1 to clear */ + vSMBusHWWriteIRQISR( pxSMBusProfile, 0x0000FFFF ); + vSMBusHWWriteERRIRQISR( pxSMBusProfile, 0x000FFFFF ); + + xError = SMBUS_SUCCESS; + } + } + + return ( xError ); +} + +/******************************************************************************* +* +* @brief enables all necessary SMBus interrupts +* +*******************************************************************************/ +SMBus_Error_Type xSMBusInterruptEnableInterrupts( struct SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + SMBus_Error_Type xError = SMBUS_ERROR; + + if( NULL != pxSMBusProfile ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + /* Enable all Interrupts */ + vSMBusHWWriteIRQIER( pxSMBusProfile, 0x0000DFEF ); + vSMBusHWWriteERRIRQIER( pxSMBusProfile, 0x000FFFFF ); + vSMBusHWWriteIRQGIEEnable( pxSMBusProfile, 1 ); + + xError = SMBUS_SUCCESS; + } + } + + return ( xError ); +} + +/******************************************************************************* +* +* @brief Checks hardware is present at the supplied base address +* Sets up hardware registers for the frequency class supplied +* initializes software structures, sets up log and event queues +* +*****************************************************************************/ +SMBus_Error_Type xInitSMBus( struct SMBUS_PROFILE_TYPE** ppxSMBusProfile, SMBus_Freq_Class_Type xFrequencyClass, void * pvBaseAddress, + SMBUS_LOG_LEVEL_TYPE xLogLevel, SMBUS_USER_SUPPLIED_ENVIRONMENT_READ_TICKS pFnReadTicks ) +{ + SMBus_Error_Type xError = SMBUS_SUCCESS; + int i = 0; + int j = 0; + uint32_t ulAXIClockFrequency = 0; + uint32_t ulPHYInputGlitchFilterEnable = 0; + uint32_t ulPHYInputGlitchFilterDuration = 0; + uint32_t ulConstant = 0; + + /* NOTE: pFnReadTicks can be NULL. It will be checked in the + logging function where it is used */ + if( ( NULL != ppxSMBusProfile ) && + ( NULL == *ppxSMBusProfile ) && + ( NULL != pvBaseAddress ) && + ( SMBUS_FREQ_MAX > xFrequencyClass ) && + ( SMBUS_LOG_LEVEL_MAX > xLogLevel ) ) + { + *ppxSMBusProfile = &xSMBusProfile; + + /* Check if we have initialized using this profile already */ + if( SMBUS_INITIALIZATION_CODE != (*ppxSMBusProfile)->ulInitialize ) + { + /* Circular Event Log Initialize */ + vLogInitialize( *ppxSMBusProfile ); + (*ppxSMBusProfile)->pFnReadTicks = pFnReadTicks; + (*ppxSMBusProfile)->pvBaseAddress = pvBaseAddress; + (*ppxSMBusProfile)->xLogLevel = xLogLevel; + + uint32_t version = ulSMBusHWReadIPVersion( *ppxSMBusProfile ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, + SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, version, __LINE__ ); + + if( SMBUS_MAGIC_NUMBER == ulSMBusHWReadIPMagicNum( *ppxSMBusProfile ) ) + { + ulAXIClockFrequency = ulSMBusHWReadBuildConfig0( *ppxSMBusProfile ); + ulPHYInputGlitchFilterEnable = ulSMBusHWReadPHYFilterControlEnable( *ppxSMBusProfile ); + + if( 1 == ulPHYInputGlitchFilterEnable ) + { + ulPHYInputGlitchFilterDuration = + SMBUS_GET_GLITCH_FILTER_DUR( ulSMBusHWReadPHYFilterControlDuration( *ppxSMBusProfile ) ); + ulConstant = SMBUS_GET_CONSTANT_WITH_GLITCH( ulPHYInputGlitchFilterDuration ); + } + else + { + ulConstant = SMBUS_GET_CONSTANT; + } + + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TBUF_MIN_100KHZ, ulAXIClockFrequency ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TBUF_MIN_400KHZ, ulAXIClockFrequency ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TBUF_MIN_1MHZ, ulAXIClockFrequency ), __LINE__ ); + + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TSU_DAT_MIN_100KHZ, ulAXIClockFrequency ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TSU_DAT_MIN_400KHZ, ulAXIClockFrequency ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TSU_DAT_MIN_1MHZ, ulAXIClockFrequency ), __LINE__ ); + + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_TGT_DATA_HOLD_100KHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TGT_DATA_HOLD_400KHZ, ulAXIClockFrequency ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TGT_DATA_HOLD_1MHZ, ulAXIClockFrequency ), __LINE__ ); + + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_DATA_HOLD_100KHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_CTLR_DATA_HOLD_400KHZ, ulAXIClockFrequency ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_CTLR_DATA_HOLD_1MHZ, ulAXIClockFrequency ), __LINE__ ); + + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_START_HOLD_100KHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_START_HOLD_400KHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_START_HOLD_1MHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_START_SETUP_100KHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_START_SETUP_400KHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_START_SETUP_1MHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_STOP_SETUP_100KHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_STOP_SETUP_400KHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_STOP_SETUP_1MHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_CLK_LOW_100KHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_CLK_LOW_400KHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_CLK_LOW_1MHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_CLK_HIGH_100KHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_CLK_HIGH_400KHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_CLK_HIGH_1MHZ, ulAXIClockFrequency, ulConstant ), __LINE__ ); + + switch( xFrequencyClass ) + { + case SMBUS_FREQ_100KHZ: + vSMBusHWWritePHYBusFreetime( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TBUF_MIN_100KHZ, ulAXIClockFrequency ) ); + vSMBusHWWritePHYTgtDataSetupTgtDataSetup( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TSU_DAT_MIN_100KHZ, ulAXIClockFrequency ) ); + vSMBusHWWritePHYTgtDataHold( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_TGT_DATA_HOLD_100KHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlDataHold( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_DATA_HOLD_100KHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlStartHold( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_START_HOLD_100KHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlStartSetup( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_START_SETUP_100KHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlStopSetup( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_STOP_SETUP_100KHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlClkTLow( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_CLK_LOW_100KHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlClkTHigh( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_CLK_HIGH_100KHZ, ulAXIClockFrequency, ulConstant ) ); + break; + + case SMBUS_FREQ_400KHZ: + vSMBusHWWritePHYBusFreetime( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TBUF_MIN_400KHZ, ulAXIClockFrequency ) ); + vSMBusHWWritePHYTgtDataSetupTgtDataSetup( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TSU_DAT_MIN_400KHZ, ulAXIClockFrequency ) ); + vSMBusHWWritePHYTgtDataHold( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TGT_DATA_HOLD_400KHZ, ulAXIClockFrequency ) ); + vSMBusHWWritePHYCtrlDataHold( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_CTLR_DATA_HOLD_400KHZ, ulAXIClockFrequency ) ); + vSMBusHWWritePHYCtrlStartHold( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_START_HOLD_400KHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlStartSetup( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_START_SETUP_400KHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlStopSetup( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_STOP_SETUP_400KHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlClkTLow( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_CLK_LOW_400KHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlClkTHigh( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_CLK_HIGH_400KHZ, ulAXIClockFrequency, ulConstant ) ); + break; + + case SMBUS_FREQ_1MHZ: + vSMBusHWWritePHYBusFreetime( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TBUF_MIN_1MHZ, ulAXIClockFrequency ) ); + vSMBusHWWritePHYTgtDataSetupTgtDataSetup( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TSU_DAT_MIN_1MHZ, ulAXIClockFrequency ) ); + vSMBusHWWritePHYTgtDataHold( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_TGT_DATA_HOLD_1MHZ, ulAXIClockFrequency ) ); + vSMBusHWWritePHYCtrlDataHold( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE( SMBUS_CTLR_DATA_HOLD_1MHZ, ulAXIClockFrequency ) ); + vSMBusHWWritePHYCtrlStartHold( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_START_HOLD_1MHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlStartSetup( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_START_SETUP_1MHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlStopSetup( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_STOP_SETUP_1MHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlClkTLow( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_CLK_LOW_1MHZ, ulAXIClockFrequency, ulConstant ) ); + vSMBusHWWritePHYCtrlClkTHigh( *ppxSMBusProfile, + SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( SMBUS_CTLR_CLK_HIGH_1MHZ, ulAXIClockFrequency, ulConstant ) ); + break; + + default: + xError = SMBUS_ERROR; + break; + } + + if( SMBUS_SUCCESS == xError ) + { + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, + SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + ulSMBusHWReadBuildConfig0( *ppxSMBusProfile ), __LINE__ ); + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_INFO, + SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_DEBUG, + ulSMBusHWReadBuildConfig1( *ppxSMBusProfile ), __LINE__ ); + + (*ppxSMBusProfile)->ucInstanceInPlay = SMBUS_INVALID_INSTANCE; + (*ppxSMBusProfile)->ulTransactionID = 0; + + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_INSTANCES; i++ ) + { + (*ppxSMBusProfile)->xSMBusInstance[i].ulFirewall1 = SMBUS_FIREWALL1; + (*ppxSMBusProfile)->xSMBusInstance[i].ulFirewall2 = SMBUS_FIREWALL2; + (*ppxSMBusProfile)->xSMBusInstance[i].ulFirewall3 = SMBUS_FIREWALL3; + (*ppxSMBusProfile)->xSMBusInstance[i].ucInstanceInUse = SMBUS_FALSE; + (*ppxSMBusProfile)->xSMBusInstance[i].ucSMBusAddress = 0; + (*ppxSMBusProfile)->xSMBusInstance[i].pFnGetProtocol = NULL; + (*ppxSMBusProfile)->xSMBusInstance[i].pFnGetData = NULL; + (*ppxSMBusProfile)->xSMBusInstance[i].pFnWriteData = NULL; + (*ppxSMBusProfile)->xSMBusInstance[i].pFnAnnounceResult = NULL; + (*ppxSMBusProfile)->xSMBusInstance[i].pFnArpAddressChange = NULL; + (*ppxSMBusProfile)->xSMBusInstance[i].pFnBusError = NULL; + (*ppxSMBusProfile)->xSMBusInstance[i].pFnBusWarning = NULL; + (*ppxSMBusProfile)->xSMBusInstance[i].ucPECRequired = SMBUS_FALSE; + (*ppxSMBusProfile)->xSMBusInstance[i].xARPCapability = SMBUS_ARP_CAPABILITY_UNKNOWN; + (*ppxSMBusProfile)->xSMBusInstance[i].ucARFlag = SMBUS_FALSE; + (*ppxSMBusProfile)->xSMBusInstance[i].ucAVFlag = SMBUS_FALSE; + (*ppxSMBusProfile)->xSMBusInstance[i].xProtocol = SMBUS_PROTOCOL_NONE; + (*ppxSMBusProfile)->xSMBusInstance[i].ucThisInstanceNumber = SMBUS_INVALID_INSTANCE; + (*ppxSMBusProfile)->xSMBusInstance[i].ucUDIDMatchedInstance = SMBUS_INVALID_INSTANCE; + + vEventBufferInitialize( &( (*ppxSMBusProfile)->xSMBusInstance[i].xEventSourceCircularBuffer ), + (*ppxSMBusProfile)->xSMBusInstance[i].xCircularBuffer, SMBUS_MAX_EVENT_ELEMENTS ); + + /* Add a pointer back to the top level */ + (*ppxSMBusProfile)->xSMBusInstance[i].pxSMBusProfile = *ppxSMBusProfile; + + /* Reset logs */ + for( j = 0; j < SMBUS_PROTOCOL_NONE; j++ ) + { + (*ppxSMBusProfile)->xSMBusInstance[i].ulMessagesComplete[j] = 0; + (*ppxSMBusProfile)->xSMBusInstance[i].ulMessagesInitiated[j] = 0; + } + } + vSMBusHWWriteCtrlDescFifoReset( *ppxSMBusProfile, 1 ); + vSMBusHWWriteTgtRxFifoReset( *ppxSMBusProfile, 1 ); + vSMBusHWWriteCtrlRxFifoReset( *ppxSMBusProfile, 1 ); + } + (*ppxSMBusProfile)->ulInitialize = SMBUS_INITIALIZATION_CODE; + } + else + { + xError = SMBUS_ERROR; + } + } + else + { + xError = SMBUS_ERROR; + } + } + else + { + xError = SMBUS_ERROR; + } + + return ( xError ); +} + +/******************************************************************************* +* +* @brief Checks all instances have already been removed +* If so sets Profile structure to default values +* +*****************************************************************************/ +SMBus_Error_Type xDeinitSMBus( struct SMBUS_PROFILE_TYPE** ppxSMBusProfile ) +{ + SMBus_Error_Type xError = SMBUS_SUCCESS; + int i = 0; + + if( ( NULL != ppxSMBusProfile ) && + ( NULL != *ppxSMBusProfile ) ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( *ppxSMBusProfile ) ) + { + xError = SMBUS_ERROR; + vLogAddEntry( *ppxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_INSTANCES; i++ ) + { + if( SMBUS_TRUE == (*ppxSMBusProfile)->xSMBusInstance[i].ucInstanceInUse ) + { + xError = SMBUS_ERROR; + break; + } + } + } + + if( SMBUS_SUCCESS == xError ) + { + xSMBusInterruptDisableAndClearInterrupts( *ppxSMBusProfile ); + (*ppxSMBusProfile)->pvBaseAddress = NULL; + (*ppxSMBusProfile)->pFnReadTicks = NULL; + (*ppxSMBusProfile)->ulInitialize = SMBUS_DEINITIALIZATION_CODE; + *ppxSMBusProfile = NULL; + } + } + else + { + xError = SMBUS_ERROR; + } + + return ( xError ); +} + +/******************************************************************************* +* +* @brief Checks that a free instance slot is available and if so stores the +* supplied data associated with the instance and enables the hardware +* to send or receive SMBus messages for the supplied instance +* +*******************************************************************************/ +uint8_t ucCreateSMBusInstance( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, + uint8_t ucSMBusAddress, + uint8_t ucUDID[SMBUS_UDID_LENGTH], + SMBus_ARP_Capability xARPCapability, + SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_PROTOCOL_TYPE pFnGetProtocol, + SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE pFnGetData, + SMBUS_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE pFnWriteData, + SMBUS_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE pFnAnnounceResult, + SMBUS_USER_SUPPLIED_ENVIRONMENT_ARP_ADRRESS_CHANGE pFnArpAddressChange, + SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR pFnBusError, + SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING pFnBusWarning, + uint8_t ucSimpleDevice) +{ + uint8_t ucInstanceToReturn = SMBUS_INVALID_INSTANCE; + uint8_t ucOkToContinue = SMBUS_TRUE; + int i = 0; + int j = 0; + + if( ( NULL != pxSMBusProfile ) && + ( ( NULL != pFnGetProtocol ) || ( SMBUS_TRUE == ucSimpleDevice ) ) && + ( NULL != pFnGetData ) && + ( NULL != pFnWriteData ) && + ( NULL != pFnAnnounceResult ) ) + { + + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + ucOkToContinue = SMBUS_FALSE; + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + /* Pre-checks before allowing the instance to be added */ + if( ( SMBUS_ARP_CAPABILITY_UNKNOWN == xARPCapability ) || + ( SMBUS_ARP_NON_ARP_CAPABLE < xARPCapability) ) + { + ucOkToContinue = SMBUS_FALSE; + } + + if( ( SMBUS_INVALID_ADDRESS_MASK & ucSMBusAddress ) && + ( SMBUS_ARP_CAPABLE == xARPCapability ) && + ( SMBUS_UDID_DYNAMIC_AND_PERSISTENT != ( ucUDID[SMBUS_UDID_DEVICE_CAPABILITIES_BYTE] & SMBUS_UDID_ADDRESS_TYPE_MASK ) ) ) + { + ucOkToContinue = SMBUS_FALSE; + } + + if( ( SMBUS_ARP_CAPABLE == xARPCapability ) && + ( SMBUS_UDID_FIXED_ADDRESS == ( ucUDID[SMBUS_UDID_DEVICE_CAPABILITIES_BYTE] & SMBUS_UDID_ADDRESS_TYPE_MASK ) ) ) + { + ucOkToContinue = SMBUS_FALSE; + } + } + + if( SMBUS_TRUE == ucOkToContinue ) + { + if( SMBUS_ARP_CAPABLE != xARPCapability ) + { + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + if( SMBUS_TRUE == pxSMBusProfile->xSMBusInstance[i].ucInstanceInUse ) + { + /* Check that the address is not already being used */ + if( pxSMBusProfile->xSMBusInstance[i].ucSMBusAddress == ucSMBusAddress ) + { + ucOkToContinue = SMBUS_FALSE; + break; + } + } + } + } + } + + if( SMBUS_TRUE == ucOkToContinue ) + { + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + if( SMBUS_FALSE == pxSMBusProfile->xSMBusInstance[i].ucInstanceInUse ) + { + pxSMBusProfile->xSMBusInstance[i].ucSMBusAddress = ucSMBusAddress; + pxSMBusProfile->xSMBusInstance[i].pFnGetProtocol = pFnGetProtocol; + pxSMBusProfile->xSMBusInstance[i].pFnGetData = pFnGetData; + pxSMBusProfile->xSMBusInstance[i].pFnWriteData = pFnWriteData; + pxSMBusProfile->xSMBusInstance[i].pFnAnnounceResult = pFnAnnounceResult; + pxSMBusProfile->xSMBusInstance[i].pFnArpAddressChange = pFnArpAddressChange; + pxSMBusProfile->xSMBusInstance[i].pFnI2CGetData = NULL; + pxSMBusProfile->xSMBusInstance[i].pFnI2CWriteData = NULL; + pxSMBusProfile->xSMBusInstance[i].pFnI2CAnnounceResult = NULL; + pxSMBusProfile->xSMBusInstance[i].pFnBusError = pFnBusError; + pxSMBusProfile->xSMBusInstance[i].pFnBusWarning = pFnBusWarning; + pxSMBusProfile->xSMBusInstance[i].ucInstanceInUse = SMBUS_TRUE; + pxSMBusProfile->xSMBusInstance[i].ucTriggerFSM = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[i].xARPCapability = xARPCapability; + /* TODO Check correct initial values depending on ARP capability */ + pxSMBusProfile->xSMBusInstance[i].ucARFlag = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[i].ulI2CDevice = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[i].ucFifoEmptyWhileInDoneCount = 0; + + if( SMBUS_ARP_CAPABLE == xARPCapability ) + { + /* AV Flag should be read from NVRAM in the case of Dynamic & Persistent Target Address */ + if( SMBUS_UDID_DYNAMIC_AND_PERSISTENT == ( ucUDID[SMBUS_UDID_DEVICE_CAPABILITIES_BYTE] & SMBUS_UDID_ADDRESS_TYPE_MASK ) ) + { + /* We are deciding the AV Flag from the address used */ + /* If the address is valid ie below 0x80 then set flag */ + /* If the address is invalid ie 0x80 or above then clear flag */ + /* If the address is equal to 0x00 then clear flag */ + if( ( SMBUS_INVALID_ADDRESS_MASK & ucSMBusAddress ) || ( 0 == ucSMBusAddress ) ) + { + /* Invalid address hence ARP needed to set both address and AV Flag */ + pxSMBusProfile->xSMBusInstance[i].ucAVFlag = SMBUS_FALSE; + } + else + { + pxSMBusProfile->xSMBusInstance[i].ucAVFlag = SMBUS_TRUE; + } + } + else + { + pxSMBusProfile->xSMBusInstance[i].ucAVFlag = SMBUS_FALSE; + } + } + else + { + pxSMBusProfile->xSMBusInstance[i].ucAVFlag = SMBUS_TRUE; + } + + pxSMBusProfile->xSMBusInstance[i].ucNewDeviceSlaveAddress = 0; + pxSMBusProfile->xSMBusInstance[i].ucNackSent = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[i].ucSimpleDevice = ucSimpleDevice; + pxSMBusProfile->xSMBusInstance[i].ucThisInstanceNumber = i; + + for( j = 0; j < SMBUS_UDID_LENGTH; j++ ) + { + pxSMBusProfile->xSMBusInstance[i].ucUDID[j] = ucUDID[j]; + } + + /* PEC Supported is taken from the PEC SUpported bit within the UDID */ + pxSMBusProfile->xSMBusInstance[i].ucPECRequired = + ( ucUDID[SMBUS_UDID_DEVICE_CAPABILITIES_BYTE] & SMBUS_UDID_PEC_SUPPORTED_BIT ); + + vSMBusHWWriteTgtControlAddress( pxSMBusProfile, i, ucSMBusAddress ); + + /* Only non-ARP capable instances should enable the bus at this point */ + /* Non-fixed ARP-capable instances should wait on the ARP process completing before enabling the bus */ + if( SMBUS_ARP_CAPABLE != pxSMBusProfile->xSMBusInstance[i].xARPCapability ) + { + vSMBusHWWriteTgtControlEnable( pxSMBusProfile, i, 1 ); + } + ucInstanceToReturn = i; + + /* If an ARP instance hasn't already been added - add it now */ + if( SMBUS_FALSE == pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ucInstanceInUse ) + { + /* Don't add ARP instance if the created device is non-ARP capable */ + if( SMBUS_ARP_NON_ARP_CAPABLE != xARPCapability ) + { + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ucInstanceInUse = SMBUS_TRUE; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ucSMBusAddress = SMBUS_DEVICE_DEFAULT_ARP_ADDRESS; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ucPECRequired = SMBUS_TRUE; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ucThisInstanceNumber = SMBUS_ARP_INSTANCE_ID; + vSMBusHWWriteTgtControlAddress( pxSMBusProfile, + SMBUS_ARP_INSTANCE_ID, SMBUS_DEVICE_DEFAULT_ARP_ADDRESS ); + vSMBusHWWriteTgtControlEnable( pxSMBusProfile, SMBUS_ARP_INSTANCE_ID, 1 ); + } + } + break; + } + } + } + } + + return ucInstanceToReturn; +} + +/****************************************************************************** +* +* @brief Checks that the supplied instance is present and attempts to remove +* it. If the instance being removed is the only instance then the ARP +* instance is also removed +* +*****************************************************************************/ +SMBus_Error_Type xDestroySMBusInstance( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucSMBusInstanceID ) +{ + SMBus_Error_Type xError = SMBUS_ERROR; + uint8_t ucDestroyArpInstance = SMBUS_TRUE; + int i = 0; + int j = 0; + + if( ( NULL != pxSMBusProfile ) && + ( SMBUS_LAST_NON_ARP_SMBUS_INSTANCE >= ucSMBusInstanceID ) ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + xError = SMBUS_ERROR; + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + if( SMBUS_TRUE == pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].ucInstanceInUse ) + { + if( SMBUS_STATE_INITIAL == pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].xState ) + { + vSMBusHWWriteTgtControlEnable( pxSMBusProfile, ucSMBusInstanceID, 0 ); + vSMBusHWWriteTgtControlAddress( pxSMBusProfile, ucSMBusInstanceID, 0 ); + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].ulFirewall1 = SMBUS_FIREWALL1; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].ulFirewall2 = SMBUS_FIREWALL2; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].ulFirewall3 = SMBUS_FIREWALL3; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].ucInstanceInUse = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].ucSMBusAddress = 0; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].pFnGetProtocol = NULL; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].pFnGetData = NULL; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].pFnWriteData = NULL; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].pFnAnnounceResult = NULL; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].pFnArpAddressChange = NULL; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].pFnBusError = NULL; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].pFnBusWarning = NULL; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].ucPECRequired = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].xARPCapability = SMBUS_ARP_CAPABILITY_UNKNOWN; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].ucARFlag = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].ucAVFlag = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].xProtocol = SMBUS_PROTOCOL_NONE; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].ucThisInstanceNumber = SMBUS_INVALID_INSTANCE; + vEventBufferInitialize( &( pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].xEventSourceCircularBuffer ), + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].xCircularBuffer, + SMBUS_MAX_EVENT_ELEMENTS ); + + /* Add a pointer back to the top level */ + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].pxSMBusProfile = pxSMBusProfile; + + /* Reset logs */ + for( j = 0; j < SMBUS_PROTOCOL_NONE; j++ ) + { + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].ulMessagesComplete[j] = 0; + pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID].ulMessagesInitiated[j] = 0; + } + + /* Now check if ARP needs to be removed */ + for( i = 0; i < ( SMBUS_NUMBER_OF_SMBUS_INSTANCES - 1 ); i++ ) + { + /* If any instance is still in use then leave the ARP instance intact */ + if( SMBUS_TRUE == pxSMBusProfile->xSMBusInstance[i].ucInstanceInUse ) + { + if( SMBUS_ARP_NON_ARP_CAPABLE != pxSMBusProfile->xSMBusInstance[i].xARPCapability ) + { + ucDestroyArpInstance = SMBUS_FALSE; + } + } + } + + if( SMBUS_TRUE == ucDestroyArpInstance ) + { + vSMBusHWWriteTgtControlEnable( pxSMBusProfile, SMBUS_ARP_INSTANCE_ID, 0 ); + vSMBusHWWriteTgtControlAddress( pxSMBusProfile, SMBUS_ARP_INSTANCE_ID, 0 ); + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ulFirewall1 = SMBUS_FIREWALL1; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ulFirewall2 = SMBUS_FIREWALL2; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ulFirewall3 = SMBUS_FIREWALL3; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ucInstanceInUse = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ucSMBusAddress = 0; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].pFnGetProtocol = NULL; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].pFnGetData = NULL; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ucPECRequired = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].xARPCapability = SMBUS_ARP_CAPABILITY_UNKNOWN; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ucARFlag = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ucAVFlag = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].xProtocol = SMBUS_PROTOCOL_NONE; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ucThisInstanceNumber = SMBUS_INVALID_INSTANCE; + vEventBufferInitialize( &( pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].xEventSourceCircularBuffer ), + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].xCircularBuffer, + SMBUS_MAX_EVENT_ELEMENTS ); + + /* Add a pointer back to the top level */ + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].pxSMBusProfile = pxSMBusProfile; + + /* Reset logs */ + for( j = 0; j < SMBUS_PROTOCOL_NONE; j++ ) + { + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ulMessagesComplete[j] = 0; + pxSMBusProfile->xSMBusInstance[SMBUS_ARP_INSTANCE_ID].ulMessagesInitiated[j] = 0; + } + } + + xError = SMBUS_SUCCESS; + } + } + } + } + + return ( xError ); +} + +/******************************************************************************* +* +* @brief Will initiate an SMBus message from the supplied intance as a +* controller +* +*****************************************************************************/ +SMBus_Error_Type xSMBusControllerInitiateCommand( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucSMBusInstanceID, + uint8_t ucSMBusDestinationAddress, uint8_t ucCommand, + SMBus_Command_Protocol_Type xProtocol, uint16_t usDataSize, uint8_t* pucData, + uint8_t ucPecRequiredForTransaction, uint32_t* pulTransactionID ) +{ + SMBus_Error_Type xError = SMBUS_ERROR; + + if( ( NULL != pxSMBusProfile ) && + ( SMBUS_LAST_NON_ARP_SMBUS_INSTANCE >= ucSMBusInstanceID ) && + ( SMBUS_PROTOCOL_NONE > xProtocol ) && + ( SMBUS_DATA_SIZE_MAX >= usDataSize ) && + ( NULL != pucData ) && + ( SMBUS_TRUE >= ucPecRequiredForTransaction ) && + ( NULL != pulTransactionID ) ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + xError = SMBUS_ERROR; + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else if( ( SMBUS_SMBCLK_LOW_TIMEOUT_DETECTED == ulSMBusHWReadPHYStatusSMBClkLowTimeout( pxSMBusProfile ) ) || + ( SMBUS_SMBDAT_LOW_TIMEOUT_DETECTED == ulSMBusHWReadPHYStatusSMBDATLowTimeout( pxSMBusProfile ) ) ) + { + xError = SMBUS_ERROR; + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + SMBUS_INSTANCE_TYPE* pxSMBusInstance = &( pxSMBusProfile->xSMBusInstance[ucSMBusInstanceID] ); + + if( SMBUS_INVALID_INSTANCE == pxSMBusProfile->ucInstanceInPlay ) + { + /* Do we need to check if one is in progress for this instance */ + if( SMBUS_STATE_INITIAL == pxSMBusInstance->xState ) + { + *pulTransactionID = pxSMBusProfile->ulTransactionID++; + pxSMBusProfile->ucInstanceInPlay = ucSMBusInstanceID; + + /* Lets copy the data needed and the protocol to use */ + memcpy( pxSMBusInstance->ucSendData, pucData, ( sizeof( uint8_t ) * usDataSize ) ); + pxSMBusInstance->usSendDataSize = usDataSize; + pxSMBusInstance->usSendIndex = 0; + pxSMBusInstance->ucCommand = ucCommand; + pxSMBusInstance->xProtocol = xProtocol; + + if( SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED == xProtocol ) + { + pxSMBusInstance->ucCommand = ucCommand | SMBUS_ARP_UDID_DIRECTED_COMMAND; + } + if( SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED == xProtocol ) + { + pxSMBusInstance->ucCommand = ucCommand & SMBUS_ARP_DIRECTED_COMMAND_ADDRESS_MASK; + } + + pxSMBusInstance->ucSMBusDestinationAddress = ucSMBusDestinationAddress; + pxSMBusInstance->ucPecRequiredForTransaction = ucPecRequiredForTransaction; + + /* First Reset the descriptor FIFO */ + vSMBusHWWriteCtrlDescFifoReset( pxSMBusProfile, 1 ); + vSMBusHWWriteCtrlRxFifoReset( pxSMBusProfile, 1 ); + + /* Create an action to get state machine into the next state; */ + vSMBusGenerateEvent_E_SEND_NEXT_BYTE( pxSMBusInstance ); + + /* Disable interrupts */ + vSMBusHWWriteIRQGIEEnable( pxSMBusProfile, 0 ); + + /* Call SMBusEventQueueHandle */ + vSMBusEventQueueHandle( pxSMBusProfile ); + + /* Re-enable all the Controller interrupts */ + vSMBusHWWriteIRQIER( pxSMBusProfile, 0x0000DFEF ); + + /* Re-enable interrupts */ + vSMBusHWWriteIRQGIEEnable( pxSMBusProfile, 1 ); + + xError = SMBUS_SUCCESS; + } + } + } + } + + return ( xError ); +} + + +/******************************************************************************* +* +* @brief Retrieves SMBus log that is stored as a circular buffer in profile struct +* as ASCII char array +* +*****************************************************************************/ +SMBus_Error_Type xSMBusGetLog( struct SMBUS_PROFILE_TYPE* pxSMBusProfile, char* pcLogBuffer, uint32_t* pulLogSizeBytes ) +{ + SMBus_Error_Type xError = SMBUS_ERROR; + + if( ( NULL != pxSMBusProfile ) && + ( NULL != pcLogBuffer ) && + ( NULL != pulLogSizeBytes ) ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + xError = SMBUS_ERROR; + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + vLogDisplayLog( pxSMBusProfile, pcLogBuffer, pulLogSizeBytes ); + xError = SMBUS_SUCCESS; + } + } + + return ( xError ); +} + + +/******************************************************************************* +* +* @brief Resets SMBus Driver Log +* +*****************************************************************************/ +SMBus_Error_Type xSMBusLogReset( struct SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + SMBus_Error_Type xError = SMBUS_ERROR; + + if( NULL != pxSMBusProfile ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + vLogInitialize( pxSMBusProfile ); + xError = SMBUS_SUCCESS; + } + } + + return ( xError ); +} + +/******************************************************************************* +* +* @brief Enables logging +* +*******************************************************************************/ +void vSMBusLogEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + if( NULL != pxSMBusProfile ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + pxSMBusProfile->xLogLevel = SMBUS_LOG_LEVEL_DEBUG; + } + } +} + +/******************************************************************************* +* +* @brief Disables logging +* +*******************************************************************************/ +void vSMBusLogDisable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + if( NULL != pxSMBusProfile ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + pxSMBusProfile->xLogLevel = SMBUS_LOG_LEVEL_NONE; + } + } +} + +/******************************************************************************* +* +* @brief Resets the statistics log values for the specified instance +* +*******************************************************************************/ +void vSMBusResetStatsLogInstance( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucSMBusInstance ) +{ + int i = 0; + + if( ( NULL != pxSMBusProfile ) && + ( SMBUS_LAST_SMBUS_INSTANCE >= ucSMBusInstance ) ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + if( SMBUS_LAST_SMBUS_INSTANCE >= ucSMBusInstance ) + { + for( i = 0; i < SMBUS_PROTOCOL_NONE; i++ ) + { + pxSMBusProfile->xSMBusInstance[ucSMBusInstance].ulMessagesComplete[i] = 0; + pxSMBusProfile->xSMBusInstance[ucSMBusInstance].ulMessagesInitiated[i] = 0; + } + } + } + } +} + +/******************************************************************************* +* +* @brief Reads the statistics log values for the specified instance +* +*******************************************************************************/ +void vSMBusReadStatsLogInstance( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucSMBusInstance, + SMBUS_LOG_TYPE* pxSMBusMessageLog ) +{ + int i = 0; + + if( ( NULL != pxSMBusProfile ) && + ( SMBUS_LAST_SMBUS_INSTANCE >= ucSMBusInstance ) && + ( NULL != pxSMBusMessageLog ) ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + for( i = 0; i < SMBUS_PROTOCOL_NONE; i++ ) + { + pxSMBusMessageLog->ulMessagesComplete[i] = + pxSMBusProfile->xSMBusInstance[ucSMBusInstance].ulMessagesComplete[i]; + pxSMBusMessageLog->ulMessagesInitiated[i] = + pxSMBusProfile->xSMBusInstance[ucSMBusInstance].ulMessagesInitiated[i]; + } + } + } +} + +/******************************************************************************* +* +* @brief Converts a protocol enum value to a text string for logging +* +*******************************************************************************/ +char* pcProtocolToString( uint8_t ucProtocol ) +{ + char* pcResult = prvpcProtocol_UNKNOWN; + + switch( ucProtocol ) + { + case SMBUS_PROTOCOL_QUICK_COMMAND_HI: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_QUICK_COMMAND_HI; + break; + + case SMBUS_PROTOCOL_QUICK_COMMAND_LO: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_QUICK_COMMAND_LO; + break; + + case SMBUS_PROTOCOL_SEND_BYTE: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_SEND_BYTE; + break; + + case SMBUS_PROTOCOL_RECEIVE_BYTE: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_RECEIVE_BYTE; + break; + + case SMBUS_PROTOCOL_WRITE_BYTE: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_WRITE_BYTE; + break; + + case SMBUS_PROTOCOL_WRITE_WORD: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_WRITE_WORD; + break; + + case SMBUS_PROTOCOL_READ_BYTE: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_READ_BYTE; + break; + + case SMBUS_PROTOCOL_READ_WORD: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_READ_WORD; + break; + + case SMBUS_PROTOCOL_PROCESS_CALL: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_PROCESS_CALL; + break; + + case SMBUS_PROTOCOL_BLOCK_WRITE: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_BLOCK_WRITE; + break; + + case SMBUS_PROTOCOL_BLOCK_READ: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_BLOCK_READ; + break; + + case SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL; + break; + + case SMBUS_PROTOCOL_HOST_NOTIFY: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_HOST_NOTIFY; + break; + + case SMBUS_PROTOCOL_WRITE_32: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_WRITE_32; + break; + + case SMBUS_PROTOCOL_READ_32: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_READ_32; + break; + + case SMBUS_PROTOCOL_WRITE_64: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_WRITE_64; + break; + + case SMBUS_PROTOCOL_READ_64: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_READ_64; + break; + + case SMBUS_PROTOCOL_NONE: + pcResult = prvpcProtocol_SMBUS_PROTOCOL_NONE; + break; + + case SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP: + pcResult = prvpcProtocol_SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP; + break; + + case SMBUS_ARP_PROTOCOL_RESET_DEVICE: + pcResult = prvpcProtocol_SMBUS_ARP_PROTOCOL_RESET_DEVICE; + break; + + case SMBUS_ARP_PROTOCOL_GET_UDID: + pcResult = prvpcProtocol_SMBUS_ARP_PROTOCOL_GET_UDID; + break; + + case SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS: + pcResult = prvpcProtocol_SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS; + break; + + case SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED: + pcResult = prvpcProtocol_SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED; + break; + + case SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED: + pcResult = prvpcProtocol_SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED; + break; + + default: + pcResult = prvpcProtocol_UNKNOWN; + break; + } + + return pcResult; +} + +/******************************************************************************* +* +* @brief Creates an i2c device to act as both a master and a slave +* Checks that a free instance slot is available and if so stores the +* supplied data associated with the instance and enables the hardware +* to send or receive I2C messages for the supplied instance +* +*******************************************************************************/ +uint8_t ucI2CCreateDevice( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucAddr, + I2C_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE pFnGetData, + I2C_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE pFnWriteData, + I2C_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE pFnAnnounceResult, + I2C_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR pFnBusError, + I2C_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING pFnBusWarning ) +{ + uint8_t ucInstanceToReturn = SMBUS_INVALID_INSTANCE; + uint8_t ucOkToContinue = SMBUS_TRUE; + int i = 0; + struct SMBUS_PROFILE_TYPE* pxSMBusProfile = NULL; + + if( ( NULL != pxI2cProfile ) && + ( NULL != pFnGetData ) && + ( NULL != pFnWriteData ) && + ( NULL != pFnAnnounceResult ) ) + { + pxSMBusProfile = ( struct SMBUS_PROFILE_TYPE* )pxI2cProfile; + + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + ucOkToContinue = SMBUS_FALSE; + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + + if( SMBUS_INVALID_ADDRESS_MASK & ucAddr ) + { + ucOkToContinue = SMBUS_FALSE; + } + + if( SMBUS_TRUE == ucOkToContinue ) + { + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + if( SMBUS_TRUE == pxSMBusProfile->xSMBusInstance[i].ucInstanceInUse ) + { + /* Check that the address is not already being used */ + if( pxSMBusProfile->xSMBusInstance[i].ucSMBusAddress == ucAddr ) + { + ucOkToContinue = SMBUS_FALSE; + break; + } + } + } + } + + if( SMBUS_TRUE == ucOkToContinue ) + { + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + if( SMBUS_FALSE == pxSMBusProfile->xSMBusInstance[i].ucInstanceInUse ) + { + pxSMBusProfile->xSMBusInstance[i].ucSMBusAddress = ucAddr; + pxSMBusProfile->xSMBusInstance[i].pFnGetProtocol = NULL; + pxSMBusProfile->xSMBusInstance[i].pFnGetData = NULL; + pxSMBusProfile->xSMBusInstance[i].pFnWriteData = NULL; + pxSMBusProfile->xSMBusInstance[i].pFnAnnounceResult = NULL; + pxSMBusProfile->xSMBusInstance[i].pFnArpAddressChange = NULL; + pxSMBusProfile->xSMBusInstance[i].pFnI2CGetData = pFnGetData; + pxSMBusProfile->xSMBusInstance[i].pFnI2CWriteData = pFnWriteData; + pxSMBusProfile->xSMBusInstance[i].pFnI2CAnnounceResult = pFnAnnounceResult; + pxSMBusProfile->xSMBusInstance[i].pFnBusError = pFnBusError; + pxSMBusProfile->xSMBusInstance[i].pFnBusWarning = pFnBusWarning; + pxSMBusProfile->xSMBusInstance[i].ucInstanceInUse = SMBUS_TRUE; + pxSMBusProfile->xSMBusInstance[i].ucTriggerFSM = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[i].ulI2CDevice = SMBUS_TRUE; + + /* TODO Check correct initial values depending on ARP capability */ + pxSMBusProfile->xSMBusInstance[i].ucNewDeviceSlaveAddress = 0; + pxSMBusProfile->xSMBusInstance[i].ucNackSent = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[i].ucSimpleDevice = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[i].ucThisInstanceNumber = i; + + /* PEC not supported from driver*/ + pxSMBusProfile->xSMBusInstance[i].ucPECRequired = SMBUS_FALSE; + vSMBusHWWriteTgtControlAddress( pxSMBusProfile, i, ucAddr ); + + /* enable the bus */ + vSMBusHWWriteTgtControlEnable( pxSMBusProfile, i, 1 ); + ucInstanceToReturn = i; + break; + } + } + } + } + + return ucInstanceToReturn; +} + +/****************************************************************************** +* +* @brief Destroys a previously created i2c device +* +*****************************************************************************/ +uint8_t ucI2CDestroyDevice( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucDeviceId ) +{ + SMBus_Error_Type xError = SMBUS_ERROR; + int j = 0; + struct SMBUS_PROFILE_TYPE* pxSMBusProfile = NULL; + + + if( ( NULL != pxI2cProfile ) && + ( SMBUS_LAST_NON_ARP_SMBUS_INSTANCE >= ucDeviceId ) ) + { + pxSMBusProfile = ( struct SMBUS_PROFILE_TYPE* )pxI2cProfile; + + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + xError = SMBUS_ERROR; + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + if( SMBUS_TRUE == pxSMBusProfile->xSMBusInstance[ucDeviceId].ucInstanceInUse ) + { + if( SMBUS_STATE_INITIAL == pxSMBusProfile->xSMBusInstance[ucDeviceId].xState ) + { + vSMBusHWWriteTgtControlEnable( pxSMBusProfile, ucDeviceId, 0 ); + vSMBusHWWriteTgtControlAddress( pxSMBusProfile, ucDeviceId, 0 ); + pxSMBusProfile->xSMBusInstance[ucDeviceId].ulFirewall1 = SMBUS_FIREWALL1; + pxSMBusProfile->xSMBusInstance[ucDeviceId].ulFirewall2 = SMBUS_FIREWALL2; + pxSMBusProfile->xSMBusInstance[ucDeviceId].ulFirewall3 = SMBUS_FIREWALL3; + pxSMBusProfile->xSMBusInstance[ucDeviceId].ucInstanceInUse = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[ucDeviceId].ucSMBusAddress = 0; + pxSMBusProfile->xSMBusInstance[ucDeviceId].pFnI2CGetData = NULL; + pxSMBusProfile->xSMBusInstance[ucDeviceId].pFnI2CWriteData = NULL; + pxSMBusProfile->xSMBusInstance[ucDeviceId].pFnI2CAnnounceResult = NULL; + pxSMBusProfile->xSMBusInstance[ucDeviceId].pFnBusError = NULL; + pxSMBusProfile->xSMBusInstance[ucDeviceId].pFnBusWarning = NULL; + pxSMBusProfile->xSMBusInstance[ucDeviceId].ucPECRequired = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[ucDeviceId].xARPCapability = SMBUS_ARP_CAPABILITY_UNKNOWN; + pxSMBusProfile->xSMBusInstance[ucDeviceId].ucARFlag = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[ucDeviceId].ucAVFlag = SMBUS_FALSE; + pxSMBusProfile->xSMBusInstance[ucDeviceId].xProtocol = SMBUS_PROTOCOL_NONE; + pxSMBusProfile->xSMBusInstance[ucDeviceId].ucThisInstanceNumber = SMBUS_INVALID_INSTANCE; + pxSMBusProfile->xSMBusInstance[ucDeviceId].ulI2CDevice = SMBUS_FALSE; + vEventBufferInitialize( &( pxSMBusProfile->xSMBusInstance[ucDeviceId].xEventSourceCircularBuffer ), + pxSMBusProfile->xSMBusInstance[ucDeviceId].xCircularBuffer, + SMBUS_MAX_EVENT_ELEMENTS ); + + /* Add a pointer back to the top level */ + pxSMBusProfile->xSMBusInstance[ucDeviceId].pxSMBusProfile = pxSMBusProfile; + + /* Reset logs */ + for( j = 0; j < SMBUS_PROTOCOL_NONE; j++ ) + { + pxSMBusProfile->xSMBusInstance[ucDeviceId].ulMessagesComplete[j] = 0; + pxSMBusProfile->xSMBusInstance[ucDeviceId].ulMessagesInitiated[j] = 0; + } + + xError = SMBUS_SUCCESS; + } + } + } + } + + return ( xError ); +} + +/****************************************************************************** +* +* @brief Writes data to a remote slave as a master +* +*******************************************************************************/ +uint8_t ucI2CWriteData( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucDeviceId, + uint8_t ucAddr, + uint8_t* pucData, + uint16_t usNumBytes ) +{ + SMBus_Error_Type xError = SMBUS_ERROR; + struct SMBUS_PROFILE_TYPE* pxSMBusProfile = NULL; + + pxSMBusProfile = ( struct SMBUS_PROFILE_TYPE* )pxI2cProfile; + + if( ( NULL != pxSMBusProfile ) && + ( SMBUS_LAST_NON_ARP_SMBUS_INSTANCE >= ucDeviceId ) && + ( SMBUS_DATA_SIZE_MAX >= usNumBytes ) && + ( NULL != pucData ) ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + xError = SMBUS_ERROR; + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + SMBUS_INSTANCE_TYPE* pxSMBusInstance = &( pxSMBusProfile->xSMBusInstance[ucDeviceId] ); + + if( SMBUS_TRUE == pxSMBusInstance->ucInstanceInUse ) + { + if( SMBUS_INVALID_INSTANCE == pxSMBusProfile->ucInstanceInPlay ) + { + /* Do we need to check if one is in progress for this instance */ + if( SMBUS_STATE_INITIAL == pxSMBusInstance->xState ) + { + /* Lets copy the data needed and the protocol to use */ + memcpy( pxSMBusInstance->ucSendData, pucData, ( sizeof( uint8_t ) * usNumBytes ) ); + pxSMBusProfile->ucInstanceInPlay = ucDeviceId; + pxSMBusInstance->usSendDataSize = usNumBytes; + pxSMBusInstance->usSendIndex = 0; + pxSMBusInstance->ulI2CTransaction = SMBUS_TRUE; + pxSMBusInstance->xProtocol = I2C_PROTOCOL_WRITE; + pxSMBusInstance->ucSMBusDestinationAddress = ucAddr; + + /* First Reset the descriptor FIFO */ + vSMBusHWWriteCtrlDescFifoReset( pxSMBusProfile, 1 ); + vSMBusHWWriteCtrlRxFifoReset( pxSMBusProfile, 1 ); + + /* Create an action to get state machine into the next state; */ + vSMBusGenerateEvent_E_SEND_NEXT_BYTE( pxSMBusInstance ); + + /* Disable interrupts */ + vSMBusHWWriteIRQGIEEnable( pxSMBusProfile, 0 ); + + /* Call SMBusEventQueueHandle */ + vSMBusEventQueueHandle( pxSMBusProfile ); + + /* Re-enable all the Controller interrupts */ + vSMBusHWWriteIRQIER( pxSMBusProfile, 0x0000DFEF ); + + /* Re-enable interrupts */ + vSMBusHWWriteIRQGIEEnable( pxSMBusProfile, 1 ); + + xError = SMBUS_SUCCESS; + } + } + } + } + } + + return ( xError ); +} + +/****************************************************************************** +* +* @brief Reads data from a remote slave as a master +* +*******************************************************************************/ +uint8_t ucI2CReadData( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucDeviceId, + uint8_t ucAddr, + uint16_t usNumBytes ) +{ + SMBus_Error_Type xError = SMBUS_ERROR; + struct SMBUS_PROFILE_TYPE* pxSMBusProfile = NULL; + + pxSMBusProfile = ( struct SMBUS_PROFILE_TYPE* )pxI2cProfile; + + if( ( NULL != pxSMBusProfile ) && + ( SMBUS_LAST_NON_ARP_SMBUS_INSTANCE >= ucDeviceId ) && + ( SMBUS_DATA_SIZE_MAX >= usNumBytes ) ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + xError = SMBUS_ERROR; + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + SMBUS_INSTANCE_TYPE* pxSMBusInstance = &( pxSMBusProfile->xSMBusInstance[ucDeviceId] ); + + if( SMBUS_INVALID_INSTANCE == pxSMBusProfile->ucInstanceInPlay ) + { + /* Do we need to check if one is in progress for this instance */ + if( SMBUS_STATE_INITIAL == pxSMBusInstance->xState ) + { + pxSMBusProfile->ucInstanceInPlay = ucDeviceId; + pxSMBusInstance->usExpectedByteCount = usNumBytes; + pxSMBusInstance->xProtocol = I2C_PROTOCOL_READ; + pxSMBusInstance->ucSMBusDestinationAddress = ucAddr; + + /* First Reset the descriptor FIFO */ + vSMBusHWWriteCtrlDescFifoReset( pxSMBusProfile, 1 ); + vSMBusHWWriteCtrlRxFifoReset( pxSMBusProfile, 1 ); + + /* Create an action to get state machine into the next state; */ + vSMBusGenerateEvent_E_SEND_NEXT_BYTE( pxSMBusInstance ); + + /* Disable interrupts */ + vSMBusHWWriteIRQGIEEnable( pxSMBusProfile, 0 ); + + /* Call SMBusEventQueueHandle */ + vSMBusEventQueueHandle( pxSMBusProfile ); + + /* Re-enable all the Controller interrupts */ + vSMBusHWWriteIRQIER( pxSMBusProfile, 0x0000DFEF ); + + /* Re-enable interrupts */ + vSMBusHWWriteIRQGIEEnable( pxSMBusProfile, 1 ); + + xError = SMBUS_SUCCESS; + } + } + } + } + + return ( xError ); +} + +/****************************************************************************** +* +* @brief Writes data to and then reads from remote slave as a master +* +*******************************************************************************/ +uint8_t ucI2CWriteReadData( struct I2C_PROFILE_TYPE* pxI2cProfile, + uint8_t ucDeviceId, + uint8_t ucAddr, + uint8_t* pucWriteData, + uint16_t usNumWriteBytes, + uint16_t usNumReadBytes ) +{ + SMBus_Error_Type xError = SMBUS_ERROR; + struct SMBUS_PROFILE_TYPE* pxSMBusProfile = NULL; + + pxSMBusProfile = ( struct SMBUS_PROFILE_TYPE* )pxI2cProfile; + + if( ( NULL != pxSMBusProfile ) && + ( SMBUS_LAST_NON_ARP_SMBUS_INSTANCE >= ucDeviceId ) && + ( SMBUS_DATA_SIZE_MAX >= usNumWriteBytes ) && + ( NULL != pucWriteData ) && + ( SMBUS_DATA_SIZE_MAX >= usNumReadBytes ) && + ( I2C_READ_DATA_SIZE_MIN <= usNumReadBytes ) ) + { + if( SMBUS_SUCCESS != xSMBusFirewallCheck( pxSMBusProfile ) ) + { + xError = SMBUS_ERROR; + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_ERROR, + SMBUS_ERROR, __LINE__ ); + } + else + { + SMBUS_INSTANCE_TYPE* pxSMBusInstance = &( pxSMBusProfile->xSMBusInstance[ucDeviceId] ); + + if( SMBUS_INVALID_INSTANCE == pxSMBusProfile->ucInstanceInPlay ) + { + /* Do we need to check if one is in progress for this instance */ + if( SMBUS_STATE_INITIAL == pxSMBusInstance->xState ) + { + memcpy( pxSMBusInstance->ucSendData, pucWriteData, ( sizeof( uint8_t ) * usNumWriteBytes ) ); + pxSMBusProfile->ucInstanceInPlay = ucDeviceId; + pxSMBusInstance->usSendDataSize = usNumWriteBytes; + pxSMBusInstance->usSendIndex = 0; + pxSMBusInstance->usExpectedByteCount = usNumReadBytes; + pxSMBusInstance->xProtocol = I2C_PROTOCOL_WRITE_READ; + pxSMBusInstance->ucSMBusDestinationAddress = ucAddr; + + /* First Reset the descriptor FIFO */ + vSMBusHWWriteCtrlDescFifoReset( pxSMBusProfile, 1 ); + vSMBusHWWriteCtrlRxFifoReset( pxSMBusProfile, 1 ); + + /* Create an action to get state machine into the next state; */ + vSMBusGenerateEvent_E_SEND_NEXT_BYTE( pxSMBusInstance ); + + /* Disable interrupts */ + vSMBusHWWriteIRQGIEEnable( pxSMBusProfile, 0 ); + + /* Call SMBusEventQueueHandle */ + vSMBusEventQueueHandle( pxSMBusProfile ); + + /* Re-enable all the Controller interrupts */ + vSMBusHWWriteIRQIER( pxSMBusProfile, 0x0000DFEF ); + + /* Re-enable interrupts */ + vSMBusHWWriteIRQGIEEnable( pxSMBusProfile, 1 ); + + xError = SMBUS_SUCCESS; + } + } + } + } + + return ( xError ); +} diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_event.c b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_event.c new file mode 100755 index 00000000..14a652d0 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_event.c @@ -0,0 +1,761 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the functions for raising events and adding them to the circular event buffer + * for the SMBus driver. + * + * @file smbus_event.c + * + */ + +#include "smbus.h" +#include "smbus_internal.h" +#include "smbus_event_buffer.h" +#include "smbus_event.h" + +char* pEvent_E_TARGET_WRITE_IRQ = "E_TARGET_WRITE_IRQ"; +char* pEvent_E_TARGET_READ_IRQ = "E_TARGET_READ_IRQ"; +char* pEvent_E_TARGET_DATA_IRQ = "E_TARGET_DATA_IRQ"; +char* pEvent_E_TARGET_DONE_IRQ = "E_TARGET_DONE_IRQ"; +char* pEvent_E_TARGET_DESC_IRQ = "E_TARGET_DESC_IRQ"; +char* pEvent_E_TARGET_LOA_ERROR_IRQ = "E_TARGET_LOA_ERROR_IRQ"; +char* pEvent_E_TARGET_PEC_ERROR_IRQ = "E_TARGET_PEC_ERROR_IRQ"; +char* pEvent_E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ + = "E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ"; +char* pEvent_E_TARGET_RX_FIFO_ERROR_ERROR_IRQ + = "E_TARGET_RX_FIFO_ERROR_ERROR_IRQ"; +char* pEvent_E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ + = "E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ"; +char* pEvent_E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ + = "E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ"; +char* pEvent_E_TARGET_DESC_FIFO_ERROR_IRQ + = "E_TARGET_DESC_FIFO_ERROR_IRQ"; +char* pEvent_E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ + = "E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ"; +char* pEvent_E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ + = "E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ"; +char* pEvent_E_TARGET_DESC_ERROR_IRQ + = "E_TARGET_DESC_ERROR_IRQ"; +char* pEvent_E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ + = "E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ"; +char* pEvent_E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ + = "E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ"; +char* pEvent_E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ + = "E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ"; +char* pEvent_E_CONTROLLER_WRITE_IRQ = "E_CONTROLLER_WRITE_IRQ"; +char* pEvent_E_CONTROLLER_READ_IRQ = "E_CONTROLLER_READ_IRQ"; +char* pEvent_E_CONTROLLER_DATA_IRQ = "E_CONTROLLER_DATA_IRQ"; +char* pEvent_E_CONTROLLER_DONE_IRQ = "E_CONTROLLER_DONE_IRQ"; +char* pEvent_E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ + = "E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ"; +char* pEvent_E_CONTROLLER_LOA_ERROR_IRQ = "E_CONTROLLER_LOA_ERROR_IRQ"; +char* pEvent_E_CONTROLLER_NACK_ERROR_IRQ = "E_CONTROLLER_NACK_ERROR_IRQ"; +char* pEvent_E_CONTROLLER_PEC_ERROR_IRQ = "E_CONTROLLER_PEC_ERROR_IRQ"; +char* pEvent_E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ + = "E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ"; +char* pEvent_E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ + = "E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ"; +char* pEvent_E_CONTROLLER_RX_FIFO_ERROR_IRQ + = "E_CONTROLLER_RX_FIFO_ERROR_IRQ"; +char* pEvent_E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ + = "E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ"; +char* pEvent_E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ + = "E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ"; +char* pEvent_E_CONTROLLER_DESC_FIFO_ERROR_IRQ + = "E_CONTROLLER_DESC_FIFO_ERROR_IRQ"; +char* pEvent_E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ + = "E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ"; +char* pEvent_E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ + = "E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ"; +char* pEvent_E_CONTROLLER_DESC_ERROR_IRQ = "E_CONTROLLER_DESC_ERROR_IRQ"; +char* pEvent_E_SEND_NEXT_BYTE = "E_SEND_NEXT_BYTE"; +char* pEvent_E_IS_PEC_REQUIRED = "E_IS_PEC_REQUIRED"; +char* pEvent_E_DESC_FIFO_ALMOST_EMPTY_IRQ = "E_DESC_FIFO_ALMOST_EMPTY_IRQ"; +char* pEvent_UNKNOWN = "UNKNOWN"; + +/******************************************************************************* +* +* @brief If the instance is valid, this function will attempt to write the event +* into the instance's event log +* +*******************************************************************************/ +void vSMBusCreateEvent( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + uint32_t ulWrite_Position = 0; + + if( NULL != pxSMBusInstance ) + { + if( SMBUS_EVENT_BUFFER_FAIL == ucEventBufferTryWrite( &( pxSMBusInstance->xEventSourceCircularBuffer ), ucAnyEvent, &ulWrite_Position ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, ucAnyEvent, __LINE__ ); + } + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_IS_PEC_REQUIRED +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_IS_PEC_REQUIRED( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_IS_PEC_REQUIRED ); + /* Force the State machine to run again */ + pxSMBusInstance->ucTriggerFSM = SMBUS_TRUE; + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_SEND_NEXT_BYTE +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_SEND_NEXT_BYTE( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_SEND_NEXT_BYTE ); + /* Force the State machine to run again */ + pxSMBusInstance->ucTriggerFSM = SMBUS_TRUE; + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_WRITE_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_WRITE_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_WRITE_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_DATA_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_DATA_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_DATA_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DATA_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DATA_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_DATA_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_READ_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_READ_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_READ_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_DONE_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_DONE_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_DONE_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DONE_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DONE_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_DONE_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_LOA_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_LOA_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_LOA_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_PEC_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_PEC_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_PEC_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_RX_FIFO_ERROR_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_RX_FIFO_ERROR_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_RX_FIFO_ERROR_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_DESC_FIFO_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_DESC_FIFO_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_DESC_FIFO_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_DESC_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_DESC_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_DESC_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_LOA_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_LOA_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_LOA_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_NACK_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_NACK_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_NACK_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_PEC_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_PEC_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_PEC_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_RX_FIFO_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_RX_FIFO_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_RX_FIFO_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DESC_FIFO_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DESC_FIFO_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_DESC_FIFO_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DESC_ERROR_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DESC_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_DESC_ERROR_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_DESC_FIFO_ALMOST_EMPTY_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_DESC_FIFO_ALMOST_EMPTY_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_DESC_FIFO_ALMOST_EMPTY_IRQ ); + } +} + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusCreateEvent( pxSMBusInstance, E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ ); + } +} + +/******************************************************************************* +* +* @brief Converts an event enum value to a text string for logging +* +*******************************************************************************/ +/* Event helper functions */ +char* pcEventToString( uint8_t ucEvent ) +{ + char* pResult = NULL; + + switch( ucEvent ) + { + case E_TARGET_WRITE_IRQ: + pResult = pEvent_E_TARGET_WRITE_IRQ; + break; + + case E_TARGET_READ_IRQ: + pResult = pEvent_E_TARGET_READ_IRQ; + break; + + case E_TARGET_DATA_IRQ: + pResult = pEvent_E_TARGET_DATA_IRQ; + break; + + case E_TARGET_DONE_IRQ: + pResult = pEvent_E_TARGET_DONE_IRQ; + break; + + case E_TARGET_DESC_IRQ: + pResult = pEvent_E_TARGET_DESC_IRQ; + break; + + case E_TARGET_LOA_ERROR_IRQ: + pResult = pEvent_E_TARGET_LOA_ERROR_IRQ; + break; + + case E_TARGET_PEC_ERROR_IRQ: + pResult = pEvent_E_TARGET_PEC_ERROR_IRQ; + break; + + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + pResult = pEvent_E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ; + break; + + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + pResult = pEvent_E_TARGET_RX_FIFO_ERROR_ERROR_IRQ; + break; + + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + pResult = pEvent_E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ; + break; + + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + pResult = pEvent_E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ; + break; + + case E_TARGET_DESC_FIFO_ERROR_IRQ: + pResult = pEvent_E_TARGET_DESC_FIFO_ERROR_IRQ; + break; + + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + pResult = pEvent_E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ; + break; + + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + pResult = pEvent_E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ; + break; + + case E_TARGET_DESC_ERROR_IRQ: + pResult = pEvent_E_TARGET_DESC_ERROR_IRQ; + break; + + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + pResult = pEvent_E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ; + break; + + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + pResult = pEvent_E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ; + break; + + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + pResult = pEvent_E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ; + break; + + case E_CONTROLLER_WRITE_IRQ: + pResult = pEvent_E_CONTROLLER_WRITE_IRQ; + break; + + case E_CONTROLLER_READ_IRQ: + pResult = pEvent_E_CONTROLLER_READ_IRQ; + break; + + case E_CONTROLLER_DATA_IRQ: + pResult = pEvent_E_CONTROLLER_DATA_IRQ; + break; + + case E_CONTROLLER_DONE_IRQ: + pResult = pEvent_E_CONTROLLER_DONE_IRQ; + break; + + case E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ: + pResult = pEvent_E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ; + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + pResult = pEvent_E_CONTROLLER_LOA_ERROR_IRQ; + break; + + case E_CONTROLLER_NACK_ERROR_IRQ: + pResult = pEvent_E_CONTROLLER_NACK_ERROR_IRQ; + break; + + case E_CONTROLLER_PEC_ERROR_IRQ: + pResult = pEvent_E_CONTROLLER_PEC_ERROR_IRQ; + break; + + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + pResult = pEvent_E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ; + break; + + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + pResult = pEvent_E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ; + break; + + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + pResult = pEvent_E_CONTROLLER_RX_FIFO_ERROR_IRQ; + break; + + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + pResult = pEvent_E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ; + break; + + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + pResult = pEvent_E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ; + break; + + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + pResult = pEvent_E_CONTROLLER_DESC_FIFO_ERROR_IRQ; + break; + + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + pResult = pEvent_E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ; + break; + + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + pResult = pEvent_E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ; + break; + + case E_CONTROLLER_DESC_ERROR_IRQ: + pResult = pEvent_E_CONTROLLER_DESC_ERROR_IRQ; + break; + + case E_SEND_NEXT_BYTE: + pResult = pEvent_E_SEND_NEXT_BYTE; + break; + + case E_IS_PEC_REQUIRED: + pResult = pEvent_E_IS_PEC_REQUIRED; + break; + + case E_DESC_FIFO_ALMOST_EMPTY_IRQ: + pResult = pEvent_E_DESC_FIFO_ALMOST_EMPTY_IRQ; + break; + + default: + pResult = pEvent_UNKNOWN; + break; + } + + return pResult; +} diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_event.h b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_event.h new file mode 100755 index 00000000..52369904 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_event.h @@ -0,0 +1,584 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the defintions of the SMBus state machine events and + * function declarations for the functions which generate those events + * + * @file smbus_event.h + * + */ + +#ifndef _SMBUS_EVENT_H_ +#define _SMBUS_EVENT_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "smbus.h" +#include "smbus_event_buffer.h" + +#define E_TARGET_WRITE_IRQ ( 0x01 ) +#define E_TARGET_READ_IRQ ( 0x02 ) +#define E_TARGET_DATA_IRQ ( 0x03 ) +#define E_TARGET_DONE_IRQ ( 0x04 ) +#define E_TARGET_DESC_IRQ ( 0x05 ) +#define E_TARGET_LOA_ERROR_IRQ ( 0x06 ) +#define E_TARGET_PEC_ERROR_IRQ ( 0x07 ) +#define E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ ( 0x08 ) +#define E_TARGET_RX_FIFO_ERROR_ERROR_IRQ ( 0x09 ) +#define E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ ( 0x0A ) +#define E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ ( 0x0B ) +#define E_TARGET_DESC_FIFO_ERROR_IRQ ( 0x0C ) +#define E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ ( 0x0D ) +#define E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ ( 0x0E ) +#define E_TARGET_DESC_ERROR_IRQ ( 0x0F ) +#define E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ ( 0x10 ) +#define E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ ( 0x11 ) +#define E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ ( 0x12 ) +#define E_CONTROLLER_WRITE_IRQ ( 0x13 ) +#define E_CONTROLLER_READ_IRQ ( 0x14 ) +#define E_CONTROLLER_DATA_IRQ ( 0x15 ) +#define E_CONTROLLER_DONE_IRQ ( 0x16 ) +#define E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ ( 0x17 ) +#define E_CONTROLLER_LOA_ERROR_IRQ ( 0x18 ) +#define E_CONTROLLER_NACK_ERROR_IRQ ( 0x19 ) +#define E_CONTROLLER_PEC_ERROR_IRQ ( 0x1A ) +#define E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ ( 0x1B ) +#define E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ ( 0x1C ) +#define E_CONTROLLER_RX_FIFO_ERROR_IRQ ( 0x1D ) +#define E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ ( 0x1E ) +#define E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ ( 0x1F ) +#define E_CONTROLLER_DESC_FIFO_ERROR_IRQ ( 0x20 ) +#define E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ ( 0x21 ) +#define E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ ( 0x22 ) +#define E_CONTROLLER_DESC_ERROR_IRQ ( 0x23 ) +#define E_SEND_NEXT_BYTE ( 0x24 ) +#define E_IS_PEC_REQUIRED ( 0x25 ) +#define E_DESC_FIFO_ALMOST_EMPTY_IRQ ( 0x26 ) + +/******************************************************************************* +* +* @brief If the instance is valid, this function will attempt to write the event +* into the instance's event log +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* @param ucAnyEvent is any SMBus state machine event +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusCreateEvent( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_IS_PEC_REQUIRED +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_IS_PEC_REQUIRED( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_SEND_NEXT_BYTE +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_SEND_NEXT_BYTE( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_WRITE_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_WRITE_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_DATA_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_DATA_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_READ_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_READ_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_DONE_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_DONE_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_LOA_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_LOA_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_PEC_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_PEC_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_RX_FIFO_ERROR_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_RX_FIFO_ERROR_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_DESC_FIFO_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_DESC_FIFO_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_DESC_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_DESC_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DONE_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DONE_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_LOA_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_LOA_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_NACK_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_NACK_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_PEC_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_PEC_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_RX_FIFO_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_RX_FIFO_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DESC_FIFO_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DESC_FIFO_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DESC_ERROR_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DESC_ERROR_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DATA_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DATA_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_DESC_FIFO_ALMOST_EMPTY_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_DESC_FIFO_ALMOST_EMPTY_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief If the instance is valid, this function will call vSMBusCreateEvent +* with event E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ +* +* @param pxSMBusInstance is a pointer to the SMBus instance data +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusGenerateEvent_E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/******************************************************************************* +* +* @brief Converts an event enum value to a text string for logging +* +* @param ucEvent is any state machine event enum value +* +* @return A text string of the event +* +* @note None. +* +*******************************************************************************/ +char* pcEventToString( uint8_t ucEvent ); + +#ifdef __cplusplus +} +#endif + +#endif /* _SMBUS_EVENT_H_ */ diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_event_buffer.c b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_event_buffer.c new file mode 100755 index 00000000..1848deb1 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_event_buffer.c @@ -0,0 +1,135 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the function definitions for the event buffer intialize, read and write functions + * + * @file smbus_event_buffer.c + * + */ + +#include "smbus_internal.h" +#include "smbus_event_buffer.h" + +/********************** Static function declarations ***************************/ + +/****************************************************************************** +* +* @brief This function increments the event buffer index until it hits the +* max value at which point it sets it to 0. +* +* @param pxContext is a pointer to the event buffer structure. +* @param ulAnyIndex is the current index position +* +* @return uint32_t new index position +* +* @note None. +* +*****************************************************************************/ +static uint32_t ulEventBufferInc( SMBUS_EVENT_BUFFER_TYPE* pxContext, uint32_t ulAnyIndex ); + +/*******************************************************************************/ + +/****************************************************************************** +* +* @brief Walks through all elements of the event buffer. It sets all the elements to unoccupied +* and sets the event value to 0. +* +*****************************************************************************/ +void vEventBufferInitialize( SMBUS_EVENT_BUFFER_TYPE* pxContext, SMBUS_EVENT_BUFFER_ELEMENT_TYPE* pxEventBuffer, uint32_t ulMaxElements ) +{ + uint32_t i = 0; + + if( ( NULL != pxContext ) && + ( NULL != pxEventBuffer ) ) + { + pxContext->ulMaxElements = ulMaxElements; + pxContext->pxEventBuffer = pxEventBuffer; + + for( i = 0; i < ( pxContext->ulMaxElements ); i++ ) + { + pxContext->pxEventBuffer[i].ucIsOccupied = SMBUS_FALSE; + pxContext->pxEventBuffer[i].ucOctet = 0x00; + } + + pxContext->ulWrite = 0; + pxContext->ulRead = 0; + } +} + +/****************************************************************************** +* +* @brief This function increments the event buffer index until it hits the +* max value at which point it sets it to 0. +* +*****************************************************************************/ +static uint32_t ulEventBufferInc( SMBUS_EVENT_BUFFER_TYPE* pxContext, uint32_t ulAnyIndex ) +{ + uint32_t ulResult = ulAnyIndex; + + if( NULL != pxContext ) + { + ulResult++; + + if( ( pxContext->ulMaxElements ) <= ulResult ) + { + ulResult = 0; + } + } + return ( ulResult ); +} + +/****************************************************************************** +* +* @brief If the write location is not occupied the event is written to that +* location. The location is marked as occupied and the write location +* is incremented +* +*****************************************************************************/ +uint8_t ucEventBufferTryWrite( SMBUS_EVENT_BUFFER_TYPE* pxContext, uint8_t ucAnyCharacter, uint32_t* pulWrite_Position ) +{ + uint8_t ucResult = SMBUS_EVENT_BUFFER_FAIL; + + if( ( NULL != pxContext ) && + ( NULL != pulWrite_Position ) ) + { + if( SMBUS_FALSE == pxContext->pxEventBuffer[pxContext->ulWrite].ucIsOccupied ) + { + *pulWrite_Position = pxContext->ulWrite; + pxContext->pxEventBuffer[pxContext->ulWrite].ucOctet = ucAnyCharacter; + pxContext->pxEventBuffer[pxContext->ulWrite].ucIsOccupied = SMBUS_TRUE; + pxContext->ulWrite = ulEventBufferInc( pxContext, pxContext->ulWrite ); + ucResult = SMBUS_EVENT_BUFFER_SUCCESS; + } + } + return ( ucResult ); +} + +/****************************************************************************** +* +* @brief If the read location is occupied the event at the location is read +* The read location is then marked as empty and the read location incremented +* +*****************************************************************************/ +uint8_t ucEventBufferTryRead( SMBUS_EVENT_BUFFER_TYPE* pxContext, uint8_t* pucAnyCharacter, uint32_t* pulRead_Position ) +{ + uint8_t ucResult = SMBUS_FALSE; + + if( ( NULL != pxContext ) && + ( NULL != pucAnyCharacter ) && + ( NULL != pulRead_Position ) ) + { + *pucAnyCharacter = 0xCC; + + if( SMBUS_TRUE == pxContext->pxEventBuffer[pxContext->ulRead].ucIsOccupied ) + { + *pulRead_Position = pxContext->ulRead; + *pucAnyCharacter = pxContext->pxEventBuffer[pxContext->ulRead].ucOctet; + pxContext->pxEventBuffer[pxContext->ulRead].ucIsOccupied = SMBUS_FALSE; + pxContext->ulRead = ulEventBufferInc( pxContext, pxContext->ulRead ); + ucResult = SMBUS_TRUE; + } + } + + return ( ucResult ); +} diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_event_buffer.h b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_event_buffer.h new file mode 100755 index 00000000..bcb37710 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_event_buffer.h @@ -0,0 +1,79 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the structs and function declarations for the event buffer functions + * + * @file smbus_event_buffer.h + * + */ + +#ifndef _SMBUS_EVENT_BUFFER_H_ +#define _SMBUS_EVENT_BUFFER_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "smbus.h" + +#define SMBUS_EVENT_BUFFER_SUCCESS ( 0 ) +#define SMBUS_EVENT_BUFFER_FAIL ( 1 ) + +/****************************************************************************** +* +* @brief Walks through all elements of the event buffer. It sets all the elements to unoccupied +* and sets the event value to 0. +* +* @param pxContext is a pointer to the event buffer structure. +* @param pxEventBuffer is the pointer to the event buffer element +* @param ulMaxElements is the number of elements in the event log. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vEventBufferInitialize( SMBUS_EVENT_BUFFER_TYPE* pxContext, SMBUS_EVENT_BUFFER_ELEMENT_TYPE* pxEventBuffer, uint32_t ulMaxElements ); + +/****************************************************************************** +* +* @brief If the write location is not occupied the event is written to that +* location. The location is marked as occupied and the write location +* is incremented +* +* @param pxContext is a pointer to the event buffer structure. +* @param ucAnyCharacter is the event to write to the event buffer +* @param pulWrite_Position is a pointer to the location the event was written to +* +* @return SMBUS_FALSE - if write fails +* SMBUS_TRUE - if write succeeds +* +* @note None. +* +*****************************************************************************/ +uint8_t ucEventBufferTryWrite( SMBUS_EVENT_BUFFER_TYPE* pxContext, uint8_t ucAnyCharacter, uint32_t* pulWrite_Position ); + +/****************************************************************************** +* +* @brief If the read location is occupied the event at the location is read +* The read location is then marked as empty and the read location incremented +* +* @param pxContext is a pointer to the event buffer structure. +* @param pucAnyCharacter is a pointer to the event read +* @param pulRead_Position is a pointer to the location the event was read from +* +* @return SMBUS_FALSE - if read fails +* SMBUS_TRUE - if write succeeds +* +* @note None. +* +*****************************************************************************/ +uint8_t ucEventBufferTryRead( SMBUS_EVENT_BUFFER_TYPE* pxContext, uint8_t* pucAnyCharacter, uint32_t* pulRead_Position ); + +#ifdef __cplusplus +} +#endif + +#endif /* _SMBUS_EVENT_BUFFER_H_ */ diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_hardware.h b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_hardware.h new file mode 100755 index 00000000..a5c4f37a --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_hardware.h @@ -0,0 +1,447 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the SMBus IP register offsets and bit mask defintions + * for the SMBus driver. + * + * This file is autogenerated from the coreinfo.yaml file + * Do not edit this file + * + * @file smbus_hardware.h + * + */ + +#ifndef _SMBUS_HARDWARE_H_ +#define _SMBUS_HARDWARE_H_ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define SMBUS_REG_IP_VERSION 0x0000 +#define SMBUS_REG_IP_REVISION 0x0004 +#define SMBUS_REG_IP_MAGIC_NUM 0x0008 +#define SMBUS_REG_IP_BUILD_CONFIG_0 0x000C +#define SMBUS_REG_IP_BUILD_CONFIG_1 0x0010 +#define SMBUS_REG_IRQ_GIE 0x0020 +#define SMBUS_REG_IRQ_IER 0x0024 +#define SMBUS_REG_IRQ_ISR 0x0028 +#define SMBUS_REG_ERR_IRQ_IER 0x002C +#define SMBUS_REG_ERR_IRQ_ISR 0x0030 +#define SMBUS_REG_IRQ_ISR_FORCE 0x0034 +#define SMBUS_REG_ERR_IRQ_ISR_FORCE 0x0038 +#define SMBUS_REG_PHY_STATUS 0x0200 +#define SMBUS_REG_PHY_FILTER_CONTROL 0x0204 +#define SMBUS_REG_PHY_BUS_FREE_TIME 0x0208 +#define SMBUS_REG_PHY_IDLE_THRESHOLD 0x020C +#define SMBUS_REG_PHY_TIMEOUT_PRESCALER 0x0210 +#define SMBUS_REG_PHY_TIMEOUT_MIN 0x0214 +#define SMBUS_REG_PHY_TIMEOUT_MAX 0x0218 +#define SMBUS_REG_PHY_RESET_CONTROL 0x021C +#define SMBUS_REG_PHY_TGT_DATA_SETUP 0x0400 +#define SMBUS_REG_PHY_TGT_TEXT_PRESCALER 0x0404 +#define SMBUS_REG_PHY_TGT_TEXT_TIMEOUT 0x0408 +#define SMBUS_REG_PHY_TGT_TEXT_MAX 0x040C +#define SMBUS_REG_PHY_TGT_DBG_STATE 0x0410 +#define SMBUS_REG_PHY_TGT_DATA_HOLD 0x0414 +#define SMBUS_REG_TGT_STATUS 0x0600 +#define SMBUS_REG_TGT_DESC_FIFO 0x0604 +#define SMBUS_REG_TGT_DESC_STATUS 0x0608 +#define SMBUS_REG_TGT_RX_FIFO 0x060C +#define SMBUS_REG_TGT_RX_FIFO_STATUS 0x0610 +#define SMBUS_REG_TGT_RX_FIFO_FILL_THRESHOLD 0x0614 +#define SMBUS_REG_TGT_DBG 0x0618 +#define SMBUS_REG_TGT_CONTROL_0 0x0620 +#define SMBUS_REG_TGT_CONTROL_1 0x0624 +#define SMBUS_REG_TGT_CONTROL_2 0x0628 +#define SMBUS_REG_TGT_CONTROL_3 0x062C +#define SMBUS_REG_TGT_CONTROL_4 0x0630 +#define SMBUS_REG_TGT_CONTROL_5 0x0634 +#define SMBUS_REG_TGT_CONTROL_6 0x0638 +#define SMBUS_REG_TGT_CONTROL_7 0x063C +#define SMBUS_REG_PHY_CTLR_DATA_HOLD 0x0800 +#define SMBUS_REG_PHY_CTLR_START_HOLD 0x0804 +#define SMBUS_REG_PHY_CTLR_START_SETUP 0x0808 +#define SMBUS_REG_PHY_CTLR_STOP_SETUP 0x080C +#define SMBUS_REG_PHY_CTLR_CLK_TLOW 0x0810 +#define SMBUS_REG_PHY_CTLR_CLK_THIGH 0x0814 +#define SMBUS_REG_PHY_CTLR_TEXT_PRESCALER 0x0818 +#define SMBUS_REG_PHY_CTLR_TEXT_TIMEOUT 0x081C +#define SMBUS_REG_PHY_CTLR_TEXT_MAX 0x0820 +#define SMBUS_REG_PHY_CTLR_CEXT_PRESCALER 0x0824 +#define SMBUS_REG_PHY_CTLR_CEXT_TIMEOUT 0x0828 +#define SMBUS_REG_PHY_CTLR_CEXT_MAX 0x082C +#define SMBUS_REG_PHY_CTLR_DBG_STATE 0x0830 +#define SMBUS_REG_CTLR_CONTROL 0x0A00 +#define SMBUS_REG_CTLR_STATUS 0x0A04 +#define SMBUS_REG_CTLR_DESC_FIFO 0x0A08 +#define SMBUS_REG_CTLR_DESC_STATUS 0x0A0C +#define SMBUS_REG_CTLR_RX_FIFO 0x0A10 +#define SMBUS_REG_CTLR_RX_FIFO_STATUS 0x0A14 +#define SMBUS_REG_CTLR_RX_FIFO_FILL_THRESHOLD 0x0A18 +#define SMBUS_REG_CTLR_DBG 0x0A1C + + + +#define SMBUS_IP_VERSION_MAJOR_VERSION_FIELD_POSITION 16 +#define SMBUS_IP_VERSION_MINOR_VERSION_FIELD_POSITION 0 +#define SMBUS_IP_REVISION_CORE_REVISION_FIELD_POSITION 0 +#define SMBUS_IP_MAGIC_NUM_MAGIC_NUMBER_FIELD_POSITION 0 +#define SMBUS_IP_BUILD_CONFIG_0_FREQ_HZ_AXI_ACLK_FIELD_POSITION 0 +#define SMBUS_IP_BUILD_CONFIG_1_NUM_TARGET_DEVICES_FIELD_POSITION 4 +#define SMBUS_IP_BUILD_CONFIG_1_SMBUS_DEV_CLASS_FIELD_POSITION 0 +#define SMBUS_IRQ_GIE_ENABLE_FIELD_POSITION 0 +#define SMBUS_IRQ_IER_CTLR_DESC_FIFO_ALMOST_EMPTY_FIELD_POSITION 15 +#define SMBUS_IRQ_IER_CTLR_RX_FIFO_FILL_THRESHOLD_FIELD_POSITION 14 +#define SMBUS_IRQ_IER_CTLR_DESC_FIFO_EMPTY_FIELD_POSITION 13 +#define SMBUS_IRQ_IER_CTLR_DONE_FIELD_POSITION 12 +#define SMBUS_IRQ_IER_CTLR_PEC_ERROR_FIELD_POSITION 11 +#define SMBUS_IRQ_IER_CTLR_NACK_ERROR_FIELD_POSITION 10 +#define SMBUS_IRQ_IER_CTLR_LOA_FIELD_POSITION 9 +#define SMBUS_IRQ_IER_TGT_DESC_FIFO_ALMOST_EMPTY_FIELD_POSITION 8 +#define SMBUS_IRQ_IER_TGT_WRITE_FIELD_POSITION 7 +#define SMBUS_IRQ_IER_TGT_READ_FIELD_POSITION 6 +#define SMBUS_IRQ_IER_TGT_RX_FIFO_FILL_THRESHOLD_FIELD_POSITION 5 +#define SMBUS_IRQ_IER_TGT_DESC_FIFO_EMPTY_FIELD_POSITION 4 +#define SMBUS_IRQ_IER_TGT_DONE_FIELD_POSITION 3 +#define SMBUS_IRQ_IER_TGT_PEC_ERROR_FIELD_POSITION 2 +#define SMBUS_IRQ_IER_TGT_LOA_FIELD_POSITION 1 +#define SMBUS_IRQ_IER_ERROR_IRQ_FIELD_POSITION 0 +#define SMBUS_IRQ_ISR_CTLR_DESC_FIFO_ALMOST_EMPTY_FIELD_POSITION 15 +#define SMBUS_IRQ_ISR_CTLR_RX_FIFO_FILL_THRESHOLD_FIELD_POSITION 14 +#define SMBUS_IRQ_ISR_CTLR_DESC_FIFO_EMPTY_FIELD_POSITION 13 +#define SMBUS_IRQ_ISR_CTLR_DONE_FIELD_POSITION 12 +#define SMBUS_IRQ_ISR_CTLR_PEC_ERROR_FIELD_POSITION 11 +#define SMBUS_IRQ_ISR_CTLR_NACK_ERROR_FIELD_POSITION 10 +#define SMBUS_IRQ_ISR_CTLR_LOA_FIELD_POSITION 9 +#define SMBUS_IRQ_ISR_TGT_DESC_FIFO_ALMOST_EMPTY_FIELD_POSITION 8 +#define SMBUS_IRQ_ISR_TGT_WRITE_FIELD_POSITION 7 +#define SMBUS_IRQ_ISR_TGT_READ_FIELD_POSITION 6 +#define SMBUS_IRQ_ISR_TGT_RX_FIFO_FILL_THRESHOLD_FIELD_POSITION 5 +#define SMBUS_IRQ_ISR_TGT_DESC_FIFO_EMPTY_FIELD_POSITION 4 +#define SMBUS_IRQ_ISR_TGT_DONE_FIELD_POSITION 3 +#define SMBUS_IRQ_ISR_TGT_PEC_ERROR_FIELD_POSITION 2 +#define SMBUS_IRQ_ISR_TGT_LOA_FIELD_POSITION 1 +#define SMBUS_IRQ_ISR_ERROR_IRQ_FIELD_POSITION 0 +#define SMBUS_ERR_IRQ_IER_PHY_CTLR_CEXT_TIMEOUT_FIELD_POSITION 19 +#define SMBUS_ERR_IRQ_IER_PHY_CTLR_TEXT_TIMEOUT_FIELD_POSITION 18 +#define SMBUS_ERR_IRQ_IER_CTLR_RX_FIFO_ERROR_FIELD_POSITION 17 +#define SMBUS_ERR_IRQ_IER_CTLR_RX_FIFO_OVERFLOW_FIELD_POSITION 16 +#define SMBUS_ERR_IRQ_IER_CTLR_RX_FIFO_UNDERFLOW_FIELD_POSITION 15 +#define SMBUS_ERR_IRQ_IER_CTLR_DESC_FIFO_ERROR_FIELD_POSITION 14 +#define SMBUS_ERR_IRQ_IER_CTLR_DESC_FIFO_OVERFLOW_FIELD_POSITION 13 +#define SMBUS_ERR_IRQ_IER_CTLR_DESC_FIFO_UNDERFLOW_FIELD_POSITION 12 +#define SMBUS_ERR_IRQ_IER_CTLR_DESC_ERROR_FIELD_POSITION 11 +#define SMBUS_ERR_IRQ_IER_PHY_TGT_TEXT_TIMEOUT_FIELD_POSITION 10 +#define SMBUS_ERR_IRQ_IER_TGT_RX_FIFO_ERROR_FIELD_POSITION 9 +#define SMBUS_ERR_IRQ_IER_TGT_RX_FIFO_OVERFLOW_FIELD_POSITION 8 +#define SMBUS_ERR_IRQ_IER_TGT_RX_FIFO_UNDERFLOW_FIELD_POSITION 7 +#define SMBUS_ERR_IRQ_IER_TGT_DESC_FIFO_ERROR_FIELD_POSITION 6 +#define SMBUS_ERR_IRQ_IER_TGT_DESC_FIFO_OVERFLOW_FIELD_POSITION 5 +#define SMBUS_ERR_IRQ_IER_TGT_DESC_FIFO_UNDERFLOW_FIELD_POSITION 4 +#define SMBUS_ERR_IRQ_IER_TGT_DESC_ERROR_FIELD_POSITION 3 +#define SMBUS_ERR_IRQ_IER_PHY_UNEXPTD_BUS_IDLE_FIELD_POSITION 2 +#define SMBUS_ERR_IRQ_IER_PHY_SMBDAT_LOW_TIMEOUT_FIELD_POSITION 1 +#define SMBUS_ERR_IRQ_IER_PHY_SMBCLK_LOW_TIMEOUT_FIELD_POSITION 0 +#define SMBUS_ERR_IRQ_ISR_PHY_CTLR_CEXT_TIMEOUT_FIELD_POSITION 19 +#define SMBUS_ERR_IRQ_ISR_PHY_CTLR_TEXT_TIMEOUT_FIELD_POSITION 18 +#define SMBUS_ERR_IRQ_ISR_CTLR_RX_FIFO_ERROR_FIELD_POSITION 17 +#define SMBUS_ERR_IRQ_ISR_CTLR_RX_FIFO_OVERFLOW_FIELD_POSITION 16 +#define SMBUS_ERR_IRQ_ISR_CTLR_RX_FIFO_UNDERFLOW_FIELD_POSITION 15 +#define SMBUS_ERR_IRQ_ISR_CTLR_DESC_FIFO_ERROR_FIELD_POSITION 14 +#define SMBUS_ERR_IRQ_ISR_CTLR_DESC_FIFO_OVERFLOW_FIELD_POSITION 13 +#define SMBUS_ERR_IRQ_ISR_CTLR_DESC_FIFO_UNDERFLOW_FIELD_POSITION 12 +#define SMBUS_ERR_IRQ_ISR_CTLR_DESC_ERROR_FIELD_POSITION 11 +#define SMBUS_ERR_IRQ_ISR_PHY_TGT_TEXT_TIMEOUT_FIELD_POSITION 10 +#define SMBUS_ERR_IRQ_ISR_TGT_RX_FIFO_ERROR_FIELD_POSITION 9 +#define SMBUS_ERR_IRQ_ISR_TGT_RX_FIFO_OVERFLOW_FIELD_POSITION 8 +#define SMBUS_ERR_IRQ_ISR_TGT_RX_FIFO_UNDERFLOW_FIELD_POSITION 7 +#define SMBUS_ERR_IRQ_ISR_TGT_DESC_FIFO_ERROR_FIELD_POSITION 6 +#define SMBUS_ERR_IRQ_ISR_TGT_DESC_FIFO_OVERFLOW_FIELD_POSITION 5 +#define SMBUS_ERR_IRQ_ISR_TGT_DESC_FIFO_UNDERFLOW_FIELD_POSITION 4 +#define SMBUS_ERR_IRQ_ISR_TGT_DESC_ERROR_FIELD_POSITION 3 +#define SMBUS_ERR_IRQ_ISR_PHY_UNEXPTD_BUS_IDLE_FIELD_POSITION 2 +#define SMBUS_ERR_IRQ_ISR_PHY_SMBDAT_LOW_TIMEOUT_FIELD_POSITION 1 +#define SMBUS_ERR_IRQ_ISR_PHY_SMBCLK_LOW_TIMEOUT_FIELD_POSITION 0 +#define SMBUS_IRQ_ISR_FORCE_IRQ_ISR_FORCE_FIELD_POSITION 0 +#define SMBUS_ERR_IRQ_ISR_FORCE_ERR_IRQ_ISR_FORCE_FIELD_POSITION 0 +#define SMBUS_PHY_STATUS_SMBDAT_LOW_TIMEOUT_FIELD_POSITION 2 +#define SMBUS_PHY_STATUS_SMBCLK_LOW_TIMEOUT_FIELD_POSITION 1 +#define SMBUS_PHY_STATUS_BUS_IDLE_FIELD_POSITION 0 +#define SMBUS_PHY_FILTER_CONTROL_ENABLE_FIELD_POSITION 31 +#define SMBUS_PHY_FILTER_CONTROL_DURATION_FIELD_POSITION 0 +#define SMBUS_PHY_BUS_FREE_TIME_BUS_FREE_TIME_FIELD_POSITION 0 +#define SMBUS_PHY_IDLE_THRESHOLD_IDLE_THRESHOLD_FIELD_POSITION 0 +#define SMBUS_PHY_TIMEOUT_PRESCALER_TIMEOUT_PRESCALER_FIELD_POSITION 0 +#define SMBUS_PHY_TIMEOUT_MIN_TIMEOUT_ENABLE_FIELD_POSITION 31 +#define SMBUS_PHY_TIMEOUT_MIN_TIMEOUT_MIN_FIELD_POSITION 0 +#define SMBUS_PHY_TIMEOUT_MAX_TIMEOUT_MAX_FIELD_POSITION 0 +#define SMBUS_PHY_RESET_CONTROL_SMBCLK_FORCE_TIMEOUT_FIELD_POSITION 31 +#define SMBUS_PHY_RESET_CONTROL_SMBCLK_FORCE_LOW_FIELD_POSITION 0 +#define SMBUS_PHY_TGT_DATA_SETUP_TGT_DATA_SETUP_FIELD_POSITION 0 +#define SMBUS_PHY_TGT_TEXT_PRESCALER_TGT_TEXT_PRESCALER_FIELD_POSITION 0 +#define SMBUS_PHY_TGT_TEXT_TIMEOUT_TGT_TEXT_TIMEOUT_FIELD_POSITION 0 +#define SMBUS_PHY_TGT_TEXT_MAX_TGT_TEXT_MAX_FIELD_POSITION 0 +#define SMBUS_PHY_TGT_DBG_STATE_DBG_STATE_FIELD_POSITION 0 +#define SMBUS_PHY_TGT_DATA_HOLD_DATA_HOLD_FIELD_POSITION 0 +#define SMBUS_TGT_STATUS_ACTIVE_FIELD_POSITION 8 +#define SMBUS_TGT_STATUS_ADDRESS_FIELD_POSITION 1 +#define SMBUS_TGT_STATUS_RW_FIELD_POSITION 0 +#define SMBUS_TGT_DESC_FIFO_ID_FIELD_POSITION 8 +#define SMBUS_TGT_DESC_FIFO_PAYLOAD_FIELD_POSITION 0 +#define SMBUS_TGT_DESC_STATUS_FILL_LEVEL_FIELD_POSITION 8 +#define SMBUS_TGT_DESC_STATUS_FULL_FIELD_POSITION 5 +#define SMBUS_TGT_DESC_STATUS_ALMOST_FULL_FIELD_POSITION 4 +#define SMBUS_TGT_DESC_STATUS_ALMOST_EMPTY_FIELD_POSITION 1 +#define SMBUS_TGT_DESC_STATUS_EMPTY_FIELD_POSITION 0 +#define SMBUS_TGT_RX_FIFO_RESET_FIELD_POSITION 31 +#define SMBUS_TGT_RX_FIFO_PAYLOAD_FIELD_POSITION 0 +#define SMBUS_TGT_RX_FIFO_STATUS_MAX_FILL_LEVEL_FIELD_POSITION 16 +#define SMBUS_TGT_RX_FIFO_STATUS_FILL_LEVEL_FIELD_POSITION 8 +#define SMBUS_TGT_RX_FIFO_STATUS_RESET_BUSY_FIELD_POSITION 6 +#define SMBUS_TGT_RX_FIFO_STATUS_FULL_FIELD_POSITION 5 +#define SMBUS_TGT_RX_FIFO_STATUS_ALMOST_FULL_FIELD_POSITION 4 +#define SMBUS_TGT_RX_FIFO_STATUS_ALMOST_EMPTY_FIELD_POSITION 1 +#define SMBUS_TGT_RX_FIFO_STATUS_EMPTY_FIELD_POSITION 0 +#define SMBUS_TGT_RX_FIFO_FILL_THRESHOLD_FILL_THRESHOLD_FIELD_POSITION 0 +#define SMBUS_TGT_DBG_FORCE_PEC_ERROR_FIELD_POSITION 31 +#define SMBUS_TGT_DBG_DBG_STATE_FIELD_POSITION 0 +#define SMBUS_TGT_CONTROL_0_ENABLE_FIELD_POSITION 31 +#define SMBUS_TGT_CONTROL_0_ADDRESS_FIELD_POSITION 1 +#define SMBUS_TGT_CONTROL_1_ENABLE_FIELD_POSITION 31 +#define SMBUS_TGT_CONTROL_1_ADDRESS_FIELD_POSITION 1 +#define SMBUS_TGT_CONTROL_2_ENABLE_FIELD_POSITION 31 +#define SMBUS_TGT_CONTROL_2_ADDRESS_FIELD_POSITION 1 +#define SMBUS_TGT_CONTROL_3_ENABLE_FIELD_POSITION 31 +#define SMBUS_TGT_CONTROL_3_ADDRESS_FIELD_POSITION 1 +#define SMBUS_TGT_CONTROL_4_ENABLE_FIELD_POSITION 31 +#define SMBUS_TGT_CONTROL_4_ADDRESS_FIELD_POSITION 1 +#define SMBUS_TGT_CONTROL_5_ENABLE_FIELD_POSITION 31 +#define SMBUS_TGT_CONTROL_5_ADDRESS_FIELD_POSITION 1 +#define SMBUS_TGT_CONTROL_6_ENABLE_FIELD_POSITION 31 +#define SMBUS_TGT_CONTROL_6_ADDRESS_FIELD_POSITION 1 +#define SMBUS_TGT_CONTROL_7_ENABLE_FIELD_POSITION 31 +#define SMBUS_TGT_CONTROL_7_ADDRESS_FIELD_POSITION 1 +#define SMBUS_PHY_CTLR_DATA_HOLD_CTLR_DATA_HOLD_FIELD_POSITION 0 +#define SMBUS_PHY_CTLR_START_HOLD_CTLR_START_HOLD_FIELD_POSITION 0 +#define SMBUS_PHY_CTLR_START_SETUP_CTLR_START_SETUP_FIELD_POSITION 0 +#define SMBUS_PHY_CTLR_STOP_SETUP_CTLR_STOP_SETUP_FIELD_POSITION 0 +#define SMBUS_PHY_CTLR_CLK_TLOW_CTLR_CLK_TLOW_FIELD_POSITION 0 +#define SMBUS_PHY_CTLR_CLK_THIGH_CTLR_CLK_THIGH_FIELD_POSITION 0 +#define SMBUS_PHY_CTLR_TEXT_PRESCALER_CTLR_TEXT_PRESCALER_FIELD_POSITION 0 +#define SMBUS_PHY_CTLR_TEXT_TIMEOUT_CTLR_TEXT_TIMEOUT_FIELD_POSITION 0 +#define SMBUS_PHY_CTLR_TEXT_MAX_CTLR_TEXT_MAX_FIELD_POSITION 0 +#define SMBUS_PHY_CTLR_CEXT_PRESCALER_CTLR_CEXT_PRESCALER_FIELD_POSITION 0 +#define SMBUS_PHY_CTLR_CEXT_TIMEOUT_CTLR_CEXT_TIMEOUT_FIELD_POSITION 0 +#define SMBUS_PHY_CTLR_CEXT_MAX_CTLR_CEXT_MAX_FIELD_POSITION 0 +#define SMBUS_PHY_CTLR_DBG_STATE_DBG_STATE_FIELD_POSITION 0 +#define SMBUS_CTLR_CONTROL_ENABLE_FIELD_POSITION 0 +#define SMBUS_CTLR_STATUS_ENABLE_FIELD_POSITION 0 +#define SMBUS_CTLR_DESC_FIFO_RESET_FIELD_POSITION 31 +#define SMBUS_CTLR_DESC_FIFO_ID_FIELD_POSITION 8 +#define SMBUS_CTLR_DESC_FIFO_PAYLOAD_FIELD_POSITION 0 +#define SMBUS_CTLR_DESC_STATUS_FILL_LEVEL_FIELD_POSITION 8 +#define SMBUS_CTLR_DESC_STATUS_RESET_BUSY_FIELD_POSITION 6 +#define SMBUS_CTLR_DESC_STATUS_FULL_FIELD_POSITION 5 +#define SMBUS_CTLR_DESC_STATUS_ALMOST_FULL_FIELD_POSITION 4 +#define SMBUS_CTLR_DESC_STATUS_ALMOST_EMPTY_FIELD_POSITION 1 +#define SMBUS_CTLR_DESC_STATUS_EMPTY_FIELD_POSITION 0 +#define SMBUS_CTLR_RX_FIFO_RESET_FIELD_POSITION 31 +#define SMBUS_CTLR_RX_FIFO_PAYLOAD_FIELD_POSITION 0 +#define SMBUS_CTLR_RX_FIFO_STATUS_MAX_FILL_LEVEL_FIELD_POSITION 16 +#define SMBUS_CTLR_RX_FIFO_STATUS_FILL_LEVEL_FIELD_POSITION 8 +#define SMBUS_CTLR_RX_FIFO_STATUS_RESET_BUSY_FIELD_POSITION 6 +#define SMBUS_CTLR_RX_FIFO_STATUS_FULL_FIELD_POSITION 5 +#define SMBUS_CTLR_RX_FIFO_STATUS_ALMOST_FULL_FIELD_POSITION 4 +#define SMBUS_CTLR_RX_FIFO_STATUS_ALMOST_EMPTY_FIELD_POSITION 1 +#define SMBUS_CTLR_RX_FIFO_STATUS_EMPTY_FIELD_POSITION 0 +#define SMBUS_CTLR_RX_FIFO_FILL_THRESHOLD_FILL_THRESHOLD_FIELD_POSITION 0 +#define SMBUS_CTLR_DBG_FORCE_PEC_ERROR_FIELD_POSITION 31 +#define SMBUS_CTLR_DBG_DBG_STATE_FIELD_POSITION 0 + + +#define SMBUS_IP_VERSION_MAJOR_VERSION_MASK 0xFFFF0000U +#define SMBUS_IP_VERSION_MINOR_VERSION_MASK 0x0000FFFFU +#define SMBUS_IP_REVISION_CORE_REVISION_MASK 0x0000FFFFU +#define SMBUS_IP_MAGIC_NUM_MAGIC_NUMBER_MASK 0xFFFFFFFFU +#define SMBUS_IP_BUILD_CONFIG_0_FREQ_HZ_AXI_ACLK_MASK 0xFFFFFFFFU +#define SMBUS_IP_BUILD_CONFIG_1_NUM_TARGET_DEVICES_MASK 0x000000F0U +#define SMBUS_IP_BUILD_CONFIG_1_SMBUS_DEV_CLASS_MASK 0x00000003U +#define SMBUS_IRQ_GIE_ENABLE_MASK 0x00000001U +#define SMBUS_IRQ_IER_CTLR_DESC_FIFO_ALMOST_EMPTY_MASK 0x00008000U +#define SMBUS_IRQ_IER_CTLR_RX_FIFO_FILL_THRESHOLD_MASK 0x00004000U +#define SMBUS_IRQ_IER_CTLR_DESC_FIFO_EMPTY_MASK 0x00002000U +#define SMBUS_IRQ_IER_CTLR_DONE_MASK 0x00001000U +#define SMBUS_IRQ_IER_CTLR_PEC_ERROR_MASK 0x00000800U +#define SMBUS_IRQ_IER_CTLR_NACK_ERROR_MASK 0x00000400U +#define SMBUS_IRQ_IER_CTLR_LOA_MASK 0x00000200U +#define SMBUS_IRQ_IER_TGT_DESC_FIFO_ALMOST_EMPTY_MASK 0x00000100U +#define SMBUS_IRQ_IER_TGT_WRITE_MASK 0x00000080U +#define SMBUS_IRQ_IER_TGT_READ_MASK 0x00000040U +#define SMBUS_IRQ_IER_TGT_RX_FIFO_FILL_THRESHOLD_MASK 0x00000020U +#define SMBUS_IRQ_IER_TGT_DESC_FIFO_EMPTY_MASK 0x00000010U +#define SMBUS_IRQ_IER_TGT_DONE_MASK 0x00000008U +#define SMBUS_IRQ_IER_TGT_PEC_ERROR_MASK 0x00000004U +#define SMBUS_IRQ_IER_TGT_LOA_MASK 0x00000002U +#define SMBUS_IRQ_IER_ERROR_IRQ_MASK 0x00000001U +#define SMBUS_IRQ_ISR_CTLR_DESC_FIFO_ALMOST_EMPTY_MASK 0x00008000U +#define SMBUS_IRQ_ISR_CTLR_RX_FIFO_FILL_THRESHOLD_MASK 0x00004000U +#define SMBUS_IRQ_ISR_CTLR_DESC_FIFO_EMPTY_MASK 0x00002000U +#define SMBUS_IRQ_ISR_CTLR_DONE_MASK 0x00001000U +#define SMBUS_IRQ_ISR_CTLR_PEC_ERROR_MASK 0x00000800U +#define SMBUS_IRQ_ISR_CTLR_NACK_ERROR_MASK 0x00000400U +#define SMBUS_IRQ_ISR_CTLR_LOA_MASK 0x00000200U +#define SMBUS_IRQ_ISR_TGT_DESC_FIFO_ALMOST_EMPTY_MASK 0x00000100U +#define SMBUS_IRQ_ISR_TGT_WRITE_MASK 0x00000080U +#define SMBUS_IRQ_ISR_TGT_READ_MASK 0x00000040U +#define SMBUS_IRQ_ISR_TGT_RX_FIFO_FILL_THRESHOLD_MASK 0x00000020U +#define SMBUS_IRQ_ISR_TGT_DESC_FIFO_EMPTY_MASK 0x00000010U +#define SMBUS_IRQ_ISR_TGT_DONE_MASK 0x00000008U +#define SMBUS_IRQ_ISR_TGT_PEC_ERROR_MASK 0x00000004U +#define SMBUS_IRQ_ISR_TGT_LOA_MASK 0x00000002U +#define SMBUS_IRQ_ISR_ERROR_IRQ_MASK 0x00000001U +#define SMBUS_ERR_IRQ_IER_PHY_CTLR_CEXT_TIMEOUT_MASK 0x00080000U +#define SMBUS_ERR_IRQ_IER_PHY_CTLR_TEXT_TIMEOUT_MASK 0x00040000U +#define SMBUS_ERR_IRQ_IER_CTLR_RX_FIFO_ERROR_MASK 0x00020000U +#define SMBUS_ERR_IRQ_IER_CTLR_RX_FIFO_OVERFLOW_MASK 0x00010000U +#define SMBUS_ERR_IRQ_IER_CTLR_RX_FIFO_UNDERFLOW_MASK 0x00008000U +#define SMBUS_ERR_IRQ_IER_CTLR_DESC_FIFO_ERROR_MASK 0x00004000U +#define SMBUS_ERR_IRQ_IER_CTLR_DESC_FIFO_OVERFLOW_MASK 0x00002000U +#define SMBUS_ERR_IRQ_IER_CTLR_DESC_FIFO_UNDERFLOW_MASK 0x00001000U +#define SMBUS_ERR_IRQ_IER_CTLR_DESC_ERROR_MASK 0x00000800U +#define SMBUS_ERR_IRQ_IER_PHY_TGT_TEXT_TIMEOUT_MASK 0x00000400U +#define SMBUS_ERR_IRQ_IER_TGT_RX_FIFO_ERROR_MASK 0x00000200U +#define SMBUS_ERR_IRQ_IER_TGT_RX_FIFO_OVERFLOW_MASK 0x00000100U +#define SMBUS_ERR_IRQ_IER_TGT_RX_FIFO_UNDERFLOW_MASK 0x00000080U +#define SMBUS_ERR_IRQ_IER_TGT_DESC_FIFO_ERROR_MASK 0x00000040U +#define SMBUS_ERR_IRQ_IER_TGT_DESC_FIFO_OVERFLOW_MASK 0x00000020U +#define SMBUS_ERR_IRQ_IER_TGT_DESC_FIFO_UNDERFLOW_MASK 0x00000010U +#define SMBUS_ERR_IRQ_IER_TGT_DESC_ERROR_MASK 0x00000008U +#define SMBUS_ERR_IRQ_IER_PHY_UNEXPTD_BUS_IDLE_MASK 0x00000004U +#define SMBUS_ERR_IRQ_IER_PHY_SMBDAT_LOW_TIMEOUT_MASK 0x00000002U +#define SMBUS_ERR_IRQ_IER_PHY_SMBCLK_LOW_TIMEOUT_MASK 0x00000001U +#define SMBUS_ERR_IRQ_ISR_PHY_CTLR_CEXT_TIMEOUT_MASK 0x00080000U +#define SMBUS_ERR_IRQ_ISR_PHY_CTLR_TEXT_TIMEOUT_MASK 0x00040000U +#define SMBUS_ERR_IRQ_ISR_CTLR_RX_FIFO_ERROR_MASK 0x00020000U +#define SMBUS_ERR_IRQ_ISR_CTLR_RX_FIFO_OVERFLOW_MASK 0x00010000U +#define SMBUS_ERR_IRQ_ISR_CTLR_RX_FIFO_UNDERFLOW_MASK 0x00008000U +#define SMBUS_ERR_IRQ_ISR_CTLR_DESC_FIFO_ERROR_MASK 0x00004000U +#define SMBUS_ERR_IRQ_ISR_CTLR_DESC_FIFO_OVERFLOW_MASK 0x00002000U +#define SMBUS_ERR_IRQ_ISR_CTLR_DESC_FIFO_UNDERFLOW_MASK 0x00001000U +#define SMBUS_ERR_IRQ_ISR_CTLR_DESC_ERROR_MASK 0x00000800U +#define SMBUS_ERR_IRQ_ISR_PHY_TGT_TEXT_TIMEOUT_MASK 0x00000400U +#define SMBUS_ERR_IRQ_ISR_TGT_RX_FIFO_ERROR_MASK 0x00000200U +#define SMBUS_ERR_IRQ_ISR_TGT_RX_FIFO_OVERFLOW_MASK 0x00000100U +#define SMBUS_ERR_IRQ_ISR_TGT_RX_FIFO_UNDERFLOW_MASK 0x00000080U +#define SMBUS_ERR_IRQ_ISR_TGT_DESC_FIFO_ERROR_MASK 0x00000040U +#define SMBUS_ERR_IRQ_ISR_TGT_DESC_FIFO_OVERFLOW_MASK 0x00000020U +#define SMBUS_ERR_IRQ_ISR_TGT_DESC_FIFO_UNDERFLOW_MASK 0x00000010U +#define SMBUS_ERR_IRQ_ISR_TGT_DESC_ERROR_MASK 0x00000008U +#define SMBUS_ERR_IRQ_ISR_PHY_UNEXPTD_BUS_IDLE_MASK 0x00000004U +#define SMBUS_ERR_IRQ_ISR_PHY_SMBDAT_LOW_TIMEOUT_MASK 0x00000002U +#define SMBUS_ERR_IRQ_ISR_PHY_SMBCLK_LOW_TIMEOUT_MASK 0x00000001U +#define SMBUS_IRQ_ISR_FORCE_IRQ_ISR_FORCE_MASK 0x0000FFFFU +#define SMBUS_ERR_IRQ_ISR_FORCE_ERR_IRQ_ISR_FORCE_MASK 0x000FFFFFU +#define SMBUS_PHY_STATUS_SMBDAT_LOW_TIMEOUT_MASK 0x00000004U +#define SMBUS_PHY_STATUS_SMBCLK_LOW_TIMEOUT_MASK 0x00000002U +#define SMBUS_PHY_STATUS_BUS_IDLE_MASK 0x00000001U +#define SMBUS_PHY_FILTER_CONTROL_ENABLE_MASK 0x80000000U +#define SMBUS_PHY_FILTER_CONTROL_DURATION_MASK 0x0000001FU +#define SMBUS_PHY_BUS_FREE_TIME_BUS_FREE_TIME_MASK 0x00000FFFU +#define SMBUS_PHY_IDLE_THRESHOLD_IDLE_THRESHOLD_MASK 0x00007FFFU +#define SMBUS_PHY_TIMEOUT_PRESCALER_TIMEOUT_PRESCALER_MASK 0x00001FFFU +#define SMBUS_PHY_TIMEOUT_MIN_TIMEOUT_ENABLE_MASK 0x80000000U +#define SMBUS_PHY_TIMEOUT_MIN_TIMEOUT_MIN_MASK 0x00000FFFU +#define SMBUS_PHY_TIMEOUT_MAX_TIMEOUT_MAX_MASK 0x00000FFFU +#define SMBUS_PHY_RESET_CONTROL_SMBCLK_FORCE_TIMEOUT_MASK 0x80000000U +#define SMBUS_PHY_RESET_CONTROL_SMBCLK_FORCE_LOW_MASK 0x00000FFFU +#define SMBUS_PHY_TGT_DATA_SETUP_TGT_DATA_SETUP_MASK 0x000003FFU +#define SMBUS_PHY_TGT_TEXT_PRESCALER_TGT_TEXT_PRESCALER_MASK 0x000001FFU +#define SMBUS_PHY_TGT_TEXT_TIMEOUT_TGT_TEXT_TIMEOUT_MASK 0x00007FFFU +#define SMBUS_PHY_TGT_TEXT_MAX_TGT_TEXT_MAX_MASK 0x00007FFFU +#define SMBUS_PHY_TGT_DBG_STATE_DBG_STATE_MASK 0x000000FFU +#define SMBUS_PHY_TGT_DATA_HOLD_DATA_HOLD_MASK 0x000003FFU +#define SMBUS_TGT_STATUS_ACTIVE_MASK 0x00000100U +#define SMBUS_TGT_STATUS_ADDRESS_MASK 0x000000FEU +#define SMBUS_TGT_STATUS_RW_MASK 0x00000001U +#define SMBUS_TGT_DESC_FIFO_ID_MASK 0x00000F00U +#define SMBUS_TGT_DESC_FIFO_PAYLOAD_MASK 0x000000FFU +#define SMBUS_TGT_DESC_STATUS_FILL_LEVEL_MASK 0x00007F00U +#define SMBUS_TGT_DESC_STATUS_FULL_MASK 0x00000020U +#define SMBUS_TGT_DESC_STATUS_ALMOST_FULL_MASK 0x00000010U +#define SMBUS_TGT_DESC_STATUS_ALMOST_EMPTY_MASK 0x00000002U +#define SMBUS_TGT_DESC_STATUS_EMPTY_MASK 0x00000001U +#define SMBUS_TGT_RX_FIFO_RESET_MASK 0x80000000U +#define SMBUS_TGT_RX_FIFO_PAYLOAD_MASK 0x000000FFU +#define SMBUS_TGT_RX_FIFO_STATUS_MAX_FILL_LEVEL_MASK 0x007F0000U +#define SMBUS_TGT_RX_FIFO_STATUS_FILL_LEVEL_MASK 0x00007F00U +#define SMBUS_TGT_RX_FIFO_STATUS_RESET_BUSY_MASK 0x00000040U +#define SMBUS_TGT_RX_FIFO_STATUS_FULL_MASK 0x00000020U +#define SMBUS_TGT_RX_FIFO_STATUS_ALMOST_FULL_MASK 0x00000010U +#define SMBUS_TGT_RX_FIFO_STATUS_ALMOST_EMPTY_MASK 0x00000002U +#define SMBUS_TGT_RX_FIFO_STATUS_EMPTY_MASK 0x00000001U +#define SMBUS_TGT_RX_FIFO_FILL_THRESHOLD_FILL_THRESHOLD_MASK 0x0000007FU +#define SMBUS_TGT_DBG_FORCE_PEC_ERROR_MASK 0x80000000U +#define SMBUS_TGT_DBG_DBG_STATE_MASK 0x0000007FU +#define SMBUS_TGT_CONTROL_0_ENABLE_MASK 0x80000000U +#define SMBUS_TGT_CONTROL_0_ADDRESS_MASK 0x000000FEU +#define SMBUS_TGT_CONTROL_1_ENABLE_MASK 0x80000000U +#define SMBUS_TGT_CONTROL_1_ADDRESS_MASK 0x000000FEU +#define SMBUS_TGT_CONTROL_2_ENABLE_MASK 0x80000000U +#define SMBUS_TGT_CONTROL_2_ADDRESS_MASK 0x000000FEU +#define SMBUS_TGT_CONTROL_3_ENABLE_MASK 0x80000000U +#define SMBUS_TGT_CONTROL_3_ADDRESS_MASK 0x000000FEU +#define SMBUS_TGT_CONTROL_4_ENABLE_MASK 0x80000000U +#define SMBUS_TGT_CONTROL_4_ADDRESS_MASK 0x000000FEU +#define SMBUS_TGT_CONTROL_5_ENABLE_MASK 0x80000000U +#define SMBUS_TGT_CONTROL_5_ADDRESS_MASK 0x000000FEU +#define SMBUS_TGT_CONTROL_6_ENABLE_MASK 0x80000000U +#define SMBUS_TGT_CONTROL_6_ADDRESS_MASK 0x000000FEU +#define SMBUS_TGT_CONTROL_7_ENABLE_MASK 0x80000000U +#define SMBUS_TGT_CONTROL_7_ADDRESS_MASK 0x000000FEU +#define SMBUS_PHY_CTLR_DATA_HOLD_CTLR_DATA_HOLD_MASK 0x00007FFFU +#define SMBUS_PHY_CTLR_START_HOLD_CTLR_START_HOLD_MASK 0x00007FFFU +#define SMBUS_PHY_CTLR_START_SETUP_CTLR_START_SETUP_MASK 0x00007FFFU +#define SMBUS_PHY_CTLR_STOP_SETUP_CTLR_STOP_SETUP_MASK 0x00007FFFU +#define SMBUS_PHY_CTLR_CLK_TLOW_CTLR_CLK_TLOW_MASK 0x00007FFFU +#define SMBUS_PHY_CTLR_CLK_THIGH_CTLR_CLK_THIGH_MASK 0x00007FFFU +#define SMBUS_PHY_CTLR_TEXT_PRESCALER_CTLR_TEXT_PRESCALER_MASK 0x000001FFU +#define SMBUS_PHY_CTLR_TEXT_TIMEOUT_CTLR_TEXT_TIMEOUT_MASK 0x00007FFFU +#define SMBUS_PHY_CTLR_TEXT_MAX_CTLR_TEXT_MAX_MASK 0x00007FFFU +#define SMBUS_PHY_CTLR_CEXT_PRESCALER_CTLR_CEXT_PRESCALER_MASK 0x000001FFU +#define SMBUS_PHY_CTLR_CEXT_TIMEOUT_CTLR_CEXT_TIMEOUT_MASK 0x00003FFFU +#define SMBUS_PHY_CTLR_CEXT_MAX_CTLR_CEXT_MAX_MASK 0x00003FFFU +#define SMBUS_PHY_CTLR_DBG_STATE_DBG_STATE_MASK 0x000000FFU +#define SMBUS_CTLR_CONTROL_ENABLE_MASK 0x00000001U +#define SMBUS_CTLR_STATUS_ENABLE_MASK 0x00000001U +#define SMBUS_CTLR_DESC_FIFO_RESET_MASK 0x80000000U +#define SMBUS_CTLR_DESC_FIFO_ID_MASK 0x00000F00U +#define SMBUS_CTLR_DESC_FIFO_PAYLOAD_MASK 0x000000FFU +#define SMBUS_CTLR_DESC_STATUS_FILL_LEVEL_MASK 0x00007F00U +#define SMBUS_CTLR_DESC_STATUS_RESET_BUSY_MASK 0x00000040U +#define SMBUS_CTLR_DESC_STATUS_FULL_MASK 0x00000020U +#define SMBUS_CTLR_DESC_STATUS_ALMOST_FULL_MASK 0x00000010U +#define SMBUS_CTLR_DESC_STATUS_ALMOST_EMPTY_MASK 0x00000002U +#define SMBUS_CTLR_DESC_STATUS_EMPTY_MASK 0x00000001U +#define SMBUS_CTLR_RX_FIFO_RESET_MASK 0x80000000U +#define SMBUS_CTLR_RX_FIFO_PAYLOAD_MASK 0x000000FFU +#define SMBUS_CTLR_RX_FIFO_STATUS_MAX_FILL_LEVEL_MASK 0x007F0000U +#define SMBUS_CTLR_RX_FIFO_STATUS_FILL_LEVEL_MASK 0x00007F00U +#define SMBUS_CTLR_RX_FIFO_STATUS_RESET_BUSY_MASK 0x00000040U +#define SMBUS_CTLR_RX_FIFO_STATUS_FULL_MASK 0x00000020U +#define SMBUS_CTLR_RX_FIFO_STATUS_ALMOST_FULL_MASK 0x00000010U +#define SMBUS_CTLR_RX_FIFO_STATUS_ALMOST_EMPTY_MASK 0x00000002U +#define SMBUS_CTLR_RX_FIFO_STATUS_EMPTY_MASK 0x00000001U +#define SMBUS_CTLR_RX_FIFO_FILL_THRESHOLD_FILL_THRESHOLD_MASK 0x0000007FU +#define SMBUS_CTLR_DBG_FORCE_PEC_ERROR_MASK 0x80000000U +#define SMBUS_CTLR_DBG_DBG_STATE_MASK 0x0000007FU + +#ifdef __cplusplus +} +#endif + + +#endif /* _SMBUS_HARDWARE_H_ */ diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_hardware_access.c b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_hardware_access.c new file mode 100755 index 00000000..3890624f --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_hardware_access.c @@ -0,0 +1,3894 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains functions to read and write to the SMBus IP register map + * It also has functions for writing Descriptors to the IPs Descriptor FIFO + * + * @file smbus_hardware_access.c + * + */ + +#include "smbus.h" +#include "smbus_internal.h" +#include "smbus_hardware_access.h" + +char* pDescriptorTargetRead = "DESC_TARGET_READ"; +char* pDescriptorTargetPEC = "DESC_TARGET_READ_PEC"; +char* pDescriptorTargetWriteACK = "DESC_TARGET_WRITE_ACK"; +char* pDescriptorTargetWriteNACK = "DESC_TARGET_WRITE_NACK"; +char* pDescriptorTargetWritePEC = "DESC_TARGET_WRITE_PEC"; +char* pDescriptorControllerReadStart = "DESC_CONTROLLER_READ_START"; +char* pDescriptorControllerReadQuick = "DESC_CONTROLLER_READ_QUICK"; +char* pDescriptorControllerReadByte = "DESC_CONTROLLER_READ_BYTE"; +char* pDescriptorControllerReadStop = "DESC_CONTROLLER_READ_STOP"; +char* pDescriptorControllerReadPEC = "DESC_CONTROLLER_READ_PEC"; +char* pDescriptorControllerWriteStart = "DESC_CONTROLLER_WRITE_START"; +char* pDescriptorControllerWriteQuick = "DESC_CONTROLLER_WRITE_QUICK"; +char* pDescriptorControllerWriteByte = "DESC_CONTROLLER_WRITE_BYTE"; +char* pDescriptorControllerWriteStop = "DESC_CONTROLLER_WRITE_STOP"; +char* pDescriptorControllerWritePEC = "DESC_CONTROLLER_WRITE_PEC"; +char* pDescriptorUnknown = "DESC_UNKNOWN"; + +/********************** Static function declarations ***************************/ + +/****************************************************************************** +* +* @brief Reads the uint32_t value from a hardware adddress +* +* @param pvAddr is a pointer to a hardware address +* +* @return uint32_t +* +* @note None. +* +*****************************************************************************/ +static inline uint32_t prvulSMBusIn32( void* pvAddr ); + +/****************************************************************************** +* +* @brief Writes a uint32_t value to a hardware adddress +* +* @param pvAddr is a pointer to a hardware address +* @param ulValue is uint32_t value to be written +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static inline void prvvSMBusOut32( void* pvAddr, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Look up the descriptor uint8_t value for the given descriptor ENUM +* +* @param xDescriptor is the descriptor ENUM to use for the look up. +* +* @return uint8_t descriptor ID value +* +* @note None. +* +*****************************************************************************/ +static uint8_t prvucSMBusGenericDescriptorIDLookup( SMBus_HW_Descriptor_Type xDescriptor ); + +/****************************************************************************** +* +* @brief Given the descriptor, look up the descriptor ID and write it into the +* IP's Target descriptor FIFO. Depending on the descriptor type a payload +* byte may be written along with the descriptor. +* The ucNoStatusCheck can be used to check if the FIFO is full before +* writing the descriptor or ignore the check +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param xDescriptor is the descriptor ENUM +* @param ucPayload is the optional payload byte +* @param ucNoStatusCheck is a boolean check +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static uint8_t prvucSMBusTargetDescriptorApply( SMBUS_PROFILE_TYPE* pxSMBusProfile, SMBus_HW_Descriptor_Type xDescriptor, + uint8_t ucPayload, uint8_t ucNoStatusCheck ); + +/****************************************************************************** +* +* @brief Given the descriptor, look up the descriptor ID and write it into the +* IP's Controller descriptor FIFO. Depending on the descriptor type a +* payload byte may be written along with the descriptor. +* The ucNoStatusCheck can be used to check if the FIFO is full before +* writing the descriptor or ignore the check +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param xDescriptor is the descriptor ENUM +* @param ucPayload is the optional payload byte +* @param ucNoStatusCheck is a boolean check +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static uint8_t prvucSMBusControllerDescriptorApply( SMBUS_PROFILE_TYPE* pxSMBusProfile, + SMBus_HW_Descriptor_Type xDescriptor, uint8_t ucPayload, + uint8_t ucNoStatusCheck ); + +/****************************************************************************** +* +* @brief Return the value read form the register offset location +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulRegisterOffset offset from the start of the IP's base address +* +* @return uint32_t value +* +* @note None. +* +*****************************************************************************/ +static uint32_t prvulSMBusHardwareRead( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulRegisterOffset ); + +/****************************************************************************** +* +* @brief Write the supplied value to the register location +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulRegisterOffset offset from the start of the IP's base address +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHardwareWrite( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulRegisterOffset, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Modify the masked part of the register with the value supplied +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulRegisterOffset offset from the start of the IP's base address +* @param ulMask bitmask to use for the write +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHardwareWriteWithMask( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulRegisterOffset, + uint32_t ulMask, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_0 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl0Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_0 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl0Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_1 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl1Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_1 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl1Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_2 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl2Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_2 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl2Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_3 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl3Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_3 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl3Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_4 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl4Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_4 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl4Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_5 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl5Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_5 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl5Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_6 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl6Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_6 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl6Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_7 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl7Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_7 +* register +* +* @param pxSMBusProfile is a pointer to the SMBus profile. +* @param ulValue is the value to write +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl7Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/*******************************************************************************/ + +/****************************************************************************** +* +* @brief Reads the uint32_t value from a hardware adddress +* +*****************************************************************************/ +static inline uint32_t prvulSMBusIn32( void* pvAddr ) +{ + return *( volatile uint32_t* )pvAddr; +} + +/****************************************************************************** +* +* @brief Writes a uint32_t value to a hardware adddress +* +*****************************************************************************/ +static inline void prvvSMBusOut32( void* pvAddr, uint32_t ulValue ) +{ + /* write 32 bit value to specified address */ + volatile uint32_t* LocalAddr = ( volatile uint32_t* )pvAddr; + *LocalAddr = ulValue; +} + +/****************************************************************************** +* +* @brief Look up the descriptor uint8_t value for the given descriptor ENUM +* +*****************************************************************************/ +static uint8_t prvucSMBusGenericDescriptorIDLookup( SMBus_HW_Descriptor_Type xDescriptor ) +{ + uint8_t ucDescriptorID = 0xFF; + + switch( xDescriptor ) + { + case DESC_CONTROLLER_WRITE_START: + ucDescriptorID = 0x0; + break; + + case DESC_CONTROLLER_WRITE_QUICK: + ucDescriptorID = 0x1; + break; + + case DESC_CONTROLLER_WRITE_BYTE: + ucDescriptorID = 0x2; + break; + + case DESC_CONTROLLER_WRITE_STOP: + ucDescriptorID = 0x3; + break; + + case DESC_CONTROLLER_WRITE_PEC: + ucDescriptorID = 0x4; + break; + + case DESC_CONTROLLER_READ_START: + ucDescriptorID = 0x8; + break; + + case DESC_CONTROLLER_READ_QUICK: + ucDescriptorID = 0x9; + break; + + case DESC_CONTROLLER_READ_BYTE: + ucDescriptorID = 0xA; + break; + + case DESC_CONTROLLER_READ_STOP: + ucDescriptorID = 0xB; + break; + + case DESC_CONTROLLER_READ_PEC: + ucDescriptorID = 0xC; + break; + + case DESC_TARGET_WRITE_ACK: + ucDescriptorID = 0x0; + break; + + case DESC_TARGET_WRITE_NACK: + ucDescriptorID = 0x1; + break; + + case DESC_TARGET_WRITE_PEC: + ucDescriptorID = 0x2; + break; + + case DESC_TARGET_READ: + ucDescriptorID = 0x8; + break; + + case DESC_TARGET_READ_PEC: + ucDescriptorID = 0x9; + break; + + default: + break; + } + + return ucDescriptorID; +} + +/****************************************************************************** +* +* @brief Given the descriptor, look up the descriptor ID and write it into the +* IP's Target descriptor FIFO. Depending on the descriptor type a payload +* byte may be written along with the descriptor. +* The ucNoStatusCheck can be used to check if the FIFO is full before +* writing the descriptor or ignore the check +* +*****************************************************************************/ +static uint8_t prvucSMBusTargetDescriptorApply( SMBUS_PROFILE_TYPE* pxSMBusProfile, SMBus_HW_Descriptor_Type xDescriptor, + uint8_t ucPayload, uint8_t ucNoStatusCheck ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + uint8_t ucDescriptorID = 0; + uint32_t ulValue = 0; + + if( ( NULL != pxSMBusProfile ) && + ( DESC_MAX > xDescriptor ) ) + { + ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS; + + if( SMBUS_FALSE == ucNoStatusCheck ) + { + if( SMBUS_DESC_FIFO_IS_FULL == ulSMBusHWReadTgtDescStatusFull( pxSMBusProfile ) ) + { + ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + } + } + + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS == ucReturnCode ) + { + ucDescriptorID = prvucSMBusGenericDescriptorIDLookup( xDescriptor ); + ulValue = ( ( uint32_t )ucDescriptorID << SMBUS_TGT_DESC_FIFO_ID_FIELD_POSITION ) | ( uint32_t )ucPayload; + + vSMBusHWWriteTgtDescFifo( pxSMBusProfile, ulValue ); + } + } + return ucReturnCode; +} + +/****************************************************************************** +* +* @brief Given the descriptor, look up the descriptor ID and write it into the +* IP's Controller descriptor FIFO. Depending on the descriptor type a +* payload byte may be written along with the descriptor. +* The ucNoStatusCheck can be used to check if the FIFO is full before +* writing the descriptor or ignore the check +* +*****************************************************************************/ +static uint8_t prvucSMBusControllerDescriptorApply( SMBUS_PROFILE_TYPE* pxSMBusProfile, + SMBus_HW_Descriptor_Type xDescriptor, uint8_t ucPayload, + uint8_t ucNoStatusCheck ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + uint8_t ucDescriptorID = 0; + uint32_t ulValue = 0; + + if( ( NULL != pxSMBusProfile ) && + ( DESC_MAX > xDescriptor ) ) + { + ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS; + + if( SMBUS_FALSE == ucNoStatusCheck ) + { + if( SMBUS_DESC_FIFO_IS_FULL == ulSMBusHWReadCtrlDescStatusFull( pxSMBusProfile ) ) + { + ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + } + } + + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS == ucReturnCode ) + { + ucDescriptorID = prvucSMBusGenericDescriptorIDLookup( xDescriptor ); + ulValue = ( ( uint32_t )ucDescriptorID << SMBUS_CTLR_DESC_FIFO_ID_FIELD_POSITION ) | ( uint32_t )ucPayload; + + vSMBusHWWriteCtrlDescFifo( pxSMBusProfile, ulValue ); + } + } + return ucReturnCode; +} + +/******************************************************************************* +* +* @brief Writes a data byte along with a Target Read - Read Descriptor ID to transmit the data byte +* +*******************************************************************************/ +uint8_t ucSMBusTargetReadDescriptorRead( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucData ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + + if( NULL != pxSMBusProfile ) + { + ucReturnCode = prvucSMBusTargetDescriptorApply( pxSMBusProfile, DESC_TARGET_READ, ucData, SMBUS_FALSE ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Target Read - PEC Descriptor ID to the Target Descriptor FIFO +* To iform the IP to transmit the PEC byte it has calculated on the data +* +*****************************************************************/ +uint8_t ucSMBusTargetReadDescriptorPECRead( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + ucReturnCode = prvucSMBusTargetDescriptorApply( pxSMBusProfile, DESC_TARGET_READ_PEC, 0, SMBUS_FALSE ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Target Write - ACK Descriptor ID to the Target Descriptor FIFO +* To inform the IP to transmit an ACK +* +*******************************************************************************/ +uint8_t ucSMBusTargetWriteDescriptorACK( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucNoStatusCheck ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + ucReturnCode = prvucSMBusTargetDescriptorApply( pxSMBusProfile, DESC_TARGET_WRITE_ACK, 0, ucNoStatusCheck ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Target Write - NACK Descriptor ID to the Target Descriptor FIFO +* To inform the IP to transmit a NACK +* +*******************************************************************************/ +uint8_t ucSMBusTargetWriteDescriptorNACK( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + ucReturnCode = prvucSMBusTargetDescriptorApply( pxSMBusProfile, DESC_TARGET_WRITE_NACK, 0, SMBUS_FALSE ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Target Write - PEC Descriptor ID to the Target Descriptor FIFO +* To inform the IP to interpret the previous byte as a PEC +* +*******************************************************************************/ +uint8_t ucSMBusTargetWriteDescriptorPEC( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + ucReturnCode = prvucSMBusTargetDescriptorApply( pxSMBusProfile, DESC_TARGET_WRITE_PEC, 0, SMBUS_FALSE ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Controller Write - START Descriptor ID to the Controller Descriptor FIFO +* To inform the IP to transmit a START condition +* +*******************************************************************************/ +uint8_t ucSMBusControllerWriteDescriptorStartWrite( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucDestination ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + /* Destination is a 7-bit address occupying bits 7:1, bit 0 is the r/W bit + This is a write so set the R/W bit to Zero */ + ucDestination = ( ucDestination << 1 ); + ucReturnCode = prvucSMBusControllerDescriptorApply( pxSMBusProfile, DESC_CONTROLLER_WRITE_START, ucDestination, SMBUS_FALSE ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Controller Write - QUICK Descriptor ID to the Controller Descriptor FIFO +* To inform the IP to transmit a START condition followed by a STOP +* +*******************************************************************************/ +uint8_t ucSMBusControllerWriteDescriptorQuickWrite( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucDestination ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + ucDestination = ( ucDestination << 1 ); + ucReturnCode = prvucSMBusControllerDescriptorApply( pxSMBusProfile, DESC_CONTROLLER_WRITE_QUICK, ucDestination, SMBUS_FALSE ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Controller Write - BYTE Descriptor ID to the Controller Descriptor FIFO +* along with a data byte +* To inform the IP to transmit the data byte +* +*******************************************************************************/ +uint8_t ucSMBusControllerWriteDescriptorByte( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucData, uint8_t ucNoStatusCheck ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + ucReturnCode = prvucSMBusControllerDescriptorApply( pxSMBusProfile, DESC_CONTROLLER_WRITE_BYTE, ucData, ucNoStatusCheck ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Controller Write - STOP Descriptor ID to the Controller Descriptor FIFO +* along with a data byte +* To inform the IP to transmit the data byte followed by a STOP condition +* +*******************************************************************************/ +uint8_t ucSMBusControllerWriteDescriptorStopWrite( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucData ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + ucReturnCode = prvucSMBusControllerDescriptorApply( pxSMBusProfile, DESC_CONTROLLER_WRITE_STOP, ucData, SMBUS_FALSE ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Controller Write - PEC Descriptor ID to the Controller Descriptor FIFO +* To inform the IP to transmit the PEC verify an ACK and then transmit a STOP +* +*******************************************************************************/ +uint8_t ucSMBusControllerWriteDescriptorPECWrite( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + ucReturnCode = prvucSMBusControllerDescriptorApply( pxSMBusProfile, DESC_CONTROLLER_WRITE_PEC, 0, SMBUS_FALSE ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Controller Read - START Descriptor ID to the Controller Descriptor FIFO +* along with Target address +* To inform the IP to start a new READ transaction +* +*******************************************************************************/ +uint8_t ucSMBusControllerReadDescriptorStart( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucDestination ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + /* Destination is a 7-bit address occupying bits 7:1, bit 0 is the r/W bit + This is a read so set the R/W bit to One */ + ucDestination = ( ucDestination << 1 ) | 0x01; + ucReturnCode = prvucSMBusControllerDescriptorApply( pxSMBusProfile, DESC_CONTROLLER_READ_START, ucDestination, SMBUS_FALSE ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Controller Read - QUICK Descriptor ID to the Controller Descriptor FIFO +* along with Target address +* To inform the IP to start a new READ transaction followed by a STOP +* +*******************************************************************************/ +uint8_t ucSMBusControllerReadDescriptorQuickRead( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucDestination ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + ucDestination = ( ucDestination << 1 ) | 0x01; + ucReturnCode = prvucSMBusControllerDescriptorApply( pxSMBusProfile, DESC_CONTROLLER_READ_QUICK, ucDestination, SMBUS_FALSE ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Controller Read - BYTE Descriptor ID to the Controller Descriptor FIFO +* To inform the IP to transmit an ACK for the previous byte received +* +*******************************************************************************/ +uint8_t ucSMBusControllerReadDescriptorByte( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucNoStatusCheck ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + ucReturnCode = prvucSMBusControllerDescriptorApply( pxSMBusProfile, DESC_CONTROLLER_READ_BYTE, 0, ucNoStatusCheck ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Controller Read - STOP Descriptor ID to the Controller Descriptor FIFO +* To inform the IP to transmit a NACK followed by a STOP condition +* +*******************************************************************************/ +uint8_t ucSMBusControllerReadDescriptorStop( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + ucReturnCode = prvucSMBusControllerDescriptorApply( pxSMBusProfile, DESC_CONTROLLER_READ_STOP, 0, SMBUS_FALSE ); + } + return ( ucReturnCode ); +} + +/******************************************************************************* +* +* @brief Writes a Controller Read - PEC Descriptor ID to the Controller Descriptor FIFO +* To inform the IP to transmit a NACK followed by a STOP and use the last received byte +* to perform a PEC check +* +*******************************************************************************/ +uint8_t ucSMBusControllerReadDescriptorPEC( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint8_t ucReturnCode = SMBUS_HW_DESCRIPTOR_WRITE_FAIL; + if( NULL != pxSMBusProfile ) + { + ucReturnCode = prvucSMBusControllerDescriptorApply( pxSMBusProfile, DESC_CONTROLLER_READ_PEC, 0, SMBUS_FALSE ); + } + return ( ucReturnCode ); +} + +/* Descriptor helper functions*/ + +/******************************************************************************* +* +* @brief Converts an Descriptor enum value to a text string for logging +* +*******************************************************************************/ +char* pcDescriptorToString( SMBus_HW_Descriptor_Type xDescriptor ) +{ + char* pResult = NULL; + + switch( xDescriptor ) + { + case DESC_TARGET_READ: + pResult = pDescriptorTargetRead; + break; + + case DESC_TARGET_READ_PEC: + pResult = pDescriptorTargetPEC; + break; + + case DESC_TARGET_WRITE_ACK: + pResult = pDescriptorTargetWriteACK; + break; + + case DESC_TARGET_WRITE_NACK: + pResult = pDescriptorTargetWriteNACK; + break; + + case DESC_TARGET_WRITE_PEC: + pResult = pDescriptorTargetWritePEC; + break; + + case DESC_CONTROLLER_READ_START: + pResult = pDescriptorControllerReadStart; + break; + + case DESC_CONTROLLER_READ_QUICK: + pResult = pDescriptorControllerReadQuick; + break; + + case DESC_CONTROLLER_READ_BYTE: + pResult = pDescriptorControllerReadByte; + break; + + case DESC_CONTROLLER_READ_STOP: + pResult = pDescriptorControllerReadStop; + break; + + case DESC_CONTROLLER_READ_PEC: + pResult = pDescriptorControllerReadPEC; + break; + + case DESC_CONTROLLER_WRITE_START: + pResult = pDescriptorControllerWriteStart; + break; + + case DESC_CONTROLLER_WRITE_QUICK: + pResult = pDescriptorControllerWriteQuick; + break; + + case DESC_CONTROLLER_WRITE_BYTE: + pResult = pDescriptorControllerWriteByte; + break; + + case DESC_CONTROLLER_WRITE_STOP: + pResult = pDescriptorControllerWriteStop; + break; + + case DESC_CONTROLLER_WRITE_PEC: + pResult = pDescriptorControllerWritePEC; + break; + + default: + pResult = pDescriptorUnknown; + break; + } + + return pResult; +} + +/****************************************************************************** +* +* @brief Return the value read form the register offset location +* +*****************************************************************************/ +static uint32_t prvulSMBusHardwareRead( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulRegisterOffset ) +{ + uint32_t ulReadValue = 0; + volatile uintptr_t xAddress = 0; + + if( NULL != pxSMBusProfile ) + { + xAddress = ( uintptr_t )( ( ( SMBUS_BASE_ADDRESS_TYPE )pxSMBusProfile->pvBaseAddress ) + ulRegisterOffset / 4 ); + ulReadValue = prvulSMBusIn32( ( void* )xAddress ); + + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_HW_READ, ( uint32_t )ulRegisterOffset, ( uint32_t )ulReadValue ); + } + + return ( ulReadValue ); +} + +/****************************************************************************** +* +* @brief Write the supplied value to the register offset location +* +*****************************************************************************/ +static void prvvSMBusHardwareWrite( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulRegisterOffset, uint32_t ulValue ) +{ + volatile uintptr_t xAddress = 0; + + if( NULL != pxSMBusProfile ) + { + xAddress = ( uintptr_t )( ( ( SMBUS_BASE_ADDRESS_TYPE )pxSMBusProfile->pvBaseAddress ) + ulRegisterOffset / 4 ); + + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_HW_WRITE, ( uint32_t )ulRegisterOffset, ( uint32_t )ulValue ); + prvvSMBusOut32( ( void* )xAddress, ulValue ); + } +} + +/****************************************************************************** +* +* @brief Modify the masked part of the register offset location with the value supplied +* +*****************************************************************************/ +static void prvvSMBusHardwareWriteWithMask( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulRegisterOffset, + uint32_t ulMask, uint32_t ulValue ) +{ + + uint32_t ulRegisterulValue = 0; + uint32_t ulMaskedulValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulRegisterulValue = prvulSMBusHardwareRead( pxSMBusProfile, ulRegisterOffset ); + ulRegisterulValue = ulRegisterulValue & ~ulMask; + ulMaskedulValue = ulValue & ulMask; + + ulRegisterulValue = ulRegisterulValue | ulMaskedulValue; + + prvvSMBusHardwareWrite( pxSMBusProfile, ulRegisterOffset, ulRegisterulValue ); + } +} + +/* SMBUS_REG_IP_VERSION */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IP_VERSION +* +*******************************************************************************/ +uint32_t ulSMBusHWReadIPVersion( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue = ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_IP_VERSION ) ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_IP_REVISION */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IP_REVISION +* +*******************************************************************************/ +uint32_t ulSMBusHWReadIPRevision( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_IP_REVISION ) ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_IP_MAGIC_NUM */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IP_MAGIC_NUM +* +*******************************************************************************/ +uint32_t ulSMBusHWReadIPMagicNum( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_IP_MAGIC_NUM ) ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_BUILD_CONFIG_0 */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_BUILD_CONFIG_0 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadBuildConfig0( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_IP_BUILD_CONFIG_0 ) ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_BUILD_CONFIG_1 */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_BUILD_CONFIG_1 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadBuildConfig1( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_IP_BUILD_CONFIG_1 ) ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_IRQ_GIE */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IRQ_GIE +* +*******************************************************************************/ +uint32_t ulSMBusHWReadIRQGIEEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_IRQ_GIE ) & SMBUS_IRQ_GIE_ENABLE_MASK ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_IRQ_IER */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IRQ_IER +* +*******************************************************************************/ +uint32_t ulSMBusHWReadIRQIER( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_IRQ_IER ) ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_IRQ_ISR */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IRQ_ISR +* +*******************************************************************************/ +uint32_t ulSMBusHWReadIRQISR( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_IRQ_ISR ) ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_IRQ_ERR_IER */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IRQ_ERR_IER +* +*******************************************************************************/ +uint32_t ulSMBusHWReadErrIRQIER( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_ERR_IRQ_IER ) ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_IRQ_ERR_ISR */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IRQ_ERR_ISR +* +*******************************************************************************/ +uint32_t ulSMBusHWReadErrIRQISR( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_ERR_IRQ_ISR ) ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_STATUS */ +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_STATUS_SMBDAT_LOW_TIMEOUT bitfield from hardware +* register SMBUS_REG_PHY_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYStatus( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_STATUS ) ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_STATUS_SMBCLK_LOW_TIMEOUT bitfield from hardware +* register SMBUS_REG_PHY_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYStatusSMBDATLowTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_STATUS ) + & SMBUS_PHY_STATUS_SMBDAT_LOW_TIMEOUT_MASK ) >> SMBUS_PHY_STATUS_SMBDAT_LOW_TIMEOUT_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_STATUS_SMBCLK_LOW_TIMEOUT bitfield from hardware +* register SMBUS_REG_PHY_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYStatusSMBClkLowTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_STATUS ) + & SMBUS_PHY_STATUS_SMBCLK_LOW_TIMEOUT_MASK ) >> SMBUS_PHY_STATUS_SMBCLK_LOW_TIMEOUT_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_STATUS_BUS_IDLE bitfield from hardware register +* SMBUS_REG_PHY_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYStatusBusIdle( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_STATUS ) & SMBUS_PHY_STATUS_BUS_IDLE_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_FILTER_CONTROL */ +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_FILTER_CONTROL_ENABLE bitfield from hardware +* register SMBUS_REG_PHY_FILTER_CONTROL +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYFilterControl( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_FILTER_CONTROL ) ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_FILTER_CONTROL_ENABLE bitfield from hardware +* register SMBUS_REG_PHY_FILTER_CONTROL +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYFilterControlEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_FILTER_CONTROL ) + & SMBUS_PHY_FILTER_CONTROL_ENABLE_MASK ) >> SMBUS_PHY_FILTER_CONTROL_ENABLE_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_FILTER_CONTROL_DURATION bitfield from hardware +* register SMBUS_REG_PHY_FILTER_CONTROL +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYFilterControlDuration( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_FILTER_CONTROL ) + & SMBUS_PHY_FILTER_CONTROL_DURATION_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_BUS_FREE_TIME */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_PHY_BUS_FREE_TIME +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYBusFreetime( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_BUS_FREE_TIME ) ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_IDLE_THRESHOLD */ +/******************************************************************************* +* +* @brief Reads the IDLE_THRESHOLD bitfield from hardware register +* SMBUS_REG_PHY_IDLE_THRESHOLD +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYIdleThresholdIdleThreshold( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_IDLE_THRESHOLD ) + & SMBUS_PHY_IDLE_THRESHOLD_IDLE_THRESHOLD_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TIMEOUT_PRESCALER */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_PHY_TIMEOUT_PRESCALER +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTimeoutPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_TIMEOUT_PRESCALER ) ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TIMEOUT_MIN */ +/******************************************************************************* +* +* @brief Reads the MIN_TIMEOUT_ENABLE bitfield from hardware register +* SMBUS_REG_PHY_TIMEOUT_MIN +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTimeoutMin( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_TIMEOUT_MIN ) ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the MIN_TIMEOUT_MIN bitfield from hardware register +* SMBUS_REG_PHY_TIMEOUT_MIN +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTimeoutMinTimeoutEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_TIMEOUT_MIN ) + & SMBUS_PHY_TIMEOUT_MIN_TIMEOUT_ENABLE_MASK ) >> SMBUS_PHY_TIMEOUT_MIN_TIMEOUT_ENABLE_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_FILTER_CONTROL_DURATION bitfield from hardware +* register SMBUS_REG_PHY_FILTER_CONTROL +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTimeoutMinTimeoutMin( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_TIMEOUT_MIN ) + & SMBUS_PHY_TIMEOUT_MIN_TIMEOUT_MIN_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TIMEOUT_MAX */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_PHY_TIMEOUT_MAX +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTimeoutMax( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_TIMEOUT_MAX ) ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_RESET_CONTROL */ +/******************************************************************************* +* +* @brief Reads the SMBCLK_FORCE_LOW bitfield from hardware register +* SMBUS_REG_PHY_RESET_CONTROL +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYResetControlSMBClkForce( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_RESET_CONTROL ) + & SMBUS_PHY_RESET_CONTROL_SMBCLK_FORCE_LOW_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TGT_DATA_SETUP */ +/******************************************************************************* +* +* @brief Reads the TGT_DATA_SETUP bitfield from hardware register +* SMBUS_REG_PHY_TGT_DATA_SETUP +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTgtDataSetupTgtDataSetup( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_TGT_DATA_SETUP ) + & SMBUS_PHY_TGT_DATA_SETUP_TGT_DATA_SETUP_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TGT_TEXT_PRESCALER */ +/******************************************************************************* +* +* @brief Reads the TGT_TEXT_PRESCALER bitfield from hardware register +* SMBUS_REG_PHY_TGT_TEXT_PRESCALER +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTgtTextPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_TGT_TEXT_PRESCALER ) + & SMBUS_PHY_TGT_TEXT_PRESCALER_TGT_TEXT_PRESCALER_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TGT_TEXT_TIMEOUT */ +/******************************************************************************* +* +* @brief Reads the TGT_TEXT_TIMEOUT bitfield from hardware register +* SMBUS_REG_PHY_TGT_TEXT_TIMEOUT +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTgtTextTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_TGT_TEXT_TIMEOUT ) + & SMBUS_PHY_TGT_TEXT_TIMEOUT_TGT_TEXT_TIMEOUT_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TGT_TEXT_MAX */ +/******************************************************************************* +* +* @brief Reads the TGT_TEXT_MAX bitfield from hardware register +* SMBUS_REG_PHY_TGT_TEXT_MAX +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTgtTextMax( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_TGT_TEXT_MAX ) + & SMBUS_PHY_TGT_TEXT_MAX_TGT_TEXT_MAX_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TGT_DBG_STATE */ +/******************************************************************************* +* +* @brief Reads the DBG_STATE bitfield from hardware register +* SMBUS_REG_PHY_TGT_DBG_STATE +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTgtDbgState( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_TGT_DBG_STATE ) + & SMBUS_PHY_TGT_DBG_STATE_DBG_STATE_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TGT_DATA_HOLD */ +/******************************************************************************* +* +* @brief Reads the DATA_HOLD bitfield from hardware register +* SMBUS_REG_PHY_TGT_DATA_HOLD +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTgtDataHold( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_TGT_DATA_HOLD ) + & SMBUS_PHY_TGT_DATA_HOLD_DATA_HOLD_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_TGT_STATUS */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_TGT_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtStatus( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_STATUS ) ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the TGT_STATUS_ACTIVE bitfield from hardware register +* SMBUS_REG_TGT_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtStatusActive( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_STATUS ) + & SMBUS_TGT_STATUS_ACTIVE_MASK ) >> SMBUS_TGT_STATUS_ACTIVE_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the TGT_STATUS_ADDRESS bitfield from hardware register +* SMBUS_REG_TGT_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtStatusAddress( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_STATUS ) + & SMBUS_TGT_STATUS_ADDRESS_MASK ) >> SMBUS_TGT_STATUS_ADDRESS_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the TGT_STATUS_RW bitfield from hardware register +* SMBUS_REG_TGT_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtStatusRW( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_STATUS ) + & SMBUS_TGT_STATUS_RW_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_TGT_DESC_STATUS */ +/******************************************************************************* +* +* @brief Reads the FILL_LEVEL bitfield from hardware register +* SMBUS_REG_TGT_DESC_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtDescStatusFillLevel( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_DESC_STATUS ) + & SMBUS_TGT_DESC_STATUS_FILL_LEVEL_MASK ) >> SMBUS_TGT_DESC_STATUS_FILL_LEVEL_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the FULL bitfield from hardware register +* SMBUS_REG_TGT_DESC_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtDescStatusFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_DESC_STATUS ) + & SMBUS_TGT_DESC_STATUS_FULL_MASK ) >> SMBUS_TGT_DESC_STATUS_FULL_FIELD_POSITION ); + } + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ALMOST_FULL bitfield from hardware register +* SMBUS_REG_TGT_DESC_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtDescStatusAlmostFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_DESC_STATUS ) + & SMBUS_TGT_DESC_STATUS_ALMOST_FULL_MASK ) >> SMBUS_TGT_DESC_STATUS_ALMOST_FULL_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ALMOST_EMPTY bitfield from hardware register +* SMBUS_REG_TGT_DESC_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtDescStatusAlmostEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_DESC_STATUS ) + & SMBUS_TGT_DESC_STATUS_ALMOST_EMPTY_MASK ) >> SMBUS_TGT_DESC_STATUS_ALMOST_EMPTY_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the EMPTY bitfield from hardware register +* SMBUS_REG_TGT_DESC_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtDescStatusEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_DESC_STATUS ) + & SMBUS_TGT_DESC_STATUS_EMPTY_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_TGT_RX_FIFO */ +/******************************************************************************* +* +* @brief Reads the PAYLOAD bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoPayload( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_RX_FIFO ) + & SMBUS_TGT_RX_FIFO_PAYLOAD_MASK ) >> SMBUS_TGT_RX_FIFO_PAYLOAD_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_TGT_RX_FIFO_STATUS */ +/******************************************************************************* +* +* @brief Reads the FILL_LEVEL bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoStatusFillLevel( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_RX_FIFO_STATUS ) + & SMBUS_TGT_RX_FIFO_STATUS_FILL_LEVEL_MASK ) >> SMBUS_TGT_RX_FIFO_STATUS_FILL_LEVEL_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the RESET_BUSY bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoStatusResetBusY( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_RX_FIFO_STATUS ) + & SMBUS_TGT_RX_FIFO_STATUS_RESET_BUSY_MASK ) >> SMBUS_TGT_RX_FIFO_STATUS_RESET_BUSY_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the FULL bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoStatusFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_RX_FIFO_STATUS ) + & SMBUS_TGT_RX_FIFO_STATUS_FULL_MASK ) >> SMBUS_TGT_RX_FIFO_STATUS_FULL_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ALMOST_FULL bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoStatusAlmostFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_RX_FIFO_STATUS ) + & SMBUS_TGT_RX_FIFO_STATUS_ALMOST_FULL_MASK ) >> SMBUS_TGT_RX_FIFO_STATUS_ALMOST_FULL_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ALMOST_EMPTY bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoStatusAlmostEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_RX_FIFO_STATUS ) + & SMBUS_TGT_RX_FIFO_STATUS_ALMOST_EMPTY_MASK ) >> SMBUS_TGT_RX_FIFO_STATUS_ALMOST_EMPTY_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the EMPTY bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoStatusEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_RX_FIFO_STATUS ) + & SMBUS_TGT_RX_FIFO_STATUS_EMPTY_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_TGT_RX_FIFO_FILL_THRESHOLD */ +/******************************************************************************* +* +* @brief Reads the FILL_THRESHOLD bitfield from hardware register +* SMBUS_REG_TGT_RX_FIFO_FILL_THRESHOLD +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoFillThresholdFillThresh( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_RX_FIFO_FILL_THRESHOLD ) + & SMBUS_TGT_RX_FIFO_FILL_THRESHOLD_FILL_THRESHOLD_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_TGT_DBG */ +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_TGT_DBG +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtDbg( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_DBG ) + & SMBUS_TGT_DBG_DBG_STATE_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_TGT_CONTROL_0 */ +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_0 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl0Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_0 ) + & SMBUS_TGT_CONTROL_0_ENABLE_MASK ) >> SMBUS_TGT_CONTROL_0_ENABLE_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_0 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl0Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_0 ) + & SMBUS_TGT_CONTROL_0_ADDRESS_MASK ) >> SMBUS_TGT_CONTROL_0_ADDRESS_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_TGT_CONTROL_1 */ +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_1 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl1Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_1 ) + & SMBUS_TGT_CONTROL_1_ENABLE_MASK ) >> SMBUS_TGT_CONTROL_1_ENABLE_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_1 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl1Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_1 ) + & SMBUS_TGT_CONTROL_1_ADDRESS_MASK ) >> SMBUS_TGT_CONTROL_1_ADDRESS_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_TGT_CONTROL_2 */ +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_2 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl2Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_2 ) + & SMBUS_TGT_CONTROL_2_ENABLE_MASK ) >> SMBUS_TGT_CONTROL_2_ENABLE_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_2 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl2Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_2 ) + & SMBUS_TGT_CONTROL_2_ADDRESS_MASK ) >> SMBUS_TGT_CONTROL_2_ADDRESS_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_TGT_CONTROL_3 */ +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_3 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl3Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_3 ) + & SMBUS_TGT_CONTROL_3_ENABLE_MASK ) >> SMBUS_TGT_CONTROL_3_ENABLE_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_3 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl3Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_3 ) + & SMBUS_TGT_CONTROL_3_ADDRESS_MASK ) >> SMBUS_TGT_CONTROL_3_ADDRESS_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_TGT_CONTROL_4 */ +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_4 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl4Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_4 ) + & SMBUS_TGT_CONTROL_4_ENABLE_MASK ) >> SMBUS_TGT_CONTROL_4_ENABLE_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_4 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl4Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_4 ) + & SMBUS_TGT_CONTROL_4_ADDRESS_MASK ) >> SMBUS_TGT_CONTROL_4_ADDRESS_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_TGT_CONTROL_5 */ +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_5 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl5Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_5 ) + & SMBUS_TGT_CONTROL_5_ENABLE_MASK ) >> SMBUS_TGT_CONTROL_5_ENABLE_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_5 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl5Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_5 ) + & SMBUS_TGT_CONTROL_5_ADDRESS_MASK ) >> SMBUS_TGT_CONTROL_5_ADDRESS_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_TGT_CONTROL_6 */ +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_6 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl6Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_6 ) + & SMBUS_TGT_CONTROL_6_ENABLE_MASK ) >> SMBUS_TGT_CONTROL_6_ENABLE_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_6 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl6Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_6 ) + & SMBUS_TGT_CONTROL_6_ADDRESS_MASK ) >> SMBUS_TGT_CONTROL_6_ADDRESS_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/* SMBUS_REG_TGT_CONTROL_7 */ +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_7 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl7Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_7 ) + & SMBUS_TGT_CONTROL_7_ENABLE_MASK ) >> SMBUS_TGT_CONTROL_7_ENABLE_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_7 +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl7Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_7 ) + & SMBUS_TGT_CONTROL_7_ADDRESS_MASK ) >> SMBUS_TGT_CONTROL_7_ADDRESS_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_DATA_HOLD */ +/******************************************************************************* +* +* @brief Reads the DATA_HOLD bitfield from hardware register +* SMBUS_REG_PHY_CTLR_DATA_HOLD +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlDataHold( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_DATA_HOLD ) + & SMBUS_PHY_CTLR_DATA_HOLD_CTLR_DATA_HOLD_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_START_HOLD */ +/******************************************************************************* +* +* @brief Reads the START_HOLD bitfield from hardware register +* SMBUS_REG_PHY_CTLR_START_HOLD +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlStartHold( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_START_HOLD ) + & SMBUS_PHY_CTLR_START_HOLD_CTLR_START_HOLD_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_START_SETUP */ +/******************************************************************************* +* +* @brief Reads the START_SETUP bitfield from hardware register +* SMBUS_REG_PHY_CTLR_START_SETUP +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlStartSetup( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_START_SETUP ) + & SMBUS_PHY_CTLR_START_SETUP_CTLR_START_SETUP_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_STOP_SETUP */ +/******************************************************************************* +* +* @brief Reads the STOP_SETUP bitfield from hardware register +* SMBUS_REG_PHY_CTLR_STOP_SETUP +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlStopSetup( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_STOP_SETUP ) + & SMBUS_PHY_CTLR_STOP_SETUP_CTLR_STOP_SETUP_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_CLK_TLOW */ +/******************************************************************************* +* +* @brief Reads the CLK_TLOW bitfield from hardware register +* SMBUS_REG_PHY_CTLR_CLK_TLOW +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlClkTLow( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_CLK_TLOW ) + & SMBUS_PHY_CTLR_CLK_TLOW_CTLR_CLK_TLOW_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_CLK_THIGH */ +/******************************************************************************* +* +* @brief Reads the CLK_THIGH bitfield from hardware register +* SMBUS_REG_PHY_CTLR_CLK_THIGH +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlClkTHigh( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_CLK_THIGH ) + & SMBUS_PHY_CTLR_CLK_THIGH_CTLR_CLK_THIGH_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_TEXT_PRESCALER */ +/******************************************************************************* +* +* @brief Reads the TEXT_PRESCALER bitfield from hardware register +* SMBUS_REG_PHY_CTLR_TEXT_PRESCALER +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlTextPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_TEXT_PRESCALER ) + & SMBUS_PHY_CTLR_TEXT_PRESCALER_CTLR_TEXT_PRESCALER_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_TEXT_TIMEOUT */ +/******************************************************************************* +* +* @brief Reads the TEXT_TIMEOUT bitfield from hardware register +* SMBUS_REG_PHY_CTLR_TEXT_TIMEOUT +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlTextTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_TEXT_TIMEOUT ) + & SMBUS_PHY_CTLR_TEXT_TIMEOUT_CTLR_TEXT_TIMEOUT_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_TEXT_MAX */ +/******************************************************************************* +* +* @brief Reads the TEXT_MAX bitfield from hardware register +* SMBUS_REG_PHY_CTLR_TEXT_MAX +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlTextMax( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_TEXT_MAX ) + & SMBUS_PHY_CTLR_TEXT_MAX_CTLR_TEXT_MAX_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_CEXT_PRESCALER */ +/******************************************************************************* +* +* @brief Reads the CEXT_PRESCALER bitfield from hardware register +* SMBUS_REG_PHY_CTLR_CEXT_PRESCALER +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlCextPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_CEXT_PRESCALER ) + & SMBUS_PHY_CTLR_CEXT_PRESCALER_CTLR_CEXT_PRESCALER_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_CEXT_TIMEOUT */ +/******************************************************************************* +* +* @brief Reads the CEXT_TIMEOUT bitfield from hardware register +* SMBUS_REG_PHY_CTLR_CEXT_TIMEOUT +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlCextTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_CEXT_TIMEOUT ) + & SMBUS_PHY_CTLR_CEXT_TIMEOUT_CTLR_CEXT_TIMEOUT_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_CEXT_MAX */ +/******************************************************************************* +* +* @brief Reads the CEXT_MAX bitfield from hardware register +* SMBUS_REG_PHY_CTLR_CEXT_MAX +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlCextMax( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_CEXT_MAX ) + & SMBUS_PHY_CTLR_CEXT_MAX_CTLR_CEXT_MAX_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_DBG_STATE */ +/******************************************************************************* +* +* @brief Reads the DBG_STATE bitfield from hardware register +* SMBUS_REG_PHY_CTLR_DBG_STATE +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlDbgState( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_PHY_CTLR_DBG_STATE ) + & SMBUS_PHY_CTLR_DBG_STATE_DBG_STATE_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_CTLR_STATUS */ +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_CTLR_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlStatusEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_STATUS ) + & SMBUS_CTLR_STATUS_ENABLE_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_CTLR_DESC_STATUS */ +/******************************************************************************* +* +* @brief Reads the FILL_LEVEL bitfield from hardware register +* SMBUS_REG_CTLR_DESC_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDescStatusFillLevel( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_DESC_STATUS ) + & SMBUS_CTLR_DESC_STATUS_FILL_LEVEL_MASK ) >> SMBUS_CTLR_DESC_STATUS_FILL_LEVEL_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the RESET_BUSY bitfield from hardware register +* SMBUS_REG_CTLR_DESC_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDescStatusResetBusy( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_DESC_STATUS ) + & SMBUS_CTLR_DESC_STATUS_RESET_BUSY_MASK ) >> SMBUS_CTLR_DESC_STATUS_RESET_BUSY_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the FULL bitfield from hardware register +* SMBUS_REG_CTLR_DESC_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDescStatusFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_DESC_STATUS ) + & SMBUS_CTLR_DESC_STATUS_FULL_MASK ) >> SMBUS_CTLR_DESC_STATUS_FULL_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ALMOST_FULL bitfield from hardware register +* SMBUS_REG_CTLR_DESC_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDescStatusAlmostFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_DESC_STATUS ) + & SMBUS_CTLR_DESC_STATUS_ALMOST_FULL_MASK ) >> SMBUS_CTLR_DESC_STATUS_ALMOST_FULL_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ALMOST_EMPTY bitfield from hardware register +* SMBUS_REG_CTLR_DESC_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDescStatusAlmostEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_DESC_STATUS ) + & SMBUS_CTLR_DESC_STATUS_ALMOST_EMPTY_MASK ) >> SMBUS_CTLR_DESC_STATUS_ALMOST_EMPTY_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the EMPTY bitfield from hardware register +* SMBUS_REG_CTLR_DESC_STATUS +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDescStatusEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_DESC_STATUS ) + & SMBUS_CTLR_DESC_STATUS_EMPTY_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_CTLR_RX_FIFO */ +/******************************************************************************* +* +* @brief Reads the PAYLOAD bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoPayload( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_RX_FIFO ) + & SMBUS_CTLR_RX_FIFO_PAYLOAD_MASK ) >> SMBUS_CTLR_RX_FIFO_PAYLOAD_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_CTLR_RX_FIFO_STATUS */ +/******************************************************************************* +* +* @brief Reads the FILL_LEVEL bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoStatusFillLevel( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_RX_FIFO_STATUS ) + & SMBUS_CTLR_RX_FIFO_STATUS_FILL_LEVEL_MASK ) >> SMBUS_CTLR_RX_FIFO_STATUS_FILL_LEVEL_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the RESET_BUSY bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoStatusResetBusy( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_RX_FIFO_STATUS ) + & SMBUS_CTLR_RX_FIFO_STATUS_RESET_BUSY_MASK ) >> SMBUS_CTLR_RX_FIFO_STATUS_RESET_BUSY_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the FULL bitfield from hardware register SMBUS_REG_CTLR_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoStatusFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_RX_FIFO_STATUS ) + & SMBUS_CTLR_RX_FIFO_STATUS_FULL_MASK ) >> SMBUS_CTLR_RX_FIFO_STATUS_FULL_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ALMOST_FULL bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoStatusAlmostFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_RX_FIFO_STATUS ) + & SMBUS_CTLR_RX_FIFO_STATUS_ALMOST_FULL_MASK ) >> SMBUS_CTLR_RX_FIFO_STATUS_ALMOST_FULL_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the ALMOST_EMPTY bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoStatusAlmostEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( ( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_RX_FIFO_STATUS ) + & SMBUS_CTLR_RX_FIFO_STATUS_ALMOST_EMPTY_MASK ) >> SMBUS_CTLR_RX_FIFO_STATUS_ALMOST_EMPTY_FIELD_POSITION ); + } + + return( ulReadValue ); +} + +/******************************************************************************* +* +* @brief Reads the EMPTY bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoStatusEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_RX_FIFO_STATUS ) + & SMBUS_CTLR_RX_FIFO_STATUS_EMPTY_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_CTLR_RX_FIFO_FILL_THRESHOLD */ +/******************************************************************************* +* +* @brief Reads the THRESHOLD bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO_FILL_THRESHOLD +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoFillThresholdFillThresh( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_RX_FIFO_FILL_THRESHOLD ) + & SMBUS_CTLR_RX_FIFO_FILL_THRESHOLD_FILL_THRESHOLD_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_CTLR_DBG_STATE */ +/******************************************************************************* +* +* @brief Reads the DBG_STATE bitfield from hardware register +* SMBUS_REG_CTLR_DBG +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDbgState( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint32_t ulReadValue = 0; + + if( NULL != pxSMBusProfile ) + { + ulReadValue =( prvulSMBusHardwareRead( pxSMBusProfile, SMBUS_REG_CTLR_DBG ) + & SMBUS_CTLR_DBG_DBG_STATE_MASK ); + } + + return( ulReadValue ); +} + +/******************************************************************************************************************/ + +/******************************************************************************************************************/ +/* Write Functions */ +/******************************************************************************************************************/ + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_IRQ_GIE +* +*******************************************************************************/ +void vSMBusHWWriteIRQGIEEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_IRQ_GIE, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_IRQ_IER */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_IRQ_IER +* +*******************************************************************************/ +void vSMBusHWWriteIRQIER( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_IRQ_IER, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_IRQ_ISR */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_IRQ_ISR +* +*******************************************************************************/ +void vSMBusHWWriteIRQISR( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_IRQ_ISR, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_ERR_IRQ_IER */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_ERR_IRQ_IER +* +*******************************************************************************/ +void vSMBusHWWriteERRIRQIER( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_ERR_IRQ_IER, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_ERR_IRQ_ISR */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_ERR_IRQ_ISR +* +*******************************************************************************/ +void vSMBusHWWriteERRIRQISR( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_ERR_IRQ_ISR, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_FILTER_CONTROL */ +/******************************************************************************* +* +* @brief Writes ulValue to ENABLE bitfield of hardware register +* SMBUS_REG_PHY_FILTER_CONTROL +* +*******************************************************************************/ +void vSMBusHWWritePHYFilterControlEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_PHY_FILTER_CONTROL_ENABLE_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_PHY_FILTER_CONTROL, SMBUS_PHY_FILTER_CONTROL_ENABLE_MASK, ulValue ); + } +} + +/******************************************************************************* +* +* @brief Writes ulValue to DURATION bitfield of hardware register +* SMBUS_REG_PHY_FILTER_CONTROL +* +*******************************************************************************/ +void vSMBusHWWritePHYFilterControlDuration( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_PHY_FILTER_CONTROL, SMBUS_PHY_FILTER_CONTROL_DURATION_MASK, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_BUS_FREE_TIME */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_BUS_FREE_TIME +* +*******************************************************************************/ +void vSMBusHWWritePHYBusFreetime( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_BUS_FREE_TIME, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_IDLE_THRESHOLD */ +/******************************************************************************* +* +* @brief Writes ulValue to IDLE_THRESHOLD bitfield of hardware register +* SMBUS_REG_PHY_IDLE_THRESHOLD +* +*******************************************************************************/ +void vSMBusHWWritePHYIdleThresholdIdleThreshold( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_PHY_IDLE_THRESHOLD, + SMBUS_PHY_IDLE_THRESHOLD_IDLE_THRESHOLD_MASK, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TIMEOUT_PRESCALER */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TIMEOUT_PRESCALER +* +*******************************************************************************/ +void vSMBusHWWritePHYTimeoutPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_TIMEOUT_PRESCALER, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TIMEOUT_MIN */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TIMEOUT_MIN +* +*******************************************************************************/ +void vSMBusHWWritePHYTimeoutMin( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_TIMEOUT_MIN, ulValue ); + } +} + +/******************************************************************************* +* +* @brief Writes ulValue to ENABLE bitfield of hardware register +* SMBUS_REG_PHY_TIMEOUT_MIN +* +*******************************************************************************/ +void vSMBusHWWritePHYTimeoutMinTimeoutEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_PHY_TIMEOUT_MIN_TIMEOUT_ENABLE_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_PHY_TIMEOUT_MIN, SMBUS_PHY_TIMEOUT_MIN_TIMEOUT_ENABLE_MASK, ulValue ); + } +} + +/******************************************************************************* +* +* @brief Writes ulValue to TIMEOUT_MIN bitfield of hardware register +* SMBUS_REG_PHY_TIMEOUT_MIN +* +*******************************************************************************/ +void vSMBusHWWritePHYTimeoutMinTimeoutMin( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_PHY_TIMEOUT_MIN, SMBUS_PHY_TIMEOUT_MIN_TIMEOUT_MIN_MASK, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TIMEOUT_MAX */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TIMEOUT_MAX +* +*******************************************************************************/ +void vSMBusHWWritePHYTimeoutMax( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_TIMEOUT_MAX, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_RESET_CONTROL */ +/******************************************************************************* +* +* @brief Writes ulValue to SMBCLK_FORCE_TIMEOUT bitfield of hardware register +* SMBUS_REG_PHY_RESET_CONTROL +* +*******************************************************************************/ +void vSMBusHWWritePHYResetControlSMBClkForceTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_PHY_RESET_CONTROL_SMBCLK_FORCE_TIMEOUT_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_PHY_RESET_CONTROL, + SMBUS_PHY_RESET_CONTROL_SMBCLK_FORCE_TIMEOUT_MASK, ulValue ); + } +} + +/******************************************************************************* +* +* @brief Writes ulValue to SMBCLK_FORCE_LOW bitfield of hardware register +* SMBUS_REG_PHY_RESET_CONTROL +* +*******************************************************************************/ +void vSMBusHWWritePHYResetControlSMBClkForceLow( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_PHY_RESET_CONTROL, + SMBUS_PHY_RESET_CONTROL_SMBCLK_FORCE_LOW_MASK, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TGT_DATA_SETUP */ +/******************************************************************************* +* +* @brief Writes ulValue to TGT_DATA_SETUP bitfield of hardware register +* SMBUS_REG_PHY_TGT_DATA_SETUP +* +*******************************************************************************/ +void vSMBusHWWritePHYTgtDataSetupTgtDataSetup( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_PHY_TGT_DATA_SETUP, + SMBUS_PHY_TGT_DATA_SETUP_TGT_DATA_SETUP_MASK, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TGT_TEXT_PRESCALER */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TGT_TEXT_PRESCALER +* +*******************************************************************************/ +void vSMBusHWWritePHYTgtTextPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_TGT_TEXT_PRESCALER, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TGT_TEXT_TIMEOUT */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TGT_TEXT_TIMEOUT +* +*******************************************************************************/ +void vSMBusHWWritePHYTgtTextTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_TGT_TEXT_TIMEOUT, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TGT_TEXT_MAX */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TGT_TEXT_MAX +* +*******************************************************************************/ +void vSMBusHWWritePHYTgtTextMax( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_TGT_TEXT_MAX, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_TGT_DATA_HOLD */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TGT_DATA_HOLD +* +*******************************************************************************/ +void vSMBusHWWritePHYTgtDataHold( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_TGT_DATA_HOLD, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_TGT_DESC_FIFO */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_TGT_DESC_FIFO +* +*******************************************************************************/ +void vSMBusHWWriteTgtDescFifo( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_TGT_DESC_FIFO, ulValue ); + } +} + +/******************************************************************************* +* +* @brief Writes ulValue to FIFO_ID bitfield of hardware register +* SMBUS_REG_TGT_DESC_FIFO +* +*******************************************************************************/ +void vSMBusHWWriteTgtDescFifoId( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_DESC_FIFO_ID_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_DESC_FIFO, SMBUS_TGT_DESC_FIFO_ID_MASK, ulValue ); + } +} + +/******************************************************************************* +* +* @brief Writes ulValue to PAYLOAD bitfield of hardware register +* SMBUS_REG_TGT_DESC_FIFO +* +*******************************************************************************/ +void vSMBusHWWriteTgtDescFifoPayload( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_DESC_FIFO, SMBUS_TGT_DESC_FIFO_PAYLOAD_MASK, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_TGT_RX_FIFO */ +/******************************************************************************* +* +* @brief Writes ulValue to RESET bitfield of hardware register +* SMBUS_REG_TGT_RX_FIFO +* +*******************************************************************************/ +void vSMBusHWWriteTgtRxFifoReset( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_RX_FIFO_RESET_FIELD_POSITION; + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_TGT_RX_FIFO, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_TGT_RX_FIFO_FILL_THRESHOLD */ +/******************************************************************************* +* +* @brief Writes ulValue to THRESHOLD bitfield of hardware register +* SMBUS_REG_TGT_RX_FIFO_FILL_THRESHOLD +* +*******************************************************************************/ +void vSMBusHWWriteRxFifoFillThresholdFillThresh( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_TGT_RX_FIFO_FILL_THRESHOLD, + ( SMBUS_TGT_RX_FIFO_FILL_THRESHOLD_FILL_THRESHOLD_MASK & ulValue ) ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_TGT_CONTROL_0 */ +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_0 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl0Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_0_ENABLE_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_0, SMBUS_TGT_CONTROL_0_ENABLE_MASK, ulValue ); + } +} + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_0 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl0Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_0_ADDRESS_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_0, SMBUS_TGT_CONTROL_0_ADDRESS_MASK, ulValue ); + } +} + +/* SMBUS_REG_TGT_CONTROL_1 */ +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_1 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl1Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_1_ENABLE_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_1, SMBUS_TGT_CONTROL_1_ENABLE_MASK, ulValue ); + } +} + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_1 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl1Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_1_ADDRESS_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_1, SMBUS_TGT_CONTROL_1_ADDRESS_MASK, ulValue ); + } +} + +/* SMBUS_REG_TGT_CONTROL_2 */ +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_2 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl2Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_2_ENABLE_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_2, SMBUS_TGT_CONTROL_2_ENABLE_MASK, ulValue ); + } +} + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_2 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl2Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_2_ADDRESS_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_2, SMBUS_TGT_CONTROL_2_ADDRESS_MASK, ulValue ); + } +} + +/* SMBUS_REG_TGT_CONTROL_3 */ +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_3 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl3Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_3_ENABLE_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_3, SMBUS_TGT_CONTROL_3_ENABLE_MASK, ulValue ); + } +} + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_3 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl3Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_3_ADDRESS_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_3, SMBUS_TGT_CONTROL_3_ADDRESS_MASK, ulValue ); + } +} + +/* SMBUS_REG_TGT_CONTROL_4 */ +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_4 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl4Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_4_ENABLE_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_4, SMBUS_TGT_CONTROL_4_ENABLE_MASK, ulValue ); + } +} + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_4 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl4Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_4_ADDRESS_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_4, SMBUS_TGT_CONTROL_4_ADDRESS_MASK, ulValue ); + } +} + +/* SMBUS_REG_TGT_CONTROL_5 */ +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_5 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl5Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_5_ENABLE_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_5, SMBUS_TGT_CONTROL_5_ENABLE_MASK, ulValue ); + } +} + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_5 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl5Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_5_ADDRESS_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_5, SMBUS_TGT_CONTROL_5_ADDRESS_MASK, ulValue ); + } +} + +/* SMBUS_REG_TGT_CONTROL_6 */ +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_6 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl6Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_6_ENABLE_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_6, SMBUS_TGT_CONTROL_6_ENABLE_MASK, ulValue ); + } +} + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_6 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl6Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_6_ADDRESS_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_6, SMBUS_TGT_CONTROL_6_ADDRESS_MASK, ulValue ); + } +} + +/* SMBUS_REG_TGT_CONTROL_7 */ +/****************************************************************************** +* +* @brief Write ulValue to the ENABLE bitfield of the SMBUS_REG_TGT_CONTROL_7 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl7Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_7_ENABLE_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_7, SMBUS_TGT_CONTROL_7_ENABLE_MASK, ulValue ); + } +} + +/****************************************************************************** +* +* @brief Write ulValue to the ADDRESS bitfield of the SMBUS_REG_TGT_CONTROL_7 +* register +* +*****************************************************************************/ +static void prvvSMBusHWWriteTgtControl7Address( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_TGT_CONTROL_7_ADDRESS_FIELD_POSITION; + prvvSMBusHardwareWriteWithMask( pxSMBusProfile, SMBUS_REG_TGT_CONTROL_7, SMBUS_TGT_CONTROL_7_ADDRESS_MASK, ulValue ); + } +} + +/******************************************************************************* +* +* @brief Passes the ulValue to the desired TgtControl register dependent +* on the instance value +* +*******************************************************************************/ +void vSMBusHWWriteTgtControlAddress( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucInstance, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + switch( ucInstance ) + { + case 0: + prvvSMBusHWWriteTgtControl0Address( pxSMBusProfile, ulValue ); + break; + + case 1: + prvvSMBusHWWriteTgtControl1Address( pxSMBusProfile, ulValue ); + break; + + case 2: + prvvSMBusHWWriteTgtControl2Address( pxSMBusProfile, ulValue ); + break; + + case 3: + prvvSMBusHWWriteTgtControl3Address( pxSMBusProfile, ulValue ); + break; + + case 4: + prvvSMBusHWWriteTgtControl4Address( pxSMBusProfile, ulValue ); + break; + + case 5: + prvvSMBusHWWriteTgtControl5Address( pxSMBusProfile, ulValue ); + break; + + case 6: + prvvSMBusHWWriteTgtControl6Address( pxSMBusProfile, ulValue ); + break; + + case 7: + prvvSMBusHWWriteTgtControl7Address( pxSMBusProfile, ulValue ); + break; + + default: + break; + } + } +} + +/******************************************************************************* +* +* @brief Passes the ulValue to the desired TgtControl register dependent +* on the instance value +* +*******************************************************************************/ +void vSMBusHWWriteTgtControlEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucInstance, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + switch( ucInstance ) + { + case 0: + prvvSMBusHWWriteTgtControl0Enable( pxSMBusProfile, ulValue ); + break; + + case 1: + prvvSMBusHWWriteTgtControl1Enable( pxSMBusProfile, ulValue ); + break; + + case 2: + prvvSMBusHWWriteTgtControl2Enable( pxSMBusProfile, ulValue ); + break; + + case 3: + prvvSMBusHWWriteTgtControl3Enable( pxSMBusProfile, ulValue ); + break; + + case 4: + prvvSMBusHWWriteTgtControl4Enable( pxSMBusProfile, ulValue ); + break; + + case 5: + prvvSMBusHWWriteTgtControl5Enable( pxSMBusProfile, ulValue ); + break; + + case 6: + prvvSMBusHWWriteTgtControl6Enable( pxSMBusProfile, ulValue ); + break; + + case 7: + prvvSMBusHWWriteTgtControl7Enable( pxSMBusProfile, ulValue ); + break; + + default: + break; + } + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_DATA_HOLD */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_DATA_HOLD +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlDataHold( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_CTLR_DATA_HOLD, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_START_HOLD */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_START_HOLD +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlStartHold( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_CTLR_START_HOLD, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_START_SETUP */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_START_SETUP +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlStartSetup( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_CTLR_START_SETUP, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_STOP_SETUP */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_STOP_SETUP +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlStopSetup( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_CTLR_STOP_SETUP, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_CLK_TLOW */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_CLK_TLOW +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlClkTLow( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_CTLR_CLK_TLOW, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_CLK_THIGH */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_CLK_THIGH +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlClkTHigh( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_CTLR_CLK_THIGH, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_TEXT_PRESCALER */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_TEXT_PRESCALER +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlTextPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_CTLR_TEXT_PRESCALER, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_TEXT_TIMEOUT */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_TEXT_TIMEOUT +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlTextTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_CTLR_TEXT_TIMEOUT, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_TEXT_MAX */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_TEXT_MAX +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlTextMax( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_CTLR_TEXT_MAX, ulValue ); + } +} + +/******************************************************************************************************************/ +/* SMBUS_REG_PHY_CTLR_CEXT_PRESCALER */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_CEXT_PRESCALER +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlCextPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_CTLR_CEXT_PRESCALER, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_CEXT_TIMEOUT */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_CEXT_TIMEOUT +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlCextTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_CTLR_CEXT_TIMEOUT, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_PHY_CTLR_CEXT_MAX */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_CEXT_MAX +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlCextMax( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_PHY_CTLR_CEXT_MAX, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_CTLR_CONTROL */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_CTLR_CONTROL +* +*******************************************************************************/ +void vSMBusHWWriteCtrlControlEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_CTLR_CONTROL, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_CTLR_DESC_FIFO */ +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_CTLR_DESC_FIFO +* +*******************************************************************************/ +void vSMBusHWWriteCtrlDescFifo( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_CTLR_DESC_FIFO, ulValue ); + } +} + +/******************************************************************************* +* +* @brief Writes ulValue to RESET bitfield of hardware register SMBUS_REG_CTLR_DESC_FIFO +* +*******************************************************************************/ +void vSMBusHWWriteCtrlDescFifoReset( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_CTLR_DESC_FIFO_RESET_FIELD_POSITION; + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_CTLR_DESC_FIFO, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_CTLR_RX_FIFO */ +/******************************************************************************* +* +* @brief Writes ulValue to RESET bitfield of hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +*******************************************************************************/ +void vSMBusHWWriteCtrlRxFifoReset( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + ulValue = ulValue << SMBUS_CTLR_RX_FIFO_RESET_FIELD_POSITION; + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_CTLR_RX_FIFO, ulValue ); + } +} + +/******************************************************************************************************************/ + +/* SMBUS_REG_CTLR_RX_FIFO_FILL_THRESHOLD */ +/******************************************************************************* +* +* @brief Writes ulValue to FILL_THRESHOLD bitfield of hardware register +* SMBUS_REG_CTLR_RX_FIFO_FILL_THRESHOLD +* +*******************************************************************************/ +void vSMBusHWWriteCtrlRxFifoFillThreshold( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ) +{ + if( NULL != pxSMBusProfile ) + { + prvvSMBusHardwareWrite( pxSMBusProfile, SMBUS_REG_CTLR_RX_FIFO_FILL_THRESHOLD, + ( SMBUS_CTLR_RX_FIFO_FILL_THRESHOLD_FILL_THRESHOLD_MASK & ulValue ) ); + } +} diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_hardware_access.h b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_hardware_access.h new file mode 100755 index 00000000..9a0661c9 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_hardware_access.h @@ -0,0 +1,2229 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the SMBus IP register offsets and bit mask defintions + * for the SMBus driver. + * + * @file smbus_hardware_access.h + * + */ + +#ifndef _SMBus_HARDWARE_ACCESS_H_ +#define _SMBus_HARDWARE_ACCESS_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "smbus.h" +#include "smbus_internal.h" +#include "smbus_hardware.h" + +#define SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS ( 0 ) +#define SMBUS_HW_DESCRIPTOR_WRITE_FAIL ( 1 ) + +typedef volatile int* SMBUS_BASE_ADDRESS_TYPE; + +typedef enum SMBus_HW_Descriptor_Type +{ + DESC_TARGET_READ = 0, + DESC_TARGET_READ_PEC, + DESC_TARGET_WRITE_ACK, + DESC_TARGET_WRITE_NACK, + DESC_TARGET_WRITE_PEC, + DESC_CONTROLLER_READ_START, + DESC_CONTROLLER_READ_QUICK, + DESC_CONTROLLER_READ_BYTE, + DESC_CONTROLLER_READ_STOP, + DESC_CONTROLLER_READ_PEC, + DESC_CONTROLLER_WRITE_START, + DESC_CONTROLLER_WRITE_QUICK, + DESC_CONTROLLER_WRITE_BYTE, + DESC_CONTROLLER_WRITE_STOP, + DESC_CONTROLLER_WRITE_PEC, + DESC_MAX + +} SMBus_HW_Descriptor_Type; + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IP_VERSION +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadIPVersion( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IP_REVISION +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadIPRevision( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IP_MAGIC_NUM +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadIPMagicNum( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IP_BUILD_CONFIG_0 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadBuildConfig0( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IP_BUILD_CONFIG_1 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadBuildConfig1( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the GIE_ENABLE bitfield from hardware register SMBUS_REG_IRQ_GIE +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadIRQGIEEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IRQ_IER +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadIRQIER( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_IRQ_ISR +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadIRQISR( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_ERR_IRQ_IER +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadErrIRQIER( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_ERR_IRQ_ISR +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadErrIRQISR( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_PHY_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYStatus( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_STATUS_SMBDAT_LOW_TIMEOUT bitfield from hardware +* register SMBUS_REG_PHY_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYStatusSMBDATLowTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_STATUS_SMBCLK_LOW_TIMEOUT bitfield from hardware +* register SMBUS_REG_PHY_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYStatusSMBClkLowTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_STATUS_BUS_IDLE bitfield from hardware register +* SMBUS_REG_PHY_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYStatusBusIdle( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_PHY_FILTER_CONTROL +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYFilterControl( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_FILTER_CONTROL_ENABLE bitfield from hardware +* register SMBUS_REG_PHY_FILTER_CONTROL +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYFilterControlEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the SMBUS_PHY_FILTER_CONTROL_DURATION bitfield from hardware +* register SMBUS_REG_PHY_FILTER_CONTROL +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYFilterControlDuration( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_PHY_BUS_FREE_TIME +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYBusFreetime( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the IDLE_THRESHOLD bitfield from hardware register +* SMBUS_REG_PHY_IDLE_THRESHOLD +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYIdleThresholdIdleThreshold( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_PHY_TIMEOUT_PRESCALER +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTimeoutPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_PHY_TIMEOUT_MIN +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTimeoutMin( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the MIN_TIMEOUT_ENABLE bitfield from hardware register +* SMBUS_REG_PHY_TIMEOUT_MIN +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTimeoutMinTimeoutEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the MIN_TIMEOUT_MIN bitfield from hardware register +* SMBUS_REG_PHY_TIMEOUT_MIN +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTimeoutMinTimeoutMin( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_PHY_TIMEOUT_MAX +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTimeoutMax( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the SMBCLK_FORCE_LOW bitfield from hardware register +* SMBUS_REG_PHY_RESET_CONTROL +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYResetControlSMBClkForce( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the TGT_DATA_SETUP bitfield from hardware register +* SMBUS_REG_PHY_TGT_DATA_SETUP +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTgtDataSetupTgtDataSetup( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the TGT_TEXT_PRESCALER bitfield from hardware register +* SMBUS_REG_PHY_TGT_TEXT_PRESCALER +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTgtTextPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the TGT_TEXT_TIMEOUT bitfield from hardware register +* SMBUS_REG_PHY_TGT_TEXT_TIMEOUT +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTgtTextTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the TGT_TEXT_MAX bitfield from hardware register +* SMBUS_REG_PHY_TGT_TEXT_MAX +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTgtTextMax( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the DBG_STATE bitfield from hardware register +* SMBUS_REG_PHY_TGT_DBG_STATE +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTgtDbgState( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the DATA_HOLD bitfield from hardware register +* SMBUS_REG_PHY_TGT_DATA_HOLD +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYTgtDataHold( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_TGT_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtStatus( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the TGT_STATUS_ACTIVE bitfield from hardware register +* SMBUS_REG_TGT_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtStatusActive( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the TGT_STATUS_ADDRESS bitfield from hardware register +* SMBUS_REG_TGT_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtStatusAddress( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the TGT_STATUS_RW bitfield from hardware register +* SMBUS_REG_TGT_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtStatusRW( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the FILL_LEVEL bitfield from hardware register +* SMBUS_REG_TGT_DESC_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtDescStatusFillLevel( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the FULL bitfield from hardware register +* SMBUS_REG_TGT_DESC_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtDescStatusFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ALMOST_FULL bitfield from hardware register +* SMBUS_REG_TGT_DESC_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtDescStatusAlmostFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ALMOST_EMPTY bitfield from hardware register +* SMBUS_REG_TGT_DESC_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtDescStatusAlmostEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the EMPTY bitfield from hardware register +* SMBUS_REG_TGT_DESC_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtDescStatusEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the PAYLOAD bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoPayload( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the FILL_LEVEL bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoStatusFillLevel( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the RESET_BUSY bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoStatusResetBusY( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the FULL bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoStatusFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ALMOST_FULL bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoStatusAlmostFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ALMOST_EMPTY bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoStatusAlmostEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the EMPTY bitfield from hardware register SMBUS_REG_TGT_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoStatusEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the FILL_THRESHOLD bitfield from hardware register +* SMBUS_REG_TGT_RX_FIFO_FILL_THRESHOLD +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtRxFifoFillThresholdFillThresh( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the hardware register SMBUS_REG_TGT_DBG +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtDbg( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_0 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl0Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_0 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl0Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_1 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl1Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_1 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl1Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_2 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl2Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_2 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl2Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_3 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl3Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_3 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl3Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_4 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl4Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_4 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl4Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_5 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl5Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_5 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl5Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_6 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl6Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_6 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl6Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_TGT_CONTROL_7 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl7Enable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ADDRESS bitfield from hardware register SMBUS_REG_TGT_CONTROL_7 +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadTgtControl7Address( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the DATA_HOLD bitfield from hardware register +* SMBUS_REG_PHY_CTLR_DATA_HOLD +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlDataHold( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the START_HOLD bitfield from hardware register +* SMBUS_REG_PHY_CTLR_START_HOLD +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlStartHold( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the START_SETUP bitfield from hardware register +* SMBUS_REG_PHY_CTLR_START_SETUP +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlStartSetup( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the STOP_SETUP bitfield from hardware register +* SMBUS_REG_PHY_CTLR_STOP_SETUP +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlStopSetup( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the CLK_TLOW bitfield from hardware register +* SMBUS_REG_PHY_CTLR_CLK_TLOW +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlClkTLow( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the CLK_THIGH bitfield from hardware register +* SMBUS_REG_PHY_CTLR_CLK_THIGH +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlClkTHigh( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the TEXT_PRESCALER bitfield from hardware register +* SMBUS_REG_PHY_CTLR_TEXT_PRESCALER +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlTextPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the TEXT_TIMEOUT bitfield from hardware register +* SMBUS_REG_PHY_CTLR_TEXT_TIMEOUT +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlTextTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the TEXT_MAX bitfield from hardware register +* SMBUS_REG_PHY_CTLR_TEXT_MAX +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlTextMax( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the CEXT_PRESCALER bitfield from hardware register +* SMBUS_REG_PHY_CTLR_CEXT_PRESCALER +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlCextPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the CEXT_TIMEOUT bitfield from hardware register +* SMBUS_REG_PHY_CTLR_CEXT_TIMEOUT +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlCextTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the CEXT_MAX bitfield from hardware register +* SMBUS_REG_PHY_CTLR_CEXT_MAX +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlCextMax( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the DBG_STATE bitfield from hardware register +* SMBUS_REG_PHY_CTLR_DBG_STATE +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadPHYCtrlDbgState( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ENABLE bitfield from hardware register SMBUS_REG_CTLR_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlStatusEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the FILL_LEVEL bitfield from hardware register +* SMBUS_REG_CTLR_DESC_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDescStatusFillLevel( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the RESET_BUSY bitfield from hardware register +* SMBUS_REG_CTLR_DESC_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDescStatusResetBusy( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the FULL bitfield from hardware register +* SMBUS_REG_CTLR_DESC_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDescStatusFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ALMOST_FULL bitfield from hardware register +* SMBUS_REG_CTLR_DESC_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDescStatusAlmostFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ALMOST_EMPTY bitfield from hardware register +* SMBUS_REG_CTLR_DESC_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDescStatusAlmostEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the EMPTY bitfield from hardware register +* SMBUS_REG_CTLR_DESC_STATUS +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDescStatusEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the PAYLOAD bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoPayload( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the FILL_LEVEL bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoStatusFillLevel( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the RESET_BUSY bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoStatusResetBusy( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the FULL bitfield from hardware register SMBUS_REG_CTLR_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoStatusFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ALMOST_FULL bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoStatusAlmostFull( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the ALMOST_EMPTY bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoStatusAlmostEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the EMPTY bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoStatusEmpty( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the THRESHOLD bitfield from hardware register +* SMBUS_REG_CTLR_RX_FIFO_FILL_THRESHOLD +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlRxFifoFillThresholdFillThresh( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Reads the DBG_STATE bitfield from hardware register +* SMBUS_REG_CTLR_DBG +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint32_t register value read +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusHWReadCtrlDbgState( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_IRQ_GIE +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteIRQGIEEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_IRQ_IER +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteIRQIER( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_IRQ_ISR +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteIRQISR( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_ERR_IRQ_IER +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteERRIRQIER( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_ERR_IRQ_ISR +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteERRIRQISR( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to ENABLE bitfield of hardware register +* SMBUS_REG_PHY_FILTER_CONTROL +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYFilterControlEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to DURATION bitfield of hardware register +* SMBUS_REG_PHY_FILTER_CONTROL +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYFilterControlDuration( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_BUS_FREE_TIME +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYBusFreetime( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to IDLE_THRESHOLD bitfield of hardware register +* SMBUS_REG_PHY_IDLE_THRESHOLD +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYIdleThresholdIdleThreshold( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TIMEOUT_PRESCALER +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYTimeoutPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TIMEOUT_MIN +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYTimeoutMin( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to ENABLE bitfield of hardware register +* SMBUS_REG_PHY_TIMEOUT_MIN +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYTimeoutMinTimeoutEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to TIMEOUT_MIN bitfield of hardware register +* SMBUS_REG_PHY_TIMEOUT_MIN +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYTimeoutMinTimeoutMin( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TIMEOUT_MAX +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYTimeoutMax( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to SMBCLK_FORCE_TIMEOUT bitfield of hardware register +* SMBUS_REG_PHY_RESET_CONTROL +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYResetControlSMBClkForceTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to SMBCLK_FORCE_LOW bitfield of hardware register +* SMBUS_REG_PHY_RESET_CONTROL +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYResetControlSMBClkForceLow( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to TGT_DATA_SETUP bitfield of hardware register +* SMBUS_REG_PHY_TGT_DATA_SETUP +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYTgtDataSetupTgtDataSetup( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TGT_TEXT_PRESCALER +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYTgtTextPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TGT_TEXT_TIMEOUT +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYTgtTextTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TGT_TEXT_MAX +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYTgtTextMax( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_TGT_DATA_HOLD +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYTgtDataHold( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_TGT_DESC_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteTgtDescFifo( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to FIFO_ID bitfield of hardware register +* SMBUS_REG_TGT_DESC_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteTgtDescFifoId( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to PAYLOAD bitfield of hardware register +* SMBUS_REG_TGT_DESC_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteTgtDescFifoPayload( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to RESET bitfield of hardware register +* SMBUS_REG_TGT_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteTgtRxFifoReset( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to THRESHOLD bitfield of hardware register +* SMBUS_REG_TGT_RX_FIFO_FILL_THRESHOLD +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteRxFifoFillThresholdFillThresh( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Passes the ulValue to the desired TgtControl register dependent +* on the instance value +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucInstance is SMBus instance to use +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteTgtControlEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucInstance, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Passes the ulValue to the desired TgtControl register dependent +* on the instance value +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucInstance is SMBus instance to use +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteTgtControlAddress( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucInstance, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_DATA_HOLD +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlDataHold( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_START_HOLD +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlStartHold( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_START_SETUP +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlStartSetup( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_STOP_SETUP +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlStopSetup( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_CLK_TLOW +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlClkTLow( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_CLK_THIGH +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlClkTHigh( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_TEXT_PRESCALER +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlTextPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_TEXT_TIMEOUT +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlTextTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_TEXT_MAX +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlTextMax( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_CEXT_PRESCALER +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlCextPrescaler( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_CEXT_TIMEOUT +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlCextTimeout( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_PHY_CTLR_CEXT_MAX +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWritePHYCtrlCextMax( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_CTLR_CONTROL +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteCtrlControlEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to hardware register SMBUS_REG_CTLR_DESC_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteCtrlDescFifo( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to RESET bitfield of hardware register SMBUS_REG_CTLR_DESC_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteCtrlDescFifoReset( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to RESET bitfield of hardware register +* SMBUS_REG_CTLR_RX_FIFO +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteCtrlRxFifoReset( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/******************************************************************************* +* +* @brief Writes ulValue to FILL_THRESHOLD bitfield of hardware register +* SMBUS_REG_CTLR_RX_FIFO_FILL_THRESHOLD +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulValue value to write to the register bitfield +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusHWWriteCtrlRxFifoFillThreshold( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulValue ); + +/* Descriptor read functions */ + +/******************************************************************************* +* +* @brief Writes a data byte along with a Target Read - Read Descriptor ID +* to transmit the data byte +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucData is the data byte being returned by the target +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusTargetReadDescriptorRead( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucData ); + +/******************************************************************************* +* +* @brief Writes a Target Read - PEC Descriptor ID to the Target Descriptor FIFO +* To iform the IP to transmit the PEC byte it has calculated on the data +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusTargetReadDescriptorPECRead( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Writes a Target Write - ACK Descriptor ID to the Target Descriptor FIFO +* To inform the IP to transmit an ACK +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusTargetWriteDescriptorACK( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucNoStatusCheck ); + +/******************************************************************************* +* +* @brief Writes a Target Write - NACK Descriptor ID to the Target Descriptor FIFO +* To inform the IP to transmit a NACK +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusTargetWriteDescriptorNACK( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Writes a Target Write - PEC Descriptor ID to the Target Descriptor FIFO +* To inform the IP to interpret the previous byte as a PEC +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusTargetWriteDescriptorPEC( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Writes a Controller Write - START Descriptor ID to the Controller Descriptor FIFO +* To inform the IP to transmit a START condition +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucDestination is the Target address to transmit to +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusControllerWriteDescriptorStartWrite( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucDestination ); + +/******************************************************************************* +* +* @brief Writes a Controller Write - QUICK Descriptor ID to the Controller Descriptor FIFO +* To inform the IP to transmit a START condition followed by a STOP +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucDestination is the Target address to transmit to +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusControllerWriteDescriptorQuickWrite( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucDestination ); + +/******************************************************************************* +* +* @brief Writes a Controller Write - BYTE Descriptor ID to the Controller Descriptor FIFO +* along with a data byte +* To inform the IP to transmit the data byte +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucData is the data byte to send +* @param ucNoStatusCheck allows the function to bypass a read of the fill status of the FIFO +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusControllerWriteDescriptorByte( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucData, uint8_t ucNoStatusCheck ); + +/******************************************************************************* +* +* @brief Writes a Controller Write - STOP Descriptor ID to the Controller Descriptor FIFO +* along with a data byte +* To inform the IP to transmit the data byte followed by a STOP condition +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucData is the final data byte to send +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusControllerWriteDescriptorStopWrite( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucData ); + +/******************************************************************************* +* +* @brief Writes a Controller Write - PEC Descriptor ID to the Controller Descriptor FIFO +* To inform the IP to transmit the PEC verify an ACK and then transmit a STOP +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusControllerWriteDescriptorPECWrite( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Writes a Controller Read - START Descriptor ID to the Controller Descriptor FIFO +* along with Target address +* To inform the IP to start a new READ transaction +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucDestination is the Target address to transmit to with Read bit +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusControllerReadDescriptorStart( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucDestination ); + +/******************************************************************************* +* +* @brief Writes a Controller Read - QUICK Descriptor ID to the Controller Descriptor FIFO +* along with Target address +* To inform the IP to start a new READ transaction followed by a STOP +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucDestination is the Target address to transmit to with Read bit +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusControllerReadDescriptorQuickRead( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucDestination ); + +/******************************************************************************* +* +* @brief Writes a Controller Read - BYTE Descriptor ID to the Controller Descriptor FIFO +* To inform the IP to transmit an ACK for the previous byte received +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ucNoStatusCheck allows the function to bypass a read of the fill status of the FIFO +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusControllerReadDescriptorByte( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucNoStatusCheck ); + +/******************************************************************************* +* +* @brief Writes a Controller Read - STOP Descriptor ID to the Controller Descriptor FIFO +* To inform the IP to transmit a NACK followed by a STOP condition +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusControllerReadDescriptorStop( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Writes a Controller Read - PEC Descriptor ID to the Controller +* Descriptor FIFO to inform the IP to transmit a NACK followed by a +* STOP and use the last received byte to perform a PEC check +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return SMBUS_HW_DESCRIPTOR_WRITE_FAIL - if write to descriptor fails +* SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS - if write to descriptor succeeds +* +* @note None. +* +*******************************************************************************/ +uint8_t ucSMBusControllerReadDescriptorPEC( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Converts an Descriptor enum value to a text string for logging +* +* @param SMBus_HW_Descriptor_Type is any Descriptor enum value +* +* @return A text string of the event +* +* @note None. +* +*******************************************************************************/ +char* pcDescriptorToString( SMBus_HW_Descriptor_Type xDescriptor ); + +#ifdef __cplusplus +} +#endif + +#endif /* _SMBus_HARDWARE_ACCESS_H_ */ diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_internal.h b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_internal.h new file mode 100755 index 00000000..0c43e7d5 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_internal.h @@ -0,0 +1,419 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This header file contains private definitions for the SMBus driver. + * + * @file smbus_internal.h + * + */ + +#ifndef _SMBUS_INTERNAL_H_ +#define _SMBUS_INTERNAL_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include "smbus.h" +#include "i2c.h" + +/******************************************************************************/ +/* Defines */ +/******************************************************************************/ +#define SMBUS_INVALID_ADDRESS_MASK ( 0x80 ) +#define SMBUS_DEVICE_DEFAULT_ARP_ADDRESS ( 0x61 ) +#define SMBUS_NOTIFY_ARP_MASTER_ADDRESS ( 0x10 ) +#define SMBUS_ARP_INSTANCE_ID ( 7 ) +#define SMBUS_FIRST_SMBUS_INSTANCE ( 0 ) +#define SMBUS_LAST_SMBUS_INSTANCE ( 7 ) +#define SMBUS_LAST_NON_ARP_SMBUS_INSTANCE ( SMBUS_LAST_SMBUS_INSTANCE - 1 ) +#define SMBUS_INSTANCE_UNDETERMINED ( 88 ) +#define SMBUS_UDID_ASSIGNED_ADDRESS_BYTE ( 17 ) +#define SMBUS_UDID_ASSIGNED_ADDRESS_BIT0 ( 0x01 ) +#define SMBUS_GET_UDID_DATA_LENGTH ( 17 ) +#define SMBUS_GET_UDID_MSG_LENGTH ( SMBUS_GET_UDID_DATA_LENGTH + 1 ) +#define SMBUS_UDID_DEVICE_CAPABILITIES_BYTE ( 15 ) +#define SMBUS_UDID_DTA_AV_FLAG_CLEAR ( 0xFF ) +#define SMBUS_UDID_DTA_BIT_0_SET ( 0x01 ) +#define SMBUS_UDID_ADDRESS_TYPE_MASK ( 0xC0 ) +#define SMBUS_UDID_FIXED_ADDRESS ( 0x00 ) +#define SMBUS_UDID_DYNAMIC_AND_PERSISTENT ( 0x40 ) +#define SMBUS_UDID_DYNAMIC_AND_VOLATILE ( 0x80 ) +#define SMBUS_UDID_RANDOM_NUMBER ( 0xC0 ) +#define SMBUS_MAGIC_NUMBER ( 0x534D4273 ) +#define SMBUS_FIREWALL1 ( 0xF15E2112 ) +#define SMBUS_FIREWALL2 ( 0xAC1DBA78 ) +#define SMBUS_FIREWALL3 ( 0x1CE1CE99 ) +#define SMBUS_UDID_PEC_SUPPORTED_BIT ( 0x01 ) +#define SMBUS_RX_FIFO_IS_EMPTY ( 1 ) +#define SMBUS_DESC_FIFO_IS_FULL ( 1 ) +#define SMBUS_COMMAND_INVALID ( 66 ) +#define SMBUS_FIFO_DEPTH ( 64 ) +#define SMBUS_HALF_FIFO_DEPTH ( 32 ) +#define SMBUS_FIFO_SPACE_FOR_TWO_BYTES ( SMBUS_FIFO_DEPTH - 2 ) +#define SMBUS_FIFO_FILL_TRIGGER ( 20 ) +#define SMBUS_INITIALIZATION_CODE ( 0x7AB3F91D ) +#define SMBUS_DEINITIALIZATION_CODE ( 0x0 ) +#define SMBUS_TBUF_DIVISOR ( 100000000 ) +#define SMBUS_CTRL_FIXED_INPUT_LATENCY ( 7 ) +#define SMBUS_TBUF_MIN_100KHZ ( 470 ) +#define SMBUS_TBUF_MIN_400KHZ ( 130 ) +#define SMBUS_TBUF_MIN_1MHZ ( 50 ) +#define SMBUS_TSU_DAT_MIN_100KHZ ( 125 ) +#define SMBUS_TSU_DAT_MIN_400KHZ ( 40 ) +#define SMBUS_TSU_DAT_MIN_1MHZ ( 17 ) +#define SMBUS_TGT_DATA_HOLD_100KHZ ( 33 ) +#define SMBUS_TGT_DATA_HOLD_400KHZ ( 0.11 ) +#define SMBUS_TGT_DATA_HOLD_1MHZ ( 0.11 ) +#define SMBUS_CTLR_DATA_HOLD_100KHZ ( 33 ) +#define SMBUS_CTLR_DATA_HOLD_400KHZ ( 0.11 ) +#define SMBUS_CTLR_DATA_HOLD_1MHZ ( 0.11 ) +#define SMBUS_CTLR_START_HOLD_100KHZ ( 440 ) +#define SMBUS_CTLR_START_HOLD_400KHZ ( 66 ) +#define SMBUS_CTLR_START_HOLD_1MHZ ( 28.6 ) +#define SMBUS_CTLR_START_SETUP_100KHZ ( 517 ) +#define SMBUS_CTLR_START_SETUP_400KHZ ( 66 ) +#define SMBUS_CTLR_START_SETUP_1MHZ ( 28.6 ) +#define SMBUS_CTLR_STOP_SETUP_100KHZ ( 440 ) +#define SMBUS_CTLR_STOP_SETUP_400KHZ ( 66 ) +#define SMBUS_CTLR_STOP_SETUP_1MHZ ( 28.6 ) +#define SMBUS_CTLR_CLK_LOW_100KHZ ( 517 ) +#define SMBUS_CTLR_CLK_LOW_400KHZ ( 143 ) +#define SMBUS_CTLR_CLK_LOW_1MHZ ( 55 ) +#define SMBUS_CTLR_CLK_HIGH_100KHZ ( 440 ) +#define SMBUS_CTLR_CLK_HIGH_400KHZ ( 66 ) +#define SMBUS_CTLR_CLK_HIGH_1MHZ ( 28.6 ) +#define SMBUS_GET_FREQUENCY_VALUE( x, y ) ( ulSMBusCeil( ( float )x * ( ( ( float )y )/ ( float )SMBUS_TBUF_DIVISOR ) ) - 1 ) +#define SMBUS_GET_FREQUENCY_VALUE_MINUS_CONSTANT( x, y, z ) ( ulSMBusCeil( ( float )x * ( ( ( float )y )/ ( float )SMBUS_TBUF_DIVISOR ) ) - z ) +#define SMBUS_GET_GLITCH_FILTER_DUR( x ) ( x + 1 ) +#define SMBUS_GET_CONSTANT ( SMBUS_CTRL_FIXED_INPUT_LATENCY + 1 ) +#define SMBUS_GET_CONSTANT_WITH_GLITCH( x ) ( x + SMBUS_GET_CONSTANT ) +#define SMBUS_SINGLE_ELEMENT ( 1 ) +#define SMBUS_ZERO_ELEMENTS ( 0 ) +#define SMBUS_TRUE ( 1 ) +#define SMBUS_FALSE ( 0 ) +#define SMBUS_CONTROL_ENABLE ( 1 ) +#define SMBUS_MAX_FIFO_EMPTY_WHILE_IN_DONE ( 10 ) +#define SMBUS_SMBCLK_LOW_TIMEOUT_DETECTED ( 1 ) +#define SMBUS_SMBDAT_LOW_TIMEOUT_DETECTED ( 1 ) +#define SMBUS_UNEXPECTED_READ_DESCRIPTOR_DATA ( 0xFF ) + +/* + * @enum SMBus_State_Type + * @brief Enumeration of SMBUS FSM states + */ +typedef enum SMBus_State_Type +{ + SMBUS_STATE_INITIAL = 0, + SMBUS_STATE_AWAITING_COMMAND_BYTE, + SMBUS_STATE_AWAITING_BLOCK_SIZE, + SMBUS_STATE_AWAITING_DATA, + SMBUS_STATE_AWAITING_READ, + SMBUS_STATE_READY_TO_SEND_BYTE, + SMBUS_STATE_CHECK_IF_PEC_REQUIRED, + SMBUS_STATE_AWAITING_DONE, + SMBUS_STATE_CONTROLLER_SEND_COMMAND, + SMBUS_STATE_CONTROLLER_SEND_READ_START, + SMBUS_STATE_CONTROLLER_READ_BLOCK_SIZE, + SMBUS_STATE_CONTROLLER_READ_BYTE, + SMBUS_STATE_CONTROLLER_READ_PEC, + SMBUS_STATE_CONTROLLER_READ_DONE, + SMBUS_STATE_CONTROLLER_WRITE_BYTE + +} SMBus_State_Type; + +/* + * @struct SMBUS_LOG_BUFFER_ELEMENT_TYPE + * @brief Structure to hold SMBus debug logging information + */ +typedef struct SMBUS_LOG_BUFFER_ELEMENT_TYPE +{ + uint32_t ulIsOccupied; + uint32_t ulTicks; + uint32_t ulEntry1; + uint32_t ulInstance; + uint32_t ulEntry2; + SMBUS_LOG_EVENT_TYPE xEvent; + +} SMBUS_LOG_BUFFER_ELEMENT_TYPE; + +/* + * @struct SMBUS_LOG_BUFFER_TYPE + * @brief Structure to hold SMBus read/write logging information + */ +typedef struct SMBUS_LOG_BUFFER_TYPE +{ + uint32_t ulWrite; + uint32_t ulRead; + +} SMBUS_LOG_BUFFER_TYPE; + +/* + * @struct SMBUS_EVENT_BUFFER_ELEMENT_TYPE + * @brief Structure to single SMBus State Machine Event + */ +typedef struct SMBUS_EVENT_BUFFER_ELEMENT_TYPE +{ + uint8_t ucIsOccupied; + uint8_t ucOctet; + +} SMBUS_EVENT_BUFFER_ELEMENT_TYPE; + +/* + * @struct SMBUS_EVENT_BUFFER_TYPE + * @brief Structure to hold SMBus State Machine Event queue + */ +typedef struct SMBUS_EVENT_BUFFER_TYPE +{ + uint32_t ulMaxElements; + uint32_t ulWrite; + uint32_t ulRead; + SMBUS_EVENT_BUFFER_ELEMENT_TYPE* pxEventBuffer; + +} SMBUS_EVENT_BUFFER_TYPE; + +/* + * @struct SMBUS_INSTANCE_TYPE + * @brief Structure to hold a single SMBus instance + */ +typedef struct SMBUS_INSTANCE_TYPE +{ + uint32_t ulFirewall1; + SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_PROTOCOL_TYPE pFnGetProtocol; + SMBUS_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE pFnGetData; + SMBUS_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE pFnWriteData; + SMBUS_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE pFnAnnounceResult; + SMBUS_USER_SUPPLIED_ENVIRONMENT_ARP_ADRRESS_CHANGE pFnArpAddressChange; + SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_ERROR pFnBusError; + SMBUS_USER_SUPPLIED_ENVIRONMENT_BUS_WARNING pFnBusWarning; + I2C_USER_SUPPLIED_ENVIRONMENT_GET_DATA_TYPE pFnI2CGetData; + I2C_USER_SUPPLIED_ENVIRONMENT_WRITE_DATA_TYPE pFnI2CWriteData; + I2C_USER_SUPPLIED_ENVIRONMENT_COMMAND_COMPLETE pFnI2CAnnounceResult; + void* pxSMBusProfile; + uint32_t ulI2CDevice; + uint32_t ulI2CTransaction; + uint32_t ulAction; + uint32_t ulMessagesComplete[I2C_PROTOCOL_NONE]; + uint32_t ulMessagesInitiated[I2C_PROTOCOL_NONE]; + uint16_t usSendDataSize; + uint16_t usSendIndex; + uint16_t usReceiveIndex; + uint16_t usDescriptorsSent; + uint8_t ucSendData[SMBUS_DATA_SIZE_MAX]; + uint8_t ucReceivedData[SMBUS_DATA_SIZE_MAX]; + uint8_t ucUDID[SMBUS_UDID_LENGTH]; + uint32_t ulFirewall2; + uint8_t ucInstanceInUse; + uint8_t ucSMBusAddress; + uint8_t ucPECRequired; + uint8_t ucThisInstanceNumber; + uint8_t ucEvent; + uint8_t ucCommand; + uint8_t ucSimpleDevice; + uint8_t ucExpectedByteCountPart; + uint16_t usExpectedByteCount; + uint8_t ucSMBusDestinationAddress; + uint8_t ucSMBusSenderAddress; + uint8_t ucPecRequiredForTransaction; + uint8_t ucTriggerFSM; + uint8_t ucNewDeviceSlaveAddress; + uint8_t ucUDIDMatchedInstance; + uint8_t ucARFlag; + uint8_t ucAVFlag; + uint8_t ucMatchedSMBusAddress; + uint8_t ucNackSent; + uint8_t ucPECSent; + uint8_t ucFifoEmptyWhileInDoneCount; + SMBus_State_Type xPreviousState; + SMBus_State_Type xState; + SMBus_Command_Protocol_Type xProtocol; + SMBus_ARP_Capability xARPCapability; + SMBUS_EVENT_BUFFER_TYPE xEventSourceCircularBuffer; + SMBUS_EVENT_BUFFER_ELEMENT_TYPE xCircularBuffer[SMBUS_MAX_EVENT_ELEMENTS]; + uint32_t ulFirewall3; + +} SMBUS_INSTANCE_TYPE; + +/* + * @struct SMBUS_PROFILE_TYPE + * @brief Structure to hold a single SMBus profile + */ +typedef struct SMBUS_PROFILE_TYPE +{ + SMBUS_USER_SUPPLIED_ENVIRONMENT_READ_TICKS pFnReadTicks; + void* pvBaseAddress; + uint32_t ulTransactionID; + uint32_t ulInitialize; + SMBUS_LOG_BUFFER_TYPE xLogCircularBuffer; + SMBUS_LOG_BUFFER_ELEMENT_TYPE xCircularBuffer[SMBUS_MAX_CIRCULAR_LOG_ENTRIES]; + SMBUS_INSTANCE_TYPE xSMBusInstance[SMBUS_NUMBER_OF_SMBUS_INSTANCES]; + uint8_t ucInstanceInPlay; + uint8_t ucActiveTargetInstance; + SMBUS_LOG_LEVEL_TYPE xLogLevel; + uint8_t ucUDIDMatch[SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES]; + +} SMBUS_PROFILE_TYPE; + +/******************************************************************************* +* +* @brief Does a ceiling conversion on a floating point number and returns the +* rounded up interger value +* +* @param fNum is a floating point number +* @return An integer +* +* @note None. +* +*******************************************************************************/ +uint32_t ulSMBusCeil( float fNum ); + +/******************************************************************************* +* +* @brief Converts a protocol enum value to a text string for logging +* +* @param ucProtocol is any protocol enum value +* @return A character string of the protocol +* +* @note None. +* +*******************************************************************************/ +SMBus_Error_Type xSMBusFirewallCheck(SMBUS_PROFILE_TYPE* pxSMBusProfile); + +/******************************************************************************* +* +* @brief Will add a log entry into the debug log +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param xLogLevel is the level of the log being added +* @param ulInstance is the numerical instance number +* @param xLogEvent is the type of log event +* @param ulEntry1 is a uint32_t value to log. Depending on xLogEvent this can be interpreted +* @param ulEntry2 is a 2nd uint32_t value to log. Depending on xLogEvent this can be interpreted +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vLogAddEntry( SMBUS_PROFILE_TYPE* pxSMBusProfile, SMBUS_LOG_LEVEL_TYPE xLogLevel, uint32_t ulInstance, + SMBUS_LOG_EVENT_TYPE xLogEvent, uint32_t ulEntry1, uint32_t ulEntry2 ); + +/******************************************************************************* +* +* @brief Converts a protocol enum value to a text string for logging +* +* @param ucProtocol is any protocol enum value +* @return A character string of the protocol +* +* @note None. +* +*******************************************************************************/ +char* pcProtocolToString( uint8_t ucProtocol ); + +/******************************************************************************* +* +* @brief Will walk through all active instances, check if any events have been +* raised against that instance and call into the state machine for that +* instance with each event found +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusEventQueueHandle( SMBUS_PROFILE_TYPE* pxSMBusProfile ); +/******************************************************************************* +* +* @brief Initializes the debug log. Setting its pointer to zero +* +* @param pxSMBusProfile is the pointer to the SMBUS profile +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vLogInitialize( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Will retreive the log as a character string +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param pcLogBuffer is the buffer to write the log in to. +* @param usLogSizeBytes is the number of byte being returned +* @return None +* +* @note None. +* +*******************************************************************************/ +void vLogDisplayLog( SMBUS_PROFILE_TYPE* pxSMBusProfile, char* pcLogBuffer, uint32_t* usLogSizeBytes ); +/******************************************************************************/ +/* Driver Internal APIs */ +/******************************************************************************/ + +/******************************************************************************* +* +* @brief Enables logging +* +* @param pxSMBusProfile is the pointer to the SMBUS profile +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusLogEnable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Disables logging +* +* @param pxSMBusProfile is the pointer to the SMBUS profile +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusLogDisable( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Resets the statistics log values for the specified instance +* +* @param pxSMBusProfile is the pointer to the SMBUS profile +* @param ucSMBusInstanceID is the SMBus instance ID of the instance to use as the controller +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusResetStatsLogInstance( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucSMBusInstance ); + +/******************************************************************************* +* +* @brief Reads the statistics log values for the specified instance +* +* @param pxSMBusProfile is the pointer to the SMBUS profile +* @param ucSMBusInstanceID is the SMBus instance ID of the instance to use as the controller +* @param pSMBusMessageLog is pointer to the log read +* +* @return None +* +* @note None. +* +*******************************************************************************/ +void vSMBusReadStatsLogInstance( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint8_t ucSMBusInstance, + SMBUS_LOG_TYPE* pSMBusMessageLog ); + +#ifdef __cplusplus +} +#endif + +#endif /* _SMBUS_INTERNAL_H_ */ diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_interrupt_handler.c b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_interrupt_handler.c new file mode 100755 index 00000000..947b1bcb --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_interrupt_handler.c @@ -0,0 +1,395 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the interrupt handler function which must be bound by + * application software to the interrupt system being used + * Interrupts from the SMBus IP will trigger a call to this interrupt handler + * which in turn will drive the state machine + * + * @file smbus_interrupt_handler.c + * + */ + +#include "smbus.h" +#include "smbus_internal.h" +#include "smbus_interrupt_handler.h" +#include "smbus_event.h" +#include "smbus_hardware_access.h" + +/******************************************************************************* +* +* @brief Walk through the list of active instances and determine which +* instance the address corresponds to +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* +* @return uint8_t instance number 0-7 +* +* @note None. +* +*******************************************************************************/ +static uint8_t ucSMBusDetermineInstanceFromTargetAddress( SMBUS_PROFILE_TYPE* pxSMBusProfile ); + +/******************************************************************************* +* +* @brief Function clears any set bits in the ISR and ERR_ISR registers +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure. +* @param ulISR_RegisterValue is previous value of the ISR_Register +* @param ulERR_ISR_RegisterValue is previous value of the ERR_ISR_Register +* +* @return void +* +* @note None. +* +*******************************************************************************/ +static void prvvSMBusClearInterrupts( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulISR_RegisterValue, + uint32_t ulERR_ISR_RegisterValue ); + +/******************************************************************************* +* +* @brief Walk through the list of active instances and determine which +* instance the address corresponds to +* +*******************************************************************************/ +static uint8_t ucSMBusDetermineInstanceFromTargetAddress( SMBUS_PROFILE_TYPE* pxSMBusProfile ) +{ + uint8_t ucInstance = SMBUS_INVALID_INSTANCE; + uint8_t ucAddress = 0; + int i = 0; + + if( NULL != pxSMBusProfile ) + { + ucAddress = ulSMBusHWReadTgtStatusAddress( pxSMBusProfile ); + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_INSTANCES; i++ ) + { + if( SMBUS_TRUE == pxSMBusProfile->xSMBusInstance[i].ucInstanceInUse ) + { + if( ucAddress == pxSMBusProfile->xSMBusInstance[i].ucSMBusAddress ) + { + ucInstance = i; + break; + } + } + } + } + + return ( ucInstance ); +} + +/******************************************************************************* +* +* @brief Function clears any set bits in the ISR and ERR_ISR registers +* +*******************************************************************************/ +static void prvvSMBusClearInterrupts( SMBUS_PROFILE_TYPE* pxSMBusProfile, uint32_t ulISR_RegisterValue, + uint32_t ulERR_ISR_RegisterValue ) +{ + if( NULL != pxSMBusProfile ) + { + /* Clear any raised interrupts */ + vSMBusHWWriteERRIRQISR( pxSMBusProfile, ulERR_ISR_RegisterValue ); + vSMBusHWWriteIRQISR( pxSMBusProfile, ulISR_RegisterValue ); + } +} + +/******************************************************************************* +* +* @brief Function will be a callback called from the interrupt handler +* It will determine what interrupts are present from those add +* events on the event queue and then trigger the handling of the +* events by the state machine +* +*******************************************************************************/ +void vSMBusInterruptHandler( void* pvCallBackRef ) +{ + uint32_t ulISR_RegisterValue = 0; + uint32_t ulIER_RegisterValue = 0; + uint32_t ulInterruptVector = 0; + uint32_t ulERR_ISR_RegisterValue = 0; + uint32_t ulERR_IER_RegisterValue = 0; + uint32_t ulInterruptErrorVector = 0; + uint32_t ulDisableSMBClkLowRegValue = 0; + uint32_t ulDisableSMBDatLowRegValue = 0; + uint8_t ucInstance = SMBUS_INVALID_INSTANCE; + + if( NULL != pvCallBackRef ) + { + SMBUS_PROFILE_TYPE* pxSMBusProfile = ( SMBUS_PROFILE_TYPE* )pvCallBackRef; + + /* check clk/dat status */ + if( ( SMBUS_SMBCLK_LOW_TIMEOUT_DETECTED != ulSMBusHWReadPHYStatusSMBClkLowTimeout( pxSMBusProfile ) ) && + ( SMBUS_SMBDAT_LOW_TIMEOUT_DETECTED != ulSMBusHWReadPHYStatusSMBDATLowTimeout( pxSMBusProfile ) ) ) + { + /* Re-enable all ERR_IRQ_IER interrupts */ + vSMBusHWWriteERRIRQIER( pxSMBusProfile, 0x000FFFFF ); + } + + /* Disable the interrupt */ + vSMBusHWWriteIRQGIEEnable( pxSMBusProfile, 0 ); + + /* Read registers to determine the interrupt source */ + ulISR_RegisterValue = ulSMBusHWReadIRQISR( pxSMBusProfile ); + ulIER_RegisterValue = ulSMBusHWReadIRQIER( pxSMBusProfile ); + ulInterruptVector = ulISR_RegisterValue & ulIER_RegisterValue; + + if( ulInterruptVector & SMBUS_INTERRUPT_ERROR_IRQ ) + { + ulERR_ISR_RegisterValue = ulSMBusHWReadErrIRQISR( pxSMBusProfile ); + ulERR_IER_RegisterValue = ulSMBusHWReadErrIRQIER( pxSMBusProfile ); + ulInterruptErrorVector = ulERR_ISR_RegisterValue & ulERR_IER_RegisterValue; + + /* Handle CLK/DAT line low interrupts */ + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_PHY_SMBCLK_LOW_TIMEOUT ) + { + /* Disable PHY_SMBCLK_LOW_TIMEOUT interrupt */ + ulERR_IER_RegisterValue = ulSMBusHWReadErrIRQIER( pxSMBusProfile ); + ulDisableSMBClkLowRegValue = ulERR_IER_RegisterValue & 0x000FFFFE; + vSMBusHWWriteERRIRQIER( pxSMBusProfile, ulDisableSMBClkLowRegValue ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_PHY_SMBDAT_LOW_TIMEOUT ) + { + /* Disable PHY_SMBDAT_LOW_TIMEOUT interrupt */ + ulERR_IER_RegisterValue = ulSMBusHWReadErrIRQIER( pxSMBusProfile ); + ulDisableSMBDatLowRegValue = ulERR_IER_RegisterValue & 0x000FFFFD; + vSMBusHWWriteERRIRQIER( pxSMBusProfile, ulDisableSMBDatLowRegValue ); + } + } + + vLogAddEntry( pxSMBusProfile, SMBUS_LOG_LEVEL_INFO, + SMBUS_INSTANCE_UNDETERMINED, SMBUS_LOG_EVENT_INTERRUPT_EVENT, ulISR_RegisterValue, ulERR_ISR_RegisterValue ); + + if( 0 != ( ( ulInterruptVector ) & ( SMBUS_INTERRUPT_TGT_INTERRUPTS | SMBUS_INTERRUPT_ERROR_IRQ ) ) ) + { + if( ( ulInterruptVector ) & ( SMBUS_INTERRUPT_TGT_READ_OR_WRITE_INTERRUPTS ) ) + { + pxSMBusProfile->ucActiveTargetInstance = ucSMBusDetermineInstanceFromTargetAddress( pxSMBusProfile ); + } + + ucInstance = pxSMBusProfile->ucActiveTargetInstance; + if( SMBUS_LAST_SMBUS_INSTANCE >= ucInstance ) + { + if( 0 != ( ( ulInterruptErrorVector ) & ( SMBUS_INTERRUPT_TGT_ERROR_INTERRUPTS ) ) ) + { + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_PHY_TGT_TEXT_TIMEOUT ) + { + vSMBusGenerateEvent_E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_TGT_RX_FIFO_ERROR ) + { + vSMBusGenerateEvent_E_TARGET_RX_FIFO_ERROR_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_TGT_RX_FIFO_OVERFLOW ) + { + vSMBusGenerateEvent_E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_TGT_RX_FIFO_UNDERFLOW ) + { + vSMBusGenerateEvent_E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_TGT_DESC_FIFO_ERROR ) + { + vSMBusGenerateEvent_E_TARGET_DESC_FIFO_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_TGT_DESC_FIFO_OVERFLOW ) + { + vSMBusGenerateEvent_E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_TGT_DESC_FIFO_UNDERFLOW ) + { + vSMBusGenerateEvent_E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_TGT_DESC_ERROR ) + { + vSMBusGenerateEvent_E_TARGET_DESC_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_PHY_UNEXPTD_BUS_IDLE ) + { + vSMBusGenerateEvent_E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_PHY_SMBDAT_LOW_TIMEOUT ) + { + vSMBusGenerateEvent_E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_PHY_SMBCLK_LOW_TIMEOUT ) + { + vSMBusGenerateEvent_E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + } + + if( ulInterruptVector & SMBUS_INTERRUPT_TGT_LOA ) + { + vSMBusGenerateEvent_E_TARGET_LOA_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptVector & SMBUS_INTERRUPT_TGT_PEC_ERROR ) + { + vSMBusGenerateEvent_E_TARGET_PEC_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptVector & SMBUS_INTERRUPT_TGT_READ ) + { + vSMBusGenerateEvent_E_TARGET_READ_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptVector & SMBUS_INTERRUPT_TGT_WRITE ) + { + vSMBusGenerateEvent_E_TARGET_WRITE_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptVector & SMBUS_INTERRUPT_TGT_DESC_FIFO_EMPTY ) + { + } + + if( ulInterruptVector & SMBUS_INTERRUPT_TGT_RX_FIFO_FILL_THRESHOLD ) + { + vSMBusGenerateEvent_E_TARGET_DATA_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptVector & SMBUS_INTERRUPT_TGT_DONE ) + { + vSMBusGenerateEvent_E_TARGET_DONE_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptVector & SMBUS_INTERRUPT_TGT_DESC_FIFO_ALMOST_EMPTY ) + { + vSMBusGenerateEvent_E_DESC_FIFO_ALMOST_EMPTY_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + /* Call the event handler for the target */ + vSMBusEventQueueHandle( pxSMBusProfile ); + } + else + { + /* No target instance is currently active - reset */ + vSMBusHWWriteTgtRxFifoReset( pxSMBusProfile, 1 ); + } + } + + if( 0 != ( ( ulInterruptVector ) & ( SMBUS_INTERRUPT_CTLR_INTERRUPTS | SMBUS_INTERRUPT_ERROR_IRQ ) ) ) + { + ucInstance = pxSMBusProfile->ucInstanceInPlay; + if( SMBUS_LAST_SMBUS_INSTANCE >= ucInstance ) + { + /* Create event and add it to the event queue */ + if( 0 != ( ( ulInterruptErrorVector ) & ( SMBUS_INTERRUPT_CTLR_ERROR_INTERRUPTS ) ) ) + { + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_PHY_CTLR_TEXT_TIMEOUT ) + { + vSMBusGenerateEvent_E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_PHY_CTLR_CEXT_TIMEOUT ) + { + vSMBusGenerateEvent_E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_CTLR_RX_FIFO_ERROR ) + { + vSMBusGenerateEvent_E_CONTROLLER_RX_FIFO_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_CTLR_RX_FIFO_OVERFLOW ) + { + vSMBusGenerateEvent_E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_CTLR_RX_FIFO_UNDERFLOW ) + { + vSMBusGenerateEvent_E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_CTLR_DESC_FIFO_ERROR ) + { + vSMBusGenerateEvent_E_CONTROLLER_DESC_FIFO_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_CTLR_DESC_FIFO_OVERFLOW ) + { + vSMBusGenerateEvent_E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_CTLR_DESC_FIFO_UNDERFLOW ) + { + vSMBusGenerateEvent_E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptErrorVector & SMBUS_ERROR_INTERRUPT_CTLR_DESC_ERROR ) + { + vSMBusGenerateEvent_E_CONTROLLER_DESC_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + } + + if( ulInterruptVector & SMBUS_INTERRUPT_CTLR_LOA ) + { + vSMBusGenerateEvent_E_CONTROLLER_LOA_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptVector & SMBUS_INTERRUPT_CTLR_NACK_ERROR ) + { + vSMBusGenerateEvent_E_CONTROLLER_NACK_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptVector & SMBUS_INTERRUPT_CTLR_PEC_ERROR ) + { + vSMBusGenerateEvent_E_CONTROLLER_PEC_ERROR_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptVector & SMBUS_INTERRUPT_CTLR_DESC_FIFO_EMPTY ) + { + } + + if( ulInterruptVector & SMBUS_INTERRUPT_CTLR_RX_FIFO_FILL_THRESHOLD ) + { + vSMBusGenerateEvent_E_CONTROLLER_DATA_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + if( ulInterruptVector & SMBUS_INTERRUPT_CTLR_DESC_FIFO_ALMOST_EMPTY ) + { + vSMBusGenerateEvent_E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + /* Moved this to last to prevent done happening before receive data */ + if( ulInterruptVector & SMBUS_INTERRUPT_CTLR_DONE ) + { + vSMBusGenerateEvent_E_CONTROLLER_DONE_IRQ( &( pxSMBusProfile->xSMBusInstance[ucInstance] ) ); + } + + /* Call the event handler for the controller */ + vSMBusEventQueueHandle( pxSMBusProfile ); + } + else + { + /* No controller instance is currently active - reset */ + vSMBusHWWriteCtrlRxFifoReset( pxSMBusProfile, 1 ); + vSMBusHWWriteCtrlDescFifoReset( pxSMBusProfile, 1 ); + } + } + + prvvSMBusClearInterrupts( pxSMBusProfile, ulISR_RegisterValue, ulERR_ISR_RegisterValue ); + + /* For debug disable all the Controller interrupts as soon as I receive CTLR_DONE */ + if( SMBUS_INVALID_INSTANCE != ucInstance ) + { + if( ulInterruptVector & SMBUS_INTERRUPT_CTLR_DONE ) + { + vSMBusHWWriteIRQIER( pxSMBusProfile, 0x000001EF ); + } + } + + /* Re-enable the interrupt */ + vSMBusHWWriteIRQGIEEnable( pxSMBusProfile, 1 ); + } +} diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_interrupt_handler.h b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_interrupt_handler.h new file mode 100755 index 00000000..b4dc8b2d --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_interrupt_handler.h @@ -0,0 +1,104 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the defintions of the SMBus Interrupts + * + * @file smbus_interrupt_handler.h + * + */ + +#ifndef _SMBUS_INTERRUPT_HANDLER_H_ +#define _SMBUS_INTERRUPT_HANDLER_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "smbus.h" + +#define SMBUS_INTERRUPT_CTLR_DESC_FIFO_ALMOST_EMPTY ( 1 << 15 ) +#define SMBUS_INTERRUPT_CTLR_RX_FIFO_FILL_THRESHOLD ( 1 << 14 ) +#define SMBUS_INTERRUPT_CTLR_DESC_FIFO_EMPTY ( 1 << 13 ) +#define SMBUS_INTERRUPT_CTLR_DONE ( 1 << 12 ) +#define SMBUS_INTERRUPT_CTLR_PEC_ERROR ( 1 << 11 ) +#define SMBUS_INTERRUPT_CTLR_NACK_ERROR ( 1 << 10 ) +#define SMBUS_INTERRUPT_CTLR_LOA ( 1 << 9 ) +#define SMBUS_INTERRUPT_TGT_DESC_FIFO_ALMOST_EMPTY ( 1 << 8 ) +#define SMBUS_INTERRUPT_TGT_WRITE ( 1 << 7 ) +#define SMBUS_INTERRUPT_TGT_READ ( 1 << 6 ) +#define SMBUS_INTERRUPT_TGT_RX_FIFO_FILL_THRESHOLD ( 1 << 5 ) +#define SMBUS_INTERRUPT_TGT_DESC_FIFO_EMPTY ( 1 << 4 ) +#define SMBUS_INTERRUPT_TGT_DONE ( 1 << 3 ) +#define SMBUS_INTERRUPT_TGT_PEC_ERROR ( 1 << 2 ) +#define SMBUS_INTERRUPT_TGT_LOA ( 1 << 1 ) +#define SMBUS_INTERRUPT_ERROR_IRQ ( 1 << 0 ) +#define SMBUS_ERROR_INTERRUPT_PHY_CTLR_CEXT_TIMEOUT ( 1 << 19 ) +#define SMBUS_ERROR_INTERRUPT_PHY_CTLR_TEXT_TIMEOUT ( 1 << 18 ) +#define SMBUS_ERROR_INTERRUPT_CTLR_RX_FIFO_ERROR ( 1 << 17 ) +#define SMBUS_ERROR_INTERRUPT_CTLR_RX_FIFO_OVERFLOW ( 1 << 16 ) +#define SMBUS_ERROR_INTERRUPT_CTLR_RX_FIFO_UNDERFLOW ( 1 << 15 ) +#define SMBUS_ERROR_INTERRUPT_CTLR_DESC_FIFO_ERROR ( 1 << 14 ) +#define SMBUS_ERROR_INTERRUPT_CTLR_DESC_FIFO_OVERFLOW ( 1 << 13 ) +#define SMBUS_ERROR_INTERRUPT_CTLR_DESC_FIFO_UNDERFLOW ( 1 << 12 ) +#define SMBUS_ERROR_INTERRUPT_CTLR_DESC_ERROR ( 1 << 11 ) +#define SMBUS_ERROR_INTERRUPT_PHY_TGT_TEXT_TIMEOUT ( 1 << 10 ) +#define SMBUS_ERROR_INTERRUPT_TGT_RX_FIFO_ERROR ( 1 << 9 ) +#define SMBUS_ERROR_INTERRUPT_TGT_RX_FIFO_OVERFLOW ( 1 << 8 ) +#define SMBUS_ERROR_INTERRUPT_TGT_RX_FIFO_UNDERFLOW ( 1 << 7 ) +#define SMBUS_ERROR_INTERRUPT_TGT_DESC_FIFO_ERROR ( 1 << 6 ) +#define SMBUS_ERROR_INTERRUPT_TGT_DESC_FIFO_OVERFLOW ( 1 << 5 ) +#define SMBUS_ERROR_INTERRUPT_TGT_DESC_FIFO_UNDERFLOW ( 1 << 4 ) +#define SMBUS_ERROR_INTERRUPT_TGT_DESC_ERROR ( 1 << 3 ) +#define SMBUS_ERROR_INTERRUPT_PHY_UNEXPTD_BUS_IDLE ( 1 << 2 ) +#define SMBUS_ERROR_INTERRUPT_PHY_SMBDAT_LOW_TIMEOUT ( 1 << 1 ) +#define SMBUS_ERROR_INTERRUPT_PHY_SMBCLK_LOW_TIMEOUT ( 1 << 0 ) + +#define SMBUS_INTERRUPT_TGT_INTERRUPTS SMBUS_INTERRUPT_TGT_DESC_FIFO_ALMOST_EMPTY |\ + SMBUS_INTERRUPT_TGT_WRITE |\ + SMBUS_INTERRUPT_TGT_READ |\ + SMBUS_INTERRUPT_TGT_RX_FIFO_FILL_THRESHOLD |\ + SMBUS_INTERRUPT_TGT_DESC_FIFO_EMPTY |\ + SMBUS_INTERRUPT_TGT_DONE |\ + SMBUS_INTERRUPT_TGT_PEC_ERROR |\ + SMBUS_INTERRUPT_TGT_LOA + +#define SMBUS_INTERRUPT_CTLR_INTERRUPTS SMBUS_INTERRUPT_CTLR_DESC_FIFO_ALMOST_EMPTY |\ + SMBUS_INTERRUPT_CTLR_RX_FIFO_FILL_THRESHOLD |\ + SMBUS_INTERRUPT_CTLR_DESC_FIFO_EMPTY |\ + SMBUS_INTERRUPT_CTLR_DONE |\ + SMBUS_INTERRUPT_CTLR_PEC_ERROR |\ + SMBUS_INTERRUPT_CTLR_NACK_ERROR |\ + SMBUS_INTERRUPT_CTLR_LOA + +#define SMBUS_INTERRUPT_CTLR_ERROR_INTERRUPTS SMBUS_ERROR_INTERRUPT_PHY_CTLR_CEXT_TIMEOUT |\ + SMBUS_ERROR_INTERRUPT_PHY_CTLR_TEXT_TIMEOUT |\ + SMBUS_ERROR_INTERRUPT_CTLR_RX_FIFO_ERROR |\ + SMBUS_ERROR_INTERRUPT_CTLR_RX_FIFO_OVERFLOW |\ + SMBUS_ERROR_INTERRUPT_CTLR_RX_FIFO_UNDERFLOW |\ + SMBUS_ERROR_INTERRUPT_CTLR_DESC_FIFO_ERROR |\ + SMBUS_ERROR_INTERRUPT_CTLR_DESC_FIFO_OVERFLOW |\ + SMBUS_ERROR_INTERRUPT_CTLR_DESC_FIFO_UNDERFLOW |\ + SMBUS_ERROR_INTERRUPT_CTLR_DESC_ERROR + +#define SMBUS_INTERRUPT_TGT_ERROR_INTERRUPTS SMBUS_ERROR_INTERRUPT_PHY_TGT_TEXT_TIMEOUT |\ + SMBUS_ERROR_INTERRUPT_TGT_RX_FIFO_ERROR |\ + SMBUS_ERROR_INTERRUPT_TGT_RX_FIFO_OVERFLOW |\ + SMBUS_ERROR_INTERRUPT_TGT_RX_FIFO_UNDERFLOW |\ + SMBUS_ERROR_INTERRUPT_TGT_DESC_FIFO_ERROR |\ + SMBUS_ERROR_INTERRUPT_TGT_DESC_FIFO_OVERFLOW |\ + SMBUS_ERROR_INTERRUPT_TGT_DESC_FIFO_UNDERFLOW |\ + SMBUS_ERROR_INTERRUPT_TGT_DESC_ERROR |\ + SMBUS_ERROR_INTERRUPT_PHY_UNEXPTD_BUS_IDLE |\ + SMBUS_ERROR_INTERRUPT_PHY_SMBDAT_LOW_TIMEOUT |\ + SMBUS_ERROR_INTERRUPT_PHY_SMBCLK_LOW_TIMEOUT + +#define SMBUS_INTERRUPT_TGT_READ_OR_WRITE_INTERRUPTS SMBUS_INTERRUPT_TGT_WRITE |\ + SMBUS_INTERRUPT_TGT_READ + +#ifdef __cplusplus +} +#endif + +#endif /* _SMBUS_INTERRUPT_HANDLER_H_ */ diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_state.c b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_state.c new file mode 100755 index 00000000..ac994e6b --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_state.c @@ -0,0 +1,3997 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the state machine implementation + * for the SMBus driver. + * + * @file smbus_state.c + * + */ + +#include "smbus.h" +#include "smbus_internal.h" +#include "smbus_state.h" +#include "smbus_event.h" +#include "smbus_action.h" +#include "smbus_hardware_access.h" +#include "smbus_hardware.h" + +char* pcStateSMBusStateInitial = "SMBUS_STATE_INITIAL"; +char* pcStateSMBusStateAwaitingCommandByte = "SMBUS_STATE_AWAITING_COMMAND_BYTE"; +char* pcStateSMBusStateAwaitingBlockSize = "SMBUS_STATE_AWAITING_BLOCK_SIZE"; +char* pcStateSMBusStateAwaitingData = "SMBUS_STATE_AWAITING_DATA"; +char* pcStateSMBusStateAwaitingRead = "SMBUS_STATE_AWAITING_READ"; +char* pcStateSMBusStateReadyToSendByte = "SMBUS_STATE_READY_TO_SEND_BYTE"; +char* pcStateSMBusStateCheckIfPecRequired = "SMBUS_STATE_CHECK_IF_PEC_REQUIRED"; +char* pcStateSMBusStateAwaitingDone = "SMBUS_STATE_AWAITING_DONE"; +char* pcStateSMBusStateControllerSendCommand = "SMBUS_STATE_CONTROLLER_SEND_COMMAND"; +char* pcStateSMBusStateControllerSendReadStart = "SMBUS_STATE_CONTROLLER_SEND_READ_START"; +char* pcStateSMBusStateControllerReadBlockSize = "SMBUS_STATE_CONTROLLER_READ_BLOCK_SIZE"; +char* pcStateSMBusStateControllerReadByte = "SMBUS_STATE_CONTROLLER_READ_BYTE"; +char* pcStateSMBusStateControllerReadPec = "SMBUS_STATE_CONTROLLER_READ_PEC"; +char* pcStateSMBusStateControllerReadDone = "SMBUS_STATE_CONTROLLER_READ_DONE"; +char* pcStateSMBusStateControllerWriteByte = "SMBUS_STATE_CONTROLLER_WRITE_BYTE"; +char* pStateUnknown = "SMBUS_STATE_UNKNOWN"; + +/********************** Static function declarations ***************************/ + +/****************************************************************************** +* +* @brief Log an error when an event the FSM does not expect arrives +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is the latest event being handled +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vSMBusLogUnexpected( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Move current state to previous state and set the newstate as current +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param xNewState is the latest FSM state to be recorded +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vSMBusNextStateDecoder( SMBUS_INSTANCE_TYPE* pxSMBusInstance, SMBus_State_Type xNewState ); + +/****************************************************************************** +* +* @brief Perform actions on receiving an Prepare To ARP command +* Clear AR flag +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vSMBusARPPrepareToARP( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief Perform actions on receiving an ARP reset device command +* AV and AR flags will be set dependent on the ARP capabilities +* of the instance +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vSMBusARPResetDevice( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief Write a descriptor to the IP to send a NACK +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vSMBusSendNACK( SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief This function swaps the locations of two SMBus instance numbers +* within an array of SMBus instances +* +* @param pucInstanceA is an SMBus instance number +* @param pucInstanceB is an SMBus instance number +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vInstanceSwap( uint8_t* pucInstanceA, uint8_t* pucInstanceB ); + +/****************************************************************************** +* +* @brief This function takes an array of SMBus instances +* It walks through that array and reorders the instances +* in the order that they should respond to a ARP GetUDID general command +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure +* @param pucInstanceIDArray is the array of SMBus instance numbers +* @param ucArraySize is nmber of SMBus instance numbers in the array +* @param ucUDIDByteIndex is the number of UDID bytes needed to determine the order +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vUDIDInstanceSort( SMBUS_PROFILE_TYPE* pxTheProfile, uint8_t pucInstanceIDArray[], uint8_t ucArraySize , uint8_t ucUDIDByteIndex ); + +/****************************************************************************** +* +* @brief This function walks through each instance to determine if +* the UDID transmitted matches any one of the active SMBus instances +* +* @param pxSMBusProfile is a pointer to the SMBus profile structure +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* +* @return SMBUS_FALSE If no match is found +* SMBUS_TRUE If a match is found +* +* @note None. +* +*****************************************************************************/ +static uint8_t ucCheckAtLeastOneMatchFound( SMBUS_PROFILE_TYPE* pxSMBusProfile, SMBUS_INSTANCE_TYPE* pxSMBusInstance ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is Initial +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateInitial( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is AwaitingCommandByte +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateAwaitingCommandByte( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is AwaitingRead +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateAwaitingRead( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ReadyToSendByte +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateReadyToSendByte( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is CheckIfPECRequired +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateCheckIfPECRequired( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is AwaitingDone +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateAwaitingDone( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is AwaitingData +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateAwaitingData( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is AwaitingBlockSize +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateAwaitingBlockSize( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerSendCommand +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerSendCommand( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerWriteByte +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerWriteByte( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerSendReadStart +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerSendReadStart( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerReadBlockSize +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerReadBlockSize( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerReadByte +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerReadByte( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerReadPEC +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerReadPEC( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerReadDone +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerReadDone( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/*******************************************************************************/ + +/* Descriptor helper functions */ + +/****************************************************************************** +* +* @brief Is a conversion function from the state enum to character string +* to be used by logging functions +* +*****************************************************************************/ +char* pcStateToString( uint8_t ucState ) +{ + char* pResult = NULL; + + switch( ucState ) + { + case SMBUS_STATE_INITIAL: + pResult = pcStateSMBusStateInitial; + break; + + case SMBUS_STATE_AWAITING_COMMAND_BYTE: + pResult = pcStateSMBusStateAwaitingCommandByte; + break; + + case SMBUS_STATE_AWAITING_BLOCK_SIZE: + pResult = pcStateSMBusStateAwaitingBlockSize; + break; + + case SMBUS_STATE_AWAITING_DATA: + pResult = pcStateSMBusStateAwaitingData; + break; + + case SMBUS_STATE_AWAITING_READ: + pResult = pcStateSMBusStateAwaitingRead; + break; + + case SMBUS_STATE_READY_TO_SEND_BYTE: + pResult = pcStateSMBusStateReadyToSendByte; + break; + + case SMBUS_STATE_CHECK_IF_PEC_REQUIRED: + pResult = pcStateSMBusStateCheckIfPecRequired; + break; + + case SMBUS_STATE_AWAITING_DONE: + pResult = pcStateSMBusStateAwaitingDone; + break; + + case SMBUS_STATE_CONTROLLER_SEND_COMMAND: + pResult = pcStateSMBusStateControllerSendCommand; + break; + + case SMBUS_STATE_CONTROLLER_SEND_READ_START: + pResult = pcStateSMBusStateControllerSendReadStart; + break; + + case SMBUS_STATE_CONTROLLER_READ_BLOCK_SIZE: + pResult = pcStateSMBusStateControllerReadBlockSize; + break; + + case SMBUS_STATE_CONTROLLER_READ_BYTE: + pResult = pcStateSMBusStateControllerReadByte; + break; + + case SMBUS_STATE_CONTROLLER_READ_PEC: + pResult = pcStateSMBusStateControllerReadPec; + break; + + case SMBUS_STATE_CONTROLLER_READ_DONE: + pResult = pcStateSMBusStateControllerReadDone; + break; + + case SMBUS_STATE_CONTROLLER_WRITE_BYTE: + pResult = pcStateSMBusStateControllerWriteByte; + break; + + default: + pResult = pStateUnknown; + break; + } + + return pResult; +} + +/****************************************************************************** +* +* @brief Log an error when an event the FSM does not expect arrives +* +*****************************************************************************/ +static void vSMBusLogUnexpected( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + if( NULL != pxSMBusInstance ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, + pxSMBusInstance->xState, ucAnyEvent ); + } +} + +/****************************************************************************** +* +* @brief Move current state to previous state and set the newstate as current +* +*****************************************************************************/ +static void vSMBusNextStateDecoder( SMBUS_INSTANCE_TYPE* pxSMBusInstance, SMBus_State_Type xNewState ) +{ + if( NULL != pxSMBusInstance ) + { + pxSMBusInstance->xPreviousState = pxSMBusInstance->xState; + pxSMBusInstance->xState = xNewState; + } +} + +/****************************************************************************** +* +* @brief Perform actions on receiving an Prepare To ARP command +* Clear AR flag +* +*****************************************************************************/ +static void vSMBusARPPrepareToARP( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + /* Clear the AR Flag */ + pxSMBusInstance->ucARFlag = SMBUS_FALSE; + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucSMBusAddress, __LINE__ ); + /* No change to AV Flag */ + } +} + +/****************************************************************************** +* +* @brief Perform actions on receiving an ARP reset device command +* AV and AR flags will be set dependent on the ARP capabilities +* of the instance +* +*****************************************************************************/ +static void vSMBusARPResetDevice( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + /* Clear the AR Flag */ + pxSMBusInstance->ucARFlag = SMBUS_FALSE; + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucSMBusAddress, __LINE__ ); + + if( ( SMBUS_ARP_NON_ARP_CAPABLE != pxSMBusInstance->xARPCapability ) && + ( SMBUS_ARP_CAPABILITY_UNKNOWN != pxSMBusInstance->xARPCapability ) ) + { + if( SMBUS_UDID_FIXED_ADDRESS == ( pxSMBusInstance->ucUDID[SMBUS_UDID_DEVICE_CAPABILITIES_BYTE] & SMBUS_UDID_ADDRESS_TYPE_MASK ) ) + { + /* DTA */ + pxSMBusInstance->ucAVFlag = SMBUS_TRUE; + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucSMBusAddress, __LINE__ ); + } + else if( SMBUS_UDID_DYNAMIC_AND_PERSISTENT == ( pxSMBusInstance->ucUDID[SMBUS_UDID_DEVICE_CAPABILITIES_BYTE] & SMBUS_UDID_ADDRESS_TYPE_MASK ) ) + { + /* non-PTA */ + if( SMBUS_TRUE == pxSMBusInstance->ucAVFlag ) + { + /* Disable the HW, to take this address off the bus */ + vSMBusHWWriteTgtControlEnable( pxSMBusInstance->pxSMBusProfile, pxSMBusInstance->ucUDIDMatchedInstance, 0 ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucSMBusAddress, __LINE__ ); + } + + pxSMBusInstance->ucAVFlag = SMBUS_FALSE; + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucSMBusAddress, __LINE__ ); + } + /* DYNAMIC_AND_PERSISTENT we don't care */ + } + } +} + +/****************************************************************************** +* +* @brief Write a descriptor to the IP to send a NACK +* +*****************************************************************************/ +static void vSMBusSendNACK( SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + if( NULL != pxSMBusInstance ) + { + ucSMBusTargetWriteDescriptorNACK( pxSMBusInstance->pxSMBusProfile ); + pxSMBusInstance->ucNackSent = SMBUS_TRUE; + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is Initial +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateInitial( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_TARGET_WRITE_IRQ: + if( SMBUS_FALSE == pxSMBusInstance->ucSimpleDevice ) + { + if( SMBUS_TRUE == pxSMBusInstance->ulI2CDevice ) + { + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DATA ); + } + else + { + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_COMMAND_BYTE ); + } + } + else + { + /* For a simple device a WRITE_IRQ can only be SMBUS_PROTOCOL_SEND_BYTE */ + pxSMBusInstance->xProtocol = SMBUS_PROTOCOL_SEND_BYTE; + pxSMBusInstance->usExpectedByteCount = 1; + pxSMBusInstance->ucExpectedByteCountPart = 1; + vSMBusHWWriteRxFifoFillThresholdFillThresh( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->usExpectedByteCount ); + + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS == ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + pxSMBusInstance->usDescriptorsSent++; + } + + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DATA ); + } + break; + + case E_TARGET_READ_IRQ: + + if( SMBUS_FALSE == pxSMBusInstance->ucSimpleDevice ) + { + if( SMBUS_TRUE == pxSMBusInstance->ulI2CDevice ) + { + vSMBusHandleActionGetI2CDataFromApplication( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_READY_TO_SEND_BYTE ); + } + else + { + /* although this is unexpected, transmit data byte to avoid hanging the bus */ + ucSMBusTargetReadDescriptorRead( pxSMBusInstance->pxSMBusProfile, SMBUS_UNEXPECTED_READ_DESCRIPTOR_DATA ); + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + } + } + else + { + /* For a simple device a READ_IRQ can only be SMBUS_PROTOCOL_RECEIVE_BYTE */ + pxSMBusInstance->xProtocol = SMBUS_PROTOCOL_RECEIVE_BYTE; + vSMBusHandleActionGetDataFromApplication( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_READY_TO_SEND_BYTE ); + } + break; + + case E_SEND_NEXT_BYTE: + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + ulSMBusHWReadPHYCtrlDbgState( pxTheProfile ), __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + ulSMBusHWReadCtrlDbgState( pxTheProfile ), __LINE__ ); + + /* Log Controller Message Start */ + if( SMBUS_PROTOCOL_NONE != pxSMBusInstance->xProtocol ) + { + pxSMBusInstance->ulMessagesInitiated[pxSMBusInstance->xProtocol]++; + } + + switch( pxSMBusInstance->xProtocol ) + { + case SMBUS_PROTOCOL_QUICK_COMMAND_LO: + ucSMBusControllerWriteDescriptorQuickWrite( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSMBusDestinationAddress ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, 0x1 ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + break; + + case SMBUS_PROTOCOL_QUICK_COMMAND_HI: + ucSMBusControllerReadDescriptorQuickRead( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSMBusDestinationAddress ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, 0x1 ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + break; + + case SMBUS_PROTOCOL_RECEIVE_BYTE: + pxSMBusInstance->usExpectedByteCount = 1; + pxSMBusInstance->ucExpectedByteCountPart = 1; + vSMBusHandleActionCreateEventSendNextByte( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_SEND_READ_START ); + break; + + case I2C_PROTOCOL_WRITE: + case I2C_PROTOCOL_WRITE_READ: + ucSMBusControllerWriteDescriptorStartWrite( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSMBusDestinationAddress ); + vSMBusHandleActionCreateEventSendNextByte( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_WRITE_BYTE ); + break; + + case I2C_PROTOCOL_READ: + ucSMBusControllerReadDescriptorStart( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSMBusDestinationAddress ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + pxSMBusInstance->ucExpectedByteCountPart = + ( pxSMBusInstance->usExpectedByteCount < SMBUS_HALF_FIFO_DEPTH ? pxSMBusInstance->usExpectedByteCount : SMBUS_HALF_FIFO_DEPTH ); + + /* Set to no more than 32, half the depth of the FIFO */ + if( 0 < pxSMBusInstance->ucExpectedByteCountPart ) /* If its zero leave threshold at 1 */ + { + vSMBusHWWriteCtrlRxFifoFillThreshold( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucExpectedByteCountPart ); + } + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_READ_BYTE ); + break; + + default: + /* Tell the IP to send the WRITE_START */ + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucSMBusDestinationAddress, __LINE__ ); + ucSMBusControllerWriteDescriptorStartWrite( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSMBusDestinationAddress ); + vSMBusHandleActionCreateEventSendNextByte( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_SEND_COMMAND ); + break; + } + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief This function swaps the locations of two SMBus instance numbers +* within an array of SMBus instances +* +*****************************************************************************/ +static void vInstanceSwap( uint8_t* pucInstanceA, uint8_t* pucInstanceB ) +{ + if( ( NULL != pucInstanceA ) && ( NULL != pucInstanceB ) ) + { + uint8_t ucTempInstance = *pucInstanceA; + *pucInstanceA = *pucInstanceB; + *pucInstanceB = ucTempInstance; + } +} + +/****************************************************************************** +* +* @brief This function takes an array of SMBus instances +* It walks through that array and reorders the instances +* in the order that they should respond to a ARP GetUDID general command +* +*****************************************************************************/ +static void vUDIDInstanceSort( SMBUS_PROFILE_TYPE* pxTheProfile, uint8_t pucInstanceIDArray[], uint8_t ucArraySize , uint8_t ucUDIDByteIndex ) +{ + uint8_t ucOuterArrayElement = 0; + uint8_t ucInnerArrayElement = 0; + uint8_t ucSmallestElement = 0; + + if( NULL != pxTheProfile ) + { + for( ucOuterArrayElement = 0; ucOuterArrayElement < ucArraySize - 1; ucOuterArrayElement++ ) + { + /* Find the minimum element in unsorted array */ + ucSmallestElement = ucOuterArrayElement; + for( ucInnerArrayElement = ucOuterArrayElement + 1; ucInnerArrayElement < ucArraySize; ucInnerArrayElement++ ) + { + if( pxTheProfile->xSMBusInstance[pucInstanceIDArray[ucInnerArrayElement]].ucUDID[ucUDIDByteIndex] < + pxTheProfile->xSMBusInstance[pucInstanceIDArray[ucSmallestElement]].ucUDID[ucUDIDByteIndex] ) + { + ucSmallestElement = ucInnerArrayElement; + } + } + /* Swap the instance of the smallest found element with the instance of the first element */ + vInstanceSwap( &pucInstanceIDArray[ucSmallestElement], &pucInstanceIDArray[ucOuterArrayElement] ); + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is AwaitingCommandByte +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateAwaitingCommandByte( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_INSTANCE_TYPE* pxMatchedInstance = NULL; + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + uint8_t ucOKToACK = SMBUS_FALSE; + int i = 0; + int j = 0; + SMBUS_INSTANCE_TYPE* pxInstanceJ = NULL; + SMBUS_INSTANCE_TYPE* pxInstanceJPlus = NULL; + uint8_t ucUdidListSize = 0; + uint8_t ucUdidList[SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES] = { 0 }; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_DESC_FIFO_ALMOST_EMPTY_IRQ: + break; + + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_TARGET_DATA_IRQ: + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucSMBusAddress, __LINE__ ); + if( SMBUS_NOTIFY_ARP_MASTER_ADDRESS == pxSMBusInstance->ucSMBusAddress ) /* Notify ARP Master Instance */ + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucSMBusAddress, __LINE__ ); + pxSMBusInstance->xProtocol = SMBUS_PROTOCOL_HOST_NOTIFY; + pxSMBusInstance->ucCommand = ulSMBusHWReadTgtRxFifoPayload( pxSMBusInstance->pxSMBusProfile ); + pxSMBusInstance->ucSMBusSenderAddress = pxSMBusInstance->ucCommand; + pxSMBusInstance->usExpectedByteCount = 2; + pxSMBusInstance->ucExpectedByteCountPart = 2; + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, + 0, __LINE__ ); + } + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DATA ); + } + else if( SMBUS_DEVICE_DEFAULT_ARP_ADDRESS == pxSMBusInstance->ucSMBusAddress ) /* ARP Instance */ + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucSMBusAddress, __LINE__ ); + if( SMBUS_ACTION_ARP_PROTOCOL_UNDETERMINED == ucSMBusHandleActionGetARPProtocol( pxSMBusInstance ) ) + { + vSMBusSendNACK( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + else + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->xProtocol, __LINE__ ); + + if( SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS == pxSMBusInstance->xProtocol ) + { + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + pxTheProfile->ucUDIDMatch[i] = SMBUS_TRUE; + } + + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, + 0, __LINE__ ); + } + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_BLOCK_SIZE ); + } + + if( ( SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_RESET_DEVICE == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED == pxSMBusInstance->xProtocol ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->xProtocol, __LINE__ ); + pxSMBusInstance->usExpectedByteCount = 0; + pxSMBusInstance->ucExpectedByteCountPart = 0; + + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + /* Check that at least one target is ARP capable */ + pxMatchedInstance = &( pxTheProfile->xSMBusInstance[i] ); + if( ( SMBUS_ARP_CAPABLE == pxMatchedInstance->xARPCapability ) || + ( SMBUS_ARP_FIXED_AND_DISCOVERABLE == pxMatchedInstance->xARPCapability ) ) + { + /* If the ARP controller is on the same IP don't change it's settings */ + if( pxTheProfile->ucInstanceInPlay != i ) + { + ucOKToACK = SMBUS_TRUE; + break; + } + } + } + + /* ACK the command */ + if( SMBUS_TRUE == ucOKToACK ) + { + if( SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED == pxSMBusInstance->xProtocol ) + { + ucOKToACK = SMBUS_FALSE; + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + /* Find the instance corresponding to the directed address */ + pxMatchedInstance = &( pxTheProfile->xSMBusInstance[i] ); + if( pxMatchedInstance->ucSMBusAddress == pxSMBusInstance->ucMatchedSMBusAddress ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxMatchedInstance->ucAVFlag, __LINE__ ); + /* Now for that instance, check if its AV flag is set */ + if( SMBUS_TRUE == pxMatchedInstance->ucAVFlag ) + { + ucOKToACK = SMBUS_TRUE; + } + break; + } + } + + if( SMBUS_TRUE == ucOKToACK ) + { + /* ACK the command */ + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, + 0, __LINE__ ); + } + ucSMBusTargetWriteDescriptorPEC( pxSMBusInstance->pxSMBusProfile ); + pxSMBusInstance->ucPECSent = SMBUS_TRUE; + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + else + { + /* NACK the command */ + vSMBusSendNACK( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } + else + { + /* ACK the command */ + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, + 0, __LINE__ ); + } + ucSMBusTargetWriteDescriptorPEC( pxSMBusInstance->pxSMBusProfile ); + pxSMBusInstance->ucPECSent = SMBUS_TRUE; + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } + else + { + /* NACK the command */ + vSMBusSendNACK( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } /* SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP, SMBUS_ARP_PROTOCOL_RESET_DEVICE and SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED */ + + if( SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED == pxSMBusInstance->xProtocol ) + { + pxSMBusInstance->usSendDataSize = SMBUS_GET_UDID_MSG_LENGTH; + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucMatchedSMBusAddress, __LINE__ ); + + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + pxMatchedInstance = &( pxTheProfile->xSMBusInstance[i] ); + + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxMatchedInstance->ucSMBusAddress, __LINE__ ); + + /* If we have a matched address and it is ARP capable */ + if( pxMatchedInstance->ucSMBusAddress == pxSMBusInstance->ucMatchedSMBusAddress ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxMatchedInstance->xARPCapability, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxMatchedInstance->ucAVFlag, __LINE__ ); + + if( SMBUS_ARP_NON_ARP_CAPABLE != pxMatchedInstance->xARPCapability ) + { + if( SMBUS_TRUE == pxMatchedInstance->ucAVFlag ) + { + ucOKToACK = SMBUS_TRUE; + + /* Byte Count */ + pxSMBusInstance->ucSendData[0] = SMBUS_GET_UDID_DATA_LENGTH; + + /* Copy the UDID into send buffer */ + for( j = 0; j < SMBUS_UDID_LENGTH; j++ ) + { + pxSMBusInstance->ucSendData[j + 1] = pxMatchedInstance->ucUDID[SMBUS_UDID_DEVICE_CAPABILITIES_BYTE - j]; + } + + /* Device Slave Address - Bit 0 in Slave Address Field should be a 1 */ + pxSMBusInstance->ucSendData[SMBUS_UDID_ASSIGNED_ADDRESS_BYTE] = + ( ( pxMatchedInstance->ucSMBusAddress << 1 ) | SMBUS_UDID_ASSIGNED_ADDRESS_BIT0 ); + break; + } + } + } + } + if( SMBUS_TRUE == ucOKToACK ) + { + /* ACK the command */ + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, 0, __LINE__ ); + } + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_READ ); + } + else + { + /* NACK the command */ + vSMBusSendNACK( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } /* SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED */ + + if( SMBUS_ARP_PROTOCOL_GET_UDID == pxSMBusInstance->xProtocol ) + { + pxSMBusInstance->usSendDataSize = SMBUS_GET_UDID_MSG_LENGTH; + + /* Look up UUID to send */ + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, i, __LINE__ ); + pxMatchedInstance = &( pxTheProfile->xSMBusInstance[i] ); + if( SMBUS_TRUE == pxMatchedInstance->ucInstanceInUse ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxMatchedInstance->xARPCapability, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxMatchedInstance->ucARFlag, __LINE__ ); + /* If we have a matched address and it is ARP capable */ + if( ( SMBUS_ARP_CAPABLE == pxMatchedInstance->xARPCapability ) || + ( SMBUS_ARP_FIXED_AND_DISCOVERABLE == pxMatchedInstance->xARPCapability ) ) + { + /* If the ARP controller is on the same IP don't change it's settings */ + if( pxTheProfile->ucInstanceInPlay != i ) + { + if( SMBUS_FALSE == pxMatchedInstance->ucARFlag ) + { + /* Add this instance to a list */ + ucUdidList[ucUdidListSize++] = i; + + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + ucUdidListSize, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + i, __LINE__ ); + } + } + } + } + } + + /* Now go through the list and eliminate the keep instances with the smallest UDID */ + /* Start with UDID byte 15 and keep iterating til only 1 instance remains */ + if( SMBUS_ZERO_ELEMENTS < ucUdidListSize ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + ucUdidListSize, __LINE__ ); + if( SMBUS_SINGLE_ELEMENT != ucUdidListSize ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + ucUdidListSize, __LINE__ ); + for( i = SMBUS_UDID_DEVICE_CAPABILITIES_BYTE; i >= 0; i-- ) + { + vUDIDInstanceSort( pxTheProfile, ucUdidList, ucUdidListSize, i ); + + /* Check if 2 or more elements are equal and remove array instances that are greater than the minimum */ + for( j = 0; j < ucUdidListSize; j++ ) + { + pxInstanceJ = &( pxTheProfile->xSMBusInstance[ucUdidList[j]] ); + pxInstanceJPlus = &( pxTheProfile->xSMBusInstance[ucUdidList[j+1]] ); + + if ( pxInstanceJ->ucUDID[i] != pxInstanceJPlus->ucUDID[i] ) + { + /* The two bytes don't match so we can break here */ + ucUdidListSize = j + 1; + break; + } + } + + /* Break out of the loop as soon as we have determined the smallest UDID ie. array size is 1 */ + if ( SMBUS_SINGLE_ELEMENT == ucUdidListSize ) + { + break; + } + } + } + + /* Now respond with the UDID of the instance identified */ + pxMatchedInstance = &( pxTheProfile->xSMBusInstance[ucUdidList[0]] ); + + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + ucUdidList[0], SMBUS_LOG_EVENT_DEBUG, + pxMatchedInstance->ucSMBusAddress, __LINE__ ); + + ucOKToACK = SMBUS_TRUE; + + /* Byte Count */ + pxSMBusInstance->ucSendData[0] = SMBUS_GET_UDID_DATA_LENGTH; + + /* Copy the UDID into send buffer */ + for( j = 0; j < SMBUS_UDID_LENGTH; j++ ) + { + pxSMBusInstance->ucSendData[j + 1] = pxMatchedInstance->ucUDID[SMBUS_UDID_DEVICE_CAPABILITIES_BYTE - j]; + } + + /* Device Slave Address */ + /* If AV flag is clear then Data 17 field should be all 1s */ + if( SMBUS_FALSE == pxMatchedInstance->ucAVFlag ) + { + pxSMBusInstance->ucSendData[SMBUS_UDID_ASSIGNED_ADDRESS_BYTE] = SMBUS_UDID_DTA_AV_FLAG_CLEAR; + } + else + { + /* Bit 0 in Slave Address Field should be a 1 */ + pxSMBusInstance->ucSendData[SMBUS_UDID_ASSIGNED_ADDRESS_BYTE] = + ( ( pxMatchedInstance->ucSMBusAddress << 1 ) | SMBUS_UDID_DTA_BIT_0_SET ); + } + } + + if( SMBUS_TRUE == ucOKToACK ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxMatchedInstance->ucSMBusAddress, __LINE__ ); + /* ACK the command */ + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, + 0, __LINE__ ); + } + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_READ ); + } + else + { + vSMBusSendNACK( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } /* SMBUS_ARP_PROTOCOL_GET_UDID */ + } + } + else /* SMBus Devices */ + { + /* Need protocol now. */ + vSMBusHandleActionGetProtocol( pxSMBusInstance ); + + switch( pxSMBusInstance->xProtocol ) + { + case SMBUS_PROTOCOL_BLOCK_READ: + case SMBUS_PROTOCOL_READ_64: + case SMBUS_PROTOCOL_READ_32: + case SMBUS_PROTOCOL_READ_WORD: + case SMBUS_PROTOCOL_READ_BYTE: + vSMBusHandleActionGetDataFromApplication( pxSMBusInstance ); + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, + 0, __LINE__ ); + } + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_READ ); + break; + + case SMBUS_PROTOCOL_WRITE_64: + pxSMBusInstance->usExpectedByteCount = 8; + pxSMBusInstance->ucExpectedByteCountPart = 8; + break; + + case SMBUS_PROTOCOL_WRITE_32: + pxSMBusInstance->usExpectedByteCount = 4; + pxSMBusInstance->ucExpectedByteCountPart = 4; + break; + + case SMBUS_PROTOCOL_WRITE_WORD: + + case SMBUS_PROTOCOL_PROCESS_CALL: + pxSMBusInstance->usExpectedByteCount = 2; + pxSMBusInstance->ucExpectedByteCountPart = 2; + break; + + case SMBUS_PROTOCOL_WRITE_BYTE: + pxSMBusInstance->usExpectedByteCount = 1; + pxSMBusInstance->ucExpectedByteCountPart = 1; + break; + + case SMBUS_PROTOCOL_BLOCK_WRITE: + case SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL: + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_ERROR, + 0, __LINE__ ); + } + /* Don't increment Descriptors_Sent. We'll do that once we know the block size. */ + /* pxSMBusInstance->Descriptors_Sent++; */ + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_BLOCK_SIZE ); + break; + + default: + /* If Protocol is not recognized then NACK */ + vSMBusSendNACK( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + break; + } + + switch( pxSMBusInstance->xProtocol ) + { + case SMBUS_PROTOCOL_WRITE_64: + case SMBUS_PROTOCOL_WRITE_32: + case SMBUS_PROTOCOL_WRITE_WORD: + case SMBUS_PROTOCOL_WRITE_BYTE: + case SMBUS_PROTOCOL_PROCESS_CALL: + vSMBusHWWriteRxFifoFillThresholdFillThresh( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->usExpectedByteCount ); + for( i = 0; i < pxSMBusInstance->usExpectedByteCount + 1; i++ ) + { + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS == ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + pxSMBusInstance->usDescriptorsSent++; + } + } + + /* Check if more data is already waiting */ + if( SMBUS_RX_FIFO_IS_EMPTY != ulSMBusHWReadTgtRxFifoStatusEmpty( pxSMBusInstance->pxSMBusProfile ) ) + { + /* If FIFO isn't empty generate an E_TARGET_DATA_IRQ event + and handle in SMBUS_STATE_AWAITING_DATA */ + vSMBusGenerateEvent_E_TARGET_DATA_IRQ( pxSMBusInstance ); + } + + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DATA ); + break; + + default: + break; + } + } + + if( SMBUS_PROTOCOL_NONE != pxSMBusInstance->xProtocol ) + { + pxSMBusInstance->ulMessagesInitiated[pxSMBusInstance->xProtocol]++; + } + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is AwaitingRead +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateAwaitingRead( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + uint8_t ucCurrentFill = 0; + int i = 0; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_DESC_FIFO_ALMOST_EMPTY_IRQ: + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_INFO, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usDescriptorsSent, __LINE__ ); + + ucCurrentFill = ulSMBusHWReadTgtDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ( SMBUS_FIFO_DEPTH - ucCurrentFill ); i++ ) + { + if( pxSMBusInstance->usDescriptorsSent < pxSMBusInstance->usExpectedByteCount ) + { + uint8_t ucNoStatusCheck = SMBUS_TRUE; + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, ucNoStatusCheck ) ) + { + break; + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + } + } + break; + + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_TARGET_READ_IRQ: + if( ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_READ == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED == pxSMBusInstance->xProtocol ) ) + { + /* vSMBusHandleActionCreateEventSendNextByte( pxSMBusInstance ); */ + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_READY_TO_SEND_BYTE ); + } + break; + + case E_TARGET_DATA_IRQ: + /* DATA_IRQ may have been added to the queue at the same time as READ_IRQ */ + /* Ignore for now DATA_IRQ will assert again */ + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ReadyToSendByte +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateReadyToSendByte( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + uint8_t ucCurrentFill = 0; + int i = 0; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_DESC_FIFO_ALMOST_EMPTY_IRQ: + if( ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_READ == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_RECEIVE_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED == pxSMBusInstance->xProtocol ) || + ( SMBUS_TRUE == pxSMBusInstance->ulI2CDevice ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usSendIndex, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usSendDataSize, __LINE__ ); + + /* Read how much space is available in the descriptor FIFO and write that number of ACKs */ + ucCurrentFill = ulSMBusHWReadTgtDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ( SMBUS_FIFO_DEPTH - ucCurrentFill ); i++ ) + { + if( pxSMBusInstance->usSendIndex < pxSMBusInstance->usSendDataSize ) + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusTargetReadDescriptorRead( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSendData[pxSMBusInstance->usSendIndex] ) ) + { + break; + } + else + { + pxSMBusInstance->usSendIndex++; + } + } + } + + if( pxSMBusInstance->usSendIndex == pxSMBusInstance->usSendDataSize ) + { + vSMBusHandleActionCreateEventIsPECRequired( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CHECK_IF_PEC_REQUIRED ); + } + } + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is CheckIfPECRequired +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateCheckIfPECRequired( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_IS_PEC_REQUIRED: + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, + SMBUS_LOG_EVENT_DEBUG, pxSMBusInstance->xProtocol, __LINE__ ); + if( ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_READ == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_RECEIVE_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_TRUE == pxSMBusInstance->ulI2CDevice ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucPECRequired, __LINE__ ); + if( SMBUS_TRUE == pxSMBusInstance->ucPECRequired ) + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusTargetReadDescriptorPECRead( pxSMBusInstance->pxSMBusProfile ) ) + { + vSMBusHandleActionCreateEventIsPECRequired( pxSMBusInstance ); + } + else + { + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } + else + { + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } + + if( ( SMBUS_ARP_PROTOCOL_GET_UDID == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED == pxSMBusInstance->xProtocol ) ) + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusTargetReadDescriptorPECRead( pxSMBusInstance->pxSMBusProfile ) ) + { + vSMBusHandleActionCreateEventIsPECRequired( pxSMBusInstance ); + } + else + { + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is AwaitingDone +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateAwaitingDone( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_INSTANCE_TYPE* pMatched_Instance = NULL; + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + uint8_t ucCurrentFill = 0; + int i = 0; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ: + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usDescriptorsSent, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usExpectedByteCount, __LINE__ ); + break; + + case E_DESC_FIFO_ALMOST_EMPTY_IRQ: + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usDescriptorsSent, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usExpectedByteCount, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usReceiveIndex, __LINE__ ); + + pxSMBusInstance->ucFifoEmptyWhileInDoneCount++; + + if( SMBUS_MAX_FIFO_EMPTY_WHILE_IN_DONE < pxSMBusInstance->ucFifoEmptyWhileInDoneCount ) + { + /* We have an issue */ + vSMBusSendNACK( pxSMBusInstance ); + } + else + { + /* We may have got here as all data has arrived but we may not have sent all ACKs necessary */ + /* However if we NACK in the middle of ASSIGN_ARP don't send more descriptors */ + if( SMBUS_FALSE == pxSMBusInstance->ucNackSent ) + { + ucCurrentFill = ulSMBusHWReadTgtDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ( SMBUS_FIFO_DEPTH - ucCurrentFill ); i++ ) + { + if( pxSMBusInstance->usDescriptorsSent < pxSMBusInstance->usExpectedByteCount ) + { + uint8_t ucNoStatusCheck = SMBUS_TRUE; + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, ucNoStatusCheck ) ) + { + break; + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + } + } + } + + /* Maybe a PEC arrived */ + if( pxSMBusInstance->usReceiveIndex >= pxSMBusInstance->usExpectedByteCount + 1 ) + { + /* Should I have received a PEC */ + if( ( SMBUS_TRUE == pxSMBusInstance->ucPECRequired ) && + ( SMBUS_FALSE == pxSMBusInstance->ucPECSent ) ) + { + ucSMBusTargetWriteDescriptorPEC( pxSMBusInstance->pxSMBusProfile ); + pxSMBusInstance->ucPECSent = SMBUS_TRUE; + } + else + { + /* Send a NACK and wait on DONE */ + if( SMBUS_TRUE == pxSMBusInstance->ucSimpleDevice ) + { + vSMBusSendNACK( pxSMBusInstance ); + } + } + } + } + break; + + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_TARGET_READ_IRQ: + /* Should not get this here. Send a NACK and wait on DONE */ + vSMBusSendNACK( pxSMBusInstance ); + break; + + case E_TARGET_DONE_IRQ: + if( SMBUS_PROTOCOL_NONE == pxSMBusInstance->xProtocol ) + { + /* VMC_ERR( "ERROR: Protocol = SMBUS_PROTOCOL_NONE\n" ); */ + } + else + { + pxSMBusInstance->ulMessagesComplete[pxSMBusInstance->xProtocol]++; + } + + /* I2C Target has no protocol set so use ulI2CDevice */ + if( SMBUS_TRUE == pxSMBusInstance->ulI2CDevice ) + { + /* Report Data to Application */ + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucCommand, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usExpectedByteCount, __LINE__ ); + + if( SMBUS_FALSE == pxSMBusInstance->ucNackSent ) + { + vSMBusHandleActionAnnounceI2CResultToApplication( pxSMBusInstance, SMBUS_SUCCESS ); + } + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + } + else + { + if( ( SMBUS_PROTOCOL_BLOCK_WRITE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_SEND_BYTE == pxSMBusInstance->xProtocol ) ) + { + /* Report Data to Application */ + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucCommand, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usExpectedByteCount, __LINE__ ); + + if( SMBUS_FALSE == pxSMBusInstance->ucNackSent ) + { + vSMBusHandleActionWriteDataToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID ); + } + } + + if( SMBUS_PROTOCOL_HOST_NOTIFY == pxSMBusInstance->xProtocol ) + { + /* Report Data to Application */ + vSMBusHandleActionWriteDataToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID ); + } + + if( SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS == pxSMBusInstance->xProtocol ) + { + if( SMBUS_FALSE == pxSMBusInstance->ucNackSent ) + { + /* Change the address for the required slave + Determine which slave instance the UDID matched for */ + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucUDIDMatchedInstance, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucNewDeviceSlaveAddress, __LINE__ ); + + pMatched_Instance = &( pxTheProfile->xSMBusInstance[pxSMBusInstance->ucUDIDMatchedInstance] ); + + if( ( SMBUS_ARP_CAPABLE == pMatched_Instance->xARPCapability ) || + ( SMBUS_ARP_FIXED_AND_DISCOVERABLE == pMatched_Instance->xARPCapability ) ) + { + pMatched_Instance->ucARFlag = SMBUS_TRUE; + pMatched_Instance->ucAVFlag = SMBUS_TRUE; + } + + if( SMBUS_ARP_CAPABLE == pMatched_Instance->xARPCapability ) + { + pMatched_Instance->ucSMBusAddress = pxSMBusInstance->ucNewDeviceSlaveAddress; + + /* Disable the HW, Change the address and re-enable the HW */ + vSMBusHWWriteTgtControlEnable( pxTheProfile, pxSMBusInstance->ucUDIDMatchedInstance, 0 ); + vSMBusHWWriteTgtControlAddress( pxTheProfile, pxSMBusInstance->ucUDIDMatchedInstance, + pMatched_Instance->ucSMBusAddress ); + vSMBusHWWriteTgtControlEnable( pxTheProfile, pxSMBusInstance->ucUDIDMatchedInstance, 1 ); + + /* Report Data to Application */ + vSMBusHandleActionNotifyAddressChangeToApplication( pMatched_Instance, + pxTheProfile->ulTransactionID ); + } + } + } + + if( SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP == pxSMBusInstance->xProtocol ) + { + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + pMatched_Instance = &( pxTheProfile->xSMBusInstance[i] ); + if( SMBUS_TRUE == pMatched_Instance->ucInstanceInUse ) + { + if( ( SMBUS_ARP_CAPABLE == pMatched_Instance->xARPCapability ) || + ( SMBUS_ARP_FIXED_AND_DISCOVERABLE == pMatched_Instance->xARPCapability ) || + ( SMBUS_ARP_FIXED_NOT_DISCOVERABLE == pMatched_Instance->xARPCapability ) ) + { + /* If the ARP controller is on the same IP don't change it's settings */ + if( pxTheProfile->ucInstanceInPlay != i ) + { + vSMBusARPPrepareToARP( pMatched_Instance ); + } + } + } + } + } + + if( SMBUS_ARP_PROTOCOL_RESET_DEVICE == pxSMBusInstance->xProtocol ) + { + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, i, __LINE__ ); + pMatched_Instance = &( pxTheProfile->xSMBusInstance[i] ); + if( SMBUS_TRUE == pMatched_Instance->ucInstanceInUse ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pMatched_Instance->ucSMBusAddress, __LINE__ ); + if( ( SMBUS_ARP_CAPABLE == pMatched_Instance->xARPCapability ) || + ( SMBUS_ARP_FIXED_AND_DISCOVERABLE == pMatched_Instance->xARPCapability ) || + ( SMBUS_ARP_FIXED_NOT_DISCOVERABLE == pMatched_Instance->xARPCapability ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pMatched_Instance->ucSMBusAddress, __LINE__ ); + + /* If the ARP controller is on the same IP don't change it's settings */ + if( pxTheProfile->ucInstanceInPlay != i ) + { + vSMBusARPResetDevice( pMatched_Instance ); + } + } + } + } + } + + if( SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED == pxSMBusInstance->xProtocol ) + { + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + pMatched_Instance = &( pxTheProfile->xSMBusInstance[i] ); + if( pMatched_Instance->ucSMBusAddress == pxSMBusInstance->ucMatchedSMBusAddress ) + { + if( SMBUS_TRUE == pMatched_Instance->ucInstanceInUse ) + { + if( ( SMBUS_ARP_CAPABLE == pMatched_Instance->xARPCapability ) || + ( SMBUS_ARP_FIXED_AND_DISCOVERABLE == pMatched_Instance->xARPCapability ) || + ( SMBUS_ARP_FIXED_NOT_DISCOVERABLE == pMatched_Instance->xARPCapability ) ) + { + vSMBusARPResetDevice( pMatched_Instance ); + } + } + } + } + } + + if( ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_WRITE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_READ == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_RECEIVE_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_SEND_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_HOST_NOTIFY == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_NONE == pxSMBusInstance->xProtocol ) ) + { + if( SMBUS_FALSE == pxSMBusInstance->ucNackSent ) + { + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_SUCCESS ); + } + else + { + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + } + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + } + + if( ( SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_RESET_DEVICE == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED == pxSMBusInstance->xProtocol ) ) + { + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + } + } + break; + + /* Awaiting DONE but a DATA_IRQ arrives means a PEC has arrived */ + case E_TARGET_DATA_IRQ: + if( ( SMBUS_PROTOCOL_BLOCK_WRITE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_SEND_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_RESET_DEVICE == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED == pxSMBusInstance->xProtocol ) ) + { + /* Read as much data as is available */ + ucCurrentFill = ulSMBusHWReadTgtRxFifoStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ucCurrentFill; i++ ) + { + pxSMBusInstance->ucReceivedData[pxSMBusInstance->usReceiveIndex++] = + ulSMBusHWReadTgtRxFifoPayload( pxSMBusInstance->pxSMBusProfile ); + } + } + break; + + case E_CONTROLLER_DONE_IRQ: + if( SMBUS_PROTOCOL_BLOCK_READ == pxSMBusInstance->xProtocol ) + { + /* Report Data to Application */ + vSMBusHandleActionWriteDataToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID ); + } + + if( SMBUS_PROTOCOL_NONE == pxSMBusInstance->xProtocol ) + { + /* VMC_ERR( "ERROR: Protocol = SMBUS_PROTOCOL_NONE\n" ); */ + } + else + { + pxSMBusInstance->ulMessagesComplete[pxSMBusInstance->xProtocol]++; + } + + if( I2C_PROTOCOL_WRITE == pxSMBusInstance->xProtocol ) + { + vSMBusHandleActionAnnounceI2CResultToApplication( pxSMBusInstance, SMBUS_SUCCESS ); + } + else + { + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, + pxTheProfile->ulTransactionID, SMBUS_SUCCESS ); + } + + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief This function walks through each instance to determine if +* the UDID transmitted matches any one of the active SMBus instances +* +*****************************************************************************/ +static uint8_t ucCheckAtLeastOneMatchFound( SMBUS_PROFILE_TYPE* pxSMBusProfile, SMBUS_INSTANCE_TYPE* pxSMBusInstance ) +{ + uint8_t ucAtLeastOneMatchFound = SMBUS_FALSE; + int i = 0; + + if( ( NULL != pxSMBusProfile ) && + ( NULL != pxSMBusInstance ) ) + { + for( i = 0; i < SMBUS_NUMBER_OF_SMBUS_NON_ARP_INSTANCES; i++ ) + { + if( SMBUS_TRUE == pxSMBusProfile->xSMBusInstance[i].ucInstanceInUse ) + { + if( SMBUS_TRUE == pxSMBusProfile->ucUDIDMatch[i] ) + { + int Index = 15 - pxSMBusInstance->usReceiveIndex; + + if( pxSMBusProfile->xSMBusInstance[i].ucUDID[Index] + == pxSMBusInstance->ucReceivedData[pxSMBusInstance->usReceiveIndex] ) + { + ucAtLeastOneMatchFound = SMBUS_TRUE; + pxSMBusInstance->ucUDIDMatchedInstance = i; + } + else + { + pxSMBusProfile->ucUDIDMatch[i] = SMBUS_FALSE; + } + } + } + } + + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + ucAtLeastOneMatchFound, __LINE__ ); + } + return ( ucAtLeastOneMatchFound ); +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is AwaitingData +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateAwaitingData( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + uint8_t ucNoStatusCheck = SMBUS_TRUE; + uint8_t ucCurrentFill = 0; + int i = 0; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_DESC_FIFO_ALMOST_EMPTY_IRQ: + /* ACKs need to be done after the received byte is checked for SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS */ + if( SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS != pxSMBusInstance->xProtocol ) + { + if( pxSMBusInstance->ulI2CDevice ) + { + /* Read how much space is available in the descriptor FIFO and write that number of ACKs */ + ucCurrentFill = ulSMBusHWReadTgtDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ( SMBUS_FIFO_DEPTH - ucCurrentFill ); i++ ) + { + if( pxSMBusInstance->usDescriptorsSent < pxSMBusInstance->usReceiveIndex ) + { + ucNoStatusCheck = SMBUS_TRUE; + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, ucNoStatusCheck ) ) + { + break; + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + } + } + } + else + { + /* Read how much space is available in the descriptor FIFO and write that number of ACKs */ + ucCurrentFill = ulSMBusHWReadTgtDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ( SMBUS_FIFO_DEPTH - ucCurrentFill ); i++ ) + { + if( pxSMBusInstance->usDescriptorsSent < pxSMBusInstance->usExpectedByteCount ) + { + ucNoStatusCheck = SMBUS_TRUE; + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, ucNoStatusCheck ) ) + { + break; + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + } + } + } + } + break; + + case E_TARGET_READ_IRQ: + if( SMBUS_PROTOCOL_HOST_NOTIFY != pxSMBusInstance->xProtocol ) + { + if( SMBUS_TRUE == pxSMBusInstance->ulI2CDevice ) + { + if( SMBUS_FALSE == pxSMBusInstance->ucNackSent ) + { + if( 0 < pxSMBusInstance->usReceiveIndex ) + { + vSMBusHandleActionWriteI2CDataToApplication( pxSMBusInstance); + } + } + vSMBusHandleActionGetI2CDataFromApplication( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_READY_TO_SEND_BYTE ); + } + else + { + /* READ_IRQ may have been added to the queue along with DATA_IRQ */ + /* Ignore for now and add back onto the queue */ + vSMBusGenerateEvent_E_TARGET_READ_IRQ( pxSMBusInstance ); + } + } + else + { + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + } + break; + + case E_TARGET_DONE_IRQ: + if( SMBUS_TRUE == pxSMBusInstance->ulI2CDevice ) + { + /* Received a STOP */ + if( SMBUS_FALSE == pxSMBusInstance->ucNackSent ) + { + if( 0 < pxSMBusInstance->usReceiveIndex ) + { + vSMBusHandleActionWriteI2CDataToApplication( pxSMBusInstance); + } + } + /* Not ready to handle this add it back on the queue and handle it in SMBUS_STATE_AWAITING_DONE */ + vSMBusGenerateEvent_E_TARGET_DONE_IRQ( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + else + { + /* Shouldn't get here unless a block write size is incorrect */ + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + /* TODO: Need a new error defined since we are calling BusError with DONE_IRQ */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + } + break; + + case E_TARGET_DATA_IRQ: + if( SMBUS_TRUE == pxSMBusInstance->ulI2CDevice ) + { + /* Read as much data as is available */ + ucCurrentFill = ulSMBusHWReadTgtRxFifoStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ucCurrentFill; i++ ) + { + pxSMBusInstance->ucReceivedData[pxSMBusInstance->usReceiveIndex++] = + ulSMBusHWReadTgtRxFifoPayload( pxSMBusInstance->pxSMBusProfile ); + } + } + else + { + switch( pxSMBusInstance->xProtocol ) + { + case SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS: + { + ucCurrentFill = ulSMBusHWReadTgtRxFifoStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ucCurrentFill; i++ ) + { + pxSMBusInstance->ucReceivedData[pxSMBusInstance->usReceiveIndex] = + ulSMBusHWReadTgtRxFifoPayload( pxSMBusInstance->pxSMBusProfile ); + + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usReceiveIndex, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucReceivedData[pxSMBusInstance->usReceiveIndex], __LINE__ ); + if( SMBUS_UDID_LENGTH > pxSMBusInstance->usReceiveIndex ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucReceivedData[pxSMBusInstance->usReceiveIndex], __LINE__ ); + /* Check if this byte matches one of our instances */ + if( SMBUS_TRUE == ucCheckAtLeastOneMatchFound( pxSMBusInstance->pxSMBusProfile, pxSMBusInstance ) ) + { + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS == ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + pxSMBusInstance->usDescriptorsSent++; + } + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DATA ); + } + else + { + vSMBusSendNACK( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + pxSMBusInstance->usReceiveIndex++; + } + else if( SMBUS_UDID_LENGTH == pxSMBusInstance->usReceiveIndex ) + { + /* The UDID matched so assign new slave address to that */ + pxSMBusInstance->ucNewDeviceSlaveAddress = + ( pxSMBusInstance->ucReceivedData[pxSMBusInstance->usReceiveIndex] >> SMBUS_TGT_CONTROL_0_ADDRESS_FIELD_POSITION ); + + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucReceivedData[pxSMBusInstance->usReceiveIndex], __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucUDIDMatchedInstance, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucNewDeviceSlaveAddress, __LINE__ ); + + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS == ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + pxSMBusInstance->usDescriptorsSent++; + } + pxSMBusInstance->usReceiveIndex++; + } + else + { + /* PEC */ + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usReceiveIndex, __LINE__ ); + ucSMBusTargetWriteDescriptorPEC( pxSMBusInstance->pxSMBusProfile ); + pxSMBusInstance->ucPECSent = SMBUS_TRUE; + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } + } + break; + + case SMBUS_PROTOCOL_HOST_NOTIFY: + case SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL: + case SMBUS_PROTOCOL_PROCESS_CALL: + case SMBUS_PROTOCOL_BLOCK_WRITE: + case SMBUS_PROTOCOL_WRITE_64: + case SMBUS_PROTOCOL_WRITE_32: + case SMBUS_PROTOCOL_WRITE_WORD: + case SMBUS_PROTOCOL_WRITE_BYTE: + case SMBUS_PROTOCOL_SEND_BYTE: + /* Read as much data as is available */ + ucCurrentFill = ulSMBusHWReadTgtRxFifoStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ucCurrentFill; i++ ) + { + pxSMBusInstance->ucReceivedData[pxSMBusInstance->usReceiveIndex++] = + ulSMBusHWReadTgtRxFifoPayload( pxSMBusInstance->pxSMBusProfile ); + } + + /* Check if we need to change threshold level */ + if( pxSMBusInstance->usReceiveIndex < pxSMBusInstance->usExpectedByteCount ) + { + if( SMBUS_FIFO_FILL_TRIGGER > ( pxSMBusInstance->usExpectedByteCount - pxSMBusInstance->usReceiveIndex ) ) + { + pxSMBusInstance->ucExpectedByteCountPart = 1; + } + else + { + pxSMBusInstance->ucExpectedByteCountPart = SMBUS_FIFO_FILL_TRIGGER; + } + + /* Set up the threshold again */ + vSMBusHWWriteRxFifoFillThresholdFillThresh( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucExpectedByteCountPart ); + + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DATA ); + } + else /* We've got all the bytes */ + { + /* Set threshold back to 1 */ + vSMBusHWWriteRxFifoFillThresholdFillThresh( pxSMBusInstance->pxSMBusProfile, 1 ); + + if( ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_PROCESS_CALL == pxSMBusInstance->xProtocol ) ) + { + /* Write the received data */ + if( SMBUS_FALSE == pxSMBusInstance->ucNackSent ) + { + vSMBusHandleActionWriteDataToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID ); + } + vSMBusHandleActionGetDataFromApplication( pxSMBusInstance ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usSendDataSize, __LINE__ ); + + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_READ ); + } + else + { + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } + break; + + default: + break; + } + break; /* case E_TARGET_DATA_IRQ: */ + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is AwaitingBlockSize +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateAwaitingBlockSize( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_DESC_FIFO_ALMOST_EMPTY_IRQ: + break; + + case E_TARGET_DATA_IRQ: + if( ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_WRITE == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS == pxSMBusInstance->xProtocol ) ) + { + /* Get the block size and set Expected_Byte_Count */ + if( SMBUS_RX_FIFO_IS_EMPTY != ulSMBusHWReadTgtRxFifoStatusEmpty( pxSMBusInstance->pxSMBusProfile ) ) + { + pxSMBusInstance->usExpectedByteCount = + ulSMBusHWReadTgtRxFifoPayload( pxSMBusInstance->pxSMBusProfile ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usDescriptorsSent, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usExpectedByteCount, __LINE__ ); + + /* Now send ACK for the block size */ + if( SMBUS_HW_DESCRIPTOR_WRITE_SUCCESS != ucSMBusTargetWriteDescriptorACK( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_ERROR, + pxSMBusInstance->ucThisInstanceNumber, + SMBUS_LOG_EVENT_ERROR, 0, __LINE__ ); + } + } + else + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + 0, __LINE__ ); + break; + } + + pxSMBusInstance->usReceiveIndex = 0; + + /* Change threshold to match block size - or full fifo */ + pxSMBusInstance->ucExpectedByteCountPart = + ( pxSMBusInstance->usExpectedByteCount < SMBUS_FIFO_FILL_TRIGGER ? 1 : SMBUS_FIFO_FILL_TRIGGER ); + + vSMBusHWWriteRxFifoFillThresholdFillThresh( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucExpectedByteCountPart ); + + /* Check for block size of 0 */ + if( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) + { + if( 0 == pxSMBusInstance->usExpectedByteCount ) + { + /* Now get data to send back */ + vSMBusHandleActionGetDataFromApplication( pxSMBusInstance ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usSendDataSize, __LINE__ ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_READ ); + } + else + { + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DATA ); + } + } + else + { + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DATA ); + } + } + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerSendCommand +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerSendCommand( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_SEND_NEXT_BYTE: + if( ( SMBUS_PROTOCOL_BLOCK_READ == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED == pxSMBusInstance->xProtocol ) ) + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerWriteDescriptorByte( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucCommand, SMBUS_FALSE ) ) + { + /* If SMBus_Controller_Write_Descriptor_Byte( ) is true pop out and wait on descriptor fifo emptying */ + } + else + { + vSMBusHandleActionCreateEventSendNextByte( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_SEND_READ_START ); + } + } + + if( ( SMBUS_PROTOCOL_BLOCK_WRITE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_HOST_NOTIFY == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_RESET_DEVICE == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS == pxSMBusInstance->xProtocol ) ) + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerWriteDescriptorByte( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucCommand, SMBUS_FALSE ) ) + { + /* If SMBus_Controller_Write_Descriptor_Byte( ) is true pop out and wait on descriptor fifo emptying */ + } + else + { + vSMBusHandleActionCreateEventSendNextByte( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_WRITE_BYTE ); + } + } + + if( SMBUS_PROTOCOL_SEND_BYTE == pxSMBusInstance->xProtocol ) + { + vSMBusHandleActionCreateEventSendNextByte( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_WRITE_BYTE ); + } + break; + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerWriteByte +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerWriteByte( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + uint8_t ucNoStatusCheck = SMBUS_TRUE; + uint8_t ucCurrentFill = 0; + int i = 0; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_SEND_NEXT_BYTE: + case E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ: + if( ( SMBUS_PROTOCOL_BLOCK_WRITE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_WRITE_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_SEND_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_HOST_NOTIFY == pxSMBusInstance->xProtocol ) || + ( I2C_PROTOCOL_WRITE == pxSMBusInstance->xProtocol ) || + ( I2C_PROTOCOL_WRITE_READ == pxSMBusInstance->xProtocol ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usSendDataSize, __LINE__ ); + + if( 1 < pxSMBusInstance->usSendDataSize ) + { + /* Read how much room is in Descriptor FIFO */ + ucCurrentFill = ulSMBusHWReadCtrlDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ( SMBUS_FIFO_DEPTH - ucCurrentFill ); i++ ) + { + if( 1 < pxSMBusInstance->usSendDataSize ) + { + ucNoStatusCheck = SMBUS_TRUE; + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->usSendIndex, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucSendData[pxSMBusInstance->usSendIndex], __LINE__ ); + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerWriteDescriptorByte( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSendData[pxSMBusInstance->usSendIndex], ucNoStatusCheck ) ) + { + break; + } + else + { + pxSMBusInstance->usSendIndex++; + pxSMBusInstance->usSendDataSize--; + } + } + } + + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + } + else + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usSendDataSize, __LINE__ ); + if( ( SMBUS_PROTOCOL_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( I2C_PROTOCOL_WRITE_READ == pxSMBusInstance->xProtocol )) + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerWriteDescriptorByte( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSendData[pxSMBusInstance->usSendIndex], SMBUS_FALSE ) ) + { + /* If SMBus_Controller_Write_Descriptor_Byte( ) is true + pop out and wait on descriptor fifo emptying */ + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_WRITE_BYTE ); + } + else + { + vSMBusHandleActionCreateEventSendNextByte( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_SEND_READ_START ); + } + } + else + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usSendDataSize, __LINE__ ); + if( SMBUS_PROTOCOL_HOST_NOTIFY == pxSMBusInstance->xProtocol ) /* No PEC with Host Notify */ + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerWriteDescriptorStopWrite( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSendData[pxSMBusInstance->usSendIndex] ) ) + { + /* If SMBus_Controller_Write_Descriptor_Byte( ) is true + pop out and wait on descriptor fifo emptying */ + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_WRITE_BYTE ); + } + else + { + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } + else + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->ucPecRequiredForTransaction, __LINE__ ); + if( SMBUS_TRUE == pxSMBusInstance->ucPecRequiredForTransaction ) + { + /* Need space for 2 bytes in decscriptor fifo here */ + if( SMBUS_FIFO_SPACE_FOR_TWO_BYTES >= ulSMBusHWReadCtrlDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ) ) + { + + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerWriteDescriptorByte( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSendData[pxSMBusInstance->usSendIndex], SMBUS_FALSE ) ) + { + /* Should never get here but if so just stay in this state */ + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_WRITE_BYTE ); + } + else + { + ucSMBusControllerWriteDescriptorPECWrite( pxSMBusInstance->pxSMBusProfile ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } + else + { + /* If SMBus_Controller_Write_Descriptor_Byte( ) is true + pop out and wait on descriptor fifo emptying */ + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_WRITE_BYTE ); + } + } + else + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerWriteDescriptorStopWrite( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSendData[pxSMBusInstance->usSendIndex] ) ) + { + /* If SMBus_Controller_Write_Descriptor_Byte( ) is true + pop out and wait on descriptor fifo emptying */ + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_WRITE_BYTE ); + } + else + { + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + } + } + } + } + } + + if( SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS == pxSMBusInstance->xProtocol ) + { + /* Read how much room is in Descriptor FIFO */ + ucCurrentFill = ulSMBusHWReadCtrlDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ( SMBUS_FIFO_DEPTH - ucCurrentFill ); i++ ) + { + if( 0 < pxSMBusInstance->usSendDataSize ) + { + ucNoStatusCheck = SMBUS_TRUE; + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerWriteDescriptorByte( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSendData[pxSMBusInstance->usSendIndex], ucNoStatusCheck ) ) + { + break; + } + else + { + pxSMBusInstance->usSendIndex++; + pxSMBusInstance->usSendDataSize--; + } + } + else + { + break; + } + } + + /* Now send the PEC */ + ucSMBusControllerWriteDescriptorPECWrite( pxSMBusInstance->pxSMBusProfile ); + + /* And enable the controller to send descriptors */ + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + + if( ( SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_RESET_DEVICE == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED == pxSMBusInstance->xProtocol ) ) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->xProtocol, __LINE__ ); + ucSMBusControllerWriteDescriptorPECWrite( pxSMBusInstance->pxSMBusProfile ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_AWAITING_DONE ); + } + + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerSendReadStart +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerSendReadStart( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + int i = 0; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch ( ucAnyEvent ) + { + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_SEND_NEXT_BYTE: + if( I2C_PROTOCOL_WRITE_READ == pxSMBusInstance->xProtocol ) + { + pxSMBusInstance->usDescriptorsSent = 0; + ucSMBusControllerReadDescriptorStart( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSMBusDestinationAddress ); + pxSMBusInstance->ucExpectedByteCountPart = + ( pxSMBusInstance->usExpectedByteCount < SMBUS_HALF_FIFO_DEPTH ? pxSMBusInstance->usExpectedByteCount : SMBUS_HALF_FIFO_DEPTH ); + + /* Set to no more than 32 */ + if( 0 < pxSMBusInstance->ucExpectedByteCountPart ) /* If its zero leave threshold at 1 */ + { + vSMBusHWWriteCtrlRxFifoFillThreshold( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucExpectedByteCountPart ); + } + + if( 0 == pxSMBusInstance->usExpectedByteCount ) + { + ucSMBusControllerReadDescriptorStop( pxSMBusInstance->pxSMBusProfile ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_READ_DONE ); + } + else + { + //ucSMBusControllerReadDescriptorByte( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_READ_BYTE ); + } + } + + + + if( ( SMBUS_PROTOCOL_BLOCK_READ == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED == pxSMBusInstance->xProtocol ) ) + { + pxSMBusInstance->usDescriptorsSent = 0; + ucSMBusControllerReadDescriptorStart( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSMBusDestinationAddress ); + ulSMBusHWReadCtrlDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); /* Send all descriptors */ + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->xProtocol, __LINE__ ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_READ_BLOCK_SIZE ); + } + + if( ( SMBUS_PROTOCOL_READ_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_RECEIVE_BYTE == pxSMBusInstance->xProtocol ) ) + { + switch ( pxSMBusInstance->xProtocol ) + { + case SMBUS_PROTOCOL_READ_64: + pxSMBusInstance->usExpectedByteCount = 8; + pxSMBusInstance->ucExpectedByteCountPart = 8; + pxSMBusInstance->usDescriptorsSent = 0; + break; + + case SMBUS_PROTOCOL_READ_32: + pxSMBusInstance->usExpectedByteCount = 4; + pxSMBusInstance->ucExpectedByteCountPart = 4; + pxSMBusInstance->usDescriptorsSent = 0; + break; + + case SMBUS_PROTOCOL_READ_WORD: + pxSMBusInstance->usExpectedByteCount = 2; + pxSMBusInstance->ucExpectedByteCountPart = 2; + pxSMBusInstance->usDescriptorsSent = 0; + break; + + case SMBUS_PROTOCOL_READ_BYTE: + pxSMBusInstance->usExpectedByteCount = 1; + pxSMBusInstance->ucExpectedByteCountPart = 1; + pxSMBusInstance->usDescriptorsSent = 0; + break; + + case SMBUS_PROTOCOL_PROCESS_CALL: + pxSMBusInstance->usExpectedByteCount = 2; + pxSMBusInstance->ucExpectedByteCountPart = 2; + pxSMBusInstance->usDescriptorsSent = 0; + break; + + case SMBUS_PROTOCOL_RECEIVE_BYTE: + pxSMBusInstance->usExpectedByteCount = 1; + pxSMBusInstance->ucExpectedByteCountPart = 1; + pxSMBusInstance->usDescriptorsSent = 0; + break; + + default: + break; + } + vSMBusHWWriteCtrlRxFifoFillThreshold( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucExpectedByteCountPart ); + + /* WRITE_START, WRITE_BYTE, READ_START, */ + ucSMBusControllerReadDescriptorStart( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucSMBusDestinationAddress ); + + /* If PEC + READ_BYTE * ( BYTE_COUNT ), READ_PEC */ + + /* else + READ_BYTE * ( BYTE_COUNT-1 ), READ_STOP */ + + if( SMBUS_TRUE == pxSMBusInstance->ucPecRequiredForTransaction ) + { + for( i = 0; i < pxSMBusInstance->ucExpectedByteCountPart; i++ ) + { + ucSMBusControllerReadDescriptorByte( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ); + pxSMBusInstance->usDescriptorsSent++; + } + + ucSMBusControllerReadDescriptorPEC( pxSMBusInstance->pxSMBusProfile ); + } + else + { + for( i = 0; i < pxSMBusInstance->ucExpectedByteCountPart - 1; i++ ) + { + ucSMBusControllerReadDescriptorByte( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ); + pxSMBusInstance->usDescriptorsSent++; + } + ucSMBusControllerReadDescriptorStop( pxSMBusInstance->pxSMBusProfile ); + pxSMBusInstance->usDescriptorsSent++; + } + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); /* Send all descriptors */ + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_READ_BYTE ); + } + + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerReadBlockSize +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerReadBlockSize( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ: + /* Need block size before we can proceed */ + break; + + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + ulSMBusHWReadPHYCtrlDbgState( pxTheProfile ), __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + ulSMBusHWReadCtrlDbgState( pxTheProfile ), __LINE__ ); + + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + ulSMBusHWReadPHYCtrlDbgState( pxTheProfile ), __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + ulSMBusHWReadCtrlDbgState( pxTheProfile ), __LINE__ ); + break; + + case E_CONTROLLER_DATA_IRQ: + if( ( SMBUS_PROTOCOL_BLOCK_READ == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED == pxSMBusInstance->xProtocol ) ) + { + pxSMBusInstance->usExpectedByteCount = ulSMBusHWReadCtrlRxFifoPayload( pxSMBusInstance->pxSMBusProfile ); + + pxSMBusInstance->usDescriptorsSent = 0; + pxSMBusInstance->ucExpectedByteCountPart = + ( pxSMBusInstance->usExpectedByteCount < SMBUS_HALF_FIFO_DEPTH ? pxSMBusInstance->usExpectedByteCount : SMBUS_HALF_FIFO_DEPTH ); + + /* Set to no more than 32 */ + if( 0 < pxSMBusInstance->ucExpectedByteCountPart ) /* If its zero leave threshold at 1 */ + { + vSMBusHWWriteCtrlRxFifoFillThreshold( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucExpectedByteCountPart ); + } + + /* ACK the block read */ + if( ( SMBUS_TRUE == pxSMBusInstance->ucPecRequiredForTransaction ) || + ( SMBUS_DEVICE_DEFAULT_ARP_ADDRESS == pxSMBusInstance->ucSMBusDestinationAddress ) ) /* PEC required for all ARP protocols */ + { + ucSMBusControllerReadDescriptorByte( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_READ_BYTE ); + + if( 0 == pxSMBusInstance->usExpectedByteCount ) + { + /* For the special case of 0 size block with a PEC */ + ucSMBusControllerReadDescriptorPEC( pxSMBusInstance->pxSMBusProfile ); + } + } + else + { + if( 0 == pxSMBusInstance->usExpectedByteCount ) + { + ucSMBusControllerReadDescriptorStop( pxSMBusInstance->pxSMBusProfile ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_READ_DONE ); + } + else + { + ucSMBusControllerReadDescriptorByte( pxSMBusInstance->pxSMBusProfile, SMBUS_FALSE ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_READ_BYTE ); + } + } + } + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerReadByte +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerReadByte( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + int i = 0; + uint8_t ucCurrentFill = 0; + uint8_t ucNoStatusCheck = SMBUS_TRUE; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch ( ucAnyEvent ) + { + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ: + if( ( SMBUS_PROTOCOL_BLOCK_READ == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED == pxSMBusInstance->xProtocol ) || + ( I2C_PROTOCOL_READ == pxSMBusInstance->xProtocol ) || + ( I2C_PROTOCOL_WRITE_READ == pxSMBusInstance->xProtocol )) + { + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usDescriptorsSent, __LINE__ ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usExpectedByteCount, __LINE__ ); + + if( pxSMBusInstance->usDescriptorsSent < pxSMBusInstance->usExpectedByteCount ) + { + if( SMBUS_TRUE == pxSMBusInstance->ucPecRequiredForTransaction ) + { + ucCurrentFill = ulSMBusHWReadCtrlDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ( SMBUS_FIFO_DEPTH - ucCurrentFill ); i++ ) + { + if( pxSMBusInstance->usDescriptorsSent < pxSMBusInstance->usExpectedByteCount ) + { + ucNoStatusCheck = SMBUS_TRUE; + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerReadDescriptorByte( pxSMBusInstance->pxSMBusProfile, ucNoStatusCheck ) ) + { + break; + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + } + else + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerReadDescriptorPEC( pxSMBusInstance->pxSMBusProfile ) ) + { + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + break; + } + } + } + else + { + ucCurrentFill = ulSMBusHWReadCtrlDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ( SMBUS_FIFO_DEPTH - ucCurrentFill ); i++ ) + { + if( pxSMBusInstance->usDescriptorsSent < ( pxSMBusInstance->usExpectedByteCount - 1 ) ) + { + ucNoStatusCheck = SMBUS_TRUE; + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerReadDescriptorByte( pxSMBusInstance->pxSMBusProfile, ucNoStatusCheck ) ) + { + break; + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + } + else if( pxSMBusInstance->usDescriptorsSent == ( pxSMBusInstance->usExpectedByteCount - 1 ) ) + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerReadDescriptorStop( pxSMBusInstance->pxSMBusProfile ) ) + { + break; + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + } + } + } + ulSMBusHWReadCtrlDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + } + } + break; + + case E_CONTROLLER_DONE_IRQ: + /* Got this early just put the event back on the queue until we have read any received data + SMBus_GenerateEvent_E_CONTROLLER_DONE_IRQ( pxSMBusInstance ); */ + break; + + case E_CONTROLLER_DATA_IRQ: + if( ( SMBUS_PROTOCOL_READ_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_RECEIVE_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_READ == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID == pxSMBusInstance->xProtocol ) || + ( SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED == pxSMBusInstance->xProtocol ) || + ( I2C_PROTOCOL_READ == pxSMBusInstance->xProtocol ) || + ( I2C_PROTOCOL_WRITE_READ == pxSMBusInstance->xProtocol ) ) + { + /* Read until FIFO is empty. If true RX FIFO is empty */ + while( !ulSMBusHWReadCtrlRxFifoStatusEmpty( pxSMBusInstance->pxSMBusProfile ) ) + { + pxSMBusInstance->ucReceivedData[pxSMBusInstance->usReceiveIndex++] = + ulSMBusHWReadCtrlRxFifoPayload( pxSMBusInstance->pxSMBusProfile ); + } + + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usReceiveIndex, __LINE__ ); + + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usExpectedByteCount, __LINE__ ); + + if( pxSMBusInstance->usReceiveIndex >= pxSMBusInstance->usExpectedByteCount ) + { + /* We've got all the expected data but we might still be expecting a PEC */ + + vSMBusHWWriteCtrlRxFifoFillThreshold( pxSMBusInstance->pxSMBusProfile, 1 ); + + if( SMBUS_TRUE == pxSMBusInstance->ucPecRequiredForTransaction ) + { + if( pxSMBusInstance->usReceiveIndex > pxSMBusInstance->usExpectedByteCount ) + { + /* We've already got the PEC */ + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_READ_DONE ); + } + } + else + { + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_READ_DONE ); + } + } + else + { + /* We are expecting more data - stay in this state and wait on another data IRQ + Set threshold to data we are still expecting */ + if( SMBUS_HALF_FIFO_DEPTH > ( pxSMBusInstance->usExpectedByteCount - pxSMBusInstance->usReceiveIndex ) ) + { + pxSMBusInstance->ucExpectedByteCountPart = + ( pxSMBusInstance->usExpectedByteCount - pxSMBusInstance->usReceiveIndex ); + } + else + { + pxSMBusInstance->ucExpectedByteCountPart = SMBUS_HALF_FIFO_DEPTH; + } + + vSMBusHWWriteCtrlRxFifoFillThreshold( pxSMBusInstance->pxSMBusProfile, + pxSMBusInstance->ucExpectedByteCountPart ); + } + } + + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerReadPEC +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerReadPEC( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_DATA_IRQ: + if( ( SMBUS_PROTOCOL_BLOCK_READ == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_64 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_32 == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_WORD == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_READ_BYTE == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL == pxSMBusInstance->xProtocol ) || + ( SMBUS_PROTOCOL_RECEIVE_BYTE == pxSMBusInstance->xProtocol ) ) + { + if( SMBUS_TRUE == pxSMBusInstance->ucPecRequiredForTransaction ) + { + ucSMBusControllerReadDescriptorPEC( pxSMBusInstance->pxSMBusProfile ); + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_CONTROLLER_READ_DONE ); + } + } + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief Handle any event to the State Machine +* when the current state is ControllerReadDone +* +*****************************************************************************/ +static void vDefaultSMBusFSMSMBusStateControllerReadDone( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + SMBUS_PROFILE_TYPE* pxTheProfile = NULL; + uint8_t ucNoStatusCheck = SMBUS_TRUE; + uint8_t ucCurrentFill = 0; + int i = 0; + + if( NULL != pxSMBusInstance ) + { + pxTheProfile = pxSMBusInstance->pxSMBusProfile; + + switch( ucAnyEvent ) + { + case E_CONTROLLER_DATA_IRQ: + if( I2C_PROTOCOL_READ == pxSMBusInstance->xProtocol ) + { + /* Read until FIFO is empty. If true RX FIFO is empty */ + while( !ulSMBusHWReadCtrlRxFifoStatusEmpty( pxSMBusInstance->pxSMBusProfile ) ) + { + pxSMBusInstance->ucReceivedData[pxSMBusInstance->usReceiveIndex++] = + ulSMBusHWReadCtrlRxFifoPayload( pxSMBusInstance->pxSMBusProfile ); + } + + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usReceiveIndex, __LINE__ ); + + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->usExpectedByteCount, __LINE__ ); + + } + break; + + case E_CONTROLLER_DESC_FIFO_ALMOST_EMPTY_IRQ: + /* Check if we need to send any more ACKs */ + if( I2C_PROTOCOL_READ == pxSMBusInstance->xProtocol ) + { + if( pxSMBusInstance->usDescriptorsSent < pxSMBusInstance->usReceiveIndex ) + { + if( pxSMBusInstance->usDescriptorsSent == ( pxSMBusInstance->usReceiveIndex-1 ) ) + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerReadDescriptorStop( pxSMBusInstance->pxSMBusProfile ) ) + { + break; + } + else + { + pxSMBusInstance->usDescriptorsSent++; + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + } + } + else + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerReadDescriptorByte( pxSMBusInstance->pxSMBusProfile, ucNoStatusCheck ) ) + { + break; + } + else + { + pxSMBusInstance->usDescriptorsSent++; + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + } + } + + } + } + else if( pxSMBusInstance->usDescriptorsSent < pxSMBusInstance->usExpectedByteCount ) + { + if( SMBUS_TRUE == pxSMBusInstance->ucPecRequiredForTransaction ) + { + ucCurrentFill = ulSMBusHWReadCtrlDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ( SMBUS_FIFO_DEPTH - ucCurrentFill ); i++ ) + { + if( pxSMBusInstance->usDescriptorsSent < pxSMBusInstance->usExpectedByteCount ) + { + ucNoStatusCheck = SMBUS_TRUE; + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerReadDescriptorByte( pxSMBusInstance->pxSMBusProfile, ucNoStatusCheck ) ) + { + break; + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + } + else + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerReadDescriptorPEC( pxSMBusInstance->pxSMBusProfile ) ) + { + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + break; + } + } + } + else + { + ucCurrentFill = ulSMBusHWReadCtrlDescStatusFillLevel( pxSMBusInstance->pxSMBusProfile ); + for( i = 0; i < ( SMBUS_FIFO_DEPTH - ucCurrentFill ); i++ ) + { + if( pxSMBusInstance->usDescriptorsSent < ( pxSMBusInstance->usExpectedByteCount - 1 ) ) + { + ucNoStatusCheck = SMBUS_TRUE; + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerReadDescriptorByte( pxSMBusInstance->pxSMBusProfile, ucNoStatusCheck ) ) + { + break; + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + } + else if( pxSMBusInstance->usDescriptorsSent == ( pxSMBusInstance->usExpectedByteCount - 1 ) ) + { + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerReadDescriptorStop( pxSMBusInstance->pxSMBusProfile ) ) + { + break; + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + } + } + vSMBusHWWriteCtrlControlEnable( pxSMBusInstance->pxSMBusProfile, SMBUS_CONTROL_ENABLE ); + } + } + else if( SMBUS_TRUE == pxSMBusInstance->ucPecRequiredForTransaction ) + { + if( pxSMBusInstance->usDescriptorsSent == pxSMBusInstance->usExpectedByteCount ) + { + /* Descriptor for PEC still required */ + if( SMBUS_HW_DESCRIPTOR_WRITE_FAIL == ucSMBusControllerReadDescriptorPEC( pxSMBusInstance->pxSMBusProfile ) ) + { + } + else + { + pxSMBusInstance->usDescriptorsSent++; + } + } + } + break; + + case E_TARGET_PHY_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_TEXT_TIMEOUT_ERROR_IRQ: + case E_CONTROLLER_PHY_CTLR_CEXT_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusWarning( pxSMBusInstance, ucAnyEvent ); + break; + + case E_CONTROLLER_LOA_ERROR_IRQ: + case E_CONTROLLER_NACK_ERROR_IRQ: + case E_CONTROLLER_PEC_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_CONTROLLER_DESC_ERROR_IRQ: + /* Report Result to Application */ + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID, SMBUS_ERROR ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_TARGET_LOA_ERROR_IRQ: + case E_TARGET_PEC_ERROR_IRQ: + case E_TARGET_RX_FIFO_ERROR_ERROR_IRQ: + case E_TARGET_RX_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_RX_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_ERROR_IRQ: + case E_TARGET_DESC_FIFO_OVERFLOW_ERROR_IRQ: + case E_TARGET_DESC_FIFO_UNDERFLOW_ERROR_IRQ: + case E_TARGET_DESC_ERROR_IRQ: + case E_TARGET_PHY_UNEXPTD_BUS_IDLE_ERROR_IRQ: + case E_TARGET_PHY_SMBDAT_LOW_TIMEOUT_DESC_ERROR_IRQ: + case E_TARGET_PHY_SMBCLK_LOW_TIMEOUT_ERROR_IRQ: + vSMBusHandleActionBusError( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + + case E_CONTROLLER_DONE_IRQ: + switch( pxSMBusInstance->xProtocol ) + { + case SMBUS_PROTOCOL_BLOCK_READ: + case SMBUS_PROTOCOL_READ_64: + case SMBUS_PROTOCOL_READ_32: + case SMBUS_PROTOCOL_READ_WORD: + case SMBUS_PROTOCOL_READ_BYTE: + case SMBUS_PROTOCOL_PROCESS_CALL: + case SMBUS_PROTOCOL_BLOCK_WRITE_BLOCK_READ_PROCESS_CALL: + case SMBUS_PROTOCOL_RECEIVE_BYTE: + case SMBUS_ARP_PROTOCOL_GET_UDID_DIRECTED: + case SMBUS_ARP_PROTOCOL_GET_UDID: + { + /* Report Data to Application */ + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->xProtocol, __LINE__ ); + vSMBusHandleActionWriteDataToApplication( pxSMBusInstance, pxTheProfile->ulTransactionID ); + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, + pxTheProfile->ulTransactionID, SMBUS_SUCCESS ); + + /* Log completed message */ + pxSMBusInstance->ulMessagesComplete[pxSMBusInstance->xProtocol]++; + + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + } + break; + + case I2C_PROTOCOL_READ: + case I2C_PROTOCOL_WRITE_READ: + { + /* Report Data to Application */ + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + pxSMBusInstance->xProtocol, __LINE__ ); + vSMBusHandleActionWriteI2CDataToApplication( pxSMBusInstance ); + vSMBusHandleActionAnnounceI2CResultToApplication( pxSMBusInstance, SMBUS_SUCCESS ); + + /* Log completed message */ + pxSMBusInstance->ulMessagesComplete[pxSMBusInstance->xProtocol]++; + + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + } + break; + + case SMBUS_PROTOCOL_SEND_BYTE: + case SMBUS_PROTOCOL_WRITE_BYTE: + case SMBUS_PROTOCOL_WRITE_WORD: + case SMBUS_PROTOCOL_BLOCK_WRITE: + case SMBUS_PROTOCOL_HOST_NOTIFY: + case SMBUS_PROTOCOL_WRITE_32: + case SMBUS_PROTOCOL_WRITE_64: + case SMBUS_ARP_PROTOCOL_PREPARE_TO_ARP: + case SMBUS_ARP_PROTOCOL_RESET_DEVICE: + case SMBUS_ARP_PROTOCOL_ASSIGN_ADDRESS: + case SMBUS_ARP_PROTOCOL_RESET_DEVICE_DIRECTED: + { + /* Report Result to Application */ + vSMBusHandleActionAnnounceResultToApplication( pxSMBusInstance, + pxTheProfile->ulTransactionID, SMBUS_SUCCESS ); + + /* Log completed message */ + pxSMBusInstance->ulMessagesComplete[pxSMBusInstance->xProtocol]++; + + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + } + break; + + case I2C_PROTOCOL_WRITE: + { + /* Report Result to Application */ + vSMBusHandleActionAnnounceI2CResultToApplication( pxSMBusInstance, SMBUS_SUCCESS ); + + /* Log completed message */ + pxSMBusInstance->ulMessagesComplete[pxSMBusInstance->xProtocol]++; + + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + } + break; + + default: + break; + } + + break; + + default: + vSMBusLogUnexpected( pxSMBusInstance, ucAnyEvent ); + vSMBusHandleActionResetAllData( pxSMBusInstance ); + vSMBusNextStateDecoder( pxSMBusInstance, SMBUS_STATE_INITIAL ); + break; + } + } +} + +/****************************************************************************** +* +* @brief Is the finite state machine for the specified SMBus instance +* The function will look up the current state, bytes sent, bytes received etc +* and given the event passed in it will transition to a new state +* +*****************************************************************************/ +void vSMBusFSM( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ) +{ + if( NULL != pxSMBusInstance ) + { + vSMBusClearAction( pxSMBusInstance ); + + SMBus_State_Type xState = pxSMBusInstance->xState; + pxSMBusInstance->ucEvent = ucAnyEvent; + + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_INFO, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_FSM_EVENT, + ( uint32_t )xState, ( uint32_t )ucAnyEvent ); + vLogAddEntry( pxSMBusInstance->pxSMBusProfile, SMBUS_LOG_LEVEL_DEBUG, + pxSMBusInstance->ucThisInstanceNumber, SMBUS_LOG_EVENT_DEBUG, + ( uint32_t )ucAnyEvent, __LINE__ ); + + switch ( pxSMBusInstance->xState ) + { + case SMBUS_STATE_INITIAL: + vDefaultSMBusFSMSMBusStateInitial( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_AWAITING_COMMAND_BYTE: + vDefaultSMBusFSMSMBusStateAwaitingCommandByte( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_AWAITING_BLOCK_SIZE: + vDefaultSMBusFSMSMBusStateAwaitingBlockSize( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_AWAITING_DATA: + vDefaultSMBusFSMSMBusStateAwaitingData( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_AWAITING_READ: + vDefaultSMBusFSMSMBusStateAwaitingRead( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_READY_TO_SEND_BYTE: + vDefaultSMBusFSMSMBusStateReadyToSendByte( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_CHECK_IF_PEC_REQUIRED: + vDefaultSMBusFSMSMBusStateCheckIfPECRequired( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_AWAITING_DONE: + vDefaultSMBusFSMSMBusStateAwaitingDone( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_CONTROLLER_SEND_COMMAND: + vDefaultSMBusFSMSMBusStateControllerSendCommand( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_CONTROLLER_SEND_READ_START: + vDefaultSMBusFSMSMBusStateControllerSendReadStart( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_CONTROLLER_READ_BLOCK_SIZE: + vDefaultSMBusFSMSMBusStateControllerReadBlockSize( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_CONTROLLER_READ_BYTE: + vDefaultSMBusFSMSMBusStateControllerReadByte( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_CONTROLLER_READ_PEC: + vDefaultSMBusFSMSMBusStateControllerReadPEC( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_CONTROLLER_READ_DONE: + vDefaultSMBusFSMSMBusStateControllerReadDone( pxSMBusInstance, ucAnyEvent ); + break; + + case SMBUS_STATE_CONTROLLER_WRITE_BYTE: + vDefaultSMBusFSMSMBusStateControllerWriteByte( pxSMBusInstance, ucAnyEvent ); + break; + + default: + break; + } + } +} diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_state.h b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_state.h new file mode 100755 index 00000000..dd4621a5 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_state.h @@ -0,0 +1,55 @@ +/** + * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the defintion of the SMBus FInite State Machine + * + * @file smbus_state.h + * + */ + +#ifndef _SMBUS_STATE_H_ +#define _SMBUS_STATE_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "smbus.h" + +/****************************************************************************** +* +* @brief Is the finite state machine for the specified SMBus instance +* The function will look up the current state, bytes sent, bytes received etc +* and given the event passed in it will transition to a new state +* +* @param pxSMBusInstance is a pointer to the SMBus instance structure. +* @param ucAnyEvent is an event triggered by the driver or by an interrupt +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void vSMBusFSM( SMBUS_INSTANCE_TYPE* pxSMBusInstance, uint8_t ucAnyEvent ); + +/****************************************************************************** +* +* @brief Is a conversion function from the state enum to character string +* to be used by logging functions +* +* @param xState is any of the state machine state values +* +* @return A character string +* +* @note None. +* +*****************************************************************************/ +char* pcStateToString( uint8_t xState ); + +#ifdef __cplusplus +} +#endif + +#endif /* _SMBUS_STATE_H_ */ diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_version.h b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_version.h new file mode 100755 index 00000000..bc2a175c --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/fw/smbus_version.h @@ -0,0 +1,15 @@ + +#ifndef _smbus_VERSION_H_ +#define _smbus_VERSION_H_ + +#define GIT_TAG "1.2.0_Release" +#define GIT_TAG_VER_MAJOR (1) +#define GIT_TAG_VER_MINOR (2) +#define GIT_TAG_VER_PATCH (0) +#define GIT_TAG_VER_DEV_COMMITS (0) + +#define GIT_HASH "3efeff2946cc63d1264e054c00863049ed8d4430" +#define GIT_STATUS (0) + +#endif // _smbus_VERSION_H_ + diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/bd/bd.tcl b/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/bd/bd.tcl new file mode 100755 index 00000000..1dc2d95d --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/bd/bd.tcl @@ -0,0 +1,78 @@ +# (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of AMD and is protected under U.S. and international copyright +# and other intellectual property laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# AMD, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) AMD shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or AMD had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# AMD products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of AMD products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +############################################################ + +#==============================================================================# +# Initialization Procedure +#==============================================================================# + +proc init { cellPath otherInfo } { + bd::mark_propagate_overrideable [get_bd_cells $cellPath] [list FREQ_HZ_AXI_ACLK] +} + +#==============================================================================# +# Post IP Configuration Procedure +#==============================================================================# + +proc post_config_ip { cellPath otherInfo } { +} + +#==============================================================================# +# Post Propagate Procedure +#==============================================================================# + +proc post_propagate { cellPath otherInfo } { + set cell [get_bd_cells $cellPath] + set clk [get_bd_pins $cellPath/s_axi_aclk] + set freq_hz [get_property CONFIG.FREQ_HZ $clk] + set val_src [string toupper [get_property CONFIG.FREQ_HZ_AXI_ACLK.VALUE_SRC $cell]] + if {$val_src ne "USER"} { + if {$freq_hz == ""} { + ::bd::send_msg -of $cellPath -type error -msg_id 1 -text "AXI Clock Frequency has not propagated" + } else { + set_property CONFIG.FREQ_HZ_AXI_ACLK $freq_hz $cell + } + } +} diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/component.xml b/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/component.xml new file mode 100755 index 00000000..9a5154e9 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/component.xml @@ -0,0 +1,4598 @@ + + + xilinx.com + ip + smbus + 1.1 + + + S_AXI + + + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + RESET + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + CLOCK + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + S_AXI + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + 100000000 + + + + + INTERRUPT + + + + + + + INTERRUPT + + + ip2intc_irpt + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + SMBUS + + + + + + + SCL_I + + + smbclk_i + + + + + SCL_O + + + smbclk_o + + + + + SCL_T + + + smbclk_t + + + + + SDA_I + + + smbdat_i + + + + + SDA_O + + + smbdat_o + + + + + SDA_T + + + smbdat_t + + + + + + + + S_AXI + + Reg + 0 + 4096 + 32 + register + read-write + + IP_VERSION + IP_VERSION + IP Major/Minor Version Information Register + 0x000 + 32 + read-only + + 65536 + + + MAJOR_VERSION + MAJOR_VERSION + IP Major Version +Returns the IP Major Version + + 16 + 16 + read-only + + 0 + 0 + + false + + + MINOR_VERSION + MINOR_VERSION + IP Minor Version +Returns the IP Minor Version + + 0 + 16 + read-only + + 0 + 0 + + false + + + + IP_REVISION + IP_REVISION + IP Revision Information Register + 0x004 + 32 + read-only + + 0 + + + CORE_REVISION + CORE_REVISION + IP Core Revision +Returns the IP Core Revision + + 0 + 16 + read-only + + 0 + 0 + + false + + + + IP_MAGIC_NUM + IP_MAGIC_NUM + IP Magic Number Register + 0x008 + 32 + read-only + + 0x534D4273 + + + MAGIC_NUMBER + MAGIC_NUMBER + IP Magic Number +Returns a read-only identifier to assist with debug/bring-up. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + IP_BUILD_CONFIG_0 + IP_BUILD_CONFIG_0 + IP Build Configuration 0 Register + 0x00C + 32 + read-only + + 100000000 + + + FREQ_HZ_AXI_ACLK + FREQ_HZ_AXI_ACLK + Input AXI ACLK Frequency +Returns the value of the FREQ_HZ_AXI_ACLK parameter as configured at build time. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + IP_BUILD_CONFIG_1 + IP_BUILD_CONFIG_1 + IP Build Configuration 1 Register + 0x010 + 32 + read-only + + 128 + + + NUM_TARGET_DEVICES + NUM_TARGET_DEVICES + Number of Target Devices supported +Returns the value of the NUM_TARGET_DEVICES parameter as configured at build time. + + 4 + 4 + read-only + + 0 + 0 + + false + + + SMBUS_DEV_CLASS + SMBUS_DEV_CLASS + Default SMBus Device Class +Returns the value of the SMBUS_DEV_CLASS parameter as configured at build time. + + 0 + 2 + read-only + + 0 + 0 + + false + + + + IRQ_GIE + IRQ_GIE + Global Interrupt Enable Register + 0x020 + 32 + read-write + + 0x0 + + + ENABLE + ENABLE + Global Interrupt Enable +When set, interrupts enabled in the IRQ_IER register can assert the ip2intc_irpt interrupt output. +0x0 - Disable the interrupt output +0x1 - Enable the interrupt output + + 0 + 1 + read-write + + 0 + 0 + + false + + + + IRQ_IER + IRQ_IER + Interrupt Enable Register + 0x024 + 32 + read-write + + 0x0 + + + CTLR_DESC_FIFO_ALMOST_EMPTY + CTLR_DESC_FIFO_ALMOST_EMPTY + Controller Descriptor FIFO Almost Empty Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_DESC_FIFO_ALMOST_EMPTY field as set. +0x0 - CTLR_DESC_FIFO_ALMOST_EMPTY interrupt disabled +0x1 - CTLR_DESC_FIFO_ALMOST_EMPTY interrupt enabled + + 15 + 1 + read-write + + 0 + 0 + + false + + + CTLR_RX_FIFO_FILL_THRESHOLD + CTLR_RX_FIFO_FILL_THRESHOLD + Controller Receive FIFO Fill Threshold Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_RX_FIFO_FILL_THRESHOLD field as set. +0x0 - CTLR_RX_FIFO_FILL_THRESHOLD interrupt disabled +0x1 - CTLR_RX_FIFO_FILL_THRESHOLD interrupt enabled + + 14 + 1 + read-write + + 0 + 0 + + false + + + CTLR_DESC_FIFO_EMPTY + CTLR_DESC_FIFO_EMPTY + Controller Descriptor FIFO Empty Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_DESC_FIFO_EMPTY field as set. +0x0 - CTLR_DESC_FIFO_EMPTY interrupt disabled +0x1 - CTLR_DESC_FIFO_EMPTY interrupt enabled + + 13 + 1 + read-write + + 0 + 0 + + false + + + CTLR_DONE + CTLR_DONE + Controller Done Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_DONE field as set. +0x0 - CTLR_DONE interrupt disabled +0x1 - CTLR_DONE interrupt enabled + + 12 + 1 + read-write + + 0 + 0 + + false + + + CTLR_PEC_ERROR + CTLR_PEC_ERROR + Controller PEC Error Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_PEC_ERROR field as set. +0x0 - CTLR_PEC_ERROR interrupt disabled +0x1 - CTLR_PEC_ERROR interrupt enabled + + 11 + 1 + read-write + + 0 + 0 + + false + + + CTLR_NACK_ERROR + CTLR_NACK_ERROR + Controller NACK Error Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_NACK_ERROR field as set. +0x0 - CTLR_NACK_ERROR interrupt disabled +0x1 - CTLR_NACK_ERROR interrupt enabled + + 10 + 1 + read-write + + 0 + 0 + + false + + + CTLR_LOA + CTLR_LOA + Controller Loss of Arbitration Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the CTLR_LOA field as set. +0x0 - CTLR_LOA interrupt disabled +0x1 - CTLR_LOA interrupt enabled + + 9 + 1 + read-write + + 0 + 0 + + false + + + TGT_DESC_FIFO_ALMOST_EMPTY + TGT_DESC_FIFO_ALMOST_EMPTY + Target Descriptor FIFO Almost Empty Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_DESC_FIFO_ALMOST_EMPTY field as set. +0x0 - TGT_DESC_FIFO_ALMOST_EMPTY interrupt disabled +0x1 - TGT_DESC_FIFO_ALMOST_EMPTY interrupt enabled + + 8 + 1 + read-write + + 0 + 0 + + false + + + TGT_WRITE + TGT_WRITE + Target Write Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_WRITE field as set. +0x0 - TGT_WRITE interrupt disabled +0x1 - TGT_WRITE interrupt enabled + + 7 + 1 + read-write + + 0 + 0 + + false + + + TGT_READ + TGT_READ + Target Read Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_READ field as set. +0x0 - TGT_READ interrupt disabled +0x1 - TGT_READ interrupt enabled + + 6 + 1 + read-write + + 0 + 0 + + false + + + TGT_RX_FIFO_FILL_THRESHOLD + TGT_RX_FIFO_FILL_THRESHOLD + Target Receive FIFO Fill Threshold Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_RX_FIFO_FILL_THRESHOLD field as set. +0x0 - TGT_RX_FIFO_FILL_THRESHOLD interrupt disabled +0x1 - TGT_RX_FIFO_FILL_THRESHOLD interrupt enabled + + 5 + 1 + read-write + + 0 + 0 + + false + + + TGT_DESC_FIFO_EMPTY + TGT_DESC_FIFO_EMPTY + Target Descriptor FIFO Empty Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_DESC_FIFO_EMPTY field as set. +0x0 - TGT_DESC_FIFO_EMPTY interrupt disabled +0x1 - TGT_DESC_FIFO_EMPTY interrupt enabled + + 4 + 1 + read-write + + 0 + 0 + + false + + + TGT_DONE + TGT_DONE + Target Done Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_DONE field as set. +0x0 - TGT_DONE interrupt disabled +0x1 - TGT_DONE interrupt enabled + + 3 + 1 + read-write + + 0 + 0 + + false + + + TGT_PEC_ERROR + TGT_PEC_ERROR + Target PEC Error Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_PEC_ERROR field as set. +0x0 - TGT_PEC_ERROR interrupt disabled +0x1 - TGT_PEC_ERROR interrupt enabled + + 2 + 1 + read-write + + 0 + 0 + + false + + + TGT_LOA + TGT_LOA + Target Loss of Arbitration Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the TGT_LOA field as set. +0x0 - TGT_LOA interrupt disabled +0x1 - TGT_LOA interrupt enabled + + 1 + 1 + read-write + + 0 + 0 + + false + + + ERROR_IRQ + ERROR_IRQ + Error Interrupt Enable +When set, an interrupt will be generated when the IRQ_ISR register reports the ERROR_IRQ field as set. +0x0 - ERROR_IRQ interrupt disabled +0x1 - ERROR_IRQ interrupt enabled + + 0 + 1 + read-write + + 0 + 0 + + false + + + + IRQ_ISR + IRQ_ISR + Interrupt Status Register + 0x028 + 32 + read-write + + 0x0 + + + CTLR_DESC_FIFO_ALMOST_EMPTY + CTLR_DESC_FIFO_ALMOST_EMPTY + Controller Descriptor FIFO Almost Empty Interrupt Status +Set when the Controller has detected only one descriptor in the Descriptor FIFO and a transaction is in progress. +0x0 - Controller Descriptor FIFO contains more than one descriptor or no transaction in progress +0x1 - Controller Descriptor FIFO only contains one descriptor and a transaction is in progress + + 15 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_RX_FIFO_FILL_THRESHOLD + CTLR_RX_FIFO_FILL_THRESHOLD + Controller Receive FIFO Fill Threshold Interrupt Status +Set when the Controller Receive FIFO has reached the fill level configured in the CTLR_RX_FIFO_FILL_THRESHOLD register. +0x0 - Controller Receive FIFO fill level below configured threshold +0x1 - Controller Receive FIFO has reached the configured fill threshold + + 14 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_DESC_FIFO_EMPTY + CTLR_DESC_FIFO_EMPTY + Controller Descriptor FIFO Empty Interrupt Status +Set when the Controller has detected the Descriptor FIFO is empty and another descriptor is required. +0x0 - Controller Descriptor FIFO not empty or descriptor not required +0x1 - Controller Descriptor FIFO empty and a descriptor is required + + 13 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_DONE + CTLR_DONE + Controller Done Interrupt Status +Set when the Controller has successfully completed the transaction. +0x0 - Controller transaction not complete or no transaction in progress +0x1 - Controller transaction is complete + + 12 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_PEC_ERROR + CTLR_PEC_ERROR + Controller PEC Error Interrupt Status +Set when the Controller has detected a PEC error during a Read transaction with PEC enabled. +0x0 - No PEC error +0x1 - PEC error detected during Read + + 11 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_NACK_ERROR + CTLR_NACK_ERROR + Controller NACK Error Interrupt Status +Set when the Controller has received a NACK response from the Target following transmission of a byte as Controller-transmitter. +0x0 - No NACK response from Target +0x1 - Target responded with NACK + + 10 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_LOA + CTLR_LOA + Controller Loss of Arbitration Interrupt Status +Set when the Controller has detected loss of arbitration as a Controller-transmitter. +0x0 - No loss of arbitration detected +0x1 - Loss of arbitration detected + + 9 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_DESC_FIFO_ALMOST_EMPTY + TGT_DESC_FIFO_ALMOST_EMPTY + Target Descriptor FIFO Almost Empty Interrupt Status +Set when the Target has detected only one descriptor in the Descriptor FIFO and a transaction is in progress +0x0 - Target Descriptor FIFO contains more than one descriptor or no transaction in progress +0x1 - Target Descriptor FIFO only contains one descriptor and a transaction is in progress + + 8 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_WRITE + TGT_WRITE + Target Write Interrupt Status +Set when the Target has detected a start of write transaction for a Target device enabled in TGT_CONTROL_[7:0] +0x0 - No write detected matching an enabled target device +0x1 - Start of write detected matching an enabled target device, details available in TGT_STATUS + + 7 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_READ + TGT_READ + Target Read Interrupt Status +Set when the Target has detected a start of read transaction for a Target device enabled in TGT_CONTROL_[7:0] +0x0 - No read detected matching an enabled target device +0x1 - Start of read detected matching an enabled target device, details available in TGT_STATUS + + 6 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_RX_FIFO_FILL_THRESHOLD + TGT_RX_FIFO_FILL_THRESHOLD + Target Receive FIFO Fill Threshold Interrupt Status +Set when the Target Receive FIFO has reached the fill level configured in the TGT_RX_FIFO_FILL_THRESHOLD register +0x0 - Target Receive FIFO fill level below configured threshold +0x1 - Target Receive FIFO has reached the configured fill threshold + + 5 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_DESC_FIFO_EMPTY + TGT_DESC_FIFO_EMPTY + Target Descriptor FIFO Empty Interrupt Status +Set when the Target has detected the Descriptor FIFO is empty and another descriptor is required +0x0 - Target Descriptor FIFO not empty or descriptor not required +0x1 - Target Descriptor FIFO empty and a descriptor is required + + 4 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_DONE + TGT_DONE + Target Done Interrupt Status +Target has detected a STOP condition, transaction is complete and no PEC error detected (if write, if applicable) +0x0 - Target transaction not done +0x1 - Target transaction done + + 3 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_PEC_ERROR + TGT_PEC_ERROR + Target PEC Error Interrupt Status +Set when the Target has detected a STOP condition, transaction is complete but PEC error detected (only applicable to Writes) +0x0 - Target transaction not done +0x1 - Target transaction done, but PEC error detected + + 2 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_LOA + TGT_LOA + Target Loss of Arbitration Interrupt Status +When set the Target has detected loss of arbitration as a Target-transmitter +0x0 - No loss of arbitration detected +0x1 - Loss of arbitration detected + + 1 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + ERROR_IRQ + ERROR_IRQ + Error Interrupt Status +Set when an error condition has occurred that is both enabled in the ERR_IRQ_IER register and set in the ERR_IRQ_ISR register. +0x0 - No error condition detected +0x1 - Error condition detected + + 0 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + + ERR_IRQ_IER + ERR_IRQ_IER + Error Interrupt Enable Register + 0x02C + 32 + read-write + + 0x0 + + + PHY_CTLR_CEXT_TIMEOUT + PHY_CTLR_CEXT_TIMEOUT + Controller PHY CEXT Timeout Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the PHY_CTLR_CEXT_TIMEOUT field as set. +0x0 - PHY_CTLR_CEXT_TIMEOUT interrupt disabled +0x1 - PHY_CTLR_CEXT_TIMEOUT interrupt enabled + + 19 + 1 + read-write + + 0 + 0 + + false + + + PHY_CTLR_TEXT_TIMEOUT + PHY_CTLR_TEXT_TIMEOUT + Controller PHY TEXT Timeout Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the PHY_CTLR_TEXT_TIMEOUT field as set. +0x0 - PHY_CTLR_TEXT_TIMEOUT interrupt disabled +0x1 - PHY_CTLR_TEXT_TIMEOUT interrupt enabled + + 18 + 1 + read-write + + 0 + 0 + + false + + + CTLR_RX_FIFO_ERROR + CTLR_RX_FIFO_ERROR + Controller Receive FIFO Error Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_RX_FIFO_ERROR field as set. +0x0 - CTLR_RX_FIFO_ERROR interrupt disabled +0x1 - CTLR_RX_FIFO_ERROR interrupt enabled + + 17 + 1 + read-write + + 0 + 0 + + false + + + CTLR_RX_FIFO_OVERFLOW + CTLR_RX_FIFO_OVERFLOW + Controller Receive FIFO Overflow Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_RX_FIFO_OVERFLOW field as set. +0x0 - CTLR_RX_FIFO_OVERFLOW interrupt disabled +0x1 - CTLR_RX_FIFO_OVERFLOW interrupt enabled + + 16 + 1 + read-write + + 0 + 0 + + false + + + CTLR_RX_FIFO_UNDERFLOW + CTLR_RX_FIFO_UNDERFLOW + Controller Receive FIFO Underflow Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_RX_FIFO_UNDERFLOW field as set. +0x0 - CTLR_RX_FIFO_UNDERFLOW interrupt disabled +0x1 - CTLR_RX_FIFO_UNDERFLOW interrupt enabled + + 15 + 1 + read-write + + 0 + 0 + + false + + + CTLR_DESC_FIFO_ERROR + CTLR_DESC_FIFO_ERROR + Controller Descriptor FIFO Error Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_DESC_FIFO_ERROR field as set. +0x0 - CTLR_DESC_FIFO_ERROR interrupt disabled +0x1 - CTLR_DESC_FIFO_ERROR interrupt enabled + + 14 + 1 + read-write + + 0 + 0 + + false + + + CTLR_DESC_FIFO_OVERFLOW + CTLR_DESC_FIFO_OVERFLOW + Controller Descriptor FIFO Overflow Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_DESC_FIFO_OVERFLOW field as set. +0x0 - CTLR_DESC_FIFO_OVERFLOW interrupt disabled +0x1 - CTLR_DESC_FIFO_OVERFLOW interrupt enabled + + 13 + 1 + read-write + + 0 + 0 + + false + + + CTLR_DESC_FIFO_UNDERFLOW + CTLR_DESC_FIFO_UNDERFLOW + Controller Descriptor FIFO Underflow Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_DESC_FIFO_UNDERFLOW field as set. +0x0 - CTLR_DESC_FIFO_UNDERFLOW interrupt disabled +0x1 - CTLR_DESC_FIFO_UNDERFLOW interrupt enabled + + 12 + 1 + read-write + + 0 + 0 + + false + + + CTLR_DESC_ERROR + CTLR_DESC_ERROR + Controller Descriptor Error Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the CTLR_DESC_ERROR field as set. +0x0 - CTLR_DESC_ERROR interrupt disabled +0x1 - CTLR_DESC_ERROR interrupt enabled + + 11 + 1 + read-write + + 0 + 0 + + false + + + PHY_TGT_TEXT_TIMEOUT + PHY_TGT_TEXT_TIMEOUT + Target PHY TEXT Timeout Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the PHY_TGT_TEXT_TIMEOUT field as set. +0x0 - PHY_TGT_TEXT_TIMEOUT interrupt disabled +0x1 - PHY_TGT_TEXT_TIMEOUT interrupt enabled + + 10 + 1 + read-write + + 0 + 0 + + false + + + TGT_RX_FIFO_ERROR + TGT_RX_FIFO_ERROR + Target Receive FIFO Error Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_RX_FIFO_ERROR field as set. +0x0 - TGT_RX_FIFO_ERROR interrupt disabled +0x1 - TGT_RX_FIFO_ERROR interrupt enabled + + 9 + 1 + read-write + + 0 + 0 + + false + + + TGT_RX_FIFO_OVERFLOW + TGT_RX_FIFO_OVERFLOW + Target Receive FIFO Overflow Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_RX_FIFO_OVERFLOW field as set. +0x0 - TGT_RX_FIFO_OVERFLOW interrupt disabled +0x1 - TGT_RX_FIFO_OVERFLOW interrupt enabled + + 8 + 1 + read-write + + 0 + 0 + + false + + + TGT_RX_FIFO_UNDERFLOW + TGT_RX_FIFO_UNDERFLOW + Target Receive FIFO Underflow Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_RX_FIFO_UNDERFLOW field as set. +0x0 - TGT_RX_FIFO_UNDERFLOW interrupt disabled +0x1 - TGT_RX_FIFO_UNDERFLOW interrupt enabled + + 7 + 1 + read-write + + 0 + 0 + + false + + + TGT_DESC_FIFO_ERROR + TGT_DESC_FIFO_ERROR + Target Descriptor FIFO Error Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_DESC_FIFO_ERROR field as set. +0x0 - TGT_DESC_FIFO_ERROR interrupt disabled +0x1 - TGT_DESC_FIFO_ERROR interrupt enabled + + 6 + 1 + read-write + + 0 + 0 + + false + + + TGT_DESC_FIFO_OVERFLOW + TGT_DESC_FIFO_OVERFLOW + Target Descriptor FIFO Overflow Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_DESC_FIFO_OVERFLOW field as set. +0x0 - TGT_DESC_FIFO_OVERFLOW interrupt disabled +0x1 - TGT_DESC_FIFO_OVERFLOW interrupt enabled + + 5 + 1 + read-write + + 0 + 0 + + false + + + TGT_DESC_FIFO_UNDERFLOW + TGT_DESC_FIFO_UNDERFLOW + Target Descriptor FIFO Underflow Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_DESC_FIFO_UNDERFLOW field as set. +0x0 - TGT_DESC_FIFO_UNDERFLOW interrupt disabled +0x1 - TGT_DESC_FIFO_UNDERFLOW interrupt enabled + + 4 + 1 + read-write + + 0 + 0 + + false + + + TGT_DESC_ERROR + TGT_DESC_ERROR + Target Descriptor Error Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the TGT_DESC_ERROR field as set. +0x0 - TGT_DESC_ERROR interrupt disabled +0x1 - TGT_DESC_ERROR interrupt enabled + + 3 + 1 + read-write + + 0 + 0 + + false + + + PHY_UNEXPTD_BUS_IDLE + PHY_UNEXPTD_BUS_IDLE + PHY Unexpected Bus Idle Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the PHY_UNEXPTD_BUS_IDLE field as set. +0x0 - PHY_UNEXPTD_BUS_IDLE interrupt disabled +0x1 - PHY_UNEXPTD_BUS_IDLE interrupt enabled + + 2 + 1 + read-write + + 0 + 0 + + false + + + PHY_SMBDAT_LOW_TIMEOUT + PHY_SMBDAT_LOW_TIMEOUT + PHY SMBDAT Low Timeout Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the PHY_SMBDAT_LOW_TIMEOUT field as set. +0x0 - PHY_SMBDAT_LOW_TIMEOUT interrupt disabled +0x1 - PHY_SMBDAT_LOW_TIMEOUT interrupt enabled + + 1 + 1 + read-write + + 0 + 0 + + false + + + PHY_SMBCLK_LOW_TIMEOUT + PHY_SMBCLK_LOW_TIMEOUT + PHY SMBCLK Low Timeout Interrupt Enable +When set, an interrupt will be generated when the ERR_IRQ_ISR register reports the PHY_SMBCLK_LOW_TIMEOUT field as set. +0x0 - PHY_SMBCLK_LOW_TIMEOUT interrupt disabled +0x1 - PHY_SMBCLK_LOW_TIMEOUT interrupt enabled + + 0 + 1 + read-write + + 0 + 0 + + false + + + + ERR_IRQ_ISR + ERR_IRQ_ISR + Error Interrupt Status Register + 0x030 + 32 + read-write + + 0x0 + + + PHY_CTLR_CEXT_TIMEOUT + PHY_CTLR_CEXT_TIMEOUT + Controller PHY CEXT Timeout Interrupt Status +Set when the Controller PHY has detected SMBCLK stretching performed by the Controller function beyond the threshold configured in the PHY_CTLR_CEXT_TIMEOUT register. +0x0 - Controller function clock stretching has not exceeded threshold +0x1 - Controller function clock stretching has exceeded the threshold + + 19 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + PHY_CTLR_TEXT_TIMEOUT + PHY_CTLR_TEXT_TIMEOUT + Controller PHY TEXT Timeout Interrupt Status +Set when the Controller has detected SMBCLK stretching performed by an external Target beyond the threshold configured in the PHY_CTLR_TEXT_TIMEOUT register. +0x0 - Controller function has not detected Target clock stretching that exceeds the threshold +0x1 - Controller function has detected Target clock stretching that exceeds the threshold + + 18 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_RX_FIFO_ERROR + CTLR_RX_FIFO_ERROR + Controller Receive FIFO Error Interrupt Status +Set when the Controller has detected that an attempt to read or write to the Receive FIFO while it is in reset has been made. +0x0 - No Receive FIFO read/write error detected +0x1 - Receive FIFO read/write error detected + + 17 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_RX_FIFO_OVERFLOW + CTLR_RX_FIFO_OVERFLOW + Controller Receive FIFO Overflow Interrupt Status +Set when the Controller has detected the Receive FIFO has overflowed. +0x0 - No Receive FIFO overflow detected +0x1 - Receive FIFO overflow detected + + 16 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_RX_FIFO_UNDERFLOW + CTLR_RX_FIFO_UNDERFLOW + Controller Receive FIFO Underflow Interrupt Status +Set when the Controller has detected the Receive FIFO has underflowed. +0x0 - No Receive FIFO underflow detected +0x1 - Receive FIFO underflow detected + + 15 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_DESC_FIFO_ERROR + CTLR_DESC_FIFO_ERROR + Controller Descriptor FIFO Error Interrupt Status +Set when the Controller has detected that an attempt to write to the Descriptor FIFO while it is in reset has been made. +0x0 - No Descriptor FIFO write error detected +0x1 - Descriptor FIFO write error detected + + 14 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_DESC_FIFO_OVERFLOW + CTLR_DESC_FIFO_OVERFLOW + Controller Descriptor FIFO Overflow Interrupt Status +Set when the Controller has detected the Descriptor FIFO has overflowed. +0x0 - No Descriptor FIFO overflow detected +0x1 - Descriptor FIFO overflow detected + + 13 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_DESC_FIFO_UNDERFLOW + CTLR_DESC_FIFO_UNDERFLOW + Controller Descriptor FIFO Underflow Interrupt Status +Set when the Controller has detected the Descriptor FIFO has underflowed. +0x0 - No Descriptor FIFO underflow detected +0x1 - Descriptor FIFO underflow detected + + 12 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + CTLR_DESC_ERROR + CTLR_DESC_ERROR + Controller Descriptor Error Interrupt Status +Set when the Controller has received an invalid descriptor ID via the Descriptor FIFO or the first descriptor in the sequence is not a START descriptor. +0x0 - No descriptor error detected +0x1 - Descriptor error detected + + 11 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + PHY_TGT_TEXT_TIMEOUT + PHY_TGT_TEXT_TIMEOUT + Target PHY TEXT Timeout Interrupt Status +Set when the PHY has detected SMBCLK stretching performed by the Target function beyond the threshold configured in the PHY_TGT_TEXT_TIMEOUT register. +0x0 - Target function clock stretching has not exceeded threshold +0x1 - Target function clock stretching has exceeded the threshold + + 10 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_RX_FIFO_ERROR + TGT_RX_FIFO_ERROR + Target Receive FIFO Error Interrupt Status +Set when the Target has detected that an attempt to read or write to the Receive FIFO whilst it is in reset has been made. +0x0 - No Receive FIFO read/write error detected +0x1 - Receive FIFO read/write error detected + + 9 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_RX_FIFO_OVERFLOW + TGT_RX_FIFO_OVERFLOW + Target Receive FIFO Overflow Interrupt Status +Set when the Target has detected the Receive FIFO has overflowed +0x0 - No Receive FIFO overflow detected +0x1 - Receive FIFO overflow detected + + 8 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_RX_FIFO_UNDERFLOW + TGT_RX_FIFO_UNDERFLOW + Target Receive FIFO Underflow Interrupt Status +Set when the Target has detected the Receive FIFO has underflowed +0x0 - No Receive FIFO underflow detected +0x1 - Receive FIFO underflow detected + + 7 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_DESC_FIFO_ERROR + TGT_DESC_FIFO_ERROR + Target Descriptor FIFO Error Interrupt Status +Set when the Target has detected that an attempt to write to the Descriptor FIFO whilst it is in reset has been made. +0x0 - No Descriptor FIFO write error detected +0x1 - Descriptor FIFO write error detected + + 6 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_DESC_FIFO_OVERFLOW + TGT_DESC_FIFO_OVERFLOW + Target Descriptor FIFO Overflow Interrupt Status +Set when the Target has detected the Descriptor FIFO has overflowed +0x0 - No Descriptor FIFO overflow detected +0x1 - Descriptor FIFO overflow detected + + 5 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_DESC_FIFO_UNDERFLOW + TGT_DESC_FIFO_UNDERFLOW + Target Descriptor FIFO Underflow Interrupt Status +Set when the Target has detected the Descriptor FIFO has underflowed +0x0 - No Descriptor FIFO underflow detected +0x1 - Descriptor FIFO underflow detected + + 4 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + TGT_DESC_ERROR + TGT_DESC_ERROR + Target Descriptor Error Interrupt Status +Set when the Target has received an invalid descriptor via the Descriptor FIFO. +This is asserted when either an undefined descriptor ID or unexpected type (e.g. read descriptor during a write) is received. +0x0 - No descriptor error detected +0x1 - Descriptor error detected + + 3 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + PHY_UNEXPTD_BUS_IDLE + PHY_UNEXPTD_BUS_IDLE + PHY Unexpected Bus Idle Interrupt Status +Set when the PHY has detected an unexpected bus idle condition by observing SMBCLK/SMBDAT inputs high beyond the threshold configured in the PHY_IDLE_THRESHOLD register, whilst a transaction is in progress (i.e. no STOP condition). +0x0 - No unexpected bus idle detected +0x1 - Unexpected bus idle condition detected + + 2 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + PHY_SMBDAT_LOW_TIMEOUT + PHY_SMBDAT_LOW_TIMEOUT + PHY SMBDAT Low Timeout Interrupt Status +Set when the PHY has detected SMBDAT persistently low following a rising edge on SMBCLK for the timeout value configured in the PHY_TIMEOUT_MAX register. +0x0 - No SMBDAT low timeout +0x1 - SMBDAT low timeout detected + + 1 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + PHY_SMBCLK_LOW_TIMEOUT + PHY_SMBCLK_LOW_TIMEOUT + PHY SMBCLK Low Timeout Interrupt Status +Set when the PHY has detected SMBCLK persistently low for the timeout value configured in the PHY_TIMEOUT_MIN register. +0x0 - No SMBCLK low timeout +0x1 - SMBCLK low timeout detected + + 0 + 1 + read-write + oneToClear + + 0 + 0 + + false + + + + IRQ_ISR_FORCE + IRQ_ISR_FORCE + Debug IRQ ISR Force Control Register + 0x034 + 32 + write-only + + 0x0 + + + IRQ_ISR_FORCE + IRQ_ISR_FORCE + Debug IRQ ISR Force +Debug - When set, the equivalent bit in the IRQ_ISR register is set to '1' in order to force assertion of the interrupt source. +0x0 - No forced assertion of the equivalent bit in IRQ_ISR register +0x1 - Equivalent bit in the IRQ_ISR register is forced to '1' + + 0 + 16 + write-only + + 0 + 0 + + false + + + + ERR_IRQ_ISR_FORCE + ERR_IRQ_ISR_FORCE + Debug Error IRQ ISR Force Control Register + 0x038 + 32 + write-only + + 0x0 + + + ERR_IRQ_ISR_FORCE + ERR_IRQ_ISR_FORCE + Debug Error IRQ ISR Force +Debug - When set, the equivalent bit in the ERR_IRQ_ISR register is set to '1' in order to force assertion of the interrupt source. +0x0 - No forced assertion of the equivalent bit in ERR_IRQ_ISR register +0x1 - Equivalent bit in the ERR_IRQ_ISR register is forced to '1' + + 0 + 20 + write-only + + 0 + 0 + + false + + + + PHY_STATUS + PHY_STATUS + PHY Status Register + 0x200 + 32 + read-only + + 0x0 + + + SMBDAT_LOW_TIMEOUT + SMBDAT_LOW_TIMEOUT + SMBDAT Low Timeout Status +Indicates when the SMBus PHY has detected a SMBDAT low timeout in accordance with the threshold configured in the PHY_TIMEOUT_MAX register. +0x0 - SMBDAT low timeout not detected +0x1 - SMBDAT low timeout detected + + 2 + 1 + read-only + + 0 + 0 + + false + + + SMBCLK_LOW_TIMEOUT + SMBCLK_LOW_TIMEOUT + SMBCLK Low Timeout Status +Indicates when the SMBus PHY has detected a SMBCLK low timeout in accordance with the threshold configured in the PHY_TIMEOUT_MIN register. +0x0 - SMBCLK low timeout not detected +0x1 - SMBCLK low timeout detected + + 1 + 1 + read-only + + 0 + 0 + + false + + + BUS_IDLE + BUS_IDLE + Bus Idle Status +Indicates when the SMBus PHY has detected the Bus Idle condition +0x0 - Bus Idle condition not detected +0x1 - Bus is Idle + + 0 + 1 + read-only + + 0 + 0 + + false + + + + PHY_FILTER_CONTROL + PHY_FILTER_CONTROL + PHY Filter Control Register + 0x204 + 32 + read-write + + 0x80000000 + + + ENABLE + ENABLE + Input Glitch Filter Enable +Enable the SMBCLK/SMBDAT input glitch filter +0x0 - Input glitch filter disabled +0x1 - Input glitch filter enabled + + 31 + 1 + read-write + + 0 + 0 + + false + + + DURATION + DURATION + Input Glitch Filter Duration +Configure the duration that the SMBCLK or SMBDAT inputs must be stable for before registering as a change in state. +This value is calculated as Time = s_axi_aclk period x (DURATION + 1) +This value must be configured to meet tSPIKE:MAX in accordance with the SMBus Specification. + + 0 + 5 + read-write + + 0 + 0 + + false + + + + PHY_BUS_FREE_TIME + PHY_BUS_FREE_TIME + PHY Bus Free Time Control Register + 0x208 + 32 + read-write + + 0x0 + + + BUS_FREE_TIME + BUS_FREE_TIME + Bus Free Time Control +Configure the amount of time to wait following detection of a STOP condition before declaring a bus idle condition. +This value is calculated as Time = s_axi_aclk period x (BUS_FREE_TIME + 1) +This value must be configured to meet tBUF:MIN in accordance with the SMBus Specification. + + 0 + 12 + read-write + + 0 + 0 + + false + + + + PHY_IDLE_THRESHOLD + PHY_IDLE_THRESHOLD + PHY Idle Threshold Control Register + 0x20C + 32 + read-write + + 0x0 + + + IDLE_THRESHOLD + IDLE_THRESHOLD + Bus Idle Time Control +Configure the amount of time that both SMBCLK and SMBDAT must be high before declaring a bus idle condition. +This value is calculated as Time = s_axi_aclk period x (IDLE_THRESHOLD + 1) +This value must be configured to meet tHIGH:MAX in accordance with the SMBus Specification. + + 0 + 15 + read-write + + 0 + 0 + + false + + + + PHY_TIMEOUT_PRESCALER + PHY_TIMEOUT_PRESCALER + PHY Timeout Prescaler Control Register + 0x210 + 32 + read-write + + 0x0 + + + TIMEOUT_PRESCALER + TIMEOUT_PRESCALER + Timeout Prescaler Configuration +Configure the amount of time to wait before incrementing either the PHY_TIMEOUT_MIN or PHY_TIMEOUT_MAX counters. +This value is calculated as Prescaler_Time = s_axi_aclk period x (TIMEOUT_PRESCALER + 1) +The Prescaler_Time should be configured for 10us in order to stay within range of the PHY_TIMEOUT_MIN and PHY_TIMEOUT_MAX counters. + + 0 + 13 + read-write + + 0 + 0 + + false + + + + PHY_TIMEOUT_MIN + PHY_TIMEOUT_MIN + PHY Minimum Timeout Control Register + 0x214 + 32 + read-write + + 0x0 + + + TIMEOUT_ENABLE + TIMEOUT_ENABLE + Minimum Timeout Detection Enable +Enable/disable the SMBCLK low timeout detection and subsequent consequent actions. +0x0 - SMBCLK low timeout detection disabled +0x1 - SMBCLK low timeout detection enabled + + 31 + 1 + read-write + + 0 + 0 + + false + + + TIMEOUT_MIN + TIMEOUT_MIN + Minimum Timeout Configuration +Configure the threshold used to detect a SMBCLK low timeout and trigger the PHY_SMBCLK_TIMEOUT interrupt. +This value must be configured to meet tTIMEOUT:MIN in accordance with the SMBus Specification. +This value is calculated as Timeout_Min_Time = ((TIMEOUT_MIN + 1) x Prescaler_Time) - Prescaler_Time + + 0 + 12 + read-write + + 0 + 0 + + false + + + + PHY_TIMEOUT_MAX + PHY_TIMEOUT_MAX + PHY Maximum Timeout Control Register + 0x218 + 32 + read-write + + 0x0 + + + TIMEOUT_MAX + TIMEOUT_MAX + Maximum Timeout Configuration +Configure the threshold used to detect a SMBDAT low timeout and trigger the PHY_SMBDAT_TIMEOUT interrupt. +This value must be configured to meet tTIMEOUT:MAX in accordance with the SMBus Specification. +This value is calculated as Timeout_Max_Time = ((TIMEOUT_MAX + 1) x Prescaler_Time) - Prescaler_Time + + 0 + 12 + read-write + + 0 + 0 + + false + + + + PHY_RESET_CONTROL + PHY_RESET_CONTROL + PHY Reset Control Register + 0x21C + 32 + read-write + + 0x0 + + + SMBCLK_FORCE_TIMEOUT + SMBCLK_FORCE_TIMEOUT + SMBCLK Timeout Force Control +Override the SMBCLK low detection to force assertion of this timeout and subsequent consequent actions. +0x0 - No SMBCLK low timeout forced assertion +0x1 - Force assertion of the SMBCLK low timeout and subsequent consequent actions + + 31 + 1 + write-only + + 0 + 0 + + false + + + SMBCLK_FORCE_LOW + SMBCLK_FORCE_LOW + SMBCLK Output Force Control +Override the PHY control of the SMBCLK and force the output low. +0xCFB = SMBCLK force low +Any other value = SMBCLK under PHY control + + 0 + 12 + read-write + + 0 + 0 + + false + + + + PHY_TGT_DATA_SETUP + PHY_TGT_DATA_SETUP + Target PHY Data Setup Control Register + 0x400 + 32 + read-write + + 0x0 + + + TGT_DATA_SETUP + TGT_DATA_SETUP + Target PHY Data Setup +Configure the data setup time when operating as a Target-transmitter post clock stretching. +This value must be configured to meet tSU:DAT:Min in accordance with the SMBus Specification and account for tR:Max/tF:Max. +This value is calculated as Setup Time = s_axi_aclk period x (TGT_DATA_SETUP + 1) + + 0 + 10 + read-write + + 0 + 0 + + false + + + + PHY_TGT_TEXT_PRESCALER + PHY_TGT_TEXT_PRESCALER + Target PHY TEXT Timeout Prescaler Configuration Register + 0x404 + 32 + read-write + + 0x0 + + + TGT_TEXT_PRESCALER + TGT_TEXT_PRESCALER + Target PHY TEXT Timeout Prescaler Configuration +Configure the amount of time to measure before incrementing the PHY_TGT_TEXT_TIMEOUT counter when SMBCLK stretching is active within the Target function. +This value is calculated as Text_Prescaler_Time = s_axi_aclk period x (TGT_TEXT_PRESCALER+ 1) +The Text_Prescaler_Time should be configured for 1us in order to stay within range of the PHY_TGT_TEXT_TIMEOUT counter. + + 0 + 9 + read-write + + 0 + 0 + + false + + + + PHY_TGT_TEXT_TIMEOUT + PHY_TGT_TEXT_TIMEOUT + Target PHY TEXT Timeout Configuration Register + 0x408 + 32 + read-write + + 0x0 + + + TGT_TEXT_TIMEOUT + TGT_TEXT_TIMEOUT + Target PHY TEXT Timeout Configuration +Configure the threshold used to detect that the Target function has exceeded the cumulative clock stretching threshold and trigger the TGT_TEXT_TIMEOUT interrupt. +This value must be configured to meet tLOW:TEXT in accordance with the SMBus Specification. +This value is calculated as Text_Timeout_Time = TGT_TEXT_TIMEOUT x Text_Prescaler_Time + + 0 + 15 + read-write + + 0 + 0 + + false + + + + PHY_TGT_TEXT_MAX + PHY_TGT_TEXT_MAX + Target PHY TEXT Timeout Max Status Register + 0x40C + 32 + read-write + + 0x0 + + + TGT_TEXT_MAX + TGT_TEXT_MAX + Target PHY TEXT Timeout Max +Indicates the maximum amount of cumulative time in Text_Prescaler_Time units that the Target function has spent performing SMBCLK stretching during any single transaction (between an initial START and a STOP). + + 0 + 15 + read-write + clear + + 0 + 0 + + false + + + + PHY_TGT_DBG_STATE + PHY_TGT_DBG_STATE + Target PHY Debug State Register + 0x410 + 32 + read-only + + 0x1 + + + DBG_STATE + DBG_STATE + Target PHY Debug State +Reports the current Target PHY FSM State to assist with debug. + + 0 + 8 + read-only + + 0 + 0 + + false + + + + PHY_TGT_DATA_HOLD + PHY_TGT_DATA_HOLD + Target PHY Data Hold Control Register + 0x414 + 32 + read-write + + 0x0 + + + TGT_DATA_HOLD + TGT_DATA_HOLD + Target PHY Data Hold +Configure the data hold time when operating as a Target-transmitter. +This value must be configured to meet tSU:DAT:Min in accordance with the SMBus Specification. +This value is calculated as - +If PHY_FILTER_CONTROL__ENABLE = 0x1 +Hold Time = s_axi_aclk period x (TGT_DATA_HOLD + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) +If PHY_FILTER_CONTROL__ENABLE = 0x0 +Hold Time = s_axi_aclk period x (TGT_DATA_HOLD + 8) + + 0 + 10 + read-write + + 0 + 0 + + false + + + + TGT_STATUS + TGT_STATUS + Target Status Register + 0x600 + 32 + read-only + + 0x0 + + + ACTIVE + ACTIVE + Target Active Status +Indicates that the Target function has received a transaction that matches an enabled address in TGT_CONTROL_[7:0] +0x0 - No active transaction in progress +0x1 - Active Target transaction in progress + + 8 + 1 + read-only + + 0 + 0 + + false + + + ADDRESS + ADDRESS + Target Address Status +Target address for the current transaction, only valid when ACTIVE = 0x1 + + 1 + 7 + read-only + + 0 + 0 + + false + + + RW + RW + Target Read/Write Status +Indicates the current transaction type, only valid when ACTIVE = 0x1 +0x0 = Write transaction +0x1 = Read transaction + + 0 + 1 + read-only + + 0 + 0 + + false + + + + TGT_DESC_FIFO + TGT_DESC_FIFO + Target Descriptor FIFO Control Register +Writing to this register pushes the value into the Target Descriptor FIFO + + 0x604 + 32 + write-only + + 0x0 + + + ID + ID + Target Descriptor ID. Valid IDs are as follows - +0x0 - TARGET_WRITE_ACK +0x1 - TARGET_WRITE_NACK +0x2 - TARGET_WRITE_PEC +0x8 - TARGET_READ +0x9 - TARGET_READ_PEC + + 8 + 4 + write-only + + 0 + 0 + + false + + + PAYLOAD + PAYLOAD + Target Descriptor Payload +Data payload for transmission as a Target-transmitter. +Valid only when ID = 0x8 (TARGET_READ). + + 0 + 8 + write-only + + 0 + 0 + + false + + + + TGT_DESC_STATUS + TGT_DESC_STATUS + Target Descriptor FIFO Status Register + 0x608 + 32 + read-only + + 0x0 + + + FILL_LEVEL + FILL_LEVEL + Target Descriptor FIFO Fill Level Status +Indicates the current fill level of the Target Descriptor FIFO. + + 8 + 7 + read-only + + 0 + 0 + + false + + + FULL + FULL + Target Descriptor FIFO Full Status +Indicates if the Target Descriptor FIFO is full +0x0 - FIFO not full +0x1 - FIFO full + + 5 + 1 + read-only + + 0 + 0 + + false + + + ALMOST_FULL + ALMOST_FULL + Target Descriptor FIFO Almost Full Status +Indicates if the Target Descriptor FIFO is almost full +0x0 - FIFO has space for more than one descriptor +0x1 - FIFO only has space for one more descriptor + + 4 + 1 + read-only + + 0 + 0 + + false + + + ALMOST_EMPTY + ALMOST_EMPTY + Target Descriptor FIFO Almost Empty Status +Indicates if the Target Descriptor FIFO is almost empty +0x0 - FIFO contains more than one descriptor +0x1 - FIFO contains one descriptor or less + + 1 + 1 + read-only + + 0 + 0 + + false + + + EMPTY + EMPTY + Target Descriptor FIFO Empty Status +Indicates if the Target Descriptor FIFO is empty +0x0 - FIFO not empty +0x1 - FIFO empty + + 0 + 1 + read-only + + 0 + 0 + + false + + + + TGT_RX_FIFO + TGT_RX_FIFO + Target Receive FIFO Register + 0x60C + 32 + read-only + + 0x0 + + + RESET + RESET + Target Receive FIFO Reset Control +When set the Target Receive FIFO is reset to a known state. +Poll the RESET_BUSY field in the TGT_RX_FIFO_STATUS register to determine when the reset is complete. +0x0 - FIFO not reset +0x1 - Reset FIFO + + 31 + 1 + write-only + + 0 + 0 + + false + + + PAYLOAD + PAYLOAD + Target Receive Payload Byte +Reading this register pops a value from the Target Receive FIFO. + + 0 + 8 + read-only + + 0 + 0 + + modify + false + + + + TGT_RX_FIFO_STATUS + TGT_RX_FIFO_STATUS + Target Receive FIFO Status Register + 0x610 + 32 + read-only + + 0x0 + + + MAX_FILL_LEVEL + MAX_FILL_LEVEL + Target Receive FIFO Max Fill Level Status +Indicates the maximum recorded fill level of the Target Receive FIFO. + + 16 + 7 + read-write + oneToClear + + 0 + 0 + + false + + + FILL_LEVEL + FILL_LEVEL + Target Receive FIFO Fill Level Status +Indicates the current fill level of the Target Receive FIFO. + + 8 + 7 + read-only + + 0 + 0 + + false + + + RESET_BUSY + RESET_BUSY + Target Receive FIFO Reset Busy Status +Indicates if the Target Receive FIFO is currently undergoing a reset and is unavailable for either read or write. +0x0 - FIFO not in reset +0x1 - FIFO reset in progress + + 6 + 1 + read-only + + 0 + 0 + + false + + + FULL + FULL + Target Receive FIFO Full Status +Indicates if the Target Receive FIFO is full +0x0 - FIFO not full +0x1 - FIFO full + + 5 + 1 + read-only + + 0 + 0 + + false + + + ALMOST_FULL + ALMOST_FULL + Target Receive FIFO Almost Full Status +Indicates if the Target Receive FIFO is almost full +0x0 - FIFO has space for two or more bytes +0x1 - FIFO only has space for one more byte + + 4 + 1 + read-only + + 0 + 0 + + false + + + ALMOST_EMPTY + ALMOST_EMPTY + Target Receive FIFO Almost Empty Status +Indicates if the Target Receive FIFO is almost empty +0x0 - FIFO contains more than one byte +0x1 - FIFO contains one byte or less + + 1 + 1 + read-only + + 0 + 0 + + false + + + EMPTY + EMPTY + Target Receive FIFO Empty Status +Indicates if the Target Receive FIFO is empty +0x0 - FIFO not empty +0x1 - FIFO empty + + 0 + 1 + read-only + + 0 + 0 + + false + + + + TGT_RX_FIFO_FILL_THRESHOLD + TGT_RX_FIFO_FILL_THRESHOLD + Target Receive FIFO Fill Threshold Control Register + 0x614 + 32 + read-write + + 0x1 + + + FILL_THRESHOLD + FILL_THRESHOLD + Target Receive FIFO Fill Threshold +Configure the Target Receive FIFO fill threshold that should trigger assertion of the TGT_RX_FIFO_FILL_THRESHOLD interrupt. + + 0 + 7 + read-write + + 0 + 0 + + false + + + + TGT_DBG + TGT_DBG + Target Debug Register + 0x618 + 32 + read-only + + 0x1 + + + FORCE_PEC_ERROR + FORCE_PEC_ERROR + Target Debug Force PEC Error +Corrupts the PEC byte generation/checking. When set, writes with PEC enabled will always report an error and the PEC byte transmitted during a read will be corrupted. +0x0 - PEC Error insertion disabled +0x1 - PEC Error insertion enabled + + 31 + 1 + read-write + + 0 + 0 + + false + + + DBG_STATE + DBG_STATE + Target Debug State +Reports the current Target FSM State to assist with debug. + + 0 + 7 + read-only + + 0 + 0 + + false + + + + TGT_CONTROL_0 + TGT_CONTROL_0 + Target Device 0 Control Register + 0x620 + 32 + read-write + + 0x0 + + + ENABLE + ENABLE + Target Device 0 Enable +Configure the enable for Target Device 0 +0x0 - Target Device 0 disabled +0x1 - Target Device 0 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + + 31 + 1 + read-write + + 0 + 0 + + false + + + ADDRESS + ADDRESS + Target Device 0 Address +Configure the address for Device 0 + + 1 + 7 + read-write + + 0 + 0 + + false + + + + TGT_CONTROL_1 + TGT_CONTROL_1 + Target Device 1 Control Register + 0x624 + 32 + read-write + + 0x0 + + + ENABLE + ENABLE + Target Device 1 Enable +Configure the enable for Target Device 1 +0x0 - Target Device 1 disabled +0x1 - Target Device 1 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + + 31 + 1 + read-write + + 0 + 0 + + false + + + ADDRESS + ADDRESS + Target Device 1 Address +Configure the address for Device 1 + + 1 + 7 + read-write + + 0 + 0 + + false + + + + + true + + + + + + TGT_CONTROL_2 + TGT_CONTROL_2 + Target Device 2 Control Register + 0x628 + 32 + read-write + + 0x0 + + + ENABLE + ENABLE + Target Device 2 Enable +Configure the enable for Target Device 2 +0x0 - Target Device 2 disabled +0x1 - Target Device 2 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + + 31 + 1 + read-write + + 0 + 0 + + false + + + ADDRESS + ADDRESS + Target Device 2 Address +Configure the address for Device 2 + + 1 + 7 + read-write + + 0 + 0 + + false + + + + + true + + + + + + TGT_CONTROL_3 + TGT_CONTROL_3 + Target Device 3 Control Register + 0x62C + 32 + read-write + + 0x0 + + + ENABLE + ENABLE + Target Device 3 Enable +Configure the enable for Target Device 3 +0x0 - Target Device 3 disabled +0x1 - Target Device 3 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + + 31 + 1 + read-write + + 0 + 0 + + false + + + ADDRESS + ADDRESS + Target Device 3 Address +Configure the address for Device 3 + + 1 + 7 + read-write + + 0 + 0 + + false + + + + + true + + + + + + TGT_CONTROL_4 + TGT_CONTROL_4 + Target Device 4 Control Register + 0x630 + 32 + read-write + + 0x0 + + + ENABLE + ENABLE + Target Device 4 Enable +Configure the enable for Target Device 4 +0x0 - Target Device 4 disabled +0x1 - Target Device 4 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + + 31 + 1 + read-write + + 0 + 0 + + false + + + ADDRESS + ADDRESS + Target Device 4 Address +Configure the address for Device 4 + + 1 + 7 + read-write + + 0 + 0 + + false + + + + + true + + + + + + TGT_CONTROL_5 + TGT_CONTROL_5 + Target Device 5 Control Register + 0x634 + 32 + read-write + + 0x0 + + + ENABLE + ENABLE + Target Device 5 Enable +Configure the enable for Target Device 5 +0x0 - Target Device 5 disabled +0x1 - Target Device 5 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + + 31 + 1 + read-write + + 0 + 0 + + false + + + ADDRESS + ADDRESS + Target Device 5 Address +Configure the address for Device 5 + + 1 + 7 + read-write + + 0 + 0 + + false + + + + + true + + + + + + TGT_CONTROL_6 + TGT_CONTROL_6 + Target Device 6 Control Register + 0x638 + 32 + read-write + + 0x0 + + + ENABLE + ENABLE + Target Device 6 Enable +Configure the enable for Target Device 6 +0x0 - Target Device 6 disabled +0x1 - Target Device 6 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + + 31 + 1 + read-write + + 0 + 0 + + false + + + ADDRESS + ADDRESS + Target Device 6 Address +Configure the address for Device 6 + + 1 + 7 + read-write + + 0 + 0 + + false + + + + + true + + + + + + TGT_CONTROL_7 + TGT_CONTROL_7 + Target Device 7 Control Register + 0x63C + 32 + read-write + + 0x0 + + + ENABLE + ENABLE + Target Device 7 Enable +Configure the enable for Target Device 7 +0x0 - Target Device 7 disabled +0x1 - Target Device 7 enabled, the IP will automatically ACK a transaction with an address matching ADDRESS + + 31 + 1 + read-write + + 0 + 0 + + false + + + ADDRESS + ADDRESS + Target Device 7 Address +Configure the address for Device 7 + + 1 + 7 + read-write + + 0 + 0 + + false + + + + + true + + + + + + PHY_CTLR_DATA_HOLD + PHY_CTLR_DATA_HOLD + Controller PHY Data Setup Control Register + 0x800 + 32 + read-write + + 0x0 + + + CTLR_DATA_HOLD + CTLR_DATA_HOLD + Controller PHY Data Hold +Configure the data hold time when operating as a Controller-transmitter. +This value must be configured to meet tHD:DAT:Min in accordance with the SMBus Specification. +This value is calculated as - +If PHY_FILTER_CONTROL__ENABLE = 0x1 +Hold Time = s_axi_aclk period x (CTLR_DATA_HOLD + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) +If PHY_FILTER_CONTROL__ENABLE = 0x0 +Hold Time = s_axi_aclk period x (CTLR_DATA_HOLD + 8) + + 0 + 15 + read-write + + 0 + 0 + + false + + + + PHY_CTLR_START_HOLD + PHY_CTLR_START_HOLD + Controller PHY Start Hold Control Register + 0x804 + 32 + read-write + + 0x0 + + + CTLR_START_HOLD + CTLR_START_HOLD + Controller PHY Start Hold +Configure the START condition hold time. +This value must be configured to meet tHD:STA:Min in accordance with the SMBus Specification. +This value is calculated as - +If PHY_FILTER_CONTROL__ENABLE = 0x1 +Hold Time = s_axi_aclk period x (CTLR_START_HOLD + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) +If PHY_FILTER_CONTROL__ENABLE = 0x0 +Hold Time = s_axi_aclk period x (CTLR_START_HOLD + 8) + + 0 + 15 + read-write + + 0 + 0 + + false + + + + PHY_CTLR_START_SETUP + PHY_CTLR_START_SETUP + Controller PHY Start Setup Control Register + 0x808 + 32 + read-write + + 0x0 + + + CTLR_START_SETUP + CTLR_START_SETUP + Controller PHY Start Setup +Configure the START condition setup time. +This value must be configured to meet tSU:STA:Min in accordance with the SMBus Specification. +This value is calculated as - +If PHY_FILTER_CONTROL__ENABLE = 0x1 +Setup Time = s_axi_aclk period x (CTLR_START_SETUP + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) +If PHY_FILTER_CONTROL__ENABLE = 0x0 +Setup Time = s_axi_aclk period x (CTLR_START_SETUP + 8) + + 0 + 15 + read-write + + 0 + 0 + + false + + + + PHY_CTLR_STOP_SETUP + PHY_CTLR_STOP_SETUP + Controller PHY Stop Setup Control Register + 0x80C + 32 + read-write + + 0x0 + + + CTLR_STOP_SETUP + CTLR_STOP_SETUP + Controller PHY Stop Setup +Configure the STOP condition setup time. +This value must be configured to meet tSU:STO:Min in accordance with the SMBus Specification. +This value is calculated as - +If PHY_FILTER_CONTROL__ENABLE = 0x1 +Setup Time = s_axi_aclk period x (CTLR_STOP_SETUP + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) +If PHY_FILTER_CONTROL__ENABLE = 0x0 +Setup Time = s_axi_aclk period x (CTLR_STOP_SETUP + 8) + + 0 + 15 + read-write + + 0 + 0 + + false + + + + PHY_CTLR_CLK_TLOW + PHY_CTLR_CLK_TLOW + Controller PHY Clock Low Control Register + 0x810 + 32 + read-write + + 0x0 + + + CTLR_CLK_TLOW + CTLR_CLK_TLOW + Controller PHY Clock Low +Configure the SMBCLK low time. +This value must be configured to meet tLOW:Min in accordance with the SMBus Specification. +This value is calculated as - +If PHY_FILTER_CONTROL__ENABLE = 0x1 +Low Time = s_axi_aclk period x (CTLR_CLK_TLOW + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) +If PHY_FILTER_CONTROL__ENABLE = 0x0 +Low Time = s_axi_aclk period x (CTLR_CLK_TLOW + 8) + + 0 + 15 + read-write + + 0 + 0 + + false + + + + PHY_CTLR_CLK_THIGH + PHY_CTLR_CLK_THIGH + Controller PHY Clock High Control Register + 0x814 + 32 + read-write + + 0x0 + + + CTLR_CLK_THIGH + CTLR_CLK_THIGH + Controller PHY Clock High +Configure the SMBCLK high time. +This value must be configured to meet tHIGH:Min in accordance with the SMBus Specification. +This value is calculated as - +If PHY_FILTER_CONTROL__ENABLE = 0x1 +Low Time = s_axi_aclk period x (CTLR_CLK_THIGH + 8 + (PHY_FILTER_CONTROL__DURATION + 1)) +If PHY_FILTER_CONTROL__ENABLE = 0x0 +Low Time = s_axi_aclk period x (CTLR_CLK_THIGH + 8) + + 0 + 15 + read-write + + 0 + 0 + + false + + + + PHY_CTLR_TEXT_PRESCALER + PHY_CTLR_TEXT_PRESCALER + Controller PHY TEXT Timeout Prescaler Control Register + 0x818 + 32 + read-write + + 0x0 + + + CTLR_TEXT_PRESCALER + CTLR_TEXT_PRESCALER + Controller PHY TEXT Timeout Prescaler Configuration +Configure the amount of time to measure before incrementing the PHY_CTLR_TEXT_TIMEOUT counter when external SMBCLK stretching is detected by the Controller function. +This value is calculated as Text_Prescaler_Time = s_axi_aclk period x (CTLR_TEXT_PRESCALER+ 1) +The Text_Prescaler_Time should be configured for 1us in order to stay within range of the PHY_CTLR_TEXT_TIMEOUT counter. + + 0 + 9 + read-write + + 0 + 0 + + false + + + + PHY_CTLR_TEXT_TIMEOUT + PHY_CTLR_TEXT_TIMEOUT + Controller PHY TEXT Timeout Control Register + 0x81C + 32 + read-write + + 0x0 + + + CTLR_TEXT_TIMEOUT + CTLR_TEXT_TIMEOUT + Controller PHY TEXT Timeout Configuration +Configure the threshold used to detect that an external Target device(s) has exceeded the cumulative clock stretching threshold and to trigger the CTLR_TEXT_TIMEOUT interrupt. +This value must be configured to meet tLOW:TEXT in accordance with the SMBus Specification. +This value is calculated as Text_Timeout_Time = CTLR_TEXT_TIMEOUT x Text_Prescaler_Time + + 0 + 15 + read-write + + 0 + 0 + + false + + + + PHY_CTLR_TEXT_MAX + PHY_CTLR_TEXT_MAX + Controller PHY TEXT Timeout Max Status Register + 0x820 + 32 + read-write + + 0x0 + + + CTLR_TEXT_MAX + CTLR_TEXT_MAX + Controller PHY TEXT Timeout Max +Indicates the maximum amount of cumulative time in Text_Prescaler_Time units that the Controller function has measured external SMBCLK stretching during any single transaction (between an initial START and a STOP). + + 0 + 15 + read-write + clear + + 0 + 0 + + false + + + + PHY_CTLR_CEXT_PRESCALER + PHY_CTLR_CEXT_PRESCALER + Controller PHY CEXT Timeout Prescaler Configuration Register + 0x824 + 32 + read-write + + 0x0 + + + CTLR_CEXT_PRESCALER + CTLR_CEXT_PRESCALER + Controller PHY CEXT Timeout Prescaler Configuration +Configure the amount of time to measure before incrementing the PHY_CTLR_CEXT_TIMEOUT counter when SMBCLK stretching is active within the Controller function. +This value is calculated as Cext_Prescaler_Time = s_axi_aclk period x (CTLR_CEXT_PRESCALER+ 1) +The Cext_Prescaler_Time should be configured for 1us in order to stay within range of the PHY_CTLR_CEXT_TIMEOUT counter. + + 0 + 9 + read-write + + 0 + 0 + + false + + + + PHY_CTLR_CEXT_TIMEOUT + PHY_CTLR_CEXT_TIMEOUT + Controller PHY CEXT Timeout Configuration Register + 0x828 + 32 + read-write + + 0x0 + + + CTLR_CEXT_TIMEOUT + CTLR_CEXT_TIMEOUT + Controller PHY CEXT Timeout Configuration +Configure the threshold used to detect that the Controller function has exceeded the cumulative clock stretching threshold and to trigger the CTLR_CEXT_TIMEOUT interrupt. +This value must be configured to meet tLOW:CEXT in accordance with the SMBus Specification. +This value is calculated as Cext_Timeout_Time = CTLR_CEXT_TIMEOUT x Cext_Prescaler_Time + + 0 + 14 + read-write + + 0 + 0 + + false + + + + PHY_CTLR_CEXT_MAX + PHY_CTLR_CEXT_MAX + Controller PHY CEXT Timeout Max Status Register + 0x82C + 32 + read-write + + 0x0 + + + CTLR_CEXT_MAX + CTLR_CEXT_MAX + Controller PHY CEXT Timeout Max +Indicates the maximum amount of cumulative time in Cext_Prescaler_Time units that the Controller function has performed SMBCLK stretching during any single byte transfer (START-ACK, ACK-ACK, ACK-STOP). + + 0 + 14 + read-write + clear + + 0 + 0 + + false + + + + PHY_CTLR_DBG_STATE + PHY_CTLR_DBG_STATE + Controller PHY Debug State Status Register + 0x830 + 32 + read-only + + 0x1 + + + DBG_STATE + DBG_STATE + Controller PHY Debug State +Reports the current Controller PHY FSM State to assist with debug. + + 0 + 8 + read-only + + 0 + 0 + + false + + + + CTLR_CONTROL + CTLR_CONTROL + Controller Enable Control Register + 0xA00 + 32 + write-only + + 0x0 + + + ENABLE + ENABLE + Controller Enable Control +Enable the Controller to begin executing the descriptors in the Descriptor FIFO. +0x0 - Controller not enabled +0x1 - Controller enabled to execute the descriptors + + 0 + 1 + write-only + + 0 + 0 + + false + + + + CTLR_STATUS + CTLR_STATUS + Controller Enable Status Register + 0xA04 + 32 + read-only + + 0x0 + + + ENABLE + ENABLE + Controller Enable Status +0x0 - Controller is disabled +0x1 - Controller is enabled + + 0 + 1 + read-only + + 0 + 0 + + false + + + + CTLR_DESC_FIFO + CTLR_DESC_FIFO + Controller Descriptor FIFO Control Register + 0xA08 + 32 + write-only + + 0x0 + + + RESET + RESET + Controller Descriptor FIFO Reset Control +When set the Controller Descriptor FIFO is reset to a known state. +Poll the RESET_BUSY field in the CTLR_DESC_STATUS register to determine when the reset is complete. +0x1 - Descriptor FIFO reset +0x0 - Descriptor FIFO not reset + + 31 + 1 + write-only + + 0 + 0 + + false + + + ID + ID + Controller Descriptor FIFO ID +Configure the next Controller Descriptor ID +Writing this register when the RESET field is 0x0 pushes a value into the Controller Descriptor FIFO + + 8 + 4 + write-only + + 0 + 0 + + false + + + PAYLOAD + PAYLOAD + Controller Descriptor FIFO Payload +Configure the next Controller Descriptor payload + + 0 + 8 + write-only + + 0 + 0 + + false + + + + CTLR_DESC_STATUS + CTLR_DESC_STATUS + Controller Descriptor FIFO Status Register + 0xA0C + 32 + read-only + + 0x0 + + + FILL_LEVEL + FILL_LEVEL + Controller Descriptor FIFO Fill Level +Indicates the current fill level of the Descriptor FIFO + + 8 + 7 + read-only + + 0 + 0 + + false + + + RESET_BUSY + RESET_BUSY + Controller Descriptor FIFO Reset Busy +Indicates if the Descriptor FIFO is currently undergoing a reset and is unavailable for either read or write. +0x0 - FIFO not in reset +0x1 - FIFO reset in progress + + 6 + 1 + read-only + + 0 + 0 + + false + + + FULL + FULL + Controller Descriptor FIFO Full +Indicates if the Descriptor FIFO is full +0x0 - FIFO not full +0x1 - FIFO full + + 5 + 1 + read-only + + 0 + 0 + + false + + + ALMOST_FULL + ALMOST_FULL + Controller Descriptor FIFO Almost Full +Indicates if the Descriptor FIFO is almost full +0x0 - FIFO has space for more than one descriptor +0x1 - FIFO only has space for one more descriptor + + 4 + 1 + read-only + + 0 + 0 + + false + + + ALMOST_EMPTY + ALMOST_EMPTY + Controller Descriptor FIFO Almost Empty +Indicates if the Descriptor FIFO is almost empty +0x0 - FIFO contains more than one descriptor +0x1 - FIFO contains one descriptor or less + + 1 + 1 + read-only + + 0 + 0 + + false + + + EMPTY + EMPTY + Controller Descriptor FIFO Empty +Indicates if the Descriptor FIFO is empty +0x0 - FIFO not empty +0x1 - FIFO empty + + 0 + 1 + read-only + + 0 + 0 + + false + + + + CTLR_RX_FIFO + CTLR_RX_FIFO + Controller Receive FIFO Control Register + 0xA10 + 32 + read-only + + 0x0 + + + RESET + RESET + Controller Receive FIFO Reset Control +When set the Controller Recieve FIFO is reset to a known state. +Poll the RESET_BUSY field in the CTLR_RX_FIFO_STATUS register to determine when the reset is complete. +0x0 - FIFO not reset +0x1 - FIFO reset + + 31 + 1 + write-only + + 0 + 0 + + false + + + PAYLOAD + PAYLOAD + Controller Receive FIFO Payload +Receive payload byte for the Controller function. +Reading this register pops a value from the Controller Receive FIFO. + + 0 + 8 + read-only + + 0 + 0 + + modify + false + + + + CTLR_RX_FIFO_STATUS + CTLR_RX_FIFO_STATUS + Controller Receive FIFO Status Register + 0xA14 + 32 + read-only + + 0x0 + + + MAX_FILL_LEVEL + MAX_FILL_LEVEL + Controller Receive FIFO Max Fill Level Status +Indicates the maximum recorded fill level of the Controller Receive FIFO. + + 16 + 7 + read-write + oneToClear + + 0 + 0 + + false + + + FILL_LEVEL + FILL_LEVEL + Controller Receive FIFO Fill Level +Indicates the current fill level of the Receive FIFO. + + 8 + 7 + read-only + + 0 + 0 + + false + + + RESET_BUSY + RESET_BUSY + Controller Receive FIFO Reset Empty +Indicates if the Receive FIFO is currently undergoing a reset and is unavailable for either read or write. +0x0 - FIFO not in reset +0x1 - FIFO reset in progress + + 6 + 1 + read-only + + 0 + 0 + + false + + + FULL + FULL + Controller Receive FIFO Full +Indicates if the Receive FIFO is full +0x0 - FIFO not full +0x1 - FIFO full + + 5 + 1 + read-only + + 0 + 0 + + false + + + ALMOST_FULL + ALMOST_FULL + Controller Receive FIFO Almost Full +Indicates if the Controller Receive FIFO is almost full +0x0 - FIFO has space for two or more bytes +0x1 - FIFO has space for only one more byte + + 4 + 1 + read-only + + 0 + 0 + + false + + + ALMOST_EMPTY + ALMOST_EMPTY + Controller Receive FIFO Almost Empty +Indicates if the Controller Receive FIFO is almost empty +0x0 - FIFO contains more than one byte +0x1 - FIFO contains one byte or less + + 1 + 1 + read-only + + 0 + 0 + + false + + + EMPTY + EMPTY + Controller Receive FIFO Empty +Indicates if the Receive FIFO is empty +0x0 - FIFO not empty +0x1 - FIFO empty + + 0 + 1 + read-only + + 0 + 0 + + false + + + + CTLR_RX_FIFO_FILL_THRESHOLD + CTLR_RX_FIFO_FILL_THRESHOLD + Controller Receive FIFO Fill Threshold Control Register + 0xA18 + 32 + read-write + + 0x1 + + + FILL_THRESHOLD + FILL_THRESHOLD + Controller Receive FIFO Fill Threshold +Configure the Controller Receive FIFO fill threshold that should assert the CTLR_RX_FIFO_FILL_THRESHOLD interrupt. + + 0 + 7 + read-write + + 0 + 0 + + false + + + + CTLR_DBG + CTLR_DBG + Controller Debug Register + 0xA1C + 32 + read-only + + 0x1 + + + FORCE_PEC_ERROR + FORCE_PEC_ERROR + Controller Debug Force PEC Error +Corrupts the PEC byte generation/checking. When set, reads with PEC enabled will always report an error and the PEC byte transmitted during a write will be corrupted. +0x0 - PEC Error insertion disabled +0x1 - PEC Error insertion enabled + + 31 + 1 + read-write + + 0 + 0 + + false + + + DBG_STATE + DBG_STATE + Controller Debug State +Reports the current Controller FSM State to assist with debug. + + 0 + 7 + read-only + + 0 + 0 + + false + + + + + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + viewChecksum + 2e56b7b3 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + cf724b7d + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + smbus_v1_1_0 + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + 7231790d + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + smbus_v1_1_0 + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + 7231790d + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + + + s_axi_aclk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_aresetn + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_awaddr + + in + + 11 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_awvalid + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_awready + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_wvalid + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_wready + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_bvalid + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_bready + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_araddr + + in + + 11 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_arvalid + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_arready + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_rvalid + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_rready + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + ip2intc_irpt + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + smbclk_i + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + smbclk_o + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + smbclk_t + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + smbdat_i + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + smbdat_o + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + smbdat_t + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + C_ADDR_WIDTH + 12 + + + C_SMBUS_DEV_CLASS + 0 + + + C_NUM_TARGET_DEVICES + 8 + + + C_FREQ_HZ_AXI_ACLK + 100000000 + + + C_MINOR_VERSION + 0 + + + C_MAJOR_VERSION + 1 + + + C_CORE_REVISION + 0 + + + C_PATCH_REVISION + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_3721d737 + 0 + 1 + 2 + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + smbus_v1_1_0 + + + + xilinx_xpgui_view_fileset + + xgui/smbus_v1_1.tcl + tclSource + XGUI_VERSION_2 + smbus_v1_1_0 + + + + xilinx_verilogbehavioralsimulation_view_fileset + + hdl/smbus_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + smbus_v1_1_0 + + + + xilinx_verilogsynthesis_view_fileset + + hdl/smbus_v1_1_vl_rfs.sv + systemVerilogSource + CHECKSUM_7231790d + smbus_v1_1_0 + + + + xilinx_versioninformation_view_fileset + + doc/smbus_v1_1_changelog.txt + text + smbus_v1_1_0 + + + + SMBus v3.2 Compliant Target/Controller IP + + + Component_Name + smbus_v1_1 + + + NUM_TARGET_DEVICES + Target Devices + 8 + + + SMBUS_DEV_CLASS + Default SMBus Device Class + 0 + + + FREQ_HZ_AXI_ACLK + S_AXI Clock Frequency (Hz) + 100000000 + + + + + + /Alveo + + SMBus + level_2 + (GENERIC_FAMILY = versal) + + XPM_CDC + XPM_MEMORY + XPM_FIFO + + http://www.xilinx.com + 0 + + smbus@2022.10 + + true + 2024-02-15T09:40:36Z + + + 2023.2 + + + + + + + + + diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/doc/smbus_v1_1_changelog.txt b/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/doc/smbus_v1_1_changelog.txt new file mode 100755 index 00000000..63b1669d --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/doc/smbus_v1_1_changelog.txt @@ -0,0 +1,75 @@ +2023.2: + * Version 1.1 + * Bug Fix: Changed the default timing parameters to give more setup/hold margin + * Bug Fix: Added register to enable Data Hold time control when operating as a Target-Transmitter + * Bug Fix: Default Data Hold time increased for better compatibility with SMBus 2.0 compatible devices + * Other: Production Release + +2023.1.2: + * Version 1.0 + * No changes + +2023.1.1: + * Version 1.0 + * No changes + +2023.1: + * Version 1.0 + * No changes + +2022.2.2: + * Version 1.0 + * No changes + +2022.2.1: + * Version 1.0 + * No changes + +2022.2: + * Version 1.0 + * Beta Release + +(c) Copyright 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved. + +This file contains confidential and proprietary information +of AMD and is protected under U.S. and international copyright +and other intellectual property laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +AMD, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) AMD shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or AMD had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +AMD products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of AMD products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/hdl/smbus_v1_1_vl_rfs.sv b/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/hdl/smbus_v1_1_vl_rfs.sv new file mode 100755 index 00000000..3df9138d --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/hdl/smbus_v1_1_vl_rfs.sv @@ -0,0 +1,4460 @@ +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "XILINX" +`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.2" +`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +DhrkRrtbNvmV3Sq7ONAjvwIJ0Bp3SdAwOwk88/7eIZNvmVs2lCwB6pGOVTM4AK1YSgoIWagPIiIy +FDGzu7Zih1U5MOaEs/YaOilwJr+BFcJSHsO7cNSiPweaTk6nRymi759WrTxrbCw7EgG2OuEbWR90 +5jd6DxvGXsQ5dGXRWoc= + +`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +UIkQWoT5QTM7GZfgza4NzCEQOqUWWQFVHqsTTHtoR0ScfPsDGI4ODucQO2r3L++2qe154u1alAkC +tJky6gOsPFSLGb9s7419M2ODxa/jrPjf6ZwqTVilUEuZcHJZPpfSKSSUAvZRrjD0vuQalU1JMrb3 +g1PbpoJtq4vJKdY+djdxFYEJ7r5PJA7RYQ73KqTWtJLoqRKsyHbEm72CNH7iaBHzMseaKf0S8/ld +drppBJ8ZkefMxWGkpZLx8OIy16gtL7B4MDbbEod0wiWWCOuRONBNZceJTaDfeXeW00lUUvcSmlCV +eFykXSMIT6UyeJ6Gh0oBnGYnsk4auufGGOYd4w== + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +Sm5Sygecy5ebmidVFuUZsRb+Vj+f4jH8B1BoSh4YKi66Xl4h2sW7/PV2q8VFj5PwzTxtmxxQSWv7 +5Xj6Pn/YrPblPi14AjLhZXxgqZCjqHqKo7oqx8EhMtCy8EkNumfXX3HNhBNExrtBUF2P1FUy+YVO +G2sclhmqp+iCTPRD9IE= + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +N31vVNbqvy0vcFaJdr7MSqrxqvMut88a4VGWgZOyZO6jnLXC+QX+3laQFMGc7DV3IqsQGAQVODuZ +pBMIg687271ZEnCmt4cTUnUI8/TaJgDc3rOhx645mxGLZijGM273STM3Ni6ItdMRxy/yO8U45Id+ +uxtGw0Sh2Wwa6OuHPxW1ZwP3n0Bf8tMlWztfAq4TTdbzCHtlfyhic86e2c6YzoHeXkHeCZEntEEs +tfySv93/EDB8VNXQl/NE7WLl4yd1G1VR3ESfDxyA/uQAr7+gGmxHP4wZLoA6EctQ/ZzRHHbb6+fq +9TeogJJvc5FwquCuS1g+Qrjc9ILd9Axh1f2Prw== + +`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +3pAiubl/Tcm/2hWHLROYPfNpEi9t75l8bsYlBYOOF/KxKIqLqLCdo8qcy2T/ANg/d/2JQFxdzo93 +BkFxhLkt/6tuXmKSDx8f3zDC7XswpILc6L/oReEFTDWpetS5fLkjRixw92mV9jzFfTsOEBcbRmzh +gwD8KbZ3FWqKzd2mP2fw4zVsQ2F7oCDM6YH7ulYBLD8t9kN1Y/8VqnGBaOJhFn/QVje8x/O/hdsN +thXzBrDO/9a6ZIuqzSkXtf8pv93B/oV0aCAxHfbU/byOO14v1ZJnDD8oiQtDxLhIiZ3uytVEzxWm +LRLO/fDEnF+73UNQdonSoitS3nhSRcZ/Dzdk8Q== + +`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +mclPRAadfLDkt0NEyPOu3rlSBS8eXVH9nUjIsePhmKA4AcZq5tx7bcrgPajxzASoZn36PwbI/JTM +LqB/oFXMdS61Z19m3h2T115ukLMl4IVkzrz733xx+J0Cwo5dbhlvZld59QDh6kygl3xjG1dvvHOh +3JJZfvdA6fMZ49+cN3bH5U4RfpLgm5E8JN72KwUM/XrGvZxjRdab1wUoFbzuDBAOuukZQ2edZobz +Yf/E9xCPb2wTJEG/TpzusQCzLosPdc2fqQAeErHuxgLDxpvRXR+wstVfitjwNrdhMsJ5DsqzXQZp +ZyE/RyX8eoho4emXnE1lLjIdzBWyL8GQPJLRAw== + +`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2022_10", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +GTO3muIN8PtRp1FNHgWzkjDZGdLEcqDF2P99ndAlRgi1c4sb3wQhlWsY/3uUgbjjgqNYimF3zTqy +0k4WjsMLXo0xFM2CjDRXE8PQdunRvo8DqMNg7rHNXVAmSBVaJ/5mciZJY93+k/VGnh83ybjbq5FZ +feUMtVIy4R46Pe4egFoODKWAsl1e1nrIs9PGMMHIJckvG2Aaeq8+T6LhOkfnd4RRx1GNHHl4qyqz +gnKbg5ztsz6Tx5nURSvVmEpMA972joefC42zjsmcxIxFOsE41cTpPbfFqmrFhOaS+vk8hlVFxE9Q +82j80/Ac+qsMFrIqw/NLCtLBLhU+g9/EJKm1iw== + +`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384) +`pragma protect key_block +QlQkHzgbZHeoaMZeeXii/8mRjiQaxADin8tbLm8YIcgcB3BVapoKcK3DwPVvr5zAY6iAvL+coCit +NjNdjZG0HVRdO2pOq0FLilFJbZlvzLcA3dgE8KvEf3ZxACrFv1OGNPvK2w4zbElO8zuQ/YtTRpdI +7rKh2RWx1z5wEn/fBwkdekztRM8oJwoTDQEKZ3mke3mWI28LTaShcJRbEysFQPDJk7LhD147MOEc +kpxx9SDJSUDpBFRyH/49Pxv/Ai1O6+tWJ5VGM4mPtHgZ0xuHMfutaLTEKo+YSm9eA3G7ErSWDthU +556pPAhh+i3zaBJZoi3yEXZKrTInyU+BxgtT8hRtY4kqyeHMKISCAxY5vp5F6LvbE/TlQiYSNCCN +kBDOEjTglOVIFCoGJh6ZycXfWBzH3sxUmFP3k4nLY7DiYI1g6Cndq0VpEoYQoNTA+846Ah6t7JiO +1z+34IkB+0zlGwiMh99jthmZZFytRdCSx81LQuUKKNHtmszp7bo002BA + +`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +Ko7ipV/JlSLJk6Gk3TSfkFUjzfU1PNztUC6RF0IF6pKIFGTfLkGoSmkSeQqKKm84N1xDF5CUNGnz +cbAeSnm56l/QgiP9sqRLe1ooS31B3FbN0P8XLcZ+/Pi2roxOkUQ43VYeViGdQcftvyq0Yp4tJBDA +ydJLZkcJboGwf+1rvvnNfM8ZKieUzuIEZChBI85yW1Oqx1ZYLfjLFu4+kZMczFzEEpD6/EXwaIDB +VZr2PrGf/klH5yS7wUXEMcVN+/a+7DfrqLMjOI/AHtGh4e3Vyfd+45UWylrw9hebgqVjOo24OjBL +9N+PI+qxyqT41JW1MRH+T3dFtgadBC0sLTaxnQ== + +`pragma protect data_method = "AES128-CBC" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 249216) +`pragma protect data_block +Y6x4WW80qjxEW/XhEdKUBVh69cCwdMPJ9aUS/sfG/gaoJtS+b0RFj+zwZYre4SXjpqMAgzCWIRzj +BMpG5CmO/OEERaSHQQrIsBj0ST7zLx5OQrn3FbFGQYkUta1sfirI2RvknUzzWkac+3eryzK2/8UI +QkQIZtgJhZDehKhuU9Xbq2iOiALxCJU+vs67QmX5LRgt2IxujW5WNL/1sPmaPL+o7tMu47DkR1aA +vWsf7wBuNYHm9tEe0uWUWIy6E8vvJie808jMnWN6+JaAgOJD1pw9MvWq+SjMj781BSQjjRAZn72p +hNQNbyjw2vIO6+XtJw/CH/RNf+PCJcMbNjwEQvYaCKQyPqCa13ZMY4i7UszHTJ6DRV/4kc0qiddz +ZsK5XEYCUD5gKZBHUrusqXP5Dap0G5TsBE3eGPXpsK3qOxHb1dQeCwYR46QsgDP3SvBU8G7+ZMhE +EkQemQDlM0tWdwhvGsWTjTr+WYOVvNMzqNNq6JmEUjQT5xliy8I1UZ2nJZGtTTzXGKCQBDLlbHZL +7RwKQWu+1g1Es0XLbpEZ7U/ymu7Ouds2ATFQGabIUGjGuWmh3H8c63rmBu1l53blG7qPepzKPXyZ +E5lUCH5CNrDjJqqOxr+NyEH6TUpKD/rOsMrRQIUbC8Ah7EOUnKeOYyTln2gluQXk4V8vfo/62W+p +TwVm98o+QzwAKl92ckCAsr1S4stxGluwArwFSwYlet4GMihuKFUhOinBADso+oPbXQ7TMBeSOSY2 +BwSJzTWRS2JFTbt4ZxX+e2WXLzZCufuC9NKP/P+w9j0HO/c4xWGuArdHL+3JnskaGSMJpS2RhvXk +ChL1bP3//XDFuJubP7nkWI0RPScwR31bo7GJmNA3IM/oArhIa6QEHwlMFyRaRqcqWmHZXhqDbkOU +ZToLrRUbz2t4Up7QH9qiZ4kwdjGp5THkWoLhZQe6helLGvmragLSj+atVv8kXBASjyXjJzR/D36f +ycLU4gTEoMx4X2E8pCcKj2Zi6csJZLiQlbDijRg6ytlvm4Ty4XxsmWMH4PRr9ui/ANDBE+PS/cv1 +WOoXdNrfpkJzylc5N1jMz30NmMzFFeDXploLP7rsF/1Q8K85FUPIDGrZ53tBaKUg5vAb8VHwYGqR +VQMrRm36yiyiORG/AXO4DssHokjaPBGTD/FbsRTo5eC+US3QGe5xkLJy4828xbzHWfp67Nt/0riL +y9akxF/BkevymBBazo0hVGUS9Dta2wP7dWHQwaJy8tesmLi2MDyje/UuqwEv0fcD6h5OvHoCxMYA +bfnXl9lQvPMT/Vt7KEOgSlbh9/5cRdQkuT4GFhW09qRkRmtY25S0lAyeOCekpnPbsRhqceeUu4M7 +dZxavaxNhL+2ywKPww0WQYK200N7+voYW6fmYqKJAWlEjvifng/bd+qNsu+AAnIZSqgDPYUa4Z+3 +eY1yiuCM4UfpZmCtSgRDPjhUgONcCpBFf5fr247F9lW435aTauk29S6ljguIg7+7Ce0W3eugqVuu +6QadAEMEYosBzxKpFguu9S6/Cay7bFcPw+aPioTnYSP93dbueqYWvmnbOCi+glCNOE+irWj3UEOy +uE81W3UbDMxeIx/+3iRufYZo1bm8j8JDO21QORNvoghVLawAviweiqOrjWm6KO+6wwNhqLQyTXXW +Elxi5gK+GhklRSkHGF9ryGuszZOspNm3HaQ8WSVgDbwyfB5mN9ebiD32tRSE9BZSbBwaa0pTf/8r +g5Ua+CjbMfrJ3Ygv+Q/Un5IB9ruoQcyRaTVZX4F34gVHOb/I4RN5AE/j6rMZG9tUybT6TXZK2tgD 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+ZVClKQ5La5e9VRLaDtE0hd2BIsoisQs+UBA+szkp5DSxM1FMPrTu+2QRq0IXwqk4OWbm8IRLAaAf +nsBuSzcQNp1z9FWNXIL7XuV0UbJTTgaATTd2kWcxkFBTsJtXKBpfC90F1PIymi9rXH47vkAoG4Q3 +3IkoTDu972J0VDAI8LTBj1IIfKvPhn2VXOjbPD87emES9iHMvxgO776KDeD7Uxc1iBfkwvVa/9zO +uGlw3fbNfyibxsakbnjj5jzdQAciCTMCLOShh5qq8OR5Kf7ZwlzcE1ORvaN9DFoVtvJmQKs5KZeX +nd6YYwl07HVwY07f +`pragma protect end_protected diff --git a/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/xgui/smbus_v1_1.tcl b/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/xgui/smbus_v1_1.tcl new file mode 100755 index 00000000..58c35066 --- /dev/null +++ b/linker/resources/base/iprepo/smbus_v1_1-20240328/ip/smbus_v1_1/xgui/smbus_v1_1.tcl @@ -0,0 +1,146 @@ +# (c) Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of AMD and is protected under U.S. and international copyright +# and other intellectual property laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# AMD, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) AMD shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or AMD had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# AMD products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of AMD products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +############################################################ + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + + #---> Adding Page ---------------------------------------------------------------------------------------------------------------------# + + set General_Config [ipgui::add_page $IPINST -name "General Configuration"] + + #---> Adding Group ----------------------------------------------------------------------------------------------------------------# + + set Class_Group [ipgui::add_group $IPINST -parent $General_Config -name "SMBus Device Class Configuration" ] + + #---> Adding Params -----------------------------------------------------------------------------------------------------------# + + set SMBUS_DEV_CLASS [ipgui::add_param $IPINST -name SMBUS_DEV_CLASS -widget comboBox -parent $Class_Group] + set_property tooltip "SMBUS_DEV_CLASS: Specify the default SMBus device class that the IP will operate at." $SMBUS_DEV_CLASS + + #---> End Params --------------------------------------------------------------------------------------------------------------# + + #---> End Group -------------------------------------------------------------------------------------------------------------------# + + #---> Adding Group ----------------------------------------------------------------------------------------------------------------# + + set Target_Group [ipgui::add_group $IPINST -parent $General_Config -name "SMBus Target Configuration" ] + + #---> Adding Params -----------------------------------------------------------------------------------------------------------# + + set NUM_TARGET_DEVICES [ipgui::add_param $IPINST -name NUM_TARGET_DEVICES -parent $Target_Group] + set_property tooltip "NUM_TARGET_DEVICES: Specify the number of devices to be supported when operating as a Target." $NUM_TARGET_DEVICES + + #---> End Params --------------------------------------------------------------------------------------------------------------# + + #---> End Group -------------------------------------------------------------------------------------------------------------------# + + #---> Adding Group ----------------------------------------------------------------------------------------------------------------# + + set Clock_Group [ipgui::add_group $IPINST -parent $General_Config -name "S_AXI Clock Frequency Configuration" ] + + #---> Adding Params -----------------------------------------------------------------------------------------------------------# + + set FREQ_HZ_AXI_ACLK [ipgui::add_param $IPINST -name FREQ_HZ_AXI_ACLK -parent $Clock_Group] + set_property tooltip "FREQ_HZ_AXI_ACLK: Specify the frequency (in Hz) of the input s_axi_aclk clock." $FREQ_HZ_AXI_ACLK + + #---> End Params --------------------------------------------------------------------------------------------------------------# + + #---> End Group -------------------------------------------------------------------------------------------------------------------# + + #---> End Page ------------------------------------------------------------------------------------------------------------------------# +} + +#==========================================================================================================================================# +# Model Parameter Update Procedures +#==========================================================================================================================================# + +proc update_MODELPARAM_VALUE.C_MAJOR_VERSION { MODELPARAM_VALUE.C_MAJOR_VERSION PROJECT_PARAM.DEVICE IPINST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + + set version [get_property VERSION [current_ipcomp]] + regexp {^(\d+)\.(\d+)$} $version -> major minor + set_property value $major ${MODELPARAM_VALUE.C_MAJOR_VERSION} + +} + +proc update_MODELPARAM_VALUE.C_MINOR_VERSION { MODELPARAM_VALUE.C_MINOR_VERSION PROJECT_PARAM.DEVICE IPINST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + + set version [get_property VERSION [current_ipcomp]] + regexp {^(\d+)\.(\d+)$} $version -> major minor + set_property value $minor ${MODELPARAM_VALUE.C_MINOR_VERSION} + +} + +proc update_MODELPARAM_VALUE.C_CORE_REVISION { MODELPARAM_VALUE.C_CORE_REVISION PROJECT_PARAM.DEVICE IPINST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + + set revision [get_property CORE_REVISION [current_ipcomp]] + set_property value $revision ${MODELPARAM_VALUE.C_CORE_REVISION} + +} + +proc update_MODELPARAM_VALUE.C_FREQ_HZ_AXI_ACLK { MODELPARAM_VALUE.C_FREQ_HZ_AXI_ACLK PARAM_VALUE.FREQ_HZ_AXI_ACLK IPINST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + + set_property value [get_property value ${PARAM_VALUE.FREQ_HZ_AXI_ACLK}] ${MODELPARAM_VALUE.C_FREQ_HZ_AXI_ACLK} + +} + +proc update_MODELPARAM_VALUE.C_SMBUS_DEV_CLASS { MODELPARAM_VALUE.C_SMBUS_DEV_CLASS PARAM_VALUE.SMBUS_DEV_CLASS IPINST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + + set_property value [get_property value ${PARAM_VALUE.SMBUS_DEV_CLASS}] ${MODELPARAM_VALUE.C_SMBUS_DEV_CLASS} + +} + +proc update_MODELPARAM_VALUE.C_NUM_TARGET_DEVICES { MODELPARAM_VALUE.C_NUM_TARGET_DEVICES PARAM_VALUE.NUM_TARGET_DEVICES IPINST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + + set_property value [get_property value ${PARAM_VALUE.NUM_TARGET_DEVICES}] ${MODELPARAM_VALUE.C_NUM_TARGET_DEVICES} + +} diff --git a/linker/resources/base/iprepo/traffic_producer/Makefile b/linker/resources/base/iprepo/traffic_producer/Makefile new file mode 100644 index 00000000..3c943b5c --- /dev/null +++ b/linker/resources/base/iprepo/traffic_producer/Makefile @@ -0,0 +1,34 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +TARGET=ip +DEVICE=xcv80-lsva4737-2MHP-e-S + +TRAFFIC_PRODUCER_BUILD_DIR=build_traffic_producer.$(DEVICE) + +all: $(TRAFFIC_PRODUCER_BUILD_DIR) + +$(TRAFFIC_PRODUCER_BUILD_DIR): + if [ ! -d "$(TRAFFIC_PRODUCER_BUILD_DIR)" ]; then \ + vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) traffic_producer; \ + fi + +clean: + rm -rf $(TRAFFIC_PRODUCER_BUILD_DIR) \ No newline at end of file diff --git a/linker/resources/base/iprepo/traffic_producer/build.tcl b/linker/resources/base/iprepo/traffic_producer/build.tcl new file mode 100644 index 00000000..5a2afc91 --- /dev/null +++ b/linker/resources/base/iprepo/traffic_producer/build.tcl @@ -0,0 +1,79 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set command [lindex $argv 0] +set device [lindex $argv 1] +set ipname [lindex $argv 2] + +set do_sim 0 +set do_syn 0 +set do_export 0 +set do_cosim 0 + +switch $command { + "sim" { + set do_sim 1 + } + "syn" { + set do_syn 1 + } + "ip" { + set do_syn 1 + set do_export 1 + } + "cosim" { + set do_syn 1 + set do_cosim 1 + } + "all" { + set do_sim 1 + set do_syn 1 + set do_export 1 + set do_cosim 1 + } + default { + puts "Unrecognized command" + exit + } +} + + +open_project build_${ipname}.${device} + +file copy -force $ipname.cpp build_${ipname}.${device}/$ipname.cpp +add_files $ipname.cpp -cflags "-std=c++14" + +set_top $ipname + +open_solution sol1 + +if {$do_syn} { + set_part $device + create_clock -period 4 -name default + config_interface -m_axi_addr64=true + csynth_design +} + +if {$do_export} { + config_export -format ip_catalog + export_design +} + +exit \ No newline at end of file diff --git a/linker/resources/base/iprepo/traffic_producer/traffic_producer.cpp b/linker/resources/base/iprepo/traffic_producer/traffic_producer.cpp new file mode 100644 index 00000000..2f81dd8d --- /dev/null +++ b/linker/resources/base/iprepo/traffic_producer/traffic_producer.cpp @@ -0,0 +1,35 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +#include "ap_axi_sdata.h" +#include "ap_int.h" +#include "hls_stream.h" + +#define DWIDTH 512 +#define TDWIDTH 3 + +typedef ap_axiu pkt; + +void traffic_producer(hls::stream &axis_out, + ap_uint<32> flits, + ap_uint dest){ + +#pragma HLS INTERFACE mode=axis port=axis_out depth=16 +#pragma HLS INTERFACE mode=s_axilite port=dest bundle=control +#pragma HLS INTERFACE mode=s_axilite port=flits bundle=control +#pragma HLS INTERFACE mode=s_axilite port=return bundle=control + + pkt axi_word; +generator: + for(unsigned int i=0; i< flits; i++){ + #pragma HLS PIPELINE II=1 + for(unsigned int j=0; j_impl_1' + create_run $child_run -parent_run impl_1 \ + -flow {Vivado Advanced Implementation 2024} \ + -pr_config $cfg2_name + + # Launch and wait + launch_runs impl_1 $child_run -to_step write_bitstream -jobs 8 + wait_on_run $child_run + puts "INFO: Implementation complete for run '$child_run'." +} + +# Example: +# build_project my_project + + diff --git a/linker/resources/base/scripts/create_project.tcl b/linker/resources/base/scripts/create_project.tcl new file mode 100644 index 00000000..6210f96e --- /dev/null +++ b/linker/resources/base/scripts/create_project.tcl @@ -0,0 +1,54 @@ +set src_dir [file dirname [file normalize [info script]]] +set cwd [pwd] + +if {[llength $argv] < 1} { + puts "INFO: No project_name provided via -tclargs; defaulting to 'user'." + set project_name "user" +} else { + set project_name [lindex $argv 0] +} + +# Design/BD names +set design_name "slash" +set bd_slash_name "slash_${project_name}" +set bd_service_layer_name "service_layer_${project_name}" + +# Generated BD Tcl paths from the linker +# ../results//bd/slash_.tcl +set slash_gen_tcl [file normalize [file join $src_dir ".." ".." ".." "results" $project_name "bd" "slash_${project_name}.tcl"]] +set service_gen_tcl [file normalize [file join $src_dir ".." ".." ".." "results" $project_name "bd" "service_layer_${project_name}.tcl"]] + +puts "PROJECT: $project_name" +puts "SLASH BD TCL: $slash_gen_tcl" +puts "SERVICE BD TCL: $service_gen_tcl" + +set list_projects [get_projects -quiet] +if { $list_projects eq ""} { + create_project $design_name "$src_dir/../build" -part xcv80-lsva4737-2MHP-e-S -force + set_property ip_repo_paths "$src_dir/../iprepo" [current_project] + update_ip_catalog + + # Base shells / containers + source [file normalize [file join $src_dir "slash_base.tcl"]] + source [file normalize [file join $src_dir "service_layer.tcl"]] + source [file normalize [file join $src_dir "top.tcl"]] + source [file normalize [file join $src_dir "enable_dfx_bdc.tcl"]] + + # --- source the **generated** BDs from the linker --- + if {![file exists $slash_gen_tcl]} { + error "Missing generated SLASH BD Tcl: $slash_gen_tcl" + } + if {![file exists $service_gen_tcl]} { + error "Missing generated SERVICE-LAYER BD Tcl: $service_gen_tcl" + } + source $slash_gen_tcl + source $service_gen_tcl + + # Wrapper / XDC / build + source [file normalize [file join $src_dir "make_wrapper.tcl"]] + source [file normalize [file join $src_dir "add_constraints.tcl"]] + source [file normalize [file join $src_dir "build_project.tcl"]] + build_project $project_name +} else { + puts "INFO: Project already open; not recreating." +} diff --git a/linker/resources/base/scripts/enable_dfx_bdc.tcl b/linker/resources/base/scripts/enable_dfx_bdc.tcl new file mode 100644 index 00000000..51003dfd --- /dev/null +++ b/linker/resources/base/scripts/enable_dfx_bdc.tcl @@ -0,0 +1,11 @@ + +current_bd_design [get_bd_designs top] + +set_property -dict [list CONFIG.ENABLE_DFX {true}] [get_bd_cells slash] +set_property -dict [list CONFIG.ENABLE_DFX {true}] [get_bd_cells service_layer] + +set_property -dict [list CONFIG.LOCK_PROPAGATE {true}] [get_bd_cells slash] +set_property -dict [list CONFIG.LOCK_PROPAGATE {true}] [get_bd_cells service_layer] + +validate_bd_design +save_bd_design diff --git a/linker/resources/base/scripts/make_wrapper.tcl b/linker/resources/base/scripts/make_wrapper.tcl new file mode 100644 index 00000000..d9864b2e --- /dev/null +++ b/linker/resources/base/scripts/make_wrapper.tcl @@ -0,0 +1,5 @@ + +add_files -norecurse [make_wrapper -files [get_files "top.bd"] -top] +update_compile_order -fileset sources_1 +update_compile_order -fileset sim_1 +set_property top top_wrapper [current_fileset] diff --git a/linker/resources/base/scripts/service_layer.tcl b/linker/resources/base/scripts/service_layer.tcl new file mode 100644 index 00000000..8702d948 --- /dev/null +++ b/linker/resources/base/scripts/service_layer.tcl @@ -0,0 +1,1731 @@ + +################################################################ +# This is a generated script based on design: service_layer +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2024.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."} + + } else { + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + } + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source service_layer_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# dcmac_syncer_reset, dcmac_syncer_reset, clock_to_clock_bus, clock_to_serdes, clock_to_clock_bus, clock_to_serdes, clock_to_serdes, dcmac200g_ctl_port, clock_to_clock_bus, clock_to_serdes, axis_seg_to_unseg_converter, axis_unseg_to_seg_converter, dcmac_syncer_reset, dcmac_syncer_reset, clock_to_clock_bus, clock_to_serdes, clock_to_clock_bus, clock_to_serdes, clock_to_serdes, dcmac200g_ctl_port, clock_to_clock_bus, clock_to_serdes, axis_seg_to_unseg_converter, axis_unseg_to_seg_converter + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xcv80-lsva4737-2MHP-e-S +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name service_layer + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_register_slice:2.1\ +xilinx.com:ip:axis_noc:1.0\ +xilinx.com:hls:hbm_bandwidth:1.0\ +xilinx.com:ip:axi_noc:1.1\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:hls:traffic_producer:1.0\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:axis_dwidth_converter:1.1\ +xilinx.com:ip:axis_data_fifo:2.0\ +xilinx.com:ip:clk_wizard:1.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:util_vector_logic:2.0\ +xilinx.com:ip:xlslice:1.0\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:inline_hdl:ilreduced_logic:1.0\ +xilinx.com:ip:dcmac:2.5\ +xilinx.com:ip:axi_gpio:2.0\ +xilinx.com:ip:util_ds_buf:2.2\ +xilinx.com:ip:gt_quad_base:1.1\ +xilinx.com:ip:bufg_gt:1.0\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 0 +if { $bCheckModules == 1 } { + set list_check_mods "\ +dcmac_syncer_reset\ +dcmac_syncer_reset\ +clock_to_clock_bus\ +clock_to_serdes\ +clock_to_clock_bus\ +clock_to_serdes\ +clock_to_serdes\ +dcmac200g_ctl_port\ +clock_to_clock_bus\ +clock_to_serdes\ +axis_seg_to_unseg_converter\ +axis_unseg_to_seg_converter\ +dcmac_syncer_reset\ +dcmac_syncer_reset\ +clock_to_clock_bus\ +clock_to_serdes\ +clock_to_clock_bus\ +clock_to_serdes\ +clock_to_serdes\ +dcmac200g_ctl_port\ +clock_to_clock_bus\ +clock_to_serdes\ +axis_seg_to_unseg_converter\ +axis_unseg_to_seg_converter\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: dcmac_gt1_wrapper +############################# DCMAC instance wrapper ############################# +proc add_dcmac_inst {} { + + set DCMAC0_ENABLED 1 + set DCMAC1_ENABLED 1 + + ## Each DCMAC can support 2 QSFP56 interfaces + ## select how many QSFP56 you want for each DCMAC, provided they are enabled + + ## Setup number of QSFP56 interfaces for DCMAC0 + set DUAL_QSFP_DCMAC0 0 + + ## Setup number of QSFP56 interfaces for DCMAC1 + set DUAL_QSFP_DCMAC1 0 + + # Create network hierarchy + if { ${DCMAC0_ENABLED} == "1" } { + create_qsfp_hierarchy 0 ${DUAL_QSFP_DCMAC0} + } + if { ${DCMAC1_ENABLED} == "1" } { + create_qsfp_hierarchy 1 ${DUAL_QSFP_DCMAC1} + } +} +set current_file [file normalize [info script]] +set current_dir [file normalize ${current_file}] +set dcmac_base [file normalize [file join $current_dir .. .. .. dcmac]] + +# Absolute paths (normalized) +set ::slash_dcmac_tcl [file join $dcmac_base tcl dcmac.tcl] +set ::slash_dcmac_hdl [file join $dcmac_base hdl] + +# Source the DCMAC Tcl helpers +source $::slash_dcmac_tcl + +# Import DCMAC source files +import_files -fileset sources_1 -norecurse [file join $::slash_dcmac_hdl axis_seg_to_unseg_converter.v] +import_files -fileset sources_1 -norecurse [file join $::slash_dcmac_hdl clock_to_clock_bus.v] +import_files -fileset sources_1 -norecurse [file join $::slash_dcmac_hdl dcmac200g_ctl_port.v] +import_files -fileset sources_1 -norecurse [file join $::slash_dcmac_hdl serdes_clock.v] +import_files -fileset sources_1 -norecurse [file join $::slash_dcmac_hdl syncer_reset.v] + +# --- DCMAC creation variables --- +set DCMAC0_ENABLED 1 +set DCMAC1_ENABLED 1 +set DUAL_QSFP_DCMAC0 0 +set DUAL_QSFP_DCMAC1 0 + +# Calls proc add_dcmac_inst which expects the above variables +# add_dcmac_inst + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set M_DCMAC_INIS0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS0 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS0 + + set M_DCMAC_INIS1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS1 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS1 + + set M_DCMAC_INIS2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS2 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS2 + + set M_DCMAC_INIS3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS3 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS3 + + set M_DCMAC_INIS4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS4 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS4 + + set M_DCMAC_INIS5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS5 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS5 + + set M_DCMAC_INIS6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS6 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS6 + + set M_DCMAC_INIS7 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS7 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS7 + + set M_VIRT_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M_VIRT_0 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_VIRT_0 + + set M_VIRT_1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M_VIRT_1 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_VIRT_1 + + set M_VIRT_2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M_VIRT_2 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_VIRT_2 + + set M_VIRT_3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M_VIRT_3 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_VIRT_3 + + set S_DCMAC_INIS0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS0 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS0 + + set S_DCMAC_INIS1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS1 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS1 + + set S_DCMAC_INIS2 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS2 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS2 + + set S_DCMAC_INIS3 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS3 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS3 + + set S_DCMAC_INIS4 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS4 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS4 + + set S_DCMAC_INIS5 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS5 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS5 + + set S_DCMAC_INIS6 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS6 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS6 + + set S_DCMAC_INIS7 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS7 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS7 + + set SL2NOC_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_0 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_0 + + set SL2NOC_1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_1 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_1 + + set SL2NOC_2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_2 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_2 + + set SL2NOC_3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_3 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_3 + + set SL2NOC_4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_4 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_4 + + set SL2NOC_5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_5 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_5 + + set SL2NOC_6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_6 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_6 + + set SL2NOC_7 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_7 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_7 + + set S_VIRT_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_VIRT_0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S_VIRT_0 + + set S_VIRT_1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_VIRT_1 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S_VIRT_1 + + set S_VIRT_2 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_VIRT_2 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S_VIRT_2 + + set S_VIRT_3 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_VIRT_3 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S_VIRT_3 + + # set qsfp0_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp0_4x ] + + # set qsfp0_322mhz [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp0_322mhz ] + # set_property -dict [ list \ + # CONFIG.FREQ_HZ {322265625} \ + # ] $qsfp0_322mhz + + # set qsfp2_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp2_4x ] + + # set qsfp2_322mhz [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp2_322mhz ] + # set_property -dict [ list \ + # CONFIG.FREQ_HZ {322265625} \ + # ] $qsfp2_322mhz + + set qsfp1_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp1_4x ] + + set qsfp3_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp3_4x ] + + set S_QDMA_SLAVE_BRIDGE [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_QDMA_SLAVE_BRIDGE ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S_QDMA_SLAVE_BRIDGE + + set M_QDMA_SLAVE_BRIDGE [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_QDMA_SLAVE_BRIDGE ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4} \ + ] $M_QDMA_SLAVE_BRIDGE + + set S_AXILITE_INI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S_AXILITE_INI ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_AXILITE_INI + + + # Create ports + set aclk0 [ create_bd_port -dir I -type clk -freq_hz 300000000 aclk0 ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S_VIRT_3:S_VIRT_2:S_VIRT_1:S_VIRT_0:S_QDMA_SLAVE_BRIDGE:M_QDMA_SLAVE_BRIDGE:S_AXILITE_INI} \ + CONFIG.CLK_DOMAIN {top_clk_wizard_0_0_clk_out1} \ + ] $aclk0 + set aclk1 [ create_bd_port -dir I -type clk aclk1 ] + set_property -dict [ list \ + CONFIG.CLK_DOMAIN {bd_4885_pspmc_0_0_pl0_ref_clk} \ + ] $aclk1 + set ap_rst_n [ create_bd_port -dir I -type rst ap_rst_n ] + + # Create instance: axi_register_slice_0, and set properties + set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ] + + # Create instance: axi_register_slice_1, and set properties + set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ] + + # Create instance: axi_register_slice_2, and set properties + set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ] + + # Create instance: axi_register_slice_3, and set properties + set axi_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_3 ] + + # Create instance: dummy_noc_0, and set properties + set dummy_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_0 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_0/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_0/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_0/aclk0] + + # Create instance: dummy_noc_1, and set properties + set dummy_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_1 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_1/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_1/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_1/aclk0] + + # Create instance: dummy_noc_2, and set properties + set dummy_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_2 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_2/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_2/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_2/aclk0] + + # Create instance: dummy_noc_3, and set properties + set dummy_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_3 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_3/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_3/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_3/aclk0] + + # Create instance: dummy_noc_4, and set properties + set dummy_noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_4 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_4 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_4/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_4/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_4/aclk0] + + # Create instance: dummy_noc_5, and set properties + set dummy_noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_5 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_5 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_5/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_5/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_5/aclk0] + + # Create instance: dummy_noc_6, and set properties + set dummy_noc_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_6 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_6 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_6/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_6/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_6/aclk0] + + # Create instance: dummy_noc_7, and set properties + set dummy_noc_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_7 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_7 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_7/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_7/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_7/aclk0] + + # Create instance: dummy_noc_m_0, and set properties + set dummy_noc_m_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_0/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_0/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_0/aclk0] + + # Create instance: dummy_noc_m_1, and set properties + set dummy_noc_m_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_1/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_1/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_1/aclk0] + + # Create instance: dummy_noc_m_2, and set properties + set dummy_noc_m_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_2/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_2/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_2/aclk0] + + # Create instance: dummy_noc_m_3, and set properties + set dummy_noc_m_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_3/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_3/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_3/aclk0] + + # Create instance: dummy_noc_m_4, and set properties + set dummy_noc_m_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_4/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_4/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_4/aclk0] + + # Create instance: dummy_noc_m_5, and set properties + set dummy_noc_m_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_5/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_5/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_5/aclk0] + + # Create instance: dummy_noc_m_6, and set properties + set dummy_noc_m_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_6/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_6/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_6/aclk0] + + # Create instance: dummy_noc_m_7, and set properties + set dummy_noc_m_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_7/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_7/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_7/aclk0] + + # Create instance: eth_0, and set properties + set eth_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_0 ] + + # Create instance: eth_1, and set properties + set eth_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_1 ] + + # Create instance: eth_2, and set properties + set eth_2 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_2 ] + + # Create instance: eth_3, and set properties + set eth_3 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_3 ] + + # Create instance: eth_4, and set properties + set eth_4 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_4 ] + + # Create instance: eth_5, and set properties + set eth_5 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_5 ] + + # Create instance: eth_6, and set properties + set eth_6 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_6 ] + + # Create instance: eth_7, and set properties + set eth_7 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_7 ] + + # Create instance: sl2noc_0, and set properties + set sl2noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_0/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_0/aclk0] + + # Create instance: sl2noc_1, and set properties + set sl2noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_1/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_1/aclk0] + + # Create instance: sl2noc_2, and set properties + set sl2noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_2/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_2/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_2/aclk0] + + # Create instance: sl2noc_3, and set properties + set sl2noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_3/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_3/aclk0] + + # Create instance: sl2noc_4, and set properties + set sl2noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_4/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_4/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_4/aclk0] + + # Create instance: sl2noc_5, and set properties + set sl2noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_5/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_5/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_5/aclk0] + + # Create instance: sl2noc_6, and set properties + set sl2noc_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_6/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_6/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_6/aclk0] + + # Create instance: sl2noc_7, and set properties + set sl2noc_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_7/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_7/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_7/aclk0] + + # Create instance: sl2noc_virt_0, and set properties + set sl2noc_virt_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_virt_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_virt_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_virt_0/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_virt_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_virt_0/aclk0] + + # Create instance: sl2noc_virt_1, and set properties + set sl2noc_virt_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_virt_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_virt_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_virt_1/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_virt_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_virt_1/aclk0] + + # Create instance: sl2noc_virt_2, and set properties + set sl2noc_virt_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_virt_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_virt_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_virt_2/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_virt_2/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_virt_2/aclk0] + + # Create instance: sl2noc_virt_3, and set properties + set sl2noc_virt_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_virt_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_virt_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_virt_3/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_virt_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_virt_3/aclk0] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {16} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_0 + + + # Create instance: traffic_producer_0, and set properties + set traffic_producer_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_0 ] + + # Create instance: traffic_producer_1, and set properties + set traffic_producer_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_1 ] + + # Create instance: traffic_producer_2, and set properties + set traffic_producer_2 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_2 ] + + # Create instance: traffic_producer_3, and set properties + set traffic_producer_3 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_3 ] + + # Create instance: traffic_producer_4, and set properties + set traffic_producer_4 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_4 ] + + # Create instance: traffic_producer_5, and set properties + set traffic_producer_5 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_5 ] + + # Create instance: traffic_producer_6, and set properties + set traffic_producer_6 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_6 ] + + # Create instance: traffic_producer_7, and set properties + set traffic_producer_7 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_7 ] + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + + # # Create instance: qsfp_0_n_1 + # create_hier_cell_qsfp_0_n_1 [current_bd_instance .] qsfp_0_n_1 + + # # Create instance: qsfp_2_n_3 + # create_hier_cell_qsfp_2_n_3 [current_bd_instance .] qsfp_2_n_3 + #### DCMAC entry points #### + add_dcmac_inst + # Create instance: axi_register_slice_4, and set properties + set axi_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_4 ] + + # Create instance: smartconnect_1, and set properties + set smartconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_1 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {3} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_1 + + + # Create instance: axi_noc_0, and set properties + set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_0 + + + set_property -dict [ list \ + CONFIG.APERTURES {{0x203_0000_0000 128M}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_0/M00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_0/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_0/aclk0] + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins dummy_noc_m_0/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS0] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins dummy_noc_m_1/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins dummy_noc_m_2/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS2] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins dummy_noc_m_3/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS3] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins dummy_noc_m_4/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS4] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins dummy_noc_m_5/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS5] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins dummy_noc_m_6/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS6] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins dummy_noc_m_7/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS7] + connect_bd_intf_net -intf_net Conn9 [get_bd_intf_pins dummy_noc_0/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS0] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins dummy_noc_1/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS1] + connect_bd_intf_net -intf_net Conn11 [get_bd_intf_pins dummy_noc_2/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS2] + connect_bd_intf_net -intf_net Conn12 [get_bd_intf_pins dummy_noc_3/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS3] + connect_bd_intf_net -intf_net Conn13 [get_bd_intf_pins dummy_noc_4/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS4] + connect_bd_intf_net -intf_net Conn14 [get_bd_intf_pins dummy_noc_5/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS5] + connect_bd_intf_net -intf_net Conn15 [get_bd_intf_pins dummy_noc_6/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS6] + connect_bd_intf_net -intf_net Conn16 [get_bd_intf_pins dummy_noc_7/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS7] + connect_bd_intf_net -intf_net Conn17 [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_ports S_VIRT_0] + connect_bd_intf_net -intf_net Conn18 [get_bd_intf_pins axi_register_slice_1/S_AXI] [get_bd_intf_ports S_VIRT_1] + connect_bd_intf_net -intf_net Conn19 [get_bd_intf_pins axi_register_slice_2/S_AXI] [get_bd_intf_ports S_VIRT_2] + connect_bd_intf_net -intf_net Conn20 [get_bd_intf_pins axi_register_slice_3/S_AXI] [get_bd_intf_ports S_VIRT_3] + connect_bd_intf_net -intf_net S_AXILITE_INI_1 [get_bd_intf_ports S_AXILITE_INI] [get_bd_intf_pins axi_noc_0/S00_INI] + connect_bd_intf_net -intf_net S_AXIS_0_1 [get_bd_intf_pins qsfp_0_n_1/S_AXIS_0] [get_bd_intf_pins dummy_noc_0/M00_AXIS] + connect_bd_intf_net -intf_net S_AXI_0_1 [get_bd_intf_ports S_QDMA_SLAVE_BRIDGE] [get_bd_intf_pins axi_register_slice_4/S_AXI] + connect_bd_intf_net -intf_net axi_noc_0_M00_AXI [get_bd_intf_pins axi_noc_0/M00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_register_slice_0/M_AXI] [get_bd_intf_pins sl2noc_virt_0/S00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_register_slice_1/M_AXI] [get_bd_intf_pins sl2noc_virt_1/S00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_pins axi_register_slice_2/M_AXI] [get_bd_intf_pins sl2noc_virt_2/S00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_3_M_AXI [get_bd_intf_pins axi_register_slice_3/M_AXI] [get_bd_intf_pins sl2noc_virt_3/S00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_4_M_AXI [get_bd_intf_ports M_QDMA_SLAVE_BRIDGE] [get_bd_intf_pins axi_register_slice_4/M_AXI] + connect_bd_intf_net -intf_net dummy_noc_4_M00_AXIS [get_bd_intf_pins dummy_noc_4/M00_AXIS] [get_bd_intf_pins qsfp_2_n_3/S_AXIS_0] + connect_bd_intf_net -intf_net eth_0_m_axi_gmem0 [get_bd_intf_pins eth_0/m_axi_gmem0] [get_bd_intf_pins sl2noc_0/S00_AXI] + connect_bd_intf_net -intf_net eth_1_m_axi_gmem0 [get_bd_intf_pins eth_1/m_axi_gmem0] [get_bd_intf_pins sl2noc_1/S00_AXI] + connect_bd_intf_net -intf_net eth_2_m_axi_gmem0 [get_bd_intf_pins eth_2/m_axi_gmem0] [get_bd_intf_pins sl2noc_2/S00_AXI] + connect_bd_intf_net -intf_net eth_3_m_axi_gmem0 [get_bd_intf_pins eth_3/m_axi_gmem0] [get_bd_intf_pins sl2noc_3/S00_AXI] + connect_bd_intf_net -intf_net eth_4_m_axi_gmem0 [get_bd_intf_pins eth_4/m_axi_gmem0] [get_bd_intf_pins sl2noc_4/S00_AXI] + connect_bd_intf_net -intf_net eth_5_m_axi_gmem0 [get_bd_intf_pins eth_5/m_axi_gmem0] [get_bd_intf_pins sl2noc_5/S00_AXI] + connect_bd_intf_net -intf_net eth_6_m_axi_gmem0 [get_bd_intf_pins eth_6/m_axi_gmem0] [get_bd_intf_pins sl2noc_6/S00_AXI] + connect_bd_intf_net -intf_net eth_7_m_axi_gmem0 [get_bd_intf_pins eth_7/m_axi_gmem0] [get_bd_intf_pins sl2noc_7/S00_AXI] + connect_bd_intf_net -intf_net qsfp0_322mhz_1 [get_bd_intf_ports qsfp0_322mhz] [get_bd_intf_pins qsfp_0_n_1/qsfp_clk_322mhz] + connect_bd_intf_net -intf_net qsfp2_322mhz_1 [get_bd_intf_ports qsfp2_322mhz] [get_bd_intf_pins qsfp_2_n_3/qsfp_clk_322mhz] + connect_bd_intf_net -intf_net qsfp_0_n_1_M_AXIS_0 [get_bd_intf_pins dummy_noc_m_0/S00_AXIS] [get_bd_intf_pins qsfp_0_n_1/M_AXIS_0] + connect_bd_intf_net -intf_net qsfp_0_n_1_qsfp_gt0 [get_bd_intf_ports qsfp0_4x] [get_bd_intf_pins qsfp_0_n_1/qsfp_gt0] + connect_bd_intf_net -intf_net qsfp_2_n_3_M_AXIS_0 [get_bd_intf_pins dummy_noc_m_4/S00_AXIS] [get_bd_intf_pins qsfp_2_n_3/M_AXIS_0] + connect_bd_intf_net -intf_net qsfp_2_n_3_qsfp_gt0 [get_bd_intf_ports qsfp2_4x] [get_bd_intf_pins qsfp_2_n_3/qsfp_gt0] + connect_bd_intf_net -intf_net sl2noc_0_M00_INI [get_bd_intf_ports SL2NOC_0] [get_bd_intf_pins sl2noc_0/M00_INI] + connect_bd_intf_net -intf_net sl2noc_1_M00_INI [get_bd_intf_ports SL2NOC_1] [get_bd_intf_pins sl2noc_1/M00_INI] + connect_bd_intf_net -intf_net sl2noc_2_M00_INI [get_bd_intf_ports SL2NOC_2] [get_bd_intf_pins sl2noc_2/M00_INI] + connect_bd_intf_net -intf_net sl2noc_3_M00_INI [get_bd_intf_ports SL2NOC_3] [get_bd_intf_pins sl2noc_3/M00_INI] + connect_bd_intf_net -intf_net sl2noc_4_M00_INI [get_bd_intf_ports SL2NOC_4] [get_bd_intf_pins sl2noc_4/M00_INI] + connect_bd_intf_net -intf_net sl2noc_5_M00_INI [get_bd_intf_ports SL2NOC_5] [get_bd_intf_pins sl2noc_5/M00_INI] + connect_bd_intf_net -intf_net sl2noc_6_M00_INI [get_bd_intf_ports SL2NOC_6] [get_bd_intf_pins sl2noc_6/M00_INI] + connect_bd_intf_net -intf_net sl2noc_7_M00_INI [get_bd_intf_ports SL2NOC_7] [get_bd_intf_pins sl2noc_7/M00_INI] + connect_bd_intf_net -intf_net sl2noc_virt_0_M00_INI [get_bd_intf_ports M_VIRT_0] [get_bd_intf_pins sl2noc_virt_0/M00_INI] + connect_bd_intf_net -intf_net sl2noc_virt_1_M00_INI [get_bd_intf_ports M_VIRT_1] [get_bd_intf_pins sl2noc_virt_1/M00_INI] + connect_bd_intf_net -intf_net sl2noc_virt_2_M00_INI [get_bd_intf_ports M_VIRT_2] [get_bd_intf_pins sl2noc_virt_2/M00_INI] + connect_bd_intf_net -intf_net sl2noc_virt_3_M00_INI [get_bd_intf_ports M_VIRT_3] [get_bd_intf_pins sl2noc_virt_3/M00_INI] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins traffic_producer_0/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins smartconnect_0/M01_AXI] [get_bd_intf_pins traffic_producer_1/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins smartconnect_0/M02_AXI] [get_bd_intf_pins traffic_producer_2/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins smartconnect_0/M03_AXI] [get_bd_intf_pins traffic_producer_3/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins smartconnect_0/M04_AXI] [get_bd_intf_pins traffic_producer_4/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins smartconnect_0/M05_AXI] [get_bd_intf_pins traffic_producer_5/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins smartconnect_0/M06_AXI] [get_bd_intf_pins traffic_producer_6/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins smartconnect_0/M07_AXI] [get_bd_intf_pins traffic_producer_7/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M08_AXI [get_bd_intf_pins eth_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M08_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M09_AXI [get_bd_intf_pins eth_1/s_axi_control] [get_bd_intf_pins smartconnect_0/M09_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M10_AXI [get_bd_intf_pins eth_2/s_axi_control] [get_bd_intf_pins smartconnect_0/M10_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M11_AXI [get_bd_intf_pins eth_3/s_axi_control] [get_bd_intf_pins smartconnect_0/M11_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M12_AXI [get_bd_intf_pins eth_4/s_axi_control] [get_bd_intf_pins smartconnect_0/M12_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M13_AXI [get_bd_intf_pins eth_5/s_axi_control] [get_bd_intf_pins smartconnect_0/M13_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M14_AXI [get_bd_intf_pins eth_6/s_axi_control] [get_bd_intf_pins smartconnect_0/M14_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M15_AXI [get_bd_intf_pins smartconnect_1/S00_AXI] [get_bd_intf_pins smartconnect_0/M15_AXI] + connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins smartconnect_1/M00_AXI] [get_bd_intf_pins eth_7/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_1_M01_AXI [get_bd_intf_pins smartconnect_1/M01_AXI] [get_bd_intf_pins qsfp_0_n_1/s_axi] + connect_bd_intf_net -intf_net smartconnect_1_M02_AXI [get_bd_intf_pins smartconnect_1/M02_AXI] [get_bd_intf_pins qsfp_2_n_3/s_axi] + connect_bd_intf_net -intf_net traffic_producer_1_axis_out [get_bd_intf_pins traffic_producer_1/axis_out] [get_bd_intf_pins dummy_noc_m_1/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_2_axis_out [get_bd_intf_pins traffic_producer_2/axis_out] [get_bd_intf_pins dummy_noc_m_2/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_3_axis_out [get_bd_intf_pins traffic_producer_3/axis_out] [get_bd_intf_pins dummy_noc_m_3/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_5_axis_out [get_bd_intf_pins traffic_producer_5/axis_out] [get_bd_intf_pins dummy_noc_m_5/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_6_axis_out [get_bd_intf_pins traffic_producer_6/axis_out] [get_bd_intf_pins dummy_noc_m_6/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_7_axis_out [get_bd_intf_pins traffic_producer_7/axis_out] [get_bd_intf_pins dummy_noc_m_7/S00_AXIS] + + # Create port connections + connect_bd_net -net aclk0_1 [get_bd_ports aclk0] \ + [get_bd_pins dummy_noc_0/aclk0] \ + [get_bd_pins dummy_noc_1/aclk0] \ + [get_bd_pins dummy_noc_2/aclk0] \ + [get_bd_pins dummy_noc_3/aclk0] \ + [get_bd_pins dummy_noc_4/aclk0] \ + [get_bd_pins dummy_noc_5/aclk0] \ + [get_bd_pins dummy_noc_6/aclk0] \ + [get_bd_pins dummy_noc_7/aclk0] \ + [get_bd_pins dummy_noc_m_0/aclk0] \ + [get_bd_pins dummy_noc_m_1/aclk0] \ + [get_bd_pins dummy_noc_m_2/aclk0] \ + [get_bd_pins dummy_noc_m_3/aclk0] \ + [get_bd_pins dummy_noc_m_4/aclk0] \ + [get_bd_pins dummy_noc_m_5/aclk0] \ + [get_bd_pins dummy_noc_m_6/aclk0] \ + [get_bd_pins dummy_noc_m_7/aclk0] \ + [get_bd_pins traffic_producer_0/ap_clk] \ + [get_bd_pins traffic_producer_1/ap_clk] \ + [get_bd_pins traffic_producer_2/ap_clk] \ + [get_bd_pins traffic_producer_3/ap_clk] \ + [get_bd_pins traffic_producer_4/ap_clk] \ + [get_bd_pins traffic_producer_5/ap_clk] \ + [get_bd_pins traffic_producer_6/ap_clk] \ + [get_bd_pins traffic_producer_7/ap_clk] \ + [get_bd_pins smartconnect_0/aclk] \ + [get_bd_pins eth_0/ap_clk] \ + [get_bd_pins eth_1/ap_clk] \ + [get_bd_pins eth_2/ap_clk] \ + [get_bd_pins eth_3/ap_clk] \ + [get_bd_pins eth_4/ap_clk] \ + [get_bd_pins eth_5/ap_clk] \ + [get_bd_pins eth_6/ap_clk] \ + [get_bd_pins eth_7/ap_clk] \ + [get_bd_pins sl2noc_0/aclk0] \ + [get_bd_pins sl2noc_1/aclk0] \ + [get_bd_pins sl2noc_2/aclk0] \ + [get_bd_pins sl2noc_3/aclk0] \ + [get_bd_pins sl2noc_4/aclk0] \ + [get_bd_pins sl2noc_5/aclk0] \ + [get_bd_pins sl2noc_6/aclk0] \ + [get_bd_pins sl2noc_7/aclk0] \ + [get_bd_pins axi_register_slice_0/aclk] \ + [get_bd_pins axi_register_slice_1/aclk] \ + [get_bd_pins axi_register_slice_2/aclk] \ + [get_bd_pins axi_register_slice_3/aclk] \ + [get_bd_pins sl2noc_virt_0/aclk0] \ + [get_bd_pins sl2noc_virt_1/aclk0] \ + [get_bd_pins sl2noc_virt_2/aclk0] \ + [get_bd_pins sl2noc_virt_3/aclk0] \ + [get_bd_pins qsfp_0_n_1/ap_clk] \ + [get_bd_pins qsfp_2_n_3/ap_clk] \ + [get_bd_pins axi_register_slice_4/aclk] \ + [get_bd_pins smartconnect_1/aclk] \ + [get_bd_pins axi_noc_0/aclk0] + connect_bd_net -net aclk1_1 [get_bd_ports aclk1] \ + [get_bd_pins smartconnect_0/aclk1] \ + [get_bd_pins smartconnect_1/aclk1] + connect_bd_net -net ap_rst_n_1 [get_bd_ports ap_rst_n] \ + [get_bd_pins traffic_producer_0/ap_rst_n] \ + [get_bd_pins traffic_producer_1/ap_rst_n] \ + [get_bd_pins traffic_producer_2/ap_rst_n] \ + [get_bd_pins traffic_producer_3/ap_rst_n] \ + [get_bd_pins traffic_producer_4/ap_rst_n] \ + [get_bd_pins traffic_producer_5/ap_rst_n] \ + [get_bd_pins traffic_producer_6/ap_rst_n] \ + [get_bd_pins traffic_producer_7/ap_rst_n] \ + [get_bd_pins smartconnect_0/aresetn] \ + [get_bd_pins eth_0/ap_rst_n] \ + [get_bd_pins eth_1/ap_rst_n] \ + [get_bd_pins eth_2/ap_rst_n] \ + [get_bd_pins eth_3/ap_rst_n] \ + [get_bd_pins eth_4/ap_rst_n] \ + [get_bd_pins eth_5/ap_rst_n] \ + [get_bd_pins eth_6/ap_rst_n] \ + [get_bd_pins eth_7/ap_rst_n] \ + [get_bd_pins axi_register_slice_0/aresetn] \ + [get_bd_pins axi_register_slice_1/aresetn] \ + [get_bd_pins axi_register_slice_2/aresetn] \ + [get_bd_pins axi_register_slice_3/aresetn] \ + [get_bd_pins qsfp_0_n_1/ap_rst_n] \ + [get_bd_pins qsfp_2_n_3/ap_rst_n] \ + [get_bd_pins axi_register_slice_4/aresetn] \ + [get_bd_pins smartconnect_1/aresetn] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] \ + [get_bd_pins dummy_noc_1/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_2/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_3/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_5/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_6/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_7/M00_AXIS_tready] + + # Create address segments + assign_bd_address -offset 0x00 -range 16E -target_address_space [get_bd_addr_spaces eth_0/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_0/Reg] -force + assign_bd_address -offset 0x00 -range 16E -target_address_space [get_bd_addr_spaces eth_1/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_1/Reg] -force + assign_bd_address -offset 0x00 -range 16E -target_address_space [get_bd_addr_spaces eth_2/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_2/Reg] -force + assign_bd_address -offset 0x00 -range 16E -target_address_space [get_bd_addr_spaces eth_3/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_3/Reg] -force + assign_bd_address -offset 0x00 -range 16E -target_address_space [get_bd_addr_spaces eth_4/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_4/Reg] -force + assign_bd_address -offset 0x00 -range 16E -target_address_space [get_bd_addr_spaces eth_5/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_5/Reg] -force + assign_bd_address -offset 0x00 -range 16E -target_address_space [get_bd_addr_spaces eth_6/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_6/Reg] -force + assign_bd_address -offset 0x00 -range 16E -target_address_space [get_bd_addr_spaces eth_7/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_7/Reg] -force + # assign_bd_address -offset 0x020300110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + # assign_bd_address -offset 0x020300150000 -range 0x00010000 -with_name SEG_axi_gpio_datapath_Reg_1 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + # assign_bd_address -offset 0x020300100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + # assign_bd_address -offset 0x020300160000 -range 0x00010000 -with_name SEG_axi_gpio_gt_control_Reg_1 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + # assign_bd_address -offset 0x020300120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + # assign_bd_address -offset 0x020300170000 -range 0x00010000 -with_name SEG_axi_gpio_monitor_Reg_1 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + # assign_bd_address -offset 0x020300130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + # assign_bd_address -offset 0x020300180000 -range 0x00010000 -with_name SEG_axi_gpio_reset_txrx_Reg_1 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + # assign_bd_address -offset 0x020300140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/DCMAC_subsys/dcmac_0_core/s_axi/Reg] -force + # assign_bd_address -offset 0x020300190000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/DCMAC_subsys/dcmac_1_core/s_axi/Reg] -force + assign_bd_address -offset 0x020300000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_7/s_axi_control/Reg] -force + assign_bd_address -offset 0xE000_0000 -range 256M -target_address_space [get_bd_addr_spaces S_QDMA_SLAVE_BRIDGE] [get_bd_addr_segs M_QDMA_SLAVE_BRIDGE/Reg] -force + assign_bd_address -offset 0x00 -range 16E -target_address_space [get_bd_addr_spaces S_VIRT_0] [get_bd_addr_segs M_VIRT_0/Reg] -force + assign_bd_address -offset 0x00 -range 16E -target_address_space [get_bd_addr_spaces S_VIRT_1] [get_bd_addr_segs M_VIRT_1/Reg] -force + assign_bd_address -offset 0x00 -range 16E -target_address_space [get_bd_addr_spaces S_VIRT_2] [get_bd_addr_segs M_VIRT_2/Reg] -force + assign_bd_address -offset 0x00 -range 16E -target_address_space [get_bd_addr_spaces S_VIRT_3] [get_bd_addr_segs M_VIRT_3/Reg] -force + + set_property USAGE memory [get_bd_addr_segs M_VIRT_0/Reg] + set_property USAGE memory [get_bd_addr_segs M_VIRT_1/Reg] + set_property USAGE memory [get_bd_addr_segs M_VIRT_2/Reg] + set_property USAGE memory [get_bd_addr_segs M_VIRT_3/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_0/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_1/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_2/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_3/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_4/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_5/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_6/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_7/Reg] + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/linker/resources/base/scripts/slash_base.tcl b/linker/resources/base/scripts/slash_base.tcl new file mode 100644 index 00000000..cf0c9f3e --- /dev/null +++ b/linker/resources/base/scripts/slash_base.tcl @@ -0,0 +1,3130 @@ + +################################################################ +# This is a generated script based on design: slash_base +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2024.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."} + + } else { + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + } + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source slash_base_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xcv80-lsva4737-2MHP-e-S +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name slash_base + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:hls:hbm_bandwidth:1.0\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:ip:axi_noc:1.1\ +xilinx.com:ip:axis_noc:1.0\ +xilinx.com:hls:traffic_producer:1.0\ +xilinx.com:ip:xlconstant:1.1\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set HBM_AXI_00 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_00 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_00 + + set HBM_AXI_01 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_01 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_01 + + set HBM_AXI_10 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_10 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_10 + + set HBM_AXI_11 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_11 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_11 + + set HBM_AXI_12 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_12 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_12 + + set HBM_AXI_13 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_13 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_13 + + set HBM_AXI_14 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_14 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_14 + + set HBM_AXI_15 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_15 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_15 + + set HBM_AXI_16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_16 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_16 + + set HBM_AXI_17 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_17 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_17 + + set HBM_AXI_18 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_18 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_18 + + set HBM_AXI_19 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_19 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_19 + + set HBM_AXI_02 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_02 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_02 + + set HBM_AXI_20 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_20 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_20 + + set HBM_AXI_21 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_21 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_21 + + set HBM_AXI_22 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_22 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_22 + + set HBM_AXI_23 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_23 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_23 + + set HBM_AXI_24 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_24 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_24 + + set HBM_AXI_25 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_25 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_25 + + set HBM_AXI_26 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_26 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_26 + + set HBM_AXI_27 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_27 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_27 + + set HBM_AXI_28 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_28 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_28 + + set HBM_AXI_29 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_29 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_29 + + set HBM_AXI_03 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_03 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_03 + + set HBM_AXI_30 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_30 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_30 + + set HBM_AXI_31 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_31 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_31 + + set HBM_AXI_32 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_32 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_32 + + set HBM_AXI_33 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_33 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_33 + + set HBM_AXI_34 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_34 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_34 + + set HBM_AXI_35 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_35 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_35 + + set HBM_AXI_36 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_36 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_36 + + set HBM_AXI_37 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_37 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_37 + + set HBM_AXI_38 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_38 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_38 + + set HBM_AXI_39 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_39 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_39 + + set HBM_AXI_04 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_04 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_04 + + set HBM_AXI_40 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_40 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_40 + + set HBM_AXI_41 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_41 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_41 + + set HBM_AXI_42 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_42 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_42 + + set HBM_AXI_43 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_43 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_43 + + set HBM_AXI_44 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_44 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_44 + + set HBM_AXI_45 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_45 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_45 + + set HBM_AXI_46 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_46 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_46 + + set HBM_AXI_47 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_47 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_47 + + set HBM_AXI_48 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_48 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_48 + + set HBM_AXI_49 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_49 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_49 + + set HBM_AXI_05 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_05 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_05 + + set HBM_AXI_50 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_50 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_50 + + set HBM_AXI_51 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_51 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_51 + + set HBM_AXI_52 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_52 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_52 + + set HBM_AXI_53 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_53 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_53 + + set HBM_AXI_54 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_54 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_54 + + set HBM_AXI_55 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_55 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_55 + + set HBM_AXI_56 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_56 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_56 + + set HBM_AXI_57 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_57 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_57 + + set HBM_AXI_58 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_58 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_58 + + set HBM_AXI_59 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_59 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_59 + + set HBM_AXI_06 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_06 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_06 + + set HBM_AXI_60 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_60 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_60 + + set HBM_AXI_61 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_61 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_61 + + set HBM_AXI_62 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_62 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_62 + + set HBM_AXI_63 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_63 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_63 + + set HBM_AXI_07 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_07 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_07 + + set HBM_AXI_08 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_08 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_08 + + set HBM_AXI_09 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_09 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $HBM_AXI_09 + + set M00_INI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M00_INI ] + + set M01_INI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M01_INI ] + + set M02_INI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M02_INI ] + + set M03_INI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M03_INI ] + + set HBM_VNOC_INI_00 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_00 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_00 + + set HBM_VNOC_INI_01 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_01 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_01 + + set HBM_VNOC_INI_02 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_02 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_02 + + set HBM_VNOC_INI_03 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_03 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_03 + + set HBM_VNOC_INI_04 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_04 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_04 + + set HBM_VNOC_INI_05 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_05 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_05 + + set HBM_VNOC_INI_06 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_06 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_06 + + set HBM_VNOC_INI_07 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_07 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_07 + + set M_DCMAC_INIS0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS0 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS0 + + set M_DCMAC_INIS1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS1 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS1 + + set M_DCMAC_INIS2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS2 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS2 + + set M_DCMAC_INIS3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS3 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS3 + + set M_DCMAC_INIS4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS4 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS4 + + set M_DCMAC_INIS5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS5 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS5 + + set M_DCMAC_INIS6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS6 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS6 + + set M_DCMAC_INIS7 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS7 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS7 + + set S_DCMAC_INIS0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS0 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS0 + + set S_DCMAC_INIS1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS1 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS1 + + set S_DCMAC_INIS2 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS2 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS2 + + set S_DCMAC_INIS3 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS3 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS3 + + set S_DCMAC_INIS4 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS4 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS4 + + set S_DCMAC_INIS5 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS5 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS5 + + set S_DCMAC_INIS6 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS6 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS6 + + set S_DCMAC_INIS7 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS7 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS7 + + set SL_VIRT_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 SL_VIRT_0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + ] $SL_VIRT_0 + + set SL_VIRT_1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 SL_VIRT_1 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + ] $SL_VIRT_1 + + set SL_VIRT_2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 SL_VIRT_2 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + ] $SL_VIRT_2 + + set SL_VIRT_3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 SL_VIRT_3 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + ] $SL_VIRT_3 + + set QDMA_SLAVE_BRIDGE [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 QDMA_SLAVE_BRIDGE ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {WRITE_ONLY} \ + ] $QDMA_SLAVE_BRIDGE + + set S_AXILITE_INI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S_AXILITE_INI ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_AXILITE_INI + set_property APERTURES {{0x202_0000_0000 128M}} [get_bd_intf_ports S_AXILITE_INI] + + + # Create ports + set aclk1 [ create_bd_port -dir I -type clk -freq_hz 300000000 aclk1 ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {HBM_AXI_05:HBM_AXI_02:HBM_AXI_03:HBM_AXI_06:HBM_AXI_09:HBM_AXI_07:HBM_AXI_08:HBM_AXI_00:HBM_AXI_01:HBM_AXI_04:HBM_AXI_10:HBM_AXI_11:HBM_AXI_12:HBM_AXI_13:HBM_AXI_14:HBM_AXI_15:HBM_AXI_16:HBM_AXI_17:HBM_AXI_18:HBM_AXI_19:HBM_AXI_20:HBM_AXI_21:HBM_AXI_22:HBM_AXI_23:HBM_AXI_24:HBM_AXI_25:HBM_AXI_26:HBM_AXI_27:HBM_AXI_28:HBM_AXI_29:HBM_AXI_30:HBM_AXI_31:HBM_AXI_32:HBM_AXI_33:HBM_AXI_34:HBM_AXI_35:HBM_AXI_36:HBM_AXI_37:HBM_AXI_38:HBM_AXI_39:HBM_AXI_40:HBM_AXI_41:HBM_AXI_42:HBM_AXI_43:HBM_AXI_44:HBM_AXI_45:HBM_AXI_46:HBM_AXI_47:HBM_AXI_48:HBM_AXI_49:HBM_AXI_50:HBM_AXI_51:HBM_AXI_52:HBM_AXI_53:HBM_AXI_54:HBM_AXI_55:HBM_AXI_56:HBM_AXI_57:HBM_AXI_58:HBM_AXI_59:HBM_AXI_60:HBM_AXI_61:HBM_AXI_62:HBM_AXI_63:SL_VIRT_0:SL_VIRT_1:SL_VIRT_2:SL_VIRT_3:QDMA_SLAVE_BRIDGE:S_AXILITE_INI} \ + CONFIG.CLK_DOMAIN {top_clk_wizard_0_0_clk_out1} \ + ] $aclk1 + set ap_rst_n [ create_bd_port -dir I -type rst ap_rst_n ] + set arstn [ create_bd_port -dir I -type rst arstn ] + set s_axi_aclk [ create_bd_port -dir I -type clk -freq_hz 300000000 s_axi_aclk ] + + # Create instance: ddr_bandwidth_64, and set properties + set ddr_bandwidth_64 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 ddr_bandwidth_64 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $ddr_bandwidth_64 + + + # Create instance: ddr_bandwidth_65, and set properties + set ddr_bandwidth_65 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 ddr_bandwidth_65 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $ddr_bandwidth_65 + + + # Create instance: ddr_bandwidth_66, and set properties + set ddr_bandwidth_66 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 ddr_bandwidth_66 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $ddr_bandwidth_66 + + + # Create instance: ddr_bandwidth_67, and set properties + set ddr_bandwidth_67 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 ddr_bandwidth_67 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $ddr_bandwidth_67 + + + # Create instance: hbm_bandwidth_0, and set properties + set hbm_bandwidth_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_0 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_0 + + + # Create instance: hbm_bandwidth_1, and set properties + set hbm_bandwidth_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_1 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_1 + + + # Create instance: hbm_bandwidth_10, and set properties + set hbm_bandwidth_10 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_10 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_10 + + + # Create instance: hbm_bandwidth_11, and set properties + set hbm_bandwidth_11 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_11 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_11 + + + # Create instance: hbm_bandwidth_12, and set properties + set hbm_bandwidth_12 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_12 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_12 + + + # Create instance: hbm_bandwidth_13, and set properties + set hbm_bandwidth_13 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_13 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_13 + + + # Create instance: hbm_bandwidth_14, and set properties + set hbm_bandwidth_14 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_14 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_14 + + + # Create instance: hbm_bandwidth_15, and set properties + set hbm_bandwidth_15 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_15 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_15 + + + # Create instance: hbm_bandwidth_16, and set properties + set hbm_bandwidth_16 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_16 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_16 + + + # Create instance: hbm_bandwidth_17, and set properties + set hbm_bandwidth_17 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_17 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_17 + + + # Create instance: hbm_bandwidth_18, and set properties + set hbm_bandwidth_18 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_18 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_18 + + + # Create instance: hbm_bandwidth_19, and set properties + set hbm_bandwidth_19 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_19 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_19 + + + # Create instance: hbm_bandwidth_2, and set properties + set hbm_bandwidth_2 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_2 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_2 + + + # Create instance: hbm_bandwidth_20, and set properties + set hbm_bandwidth_20 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_20 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_20 + + + # Create instance: hbm_bandwidth_21, and set properties + set hbm_bandwidth_21 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_21 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_21 + + + # Create instance: hbm_bandwidth_22, and set properties + set hbm_bandwidth_22 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_22 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_22 + + + # Create instance: hbm_bandwidth_23, and set properties + set hbm_bandwidth_23 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_23 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_23 + + + # Create instance: hbm_bandwidth_24, and set properties + set hbm_bandwidth_24 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_24 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_24 + + + # Create instance: hbm_bandwidth_25, and set properties + set hbm_bandwidth_25 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_25 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_25 + + + # Create instance: hbm_bandwidth_26, and set properties + set hbm_bandwidth_26 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_26 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_26 + + + # Create instance: hbm_bandwidth_27, and set properties + set hbm_bandwidth_27 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_27 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_27 + + + # Create instance: hbm_bandwidth_28, and set properties + set hbm_bandwidth_28 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_28 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_28 + + + # Create instance: hbm_bandwidth_29, and set properties + set hbm_bandwidth_29 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_29 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_29 + + + # Create instance: hbm_bandwidth_3, and set properties + set hbm_bandwidth_3 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_3 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_3 + + + # Create instance: hbm_bandwidth_30, and set properties + set hbm_bandwidth_30 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_30 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_30 + + + # Create instance: hbm_bandwidth_31, and set properties + set hbm_bandwidth_31 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_31 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_31 + + + # Create instance: hbm_bandwidth_32, and set properties + set hbm_bandwidth_32 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_32 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_32 + + + # Create instance: hbm_bandwidth_33, and set properties + set hbm_bandwidth_33 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_33 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_33 + + + # Create instance: hbm_bandwidth_34, and set properties + set hbm_bandwidth_34 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_34 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_34 + + + # Create instance: hbm_bandwidth_35, and set properties + set hbm_bandwidth_35 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_35 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_35 + + + # Create instance: hbm_bandwidth_36, and set properties + set hbm_bandwidth_36 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_36 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_36 + + + # Create instance: hbm_bandwidth_37, and set properties + set hbm_bandwidth_37 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_37 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_37 + + + # Create instance: hbm_bandwidth_38, and set properties + set hbm_bandwidth_38 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_38 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_38 + + + # Create instance: hbm_bandwidth_39, and set properties + set hbm_bandwidth_39 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_39 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_39 + + + # Create instance: hbm_bandwidth_4, and set properties + set hbm_bandwidth_4 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_4 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_4 + + + # Create instance: hbm_bandwidth_40, and set properties + set hbm_bandwidth_40 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_40 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_40 + + + # Create instance: hbm_bandwidth_41, and set properties + set hbm_bandwidth_41 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_41 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_41 + + + # Create instance: hbm_bandwidth_42, and set properties + set hbm_bandwidth_42 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_42 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_42 + + + # Create instance: hbm_bandwidth_43, and set properties + set hbm_bandwidth_43 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_43 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_43 + + + # Create instance: hbm_bandwidth_44, and set properties + set hbm_bandwidth_44 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_44 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_44 + + + # Create instance: hbm_bandwidth_45, and set properties + set hbm_bandwidth_45 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_45 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_45 + + + # Create instance: hbm_bandwidth_46, and set properties + set hbm_bandwidth_46 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_46 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_46 + + + # Create instance: hbm_bandwidth_47, and set properties + set hbm_bandwidth_47 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_47 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_47 + + + # Create instance: hbm_bandwidth_48, and set properties + set hbm_bandwidth_48 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_48 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_48 + + + # Create instance: hbm_bandwidth_49, and set properties + set hbm_bandwidth_49 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_49 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_49 + + + # Create instance: hbm_bandwidth_5, and set properties + set hbm_bandwidth_5 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_5 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_5 + + + # Create instance: hbm_bandwidth_50, and set properties + set hbm_bandwidth_50 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_50 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_50 + + + # Create instance: hbm_bandwidth_51, and set properties + set hbm_bandwidth_51 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_51 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_51 + + + # Create instance: hbm_bandwidth_52, and set properties + set hbm_bandwidth_52 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_52 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_52 + + + # Create instance: hbm_bandwidth_53, and set properties + set hbm_bandwidth_53 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_53 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_53 + + + # Create instance: hbm_bandwidth_54, and set properties + set hbm_bandwidth_54 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_54 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_54 + + + # Create instance: hbm_bandwidth_55, and set properties + set hbm_bandwidth_55 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_55 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_55 + + + # Create instance: hbm_bandwidth_56, and set properties + set hbm_bandwidth_56 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_56 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_56 + + + # Create instance: hbm_bandwidth_57, and set properties + set hbm_bandwidth_57 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_57 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_57 + + + # Create instance: hbm_bandwidth_58, and set properties + set hbm_bandwidth_58 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_58 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_58 + + + # Create instance: hbm_bandwidth_59, and set properties + set hbm_bandwidth_59 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_59 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_59 + + + # Create instance: hbm_bandwidth_6, and set properties + set hbm_bandwidth_6 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_6 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_6 + + + # Create instance: hbm_bandwidth_60, and set properties + set hbm_bandwidth_60 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_60 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_60 + + + # Create instance: hbm_bandwidth_61, and set properties + set hbm_bandwidth_61 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_61 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_61 + + + # Create instance: hbm_bandwidth_62, and set properties + set hbm_bandwidth_62 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_62 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_62 + + + # Create instance: hbm_bandwidth_63, and set properties + set hbm_bandwidth_63 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_63 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_63 + + + # Create instance: hbm_bandwidth_7, and set properties + set hbm_bandwidth_7 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_7 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_7 + + + # Create instance: hbm_bandwidth_8, and set properties + set hbm_bandwidth_8 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_8 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_8 + + + # Create instance: hbm_bandwidth_9, and set properties + set hbm_bandwidth_9 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_9 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_9 + + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {16} \ + ] $smartconnect_0 + + + # Create instance: ddr_noc_0, and set properties + set ddr_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 ddr_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_0/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_0/aclk0] + + # Create instance: ddr_noc_1, and set properties + set ddr_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 ddr_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_1/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_1/aclk0] + + # Create instance: ddr_noc_2, and set properties + set ddr_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 ddr_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_2/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_2/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_2/aclk0] + + # Create instance: ddr_noc_3, and set properties + set ddr_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 ddr_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_3/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_3/aclk0] + + # Create instance: hbm_bandwidth_64, and set properties + set hbm_bandwidth_64 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_64 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_64 + + + # Create instance: hbm_bandwidth_65, and set properties + set hbm_bandwidth_65 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_65 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_65 + + + # Create instance: hbm_bandwidth_66, and set properties + set hbm_bandwidth_66 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_66 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_66 + + + # Create instance: hbm_bandwidth_67, and set properties + set hbm_bandwidth_67 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_67 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_67 + + + # Create instance: hbm_bandwidth_68, and set properties + set hbm_bandwidth_68 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_68 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_68 + + + # Create instance: hbm_bandwidth_69, and set properties + set hbm_bandwidth_69 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_69 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_69 + + + # Create instance: hbm_bandwidth_70, and set properties + set hbm_bandwidth_70 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_70 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_70 + + + # Create instance: hbm_bandwidth_71, and set properties + set hbm_bandwidth_71 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_71 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_71 + + + # Create instance: hbm_vnoc_00, and set properties + set hbm_vnoc_00 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_00 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_00 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_00/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_00/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_00/aclk0] + + # Create instance: hbm_vnoc_01, and set properties + set hbm_vnoc_01 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_01 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_01 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_01/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_01/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_01/aclk0] + + # Create instance: hbm_vnoc_02, and set properties + set hbm_vnoc_02 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_02 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_02 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_02/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_02/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_02/aclk0] + + # Create instance: hbm_vnoc_03, and set properties + set hbm_vnoc_03 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_03 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_03 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_03/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_03/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_03/aclk0] + + # Create instance: hbm_vnoc_04, and set properties + set hbm_vnoc_04 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_04 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_04 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_04/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_04/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_04/aclk0] + + # Create instance: hbm_vnoc_05, and set properties + set hbm_vnoc_05 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_05 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_05 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_05/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_05/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_05/aclk0] + + # Create instance: hbm_vnoc_06, and set properties + set hbm_vnoc_06 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_06 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_06 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_06/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_06/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_06/aclk0] + + # Create instance: hbm_vnoc_07, and set properties + set hbm_vnoc_07 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_07 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_07 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_07/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_07/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_07/aclk0] + + # Create instance: dcmac_axis_noc_0, and set properties + set dcmac_axis_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_0/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_0/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_0/aclk0] + + # Create instance: dcmac_axis_noc_1, and set properties + set dcmac_axis_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_1/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_1/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_1/aclk0] + + # Create instance: dcmac_axis_noc_2, and set properties + set dcmac_axis_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_2/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_2/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_2/aclk0] + + # Create instance: dcmac_axis_noc_3, and set properties + set dcmac_axis_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_3/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_3/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_3/aclk0] + + # Create instance: dcmac_axis_noc_4, and set properties + set dcmac_axis_noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_4/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_4/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_4/aclk0] + + # Create instance: dcmac_axis_noc_5, and set properties + set dcmac_axis_noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_5/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_5/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_5/aclk0] + + # Create instance: dcmac_axis_noc_6, and set properties + set dcmac_axis_noc_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_6/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_6/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_6/aclk0] + + # Create instance: dcmac_axis_noc_7, and set properties + set dcmac_axis_noc_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_7/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_7/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_7/aclk0] + + # Create instance: dcmac_axis_noc_s_0, and set properties + set dcmac_axis_noc_s_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_0 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_0/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_0/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_0/aclk0] + + # Create instance: dcmac_axis_noc_s_1, and set properties + set dcmac_axis_noc_s_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_1 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_1 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_1/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_1/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_1/aclk0] + + # Create instance: dcmac_axis_noc_s_2, and set properties + set dcmac_axis_noc_s_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_2 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_2 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_2/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_2/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_2/aclk0] + + # Create instance: dcmac_axis_noc_s_3, and set properties + set dcmac_axis_noc_s_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_3 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_3 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_3/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_3/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_3/aclk0] + + # Create instance: dcmac_axis_noc_s_4, and set properties + set dcmac_axis_noc_s_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_4 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_4 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_4/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_4/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_4/aclk0] + + # Create instance: dcmac_axis_noc_s_5, and set properties + set dcmac_axis_noc_s_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_5 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_5 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_5/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_5/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_5/aclk0] + + # Create instance: dcmac_axis_noc_s_6, and set properties + set dcmac_axis_noc_s_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_6 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_6 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_6/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_6/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_6/aclk0] + + # Create instance: dcmac_axis_noc_s_7, and set properties + set dcmac_axis_noc_s_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_7 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_7 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_7/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_7/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_7/aclk0] + + # Create instance: traffic_producer_0, and set properties + set traffic_producer_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_0 ] + + # Create instance: traffic_producer_1, and set properties + set traffic_producer_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_1 ] + + # Create instance: traffic_producer_2, and set properties + set traffic_producer_2 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_2 ] + + # Create instance: traffic_producer_3, and set properties + set traffic_producer_3 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_3 ] + + # Create instance: traffic_producer_4, and set properties + set traffic_producer_4 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_4 ] + + # Create instance: traffic_producer_5, and set properties + set traffic_producer_5 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_5 ] + + # Create instance: traffic_producer_6, and set properties + set traffic_producer_6 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_6 ] + + # Create instance: traffic_producer_7, and set properties + set traffic_producer_7 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_7 ] + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + + # Create instance: traffic_virt_0, and set properties + set traffic_virt_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 traffic_virt_0 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {512} $traffic_virt_0 + + + # Create instance: traffic_virt_1, and set properties + set traffic_virt_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 traffic_virt_1 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {512} $traffic_virt_1 + + + # Create instance: traffic_virt_2, and set properties + set traffic_virt_2 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 traffic_virt_2 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {512} $traffic_virt_2 + + + # Create instance: traffic_virt_3, and set properties + set traffic_virt_3 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 traffic_virt_3 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {512} $traffic_virt_3 + + + # Create instance: traffic_virt_4, and set properties + set traffic_virt_4 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 traffic_virt_4 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {128} $traffic_virt_4 + + + # Create instance: smartconnect_1, and set properties + set smartconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_1 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {16} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_1 + + + # Create instance: smartconnect_2, and set properties + set smartconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_2 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {16} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_2 + + + # Create instance: smartconnect_3, and set properties + set smartconnect_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_3 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {16} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_3 + + + # Create instance: smartconnect_4, and set properties + set smartconnect_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_4 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {16} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_4 + + + # Create instance: smartconnect_5, and set properties + set smartconnect_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_5 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {14} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_5 + + + # Create instance: axi_noc_0, and set properties + set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_0 + + + set_property -dict [ list \ + CONFIG.APERTURES {{0x202_0000_0000 128M}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_0/M00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_0/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_0/aclk0] + + # Create interface connections + connect_bd_intf_net -intf_net S00_INIS_0_1 [get_bd_intf_ports S_DCMAC_INIS0] [get_bd_intf_pins dcmac_axis_noc_s_0/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_1_1 [get_bd_intf_ports S_DCMAC_INIS1] [get_bd_intf_pins dcmac_axis_noc_s_1/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_2_1 [get_bd_intf_ports S_DCMAC_INIS2] [get_bd_intf_pins dcmac_axis_noc_s_2/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_3_1 [get_bd_intf_ports S_DCMAC_INIS3] [get_bd_intf_pins dcmac_axis_noc_s_3/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_4_1 [get_bd_intf_ports S_DCMAC_INIS4] [get_bd_intf_pins dcmac_axis_noc_s_4/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_5_1 [get_bd_intf_ports S_DCMAC_INIS5] [get_bd_intf_pins dcmac_axis_noc_s_5/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_6_1 [get_bd_intf_ports S_DCMAC_INIS6] [get_bd_intf_pins dcmac_axis_noc_s_6/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_7_1 [get_bd_intf_ports S_DCMAC_INIS7] [get_bd_intf_pins dcmac_axis_noc_s_7/S00_INIS] + connect_bd_intf_net -intf_net S_AXILITE_INI_1 [get_bd_intf_ports S_AXILITE_INI] [get_bd_intf_pins axi_noc_0/S00_INI] + connect_bd_intf_net -intf_net axi_noc_0_M00_AXI [get_bd_intf_pins axi_noc_0/M00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net dcmac_axis_noc_0_M00_INIS [get_bd_intf_ports M_DCMAC_INIS0] [get_bd_intf_pins dcmac_axis_noc_0/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_1_M00_INIS [get_bd_intf_ports M_DCMAC_INIS1] [get_bd_intf_pins dcmac_axis_noc_1/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_2_M00_INIS [get_bd_intf_ports M_DCMAC_INIS2] [get_bd_intf_pins dcmac_axis_noc_2/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_3_M00_INIS [get_bd_intf_ports M_DCMAC_INIS3] [get_bd_intf_pins dcmac_axis_noc_3/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_4_M00_INIS [get_bd_intf_ports M_DCMAC_INIS4] [get_bd_intf_pins dcmac_axis_noc_4/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_5_M00_INIS [get_bd_intf_ports M_DCMAC_INIS5] [get_bd_intf_pins dcmac_axis_noc_5/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_6_M00_INIS [get_bd_intf_ports M_DCMAC_INIS6] [get_bd_intf_pins dcmac_axis_noc_6/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_7_M00_INIS [get_bd_intf_ports M_DCMAC_INIS7] [get_bd_intf_pins dcmac_axis_noc_7/M00_INIS] + connect_bd_intf_net -intf_net ddr_bandwidth_64_m_axi_gmem0 [get_bd_intf_pins ddr_bandwidth_64/m_axi_gmem0] [get_bd_intf_pins ddr_noc_0/S00_AXI] + connect_bd_intf_net -intf_net ddr_bandwidth_65_m_axi_gmem0 [get_bd_intf_pins ddr_bandwidth_65/m_axi_gmem0] [get_bd_intf_pins ddr_noc_1/S00_AXI] + connect_bd_intf_net -intf_net ddr_bandwidth_66_m_axi_gmem0 [get_bd_intf_pins ddr_bandwidth_66/m_axi_gmem0] [get_bd_intf_pins ddr_noc_2/S00_AXI] + connect_bd_intf_net -intf_net ddr_bandwidth_67_m_axi_gmem0 [get_bd_intf_pins ddr_bandwidth_67/m_axi_gmem0] [get_bd_intf_pins ddr_noc_3/S00_AXI] + connect_bd_intf_net -intf_net ddr_noc_0_M00_INI [get_bd_intf_ports M00_INI] [get_bd_intf_pins ddr_noc_0/M00_INI] + connect_bd_intf_net -intf_net ddr_noc_1_M00_INI [get_bd_intf_ports M01_INI] [get_bd_intf_pins ddr_noc_1/M00_INI] + connect_bd_intf_net -intf_net ddr_noc_2_M00_INI [get_bd_intf_ports M02_INI] [get_bd_intf_pins ddr_noc_2/M00_INI] + connect_bd_intf_net -intf_net ddr_noc_3_M00_INI [get_bd_intf_ports M03_INI] [get_bd_intf_pins ddr_noc_3/M00_INI] + connect_bd_intf_net -intf_net hbm_bandwidth_0_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_00] [get_bd_intf_pins hbm_bandwidth_0/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_10_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_10] [get_bd_intf_pins hbm_bandwidth_10/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_11_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_11] [get_bd_intf_pins hbm_bandwidth_11/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_12_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_12] [get_bd_intf_pins hbm_bandwidth_12/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_13_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_13] [get_bd_intf_pins hbm_bandwidth_13/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_14_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_14] [get_bd_intf_pins hbm_bandwidth_14/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_15_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_15] [get_bd_intf_pins hbm_bandwidth_15/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_16_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_16] [get_bd_intf_pins hbm_bandwidth_16/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_17_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_17] [get_bd_intf_pins hbm_bandwidth_17/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_18_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_18] [get_bd_intf_pins hbm_bandwidth_18/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_19_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_19] [get_bd_intf_pins hbm_bandwidth_19/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_1_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_01] [get_bd_intf_pins hbm_bandwidth_1/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_20_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_20] [get_bd_intf_pins hbm_bandwidth_20/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_21_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_21] [get_bd_intf_pins hbm_bandwidth_21/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_22_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_22] [get_bd_intf_pins hbm_bandwidth_22/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_23_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_23] [get_bd_intf_pins hbm_bandwidth_23/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_24_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_24] [get_bd_intf_pins hbm_bandwidth_24/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_25_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_25] [get_bd_intf_pins hbm_bandwidth_25/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_26_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_26] [get_bd_intf_pins hbm_bandwidth_26/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_27_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_27] [get_bd_intf_pins hbm_bandwidth_27/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_28_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_28] [get_bd_intf_pins hbm_bandwidth_28/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_29_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_29] [get_bd_intf_pins hbm_bandwidth_29/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_2_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_02] [get_bd_intf_pins hbm_bandwidth_2/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_30_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_30] [get_bd_intf_pins hbm_bandwidth_30/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_31_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_31] [get_bd_intf_pins hbm_bandwidth_31/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_32_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_32] [get_bd_intf_pins hbm_bandwidth_32/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_33_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_33] [get_bd_intf_pins hbm_bandwidth_33/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_34_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_34] [get_bd_intf_pins hbm_bandwidth_34/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_35_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_35] [get_bd_intf_pins hbm_bandwidth_35/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_36_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_36] [get_bd_intf_pins hbm_bandwidth_36/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_37_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_37] [get_bd_intf_pins hbm_bandwidth_37/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_38_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_38] [get_bd_intf_pins hbm_bandwidth_38/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_39_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_39] [get_bd_intf_pins hbm_bandwidth_39/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_3_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_03] [get_bd_intf_pins hbm_bandwidth_3/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_40_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_40] [get_bd_intf_pins hbm_bandwidth_40/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_41_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_41] [get_bd_intf_pins hbm_bandwidth_41/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_42_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_42] [get_bd_intf_pins hbm_bandwidth_42/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_43_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_43] [get_bd_intf_pins hbm_bandwidth_43/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_44_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_44] [get_bd_intf_pins hbm_bandwidth_44/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_45_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_45] [get_bd_intf_pins hbm_bandwidth_45/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_46_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_46] [get_bd_intf_pins hbm_bandwidth_46/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_47_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_47] [get_bd_intf_pins hbm_bandwidth_47/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_48_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_48] [get_bd_intf_pins hbm_bandwidth_48/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_49_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_49] [get_bd_intf_pins hbm_bandwidth_49/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_4_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_04] [get_bd_intf_pins hbm_bandwidth_4/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_50_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_50] [get_bd_intf_pins hbm_bandwidth_50/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_51_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_51] [get_bd_intf_pins hbm_bandwidth_51/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_52_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_52] [get_bd_intf_pins hbm_bandwidth_52/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_53_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_53] [get_bd_intf_pins hbm_bandwidth_53/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_54_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_54] [get_bd_intf_pins hbm_bandwidth_54/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_55_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_55] [get_bd_intf_pins hbm_bandwidth_55/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_56_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_56] [get_bd_intf_pins hbm_bandwidth_56/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_57_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_57] [get_bd_intf_pins hbm_bandwidth_57/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_58_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_58] [get_bd_intf_pins hbm_bandwidth_58/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_59_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_59] [get_bd_intf_pins hbm_bandwidth_59/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_5_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_05] [get_bd_intf_pins hbm_bandwidth_5/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_60_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_60] [get_bd_intf_pins hbm_bandwidth_60/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_61_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_61] [get_bd_intf_pins hbm_bandwidth_61/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_62_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_62] [get_bd_intf_pins hbm_bandwidth_62/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_63_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_63] [get_bd_intf_pins hbm_bandwidth_63/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_64_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_64/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_00/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_65_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_65/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_01/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_66_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_66/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_02/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_67_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_67/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_03/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_68_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_68/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_04/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_69_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_69/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_05/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_6_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_06] [get_bd_intf_pins hbm_bandwidth_6/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_70_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_70/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_06/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_71_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_71/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_07/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_72_m_axi_gmem1 [get_bd_intf_ports QDMA_SLAVE_BRIDGE] [get_bd_intf_pins traffic_virt_4/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_7_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_07] [get_bd_intf_pins hbm_bandwidth_7/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_8_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_08] [get_bd_intf_pins hbm_bandwidth_8/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_bandwidth_9_m_axi_gmem0 [get_bd_intf_ports HBM_AXI_09] [get_bd_intf_pins hbm_bandwidth_9/m_axi_gmem0] + connect_bd_intf_net -intf_net hbm_vnoc_00_M00_INI [get_bd_intf_ports HBM_VNOC_INI_00] [get_bd_intf_pins hbm_vnoc_00/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_01_M00_INI [get_bd_intf_ports HBM_VNOC_INI_01] [get_bd_intf_pins hbm_vnoc_01/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_02_M00_INI [get_bd_intf_ports HBM_VNOC_INI_02] [get_bd_intf_pins hbm_vnoc_02/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_03_M00_INI [get_bd_intf_ports HBM_VNOC_INI_03] [get_bd_intf_pins hbm_vnoc_03/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_04_M00_INI [get_bd_intf_ports HBM_VNOC_INI_04] [get_bd_intf_pins hbm_vnoc_04/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_05_M00_INI [get_bd_intf_ports HBM_VNOC_INI_05] [get_bd_intf_pins hbm_vnoc_05/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_06_M00_INI [get_bd_intf_ports HBM_VNOC_INI_06] [get_bd_intf_pins hbm_vnoc_06/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_07_M00_INI [get_bd_intf_ports HBM_VNOC_INI_07] [get_bd_intf_pins hbm_vnoc_07/M00_INI] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins hbm_bandwidth_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins hbm_bandwidth_1/s_axi_control] [get_bd_intf_pins smartconnect_0/M01_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins hbm_bandwidth_2/s_axi_control] [get_bd_intf_pins smartconnect_0/M02_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins hbm_bandwidth_3/s_axi_control] [get_bd_intf_pins smartconnect_0/M03_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins hbm_bandwidth_4/s_axi_control] [get_bd_intf_pins smartconnect_0/M04_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins hbm_bandwidth_5/s_axi_control] [get_bd_intf_pins smartconnect_0/M05_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins hbm_bandwidth_6/s_axi_control] [get_bd_intf_pins smartconnect_0/M06_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins hbm_bandwidth_7/s_axi_control] [get_bd_intf_pins smartconnect_0/M07_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M08_AXI [get_bd_intf_pins hbm_bandwidth_8/s_axi_control] [get_bd_intf_pins smartconnect_0/M08_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M09_AXI [get_bd_intf_pins hbm_bandwidth_9/s_axi_control] [get_bd_intf_pins smartconnect_0/M09_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M10_AXI [get_bd_intf_pins hbm_bandwidth_10/s_axi_control] [get_bd_intf_pins smartconnect_0/M10_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M11_AXI [get_bd_intf_pins hbm_bandwidth_11/s_axi_control] [get_bd_intf_pins smartconnect_0/M11_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M12_AXI [get_bd_intf_pins hbm_bandwidth_12/s_axi_control] [get_bd_intf_pins smartconnect_0/M12_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M13_AXI [get_bd_intf_pins hbm_bandwidth_13/s_axi_control] [get_bd_intf_pins smartconnect_0/M13_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M14_AXI [get_bd_intf_pins hbm_bandwidth_14/s_axi_control] [get_bd_intf_pins smartconnect_0/M14_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M15_AXI [get_bd_intf_pins smartconnect_0/M15_AXI] [get_bd_intf_pins smartconnect_1/S00_AXI] + connect_bd_intf_net -intf_net smartconnect_2_M00_AXI [get_bd_intf_pins smartconnect_1/M00_AXI] [get_bd_intf_pins hbm_bandwidth_15/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M01_AXI [get_bd_intf_pins smartconnect_1/M01_AXI] [get_bd_intf_pins hbm_bandwidth_16/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M02_AXI [get_bd_intf_pins smartconnect_1/M02_AXI] [get_bd_intf_pins hbm_bandwidth_17/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M03_AXI [get_bd_intf_pins smartconnect_1/M03_AXI] [get_bd_intf_pins hbm_bandwidth_18/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M04_AXI [get_bd_intf_pins smartconnect_1/M04_AXI] [get_bd_intf_pins hbm_bandwidth_19/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M05_AXI [get_bd_intf_pins smartconnect_1/M05_AXI] [get_bd_intf_pins hbm_bandwidth_20/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M06_AXI [get_bd_intf_pins smartconnect_1/M06_AXI] [get_bd_intf_pins hbm_bandwidth_21/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M07_AXI [get_bd_intf_pins smartconnect_1/M07_AXI] [get_bd_intf_pins hbm_bandwidth_22/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M08_AXI [get_bd_intf_pins smartconnect_1/M08_AXI] [get_bd_intf_pins hbm_bandwidth_23/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M09_AXI [get_bd_intf_pins smartconnect_1/M09_AXI] [get_bd_intf_pins hbm_bandwidth_24/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M10_AXI [get_bd_intf_pins smartconnect_1/M10_AXI] [get_bd_intf_pins hbm_bandwidth_25/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M11_AXI [get_bd_intf_pins smartconnect_1/M11_AXI] [get_bd_intf_pins hbm_bandwidth_26/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M12_AXI [get_bd_intf_pins smartconnect_1/M12_AXI] [get_bd_intf_pins hbm_bandwidth_27/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M13_AXI [get_bd_intf_pins smartconnect_1/M13_AXI] [get_bd_intf_pins hbm_bandwidth_28/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M14_AXI [get_bd_intf_pins smartconnect_1/M14_AXI] [get_bd_intf_pins hbm_bandwidth_29/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M15_AXI [get_bd_intf_pins smartconnect_1/M15_AXI] [get_bd_intf_pins smartconnect_2/S00_AXI] + connect_bd_intf_net -intf_net smartconnect_3_M00_AXI [get_bd_intf_pins smartconnect_2/M00_AXI] [get_bd_intf_pins hbm_bandwidth_30/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M01_AXI [get_bd_intf_pins smartconnect_2/M01_AXI] [get_bd_intf_pins hbm_bandwidth_31/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M02_AXI [get_bd_intf_pins smartconnect_2/M02_AXI] [get_bd_intf_pins hbm_bandwidth_32/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M03_AXI [get_bd_intf_pins smartconnect_2/M03_AXI] [get_bd_intf_pins hbm_bandwidth_33/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M04_AXI [get_bd_intf_pins smartconnect_2/M04_AXI] [get_bd_intf_pins hbm_bandwidth_34/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M05_AXI [get_bd_intf_pins smartconnect_2/M05_AXI] [get_bd_intf_pins hbm_bandwidth_35/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M06_AXI [get_bd_intf_pins smartconnect_2/M06_AXI] [get_bd_intf_pins hbm_bandwidth_36/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M07_AXI [get_bd_intf_pins smartconnect_2/M07_AXI] [get_bd_intf_pins hbm_bandwidth_37/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M08_AXI [get_bd_intf_pins smartconnect_2/M08_AXI] [get_bd_intf_pins hbm_bandwidth_38/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M09_AXI [get_bd_intf_pins smartconnect_2/M09_AXI] [get_bd_intf_pins hbm_bandwidth_39/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M10_AXI [get_bd_intf_pins smartconnect_2/M10_AXI] [get_bd_intf_pins hbm_bandwidth_40/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M11_AXI [get_bd_intf_pins smartconnect_2/M11_AXI] [get_bd_intf_pins hbm_bandwidth_41/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M12_AXI [get_bd_intf_pins smartconnect_2/M12_AXI] [get_bd_intf_pins hbm_bandwidth_42/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M13_AXI [get_bd_intf_pins smartconnect_2/M13_AXI] [get_bd_intf_pins hbm_bandwidth_43/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M14_AXI [get_bd_intf_pins smartconnect_2/M14_AXI] [get_bd_intf_pins hbm_bandwidth_44/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M15_AXI [get_bd_intf_pins smartconnect_3/S00_AXI] [get_bd_intf_pins smartconnect_2/M15_AXI] + connect_bd_intf_net -intf_net smartconnect_3_M15_AXI1 [get_bd_intf_pins smartconnect_3/M15_AXI] [get_bd_intf_pins smartconnect_4/S00_AXI] + connect_bd_intf_net -intf_net smartconnect_4_M00_AXI [get_bd_intf_pins smartconnect_3/M00_AXI] [get_bd_intf_pins hbm_bandwidth_45/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M00_AXI1 [get_bd_intf_pins smartconnect_4/M00_AXI] [get_bd_intf_pins hbm_bandwidth_60/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M01_AXI [get_bd_intf_pins smartconnect_3/M01_AXI] [get_bd_intf_pins hbm_bandwidth_46/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M01_AXI1 [get_bd_intf_pins smartconnect_4/M01_AXI] [get_bd_intf_pins hbm_bandwidth_61/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M02_AXI [get_bd_intf_pins smartconnect_3/M02_AXI] [get_bd_intf_pins hbm_bandwidth_47/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M02_AXI1 [get_bd_intf_pins smartconnect_4/M02_AXI] [get_bd_intf_pins hbm_bandwidth_62/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M03_AXI [get_bd_intf_pins smartconnect_3/M03_AXI] [get_bd_intf_pins hbm_bandwidth_48/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M03_AXI1 [get_bd_intf_pins smartconnect_4/M03_AXI] [get_bd_intf_pins hbm_bandwidth_63/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M04_AXI [get_bd_intf_pins smartconnect_3/M04_AXI] [get_bd_intf_pins hbm_bandwidth_49/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M04_AXI1 [get_bd_intf_pins smartconnect_4/M04_AXI] [get_bd_intf_pins hbm_bandwidth_64/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M05_AXI [get_bd_intf_pins smartconnect_3/M05_AXI] [get_bd_intf_pins hbm_bandwidth_50/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M05_AXI1 [get_bd_intf_pins smartconnect_4/M05_AXI] [get_bd_intf_pins hbm_bandwidth_65/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M06_AXI [get_bd_intf_pins smartconnect_3/M06_AXI] [get_bd_intf_pins hbm_bandwidth_51/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M06_AXI1 [get_bd_intf_pins smartconnect_4/M06_AXI] [get_bd_intf_pins hbm_bandwidth_66/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M07_AXI [get_bd_intf_pins smartconnect_3/M07_AXI] [get_bd_intf_pins hbm_bandwidth_52/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M07_AXI1 [get_bd_intf_pins smartconnect_4/M07_AXI] [get_bd_intf_pins hbm_bandwidth_67/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M08_AXI [get_bd_intf_pins smartconnect_3/M08_AXI] [get_bd_intf_pins hbm_bandwidth_53/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M08_AXI1 [get_bd_intf_pins smartconnect_4/M08_AXI] [get_bd_intf_pins hbm_bandwidth_68/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M09_AXI [get_bd_intf_pins smartconnect_3/M09_AXI] [get_bd_intf_pins hbm_bandwidth_54/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M09_AXI1 [get_bd_intf_pins smartconnect_4/M09_AXI] [get_bd_intf_pins hbm_bandwidth_69/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M10_AXI [get_bd_intf_pins smartconnect_3/M10_AXI] [get_bd_intf_pins hbm_bandwidth_55/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M10_AXI1 [get_bd_intf_pins smartconnect_4/M10_AXI] [get_bd_intf_pins hbm_bandwidth_70/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M11_AXI [get_bd_intf_pins smartconnect_3/M11_AXI] [get_bd_intf_pins hbm_bandwidth_56/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M11_AXI1 [get_bd_intf_pins smartconnect_4/M11_AXI] [get_bd_intf_pins hbm_bandwidth_71/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M12_AXI [get_bd_intf_pins smartconnect_3/M12_AXI] [get_bd_intf_pins hbm_bandwidth_57/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M12_AXI1 [get_bd_intf_pins smartconnect_4/M12_AXI] [get_bd_intf_pins ddr_bandwidth_64/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M13_AXI [get_bd_intf_pins smartconnect_3/M13_AXI] [get_bd_intf_pins hbm_bandwidth_58/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M13_AXI1 [get_bd_intf_pins smartconnect_4/M13_AXI] [get_bd_intf_pins ddr_bandwidth_65/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M14_AXI [get_bd_intf_pins smartconnect_3/M14_AXI] [get_bd_intf_pins hbm_bandwidth_59/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M14_AXI1 [get_bd_intf_pins smartconnect_4/M14_AXI] [get_bd_intf_pins ddr_bandwidth_66/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M15_AXI [get_bd_intf_pins smartconnect_5/S00_AXI] [get_bd_intf_pins smartconnect_4/M15_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M00_AXI [get_bd_intf_pins smartconnect_5/M00_AXI] [get_bd_intf_pins ddr_bandwidth_67/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_5_M01_AXI [get_bd_intf_pins traffic_producer_0/s_axi_control] [get_bd_intf_pins smartconnect_5/M01_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M02_AXI [get_bd_intf_pins traffic_producer_1/s_axi_control] [get_bd_intf_pins smartconnect_5/M02_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M03_AXI [get_bd_intf_pins traffic_producer_2/s_axi_control] [get_bd_intf_pins smartconnect_5/M03_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M04_AXI [get_bd_intf_pins traffic_producer_3/s_axi_control] [get_bd_intf_pins smartconnect_5/M04_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M05_AXI [get_bd_intf_pins traffic_producer_4/s_axi_control] [get_bd_intf_pins smartconnect_5/M05_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M06_AXI [get_bd_intf_pins traffic_producer_5/s_axi_control] [get_bd_intf_pins smartconnect_5/M06_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M07_AXI [get_bd_intf_pins traffic_producer_6/s_axi_control] [get_bd_intf_pins smartconnect_5/M07_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M08_AXI [get_bd_intf_pins traffic_producer_7/s_axi_control] [get_bd_intf_pins smartconnect_5/M08_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M09_AXI [get_bd_intf_pins traffic_virt_0/s_axi_control] [get_bd_intf_pins smartconnect_5/M09_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M10_AXI [get_bd_intf_pins traffic_virt_1/s_axi_control] [get_bd_intf_pins smartconnect_5/M10_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M11_AXI [get_bd_intf_pins traffic_virt_2/s_axi_control] [get_bd_intf_pins smartconnect_5/M11_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M12_AXI [get_bd_intf_pins traffic_virt_3/s_axi_control] [get_bd_intf_pins smartconnect_5/M12_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M13_AXI [get_bd_intf_pins traffic_virt_4/s_axi_control] [get_bd_intf_pins smartconnect_5/M13_AXI] + connect_bd_intf_net -intf_net traffic_producer_0_axis_out [get_bd_intf_pins traffic_producer_0/axis_out] [get_bd_intf_pins dcmac_axis_noc_0/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_1_axis_out [get_bd_intf_pins traffic_producer_1/axis_out] [get_bd_intf_pins dcmac_axis_noc_1/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_2_axis_out [get_bd_intf_pins traffic_producer_2/axis_out] [get_bd_intf_pins dcmac_axis_noc_2/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_3_axis_out [get_bd_intf_pins traffic_producer_3/axis_out] [get_bd_intf_pins dcmac_axis_noc_3/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_4_axis_out [get_bd_intf_pins traffic_producer_4/axis_out] [get_bd_intf_pins dcmac_axis_noc_4/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_5_axis_out [get_bd_intf_pins traffic_producer_5/axis_out] [get_bd_intf_pins dcmac_axis_noc_5/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_6_axis_out [get_bd_intf_pins traffic_producer_6/axis_out] [get_bd_intf_pins dcmac_axis_noc_6/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_7_axis_out [get_bd_intf_pins traffic_producer_7/axis_out] [get_bd_intf_pins dcmac_axis_noc_7/S00_AXIS] + connect_bd_intf_net -intf_net traffic_virt_0_m_axi_gmem0 [get_bd_intf_ports SL_VIRT_0] [get_bd_intf_pins traffic_virt_0/m_axi_gmem0] + connect_bd_intf_net -intf_net traffic_virt_1_m_axi_gmem0 [get_bd_intf_ports SL_VIRT_1] [get_bd_intf_pins traffic_virt_1/m_axi_gmem0] + connect_bd_intf_net -intf_net traffic_virt_2_m_axi_gmem0 [get_bd_intf_ports SL_VIRT_2] [get_bd_intf_pins traffic_virt_2/m_axi_gmem0] + connect_bd_intf_net -intf_net traffic_virt_3_m_axi_gmem0 [get_bd_intf_ports SL_VIRT_3] [get_bd_intf_pins traffic_virt_3/m_axi_gmem0] + + # Create port connections + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_ports aclk1] \ + [get_bd_pins smartconnect_0/aclk1] \ + [get_bd_pins ddr_noc_0/aclk0] \ + [get_bd_pins ddr_noc_3/aclk0] \ + [get_bd_pins ddr_noc_2/aclk0] \ + [get_bd_pins ddr_noc_1/aclk0] \ + [get_bd_pins hbm_vnoc_00/aclk0] \ + [get_bd_pins hbm_vnoc_01/aclk0] \ + [get_bd_pins hbm_vnoc_02/aclk0] \ + [get_bd_pins hbm_vnoc_03/aclk0] \ + [get_bd_pins hbm_vnoc_04/aclk0] \ + [get_bd_pins hbm_vnoc_05/aclk0] \ + [get_bd_pins hbm_vnoc_06/aclk0] \ + [get_bd_pins hbm_vnoc_07/aclk0] \ + [get_bd_pins dcmac_axis_noc_0/aclk0] \ + [get_bd_pins dcmac_axis_noc_1/aclk0] \ + [get_bd_pins dcmac_axis_noc_2/aclk0] \ + [get_bd_pins dcmac_axis_noc_3/aclk0] \ + [get_bd_pins dcmac_axis_noc_4/aclk0] \ + [get_bd_pins dcmac_axis_noc_5/aclk0] \ + [get_bd_pins dcmac_axis_noc_6/aclk0] \ + [get_bd_pins dcmac_axis_noc_7/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_0/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_1/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_2/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_3/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_4/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_5/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_6/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_7/aclk0] \ + [get_bd_pins traffic_producer_0/ap_clk] \ + [get_bd_pins traffic_producer_1/ap_clk] \ + [get_bd_pins traffic_producer_2/ap_clk] \ + [get_bd_pins traffic_producer_3/ap_clk] \ + [get_bd_pins traffic_producer_4/ap_clk] \ + [get_bd_pins traffic_producer_5/ap_clk] \ + [get_bd_pins traffic_producer_6/ap_clk] \ + [get_bd_pins traffic_producer_7/ap_clk] \ + [get_bd_pins ddr_bandwidth_64/ap_clk] \ + [get_bd_pins ddr_bandwidth_65/ap_clk] \ + [get_bd_pins ddr_bandwidth_66/ap_clk] \ + [get_bd_pins ddr_bandwidth_67/ap_clk] \ + [get_bd_pins hbm_bandwidth_0/ap_clk] \ + [get_bd_pins hbm_bandwidth_10/ap_clk] \ + [get_bd_pins hbm_bandwidth_11/ap_clk] \ + [get_bd_pins hbm_bandwidth_12/ap_clk] \ + [get_bd_pins hbm_bandwidth_13/ap_clk] \ + [get_bd_pins hbm_bandwidth_14/ap_clk] \ + [get_bd_pins hbm_bandwidth_15/ap_clk] \ + [get_bd_pins hbm_bandwidth_16/ap_clk] \ + [get_bd_pins hbm_bandwidth_17/ap_clk] \ + [get_bd_pins hbm_bandwidth_18/ap_clk] \ + [get_bd_pins hbm_bandwidth_19/ap_clk] \ + [get_bd_pins hbm_bandwidth_1/ap_clk] \ + [get_bd_pins hbm_bandwidth_20/ap_clk] \ + [get_bd_pins hbm_bandwidth_21/ap_clk] \ + [get_bd_pins hbm_bandwidth_22/ap_clk] \ + [get_bd_pins hbm_bandwidth_23/ap_clk] \ + [get_bd_pins hbm_bandwidth_24/ap_clk] \ + [get_bd_pins hbm_bandwidth_25/ap_clk] \ + [get_bd_pins hbm_bandwidth_26/ap_clk] \ + [get_bd_pins hbm_bandwidth_27/ap_clk] \ + [get_bd_pins hbm_bandwidth_28/ap_clk] \ + [get_bd_pins hbm_bandwidth_29/ap_clk] \ + [get_bd_pins hbm_bandwidth_2/ap_clk] \ + [get_bd_pins hbm_bandwidth_30/ap_clk] \ + [get_bd_pins hbm_bandwidth_31/ap_clk] \ + [get_bd_pins hbm_bandwidth_32/ap_clk] \ + [get_bd_pins hbm_bandwidth_33/ap_clk] \ + [get_bd_pins hbm_bandwidth_34/ap_clk] \ + [get_bd_pins hbm_bandwidth_35/ap_clk] \ + [get_bd_pins hbm_bandwidth_36/ap_clk] \ + [get_bd_pins hbm_bandwidth_37/ap_clk] \ + [get_bd_pins hbm_bandwidth_38/ap_clk] \ + [get_bd_pins hbm_bandwidth_39/ap_clk] \ + [get_bd_pins hbm_bandwidth_3/ap_clk] \ + [get_bd_pins hbm_bandwidth_40/ap_clk] \ + [get_bd_pins hbm_bandwidth_41/ap_clk] \ + [get_bd_pins hbm_bandwidth_42/ap_clk] \ + [get_bd_pins hbm_bandwidth_43/ap_clk] \ + [get_bd_pins hbm_bandwidth_44/ap_clk] \ + [get_bd_pins hbm_bandwidth_45/ap_clk] \ + [get_bd_pins hbm_bandwidth_46/ap_clk] \ + [get_bd_pins hbm_bandwidth_47/ap_clk] \ + [get_bd_pins hbm_bandwidth_48/ap_clk] \ + [get_bd_pins hbm_bandwidth_49/ap_clk] \ + [get_bd_pins hbm_bandwidth_4/ap_clk] \ + [get_bd_pins hbm_bandwidth_50/ap_clk] \ + [get_bd_pins hbm_bandwidth_51/ap_clk] \ + [get_bd_pins hbm_bandwidth_52/ap_clk] \ + [get_bd_pins hbm_bandwidth_53/ap_clk] \ + [get_bd_pins hbm_bandwidth_54/ap_clk] \ + [get_bd_pins hbm_bandwidth_55/ap_clk] \ + [get_bd_pins hbm_bandwidth_56/ap_clk] \ + [get_bd_pins hbm_bandwidth_57/ap_clk] \ + [get_bd_pins hbm_bandwidth_58/ap_clk] \ + [get_bd_pins hbm_bandwidth_59/ap_clk] \ + [get_bd_pins hbm_bandwidth_5/ap_clk] \ + [get_bd_pins hbm_bandwidth_60/ap_clk] \ + [get_bd_pins hbm_bandwidth_61/ap_clk] \ + [get_bd_pins hbm_bandwidth_62/ap_clk] \ + [get_bd_pins hbm_bandwidth_63/ap_clk] \ + [get_bd_pins hbm_bandwidth_64/ap_clk] \ + [get_bd_pins hbm_bandwidth_65/ap_clk] \ + [get_bd_pins hbm_bandwidth_66/ap_clk] \ + [get_bd_pins hbm_bandwidth_67/ap_clk] \ + [get_bd_pins hbm_bandwidth_68/ap_clk] \ + [get_bd_pins hbm_bandwidth_69/ap_clk] \ + [get_bd_pins hbm_bandwidth_6/ap_clk] \ + [get_bd_pins hbm_bandwidth_70/ap_clk] \ + [get_bd_pins hbm_bandwidth_71/ap_clk] \ + [get_bd_pins hbm_bandwidth_7/ap_clk] \ + [get_bd_pins hbm_bandwidth_8/ap_clk] \ + [get_bd_pins hbm_bandwidth_9/ap_clk] \ + [get_bd_pins traffic_virt_0/ap_clk] \ + [get_bd_pins traffic_virt_1/ap_clk] \ + [get_bd_pins traffic_virt_2/ap_clk] \ + [get_bd_pins traffic_virt_3/ap_clk] \ + [get_bd_pins traffic_virt_4/ap_clk] \ + [get_bd_pins smartconnect_1/aclk1] \ + [get_bd_pins smartconnect_2/aclk1] \ + [get_bd_pins smartconnect_3/aclk1] \ + [get_bd_pins smartconnect_4/aclk1] \ + [get_bd_pins smartconnect_5/aclk1] \ + [get_bd_pins axi_noc_0/aclk0] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_ports ap_rst_n] \ + [get_bd_pins traffic_producer_0/ap_rst_n] \ + [get_bd_pins traffic_producer_1/ap_rst_n] \ + [get_bd_pins traffic_producer_2/ap_rst_n] \ + [get_bd_pins traffic_producer_3/ap_rst_n] \ + [get_bd_pins traffic_producer_4/ap_rst_n] \ + [get_bd_pins traffic_producer_5/ap_rst_n] \ + [get_bd_pins traffic_producer_6/ap_rst_n] \ + [get_bd_pins traffic_producer_7/ap_rst_n] \ + [get_bd_pins ddr_bandwidth_64/ap_rst_n] \ + [get_bd_pins ddr_bandwidth_65/ap_rst_n] \ + [get_bd_pins ddr_bandwidth_66/ap_rst_n] \ + [get_bd_pins ddr_bandwidth_67/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_0/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_10/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_11/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_12/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_13/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_14/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_15/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_16/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_17/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_18/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_19/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_1/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_20/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_21/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_22/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_23/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_24/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_25/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_26/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_27/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_28/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_29/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_2/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_30/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_31/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_32/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_33/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_34/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_35/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_36/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_37/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_38/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_39/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_3/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_40/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_41/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_42/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_43/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_44/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_45/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_46/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_47/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_48/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_49/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_4/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_50/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_51/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_52/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_53/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_54/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_55/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_56/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_57/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_58/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_59/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_5/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_60/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_61/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_62/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_63/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_64/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_65/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_66/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_67/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_68/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_69/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_6/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_70/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_71/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_7/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_8/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_9/ap_rst_n] \ + [get_bd_pins traffic_virt_0/ap_rst_n] \ + [get_bd_pins traffic_virt_1/ap_rst_n] \ + [get_bd_pins traffic_virt_2/ap_rst_n] \ + [get_bd_pins traffic_virt_3/ap_rst_n] \ + [get_bd_pins traffic_virt_4/ap_rst_n] + connect_bd_net -net reset_rtl_0_1 [get_bd_ports arstn] \ + [get_bd_pins smartconnect_0/aresetn] \ + [get_bd_pins smartconnect_1/aresetn] \ + [get_bd_pins smartconnect_2/aresetn] \ + [get_bd_pins smartconnect_3/aresetn] \ + [get_bd_pins smartconnect_4/aresetn] \ + [get_bd_pins smartconnect_5/aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_ports s_axi_aclk] \ + [get_bd_pins smartconnect_0/aclk] \ + [get_bd_pins smartconnect_1/aclk] \ + [get_bd_pins smartconnect_2/aclk] \ + [get_bd_pins smartconnect_3/aclk] \ + [get_bd_pins smartconnect_4/aclk] \ + [get_bd_pins smartconnect_5/aclk] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] \ + [get_bd_pins dcmac_axis_noc_s_0/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_1/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_2/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_3/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_4/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_5/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_6/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_7/M00_AXIS_tready] + + # Create address segments + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ddr_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs M00_INI/Reg] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ddr_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs M01_INI/Reg] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ddr_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs M02_INI/Reg] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ddr_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs M03_INI/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM0_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_0/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_00/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM0_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_1/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_01/Reg] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM2_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_10/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_10/Reg] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM2_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_11/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_11/Reg] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM3_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_12/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_12/Reg] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM3_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_13/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_13/Reg] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM3_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_14/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_14/Reg] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM3_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_15/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_15/Reg] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM4_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_16/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_16/Reg] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM4_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_17/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_17/Reg] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM4_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_18/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_18/Reg] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM4_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_19/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_19/Reg] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM0_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_2/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_02/Reg] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM5_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_20/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_20/Reg] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM5_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_21/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_21/Reg] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM5_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_22/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_22/Reg] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM5_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_23/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_23/Reg] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM6_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_24/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_24/Reg] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM6_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_25/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_25/Reg] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM6_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_26/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_26/Reg] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM6_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_27/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_27/Reg] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM7_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_28/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_28/Reg] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM7_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_29/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_29/Reg] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM0_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_3/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_03/Reg] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM7_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_30/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_30/Reg] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM7_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_31/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_31/Reg] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM8_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_32/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_32/Reg] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM8_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_33/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_33/Reg] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM8_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_34/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_34/Reg] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM8_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_35/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_35/Reg] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM9_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_36/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_36/Reg] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM9_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_37/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_37/Reg] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM9_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_38/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_38/Reg] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM9_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_39/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_39/Reg] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM1_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_4/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_04/Reg] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM10_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_40/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_40/Reg] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM10_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_41/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_41/Reg] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM10_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_42/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_42/Reg] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM10_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_43/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_43/Reg] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM11_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_44/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_44/Reg] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM11_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_45/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_45/Reg] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM11_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_46/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_46/Reg] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM11_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_47/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_47/Reg] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM12_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_48/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_48/Reg] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM12_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_49/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_49/Reg] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM1_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_5/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_05/Reg] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM12_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_50/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_50/Reg] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM12_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_51/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_51/Reg] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM13_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_52/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_52/Reg] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM13_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_53/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_53/Reg] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM13_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_54/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_54/Reg] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM13_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_55/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_55/Reg] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM14_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_56/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_56/Reg] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM14_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_57/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_57/Reg] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM14_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_58/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_58/Reg] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM14_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_59/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_59/Reg] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM1_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_6/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_06/Reg] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM15_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_60/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_60/Reg] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM15_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_61/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_61/Reg] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM15_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_62/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_62/Reg] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM15_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_63/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_63/Reg] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM1_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_7/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_07/Reg] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM2_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_8/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_08/Reg] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM2_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_9/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_09/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_00/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_01/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_02/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_03/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_04/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_05/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_06/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_07/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -with_name SEG_SL_0_Reg -target_address_space [get_bd_addr_spaces traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs SL_VIRT_0/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -with_name SEG_SL_1_Reg -target_address_space [get_bd_addr_spaces traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs SL_VIRT_1/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -with_name SEG_SL_2_Reg -target_address_space [get_bd_addr_spaces traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs SL_VIRT_2/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -with_name SEG_SL_3_Reg -target_address_space [get_bd_addr_spaces traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs SL_VIRT_3/Reg] -force + assign_bd_address -offset 0x44A00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces traffic_virt_4/Data_m_axi_gmem0] [get_bd_addr_segs QDMA_SLAVE_BRIDGE/Reg] -force + assign_bd_address -offset 0x020200480000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ddr_bandwidth_64/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200490000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ddr_bandwidth_65/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ddr_bandwidth_66/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ddr_bandwidth_67/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_10/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_11/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_12/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_13/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_14/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_15/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_16/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_17/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_18/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_19/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_20/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200150000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_21/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200160000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_22/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200170000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_23/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200180000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_24/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200190000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_25/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_26/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_27/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_28/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_29/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_30/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_31/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_32/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_33/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_34/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_35/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_36/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_37/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_38/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200270000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_39/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200280000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_40/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200290000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_41/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_42/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_43/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_44/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_45/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_46/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_47/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_48/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200300000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_49/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200320000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_50/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200330000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_51/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200340000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_52/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200350000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_53/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200360000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_54/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200370000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_55/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200380000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_56/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200390000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_57/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_58/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_59/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_60/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_61/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_62/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_63/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_64/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200410000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_65/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200420000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_66/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200430000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_67/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200440000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_68/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200450000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_69/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200460000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_70/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200470000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_71/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_8/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_9/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200500000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200510000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200520000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200530000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200540000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_virt_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200550000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_virt_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200560000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_virt_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200570000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_virt_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200580000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_virt_4/s_axi_control/Reg] -force + + set_property USAGE memory [get_bd_addr_segs HBM_AXI_00/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_01/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_10/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_11/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_12/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_13/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_14/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_15/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_16/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_17/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_18/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_19/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_02/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_20/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_21/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_22/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_23/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_24/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_25/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_26/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_27/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_28/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_29/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_03/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_30/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_31/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_32/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_33/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_34/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_35/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_36/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_37/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_38/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_39/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_04/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_40/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_41/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_42/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_43/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_44/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_45/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_46/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_47/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_48/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_49/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_05/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_50/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_51/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_52/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_53/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_54/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_55/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_56/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_57/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_58/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_59/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_06/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_60/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_61/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_62/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_63/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_07/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_08/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_09/Reg] + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/linker/resources/base/scripts/top.tcl b/linker/resources/base/scripts/top.tcl new file mode 100644 index 00000000..0e9419e1 --- /dev/null +++ b/linker/resources/base/scripts/top.tcl @@ -0,0 +1,5267 @@ + +################################################################ +# This is a generated script based on design: top +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2024.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."} + + } else { + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + } + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source top_script.tcl + + +# The design that will be created by this Tcl script contains the following +# block design container source references: +# slash_base, slash_user, service_layer, service_layer_user + +# Please add the sources before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xcv80-lsva4737-2MHP-e-S +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name top + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:clk_wizard:1.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:dfx_decoupler:1.0\ +xilinx.com:ip:axi_noc:1.1\ +xilinx.com:ip:axi_register_slice:2.1\ +xilinx.com:ip:util_vector_logic:2.0\ +xilinx.com:ip:versal_cips:3.4\ +xilinx.com:ip:axis_noc:1.0\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:ip:hw_discovery:1.0\ +xilinx.com:ip:shell_utils_uuid_rom:2.0\ +xilinx.com:ip:smbus:1.1\ +xilinx.com:ip:cmd_queue:2.0\ +xilinx.com:ip:axi_gpio:2.0\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:util_reduced_logic:2.0\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Block Design Container Sources +################################################################## +set bCheckSources 0 +set list_bdc_active "slash_base, service_layer" +set list_bdc_dfx "slash_user, service_layer_user" + +array set map_bdc_missing {} +set map_bdc_missing(ACTIVE) "" +set map_bdc_missing(DFX) "" +set map_bdc_missing(BDC) "" + +if { $bCheckSources == 1 } { + set list_check_srcs "\ +slash_base \ +slash_user \ +service_layer \ +service_layer_user \ +" + + common::send_gid_msg -ssname BD::TCL -id 2056 -severity "INFO" "Checking if the following sources for block design container exist in the project: $list_check_srcs .\n\n" + + foreach src $list_check_srcs { + if { [can_resolve_reference $src] == 0 } { + if { [lsearch $list_bdc_active $src] != -1 } { + set map_bdc_missing(ACTIVE) "$map_bdc_missing(ACTIVE) $src" + } elseif { [lsearch $list_bdc_dfx $src] != -1 } { + set map_bdc_missing(DFX) "$map_bdc_missing(DFX) $src" + } else { + set map_bdc_missing(BDC) "$map_bdc_missing(BDC) $src" + } + } + } + + if { [llength $map_bdc_missing(ACTIVE)] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2057 -severity "ERROR" "The following source(s) of Active variants are not found in the project: $map_bdc_missing(ACTIVE)" } + common::send_gid_msg -ssname BD::TCL -id 2060 -severity "INFO" "Please add source files for the missing source(s) above." + set bCheckIPsPassed 0 + } + if { [llength $map_bdc_missing(DFX)] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2058 -severity "ERROR" "The following source(s) of DFX variants are not found in the project: $map_bdc_missing(DFX)" } + common::send_gid_msg -ssname BD::TCL -id 2060 -severity "INFO" "Please add source files for the missing source(s) above." + set bCheckIPsPassed 0 + } + if { [llength $map_bdc_missing(BDC)] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2059 -severity "WARNING" "The following source(s) of variants are not found in the project: $map_bdc_missing(BDC)" } + common::send_gid_msg -ssname BD::TCL -id 2060 -severity "INFO" "Please add source files for the missing source(s) above." + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: pcie_mgmt_pdi_reset +proc create_hier_cell_pcie_mgmt_pdi_reset { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_pcie_mgmt_pdi_reset() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + + # Create pins + create_bd_pin -dir I -type clk clk + create_bd_pin -dir I -type rst resetn + create_bd_pin -dir I -type rst resetn_in + + # Create instance: pcie_mgmt_pdi_reset_gpio, and set properties + set pcie_mgmt_pdi_reset_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 pcie_mgmt_pdi_reset_gpio ] + set_property -dict [list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT {0x00000000} \ + CONFIG.C_GPIO2_WIDTH {1} \ + CONFIG.C_GPIO_WIDTH {1} \ + CONFIG.C_IS_DUAL {1} \ + ] $pcie_mgmt_pdi_reset_gpio + + + # Create instance: inv, and set properties + set inv [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 inv ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $inv + + + # Create instance: ccat, and set properties + set ccat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 ccat ] + + # Create instance: and_0, and set properties + set and_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 and_0 ] + set_property CONFIG.C_SIZE {2} $and_0 + + + # Create interface connections + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins pcie_mgmt_pdi_reset_gpio/S_AXI] + + # Create port connections + connect_bd_net -net and_0_Res [get_bd_pins and_0/Res] \ + [get_bd_pins pcie_mgmt_pdi_reset_gpio/gpio2_io_i] + connect_bd_net -net ccat_dout [get_bd_pins ccat/dout] \ + [get_bd_pins and_0/Op1] + connect_bd_net -net clk_1 [get_bd_pins clk] \ + [get_bd_pins pcie_mgmt_pdi_reset_gpio/s_axi_aclk] + connect_bd_net -net inv_Res [get_bd_pins inv/Res] \ + [get_bd_pins ccat/In1] + connect_bd_net -net pcie_mgmt_pdi_reset_gpio_gpio_io_o [get_bd_pins pcie_mgmt_pdi_reset_gpio/gpio_io_o] \ + [get_bd_pins ccat/In0] + connect_bd_net -net resetn_1 [get_bd_pins resetn] \ + [get_bd_pins pcie_mgmt_pdi_reset_gpio/s_axi_aresetn] + connect_bd_net -net resetn_in_1 [get_bd_pins resetn_in] \ + [get_bd_pins inv/Op1] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: base_logic +proc create_hier_cell_base_logic { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_base_logic() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_pcie_mgmt_slr0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rpu + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:pcie3_cfg_ext_rtl:1.0 pcie_cfg_ext + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 smbus_rpu + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_pcie_mgmt_pdi_reset + + + # Create pins + create_bd_pin -dir I -type clk clk_pcie + create_bd_pin -dir I -type clk clk_pl + create_bd_pin -dir I -type rst resetn_pcie_periph + create_bd_pin -dir I -type rst resetn_pl_periph + create_bd_pin -dir I -type rst resetn_pl_ic + create_bd_pin -dir O -type intr irq_gcq_m2r + create_bd_pin -dir O -type intr irq_axi_smbus_rpu + + # Create instance: pcie_slr0_mgmt_sc, and set properties + set pcie_slr0_mgmt_sc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 pcie_slr0_mgmt_sc ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {4} \ + CONFIG.NUM_SI {1} \ + ] $pcie_slr0_mgmt_sc + + + # Create instance: rpu_sc, and set properties + set rpu_sc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 rpu_sc ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_SI {1} \ + ] $rpu_sc + + + # Create instance: hw_discovery, and set properties + set hw_discovery [ create_bd_cell -type ip -vlnv xilinx.com:ip:hw_discovery:1.0 hw_discovery ] + set_property -dict [list \ + CONFIG.C_CAP_BASE_ADDR {0x600} \ + CONFIG.C_INJECT_ENDPOINTS {0} \ + CONFIG.C_MANUAL {1} \ + CONFIG.C_NEXT_CAP_ADDR {0x000} \ + CONFIG.C_NUM_PFS {1} \ + CONFIG.C_PF0_BAR_INDEX {0} \ + CONFIG.C_PF0_ENDPOINT_NAMES {0} \ + CONFIG.C_PF0_ENTRY_ADDR_0 {0x000001001000} \ + CONFIG.C_PF0_ENTRY_ADDR_1 {0x000001010000} \ + CONFIG.C_PF0_ENTRY_ADDR_2 {0x000008000000} \ + CONFIG.C_PF0_ENTRY_BAR_0 {0} \ + CONFIG.C_PF0_ENTRY_BAR_1 {0} \ + CONFIG.C_PF0_ENTRY_BAR_2 {0} \ + CONFIG.C_PF0_ENTRY_MAJOR_VERSION_0 {1} \ + CONFIG.C_PF0_ENTRY_MAJOR_VERSION_1 {1} \ + CONFIG.C_PF0_ENTRY_MAJOR_VERSION_2 {1} \ + CONFIG.C_PF0_ENTRY_MINOR_VERSION_0 {0} \ + CONFIG.C_PF0_ENTRY_MINOR_VERSION_1 {2} \ + CONFIG.C_PF0_ENTRY_MINOR_VERSION_2 {0} \ + CONFIG.C_PF0_ENTRY_RSVD0_0 {0x0} \ + CONFIG.C_PF0_ENTRY_RSVD0_1 {0x0} \ + CONFIG.C_PF0_ENTRY_RSVD0_2 {0x0} \ + CONFIG.C_PF0_ENTRY_TYPE_0 {0x50} \ + CONFIG.C_PF0_ENTRY_TYPE_1 {0x54} \ + CONFIG.C_PF0_ENTRY_TYPE_2 {0x55} \ + CONFIG.C_PF0_ENTRY_VERSION_TYPE_0 {0x01} \ + CONFIG.C_PF0_ENTRY_VERSION_TYPE_1 {0x01} \ + CONFIG.C_PF0_ENTRY_VERSION_TYPE_2 {0x01} \ + CONFIG.C_PF0_HIGH_OFFSET {0x00000000} \ + CONFIG.C_PF0_LOW_OFFSET {0x0100000} \ + CONFIG.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE {3} \ + CONFIG.C_PF0_S_AXI_ADDR_WIDTH {32} \ + ] $hw_discovery + + + # Create instance: uuid_rom, and set properties + set uuid_rom [ create_bd_cell -type ip -vlnv xilinx.com:ip:shell_utils_uuid_rom:2.0 uuid_rom ] + set_property CONFIG.C_INITIAL_UUID {00000000000000000000000000000000} $uuid_rom + + + # Create instance: axi_smbus_rpu, and set properties + set axi_smbus_rpu [ create_bd_cell -type ip -vlnv xilinx.com:ip:smbus:1.1 axi_smbus_rpu ] + set_property -dict [list \ + CONFIG.NUM_TARGET_DEVICES {8} \ + CONFIG.SMBUS_DEV_CLASS {0} \ + ] $axi_smbus_rpu + + + # Create instance: gcq_m2r, and set properties + set gcq_m2r [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmd_queue:2.0 gcq_m2r ] + + # Create interface connections + connect_bd_intf_net -intf_net axi_smbus_rpu_SMBUS [get_bd_intf_pins axi_smbus_rpu/SMBUS] [get_bd_intf_pins smbus_rpu] + connect_bd_intf_net -intf_net pcie_cfg_ext_1 [get_bd_intf_pins pcie_cfg_ext] [get_bd_intf_pins hw_discovery/s_pcie4_cfg_ext] + connect_bd_intf_net -intf_net pcie_slr0_mgmt_sc_M00_AXI [get_bd_intf_pins pcie_slr0_mgmt_sc/M00_AXI] [get_bd_intf_pins hw_discovery/s_axi_ctrl_pf0] + connect_bd_intf_net -intf_net pcie_slr0_mgmt_sc_M01_AXI [get_bd_intf_pins pcie_slr0_mgmt_sc/M01_AXI] [get_bd_intf_pins uuid_rom/S_AXI] + connect_bd_intf_net -intf_net pcie_slr0_mgmt_sc_M02_AXI [get_bd_intf_pins pcie_slr0_mgmt_sc/M02_AXI] [get_bd_intf_pins gcq_m2r/S00_AXI] + connect_bd_intf_net -intf_net pcie_slr0_mgmt_sc_M03_AXI [get_bd_intf_pins pcie_slr0_mgmt_sc/M03_AXI] [get_bd_intf_pins m_axi_pcie_mgmt_pdi_reset] + connect_bd_intf_net -intf_net rpu_sc_M00_AXI [get_bd_intf_pins rpu_sc/M00_AXI] [get_bd_intf_pins gcq_m2r/S01_AXI] + connect_bd_intf_net -intf_net rpu_sc_M01_AXI [get_bd_intf_pins axi_smbus_rpu/S_AXI] [get_bd_intf_pins rpu_sc/M01_AXI] + connect_bd_intf_net -intf_net s_axi_pcie_mgmt_slr0_1 [get_bd_intf_pins s_axi_pcie_mgmt_slr0] [get_bd_intf_pins pcie_slr0_mgmt_sc/S00_AXI] + connect_bd_intf_net -intf_net s_axi_rpu_1 [get_bd_intf_pins s_axi_rpu] [get_bd_intf_pins rpu_sc/S00_AXI] + + # Create port connections + connect_bd_net -net axi_smbus_rpu_ip2intc_irpt [get_bd_pins axi_smbus_rpu/ip2intc_irpt] \ + [get_bd_pins irq_axi_smbus_rpu] + connect_bd_net -net clk_pcie_1 [get_bd_pins clk_pcie] \ + [get_bd_pins hw_discovery/aclk_pcie] + connect_bd_net -net clk_pl_1 [get_bd_pins clk_pl] \ + [get_bd_pins pcie_slr0_mgmt_sc/aclk] \ + [get_bd_pins rpu_sc/aclk] \ + [get_bd_pins hw_discovery/aclk_ctrl] \ + [get_bd_pins uuid_rom/S_AXI_ACLK] \ + [get_bd_pins gcq_m2r/aclk] \ + [get_bd_pins axi_smbus_rpu/s_axi_aclk] + connect_bd_net -net gcq_m2r_irq_sq [get_bd_pins gcq_m2r/irq_sq] \ + [get_bd_pins irq_gcq_m2r] + connect_bd_net -net resetn_pcie_periph_1 [get_bd_pins resetn_pcie_periph] \ + [get_bd_pins hw_discovery/aresetn_pcie] + connect_bd_net -net resetn_pl_ic_1 [get_bd_pins resetn_pl_ic] \ + [get_bd_pins pcie_slr0_mgmt_sc/aresetn] \ + [get_bd_pins rpu_sc/aresetn] + connect_bd_net -net resetn_pl_periph_1 [get_bd_pins resetn_pl_periph] \ + [get_bd_pins hw_discovery/aresetn_ctrl] \ + [get_bd_pins uuid_rom/S_AXI_ARESETN] \ + [get_bd_pins gcq_m2r/aresetn] \ + [get_bd_pins axi_smbus_rpu/s_axi_aresetn] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: clock_reset +proc create_hier_cell_clock_reset { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_clock_reset() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_pcie_mgmt_pdi_reset + + + # Create pins + create_bd_pin -dir I -type clk clk_pl + create_bd_pin -dir I -type clk clk_freerun + create_bd_pin -dir I -type clk clk_pcie + create_bd_pin -dir I -type rst dma_axi_aresetn + create_bd_pin -dir I -type rst resetn_pl_axi + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pcie_ic + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pcie_periph + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pl_ic + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pl_periph + create_bd_pin -dir O -type clk clk_usr_0 + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_usr_0_ic + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_usr_0_periph + create_bd_pin -dir O -type clk clk_usr_1 + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_usr_1_ic + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_usr_1_periph + + # Create instance: pcie_psr, and set properties + set pcie_psr [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 pcie_psr ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $pcie_psr + + + # Create instance: pl_psr, and set properties + set pl_psr [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 pl_psr ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $pl_psr + + + # Create instance: usr_clk_wiz, and set properties + set usr_clk_wiz [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard:1.0 usr_clk_wiz ] + set_property -dict [list \ + CONFIG.CLKOUT_DRIVES {No_buffer,No_buffer} \ + CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY {300,500} \ + CONFIG.CLKOUT_USED {true,true} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.USE_DYN_RECONFIG {false} \ + CONFIG.USE_LOCKED {true} \ + CONFIG.USE_POWER_DOWN {false} \ + CONFIG.USE_RESET {false} \ + ] $usr_clk_wiz + + + # Create instance: usr_0_psr, and set properties + set usr_0_psr [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 usr_0_psr ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $usr_0_psr + + + # Create instance: usr_1_psr, and set properties + set usr_1_psr [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 usr_1_psr ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $usr_1_psr + + + # Create instance: pcie_mgmt_pdi_reset + create_hier_cell_pcie_mgmt_pdi_reset $hier_obj pcie_mgmt_pdi_reset + + # Create interface connections + connect_bd_intf_net -intf_net s_axi_pcie_mgmt_pdi_reset_1 [get_bd_intf_pins s_axi_pcie_mgmt_pdi_reset] [get_bd_intf_pins pcie_mgmt_pdi_reset/s_axi] + + # Create port connections + connect_bd_net -net clk_freerun_1 [get_bd_pins clk_freerun] \ + [get_bd_pins usr_clk_wiz/clk_in1] + connect_bd_net -net clk_pcie_1 [get_bd_pins clk_pcie] \ + [get_bd_pins pcie_psr/slowest_sync_clk] + connect_bd_net -net clk_pl_1 [get_bd_pins clk_pl] \ + [get_bd_pins pl_psr/slowest_sync_clk] \ + [get_bd_pins pcie_mgmt_pdi_reset/clk] + connect_bd_net -net dma_axi_aresetn_1 [get_bd_pins dma_axi_aresetn] \ + [get_bd_pins pcie_mgmt_pdi_reset/resetn_in] + connect_bd_net -net pcie_psr_interconnect_aresetn [get_bd_pins pcie_psr/interconnect_aresetn] \ + [get_bd_pins resetn_pcie_ic] + connect_bd_net -net pcie_psr_peripheral_aresetn [get_bd_pins pcie_psr/peripheral_aresetn] \ + [get_bd_pins resetn_pcie_periph] + connect_bd_net -net pl_psr_interconnect_aresetn [get_bd_pins pl_psr/interconnect_aresetn] \ + [get_bd_pins resetn_pl_ic] \ + [get_bd_pins pcie_psr/ext_reset_in] \ + [get_bd_pins usr_0_psr/ext_reset_in] \ + [get_bd_pins usr_1_psr/ext_reset_in] + connect_bd_net -net pl_psr_peripheral_aresetn [get_bd_pins pl_psr/peripheral_aresetn] \ + [get_bd_pins resetn_pl_periph] \ + [get_bd_pins pcie_mgmt_pdi_reset/resetn] + connect_bd_net -net resetn_pl_axi_1 [get_bd_pins resetn_pl_axi] \ + [get_bd_pins pl_psr/ext_reset_in] + connect_bd_net -net usr_0_psr_interconnect_aresetn [get_bd_pins usr_0_psr/interconnect_aresetn] \ + [get_bd_pins resetn_usr_0_ic] + connect_bd_net -net usr_0_psr_peripheral_aresetn [get_bd_pins usr_0_psr/peripheral_aresetn] \ + [get_bd_pins resetn_usr_0_periph] + connect_bd_net -net usr_1_psr_interconnect_aresetn [get_bd_pins usr_1_psr/interconnect_aresetn] \ + [get_bd_pins resetn_usr_1_ic] + connect_bd_net -net usr_1_psr_peripheral_aresetn [get_bd_pins usr_1_psr/peripheral_aresetn] \ + [get_bd_pins resetn_usr_1_periph] + connect_bd_net -net usr_clk_wiz_clk_out1 [get_bd_pins usr_clk_wiz/clk_out1] \ + [get_bd_pins clk_usr_0] \ + [get_bd_pins usr_0_psr/slowest_sync_clk] + connect_bd_net -net usr_clk_wiz_clk_out2 [get_bd_pins usr_clk_wiz/clk_out2] \ + [get_bd_pins clk_usr_1] \ + [get_bd_pins usr_1_psr/slowest_sync_clk] + connect_bd_net -net usr_clk_wiz_locked [get_bd_pins usr_clk_wiz/locked] \ + [get_bd_pins usr_0_psr/dcm_locked] \ + [get_bd_pins usr_1_psr/dcm_locked] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: dcmac_noc +proc create_hier_cell_dcmac_noc { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_dcmac_noc() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS2 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS3 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS3 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS4 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS4 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS5 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS5 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS6 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS6 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS7 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS7 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS8 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS8 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS9 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS9 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS10 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS10 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS11 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS11 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS12 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS12 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS13 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS13 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS14 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS14 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS15 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS15 + + + # Create pins + + # Create instance: dcmac_service2slash_0, and set properties + set dcmac_service2slash_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_0/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_0/S00_INIS] + + # Create instance: dcmac_service2slash_1, and set properties + set dcmac_service2slash_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_1/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_1/S00_INIS] + + # Create instance: dcmac_service2slash_2, and set properties + set dcmac_service2slash_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_2/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_2/S00_INIS] + + # Create instance: dcmac_service2slash_3, and set properties + set dcmac_service2slash_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_3/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_3/S00_INIS] + + # Create instance: dcmac_service2slash_4, and set properties + set dcmac_service2slash_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_4/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_4/S00_INIS] + + # Create instance: dcmac_service2slash_5, and set properties + set dcmac_service2slash_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_5/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_5/S00_INIS] + + # Create instance: dcmac_service2slash_6, and set properties + set dcmac_service2slash_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_6/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_6/S00_INIS] + + # Create instance: dcmac_service2slash_7, and set properties + set dcmac_service2slash_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_7/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_7/S00_INIS] + + # Create instance: dcmac_slash2service_0, and set properties + set dcmac_slash2service_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_0/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_0/S00_INIS] + + # Create instance: dcmac_slash2service_1, and set properties + set dcmac_slash2service_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_1/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_1/S00_INIS] + + # Create instance: dcmac_slash2service_2, and set properties + set dcmac_slash2service_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_2/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_2/S00_INIS] + + # Create instance: dcmac_slash2service_3, and set properties + set dcmac_slash2service_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_3/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_3/S00_INIS] + + # Create instance: dcmac_slash2service_4, and set properties + set dcmac_slash2service_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_4/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_4/S00_INIS] + + # Create instance: dcmac_slash2service_5, and set properties + set dcmac_slash2service_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_5/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_5/S00_INIS] + + # Create instance: dcmac_slash2service_6, and set properties + set dcmac_slash2service_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_6/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_6/S00_INIS] + + # Create instance: dcmac_slash2service_7, and set properties + set dcmac_slash2service_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_7/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_7/S00_INIS] + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins dcmac_slash2service_0/S00_INIS] [get_bd_intf_pins S00_INIS] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins dcmac_slash2service_0/M00_INIS] [get_bd_intf_pins M00_INIS] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins dcmac_slash2service_1/S00_INIS] [get_bd_intf_pins S00_INIS1] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins dcmac_slash2service_1/M00_INIS] [get_bd_intf_pins M00_INIS1] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins dcmac_slash2service_2/S00_INIS] [get_bd_intf_pins S00_INIS2] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins dcmac_slash2service_2/M00_INIS] [get_bd_intf_pins M00_INIS2] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins dcmac_slash2service_3/S00_INIS] [get_bd_intf_pins S00_INIS3] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins dcmac_slash2service_3/M00_INIS] [get_bd_intf_pins M00_INIS3] + connect_bd_intf_net -intf_net Conn9 [get_bd_intf_pins dcmac_slash2service_4/S00_INIS] [get_bd_intf_pins S00_INIS4] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins dcmac_slash2service_4/M00_INIS] [get_bd_intf_pins M00_INIS4] + connect_bd_intf_net -intf_net Conn11 [get_bd_intf_pins dcmac_slash2service_5/S00_INIS] [get_bd_intf_pins S00_INIS5] + connect_bd_intf_net -intf_net Conn12 [get_bd_intf_pins dcmac_slash2service_5/M00_INIS] [get_bd_intf_pins M00_INIS5] + connect_bd_intf_net -intf_net Conn13 [get_bd_intf_pins dcmac_slash2service_6/S00_INIS] [get_bd_intf_pins S00_INIS6] + connect_bd_intf_net -intf_net Conn14 [get_bd_intf_pins dcmac_slash2service_6/M00_INIS] [get_bd_intf_pins M00_INIS6] + connect_bd_intf_net -intf_net Conn15 [get_bd_intf_pins dcmac_slash2service_7/S00_INIS] [get_bd_intf_pins S00_INIS7] + connect_bd_intf_net -intf_net Conn16 [get_bd_intf_pins dcmac_slash2service_7/M00_INIS] [get_bd_intf_pins M00_INIS7] + connect_bd_intf_net -intf_net Conn17 [get_bd_intf_pins dcmac_service2slash_0/S00_INIS] [get_bd_intf_pins S00_INIS8] + connect_bd_intf_net -intf_net Conn18 [get_bd_intf_pins dcmac_service2slash_0/M00_INIS] [get_bd_intf_pins M00_INIS8] + connect_bd_intf_net -intf_net Conn19 [get_bd_intf_pins dcmac_service2slash_1/S00_INIS] [get_bd_intf_pins S00_INIS9] + connect_bd_intf_net -intf_net Conn20 [get_bd_intf_pins dcmac_service2slash_1/M00_INIS] [get_bd_intf_pins M00_INIS9] + connect_bd_intf_net -intf_net Conn21 [get_bd_intf_pins dcmac_service2slash_2/S00_INIS] [get_bd_intf_pins S00_INIS10] + connect_bd_intf_net -intf_net Conn22 [get_bd_intf_pins dcmac_service2slash_2/M00_INIS] [get_bd_intf_pins M00_INIS10] + connect_bd_intf_net -intf_net Conn23 [get_bd_intf_pins dcmac_service2slash_3/S00_INIS] [get_bd_intf_pins S00_INIS11] + connect_bd_intf_net -intf_net Conn24 [get_bd_intf_pins dcmac_service2slash_3/M00_INIS] [get_bd_intf_pins M00_INIS11] + connect_bd_intf_net -intf_net Conn25 [get_bd_intf_pins dcmac_service2slash_4/S00_INIS] [get_bd_intf_pins S00_INIS12] + connect_bd_intf_net -intf_net Conn26 [get_bd_intf_pins dcmac_service2slash_4/M00_INIS] [get_bd_intf_pins M00_INIS12] + connect_bd_intf_net -intf_net Conn27 [get_bd_intf_pins dcmac_service2slash_5/S00_INIS] [get_bd_intf_pins S00_INIS13] + connect_bd_intf_net -intf_net Conn28 [get_bd_intf_pins dcmac_service2slash_5/M00_INIS] [get_bd_intf_pins M00_INIS13] + connect_bd_intf_net -intf_net Conn29 [get_bd_intf_pins dcmac_service2slash_6/S00_INIS] [get_bd_intf_pins S00_INIS14] + connect_bd_intf_net -intf_net Conn30 [get_bd_intf_pins dcmac_service2slash_6/M00_INIS] [get_bd_intf_pins M00_INIS14] + connect_bd_intf_net -intf_net Conn31 [get_bd_intf_pins dcmac_service2slash_7/S00_INIS] [get_bd_intf_pins S00_INIS15] + connect_bd_intf_net -intf_net Conn32 [get_bd_intf_pins dcmac_service2slash_7/M00_INIS] [get_bd_intf_pins M00_INIS15] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: aved +proc create_hier_cell_aved { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_aved() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 gt_pcie_refclk + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt_pciea1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 smbus_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 CPM_PCIE_NOC_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 CPM_PCIE_NOC_1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 PMC_NOC_AXI_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 LPD_AXI_NOC_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_pcie_mgmt_slr0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 NOC_PMC_AXI_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 NOC_CPM_PCIE_0 + + + # Create pins + create_bd_pin -dir O -type clk pl0_ref_clk + create_bd_pin -dir O -type clk lpd_axi_noc_clk + create_bd_pin -dir O -type clk pmc_axi_noc_axi0_clk + create_bd_pin -dir O -type clk cpm_pcie_noc_axi1_clk + create_bd_pin -dir O -type clk cpm_pcie_noc_axi0_clk + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pl_periph + create_bd_pin -dir O -type clk noc_pmc_axi_axi0_clk + create_bd_pin -dir O -type clk pl3_ref_clk + create_bd_pin -dir O -type rst pl3_resetn + create_bd_pin -dir O -type clk noc_cpm_pcie_axi0_clk + create_bd_pin -dir O eos + + # Create instance: clock_reset + create_hier_cell_clock_reset $hier_obj clock_reset + + # Create instance: base_logic + create_hier_cell_base_logic $hier_obj base_logic + + # Create instance: cips, and set properties + set cips [ create_bd_cell -type ip -vlnv xilinx.com:ip:versal_cips:3.4 cips ] + set_property -dict [list \ + CONFIG.CPM_CONFIG { \ + CPM_PCIE0_MODES {None} \ + CPM_PCIE0_TANDEM {None} \ + CPM_PCIE1_ACS_CAP_ON {0} \ + CPM_PCIE1_ARI_CAP_ENABLED {1} \ + CPM_PCIE1_BRIDGE_AXI_SLAVE_IF {1} \ + CPM_PCIE1_CFG_EXT_IF {1} \ + CPM_PCIE1_CFG_VEND_ID {10ee} \ + CPM_PCIE1_COPY_PF0_QDMA_ENABLED {0} \ + CPM_PCIE1_EXT_PCIE_CFG_SPACE_ENABLED {Extended_Large} \ + CPM_PCIE1_FUNCTIONAL_MODE {QDMA} \ + CPM_PCIE1_MAX_LINK_SPEED {32.0_GT/s} \ + CPM_PCIE1_MODES {DMA} \ + CPM_PCIE1_MODE_SELECTION {Advanced} \ + CPM_PCIE1_MSI_X_OPTIONS {MSI-X_Internal} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_0 {0x0000008000000000} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_1 {0x0000008040000000} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_2 {0x0000008080000000} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_3 {0x00000080C0000000} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_4 {0x0000008100000000} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_5 {0x0000008140000000} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_HIGHADDR_0 {0x000000803FFFFFFFF} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_HIGHADDR_1 {0x000000807FFFFFFFF} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_HIGHADDR_2 {0x00000080BFFFFFFFF} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_HIGHADDR_3 {0x00000080FFFFFFFFF} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_HIGHADDR_4 {0x000000813FFFFFFFF} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_HIGHADDR_5 {0x000000817FFFFFFFF} \ + CPM_PCIE1_PF0_BAR0_QDMA_64BIT {1} \ + CPM_PCIE1_PF0_BAR0_QDMA_ENABLED {1} \ + CPM_PCIE1_PF0_BAR0_QDMA_PREFETCHABLE {1} \ + CPM_PCIE1_PF0_BAR0_QDMA_SCALE {Megabytes} \ + CPM_PCIE1_PF0_BAR0_QDMA_SIZE {256} \ + CPM_PCIE1_PF0_BAR0_QDMA_TYPE {AXI_Bridge_Master} \ + CPM_PCIE1_PF0_BAR2_QDMA_64BIT {0} \ + CPM_PCIE1_PF0_BAR2_QDMA_ENABLED {0} \ + CPM_PCIE1_PF0_BAR2_QDMA_PREFETCHABLE {0} \ + CPM_PCIE1_PF0_BAR2_QDMA_SCALE {Kilobytes} \ + CPM_PCIE1_PF0_BAR2_QDMA_SIZE {4} \ + CPM_PCIE1_PF0_BAR2_QDMA_TYPE {AXI_Bridge_Master} \ + CPM_PCIE1_PF0_BASE_CLASS_VALUE {12} \ + CPM_PCIE1_PF0_CFG_DEV_ID {50b4} \ + CPM_PCIE1_PF0_CFG_SUBSYS_ID {000e} \ + CPM_PCIE1_PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE {0} \ + CPM_PCIE1_PF0_MSIX_CAP_TABLE_OFFSET {40} \ + CPM_PCIE1_PF0_MSIX_CAP_TABLE_SIZE {1} \ + CPM_PCIE1_PF0_MSIX_ENABLED {0} \ + CPM_PCIE1_PF0_PCIEBAR2AXIBAR_QDMA_0 {0x0000020100000000} \ + CPM_PCIE1_PF0_SUB_CLASS_VALUE {00} \ + CPM_PCIE1_PF1_BAR0_QDMA_64BIT {1} \ + CPM_PCIE1_PF1_BAR0_QDMA_ENABLED {1} \ + CPM_PCIE1_PF1_BAR0_QDMA_PREFETCHABLE {1} \ + CPM_PCIE1_PF1_BAR0_QDMA_SCALE {Kilobytes} \ + CPM_PCIE1_PF1_BAR0_QDMA_SIZE {512} \ + CPM_PCIE1_PF1_BAR0_QDMA_TYPE {DMA} \ + CPM_PCIE1_PF1_BAR2_QDMA_64BIT {0} \ + CPM_PCIE1_PF1_BAR2_QDMA_ENABLED {0} \ + CPM_PCIE1_PF1_BAR2_QDMA_PREFETCHABLE {0} \ + CPM_PCIE1_PF1_BAR2_QDMA_SCALE {Kilobytes} \ + CPM_PCIE1_PF1_BAR2_QDMA_SIZE {4} \ + CPM_PCIE1_PF1_BAR2_QDMA_TYPE {AXI_Bridge_Master} \ + CPM_PCIE1_PF1_BASE_CLASS_VALUE {12} \ + CPM_PCIE1_PF1_CFG_DEV_ID {50b5} \ + CPM_PCIE1_PF1_CFG_SUBSYS_ID {000e} \ + CPM_PCIE1_PF1_CFG_SUBSYS_VEND_ID {10EE} \ + CPM_PCIE1_PF1_MSIX_CAP_TABLE_OFFSET {50000} \ + CPM_PCIE1_PF1_MSIX_CAP_TABLE_SIZE {8} \ + CPM_PCIE1_PF1_MSIX_ENABLED {1} \ + CPM_PCIE1_PF1_PCIEBAR2AXIBAR_QDMA_2 {0x0000020200000000} \ + CPM_PCIE1_PF1_SUB_CLASS_VALUE {00} \ + CPM_PCIE1_PF2_BAR0_QDMA_64BIT {1} \ + CPM_PCIE1_PF2_BAR0_QDMA_SCALE {Megabytes} \ + CPM_PCIE1_PF2_BAR0_QDMA_SIZE {128} \ + CPM_PCIE1_PF2_BAR0_QDMA_TYPE {AXI_Bridge_Master} \ + CPM_PCIE1_PF2_BAR2_QDMA_ENABLED {1} \ + CPM_PCIE1_PF2_BAR2_QDMA_SCALE {Megabytes} \ + CPM_PCIE1_PF2_BAR2_QDMA_SIZE {128} \ + CPM_PCIE1_PF2_BAR2_QDMA_TYPE {AXI_Bridge_Master} \ + CPM_PCIE1_PF2_BASE_CLASS_VALUE {12} \ + CPM_PCIE1_PF2_CFG_DEV_ID {50b6} \ + CPM_PCIE1_PF2_CFG_SUBSYS_ID {000e} \ + CPM_PCIE1_PF2_CFG_SUBSYS_VEND_ID {10EE} \ + CPM_PCIE1_PF2_PCIEBAR2AXIBAR_QDMA_0 {0x0000020200000000} \ + CPM_PCIE1_PF2_PCIEBAR2AXIBAR_QDMA_2 {0x0000020300000000} \ + CPM_PCIE1_PF2_USE_CLASS_CODE_LOOKUP_ASSISTANT {0} \ + CPM_PCIE1_PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CPM_PCIE1_TL_PF_ENABLE_REG {3} \ + } \ + CONFIG.PS_PMC_CONFIG { \ + BOOT_MODE {Custom} \ + CLOCK_MODE {Custom} \ + DDR_MEMORY_MODE {Custom} \ + DESIGN_MODE {1} \ + DEVICE_INTEGRITY_MODE {Custom} \ + IO_CONFIG_MODE {Custom} \ + PCIE_APERTURES_DUAL_ENABLE {0} \ + PCIE_APERTURES_SINGLE_ENABLE {1} \ + PMC_BANK_1_IO_STANDARD {LVCMOS3.3} \ + PMC_CRP_OSPI_REF_CTRL_FREQMHZ {200} \ + PMC_CRP_PL0_REF_CTRL_FREQMHZ {100} \ + PMC_CRP_PL1_REF_CTRL_FREQMHZ {33.3333333} \ + PMC_CRP_PL2_REF_CTRL_FREQMHZ {250} \ + PMC_CRP_PL3_REF_CTRL_FREQMHZ {200} \ + PMC_GLITCH_CONFIG {{DEPTH_SENSITIVITY 1} {MIN_PULSE_WIDTH 0.5} {TYPE CUSTOM} {VCC_PMC_VALUE 0.88}} \ + PMC_GLITCH_CONFIG_1 {{DEPTH_SENSITIVITY 1} {MIN_PULSE_WIDTH 0.5} {TYPE CUSTOM} {VCC_PMC_VALUE 0.88}} \ + PMC_GLITCH_CONFIG_2 {{DEPTH_SENSITIVITY 1} {MIN_PULSE_WIDTH 0.5} {TYPE CUSTOM} {VCC_PMC_VALUE 0.88}} \ + PMC_GPIO_EMIO_PERIPHERAL_ENABLE {0} \ + PMC_MIO11 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO12 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO13 {{AUX_IO 0} {DIRECTION inout} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \ + PMC_MIO17 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO26 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO27 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO28 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO29 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO30 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO31 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO32 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO33 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO34 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO35 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO36 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO37 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO38 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO39 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO40 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO41 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO42 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO43 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO44 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO48 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO49 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO50 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO51 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO_EN_FOR_PL_PCIE {0} \ + PMC_OSPI_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 0 .. 11}} {MODE Single}} \ + PMC_REF_CLK_FREQMHZ {33.333333} \ + PMC_SD0_DATA_TRANSFER_MODE {8Bit} \ + PMC_SD0_PERIPHERAL {{CLK_100_SDR_OTAP_DLY 0x00} {CLK_200_SDR_OTAP_DLY 0x2} {CLK_50_DDR_ITAP_DLY 0x1E} {CLK_50_DDR_OTAP_DLY 0x5} {CLK_50_SDR_ITAP_DLY 0x2C} {CLK_50_SDR_OTAP_DLY 0x5} {ENABLE 1} {IO\ +{PMC_MIO 13 .. 25}}} \ + PMC_SD0_SLOT_TYPE {eMMC} \ + PMC_USE_NOC_PMC_AXI0 {1} \ + PMC_USE_PMC_NOC_AXI0 {1} \ + PS_BANK_2_IO_STANDARD {LVCMOS3.3} \ + PS_BOARD_INTERFACE {Custom} \ + PS_CRL_CPM_TOPSW_REF_CTRL_FREQMHZ {1000} \ + PS_GEN_IPI0_ENABLE {0} \ + PS_GEN_IPI1_ENABLE {0} \ + PS_GEN_IPI2_ENABLE {0} \ + PS_GEN_IPI3_ENABLE {1} \ + PS_GEN_IPI3_MASTER {R5_0} \ + PS_GEN_IPI4_ENABLE {1} \ + PS_GEN_IPI4_MASTER {R5_0} \ + PS_GEN_IPI5_ENABLE {1} \ + PS_GEN_IPI5_MASTER {R5_1} \ + PS_GEN_IPI6_ENABLE {1} \ + PS_GEN_IPI6_MASTER {R5_1} \ + PS_GPIO_EMIO_PERIPHERAL_ENABLE {0} \ + PS_I2C0_PERIPHERAL {{ENABLE 1} {IO {PS_MIO 2 .. 3}}} \ + PS_I2C1_PERIPHERAL {{ENABLE 1} {IO {PS_MIO 0 .. 1}}} \ + PS_IRQ_USAGE {{CH0 1} {CH1 1} {CH10 0} {CH11 0} {CH12 0} {CH13 0} {CH14 0} {CH15 0} {CH2 0} {CH3 0} {CH4 0} {CH5 0} {CH6 0} {CH7 0} {CH8 0} {CH9 0}} \ + PS_KAT_ENABLE {0} \ + PS_KAT_ENABLE_1 {0} \ + PS_KAT_ENABLE_2 {0} \ + PS_MIO10 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO11 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO12 {{AUX_IO 0} {DIRECTION inout} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \ + PS_MIO13 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO14 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO18 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO19 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO22 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO23 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO24 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO25 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO4 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO5 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO6 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO7 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO8 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \ + PS_MIO9 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 1} {SLEW slow} {USAGE Reserved}} \ + PS_M_AXI_LPD_DATA_WIDTH {32} \ + PS_NUM_FABRIC_RESETS {4} \ + PS_PCIE1_PERIPHERAL_ENABLE {0} \ + PS_PCIE2_PERIPHERAL_ENABLE {1} \ + PS_PCIE_EP_RESET1_IO {PMC_MIO 24} \ + PS_PCIE_EP_RESET2_IO {PMC_MIO 25} \ + PS_PCIE_RESET {ENABLE 1} \ + PS_PL_CONNECTIVITY_MODE {Custom} \ + PS_SPI0 {{GRP_SS0_ENABLE 1} {GRP_SS0_IO {PS_MIO 15}} {GRP_SS1_ENABLE 0} {GRP_SS1_IO {PMC_MIO 14}} {GRP_SS2_ENABLE 0} {GRP_SS2_IO {PMC_MIO 13}} {PERIPHERAL_ENABLE 1} {PERIPHERAL_IO {PS_MIO 12 .. 17}}}\ +\ + PS_SPI1 {{GRP_SS0_ENABLE 0} {GRP_SS0_IO {PS_MIO 9}} {GRP_SS1_ENABLE 0} {GRP_SS1_IO {PS_MIO 8}} {GRP_SS2_ENABLE 0} {GRP_SS2_IO {PS_MIO 7}} {PERIPHERAL_ENABLE 0} {PERIPHERAL_IO {PS_MIO 6 .. 11}}} \ + PS_TTC0_PERIPHERAL_ENABLE {1} \ + PS_TTC1_PERIPHERAL_ENABLE {1} \ + PS_TTC2_PERIPHERAL_ENABLE {1} \ + PS_TTC3_PERIPHERAL_ENABLE {1} \ + PS_UART0_PERIPHERAL {{ENABLE 1} {IO {PS_MIO 8 .. 9}}} \ + PS_UART1_PERIPHERAL {{ENABLE 1} {IO {PS_MIO 20 .. 21}}} \ + PS_USE_FPD_CCI_NOC {0} \ + PS_USE_M_AXI_FPD {0} \ + PS_USE_M_AXI_LPD {1} \ + PS_USE_NOC_LPD_AXI0 {1} \ + PS_USE_PMCPL_CLK0 {1} \ + PS_USE_PMCPL_CLK1 {1} \ + PS_USE_PMCPL_CLK2 {1} \ + PS_USE_PMCPL_CLK3 {1} \ + PS_USE_STARTUP {1} \ + PS_USE_S_AXI_LPD {0} \ + SMON_ALARMS {Set_Alarms_On} \ + SMON_ENABLE_TEMP_AVERAGING {0} \ + SMON_MEAS100 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 4.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {4 V unipolar}} {NAME VCCO_500} {SUPPLY_NUM 9}} \ + SMON_MEAS101 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 4.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {4 V unipolar}} {NAME VCCO_501} {SUPPLY_NUM 10}} \ + SMON_MEAS102 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 4.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {4 V unipolar}} {NAME VCCO_502} {SUPPLY_NUM 11}} \ + SMON_MEAS103 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 4.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {4 V unipolar}} {NAME VCCO_503} {SUPPLY_NUM 12}} \ + SMON_MEAS104 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCO_700} {SUPPLY_NUM 13}} \ + SMON_MEAS105 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCO_701} {SUPPLY_NUM 14}} \ + SMON_MEAS106 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCO_702} {SUPPLY_NUM 15}} \ + SMON_MEAS118 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCC_PMC} {SUPPLY_NUM 0}} \ + SMON_MEAS119 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCC_PSFP} {SUPPLY_NUM 1}} \ + SMON_MEAS120 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCC_PSLP} {SUPPLY_NUM 2}} \ + SMON_MEAS121 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCC_RAM} {SUPPLY_NUM 3}} \ + SMON_MEAS122 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCC_SOC} {SUPPLY_NUM 4}} \ + SMON_MEAS47 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME GTYP_AVCCAUX_104} {SUPPLY_NUM 20}} \ + SMON_MEAS48 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME GTYP_AVCCAUX_105} {SUPPLY_NUM 21}} \ + SMON_MEAS64 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME GTYP_AVCC_104} {SUPPLY_NUM 18}} \ + SMON_MEAS65 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME GTYP_AVCC_105} {SUPPLY_NUM 19}} \ + SMON_MEAS81 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME GTYP_AVTT_104} {SUPPLY_NUM 22}} \ + SMON_MEAS82 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME GTYP_AVTT_105} {SUPPLY_NUM 23}} \ + SMON_MEAS96 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCAUX} {SUPPLY_NUM 6}} \ + SMON_MEAS97 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCAUX_PMC} {SUPPLY_NUM 7}} \ + SMON_MEAS98 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCAUX_SMON} {SUPPLY_NUM 8}} \ + SMON_MEAS99 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCINT} {SUPPLY_NUM 5}} \ + SMON_TEMP_AVERAGING_SAMPLES {0} \ + SMON_VOLTAGE_AVERAGING_SAMPLES {8} \ + } \ + CONFIG.PS_PMC_CONFIG_APPLIED {1} \ + ] $cips + + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins cips/gt_refclk1] [get_bd_intf_pins gt_pcie_refclk] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins cips/PCIE1_GT] [get_bd_intf_pins gt_pciea1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins base_logic/smbus_rpu] [get_bd_intf_pins smbus_0] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins cips/CPM_PCIE_NOC_0] [get_bd_intf_pins CPM_PCIE_NOC_0] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins cips/CPM_PCIE_NOC_1] [get_bd_intf_pins CPM_PCIE_NOC_1] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins cips/PMC_NOC_AXI_0] [get_bd_intf_pins PMC_NOC_AXI_0] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins cips/LPD_AXI_NOC_0] [get_bd_intf_pins LPD_AXI_NOC_0] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins base_logic/s_axi_pcie_mgmt_slr0] [get_bd_intf_pins s_axi_pcie_mgmt_slr0] + connect_bd_intf_net -intf_net NOC_CPM_PCIE_0_1 [get_bd_intf_pins NOC_CPM_PCIE_0] [get_bd_intf_pins cips/NOC_CPM_PCIE_0] + connect_bd_intf_net -intf_net NOC_PMC_AXI_0_1 [get_bd_intf_pins NOC_PMC_AXI_0] [get_bd_intf_pins cips/NOC_PMC_AXI_0] + connect_bd_intf_net -intf_net base_logic_m_axi_pcie_mgmt_pdi_reset [get_bd_intf_pins base_logic/m_axi_pcie_mgmt_pdi_reset] [get_bd_intf_pins clock_reset/s_axi_pcie_mgmt_pdi_reset] + connect_bd_intf_net -intf_net cips_M_AXI_LPD [get_bd_intf_pins cips/M_AXI_LPD] [get_bd_intf_pins base_logic/s_axi_rpu] + connect_bd_intf_net -intf_net cips_pcie1_cfg_ext [get_bd_intf_pins cips/pcie1_cfg_ext] [get_bd_intf_pins base_logic/pcie_cfg_ext] + + # Create port connections + connect_bd_net -net base_logic_irq_axi_smbus_rpu [get_bd_pins base_logic/irq_axi_smbus_rpu] \ + [get_bd_pins cips/pl_ps_irq1] + connect_bd_net -net base_logic_irq_gcq_m2r [get_bd_pins base_logic/irq_gcq_m2r] \ + [get_bd_pins cips/pl_ps_irq0] + connect_bd_net -net cips_cpm_pcie_noc_axi0_clk [get_bd_pins cips/cpm_pcie_noc_axi0_clk] \ + [get_bd_pins cpm_pcie_noc_axi0_clk] + connect_bd_net -net cips_cpm_pcie_noc_axi1_clk [get_bd_pins cips/cpm_pcie_noc_axi1_clk] \ + [get_bd_pins cpm_pcie_noc_axi1_clk] + connect_bd_net -net cips_dma1_axi_aresetn [get_bd_pins cips/dma1_axi_aresetn] \ + [get_bd_pins clock_reset/dma_axi_aresetn] + connect_bd_net -net cips_eos [get_bd_pins cips/eos] \ + [get_bd_pins eos] + connect_bd_net -net cips_lpd_axi_noc_clk [get_bd_pins cips/lpd_axi_noc_clk] \ + [get_bd_pins lpd_axi_noc_clk] + connect_bd_net -net cips_noc_cpm_pcie_axi0_clk [get_bd_pins cips/noc_cpm_pcie_axi0_clk] \ + [get_bd_pins noc_cpm_pcie_axi0_clk] + connect_bd_net -net cips_noc_pmc_axi_axi0_clk [get_bd_pins cips/noc_pmc_axi_axi0_clk] \ + [get_bd_pins noc_pmc_axi_axi0_clk] + connect_bd_net -net cips_pl0_ref_clk [get_bd_pins cips/pl0_ref_clk] \ + [get_bd_pins pl0_ref_clk] \ + [get_bd_pins cips/m_axi_lpd_aclk] \ + [get_bd_pins base_logic/clk_pl] \ + [get_bd_pins clock_reset/clk_pl] + connect_bd_net -net cips_pl0_resetn [get_bd_pins cips/pl0_resetn] \ + [get_bd_pins clock_reset/resetn_pl_axi] + connect_bd_net -net cips_pl1_ref_clk [get_bd_pins cips/pl1_ref_clk] \ + [get_bd_pins clock_reset/clk_freerun] + connect_bd_net -net cips_pl2_ref_clk [get_bd_pins cips/pl2_ref_clk] \ + [get_bd_pins cips/dma1_intrfc_clk] \ + [get_bd_pins base_logic/clk_pcie] \ + [get_bd_pins clock_reset/clk_pcie] + connect_bd_net -net cips_pl3_ref_clk [get_bd_pins cips/pl3_ref_clk] \ + [get_bd_pins pl3_ref_clk] + connect_bd_net -net cips_pl3_resetn [get_bd_pins cips/pl3_resetn] \ + [get_bd_pins pl3_resetn] + connect_bd_net -net cips_pmc_axi_noc_axi0_clk [get_bd_pins cips/pmc_axi_noc_axi0_clk] \ + [get_bd_pins pmc_axi_noc_axi0_clk] + connect_bd_net -net clock_reset_resetn_pcie_ic [get_bd_pins clock_reset/resetn_pcie_ic] \ + [get_bd_pins cips/dma1_intrfc_resetn] + connect_bd_net -net clock_reset_resetn_pcie_periph [get_bd_pins clock_reset/resetn_pcie_periph] \ + [get_bd_pins base_logic/resetn_pcie_periph] + connect_bd_net -net clock_reset_resetn_pl_ic [get_bd_pins clock_reset/resetn_pl_ic] \ + [get_bd_pins base_logic/resetn_pl_ic] + connect_bd_net -net clock_reset_resetn_pl_periph [get_bd_pins clock_reset/resetn_pl_periph] \ + [get_bd_pins base_logic/resetn_pl_periph] \ + [get_bd_pins resetn_pl_periph] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: noc +proc create_hier_cell_noc { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_noc() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 CH0_DDR4_0_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk0_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk0_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 CH0_DDR4_0_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S03_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 hbm_ref_clk_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 hbm_ref_clk_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S01_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S02_AXI + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM00_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM01_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM02_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM03_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM04_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM05_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM06_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM07_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM08_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM09_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM10_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM11_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM12_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM13_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM14_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM15_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM16_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM17_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM18_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM19_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM20_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM21_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM22_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM23_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM24_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM25_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM26_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM27_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM28_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM29_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM30_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM31_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM32_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM33_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM34_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM35_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM36_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM37_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM38_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM39_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM40_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM41_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM42_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM43_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM44_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM45_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM46_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM47_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM48_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM49_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM50_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM51_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM52_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM53_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM54_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM55_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM56_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM57_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM58_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM59_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM60_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM61_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM62_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM63_AXI + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S01_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S02_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S03_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S04_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S05_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S06_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S07_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S08_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S09_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S10_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S11_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S12_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S13_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S14_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S15_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S16_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S17_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S18_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S19_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S20_INI1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S21_INI1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S22_INI1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S23_INI1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M05_INI + set_property APERTURES {{0x203_0000_0000 128M}} [get_bd_intf_pins /static_region/noc/M05_INI] + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M04_INI + + + # Create pins + create_bd_pin -dir I -type clk aclk0 + create_bd_pin -dir I -type clk aclk3 + create_bd_pin -dir I -type clk aclk1 + create_bd_pin -dir I -type clk aclk2 + create_bd_pin -dir I -type clk aclk4 + create_bd_pin -dir I -type clk aclk5 + create_bd_pin -dir I -type clk aclk6 + + # Create instance: axi_noc_mc_ddr4_0, and set properties + set axi_noc_mc_ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_mc_ddr4_0 ] + set_property -dict [list \ + CONFIG.CONTROLLERTYPE {DDR4_SDRAM} \ + CONFIG.MC_CHAN_REGION1 {DDR_CH1} \ + CONFIG.MC_COMPONENT_WIDTH {x16} \ + CONFIG.MC_DATAWIDTH {72} \ + CONFIG.MC_DM_WIDTH {9} \ + CONFIG.MC_DQS_WIDTH {9} \ + CONFIG.MC_DQ_WIDTH {72} \ + CONFIG.MC_INIT_MEM_USING_ECC_SCRUB {true} \ + CONFIG.MC_INPUTCLK0_PERIOD {5000} \ + CONFIG.MC_MEMORY_DEVICETYPE {Components} \ + CONFIG.MC_MEMORY_SPEEDGRADE {DDR4-3200AA(22-22-22)} \ + CONFIG.MC_NO_CHANNELS {Single} \ + CONFIG.MC_RANK {1} \ + CONFIG.MC_ROWADDRESSWIDTH {16} \ + CONFIG.MC_STACKHEIGHT {1} \ + CONFIG.MC_SYSTEM_CLOCK {Differential} \ + CONFIG.NUM_CLKS {0} \ + CONFIG.NUM_MC {1} \ + CONFIG.NUM_MCP {4} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {0} \ + CONFIG.NUM_NSI {2} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_mc_ddr4_0 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS { MC_0 {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} } } \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_mc_ddr4_0/S00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS { MC_1 {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} } } \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_mc_ddr4_0/S01_INI] + + # Create instance: axi_noc_cips, and set properties + set axi_noc_cips [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_cips ] + set_property -dict [list \ + CONFIG.HBM_CHNL0_CONFIG {HBM_REORDER_EN FALSE HBM_MAINTAIN_COHERENCY TRUE HBM_Q_AGE_LIMIT 0x7F HBM_CLOSE_PAGE_REORDER FALSE HBM_LOOKAHEAD_PCH TRUE HBM_COMMAND_PARITY FALSE HBM_DQ_WR_PARITY FALSE HBM_DQ_RD_PARITY\ +FALSE HBM_RD_DBI TRUE HBM_WR_DBI TRUE HBM_REFRESH_MODE SINGLE_BANK_REFRESH HBM_PC0_PRE_DEFINED_ADDRESS_MAP USER_DEFINED_ADDRESS_MAP HBM_PC1_PRE_DEFINED_ADDRESS_MAP USER_DEFINED_ADDRESS_MAP HBM_PC0_USER_DEFINED_ADDRESS_MAP\ +1BG-15RA-1SID-2BA-5CA-1BG HBM_PC1_USER_DEFINED_ADDRESS_MAP 1BG-15RA-1SID-2BA-5CA-1BG HBM_PC0_ADDRESS_MAP BA3,RA14,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,SID,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BA2,NC,NA,NA,NA,NA\ +HBM_PC1_ADDRESS_MAP BA3,RA14,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,SID,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BA2,NC,NA,NA,NA,NA HBM_PWR_DWN_IDLE_TIMEOUT_ENTRY FALSE HBM_SELF_REF_IDLE_TIMEOUT_ENTRY\ +FALSE HBM_IDLE_TIME_TO_ENTER_PWR_DWN_MODE 0x0001000 HBM_IDLE_TIME_TO_ENTER_SELF_REF_MODE 1X HBM_ECC_CORRECTION_EN FALSE HBM_WRITE_BACK_CORRECTED_DATA TRUE HBM_ECC_SCRUBBING FALSE HBM_ECC_INITIALIZE_EN\ +FALSE HBM_ECC_SCRUB_SIZE 1092 HBM_WRITE_DATA_MASK TRUE HBM_REF_PERIOD_TEMP_COMP FALSE HBM_PARITY_LATENCY 3 HBM_PC0_PAGE_HIT 100.000 HBM_PC1_PAGE_HIT 100.000 HBM_PC0_READ_RATE 25.000 HBM_PC1_READ_RATE 25.000\ +HBM_PC0_WRITE_RATE 25.000 HBM_PC1_WRITE_RATE 25.000 HBM_PC0_PHY_ACTIVE ENABLED HBM_PC1_PHY_ACTIVE ENABLED HBM_PC0_SCRUB_START_ADDRESS 0x0000000 HBM_PC0_SCRUB_END_ADDRESS 0x3FFFBFF HBM_PC0_SCRUB_INTERVAL\ +24.000 HBM_PC1_SCRUB_START_ADDRESS 0x0000000 HBM_PC1_SCRUB_END_ADDRESS 0x3FFFBFF HBM_PC1_SCRUB_INTERVAL 24.000} \ + CONFIG.HBM_NUM_CHNL {16} \ + CONFIG.HBM_REF_CLK_FREQ0 {200.000} \ + CONFIG.HBM_REF_CLK_FREQ1 {200.000} \ + CONFIG.HBM_REF_CLK_SELECTION {External} \ + CONFIG.MI_NAMES {} \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_CLKS {7} \ + CONFIG.NUM_HBM_BLI {64} \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_NMI {6} \ + CONFIG.NUM_NSI {24} \ + CONFIG.NUM_SI {4} \ + CONFIG.SI_NAMES {} \ + CONFIG.SI_SIDEBAND_PINS { ,0,0,0} \ + ] $axi_noc_cips + + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X2Y0} \ + CONFIG.CONNECTIONS {HBM0_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM00_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X3Y0} \ + CONFIG.CONNECTIONS {HBM0_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM01_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X1Y0} \ + CONFIG.CONNECTIONS {HBM0_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM02_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X0Y0} \ + CONFIG.CONNECTIONS {HBM0_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM03_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X4Y0} \ + CONFIG.CONNECTIONS {HBM1_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM04_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X5Y0} \ + CONFIG.CONNECTIONS {HBM1_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM05_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X6Y0} \ + CONFIG.CONNECTIONS {HBM1_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM06_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X7Y0} \ + CONFIG.CONNECTIONS {HBM1_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM07_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X10Y0} \ + CONFIG.CONNECTIONS {HBM2_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM08_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X11Y0} \ + CONFIG.CONNECTIONS {HBM2_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM09_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X8Y0} \ + CONFIG.CONNECTIONS {HBM2_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM10_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X9Y0} \ + CONFIG.CONNECTIONS {HBM2_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM11_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X12Y0} \ + CONFIG.CONNECTIONS {HBM3_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM12_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X13Y0} \ + CONFIG.CONNECTIONS {HBM3_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM13_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X15Y0} \ + CONFIG.CONNECTIONS {HBM3_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM14_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X14Y0} \ + CONFIG.CONNECTIONS {HBM3_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM15_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X19Y0} \ + CONFIG.CONNECTIONS {HBM4_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM16_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X18Y0} \ + CONFIG.CONNECTIONS {HBM4_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM17_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X17Y0} \ + CONFIG.CONNECTIONS {HBM4_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM18_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X16Y0} \ + CONFIG.CONNECTIONS {HBM4_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM19_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X20Y0} \ + CONFIG.CONNECTIONS {HBM5_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM20_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X21Y0} \ + CONFIG.CONNECTIONS {HBM5_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM21_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X22Y0} \ + CONFIG.CONNECTIONS {HBM5_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM22_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X23Y0} \ + CONFIG.CONNECTIONS {HBM5_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM23_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X27Y0} \ + CONFIG.CONNECTIONS {HBM6_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM24_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X26Y0} \ + CONFIG.CONNECTIONS {HBM6_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM25_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X24Y0} \ + CONFIG.CONNECTIONS {HBM6_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM26_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X25Y0} \ + CONFIG.CONNECTIONS {HBM6_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM27_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X29Y0} \ + CONFIG.CONNECTIONS {HBM7_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM28_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X28Y0} \ + CONFIG.CONNECTIONS {HBM7_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM29_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X31Y0} \ + CONFIG.CONNECTIONS {HBM7_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM30_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X30Y0} \ + CONFIG.CONNECTIONS {HBM7_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM31_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X35Y0} \ + CONFIG.CONNECTIONS {HBM8_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM32_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X34Y0} \ + CONFIG.CONNECTIONS {HBM8_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM33_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X33Y0} \ + CONFIG.CONNECTIONS {HBM8_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM34_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X32Y0} \ + CONFIG.CONNECTIONS {HBM8_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM35_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X37Y0} \ + CONFIG.CONNECTIONS {HBM9_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM36_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X36Y0} \ + CONFIG.CONNECTIONS {HBM9_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM37_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X39Y0} \ + CONFIG.CONNECTIONS {HBM9_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM38_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X38Y0} \ + CONFIG.CONNECTIONS {HBM9_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM39_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X43Y0} \ + CONFIG.CONNECTIONS {HBM10_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM40_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X42Y0} \ + CONFIG.CONNECTIONS {HBM10_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM41_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X41Y0} \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM42_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X40Y0} \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM43_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X44Y0} \ + CONFIG.CONNECTIONS {HBM11_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM44_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X45Y0} \ + CONFIG.CONNECTIONS {HBM11_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM45_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X47Y0} \ + CONFIG.CONNECTIONS {HBM11_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM46_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X46Y0} \ + CONFIG.CONNECTIONS {HBM11_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM47_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X51Y0} \ + CONFIG.CONNECTIONS {HBM12_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM48_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X50Y0} \ + CONFIG.CONNECTIONS {HBM12_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM49_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X48Y0} \ + CONFIG.CONNECTIONS {HBM12_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM50_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X49Y0} \ + CONFIG.CONNECTIONS {HBM12_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM51_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X52Y0} \ + CONFIG.CONNECTIONS {HBM13_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM52_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X53Y0} \ + CONFIG.CONNECTIONS {HBM13_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM53_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X55Y0} \ + CONFIG.CONNECTIONS {HBM13_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM54_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X54Y0} \ + CONFIG.CONNECTIONS {HBM13_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM55_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X58Y0} \ + CONFIG.CONNECTIONS {HBM14_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM56_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X59Y0} \ + CONFIG.CONNECTIONS {HBM14_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM57_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X57Y0} \ + CONFIG.CONNECTIONS {HBM14_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM58_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X56Y0} \ + CONFIG.CONNECTIONS {HBM14_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM59_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X61Y0} \ + CONFIG.CONNECTIONS {HBM15_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM60_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X60Y0} \ + CONFIG.CONNECTIONS {HBM15_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM61_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X63Y0} \ + CONFIG.CONNECTIONS {HBM15_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM62_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X62Y0} \ + CONFIG.CONNECTIONS {HBM15_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM63_AXI] + + set_property -dict [ list \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.APERTURES {{0x201_0000_0000 0x200_0000}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/M00_AXI] + + set_property -dict [ list \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.CATEGORY {ps_pmc} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/M01_AXI] + + set_property -dict [ list \ + CONFIG.APERTURES {{0x202_0000_0000 0x100_0000}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/M04_INI] + + set_property -dict [ list \ + CONFIG.APERTURES {{0x203_0000_0000 0x40_0000}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/M05_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M02_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} HBM15_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M01_AXI {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M04_INI {read_bw {500} write_bw {500}} HBM2_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M05_INI {read_bw {500} write_bw {500}} HBM11_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M00_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} HBM9_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M00_AXI {read_bw {5} write_bw {5} read_avg_burst {64} write_avg_burst {64}}} \ + CONFIG.DEST_IDS {M01_AXI:0x1:M00_AXI:0x4} \ + CONFIG.REMAPS {M00_INI {{0x20108000000 0x00038000000 0x08000000}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {ps_pcie} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {M02_INI {read_bw {800} write_bw {800}} M00_INI {read_bw {800} write_bw {800}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M01_AXI {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M01_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} HBM0_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M04_INI {read_bw {500} write_bw {500}} M05_INI {read_bw {500} write_bw {500}} HBM9_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M03_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} HBM2_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M00_AXI {read_bw {5} write_bw {5} read_avg_burst {64} write_avg_burst {64}} HBM13_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {M01_AXI:0x1:M00_AXI:0x4} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {ps_pcie} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S01_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {M01_INI {read_bw {800} write_bw {800}} M03_INI {read_bw {800} write_bw {800}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S01_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M02_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} M00_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {ps_pmc} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S02_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {M02_INI {read_bw {800} write_bw {800}} M00_INI {read_bw {800} write_bw {800}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S02_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {ps_rpu} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S03_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {M01_INI {read_bw {800} write_bw {800}} M03_INI {read_bw {800} write_bw {800}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S03_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S04_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S05_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S06_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S07_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S08_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S09_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S10_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S11_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M02_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S12_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M03_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S13_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M02_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S14_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M03_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S15_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M02_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S16_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M03_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S17_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M02_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S18_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M03_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S19_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M02_INI {read_bw {50} write_bw {50}} HBM15_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M00_INI {read_bw {50} write_bw {50}} HBM9_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S20_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M01_INI {read_bw {50} write_bw {50}} HBM0_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M03_INI {read_bw {50} write_bw {50}} HBM2_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S21_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M02_INI {read_bw {50} write_bw {50}} HBM15_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M00_INI {read_bw {50} write_bw {50}} HBM9_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S22_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M01_INI {read_bw {50} write_bw {50}} HBM0_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M03_INI {read_bw {50} write_bw {50}} HBM2_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S23_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk0] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S01_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk1] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S02_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk2] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S03_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk3] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk4] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {HBM00_AXI:HBM01_AXI:HBM02_AXI:HBM03_AXI:HBM04_AXI:HBM05_AXI:HBM06_AXI:HBM07_AXI:HBM08_AXI:HBM09_AXI:HBM10_AXI:HBM11_AXI:HBM12_AXI:HBM13_AXI:HBM14_AXI:HBM15_AXI:HBM16_AXI:HBM17_AXI:HBM18_AXI:HBM19_AXI:HBM20_AXI:HBM21_AXI:HBM22_AXI:HBM23_AXI:HBM24_AXI:HBM25_AXI:HBM26_AXI:HBM27_AXI:HBM28_AXI:HBM29_AXI:HBM30_AXI:HBM31_AXI:HBM32_AXI:HBM33_AXI:HBM34_AXI:HBM35_AXI:HBM36_AXI:HBM37_AXI:HBM38_AXI:HBM39_AXI:HBM40_AXI:HBM41_AXI:HBM42_AXI:HBM43_AXI:HBM44_AXI:HBM45_AXI:HBM46_AXI:HBM47_AXI:HBM48_AXI:HBM49_AXI:HBM50_AXI:HBM51_AXI:HBM52_AXI:HBM53_AXI:HBM54_AXI:HBM55_AXI:HBM56_AXI:HBM57_AXI:HBM58_AXI:HBM59_AXI:HBM60_AXI:HBM61_AXI:HBM62_AXI:HBM63_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk5] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M01_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk6] + + # Create instance: axi_noc_mc_ddr4_1, and set properties + set axi_noc_mc_ddr4_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_mc_ddr4_1 ] + set_property -dict [list \ + CONFIG.CONTROLLERTYPE {DDR4_SDRAM} \ + CONFIG.MC0_CONFIG_NUM {config21} \ + CONFIG.MC0_FLIPPED_PINOUT {false} \ + CONFIG.MC_CHAN_REGION0 {DDR_CH2} \ + CONFIG.MC_COMPONENT_WIDTH {x4} \ + CONFIG.MC_DATAWIDTH {72} \ + CONFIG.MC_INIT_MEM_USING_ECC_SCRUB {true} \ + CONFIG.MC_INPUTCLK0_PERIOD {5000} \ + CONFIG.MC_MEMORY_DEVICETYPE {RDIMMs} \ + CONFIG.MC_MEMORY_SPEEDGRADE {DDR4-3200AA(22-22-22)} \ + CONFIG.MC_NO_CHANNELS {Single} \ + CONFIG.MC_PARITY {true} \ + CONFIG.MC_RANK {1} \ + CONFIG.MC_ROWADDRESSWIDTH {18} \ + CONFIG.MC_STACKHEIGHT {1} \ + CONFIG.MC_SYSTEM_CLOCK {Differential} \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MC {1} \ + CONFIG.NUM_MCP {4} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {0} \ + CONFIG.NUM_NSI {2} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_mc_ddr4_1 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS { MC_0 {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} } } \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_mc_ddr4_1/S00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS { MC_1 {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} } } \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_mc_ddr4_1/S01_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {} \ + ] [get_bd_pins /static_region/noc/axi_noc_mc_ddr4_1/aclk0] + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axi_noc_mc_ddr4_1/CH0_DDR4_0] [get_bd_intf_pins CH0_DDR4_0_1] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_noc_mc_ddr4_1/sys_clk0] [get_bd_intf_pins sys_clk0_1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins axi_noc_mc_ddr4_0/sys_clk0] [get_bd_intf_pins sys_clk0_0] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins axi_noc_mc_ddr4_0/CH0_DDR4_0] [get_bd_intf_pins CH0_DDR4_0_0] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins axi_noc_cips/S03_AXI] [get_bd_intf_pins S03_AXI] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins axi_noc_cips/hbm_ref_clk0] [get_bd_intf_pins hbm_ref_clk_0] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins axi_noc_cips/hbm_ref_clk1] [get_bd_intf_pins hbm_ref_clk_1] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins axi_noc_cips/S01_AXI] [get_bd_intf_pins S01_AXI] + connect_bd_intf_net -intf_net Conn9 [get_bd_intf_pins axi_noc_cips/S00_AXI] [get_bd_intf_pins S00_AXI] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins axi_noc_cips/S02_AXI] [get_bd_intf_pins S02_AXI] + connect_bd_intf_net -intf_net Conn11 [get_bd_intf_pins axi_noc_cips/M00_AXI] [get_bd_intf_pins M00_AXI] + connect_bd_intf_net -intf_net Conn13 [get_bd_intf_pins axi_noc_cips/HBM02_AXI] [get_bd_intf_pins HBM02_AXI] + connect_bd_intf_net -intf_net Conn14 [get_bd_intf_pins axi_noc_cips/HBM03_AXI] [get_bd_intf_pins HBM03_AXI] + connect_bd_intf_net -intf_net Conn15 [get_bd_intf_pins axi_noc_cips/HBM04_AXI] [get_bd_intf_pins HBM04_AXI] + connect_bd_intf_net -intf_net Conn16 [get_bd_intf_pins axi_noc_cips/HBM05_AXI] [get_bd_intf_pins HBM05_AXI] + connect_bd_intf_net -intf_net Conn17 [get_bd_intf_pins axi_noc_cips/HBM06_AXI] [get_bd_intf_pins HBM06_AXI] + connect_bd_intf_net -intf_net Conn18 [get_bd_intf_pins axi_noc_cips/HBM07_AXI] [get_bd_intf_pins HBM07_AXI] + connect_bd_intf_net -intf_net Conn19 [get_bd_intf_pins axi_noc_cips/HBM08_AXI] [get_bd_intf_pins HBM08_AXI] + connect_bd_intf_net -intf_net Conn20 [get_bd_intf_pins axi_noc_cips/HBM09_AXI] [get_bd_intf_pins HBM09_AXI] + connect_bd_intf_net -intf_net Conn21 [get_bd_intf_pins axi_noc_cips/HBM10_AXI] [get_bd_intf_pins HBM10_AXI] + connect_bd_intf_net -intf_net Conn22 [get_bd_intf_pins axi_noc_cips/HBM11_AXI] [get_bd_intf_pins HBM11_AXI] + connect_bd_intf_net -intf_net Conn23 [get_bd_intf_pins axi_noc_cips/HBM12_AXI] [get_bd_intf_pins HBM12_AXI] + connect_bd_intf_net -intf_net Conn24 [get_bd_intf_pins axi_noc_cips/HBM13_AXI] [get_bd_intf_pins HBM13_AXI] + connect_bd_intf_net -intf_net Conn25 [get_bd_intf_pins axi_noc_cips/HBM14_AXI] [get_bd_intf_pins HBM14_AXI] + connect_bd_intf_net -intf_net Conn26 [get_bd_intf_pins axi_noc_cips/HBM15_AXI] [get_bd_intf_pins HBM15_AXI] + connect_bd_intf_net -intf_net Conn27 [get_bd_intf_pins axi_noc_cips/HBM16_AXI] [get_bd_intf_pins HBM16_AXI] + connect_bd_intf_net -intf_net Conn28 [get_bd_intf_pins axi_noc_cips/HBM17_AXI] [get_bd_intf_pins HBM17_AXI] + connect_bd_intf_net -intf_net Conn29 [get_bd_intf_pins axi_noc_cips/HBM18_AXI] [get_bd_intf_pins HBM18_AXI] + connect_bd_intf_net -intf_net Conn30 [get_bd_intf_pins axi_noc_cips/HBM19_AXI] [get_bd_intf_pins HBM19_AXI] + connect_bd_intf_net -intf_net Conn31 [get_bd_intf_pins axi_noc_cips/HBM20_AXI] [get_bd_intf_pins HBM20_AXI] + connect_bd_intf_net -intf_net Conn32 [get_bd_intf_pins axi_noc_cips/HBM21_AXI] [get_bd_intf_pins HBM21_AXI] + connect_bd_intf_net -intf_net Conn33 [get_bd_intf_pins axi_noc_cips/HBM22_AXI] [get_bd_intf_pins HBM22_AXI] + connect_bd_intf_net -intf_net Conn34 [get_bd_intf_pins axi_noc_cips/HBM23_AXI] [get_bd_intf_pins HBM23_AXI] + connect_bd_intf_net -intf_net Conn35 [get_bd_intf_pins axi_noc_cips/HBM24_AXI] [get_bd_intf_pins HBM24_AXI] + connect_bd_intf_net -intf_net Conn36 [get_bd_intf_pins axi_noc_cips/HBM25_AXI] [get_bd_intf_pins HBM25_AXI] + connect_bd_intf_net -intf_net Conn37 [get_bd_intf_pins axi_noc_cips/HBM26_AXI] [get_bd_intf_pins HBM26_AXI] + connect_bd_intf_net -intf_net Conn38 [get_bd_intf_pins axi_noc_cips/HBM27_AXI] [get_bd_intf_pins HBM27_AXI] + connect_bd_intf_net -intf_net Conn39 [get_bd_intf_pins axi_noc_cips/HBM28_AXI] [get_bd_intf_pins HBM28_AXI] + connect_bd_intf_net -intf_net Conn40 [get_bd_intf_pins axi_noc_cips/HBM29_AXI] [get_bd_intf_pins HBM29_AXI] + connect_bd_intf_net -intf_net Conn41 [get_bd_intf_pins axi_noc_cips/HBM30_AXI] [get_bd_intf_pins HBM30_AXI] + connect_bd_intf_net -intf_net Conn42 [get_bd_intf_pins axi_noc_cips/HBM31_AXI] [get_bd_intf_pins HBM31_AXI] + connect_bd_intf_net -intf_net Conn43 [get_bd_intf_pins axi_noc_cips/HBM32_AXI] [get_bd_intf_pins HBM32_AXI] + connect_bd_intf_net -intf_net Conn44 [get_bd_intf_pins axi_noc_cips/HBM33_AXI] [get_bd_intf_pins HBM33_AXI] + connect_bd_intf_net -intf_net Conn45 [get_bd_intf_pins axi_noc_cips/HBM34_AXI] [get_bd_intf_pins HBM34_AXI] + connect_bd_intf_net -intf_net Conn46 [get_bd_intf_pins axi_noc_cips/HBM35_AXI] [get_bd_intf_pins HBM35_AXI] + connect_bd_intf_net -intf_net Conn47 [get_bd_intf_pins axi_noc_cips/HBM36_AXI] [get_bd_intf_pins HBM36_AXI] + connect_bd_intf_net -intf_net Conn48 [get_bd_intf_pins axi_noc_cips/HBM37_AXI] [get_bd_intf_pins HBM37_AXI] + connect_bd_intf_net -intf_net Conn49 [get_bd_intf_pins axi_noc_cips/HBM38_AXI] [get_bd_intf_pins HBM38_AXI] + connect_bd_intf_net -intf_net Conn50 [get_bd_intf_pins axi_noc_cips/HBM39_AXI] [get_bd_intf_pins HBM39_AXI] + connect_bd_intf_net -intf_net Conn51 [get_bd_intf_pins axi_noc_cips/HBM40_AXI] [get_bd_intf_pins HBM40_AXI] + connect_bd_intf_net -intf_net Conn52 [get_bd_intf_pins axi_noc_cips/HBM41_AXI] [get_bd_intf_pins HBM41_AXI] + connect_bd_intf_net -intf_net Conn53 [get_bd_intf_pins axi_noc_cips/HBM42_AXI] [get_bd_intf_pins HBM42_AXI] + connect_bd_intf_net -intf_net Conn54 [get_bd_intf_pins axi_noc_cips/HBM43_AXI] [get_bd_intf_pins HBM43_AXI] + connect_bd_intf_net -intf_net Conn55 [get_bd_intf_pins axi_noc_cips/HBM44_AXI] [get_bd_intf_pins HBM44_AXI] + connect_bd_intf_net -intf_net Conn56 [get_bd_intf_pins axi_noc_cips/HBM45_AXI] [get_bd_intf_pins HBM45_AXI] + connect_bd_intf_net -intf_net Conn57 [get_bd_intf_pins axi_noc_cips/HBM46_AXI] [get_bd_intf_pins HBM46_AXI] + connect_bd_intf_net -intf_net Conn58 [get_bd_intf_pins axi_noc_cips/HBM47_AXI] [get_bd_intf_pins HBM47_AXI] + connect_bd_intf_net -intf_net Conn59 [get_bd_intf_pins axi_noc_cips/HBM48_AXI] [get_bd_intf_pins HBM48_AXI] + connect_bd_intf_net -intf_net Conn60 [get_bd_intf_pins axi_noc_cips/HBM49_AXI] [get_bd_intf_pins HBM49_AXI] + connect_bd_intf_net -intf_net Conn61 [get_bd_intf_pins axi_noc_cips/HBM50_AXI] [get_bd_intf_pins HBM50_AXI] + connect_bd_intf_net -intf_net Conn62 [get_bd_intf_pins axi_noc_cips/HBM51_AXI] [get_bd_intf_pins HBM51_AXI] + connect_bd_intf_net -intf_net Conn63 [get_bd_intf_pins axi_noc_cips/HBM52_AXI] [get_bd_intf_pins HBM52_AXI] + connect_bd_intf_net -intf_net Conn64 [get_bd_intf_pins axi_noc_cips/HBM53_AXI] [get_bd_intf_pins HBM53_AXI] + connect_bd_intf_net -intf_net Conn65 [get_bd_intf_pins axi_noc_cips/HBM54_AXI] [get_bd_intf_pins HBM54_AXI] + connect_bd_intf_net -intf_net Conn66 [get_bd_intf_pins axi_noc_cips/HBM55_AXI] [get_bd_intf_pins HBM55_AXI] + connect_bd_intf_net -intf_net Conn67 [get_bd_intf_pins axi_noc_cips/HBM56_AXI] [get_bd_intf_pins HBM56_AXI] + connect_bd_intf_net -intf_net Conn68 [get_bd_intf_pins axi_noc_cips/HBM57_AXI] [get_bd_intf_pins HBM57_AXI] + connect_bd_intf_net -intf_net Conn69 [get_bd_intf_pins axi_noc_cips/HBM58_AXI] [get_bd_intf_pins HBM58_AXI] + connect_bd_intf_net -intf_net Conn70 [get_bd_intf_pins axi_noc_cips/HBM59_AXI] [get_bd_intf_pins HBM59_AXI] + connect_bd_intf_net -intf_net Conn71 [get_bd_intf_pins axi_noc_cips/HBM60_AXI] [get_bd_intf_pins HBM60_AXI] + connect_bd_intf_net -intf_net Conn72 [get_bd_intf_pins axi_noc_cips/HBM61_AXI] [get_bd_intf_pins HBM61_AXI] + connect_bd_intf_net -intf_net Conn73 [get_bd_intf_pins axi_noc_cips/HBM62_AXI] [get_bd_intf_pins HBM62_AXI] + connect_bd_intf_net -intf_net Conn74 [get_bd_intf_pins axi_noc_cips/HBM63_AXI] [get_bd_intf_pins HBM63_AXI] + connect_bd_intf_net -intf_net Conn79 [get_bd_intf_pins axi_noc_cips/S00_INI] [get_bd_intf_pins S00_INI] + connect_bd_intf_net -intf_net Conn80 [get_bd_intf_pins axi_noc_cips/S01_INI] [get_bd_intf_pins S01_INI] + connect_bd_intf_net -intf_net Conn81 [get_bd_intf_pins axi_noc_cips/S02_INI] [get_bd_intf_pins S02_INI] + connect_bd_intf_net -intf_net Conn82 [get_bd_intf_pins axi_noc_cips/S03_INI] [get_bd_intf_pins S03_INI] + connect_bd_intf_net -intf_net Conn83 [get_bd_intf_pins axi_noc_cips/S04_INI] [get_bd_intf_pins S04_INI] + connect_bd_intf_net -intf_net Conn84 [get_bd_intf_pins axi_noc_cips/S05_INI] [get_bd_intf_pins S05_INI] + connect_bd_intf_net -intf_net Conn85 [get_bd_intf_pins axi_noc_cips/S06_INI] [get_bd_intf_pins S06_INI] + connect_bd_intf_net -intf_net Conn86 [get_bd_intf_pins axi_noc_cips/S07_INI] [get_bd_intf_pins S07_INI] + connect_bd_intf_net -intf_net Conn87 [get_bd_intf_pins axi_noc_cips/S08_INI] [get_bd_intf_pins S08_INI] + connect_bd_intf_net -intf_net Conn88 [get_bd_intf_pins axi_noc_cips/S09_INI] [get_bd_intf_pins S09_INI] + connect_bd_intf_net -intf_net Conn89 [get_bd_intf_pins axi_noc_cips/S10_INI] [get_bd_intf_pins S10_INI] + connect_bd_intf_net -intf_net Conn90 [get_bd_intf_pins axi_noc_cips/S11_INI] [get_bd_intf_pins S11_INI] + connect_bd_intf_net -intf_net Conn91 [get_bd_intf_pins axi_noc_cips/S12_INI] [get_bd_intf_pins S12_INI] + connect_bd_intf_net -intf_net Conn92 [get_bd_intf_pins axi_noc_cips/S13_INI] [get_bd_intf_pins S13_INI] + connect_bd_intf_net -intf_net Conn93 [get_bd_intf_pins axi_noc_cips/S14_INI] [get_bd_intf_pins S14_INI] + connect_bd_intf_net -intf_net Conn94 [get_bd_intf_pins axi_noc_cips/S15_INI] [get_bd_intf_pins S15_INI] + connect_bd_intf_net -intf_net Conn95 [get_bd_intf_pins axi_noc_cips/S16_INI] [get_bd_intf_pins S16_INI] + connect_bd_intf_net -intf_net Conn96 [get_bd_intf_pins axi_noc_cips/S17_INI] [get_bd_intf_pins S17_INI] + connect_bd_intf_net -intf_net Conn97 [get_bd_intf_pins axi_noc_cips/S18_INI] [get_bd_intf_pins S18_INI] + connect_bd_intf_net -intf_net Conn98 [get_bd_intf_pins axi_noc_cips/S19_INI] [get_bd_intf_pins S19_INI] + connect_bd_intf_net -intf_net Conn99 [get_bd_intf_pins axi_noc_cips/S20_INI] [get_bd_intf_pins S20_INI1] + connect_bd_intf_net -intf_net Conn100 [get_bd_intf_pins axi_noc_cips/S21_INI] [get_bd_intf_pins S21_INI1] + connect_bd_intf_net -intf_net Conn101 [get_bd_intf_pins axi_noc_cips/S22_INI] [get_bd_intf_pins S22_INI1] + connect_bd_intf_net -intf_net Conn102 [get_bd_intf_pins axi_noc_cips/S23_INI] [get_bd_intf_pins S23_INI1] + connect_bd_intf_net -intf_net Conn103 [get_bd_intf_pins axi_noc_cips/M05_INI] [get_bd_intf_pins M05_INI] + connect_bd_intf_net -intf_net Conn104 [get_bd_intf_pins axi_noc_cips/M04_INI] [get_bd_intf_pins M04_INI] + connect_bd_intf_net -intf_net HBM00_AXI_1 [get_bd_intf_pins HBM00_AXI] [get_bd_intf_pins axi_noc_cips/HBM00_AXI] + connect_bd_intf_net -intf_net HBM01_AXI_1 [get_bd_intf_pins HBM01_AXI] [get_bd_intf_pins axi_noc_cips/HBM01_AXI] + connect_bd_intf_net -intf_net axi_noc_cips_M00_INI [get_bd_intf_pins axi_noc_cips/M00_INI] [get_bd_intf_pins axi_noc_mc_ddr4_0/S00_INI] + connect_bd_intf_net -intf_net axi_noc_cips_M01_AXI [get_bd_intf_pins M02_AXI] [get_bd_intf_pins axi_noc_cips/M01_AXI] + connect_bd_intf_net -intf_net axi_noc_cips_M01_INI [get_bd_intf_pins axi_noc_cips/M01_INI] [get_bd_intf_pins axi_noc_mc_ddr4_0/S01_INI] + connect_bd_intf_net -intf_net axi_noc_cips_M02_INI [get_bd_intf_pins axi_noc_cips/M02_INI] [get_bd_intf_pins axi_noc_mc_ddr4_1/S00_INI] + connect_bd_intf_net -intf_net axi_noc_cips_M03_INI [get_bd_intf_pins axi_noc_cips/M03_INI] [get_bd_intf_pins axi_noc_mc_ddr4_1/S01_INI] + + # Create port connections + connect_bd_net -net aclk0_1 [get_bd_pins aclk0] \ + [get_bd_pins axi_noc_mc_ddr4_1/aclk0] \ + [get_bd_pins axi_noc_cips/aclk4] + connect_bd_net -net aclk1_1 [get_bd_pins aclk1] \ + [get_bd_pins axi_noc_cips/aclk1] + connect_bd_net -net aclk2_1 [get_bd_pins aclk2] \ + [get_bd_pins axi_noc_cips/aclk2] + connect_bd_net -net aclk3_1 [get_bd_pins aclk3] \ + [get_bd_pins axi_noc_cips/aclk3] + connect_bd_net -net aclk4_1 [get_bd_pins aclk4] \ + [get_bd_pins axi_noc_cips/aclk0] + connect_bd_net -net aclk5_1 [get_bd_pins aclk5] \ + [get_bd_pins axi_noc_cips/aclk5] + connect_bd_net -net aclk6_1 [get_bd_pins aclk6] \ + [get_bd_pins axi_noc_cips/aclk6] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: static_region +proc create_hier_cell_static_region { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_static_region() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk0_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 CH0_DDR4_0_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 CH0_DDR4_0_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 hbm_ref_clk_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk0_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 hbm_ref_clk_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 gt_pcie_refclk + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 smbus_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt_pciea1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_axilite + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_3 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_4 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_5 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_6 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_7 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_8 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_9 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_10 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_11 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_12 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_13 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_14 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_15 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_16 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_17 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_18 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_19 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_20 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_21 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_22 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_23 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_24 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_25 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_26 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_27 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_28 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_29 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_30 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_31 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_32 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_33 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_34 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_35 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_36 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_37 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_38 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_39 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_40 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_41 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_42 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_43 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_44 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_45 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_46 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_47 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_48 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_49 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_50 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_51 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_52 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_53 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_54 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_55 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_56 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_57 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_58 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_59 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_60 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_61 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_62 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_63 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S01_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S02_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S03_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S04_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S05_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S06_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S07_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S08_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S09_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S10_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S11_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S12_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S13_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S14_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S15_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S16_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S17_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S18_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S19_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S20_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S21_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S22_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S23_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 NOC_CPM_PCIE_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M05_INI + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M04_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS2 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS3 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS3 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS4 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS4 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS5 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS5 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS6 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS6 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS7 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS7 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS8 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS8 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS9 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS9 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS10 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS10 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS11 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS11 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS12 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS12 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS13 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS13 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS14 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS14 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS15 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS15 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI2 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI3 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI3 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI4 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI4 + + + # Create pins + create_bd_pin -dir O -type clk pl0_ref_clk + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pl_periph + create_bd_pin -dir O -type clk clk_out1 + create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn + + # Create instance: noc + create_hier_cell_noc $hier_obj noc + + # Create instance: aved + create_hier_cell_aved $hier_obj aved + + # Create instance: clk_wizard_0, and set properties + set clk_wizard_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard:1.0 clk_wizard_0 ] + set_property -dict [list \ + CONFIG.CLKOUT_DRIVES {BUFG,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG} \ + CONFIG.CLKOUT_DYN_PS {None,None,None,None,None,None,None} \ + CONFIG.CLKOUT_GROUPING {Auto,Auto,Auto,Auto,Auto,Auto,Auto} \ + CONFIG.CLKOUT_MATCHED_ROUTING {false,false,false,false,false,false,false} \ + CONFIG.CLKOUT_PORT {clk_out1,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7} \ + CONFIG.CLKOUT_REQUESTED_DUTY_CYCLE {50.000,50.000,50.000,50.000,50.000,50.000,50.000} \ + CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY {300,100.000,100.000,100.000,100.000,100.000,100.000} \ + CONFIG.CLKOUT_REQUESTED_PHASE {0.000,0.000,0.000,0.000,0.000,0.000,0.000} \ + CONFIG.CLKOUT_USED {true,false,false,false,false,false,false} \ + CONFIG.RESET_TYPE {ACTIVE_LOW} \ + CONFIG.USE_DYN_RECONFIG {false} \ + ] $clk_wizard_0 + + + # Create instance: proc_sys_reset_1, and set properties + set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] + + # Create instance: dfx_decoupler_0, and set properties + set dfx_decoupler_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:dfx_decoupler:1.0 dfx_decoupler_0 ] + set_property -dict [list \ + CONFIG.ALL_PARAMS {INTF {intf_0 {ID 0 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1}\ +AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH\ +1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT\ +1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH\ +0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST\ +{WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT\ +0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_1 {ID 1 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID\ +{WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0\ +PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK\ +{WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT\ +1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_2 {ID 2 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_3 {ID 3 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_4 {ID 4 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_5 {ID 5 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_6 {ID 6 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_7 {ID 7 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_8 {ID 8 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_9 {ID 9 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_10 {ID 10 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_11 {ID 11 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_12 {ID 12 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_13 {ID 13 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_14 {ID 14 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_15 {ID 15 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_16 {ID 16 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_17 {ID 17 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_18 {ID 18 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_19 {ID 19 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_20 {ID 20 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_21 {ID 21 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_22 {ID 22 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_23 {ID 23 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_24 {ID 24 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_25 {ID 25 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_26 {ID 26 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_27 {ID 27 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_28 {ID 28 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_29 {ID 29 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_30 {ID 30 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_31 {ID 31 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_32 {ID 32 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_33 {ID 33 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_34 {ID 34 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_35 {ID 35 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_36 {ID 36 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_37 {ID 37 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_38 {ID 38 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_39 {ID 39 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_40 {ID 40 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_41 {ID 41 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_42 {ID 42 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_43 {ID 43 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_44 {ID 44 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_45 {ID 45 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_46 {ID 46 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_47 {ID 47 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_48 {ID 48 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_49 {ID 49 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_50 {ID 50 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_51 {ID 51 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_52 {ID 52 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_53 {ID 53 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_54 {ID 54 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_55 {ID 55 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_56 {ID 56 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_57 {ID 57 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_58 {ID 58 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_59 {ID 59 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_60 {ID 60 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_61 {ID 61 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH\ +0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT\ +0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH\ +1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1}\ +WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT\ +0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS\ +{WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}} intf_62 {ID 62 VLNV xilinx.com:interface:aximm_rtl:1.0\ +MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1}\ +RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT 1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH\ +3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT\ +0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT\ +0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0 PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH\ +0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER\ +{WIDTH 0 PRESENT 0}}} intf_63 {ID 63 VLNV xilinx.com:interface:aximm_rtl:1.0 MODE master PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 0 PRESENT 0} ARREADY {WIDTH 0 PRESENT 0} AWVALID {WIDTH 1 PRESENT 1} AWREADY\ +{WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 0 PRESENT 0} RREADY {WIDTH 0 PRESENT 0} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 1 PRESENT\ +1} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 0} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION\ +{WIDTH 4 PRESENT 1} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 1 PRESENT 1} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT\ +0} BID {WIDTH 1 PRESENT 1} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 0 PRESENT 0} ARLEN {WIDTH 0 PRESENT 0} ARSIZE {WIDTH 0 PRESENT 0} ARBURST {WIDTH 0\ +PRESENT 0} ARLOCK {WIDTH 0 PRESENT 0} ARCACHE {WIDTH 0 PRESENT 0} ARPROT {WIDTH 0 PRESENT 0} ARREGION {WIDTH 0 PRESENT 0} ARQOS {WIDTH 0 PRESENT 0} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA\ +{WIDTH 0 PRESENT 0} RRESP {WIDTH 0 PRESENT 0} RLAST {WIDTH 0 PRESENT 0} RUSER {WIDTH 0 PRESENT 0}}}}} \ + CONFIG.GUI_INTERFACE_NAME {intf_0} \ + CONFIG.GUI_INTERFACE_PROTOCOL {axi4} \ + CONFIG.GUI_SELECT_INTERFACE {0} \ + CONFIG.GUI_SELECT_MODE {master} \ + CONFIG.GUI_SELECT_VLNV {xilinx.com:interface:aximm_rtl:1.0} \ + ] $dfx_decoupler_0 + + + # Create instance: dcmac_noc + create_hier_cell_dcmac_noc $hier_obj dcmac_noc + + # Create instance: axi_noc_0, and set properties + set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $axi_noc_0 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /static_region/axi_noc_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /static_region/axi_noc_0/aclk0] + + # Create instance: axi_noc_1, and set properties + set axi_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_1 ] + set_property -dict [list \ + CONFIG.MI_SIDEBAND_PINS {} \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_1 + + + set_property -dict [ list \ + CONFIG.CATEGORY {ps_pcie} \ + ] [get_bd_intf_pins /static_region/axi_noc_1/M00_AXI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/axi_noc_1/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {} \ + ] [get_bd_pins /static_region/axi_noc_1/aclk0] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /static_region/axi_noc_1/aclk1] + + # Create instance: axi_register_slice_0, and set properties + set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ] + + # Create instance: axi_register_slice_1, and set properties + set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ] + + # Create instance: axi_register_slice_2, and set properties + set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ] + + # Create instance: axi_register_slice_3, and set properties + set axi_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_3 ] + + # Create instance: axi_register_slice_4, and set properties + set axi_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_4 ] + + # Create instance: util_vector_logic_0, and set properties + set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $util_vector_logic_0 + + + # Create interface connections + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins dfx_decoupler_0/rp_intf_2] [get_bd_intf_pins rp_intf_2] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins dfx_decoupler_0/rp_intf_3] [get_bd_intf_pins rp_intf_3] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins dfx_decoupler_0/rp_intf_4] [get_bd_intf_pins rp_intf_4] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins noc/sys_clk0_0] [get_bd_intf_pins sys_clk0_0] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins noc/CH0_DDR4_0_0] [get_bd_intf_pins CH0_DDR4_0_0] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins noc/CH0_DDR4_0_1] [get_bd_intf_pins CH0_DDR4_0_1] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins noc/hbm_ref_clk_0] [get_bd_intf_pins hbm_ref_clk_0] + connect_bd_intf_net -intf_net Conn9 [get_bd_intf_pins noc/sys_clk0_1] [get_bd_intf_pins sys_clk0_1] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins dfx_decoupler_0/rp_intf_5] [get_bd_intf_pins rp_intf_5] + connect_bd_intf_net -intf_net Conn11 [get_bd_intf_pins dfx_decoupler_0/rp_intf_6] [get_bd_intf_pins rp_intf_6] + connect_bd_intf_net -intf_net Conn12 [get_bd_intf_pins dfx_decoupler_0/rp_intf_7] [get_bd_intf_pins rp_intf_7] + connect_bd_intf_net -intf_net Conn13 [get_bd_intf_pins dfx_decoupler_0/rp_intf_8] [get_bd_intf_pins rp_intf_8] + connect_bd_intf_net -intf_net Conn14 [get_bd_intf_pins dfx_decoupler_0/rp_intf_9] [get_bd_intf_pins rp_intf_9] + connect_bd_intf_net -intf_net Conn15 [get_bd_intf_pins dfx_decoupler_0/rp_intf_10] [get_bd_intf_pins rp_intf_10] + connect_bd_intf_net -intf_net Conn16 [get_bd_intf_pins dfx_decoupler_0/rp_intf_11] [get_bd_intf_pins rp_intf_11] + connect_bd_intf_net -intf_net Conn17 [get_bd_intf_pins dfx_decoupler_0/rp_intf_12] [get_bd_intf_pins rp_intf_12] + connect_bd_intf_net -intf_net Conn18 [get_bd_intf_pins dfx_decoupler_0/rp_intf_13] [get_bd_intf_pins rp_intf_13] + connect_bd_intf_net -intf_net Conn19 [get_bd_intf_pins dfx_decoupler_0/rp_intf_14] [get_bd_intf_pins rp_intf_14] + connect_bd_intf_net -intf_net Conn20 [get_bd_intf_pins dfx_decoupler_0/rp_intf_15] [get_bd_intf_pins rp_intf_15] + connect_bd_intf_net -intf_net Conn21 [get_bd_intf_pins dfx_decoupler_0/rp_intf_16] [get_bd_intf_pins rp_intf_16] + connect_bd_intf_net -intf_net Conn22 [get_bd_intf_pins dfx_decoupler_0/rp_intf_17] [get_bd_intf_pins rp_intf_17] + connect_bd_intf_net -intf_net Conn23 [get_bd_intf_pins dfx_decoupler_0/rp_intf_18] [get_bd_intf_pins rp_intf_18] + connect_bd_intf_net -intf_net Conn24 [get_bd_intf_pins dfx_decoupler_0/rp_intf_19] [get_bd_intf_pins rp_intf_19] + connect_bd_intf_net -intf_net Conn25 [get_bd_intf_pins dfx_decoupler_0/rp_intf_20] [get_bd_intf_pins rp_intf_20] + connect_bd_intf_net -intf_net Conn26 [get_bd_intf_pins dfx_decoupler_0/rp_intf_21] [get_bd_intf_pins rp_intf_21] + connect_bd_intf_net -intf_net Conn27 [get_bd_intf_pins dfx_decoupler_0/rp_intf_22] [get_bd_intf_pins rp_intf_22] + connect_bd_intf_net -intf_net Conn28 [get_bd_intf_pins dfx_decoupler_0/rp_intf_23] [get_bd_intf_pins rp_intf_23] + connect_bd_intf_net -intf_net Conn29 [get_bd_intf_pins dfx_decoupler_0/rp_intf_24] [get_bd_intf_pins rp_intf_24] + connect_bd_intf_net -intf_net Conn30 [get_bd_intf_pins dfx_decoupler_0/rp_intf_25] [get_bd_intf_pins rp_intf_25] + connect_bd_intf_net -intf_net Conn31 [get_bd_intf_pins dfx_decoupler_0/rp_intf_26] [get_bd_intf_pins rp_intf_26] + connect_bd_intf_net -intf_net Conn32 [get_bd_intf_pins dfx_decoupler_0/rp_intf_27] [get_bd_intf_pins rp_intf_27] + connect_bd_intf_net -intf_net Conn33 [get_bd_intf_pins dfx_decoupler_0/rp_intf_28] [get_bd_intf_pins rp_intf_28] + connect_bd_intf_net -intf_net Conn34 [get_bd_intf_pins dfx_decoupler_0/rp_intf_29] [get_bd_intf_pins rp_intf_29] + connect_bd_intf_net -intf_net Conn35 [get_bd_intf_pins dfx_decoupler_0/rp_intf_30] [get_bd_intf_pins rp_intf_30] + connect_bd_intf_net -intf_net Conn36 [get_bd_intf_pins dfx_decoupler_0/rp_intf_31] [get_bd_intf_pins rp_intf_31] + connect_bd_intf_net -intf_net Conn37 [get_bd_intf_pins dfx_decoupler_0/rp_intf_32] [get_bd_intf_pins rp_intf_32] + connect_bd_intf_net -intf_net Conn38 [get_bd_intf_pins dfx_decoupler_0/rp_intf_33] [get_bd_intf_pins rp_intf_33] + connect_bd_intf_net -intf_net Conn39 [get_bd_intf_pins dfx_decoupler_0/rp_intf_34] [get_bd_intf_pins rp_intf_34] + connect_bd_intf_net -intf_net Conn40 [get_bd_intf_pins dfx_decoupler_0/rp_intf_35] [get_bd_intf_pins rp_intf_35] + connect_bd_intf_net -intf_net Conn41 [get_bd_intf_pins dfx_decoupler_0/rp_intf_36] [get_bd_intf_pins rp_intf_36] + connect_bd_intf_net -intf_net Conn42 [get_bd_intf_pins dfx_decoupler_0/rp_intf_37] [get_bd_intf_pins rp_intf_37] + connect_bd_intf_net -intf_net Conn43 [get_bd_intf_pins dfx_decoupler_0/rp_intf_38] [get_bd_intf_pins rp_intf_38] + connect_bd_intf_net -intf_net Conn44 [get_bd_intf_pins dfx_decoupler_0/rp_intf_39] [get_bd_intf_pins rp_intf_39] + connect_bd_intf_net -intf_net Conn45 [get_bd_intf_pins dfx_decoupler_0/rp_intf_40] [get_bd_intf_pins rp_intf_40] + connect_bd_intf_net -intf_net Conn46 [get_bd_intf_pins dfx_decoupler_0/rp_intf_41] [get_bd_intf_pins rp_intf_41] + connect_bd_intf_net -intf_net Conn47 [get_bd_intf_pins dfx_decoupler_0/rp_intf_42] [get_bd_intf_pins rp_intf_42] + connect_bd_intf_net -intf_net Conn48 [get_bd_intf_pins dfx_decoupler_0/rp_intf_43] [get_bd_intf_pins rp_intf_43] + connect_bd_intf_net -intf_net Conn49 [get_bd_intf_pins dfx_decoupler_0/rp_intf_44] [get_bd_intf_pins rp_intf_44] + connect_bd_intf_net -intf_net Conn50 [get_bd_intf_pins dfx_decoupler_0/rp_intf_45] [get_bd_intf_pins rp_intf_45] + connect_bd_intf_net -intf_net Conn51 [get_bd_intf_pins dfx_decoupler_0/rp_intf_46] [get_bd_intf_pins rp_intf_46] + connect_bd_intf_net -intf_net Conn52 [get_bd_intf_pins dfx_decoupler_0/rp_intf_47] [get_bd_intf_pins rp_intf_47] + connect_bd_intf_net -intf_net Conn53 [get_bd_intf_pins dfx_decoupler_0/rp_intf_48] [get_bd_intf_pins rp_intf_48] + connect_bd_intf_net -intf_net Conn54 [get_bd_intf_pins dfx_decoupler_0/rp_intf_49] [get_bd_intf_pins rp_intf_49] + connect_bd_intf_net -intf_net Conn55 [get_bd_intf_pins dfx_decoupler_0/rp_intf_50] [get_bd_intf_pins rp_intf_50] + connect_bd_intf_net -intf_net Conn56 [get_bd_intf_pins dfx_decoupler_0/rp_intf_51] [get_bd_intf_pins rp_intf_51] + connect_bd_intf_net -intf_net Conn57 [get_bd_intf_pins dfx_decoupler_0/rp_intf_52] [get_bd_intf_pins rp_intf_52] + connect_bd_intf_net -intf_net Conn58 [get_bd_intf_pins dfx_decoupler_0/rp_intf_53] [get_bd_intf_pins rp_intf_53] + connect_bd_intf_net -intf_net Conn59 [get_bd_intf_pins dfx_decoupler_0/rp_intf_54] [get_bd_intf_pins rp_intf_54] + connect_bd_intf_net -intf_net Conn60 [get_bd_intf_pins dfx_decoupler_0/rp_intf_55] [get_bd_intf_pins rp_intf_55] + connect_bd_intf_net -intf_net Conn61 [get_bd_intf_pins dfx_decoupler_0/rp_intf_56] [get_bd_intf_pins rp_intf_56] + connect_bd_intf_net -intf_net Conn62 [get_bd_intf_pins dfx_decoupler_0/rp_intf_57] [get_bd_intf_pins rp_intf_57] + connect_bd_intf_net -intf_net Conn63 [get_bd_intf_pins dfx_decoupler_0/rp_intf_58] [get_bd_intf_pins rp_intf_58] + connect_bd_intf_net -intf_net Conn64 [get_bd_intf_pins dfx_decoupler_0/rp_intf_59] [get_bd_intf_pins rp_intf_59] + connect_bd_intf_net -intf_net Conn65 [get_bd_intf_pins dfx_decoupler_0/rp_intf_60] [get_bd_intf_pins rp_intf_60] + connect_bd_intf_net -intf_net Conn66 [get_bd_intf_pins dfx_decoupler_0/rp_intf_61] [get_bd_intf_pins rp_intf_61] + connect_bd_intf_net -intf_net Conn67 [get_bd_intf_pins dfx_decoupler_0/rp_intf_62] [get_bd_intf_pins rp_intf_62] + connect_bd_intf_net -intf_net Conn68 [get_bd_intf_pins dfx_decoupler_0/rp_intf_63] [get_bd_intf_pins rp_intf_63] + connect_bd_intf_net -intf_net Conn69 [get_bd_intf_pins dfx_decoupler_0/rp_intf_0] [get_bd_intf_pins rp_intf_0] + connect_bd_intf_net -intf_net Conn70 [get_bd_intf_pins dfx_decoupler_0/rp_intf_1] [get_bd_intf_pins rp_intf_1] + connect_bd_intf_net -intf_net Conn71 [get_bd_intf_pins noc/hbm_ref_clk_1] [get_bd_intf_pins hbm_ref_clk_1] + connect_bd_intf_net -intf_net Conn72 [get_bd_intf_pins aved/gt_pcie_refclk] [get_bd_intf_pins gt_pcie_refclk] + connect_bd_intf_net -intf_net Conn73 [get_bd_intf_pins aved/smbus_0] [get_bd_intf_pins smbus_0] + connect_bd_intf_net -intf_net Conn74 [get_bd_intf_pins aved/gt_pciea1] [get_bd_intf_pins gt_pciea1] + connect_bd_intf_net -intf_net Conn75 [get_bd_intf_pins noc/S00_INI] [get_bd_intf_pins S00_INI] + connect_bd_intf_net -intf_net Conn76 [get_bd_intf_pins noc/S01_INI] [get_bd_intf_pins S01_INI] + connect_bd_intf_net -intf_net Conn77 [get_bd_intf_pins noc/S02_INI] [get_bd_intf_pins S02_INI] + connect_bd_intf_net -intf_net Conn78 [get_bd_intf_pins noc/S03_INI] [get_bd_intf_pins S03_INI] + connect_bd_intf_net -intf_net Conn79 [get_bd_intf_pins noc/S04_INI] [get_bd_intf_pins S04_INI] + connect_bd_intf_net -intf_net Conn80 [get_bd_intf_pins noc/S05_INI] [get_bd_intf_pins S05_INI] + connect_bd_intf_net -intf_net Conn81 [get_bd_intf_pins noc/S06_INI] [get_bd_intf_pins S06_INI] + connect_bd_intf_net -intf_net Conn82 [get_bd_intf_pins noc/S07_INI] [get_bd_intf_pins S07_INI] + connect_bd_intf_net -intf_net Conn83 [get_bd_intf_pins noc/S08_INI] [get_bd_intf_pins S08_INI] + connect_bd_intf_net -intf_net Conn84 [get_bd_intf_pins noc/S09_INI] [get_bd_intf_pins S09_INI] + connect_bd_intf_net -intf_net Conn85 [get_bd_intf_pins noc/S10_INI] [get_bd_intf_pins S10_INI] + connect_bd_intf_net -intf_net Conn86 [get_bd_intf_pins noc/S11_INI] [get_bd_intf_pins S11_INI] + connect_bd_intf_net -intf_net Conn87 [get_bd_intf_pins dcmac_noc/S00_INIS] [get_bd_intf_pins S00_INIS] + connect_bd_intf_net -intf_net Conn88 [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins S_AXI] + connect_bd_intf_net -intf_net Conn89 [get_bd_intf_pins noc/M05_INI] [get_bd_intf_pins M05_INI] + connect_bd_intf_net -intf_net Conn90 [get_bd_intf_pins noc/M04_INI] [get_bd_intf_pins M04_INI] + connect_bd_intf_net -intf_net Conn91 [get_bd_intf_pins dcmac_noc/M00_INIS] [get_bd_intf_pins M00_INIS] + connect_bd_intf_net -intf_net Conn92 [get_bd_intf_pins dcmac_noc/S00_INIS1] [get_bd_intf_pins S00_INIS1] + connect_bd_intf_net -intf_net Conn93 [get_bd_intf_pins dcmac_noc/M00_INIS1] [get_bd_intf_pins M00_INIS1] + connect_bd_intf_net -intf_net Conn94 [get_bd_intf_pins dcmac_noc/S00_INIS2] [get_bd_intf_pins S00_INIS2] + connect_bd_intf_net -intf_net Conn95 [get_bd_intf_pins dcmac_noc/M00_INIS2] [get_bd_intf_pins M00_INIS2] + connect_bd_intf_net -intf_net Conn96 [get_bd_intf_pins dcmac_noc/S00_INIS3] [get_bd_intf_pins S00_INIS3] + connect_bd_intf_net -intf_net Conn97 [get_bd_intf_pins dcmac_noc/M00_INIS3] [get_bd_intf_pins M00_INIS3] + connect_bd_intf_net -intf_net Conn98 [get_bd_intf_pins dcmac_noc/S00_INIS4] [get_bd_intf_pins S00_INIS4] + connect_bd_intf_net -intf_net Conn99 [get_bd_intf_pins dcmac_noc/M00_INIS4] [get_bd_intf_pins M00_INIS4] + connect_bd_intf_net -intf_net Conn100 [get_bd_intf_pins dcmac_noc/S00_INIS5] [get_bd_intf_pins S00_INIS5] + connect_bd_intf_net -intf_net Conn101 [get_bd_intf_pins dcmac_noc/M00_INIS5] [get_bd_intf_pins M00_INIS5] + connect_bd_intf_net -intf_net Conn102 [get_bd_intf_pins dcmac_noc/S00_INIS6] [get_bd_intf_pins S00_INIS6] + connect_bd_intf_net -intf_net Conn103 [get_bd_intf_pins dcmac_noc/M00_INIS6] [get_bd_intf_pins M00_INIS6] + connect_bd_intf_net -intf_net Conn104 [get_bd_intf_pins dcmac_noc/S00_INIS7] [get_bd_intf_pins S00_INIS7] + connect_bd_intf_net -intf_net Conn105 [get_bd_intf_pins dcmac_noc/M00_INIS7] [get_bd_intf_pins M00_INIS7] + connect_bd_intf_net -intf_net Conn106 [get_bd_intf_pins dcmac_noc/S00_INIS8] [get_bd_intf_pins S00_INIS8] + connect_bd_intf_net -intf_net Conn107 [get_bd_intf_pins dcmac_noc/M00_INIS8] [get_bd_intf_pins M00_INIS8] + connect_bd_intf_net -intf_net Conn108 [get_bd_intf_pins dcmac_noc/S00_INIS9] [get_bd_intf_pins S00_INIS9] + connect_bd_intf_net -intf_net Conn109 [get_bd_intf_pins dcmac_noc/M00_INIS9] [get_bd_intf_pins M00_INIS9] + connect_bd_intf_net -intf_net Conn110 [get_bd_intf_pins dcmac_noc/S00_INIS10] [get_bd_intf_pins S00_INIS10] + connect_bd_intf_net -intf_net Conn111 [get_bd_intf_pins dcmac_noc/M00_INIS10] [get_bd_intf_pins M00_INIS10] + connect_bd_intf_net -intf_net Conn112 [get_bd_intf_pins dcmac_noc/S00_INIS11] [get_bd_intf_pins S00_INIS11] + connect_bd_intf_net -intf_net Conn113 [get_bd_intf_pins dcmac_noc/M00_INIS11] [get_bd_intf_pins M00_INIS11] + connect_bd_intf_net -intf_net Conn114 [get_bd_intf_pins dcmac_noc/S00_INIS12] [get_bd_intf_pins S00_INIS12] + connect_bd_intf_net -intf_net Conn115 [get_bd_intf_pins dcmac_noc/M00_INIS12] [get_bd_intf_pins M00_INIS12] + connect_bd_intf_net -intf_net Conn116 [get_bd_intf_pins dcmac_noc/S00_INIS13] [get_bd_intf_pins S00_INIS13] + connect_bd_intf_net -intf_net Conn117 [get_bd_intf_pins dcmac_noc/M00_INIS13] [get_bd_intf_pins M00_INIS13] + connect_bd_intf_net -intf_net Conn118 [get_bd_intf_pins dcmac_noc/S00_INIS14] [get_bd_intf_pins S00_INIS14] + connect_bd_intf_net -intf_net Conn119 [get_bd_intf_pins dcmac_noc/M00_INIS14] [get_bd_intf_pins M00_INIS14] + connect_bd_intf_net -intf_net Conn120 [get_bd_intf_pins dcmac_noc/S00_INIS15] [get_bd_intf_pins S00_INIS15] + connect_bd_intf_net -intf_net Conn121 [get_bd_intf_pins dcmac_noc/M00_INIS15] [get_bd_intf_pins M00_INIS15] + connect_bd_intf_net -intf_net Conn122 [get_bd_intf_pins axi_register_slice_0/M_AXI] [get_bd_intf_pins M_AXI] + connect_bd_intf_net -intf_net Conn123 [get_bd_intf_pins axi_register_slice_1/S_AXI] [get_bd_intf_pins S_AXI1] + connect_bd_intf_net -intf_net Conn124 [get_bd_intf_pins axi_register_slice_1/M_AXI] [get_bd_intf_pins M_AXI1] + connect_bd_intf_net -intf_net Conn125 [get_bd_intf_pins axi_register_slice_2/S_AXI] [get_bd_intf_pins S_AXI2] + connect_bd_intf_net -intf_net Conn126 [get_bd_intf_pins axi_register_slice_2/M_AXI] [get_bd_intf_pins M_AXI2] + connect_bd_intf_net -intf_net Conn127 [get_bd_intf_pins axi_register_slice_3/S_AXI] [get_bd_intf_pins S_AXI3] + connect_bd_intf_net -intf_net Conn128 [get_bd_intf_pins axi_register_slice_3/M_AXI] [get_bd_intf_pins M_AXI3] + connect_bd_intf_net -intf_net Conn129 [get_bd_intf_pins axi_register_slice_4/S_AXI] [get_bd_intf_pins S_AXI4] + connect_bd_intf_net -intf_net Conn130 [get_bd_intf_pins axi_register_slice_4/M_AXI] [get_bd_intf_pins M_AXI4] + connect_bd_intf_net -intf_net HBM00_AXI_1 [get_bd_intf_pins noc/HBM00_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_0] + connect_bd_intf_net -intf_net HBM01_AXI_1 [get_bd_intf_pins noc/HBM01_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_1] + connect_bd_intf_net -intf_net HBM02_AXI_1 [get_bd_intf_pins noc/HBM02_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_2] + connect_bd_intf_net -intf_net HBM03_AXI_1 [get_bd_intf_pins noc/HBM03_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_3] + connect_bd_intf_net -intf_net HBM04_AXI_1 [get_bd_intf_pins noc/HBM04_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_4] + connect_bd_intf_net -intf_net HBM05_AXI_1 [get_bd_intf_pins noc/HBM05_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_5] + connect_bd_intf_net -intf_net HBM06_AXI_1 [get_bd_intf_pins noc/HBM06_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_6] + connect_bd_intf_net -intf_net HBM07_AXI_1 [get_bd_intf_pins noc/HBM07_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_7] + connect_bd_intf_net -intf_net HBM08_AXI_1 [get_bd_intf_pins noc/HBM08_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_8] + connect_bd_intf_net -intf_net HBM09_AXI_1 [get_bd_intf_pins noc/HBM09_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_9] + connect_bd_intf_net -intf_net HBM10_AXI_1 [get_bd_intf_pins noc/HBM10_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_10] + connect_bd_intf_net -intf_net HBM11_AXI_1 [get_bd_intf_pins noc/HBM11_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_11] + connect_bd_intf_net -intf_net HBM12_AXI_1 [get_bd_intf_pins noc/HBM12_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_12] + connect_bd_intf_net -intf_net HBM13_AXI_1 [get_bd_intf_pins noc/HBM13_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_13] + connect_bd_intf_net -intf_net HBM14_AXI_1 [get_bd_intf_pins noc/HBM14_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_14] + connect_bd_intf_net -intf_net HBM15_AXI_1 [get_bd_intf_pins noc/HBM15_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_15] + connect_bd_intf_net -intf_net HBM16_AXI_1 [get_bd_intf_pins noc/HBM16_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_16] + connect_bd_intf_net -intf_net HBM17_AXI_1 [get_bd_intf_pins noc/HBM17_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_17] + connect_bd_intf_net -intf_net HBM18_AXI_1 [get_bd_intf_pins noc/HBM18_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_18] + connect_bd_intf_net -intf_net HBM19_AXI_1 [get_bd_intf_pins noc/HBM19_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_19] + connect_bd_intf_net -intf_net HBM20_AXI_1 [get_bd_intf_pins noc/HBM20_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_20] + connect_bd_intf_net -intf_net HBM21_AXI_1 [get_bd_intf_pins noc/HBM21_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_21] + connect_bd_intf_net -intf_net HBM22_AXI_1 [get_bd_intf_pins noc/HBM22_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_22] + connect_bd_intf_net -intf_net HBM23_AXI_1 [get_bd_intf_pins noc/HBM23_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_23] + connect_bd_intf_net -intf_net HBM24_AXI_1 [get_bd_intf_pins noc/HBM24_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_24] + connect_bd_intf_net -intf_net HBM25_AXI_1 [get_bd_intf_pins noc/HBM25_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_25] + connect_bd_intf_net -intf_net HBM26_AXI_1 [get_bd_intf_pins noc/HBM26_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_26] + connect_bd_intf_net -intf_net HBM27_AXI_1 [get_bd_intf_pins noc/HBM27_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_27] + connect_bd_intf_net -intf_net HBM28_AXI_1 [get_bd_intf_pins noc/HBM28_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_28] + connect_bd_intf_net -intf_net HBM29_AXI_1 [get_bd_intf_pins noc/HBM29_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_29] + connect_bd_intf_net -intf_net HBM30_AXI_1 [get_bd_intf_pins noc/HBM30_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_30] + connect_bd_intf_net -intf_net HBM31_AXI_1 [get_bd_intf_pins noc/HBM31_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_31] + connect_bd_intf_net -intf_net HBM32_AXI_1 [get_bd_intf_pins noc/HBM32_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_32] + connect_bd_intf_net -intf_net HBM33_AXI_1 [get_bd_intf_pins noc/HBM33_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_33] + connect_bd_intf_net -intf_net HBM34_AXI_1 [get_bd_intf_pins noc/HBM34_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_34] + connect_bd_intf_net -intf_net HBM35_AXI_1 [get_bd_intf_pins noc/HBM35_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_35] + connect_bd_intf_net -intf_net HBM36_AXI_1 [get_bd_intf_pins noc/HBM36_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_36] + connect_bd_intf_net -intf_net HBM37_AXI_1 [get_bd_intf_pins noc/HBM37_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_37] + connect_bd_intf_net -intf_net HBM38_AXI_1 [get_bd_intf_pins noc/HBM38_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_38] + connect_bd_intf_net -intf_net HBM39_AXI_1 [get_bd_intf_pins noc/HBM39_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_39] + connect_bd_intf_net -intf_net HBM40_AXI_1 [get_bd_intf_pins noc/HBM40_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_40] + connect_bd_intf_net -intf_net HBM41_AXI_1 [get_bd_intf_pins noc/HBM41_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_41] + connect_bd_intf_net -intf_net HBM42_AXI_1 [get_bd_intf_pins noc/HBM42_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_42] + connect_bd_intf_net -intf_net HBM43_AXI_1 [get_bd_intf_pins noc/HBM43_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_43] + connect_bd_intf_net -intf_net HBM44_AXI_1 [get_bd_intf_pins noc/HBM44_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_44] + connect_bd_intf_net -intf_net HBM45_AXI_1 [get_bd_intf_pins noc/HBM45_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_45] + connect_bd_intf_net -intf_net HBM46_AXI_1 [get_bd_intf_pins noc/HBM46_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_46] + connect_bd_intf_net -intf_net HBM47_AXI_1 [get_bd_intf_pins noc/HBM47_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_47] + connect_bd_intf_net -intf_net HBM48_AXI_1 [get_bd_intf_pins noc/HBM48_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_48] + connect_bd_intf_net -intf_net HBM49_AXI_1 [get_bd_intf_pins noc/HBM49_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_49] + connect_bd_intf_net -intf_net HBM50_AXI_1 [get_bd_intf_pins noc/HBM50_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_50] + connect_bd_intf_net -intf_net HBM51_AXI_1 [get_bd_intf_pins noc/HBM51_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_51] + connect_bd_intf_net -intf_net HBM52_AXI_1 [get_bd_intf_pins noc/HBM52_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_52] + connect_bd_intf_net -intf_net HBM53_AXI_1 [get_bd_intf_pins noc/HBM53_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_53] + connect_bd_intf_net -intf_net HBM54_AXI_1 [get_bd_intf_pins noc/HBM54_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_54] + connect_bd_intf_net -intf_net HBM55_AXI_1 [get_bd_intf_pins noc/HBM55_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_55] + connect_bd_intf_net -intf_net HBM56_AXI_1 [get_bd_intf_pins noc/HBM56_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_56] + connect_bd_intf_net -intf_net HBM57_AXI_1 [get_bd_intf_pins noc/HBM57_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_57] + connect_bd_intf_net -intf_net HBM58_AXI_1 [get_bd_intf_pins noc/HBM58_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_58] + connect_bd_intf_net -intf_net HBM59_AXI_1 [get_bd_intf_pins noc/HBM59_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_59] + connect_bd_intf_net -intf_net HBM60_AXI_1 [get_bd_intf_pins noc/HBM60_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_60] + connect_bd_intf_net -intf_net HBM61_AXI_1 [get_bd_intf_pins noc/HBM61_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_61] + connect_bd_intf_net -intf_net HBM62_AXI_1 [get_bd_intf_pins noc/HBM62_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_62] + connect_bd_intf_net -intf_net HBM63_AXI_1 [get_bd_intf_pins noc/HBM63_AXI] [get_bd_intf_pins dfx_decoupler_0/s_intf_63] + connect_bd_intf_net -intf_net NOC_CPM_PCIE_0_1 [get_bd_intf_pins NOC_CPM_PCIE_0] [get_bd_intf_pins axi_noc_0/S00_AXI] + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins noc/S00_AXI] [get_bd_intf_pins aved/CPM_PCIE_NOC_0] + connect_bd_intf_net -intf_net S01_AXI_1 [get_bd_intf_pins noc/S01_AXI] [get_bd_intf_pins aved/CPM_PCIE_NOC_1] + connect_bd_intf_net -intf_net S02_AXI_1 [get_bd_intf_pins noc/S02_AXI] [get_bd_intf_pins aved/PMC_NOC_AXI_0] + connect_bd_intf_net -intf_net S03_AXI_1 [get_bd_intf_pins noc/S03_AXI] [get_bd_intf_pins aved/LPD_AXI_NOC_0] + connect_bd_intf_net -intf_net S12_INI_1 [get_bd_intf_pins S12_INI] [get_bd_intf_pins noc/S12_INI] + connect_bd_intf_net -intf_net S13_INI_1 [get_bd_intf_pins S13_INI] [get_bd_intf_pins noc/S13_INI] + connect_bd_intf_net -intf_net S14_INI_1 [get_bd_intf_pins S14_INI] [get_bd_intf_pins noc/S14_INI] + connect_bd_intf_net -intf_net S15_INI_1 [get_bd_intf_pins S15_INI] [get_bd_intf_pins noc/S15_INI] + connect_bd_intf_net -intf_net S16_INI_1 [get_bd_intf_pins S16_INI] [get_bd_intf_pins noc/S16_INI] + connect_bd_intf_net -intf_net S17_INI_1 [get_bd_intf_pins S17_INI] [get_bd_intf_pins noc/S17_INI] + connect_bd_intf_net -intf_net S18_INI_1 [get_bd_intf_pins S18_INI] [get_bd_intf_pins noc/S18_INI] + connect_bd_intf_net -intf_net S19_INI_1 [get_bd_intf_pins S19_INI] [get_bd_intf_pins noc/S19_INI] + connect_bd_intf_net -intf_net S20_INI1_1 [get_bd_intf_pins S20_INI] [get_bd_intf_pins noc/S20_INI1] + connect_bd_intf_net -intf_net S21_INI1_1 [get_bd_intf_pins S21_INI] [get_bd_intf_pins noc/S21_INI1] + connect_bd_intf_net -intf_net S22_INI1_1 [get_bd_intf_pins S22_INI] [get_bd_intf_pins noc/S22_INI1] + connect_bd_intf_net -intf_net S23_INI1_1 [get_bd_intf_pins S23_INI] [get_bd_intf_pins noc/S23_INI1] + connect_bd_intf_net -intf_net axi_noc_0_M00_INI [get_bd_intf_pins axi_noc_0/M00_INI] [get_bd_intf_pins axi_noc_1/S00_INI] + connect_bd_intf_net -intf_net axi_noc_1_M00_AXI [get_bd_intf_pins axi_noc_1/M00_AXI] [get_bd_intf_pins aved/NOC_CPM_PCIE_0] + connect_bd_intf_net -intf_net noc_M00_AXI [get_bd_intf_pins noc/M00_AXI] [get_bd_intf_pins aved/s_axi_pcie_mgmt_slr0] + connect_bd_intf_net -intf_net noc_M02_AXI [get_bd_intf_pins noc/M02_AXI] [get_bd_intf_pins aved/NOC_PMC_AXI_0] + + # Create port connections + connect_bd_net -net aclk0_1 [get_bd_pins aved/pl0_ref_clk] \ + [get_bd_pins noc/aclk0] \ + [get_bd_pins pl0_ref_clk] + connect_bd_net -net aclk1_1 [get_bd_pins aved/cpm_pcie_noc_axi1_clk] \ + [get_bd_pins noc/aclk1] + connect_bd_net -net aclk2_1 [get_bd_pins aved/pmc_axi_noc_axi0_clk] \ + [get_bd_pins noc/aclk2] + connect_bd_net -net aclk3_1 [get_bd_pins aved/lpd_axi_noc_clk] \ + [get_bd_pins noc/aclk3] + connect_bd_net -net aclk4_1 [get_bd_pins aved/cpm_pcie_noc_axi0_clk] \ + [get_bd_pins noc/aclk4] \ + [get_bd_pins axi_noc_1/aclk0] + connect_bd_net -net aclk6_1 [get_bd_pins aved/noc_pmc_axi_axi0_clk] \ + [get_bd_pins noc/aclk6] + connect_bd_net -net aved_eos [get_bd_pins aved/eos] \ + [get_bd_pins util_vector_logic_0/Op1] + connect_bd_net -net aved_noc_cpm_pcie_axi0_clk [get_bd_pins aved/noc_cpm_pcie_axi0_clk] \ + [get_bd_pins axi_noc_1/aclk1] + connect_bd_net -net aved_pl3_ref_clk [get_bd_pins aved/pl3_ref_clk] \ + [get_bd_pins clk_wizard_0/clk_in1] + connect_bd_net -net aved_pl3_resetn -boundary_type upper [get_bd_pins aved/pl3_resetn] + connect_bd_net -net aved_resetn_pl_periph [get_bd_pins aved/resetn_pl_periph] \ + [get_bd_pins resetn_pl_periph] \ + [get_bd_pins proc_sys_reset_1/ext_reset_in] + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins clk_wizard_0/clk_out1] \ + [get_bd_pins clk_out1] \ + [get_bd_pins noc/aclk5] \ + [get_bd_pins proc_sys_reset_1/slowest_sync_clk] \ + [get_bd_pins dfx_decoupler_0/intf_1_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_2_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_3_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_4_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_5_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_6_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_7_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_8_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_9_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_10_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_11_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_12_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_13_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_14_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_15_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_16_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_17_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_18_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_19_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_20_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_21_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_22_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_23_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_24_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_25_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_26_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_27_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_28_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_29_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_30_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_31_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_32_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_33_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_34_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_35_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_36_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_37_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_38_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_39_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_40_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_41_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_42_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_43_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_44_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_45_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_46_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_47_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_48_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_49_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_50_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_51_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_52_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_53_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_54_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_55_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_56_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_57_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_58_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_59_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_60_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_61_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_62_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_63_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_0_aclk] \ + [get_bd_pins axi_noc_0/aclk0] \ + [get_bd_pins axi_register_slice_0/aclk] \ + [get_bd_pins axi_register_slice_1/aclk] \ + [get_bd_pins axi_register_slice_2/aclk] \ + [get_bd_pins axi_register_slice_3/aclk] \ + [get_bd_pins axi_register_slice_4/aclk] + connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins proc_sys_reset_1/peripheral_aresetn] \ + [get_bd_pins peripheral_aresetn] \ + [get_bd_pins dfx_decoupler_0/intf_1_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_2_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_3_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_4_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_5_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_6_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_7_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_8_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_9_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_10_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_11_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_12_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_13_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_14_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_15_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_16_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_17_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_18_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_19_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_20_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_21_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_22_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_23_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_24_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_25_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_26_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_27_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_28_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_29_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_30_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_31_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_32_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_33_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_34_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_35_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_36_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_37_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_38_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_39_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_40_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_41_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_42_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_43_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_44_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_45_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_46_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_47_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_48_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_49_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_50_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_51_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_52_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_53_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_54_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_55_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_56_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_57_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_58_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_59_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_60_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_61_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_62_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_63_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_0_arstn] \ + [get_bd_pins axi_register_slice_0/aresetn] \ + [get_bd_pins axi_register_slice_1/aresetn] \ + [get_bd_pins axi_register_slice_2/aresetn] \ + [get_bd_pins axi_register_slice_3/aresetn] \ + [get_bd_pins axi_register_slice_4/aresetn] + connect_bd_net -net util_vector_logic_0_Res [get_bd_pins util_vector_logic_0/Res] \ + [get_bd_pins dfx_decoupler_0/decouple] + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + +# set_property -dict [list \ +# SRC_RM_MAP./service_layer.service_layer {service_layer_inst_0} \ +# SRC_RM_MAP./service_layer.service_layer_user {service_layer_user_inst_0} \ +# SRC_RM_MAP./slash.slash_base {slash_base_inst_0} \ +# SRC_RM_MAP./slash.slash_user {slash_user_inst_0} \ +# ] [get_bd_designs $design_name] + + + # Create interface ports + set CH0_DDR4_0_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 CH0_DDR4_0_0 ] + + set sys_clk0_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk0_0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $sys_clk0_0 + + set CH0_DDR4_0_1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 CH0_DDR4_0_1 ] + + set sys_clk0_1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk0_1 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $sys_clk0_1 + + set hbm_ref_clk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 hbm_ref_clk_0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $hbm_ref_clk_0 + + set hbm_ref_clk_1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 hbm_ref_clk_1 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $hbm_ref_clk_1 + + set gt_pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 gt_pcie_refclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $gt_pcie_refclk + + set gt_pciea1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt_pciea1 ] + + set smbus_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 smbus_0 ] + + set qsfp0_322mhz [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp0_322mhz ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {322265625} \ + ] $qsfp0_322mhz + + set qsfp2_322mhz [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp2_322mhz ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {322265625} \ + ] $qsfp2_322mhz + + set qsfp0_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp0_4x ] + + set qsfp2_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp2_4x ] + + set qsfp1_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp1_4x ] + + set qsfp3_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp3_4x ] + + + # Create ports + + # Create instance: static_region + create_hier_cell_static_region [current_bd_instance .] static_region + + # Create instance: slash, and set properties + set slash [ create_bd_cell -type container -reference slash_base slash ] + # set_property -dict [list \ + # CONFIG.ACTIVE_SIM_BD {slash_base.bd} \ + # CONFIG.ACTIVE_SYNTH_BD {slash_base.bd} \ + # CONFIG.ENABLE_DFX {false} \ + # CONFIG.LIST_SIM_BD {slash_base.bd:slash_user.bd} \ + # CONFIG.LIST_SYNTH_BD {slash_base.bd:slash_user.bd} \ + # CONFIG.LOCK_PROPAGATE {false} \ + # ] $slash + + + set_property SELECTED_SIM_MODEL rtl $slash + set_property APERTURES {{0x40_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_00] + set_property APERTURES {{0x40_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_01] + set_property APERTURES {{0x40_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_02] + set_property APERTURES {{0x40_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_03] + set_property APERTURES {{0x40_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_04] + set_property APERTURES {{0x40_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_05] + set_property APERTURES {{0x40_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_06] + set_property APERTURES {{0x40_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_07] + set_property APERTURES {{0x41_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_08] + set_property APERTURES {{0x41_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_09] + set_property APERTURES {{0x41_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_10] + set_property APERTURES {{0x41_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_11] + set_property APERTURES {{0x41_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_12] + set_property APERTURES {{0x41_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_13] + set_property APERTURES {{0x41_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_14] + set_property APERTURES {{0x41_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_15] + set_property APERTURES {{0x42_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_16] + set_property APERTURES {{0x42_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_17] + set_property APERTURES {{0x42_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_18] + set_property APERTURES {{0x42_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_19] + set_property APERTURES {{0x42_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_20] + set_property APERTURES {{0x42_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_21] + set_property APERTURES {{0x42_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_22] + set_property APERTURES {{0x42_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_23] + set_property APERTURES {{0x43_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_24] + set_property APERTURES {{0x43_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_25] + set_property APERTURES {{0x43_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_26] + set_property APERTURES {{0x43_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_27] + set_property APERTURES {{0x43_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_28] + set_property APERTURES {{0x43_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_29] + set_property APERTURES {{0x43_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_30] + set_property APERTURES {{0x43_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_31] + set_property APERTURES {{0x44_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_32] + set_property APERTURES {{0x44_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_33] + set_property APERTURES {{0x44_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_34] + set_property APERTURES {{0x44_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_35] + set_property APERTURES {{0x44_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_36] + set_property APERTURES {{0x44_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_37] + set_property APERTURES {{0x44_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_38] + set_property APERTURES {{0x44_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_39] + set_property APERTURES {{0x45_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_40] + set_property APERTURES {{0x45_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_41] + set_property APERTURES {{0x45_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_42] + set_property APERTURES {{0x45_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_43] + set_property APERTURES {{0x45_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_44] + set_property APERTURES {{0x45_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_45] + set_property APERTURES {{0x45_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_46] + set_property APERTURES {{0x45_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_47] + set_property APERTURES {{0x46_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_48] + set_property APERTURES {{0x46_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_49] + set_property APERTURES {{0x46_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_50] + set_property APERTURES {{0x46_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_51] + set_property APERTURES {{0x46_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_52] + set_property APERTURES {{0x46_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_53] + set_property APERTURES {{0x46_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_54] + set_property APERTURES {{0x46_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_55] + set_property APERTURES {{0x47_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_56] + set_property APERTURES {{0x47_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_57] + set_property APERTURES {{0x47_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_58] + set_property APERTURES {{0x47_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_59] + set_property APERTURES {{0x47_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_60] + set_property APERTURES {{0x47_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_61] + set_property APERTURES {{0x47_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_62] + set_property APERTURES {{0x47_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_63] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_00] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_01] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_02] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_03] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_04] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_05] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_06] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_07] + set_property APERTURES {{0x0 2G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/M00_INI] + set_property APERTURES {{0x0 2G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/M01_INI] + set_property APERTURES {{0x0 2G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/M02_INI] + set_property APERTURES {{0x0 2G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/M03_INI] + set_property APERTURES {{0xE000_0000 256M}} [get_bd_intf_pins /slash/QDMA_SLAVE_BRIDGE] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 32G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/SL_VIRT_0] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 32G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/SL_VIRT_1] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 32G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/SL_VIRT_2] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 32G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/SL_VIRT_3] + set_property APERTURES {{0x202_0000_0000 128M}} [get_bd_intf_pins /slash/S_AXILITE_INI] + + # Create instance: service_layer, and set properties + set service_layer [ create_bd_cell -type container -reference service_layer service_layer ] + # set_property -dict [list \ + # CONFIG.ACTIVE_SIM_BD {service_layer.bd} \ + # CONFIG.ACTIVE_SYNTH_BD {service_layer.bd} \ + # CONFIG.ENABLE_DFX {false} \ + # CONFIG.LIST_SIM_BD {service_layer.bd:service_layer_user.bd} \ + # CONFIG.LIST_SYNTH_BD {service_layer.bd:service_layer_user.bd} \ + # CONFIG.LOCK_PROPAGATE {false} \ + # ] $service_layer + + + set_property SELECTED_SIM_MODEL rtl $service_layer + set_property APERTURES {{0xE000_0000 256M}} [get_bd_intf_pins /service_layer/M_QDMA_SLAVE_BRIDGE] + set_property APERTURES {{0x0 16E}} [get_bd_intf_pins /service_layer/M_VIRT_0] + set_property APERTURES {{0x0 16E}} [get_bd_intf_pins /service_layer/M_VIRT_1] + set_property APERTURES {{0x0 16E}} [get_bd_intf_pins /service_layer/M_VIRT_2] + set_property APERTURES {{0x0 16E}} [get_bd_intf_pins /service_layer/M_VIRT_3] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_0] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_1] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_2] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_3] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_4] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_5] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_6] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_7] + set_property APERTURES {{0x203_0000_0000 128M}} [get_bd_intf_pins /service_layer/S_AXILITE_INI] + set_property APERTURES {{0xE000_0000 256M}} [get_bd_intf_pins /service_layer/S_QDMA_SLAVE_BRIDGE] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 32G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/S_VIRT_0] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 32G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/S_VIRT_1] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 32G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/S_VIRT_2] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 32G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/S_VIRT_3] + + # Create interface connections + connect_bd_intf_net -intf_net S_AXILITE_INI_1 [get_bd_intf_pins service_layer/S_AXILITE_INI] [get_bd_intf_pins static_region/M05_INI] + connect_bd_intf_net -intf_net S_AXILITE_INI_2 [get_bd_intf_pins slash/S_AXILITE_INI] [get_bd_intf_pins static_region/M04_INI] + connect_bd_intf_net -intf_net S_DCMAC_INIS0_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS0] [get_bd_intf_pins static_region/M00_INIS] + connect_bd_intf_net -intf_net S_DCMAC_INIS0_2 [get_bd_intf_pins slash/S_DCMAC_INIS0] [get_bd_intf_pins static_region/M00_INIS8] + connect_bd_intf_net -intf_net S_DCMAC_INIS1_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS1] [get_bd_intf_pins static_region/M00_INIS1] + connect_bd_intf_net -intf_net S_DCMAC_INIS1_2 [get_bd_intf_pins slash/S_DCMAC_INIS1] [get_bd_intf_pins static_region/M00_INIS9] + connect_bd_intf_net -intf_net S_DCMAC_INIS2_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS2] [get_bd_intf_pins static_region/M00_INIS2] + connect_bd_intf_net -intf_net S_DCMAC_INIS2_2 [get_bd_intf_pins slash/S_DCMAC_INIS2] [get_bd_intf_pins static_region/M00_INIS10] + connect_bd_intf_net -intf_net S_DCMAC_INIS3_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS3] [get_bd_intf_pins static_region/M00_INIS3] + connect_bd_intf_net -intf_net S_DCMAC_INIS3_2 [get_bd_intf_pins slash/S_DCMAC_INIS3] [get_bd_intf_pins static_region/M00_INIS11] + connect_bd_intf_net -intf_net S_DCMAC_INIS4_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS4] [get_bd_intf_pins static_region/M00_INIS4] + connect_bd_intf_net -intf_net S_DCMAC_INIS4_2 [get_bd_intf_pins slash/S_DCMAC_INIS4] [get_bd_intf_pins static_region/M00_INIS12] + connect_bd_intf_net -intf_net S_DCMAC_INIS5_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS5] [get_bd_intf_pins static_region/M00_INIS5] + connect_bd_intf_net -intf_net S_DCMAC_INIS5_2 [get_bd_intf_pins slash/S_DCMAC_INIS5] [get_bd_intf_pins static_region/M00_INIS13] + connect_bd_intf_net -intf_net S_DCMAC_INIS6_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS6] [get_bd_intf_pins static_region/M00_INIS6] + connect_bd_intf_net -intf_net S_DCMAC_INIS6_2 [get_bd_intf_pins slash/S_DCMAC_INIS6] [get_bd_intf_pins static_region/M00_INIS14] + connect_bd_intf_net -intf_net S_DCMAC_INIS7_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS7] [get_bd_intf_pins static_region/M00_INIS7] + connect_bd_intf_net -intf_net S_DCMAC_INIS7_2 [get_bd_intf_pins slash/S_DCMAC_INIS7] [get_bd_intf_pins static_region/M00_INIS15] + connect_bd_intf_net -intf_net S_QDMA_SLAVE_BRIDGE_1 [get_bd_intf_pins service_layer/S_QDMA_SLAVE_BRIDGE] [get_bd_intf_pins static_region/M_AXI] + connect_bd_intf_net -intf_net S_VIRT_0_1 [get_bd_intf_pins service_layer/S_VIRT_0] [get_bd_intf_pins static_region/M_AXI1] + connect_bd_intf_net -intf_net S_VIRT_1_1 [get_bd_intf_pins service_layer/S_VIRT_1] [get_bd_intf_pins static_region/M_AXI2] + connect_bd_intf_net -intf_net S_VIRT_2_1 [get_bd_intf_pins service_layer/S_VIRT_2] [get_bd_intf_pins static_region/M_AXI3] + connect_bd_intf_net -intf_net S_VIRT_3_1 [get_bd_intf_pins service_layer/S_VIRT_3] [get_bd_intf_pins static_region/M_AXI4] + connect_bd_intf_net -intf_net gt_pcie_refclk_1 [get_bd_intf_ports gt_pcie_refclk] [get_bd_intf_pins static_region/gt_pcie_refclk] + connect_bd_intf_net -intf_net hbm_ref_clk_0_1 [get_bd_intf_ports hbm_ref_clk_0] [get_bd_intf_pins static_region/hbm_ref_clk_0] + connect_bd_intf_net -intf_net hbm_ref_clk_1_1 [get_bd_intf_ports hbm_ref_clk_1] [get_bd_intf_pins static_region/hbm_ref_clk_1] + connect_bd_intf_net -intf_net qsfp0_322mhz_0_1 [get_bd_intf_ports qsfp0_322mhz] [get_bd_intf_pins service_layer/qsfp0_322mhz] + connect_bd_intf_net -intf_net qsfp2_322mhz_0_1 [get_bd_intf_ports qsfp2_322mhz] [get_bd_intf_pins service_layer/qsfp2_322mhz] + connect_bd_intf_net -intf_net service_layer_M00_INI [get_bd_intf_pins service_layer/SL2NOC_0] [get_bd_intf_pins static_region/S12_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI1 [get_bd_intf_pins service_layer/SL2NOC_1] [get_bd_intf_pins static_region/S13_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI2 [get_bd_intf_pins service_layer/SL2NOC_2] [get_bd_intf_pins static_region/S14_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI3 [get_bd_intf_pins service_layer/SL2NOC_3] [get_bd_intf_pins static_region/S15_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI4 [get_bd_intf_pins service_layer/SL2NOC_4] [get_bd_intf_pins static_region/S16_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI5 [get_bd_intf_pins service_layer/SL2NOC_5] [get_bd_intf_pins static_region/S17_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI6 [get_bd_intf_pins service_layer/SL2NOC_6] [get_bd_intf_pins static_region/S18_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI7 [get_bd_intf_pins service_layer/SL2NOC_7] [get_bd_intf_pins static_region/S19_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI12 [get_bd_intf_pins service_layer/M_VIRT_0] [get_bd_intf_pins static_region/S20_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI13 [get_bd_intf_pins service_layer/M_VIRT_1] [get_bd_intf_pins static_region/S21_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI14 [get_bd_intf_pins service_layer/M_VIRT_2] [get_bd_intf_pins static_region/S22_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI15 [get_bd_intf_pins service_layer/M_VIRT_3] [get_bd_intf_pins static_region/S23_INI] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS0 [get_bd_intf_pins service_layer/M_DCMAC_INIS0] [get_bd_intf_pins static_region/S00_INIS8] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS1 [get_bd_intf_pins service_layer/M_DCMAC_INIS1] [get_bd_intf_pins static_region/S00_INIS9] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS2 [get_bd_intf_pins service_layer/M_DCMAC_INIS2] [get_bd_intf_pins static_region/S00_INIS10] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS3 [get_bd_intf_pins service_layer/M_DCMAC_INIS3] [get_bd_intf_pins static_region/S00_INIS11] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS4 [get_bd_intf_pins service_layer/M_DCMAC_INIS4] [get_bd_intf_pins static_region/S00_INIS12] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS5 [get_bd_intf_pins service_layer/M_DCMAC_INIS5] [get_bd_intf_pins static_region/S00_INIS13] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS6 [get_bd_intf_pins service_layer/M_DCMAC_INIS6] [get_bd_intf_pins static_region/S00_INIS14] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS7 [get_bd_intf_pins service_layer/M_DCMAC_INIS7] [get_bd_intf_pins static_region/S00_INIS15] + connect_bd_intf_net -intf_net service_layer_M_QDMA_SLAVE_BRIDGE [get_bd_intf_pins service_layer/M_QDMA_SLAVE_BRIDGE] [get_bd_intf_pins static_region/NOC_CPM_PCIE_0] + connect_bd_intf_net -intf_net service_layer_qsfp0_4x [get_bd_intf_ports qsfp0_4x] [get_bd_intf_pins service_layer/qsfp0_4x] + connect_bd_intf_net -intf_net service_layer_qsfp1_4x [get_bd_intf_ports qsfp1_4x] [get_bd_intf_pins service_layer/qsfp1_4x] + connect_bd_intf_net -intf_net service_layer_qsfp2_4x [get_bd_intf_ports qsfp2_4x] [get_bd_intf_pins service_layer/qsfp2_4x] + connect_bd_intf_net -intf_net service_layer_qsfp3_4x [get_bd_intf_ports qsfp3_4x] [get_bd_intf_pins service_layer/qsfp3_4x] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_00 [get_bd_intf_pins slash/HBM_VNOC_INI_00] [get_bd_intf_pins static_region/S04_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_01 [get_bd_intf_pins slash/HBM_VNOC_INI_01] [get_bd_intf_pins static_region/S05_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_02 [get_bd_intf_pins slash/HBM_VNOC_INI_02] [get_bd_intf_pins static_region/S06_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_03 [get_bd_intf_pins slash/HBM_VNOC_INI_03] [get_bd_intf_pins static_region/S07_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_04 [get_bd_intf_pins slash/HBM_VNOC_INI_04] [get_bd_intf_pins static_region/S08_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_05 [get_bd_intf_pins slash/HBM_VNOC_INI_05] [get_bd_intf_pins static_region/S09_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_06 [get_bd_intf_pins slash/HBM_VNOC_INI_06] [get_bd_intf_pins static_region/S10_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_07 [get_bd_intf_pins slash/HBM_VNOC_INI_07] [get_bd_intf_pins static_region/S11_INI] + connect_bd_intf_net -intf_net slash_M00_INI [get_bd_intf_pins slash/M00_INI] [get_bd_intf_pins static_region/S00_INI] + connect_bd_intf_net -intf_net slash_M01_INI [get_bd_intf_pins slash/M01_INI] [get_bd_intf_pins static_region/S01_INI] + connect_bd_intf_net -intf_net slash_M02_INI [get_bd_intf_pins slash/M02_INI] [get_bd_intf_pins static_region/S02_INI] + connect_bd_intf_net -intf_net slash_M03_INI [get_bd_intf_pins slash/M03_INI] [get_bd_intf_pins static_region/S03_INI] + connect_bd_intf_net -intf_net slash_M_AXI0 [get_bd_intf_pins slash/HBM_AXI_00] [get_bd_intf_pins static_region/rp_intf_0] + connect_bd_intf_net -intf_net slash_M_AXI1 [get_bd_intf_pins slash/HBM_AXI_01] [get_bd_intf_pins static_region/rp_intf_1] + connect_bd_intf_net -intf_net slash_M_AXI2 [get_bd_intf_pins slash/HBM_AXI_02] [get_bd_intf_pins static_region/rp_intf_2] + connect_bd_intf_net -intf_net slash_M_AXI3 [get_bd_intf_pins slash/HBM_AXI_03] [get_bd_intf_pins static_region/rp_intf_3] + connect_bd_intf_net -intf_net slash_M_AXI4 [get_bd_intf_pins slash/HBM_AXI_04] [get_bd_intf_pins static_region/rp_intf_4] + connect_bd_intf_net -intf_net slash_M_AXI5 [get_bd_intf_pins slash/HBM_AXI_05] [get_bd_intf_pins static_region/rp_intf_5] + connect_bd_intf_net -intf_net slash_M_AXI6 [get_bd_intf_pins slash/HBM_AXI_06] [get_bd_intf_pins static_region/rp_intf_6] + connect_bd_intf_net -intf_net slash_M_AXI7 [get_bd_intf_pins slash/HBM_AXI_07] [get_bd_intf_pins static_region/rp_intf_7] + connect_bd_intf_net -intf_net slash_M_AXI8 [get_bd_intf_pins slash/HBM_AXI_08] [get_bd_intf_pins static_region/rp_intf_8] + connect_bd_intf_net -intf_net slash_M_AXI9 [get_bd_intf_pins slash/HBM_AXI_09] [get_bd_intf_pins static_region/rp_intf_9] + connect_bd_intf_net -intf_net slash_M_AXI10 [get_bd_intf_pins slash/HBM_AXI_10] [get_bd_intf_pins static_region/rp_intf_10] + connect_bd_intf_net -intf_net slash_M_AXI11 [get_bd_intf_pins slash/HBM_AXI_11] [get_bd_intf_pins static_region/rp_intf_11] + connect_bd_intf_net -intf_net slash_M_AXI12 [get_bd_intf_pins slash/HBM_AXI_12] [get_bd_intf_pins static_region/rp_intf_12] + connect_bd_intf_net -intf_net slash_M_AXI13 [get_bd_intf_pins slash/HBM_AXI_13] [get_bd_intf_pins static_region/rp_intf_13] + connect_bd_intf_net -intf_net slash_M_AXI14 [get_bd_intf_pins slash/HBM_AXI_14] [get_bd_intf_pins static_region/rp_intf_14] + connect_bd_intf_net -intf_net slash_M_AXI15 [get_bd_intf_pins slash/HBM_AXI_15] [get_bd_intf_pins static_region/rp_intf_15] + connect_bd_intf_net -intf_net slash_M_AXI16 [get_bd_intf_pins slash/HBM_AXI_16] [get_bd_intf_pins static_region/rp_intf_16] + connect_bd_intf_net -intf_net slash_M_AXI17 [get_bd_intf_pins slash/HBM_AXI_17] [get_bd_intf_pins static_region/rp_intf_17] + connect_bd_intf_net -intf_net slash_M_AXI18 [get_bd_intf_pins slash/HBM_AXI_18] [get_bd_intf_pins static_region/rp_intf_18] + connect_bd_intf_net -intf_net slash_M_AXI19 [get_bd_intf_pins slash/HBM_AXI_19] [get_bd_intf_pins static_region/rp_intf_19] + connect_bd_intf_net -intf_net slash_M_AXI20 [get_bd_intf_pins slash/HBM_AXI_20] [get_bd_intf_pins static_region/rp_intf_20] + connect_bd_intf_net -intf_net slash_M_AXI21 [get_bd_intf_pins slash/HBM_AXI_21] [get_bd_intf_pins static_region/rp_intf_21] + connect_bd_intf_net -intf_net slash_M_AXI22 [get_bd_intf_pins slash/HBM_AXI_22] [get_bd_intf_pins static_region/rp_intf_22] + connect_bd_intf_net -intf_net slash_M_AXI23 [get_bd_intf_pins slash/HBM_AXI_23] [get_bd_intf_pins static_region/rp_intf_23] + connect_bd_intf_net -intf_net slash_M_AXI24 [get_bd_intf_pins slash/HBM_AXI_24] [get_bd_intf_pins static_region/rp_intf_24] + connect_bd_intf_net -intf_net slash_M_AXI25 [get_bd_intf_pins slash/HBM_AXI_25] [get_bd_intf_pins static_region/rp_intf_25] + connect_bd_intf_net -intf_net slash_M_AXI26 [get_bd_intf_pins slash/HBM_AXI_26] [get_bd_intf_pins static_region/rp_intf_26] + connect_bd_intf_net -intf_net slash_M_AXI27 [get_bd_intf_pins slash/HBM_AXI_27] [get_bd_intf_pins static_region/rp_intf_27] + connect_bd_intf_net -intf_net slash_M_AXI28 [get_bd_intf_pins slash/HBM_AXI_28] [get_bd_intf_pins static_region/rp_intf_28] + connect_bd_intf_net -intf_net slash_M_AXI29 [get_bd_intf_pins slash/HBM_AXI_29] [get_bd_intf_pins static_region/rp_intf_29] + connect_bd_intf_net -intf_net slash_M_AXI30 [get_bd_intf_pins slash/HBM_AXI_30] [get_bd_intf_pins static_region/rp_intf_30] + connect_bd_intf_net -intf_net slash_M_AXI31 [get_bd_intf_pins slash/HBM_AXI_31] [get_bd_intf_pins static_region/rp_intf_31] + connect_bd_intf_net -intf_net slash_M_AXI32 [get_bd_intf_pins slash/HBM_AXI_32] [get_bd_intf_pins static_region/rp_intf_32] + connect_bd_intf_net -intf_net slash_M_AXI33 [get_bd_intf_pins slash/HBM_AXI_33] [get_bd_intf_pins static_region/rp_intf_33] + connect_bd_intf_net -intf_net slash_M_AXI34 [get_bd_intf_pins slash/HBM_AXI_34] [get_bd_intf_pins static_region/rp_intf_34] + connect_bd_intf_net -intf_net slash_M_AXI35 [get_bd_intf_pins slash/HBM_AXI_35] [get_bd_intf_pins static_region/rp_intf_35] + connect_bd_intf_net -intf_net slash_M_AXI36 [get_bd_intf_pins slash/HBM_AXI_36] [get_bd_intf_pins static_region/rp_intf_36] + connect_bd_intf_net -intf_net slash_M_AXI37 [get_bd_intf_pins slash/HBM_AXI_37] [get_bd_intf_pins static_region/rp_intf_37] + connect_bd_intf_net -intf_net slash_M_AXI38 [get_bd_intf_pins slash/HBM_AXI_38] [get_bd_intf_pins static_region/rp_intf_38] + connect_bd_intf_net -intf_net slash_M_AXI39 [get_bd_intf_pins slash/HBM_AXI_39] [get_bd_intf_pins static_region/rp_intf_39] + connect_bd_intf_net -intf_net slash_M_AXI40 [get_bd_intf_pins slash/HBM_AXI_40] [get_bd_intf_pins static_region/rp_intf_40] + connect_bd_intf_net -intf_net slash_M_AXI41 [get_bd_intf_pins slash/HBM_AXI_41] [get_bd_intf_pins static_region/rp_intf_41] + connect_bd_intf_net -intf_net slash_M_AXI42 [get_bd_intf_pins slash/HBM_AXI_42] [get_bd_intf_pins static_region/rp_intf_42] + connect_bd_intf_net -intf_net slash_M_AXI43 [get_bd_intf_pins slash/HBM_AXI_43] [get_bd_intf_pins static_region/rp_intf_43] + connect_bd_intf_net -intf_net slash_M_AXI44 [get_bd_intf_pins slash/HBM_AXI_44] [get_bd_intf_pins static_region/rp_intf_44] + connect_bd_intf_net -intf_net slash_M_AXI45 [get_bd_intf_pins slash/HBM_AXI_45] [get_bd_intf_pins static_region/rp_intf_45] + connect_bd_intf_net -intf_net slash_M_AXI46 [get_bd_intf_pins slash/HBM_AXI_46] [get_bd_intf_pins static_region/rp_intf_46] + connect_bd_intf_net -intf_net slash_M_AXI47 [get_bd_intf_pins slash/HBM_AXI_47] [get_bd_intf_pins static_region/rp_intf_47] + connect_bd_intf_net -intf_net slash_M_AXI48 [get_bd_intf_pins slash/HBM_AXI_48] [get_bd_intf_pins static_region/rp_intf_48] + connect_bd_intf_net -intf_net slash_M_AXI49 [get_bd_intf_pins slash/HBM_AXI_49] [get_bd_intf_pins static_region/rp_intf_49] + connect_bd_intf_net -intf_net slash_M_AXI50 [get_bd_intf_pins slash/HBM_AXI_50] [get_bd_intf_pins static_region/rp_intf_50] + connect_bd_intf_net -intf_net slash_M_AXI51 [get_bd_intf_pins slash/HBM_AXI_51] [get_bd_intf_pins static_region/rp_intf_51] + connect_bd_intf_net -intf_net slash_M_AXI52 [get_bd_intf_pins slash/HBM_AXI_52] [get_bd_intf_pins static_region/rp_intf_52] + connect_bd_intf_net -intf_net slash_M_AXI53 [get_bd_intf_pins slash/HBM_AXI_53] [get_bd_intf_pins static_region/rp_intf_53] + connect_bd_intf_net -intf_net slash_M_AXI54 [get_bd_intf_pins slash/HBM_AXI_54] [get_bd_intf_pins static_region/rp_intf_54] + connect_bd_intf_net -intf_net slash_M_AXI55 [get_bd_intf_pins slash/HBM_AXI_55] [get_bd_intf_pins static_region/rp_intf_55] + connect_bd_intf_net -intf_net slash_M_AXI56 [get_bd_intf_pins slash/HBM_AXI_56] [get_bd_intf_pins static_region/rp_intf_56] + connect_bd_intf_net -intf_net slash_M_AXI57 [get_bd_intf_pins slash/HBM_AXI_57] [get_bd_intf_pins static_region/rp_intf_57] + connect_bd_intf_net -intf_net slash_M_AXI58 [get_bd_intf_pins slash/HBM_AXI_58] [get_bd_intf_pins static_region/rp_intf_58] + connect_bd_intf_net -intf_net slash_M_AXI59 [get_bd_intf_pins slash/HBM_AXI_59] [get_bd_intf_pins static_region/rp_intf_59] + connect_bd_intf_net -intf_net slash_M_AXI60 [get_bd_intf_pins slash/HBM_AXI_60] [get_bd_intf_pins static_region/rp_intf_60] + connect_bd_intf_net -intf_net slash_M_AXI61 [get_bd_intf_pins slash/HBM_AXI_61] [get_bd_intf_pins static_region/rp_intf_61] + connect_bd_intf_net -intf_net slash_M_AXI62 [get_bd_intf_pins slash/HBM_AXI_62] [get_bd_intf_pins static_region/rp_intf_62] + connect_bd_intf_net -intf_net slash_M_AXI63 [get_bd_intf_pins slash/HBM_AXI_63] [get_bd_intf_pins static_region/rp_intf_63] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS0 [get_bd_intf_pins slash/M_DCMAC_INIS0] [get_bd_intf_pins static_region/S00_INIS] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS1 [get_bd_intf_pins slash/M_DCMAC_INIS1] [get_bd_intf_pins static_region/S00_INIS1] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS2 [get_bd_intf_pins slash/M_DCMAC_INIS2] [get_bd_intf_pins static_region/S00_INIS2] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS3 [get_bd_intf_pins slash/M_DCMAC_INIS3] [get_bd_intf_pins static_region/S00_INIS3] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS4 [get_bd_intf_pins slash/M_DCMAC_INIS4] [get_bd_intf_pins static_region/S00_INIS4] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS5 [get_bd_intf_pins slash/M_DCMAC_INIS5] [get_bd_intf_pins static_region/S00_INIS5] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS6 [get_bd_intf_pins slash/M_DCMAC_INIS6] [get_bd_intf_pins static_region/S00_INIS6] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS7 [get_bd_intf_pins slash/M_DCMAC_INIS7] [get_bd_intf_pins static_region/S00_INIS7] + connect_bd_intf_net -intf_net slash_QDMA_SLAVE_BRIDGE [get_bd_intf_pins slash/QDMA_SLAVE_BRIDGE] [get_bd_intf_pins static_region/S_AXI] + connect_bd_intf_net -intf_net slash_SL_VIRT_0 [get_bd_intf_pins slash/SL_VIRT_0] [get_bd_intf_pins static_region/S_AXI1] + connect_bd_intf_net -intf_net slash_SL_VIRT_1 [get_bd_intf_pins slash/SL_VIRT_1] [get_bd_intf_pins static_region/S_AXI2] + connect_bd_intf_net -intf_net slash_SL_VIRT_2 [get_bd_intf_pins slash/SL_VIRT_2] [get_bd_intf_pins static_region/S_AXI3] + connect_bd_intf_net -intf_net slash_SL_VIRT_3 [get_bd_intf_pins slash/SL_VIRT_3] [get_bd_intf_pins static_region/S_AXI4] + connect_bd_intf_net -intf_net static_region_CH0_DDR4_0_0 [get_bd_intf_ports CH0_DDR4_0_0] [get_bd_intf_pins static_region/CH0_DDR4_0_0] + connect_bd_intf_net -intf_net static_region_CH0_DDR4_0_1 [get_bd_intf_ports CH0_DDR4_0_1] [get_bd_intf_pins static_region/CH0_DDR4_0_1] + connect_bd_intf_net -intf_net static_region_gt_pciea1 [get_bd_intf_ports gt_pciea1] [get_bd_intf_pins static_region/gt_pciea1] + connect_bd_intf_net -intf_net static_region_smbus_0 [get_bd_intf_ports smbus_0] [get_bd_intf_pins static_region/smbus_0] + connect_bd_intf_net -intf_net sys_clk0_0_1 [get_bd_intf_ports sys_clk0_0] [get_bd_intf_pins static_region/sys_clk0_0] + connect_bd_intf_net -intf_net sys_clk0_1_1 [get_bd_intf_ports sys_clk0_1] [get_bd_intf_pins static_region/sys_clk0_1] + + # Create port connections + connect_bd_net -net ap_rst_n_1 [get_bd_pins static_region/peripheral_aresetn] \ + [get_bd_pins slash/ap_rst_n] \ + [get_bd_pins slash/arstn] \ + [get_bd_pins service_layer/ap_rst_n] + connect_bd_net -net aved_pl0_ref_clk [get_bd_pins static_region/pl0_ref_clk] \ + [get_bd_pins service_layer/aclk1] + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins static_region/clk_out1] \ + [get_bd_pins slash/s_axi_aclk] \ + [get_bd_pins slash/aclk1] \ + [get_bd_pins service_layer/aclk0] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM00_AXI/HBM0_PC0] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM01_AXI/HBM0_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_10/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM10_AXI/HBM2_PC1] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_11/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM11_AXI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_12/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM12_AXI/HBM3_PC0] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_13/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM13_AXI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_14/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM14_AXI/HBM3_PC1] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_15/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM15_AXI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_16/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM16_AXI/HBM4_PC0] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_17/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM17_AXI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_18/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM18_AXI/HBM4_PC1] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_19/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM19_AXI/HBM4_PC1] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM02_AXI/HBM0_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_20/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM20_AXI/HBM5_PC0] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_21/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM21_AXI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_22/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM22_AXI/HBM5_PC1] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_23/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM23_AXI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_24/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM24_AXI/HBM6_PC0] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_25/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM25_AXI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_26/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM26_AXI/HBM6_PC1] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_27/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM27_AXI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_28/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM28_AXI/HBM7_PC0] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_29/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM29_AXI/HBM7_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM03_AXI/HBM0_PC1] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_30/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM30_AXI/HBM7_PC1] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_31/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM31_AXI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_32/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM32_AXI/HBM8_PC0] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_33/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM33_AXI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_34/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM34_AXI/HBM8_PC1] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_35/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM35_AXI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_36/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM36_AXI/HBM9_PC0] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_37/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM37_AXI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_38/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM38_AXI/HBM9_PC1] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_39/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM39_AXI/HBM9_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_4/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM04_AXI/HBM1_PC0] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_40/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM40_AXI/HBM10_PC0] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_41/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM41_AXI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_42/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM42_AXI/HBM10_PC1] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_43/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM43_AXI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_44/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM44_AXI/HBM11_PC0] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_45/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM45_AXI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_46/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM46_AXI/HBM11_PC1] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_47/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM47_AXI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_48/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM48_AXI/HBM12_PC0] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_49/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM49_AXI/HBM12_PC0] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_5/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM05_AXI/HBM1_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_50/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM50_AXI/HBM12_PC1] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_51/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM51_AXI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_52/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM52_AXI/HBM13_PC0] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_53/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM53_AXI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_54/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM54_AXI/HBM13_PC1] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_55/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM55_AXI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_56/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM56_AXI/HBM14_PC0] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_57/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM57_AXI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_58/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM58_AXI/HBM14_PC1] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_59/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM59_AXI/HBM14_PC1] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_6/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM06_AXI/HBM1_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_60/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM60_AXI/HBM15_PC0] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_61/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM61_AXI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_62/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM62_AXI/HBM15_PC1] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_63/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM63_AXI/HBM15_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM9_PC1] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_7/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM07_AXI/HBM1_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_8/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM08_AXI/HBM2_PC0] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_9/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM09_AXI/HBM2_PC0] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S20_INI/HBM9_PC1] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S21_INI/HBM9_PC1] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S22_INI/HBM9_PC1] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S23_INI/HBM9_PC1] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0xE0000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_4/Data_m_axi_gmem0] [get_bd_addr_segs static_region/aved/cips/NOC_CPM_PCIE_0/pspmc_0_psv_noc_pcie_0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_4/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_5/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_6/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_7/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x020300110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset 0x020300150000 -range 0x00010000 -with_name SEG_axi_gpio_datapath_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset 0x020300100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset 0x020300160000 -range 0x00010000 -with_name SEG_axi_gpio_gt_control_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset 0x020300120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset 0x020300170000 -range 0x00010000 -with_name SEG_axi_gpio_monitor_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset 0x020300130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + assign_bd_address -offset 0x020300180000 -range 0x00010000 -with_name SEG_axi_gpio_reset_txrx_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM9_PC1] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0xFFA80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_0] -force + assign_bd_address -offset 0xFFA90000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_1] -force + assign_bd_address -offset 0xFFAA0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_2] -force + assign_bd_address -offset 0xFFAB0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_3] -force + assign_bd_address -offset 0xFFAC0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_4] -force + assign_bd_address -offset 0xFFAD0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_5] -force + assign_bd_address -offset 0xFFAE0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_6] -force + assign_bd_address -offset 0xFFAF0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_7] -force + assign_bd_address -offset 0x000100800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_0] -force + assign_bd_address -offset 0x000100D10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_cti] -force + assign_bd_address -offset 0x000100D00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_dbg] -force + assign_bd_address -offset 0x000100D30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_etm] -force + assign_bd_address -offset 0x000100D20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_pmu] -force + assign_bd_address -offset 0x000100D50000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_cti] -force + assign_bd_address -offset 0x000100D40000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_dbg] -force + assign_bd_address -offset 0x000100D70000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_etm] -force + assign_bd_address -offset 0x000100D60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_pmu] -force + assign_bd_address -offset 0x000100CA0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_cti] -force + assign_bd_address -offset 0x000100C60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_ela] -force + assign_bd_address -offset 0x000100C30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_etf] -force + assign_bd_address -offset 0x000100C20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_fun] -force + assign_bd_address -offset 0x000100F80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_atm] -force + assign_bd_address -offset 0x000100FA0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_cti2a] -force + assign_bd_address -offset 0x000100FD0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_cti2d] -force + assign_bd_address -offset 0x000100F40000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2a] -force + assign_bd_address -offset 0x000100F50000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2b] -force + assign_bd_address -offset 0x000100F60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2c] -force + assign_bd_address -offset 0x000100F70000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2d] -force + assign_bd_address -offset 0x000100F20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_fun] -force + assign_bd_address -offset 0x000100F00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_rom] -force + assign_bd_address -offset 0x000100B80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_fpd_atm] -force + assign_bd_address -offset 0x000100B70000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_fpd_stm] -force + assign_bd_address -offset 0x000100980000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_lpd_atm] -force + assign_bd_address -offset 0xFC000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_cpm] -force + assign_bd_address -offset 0xFF5E0000 -range 0x00300000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_crl_0] -force + assign_bd_address -offset 0x000101260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_crp_0] -force + assign_bd_address -offset 0xFF0B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_gpio_2] -force + assign_bd_address -offset 0xFF020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_i2c_0] -force + assign_bd_address -offset 0xFF030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_i2c_1] -force + assign_bd_address -offset 0xFF360000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_3] -force + assign_bd_address -offset 0xFF370000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_4] -force + assign_bd_address -offset 0xFF380000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_5] -force + assign_bd_address -offset 0xFF3A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_6] -force + assign_bd_address -offset 0xFF320000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_pmc] -force + assign_bd_address -offset 0xFF390000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_pmc_nobuf] -force + assign_bd_address -offset 0xFF310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_psm] -force + assign_bd_address -offset 0xFF9B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_afi_0] -force + assign_bd_address -offset 0xFF0A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_iou_secure_slcr_0] -force + assign_bd_address -offset 0xFF080000 -range 0x00020000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_iou_slcr_0] -force + assign_bd_address -offset 0xFF410000 -range 0x00100000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_slcr_0] -force + assign_bd_address -offset 0xFF510000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_slcr_secure_0] -force + assign_bd_address -offset 0xFF990000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_xppu_0] -force + assign_bd_address -offset 0xFF960000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ocm_ctrl] -force + assign_bd_address -offset 0xFFFC0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ocm_ram_0] -force + assign_bd_address -offset 0xFF980000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ocm_xmpu_0] -force + assign_bd_address -offset 0x0001011E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_aes] -force + assign_bd_address -offset 0x0001011F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_bbram_ctrl] -force + assign_bd_address -offset 0x0001012D0000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_cfi_cframe_0] -force + assign_bd_address -offset 0x0001012B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_cfu_apb_0] -force + assign_bd_address -offset 0x0001011C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_dma_0] -force + assign_bd_address -offset 0x0001011D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_dma_1] -force + assign_bd_address -offset 0x000101250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_efuse_cache] -force + assign_bd_address -offset 0x000101240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_efuse_ctrl] -force + assign_bd_address -offset 0x000101110000 -range 0x00050000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_global_0] -force + assign_bd_address -offset 0x000101020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_gpio_0] -force + assign_bd_address -offset 0x000100280000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_iomodule_0] -force + assign_bd_address -offset 0x000101010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ospi_0] -force + assign_bd_address -offset 0x000100310000 -range 0x00008000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ppu1_mdm_0] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_qspi_ospi_flash_0] -force + assign_bd_address -offset 0x000102000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram] -force + assign_bd_address -offset 0x000100240000 -range 0x00020000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram_data_cntlr] -force + assign_bd_address -offset 0x000100200000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram_instr_cntlr] -force + assign_bd_address -offset 0x000106000000 -range 0x02000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram_npi] -force + assign_bd_address -offset 0x000101200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_rsa] -force + assign_bd_address -offset 0x0001012A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_rtc_0] -force + assign_bd_address -offset 0x000101040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_sd_0] -force + assign_bd_address -offset 0x000101210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_sha] -force + assign_bd_address -offset 0x000101220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_slave_boot] -force + assign_bd_address -offset 0x000102100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_slave_boot_stream] -force + assign_bd_address -offset 0x000101270000 -range 0x00030000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_sysmon_0] -force + assign_bd_address -offset 0x000100083000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_tmr_inject_0] -force + assign_bd_address -offset 0x000100283000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_tmr_manager_0] -force + assign_bd_address -offset 0x000101230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_trng] -force + assign_bd_address -offset 0x0001012F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_xmpu_0] -force + assign_bd_address -offset 0x000101310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_xppu_0] -force + assign_bd_address -offset 0x000101300000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_xppu_npi_0] -force + assign_bd_address -offset 0xFFC90000 -range 0x0000F000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_psm_global_reg] -force + assign_bd_address -offset 0xFFE90000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_r5_1_atcm_global] -force + assign_bd_address -offset 0xFFEB0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_r5_1_btcm_global] -force + assign_bd_address -offset 0xFFE00000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_r5_tcm_ram_global] -force + assign_bd_address -offset 0xFF9A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_rpu_0] -force + assign_bd_address -offset 0xFF000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_sbsauart_0] -force + assign_bd_address -offset 0xFF010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_sbsauart_1] -force + assign_bd_address -offset 0xFF130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_scntr_0] -force + assign_bd_address -offset 0xFF140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_scntrs_0] -force + assign_bd_address -offset 0xFF040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_spi_0] -force + assign_bd_address -offset 0xFF0E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_0] -force + assign_bd_address -offset 0xFF0F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_1] -force + assign_bd_address -offset 0xFF100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_2] -force + assign_bd_address -offset 0xFF110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_3] -force + assign_bd_address -offset 0x020300140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_0_n_1/DCMAC_subsys/dcmac_0_core/s_axi/Reg] -force + assign_bd_address -offset 0x020300190000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_2_n_3/DCMAC_subsys/dcmac_1_core/s_axi/Reg] -force + assign_bd_address -offset 0x020200000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/ddr_bandwidth_64/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/ddr_bandwidth_65/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/ddr_bandwidth_66/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/ddr_bandwidth_67/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020101010000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/base_logic/gcq_m2r/S00_AXI/S00_AXI_Reg] -force + assign_bd_address -offset 0x020200040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_10/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_11/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_12/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_13/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_14/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_15/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_16/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_17/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_18/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_19/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_20/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_21/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_22/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_23/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200150000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_24/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200160000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_25/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200170000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_26/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200180000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_27/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200190000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_28/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_29/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_30/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_31/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_32/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_33/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_34/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_35/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_36/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_37/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_38/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_39/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200270000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_40/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200280000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_41/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200290000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_42/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_43/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_44/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_45/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_46/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_47/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_48/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200300000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_49/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200320000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_50/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200330000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_51/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200340000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_52/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200350000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_53/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200360000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_54/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200370000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_55/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200380000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_56/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200390000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_57/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_58/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_59/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_60/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_61/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_62/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_63/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200410000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_64/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200420000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_65/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200430000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_66/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200440000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_67/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200450000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_68/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200460000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_69/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200480000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_70/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200490000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_71/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200470000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_8/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_9/s_axi_control/Reg] -force + assign_bd_address -offset 0x020101000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/base_logic/hw_discovery/s_axi_ctrl_pf0/reg0] -force + assign_bd_address -offset 0x020101040000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/clock_reset/pcie_mgmt_pdi_reset/pcie_mgmt_pdi_reset_gpio/S_AXI/Reg] -force + assign_bd_address -offset 0x0202004C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300080000 -range 0x00010000 -with_name SEG_traffic_producer_0_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300090000 -range 0x00010000 -with_name SEG_traffic_producer_1_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000A0000 -range 0x00010000 -with_name SEG_traffic_producer_2_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000B0000 -range 0x00010000 -with_name SEG_traffic_producer_3_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200500000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000C0000 -range 0x00010000 -with_name SEG_traffic_producer_4_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200510000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000D0000 -range 0x00010000 -with_name SEG_traffic_producer_5_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200520000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000E0000 -range 0x00010000 -with_name SEG_traffic_producer_6_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200530000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000F0000 -range 0x00010000 -with_name SEG_traffic_producer_7_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200540000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_virt_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200550000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_virt_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200560000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_virt_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200570000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_virt_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200580000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_virt_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020101001000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/base_logic/uuid_rom/S_AXI/reg0] -force + assign_bd_address -offset 0x020300150000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset 0x020300110000 -range 0x00010000 -with_name SEG_axi_gpio_datapath_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset 0x020300160000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset 0x020300100000 -range 0x00010000 -with_name SEG_axi_gpio_gt_control_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset 0x020300120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset 0x020300170000 -range 0x00010000 -with_name SEG_axi_gpio_monitor_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset 0x020300130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + assign_bd_address -offset 0x020300180000 -range 0x00010000 -with_name SEG_axi_gpio_reset_txrx_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM9_PC1] -force + assign_bd_address -offset 0x050080000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_CH1] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0xFFA80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_0] -force + assign_bd_address -offset 0xFFA90000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_1] -force + assign_bd_address -offset 0xFFAA0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_2] -force + assign_bd_address -offset 0xFFAB0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_3] -force + assign_bd_address -offset 0xFFAC0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_4] -force + assign_bd_address -offset 0xFFAD0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_5] -force + assign_bd_address -offset 0xFFAE0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_6] -force + assign_bd_address -offset 0xFFAF0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_7] -force + assign_bd_address -offset 0x000100800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_0] -force + assign_bd_address -offset 0x000100D10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_cti] -force + assign_bd_address -offset 0x000100D00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_dbg] -force + assign_bd_address -offset 0x000100D30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_etm] -force + assign_bd_address -offset 0x000100D20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_pmu] -force + assign_bd_address -offset 0x000100D50000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_cti] -force + assign_bd_address -offset 0x000100D40000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_dbg] -force + assign_bd_address -offset 0x000100D70000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_etm] -force + assign_bd_address -offset 0x000100D60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_pmu] -force + assign_bd_address -offset 0x000100CA0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_cti] -force + assign_bd_address -offset 0x000100C60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_ela] -force + assign_bd_address -offset 0x000100C30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_etf] -force + assign_bd_address -offset 0x000100C20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_fun] -force + assign_bd_address -offset 0x000100F80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_atm] -force + assign_bd_address -offset 0x000100FA0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_cti2a] -force + assign_bd_address -offset 0x000100FD0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_cti2d] -force + assign_bd_address -offset 0x000100F40000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2a] -force + assign_bd_address -offset 0x000100F50000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2b] -force + assign_bd_address -offset 0x000100F60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2c] -force + assign_bd_address -offset 0x000100F70000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2d] -force + assign_bd_address -offset 0x000100F20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_fun] -force + assign_bd_address -offset 0x000100F00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_rom] -force + assign_bd_address -offset 0x000100B80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_fpd_atm] -force + assign_bd_address -offset 0x000100B70000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_fpd_stm] -force + assign_bd_address -offset 0x000100980000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_lpd_atm] -force + assign_bd_address -offset 0xFC000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_cpm] -force + assign_bd_address -offset 0xFF5E0000 -range 0x00300000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_crl_0] -force + assign_bd_address -offset 0x000101260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_crp_0] -force + assign_bd_address -offset 0xFF0B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_gpio_2] -force + assign_bd_address -offset 0xFF020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_i2c_0] -force + assign_bd_address -offset 0xFF030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_i2c_1] -force + assign_bd_address -offset 0xFF360000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_3] -force + assign_bd_address -offset 0xFF370000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_4] -force + assign_bd_address -offset 0xFF380000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_5] -force + assign_bd_address -offset 0xFF3A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_6] -force + assign_bd_address -offset 0xFF320000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_pmc] -force + assign_bd_address -offset 0xFF390000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_pmc_nobuf] -force + assign_bd_address -offset 0xFF310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_psm] -force + assign_bd_address -offset 0xFF9B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_afi_0] -force + assign_bd_address -offset 0xFF0A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_iou_secure_slcr_0] -force + assign_bd_address -offset 0xFF080000 -range 0x00020000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_iou_slcr_0] -force + assign_bd_address -offset 0xFF410000 -range 0x00100000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_slcr_0] -force + assign_bd_address -offset 0xFF510000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_slcr_secure_0] -force + assign_bd_address -offset 0xFF990000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_xppu_0] -force + assign_bd_address -offset 0xFF960000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ocm_ctrl] -force + assign_bd_address -offset 0xFFFC0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ocm_ram_0] -force + assign_bd_address -offset 0xFF980000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ocm_xmpu_0] -force + assign_bd_address -offset 0x0001011E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_aes] -force + assign_bd_address -offset 0x0001011F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_bbram_ctrl] -force + assign_bd_address -offset 0x0001012D0000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_cfi_cframe_0] -force + assign_bd_address -offset 0x0001012B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_cfu_apb_0] -force + assign_bd_address -offset 0x0001011C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_dma_0] -force + assign_bd_address -offset 0x0001011D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_dma_1] -force + assign_bd_address -offset 0x000101250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_efuse_cache] -force + assign_bd_address -offset 0x000101240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_efuse_ctrl] -force + assign_bd_address -offset 0x000101110000 -range 0x00050000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_global_0] -force + assign_bd_address -offset 0x000101020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_gpio_0] -force + assign_bd_address -offset 0x000100280000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_iomodule_0] -force + assign_bd_address -offset 0x000101010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ospi_0] -force + assign_bd_address -offset 0x000100310000 -range 0x00008000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ppu1_mdm_0] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_qspi_ospi_flash_0] -force + assign_bd_address -offset 0x000102000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram] -force + assign_bd_address -offset 0x000100240000 -range 0x00020000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram_data_cntlr] -force + assign_bd_address -offset 0x000100200000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram_instr_cntlr] -force + assign_bd_address -offset 0x000106000000 -range 0x02000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram_npi] -force + assign_bd_address -offset 0x000101200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_rsa] -force + assign_bd_address -offset 0x0001012A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_rtc_0] -force + assign_bd_address -offset 0x000101040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_sd_0] -force + assign_bd_address -offset 0x000101210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_sha] -force + assign_bd_address -offset 0x000101220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_slave_boot] -force + assign_bd_address -offset 0x000102100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_slave_boot_stream] -force + assign_bd_address -offset 0x000101270000 -range 0x00030000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_sysmon_0] -force + assign_bd_address -offset 0x000100083000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_tmr_inject_0] -force + assign_bd_address -offset 0x000100283000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_tmr_manager_0] -force + assign_bd_address -offset 0x000101230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_trng] -force + assign_bd_address -offset 0x0001012F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_xmpu_0] -force + assign_bd_address -offset 0x000101310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_xppu_0] -force + assign_bd_address -offset 0x000101300000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_xppu_npi_0] -force + assign_bd_address -offset 0xFFC90000 -range 0x0000F000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_psm_global_reg] -force + assign_bd_address -offset 0xFFE90000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_r5_1_atcm_global] -force + assign_bd_address -offset 0xFFEB0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_r5_1_btcm_global] -force + assign_bd_address -offset 0xFFE00000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_r5_tcm_ram_global] -force + assign_bd_address -offset 0xFF9A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_rpu_0] -force + assign_bd_address -offset 0xFF000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_sbsauart_0] -force + assign_bd_address -offset 0xFF010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_sbsauart_1] -force + assign_bd_address -offset 0xFF130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_scntr_0] -force + assign_bd_address -offset 0xFF140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_scntrs_0] -force + assign_bd_address -offset 0xFF040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_spi_0] -force + assign_bd_address -offset 0xFF0E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_0] -force + assign_bd_address -offset 0xFF0F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_1] -force + assign_bd_address -offset 0xFF100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_2] -force + assign_bd_address -offset 0xFF110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_3] -force + assign_bd_address -offset 0x020300140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_0_n_1/DCMAC_subsys/dcmac_0_core/s_axi/Reg] -force + assign_bd_address -offset 0x020300190000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_2_n_3/DCMAC_subsys/dcmac_1_core/s_axi/Reg] -force + assign_bd_address -offset 0x020200000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/ddr_bandwidth_64/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/ddr_bandwidth_65/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/ddr_bandwidth_66/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/ddr_bandwidth_67/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020101010000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/base_logic/gcq_m2r/S00_AXI/S00_AXI_Reg] -force + assign_bd_address -offset 0x020200040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_10/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_11/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_12/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_13/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_14/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_15/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_16/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_17/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_18/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_19/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_20/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_21/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_22/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_23/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200150000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_24/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200160000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_25/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200170000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_26/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200180000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_27/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200190000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_28/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_29/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_30/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_31/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_32/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_33/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_34/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_35/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_36/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_37/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_38/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_39/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200270000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_40/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200280000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_41/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200290000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_42/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_43/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_44/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_45/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_46/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_47/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_48/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200300000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_49/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200320000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_50/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200330000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_51/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200340000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_52/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200350000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_53/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200360000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_54/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200370000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_55/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200380000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_56/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200390000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_57/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_58/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_59/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_60/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_61/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_62/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_63/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200410000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_64/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200420000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_65/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200430000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_66/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200440000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_67/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200450000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_68/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200460000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_69/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200480000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_70/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200490000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_71/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200470000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_8/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_9/s_axi_control/Reg] -force + assign_bd_address -offset 0x020101000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/base_logic/hw_discovery/s_axi_ctrl_pf0/reg0] -force + assign_bd_address -offset 0x020101040000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/clock_reset/pcie_mgmt_pdi_reset/pcie_mgmt_pdi_reset_gpio/S_AXI/Reg] -force + assign_bd_address -offset 0x0202004C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300080000 -range 0x00010000 -with_name SEG_traffic_producer_0_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300090000 -range 0x00010000 -with_name SEG_traffic_producer_1_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000A0000 -range 0x00010000 -with_name SEG_traffic_producer_2_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000B0000 -range 0x00010000 -with_name SEG_traffic_producer_3_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200500000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000C0000 -range 0x00010000 -with_name SEG_traffic_producer_4_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200510000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000D0000 -range 0x00010000 -with_name SEG_traffic_producer_5_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200520000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000E0000 -range 0x00010000 -with_name SEG_traffic_producer_6_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200530000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000F0000 -range 0x00010000 -with_name SEG_traffic_producer_7_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200540000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_virt_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200550000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_virt_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200560000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_virt_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200570000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_virt_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200580000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_virt_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020101001000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/base_logic/uuid_rom/S_AXI/reg0] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/LPD_AXI_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_LOW0] -force + assign_bd_address -offset 0x80044000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/M_AXI_LPD] [get_bd_addr_segs static_region/aved/base_logic/axi_smbus_rpu/S_AXI/Reg] -force + assign_bd_address -offset 0x80010000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/M_AXI_LPD] [get_bd_addr_segs static_region/aved/base_logic/gcq_m2r/S01_AXI/S01_AXI_Reg] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/PMC_NOC_AXI_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_LOW0] -force + assign_bd_address -offset 0x050080000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/PMC_NOC_AXI_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/PMC_NOC_AXI_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + + # Exclude Address Segments + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/traffic_virt_4/Data_m_axi_gmem0] [get_bd_addr_segs static_region/aved/cips/NOC_CPM_PCIE_0/pspmc_0_psv_noc_pcie_1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/traffic_virt_4/Data_m_axi_gmem0] [get_bd_addr_segs static_region/aved/cips/NOC_CPM_PCIE_0/pspmc_0_psv_noc_pcie_2] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_LOW0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_apu_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_crf_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_afi_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_afi_2] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_cci_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_gpv_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_maincci_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_slave_xmpu_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_slcr_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_slcr_secure_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_smmu_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_smmutcu_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_apu_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_crf_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_afi_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_afi_2] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_cci_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_gpv_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_maincci_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_slave_xmpu_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_slcr_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_slcr_secure_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_smmu_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_smmutcu_0] + + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] + exclude_bd_addr_seg -offset 0x050080000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/LPD_AXI_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/linker/resources/bd_ports.txt b/linker/resources/bd_ports.txt new file mode 100644 index 00000000..e67976ec --- /dev/null +++ b/linker/resources/bd_ports.txt @@ -0,0 +1,88 @@ +HBM0:HBM_AXI_00 AXI4FULL +HBM1:HBM_AXI_01 AXI4FULL +HBM2:HBM_AXI_02 AXI4FULL +HBM3:HBM_AXI_03 AXI4FULL +HBM4:HBM_AXI_04 AXI4FULL +HBM5:HBM_AXI_05 AXI4FULL +HBM6:HBM_AXI_06 AXI4FULL +HBM7:HBM_AXI_07 AXI4FULL +HBM8:HBM_AXI_08 AXI4FULL +HBM9:HBM_AXI_09 AXI4FULL +HBM10:HBM_AXI_10 AXI4FULL +HBM11:HBM_AXI_11 AXI4FULL +HBM12:HBM_AXI_12 AXI4FULL +HBM13:HBM_AXI_13 AXI4FULL +HBM14:HBM_AXI_14 AXI4FULL +HBM15:HBM_AXI_15 AXI4FULL +HBM16:HBM_AXI_16 AXI4FULL +HBM17:HBM_AXI_17 AXI4FULL +HBM18:HBM_AXI_18 AXI4FULL +HBM19:HBM_AXI_19 AXI4FULL +HBM20:HBM_AXI_20 AXI4FULL +HBM21:HBM_AXI_21 AXI4FULL +HBM22:HBM_AXI_22 AXI4FULL +HBM23:HBM_AXI_23 AXI4FULL +HBM24:HBM_AXI_24 AXI4FULL +HBM25:HBM_AXI_25 AXI4FULL +HBM26:HBM_AXI_26 AXI4FULL +HBM27:HBM_AXI_27 AXI4FULL +HBM28:HBM_AXI_28 AXI4FULL +HBM29:HBM_AXI_29 AXI4FULL +HBM30:HBM_AXI_30 AXI4FULL +HBM31:HBM_AXI_31 AXI4FULL +HBM32:HBM_AXI_32 AXI4FULL +HBM33:HBM_AXI_33 AXI4FULL +HBM34:HBM_AXI_34 AXI4FULL +HBM35:HBM_AXI_35 AXI4FULL +HBM36:HBM_AXI_36 AXI4FULL +HBM37:HBM_AXI_37 AXI4FULL +HBM38:HBM_AXI_38 AXI4FULL +HBM39:HBM_AXI_39 AXI4FULL +HBM40:HBM_AXI_40 AXI4FULL +HBM41:HBM_AXI_41 AXI4FULL +HBM42:HBM_AXI_42 AXI4FULL +HBM43:HBM_AXI_43 AXI4FULL +HBM44:HBM_AXI_44 AXI4FULL +HBM45:HBM_AXI_45 AXI4FULL +HBM46:HBM_AXI_46 AXI4FULL +HBM47:HBM_AXI_47 AXI4FULL +HBM48:HBM_AXI_48 AXI4FULL +HBM49:HBM_AXI_49 AXI4FULL +HBM50:HBM_AXI_50 AXI4FULL +HBM51:HBM_AXI_51 AXI4FULL +HBM52:HBM_AXI_52 AXI4FULL +HBM53:HBM_AXI_53 AXI4FULL +HBM54:HBM_AXI_54 AXI4FULL +HBM55:HBM_AXI_55 AXI4FULL +HBM56:HBM_AXI_56 AXI4FULL +HBM57:HBM_AXI_57 AXI4FULL +HBM58:HBM_AXI_58 AXI4FULL +HBM59:HBM_AXI_59 AXI4FULL +HBM60:HBM_AXI_60 AXI4FULL +HBM61:HBM_AXI_61 AXI4FULL +HBM62:HBM_AXI_62 AXI4FULL +HBM63:HBM_AXI_63 AXI4FULL + +DDR0:M00_INI AXI4FULL +DDR1:M01_INI AXI4FULL +DDR2:M02_INI AXI4FULL +DDR3:M03_INI AXI4FULL + +MEM:HBM_VNOC_INI_00 AXI4FULL +MEM:HBM_VNOC_INI_01 AXI4FULL +MEM:HBM_VNOC_INI_02 AXI4FULL +MEM:HBM_VNOC_INI_03 AXI4FULL +MEM:HBM_VNOC_INI_04 AXI4FULL +MEM:HBM_VNOC_INI_05 AXI4FULL +MEM:HBM_VNOC_INI_06 AXI4FULL +MEM:HBM_VNOC_INI_07 AXI4FULL + +VIRT0:SL_VIRT_0 AXI4FULL +VIRT1:SL_VIRT_1 AXI4FULL +VIRT2:SL_VIRT_2 AXI4FULL +VIRT3:SL_VIRT_3 AXI4FULL + +HOST:QDMA_SLAVE_BRIDGE AXI4FULL + +clock:aclk1 CLOCK +reset:ap_rst_n RESET diff --git a/linker/resources/config.cfg b/linker/resources/config.cfg new file mode 100644 index 00000000..d1d3a3c9 --- /dev/null +++ b/linker/resources/config.cfg @@ -0,0 +1,7 @@ +[connectivity] +nk=dma:1:dma_0 +nk=offset:1:offset_0 +stream_connect=offset_0.axis_out:dma_0.axis_in +sp=dma_0.m_axi_gmem0:HBM0 +sp=offset_0.m_axi_gmem0:DDR0 + diff --git a/linker/resources/dcmac/driver/axi_gt_controller.py b/linker/resources/dcmac/driver/axi_gt_controller.py new file mode 100644 index 00000000..d4ee7297 --- /dev/null +++ b/linker/resources/dcmac/driver/axi_gt_controller.py @@ -0,0 +1,121 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + + +import argparse +import numpy as np +import time +from axigpio_mmio import AxiGpioMMIO +from generic_mmio import hex_or_int, int_types +from utils import add_common_args, get_ip_offset + + +shift_map = { + 'gt_reset': {'shift': 0, 'bits': 1}, + 'gt_line_rate': {'shift': 1, 'bits': 8}, + 'loopback': {'shift': 9, 'bits': 3}, + 'txprecursor': {'shift': 12, 'bits': 6}, + 'txpostcursor': {'shift': 18, 'bits': 6}, + 'txmaincursor': {'shift': 24, 'bits': 6}, + 'rxcdrhold': {'shift': 31, 'bits': 1}, +} + + +def _get_shift_and_mask(key: str) -> tuple[int, int]: + """Return the shift and mask give the key""" + map = shift_map[key] + return map['shift'], (1 << map['bits']) - 1 + + +def _get_updated_value(key: str, cval: int, nval: int) -> int: + """Generate the updated 32-bit value applying a shift and mask""" + + shift, mask = _get_shift_and_mask(key) + shiftedmask = np.uint32(mask << shift & 0xFFFF_FFFF) + cval_cleared = np.uint32(cval & ~shiftedmask) + shiftedval = np.uint32(((nval & mask) << shift) & 0xFFFF_FFFF) + + return np.uint32(shiftedval | cval_cleared) + + +class AxiGTController(AxiGpioMMIO): + + def __init__(self, device: str = 'e2', base_offset: int = 0x0, + gpio_index: int = 0): + self._gpio_index = gpio_index + super().__init__(device, base_offset) + + def _get(self, key: str, gpio: int = 0): + shift, mask = _get_shift_and_mask(key) + return (self.read(gpio) >> shift) & mask + + def _set(self, key: str, gpio: int, val: int): + if not isinstance(val, int_types): + raise ValueError(f"'{val=}' is not a '{int_types}' type") + + cval = self.read(gpio) + uval = _get_updated_value(key, cval, val) + self.write(gpio, uval) + + def _create_property(key: str, gpio: int = 0): + """Create property getter and setter for given key.""" + return property( + lambda self: self._get(key, gpio), + lambda self, val: self._set(key, gpio, val) + ) + + gt_reset = _create_property('gt_reset') + gt_line_rate = _create_property('gt_line_rate') + loopback = _create_property('loopback') + txprecursor = _create_property('txprecursor') + txpostcursor = _create_property('txpostcursor') + txmaincursor = _create_property('txmaincursor') + rxcdrhold = _create_property('rxcdrhold') + + +def main(args): + offset = get_ip_offset(0x204_0000, args.dcmac) + obj = AxiGTController(args.dev, offset, gpio_index=0) + + if args.reset: + print('Resetting GT') + obj.gt_reset = 1 + time.sleep(0.1) + obj.gt_reset = 0 + return + + if args.loopback is not None: + obj.loopback = args.loopback + time.sleep(0.1) + print(f'Loopback mode set to: {obj.loopback}') + return + + if args.linerate: + obj.gt_line_rate = args.linerate + time.sleep(0.1) + print(f'Line rate mode set to: {obj.gt_line_rate}') + return + + print(f'{obj.gt_reset=}') + print(f'{obj.gt_line_rate=}') + print(f'{obj.loopback=}') + print(f'{obj.txprecursor=}') + print(f'{obj.txpostcursor=}') + print(f'{obj.txmaincursor=}') + print(f'{obj.rxcdrhold=}') + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-l', '--loopback', type=hex_or_int, help="Loopback " + f" mode, a {shift_map['loopback']['bits']}-bit value", + default=None) + parser.add_argument('-r', '--reset', action='store_true', + help='Reset GT') + parser.add_argument('-s', '--linerate', help="Line-rate mode a " + f"{shift_map['gt_line_rate']['bits']}-bit value", + type=hex_or_int) + parser = add_common_args(parser) + + main(parser.parse_args()) diff --git a/linker/resources/dcmac/driver/axigpio_mmio.py b/linker/resources/dcmac/driver/axigpio_mmio.py new file mode 100644 index 00000000..80eeae77 --- /dev/null +++ b/linker/resources/dcmac/driver/axigpio_mmio.py @@ -0,0 +1,96 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + + +import argparse +from generic_mmio import GenericMMIO, int_types +from utils import add_common_args, get_ip_offset + + +key_map_offset = { + 'gpio_tri': 0x4, + 'gpio2_tri': 0xc, + 'gier': 0x11C, + 'ip_ier': 0x128, + 'ip_isr': 0x120, +} + + +class AxiGpioMMIO(GenericMMIO): + """Driver to work with AXI GPIO""" + + _data_off = 0 + _tri_off = 4 + + def write(self, gpio: int = 0, value: int = 0): + """Write to """ + offset = self._data_off + 0x8 * gpio + super().write(offset, value) + + def read(self, gpio: int = 0): + offset = self._data_off + 0x8 * gpio + return super().read(offset) + + def _get(self, key: str): + offset = key_map_offset[key] + return super().read(offset) + + def _set(self, key: str, val: int): + if not isinstance(val, int_types): + raise ValueError(f"'{val=}' is not a '{int_types}' type") + offset = key_map_offset[key] + super().write(offset, val) + + def _create_property(key: str): + """Create property getter and setter for given key.""" + return property( + lambda self: self._get(key), + lambda self, val: self._set(key, val) + ) + + gpio_tri = _create_property('gpio_tri') + gpio2_tri = _create_property('gpio2_tri') + gier = _create_property('gier') + ip_ier = _create_property('ip_ier') + ip_isr = _create_property('ip_isr') + + +def main(args): + value = 0 + if args.reset: + value = (2**32) - 1 + + offset0 = get_ip_offset(0x204_0000, args.dcmac) + obj = AxiGpioMMIO(args.dev, offset0) + obj.write(0, value) + print(f'GPIO1: 0x{obj.base_address:X}, value={obj.read(0)}') + obj.write(1, value) + print(f'GPIO2: 0x{obj.base_address:X}, value={obj.read(1)}') + del obj + + offset1 = get_ip_offset(0x204_0100, args.dcmac) + obj = AxiGpioMMIO(args.dev, offset1) + obj.write(0, value) + print(f'GPIO1: 0x{obj.base_address:X}, value={obj.read(0)}') + obj.write(1, value) + print(f'GPIO2: 0x{obj.base_address:X}, value={obj.read(1)}') + del obj + + offset2 = get_ip_offset(0x204_0300, args.dcmac) + obj = AxiGpioMMIO(args.dev, offset2) + obj.write(0, value) + print(f'GPIO1: 0x{obj.base_address:X}, value={obj.read(0)}') + obj.write(1, value) + print(f'GPIO2: 0x{obj.base_address:X}, value={obj.read(1)}') + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-r', '--reset', action='store_true', + help='Reset Logic') + parser = add_common_args(parser) + + args = parser.parse_args() + + main(args) diff --git a/linker/resources/dcmac/driver/dcmac_init.py b/linker/resources/dcmac/driver/dcmac_init.py new file mode 100644 index 00000000..212ef9f9 --- /dev/null +++ b/linker/resources/dcmac/driver/dcmac_init.py @@ -0,0 +1,164 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +import time +from axi_gt_controller import AxiGTController +from dcmac_mmio import DCMAC +from generic_mmio import hex_or_int +from gpio_monitor import AxiGPIOMonitor +from axigpio_mmio import AxiGpioMMIO +from utils import add_common_args, get_ip_offset + +def dcmac_reset_procedure(reset_tx: bool = True, dcmac_idx: int = 0): + """Reset DCMAC and GTs""" + global intf_id, dcmac, gt_gpio, monitor, gtdatapath + print(f'Working with {dcmac_idx=}') + # 1: reset GTs + if reset_tx: + print(" Resetting Tx GTs ", end= "", flush=True) + gt_gpio.gt_reset = 1 + time.sleep(0.001) + gt_gpio.gt_reset = 0 + else: + print(" Resetting only GTs RX datapath ", end= "", flush=True) + gtdatapath.write(0x0, 0xF) + time.sleep(0.01) + gtdatapath.write(0x0, 0x0) + + # 2: Wait for GT reset to finish + for _ in range(20): + signed_to_check = [f'gt{intf_id}_tx_reset_done',f'gt{intf_id}_rx_reset_done'] + ready = True + for signal in signed_to_check: + ready &= getattr(monitor, signal) == 0xF + if ready: + print(f"Done -> ", end= "", flush=True) + break + print(".", end= "", flush=True) + time.sleep(0.1) + else: + print(f"GTs not comming out of reset after 2 sec. Exiting...") + print(f" Debug info: {monitor.gt0_tx_reset_done=}, {monitor.gt1_tx_reset_done=}") + print(f" {monitor.gtpowergood=}") + time.sleep(0.1) + # time.sleep(0.5) + + # 3: reset DCMAC Tx + tx_rst_success = None + if reset_tx: + print("Resetting DCMAC Tx -> ", end= "", flush=True) + # status will be cleared after Rx reset, if successful + tx_rst_success = dcmac.reset_tx(clear_status_history= False) + + # 4: reset DCMAC Rx + print("Resetting DCMAC Rx ", end= "", flush=True) + rx_rst_success = dcmac.reset_rx(clear_status_history= True) + return tx_rst_success, rx_rst_success + +def dcmac_logic_init(args): + global intf_id, dcmac, gt_gpio, monitor, gtdatapath + + intf_id = 0 # TODO: in the future, we'll have 2 interfaces per DCMAC + dcmac = DCMAC(args.dev, get_ip_offset(0x200_0000, args.dcmac)) + gt_gpio = AxiGTController(args.dev, get_ip_offset(0x204_0000, args.dcmac), + gpio_index=0) + monitor = AxiGPIOMonitor(args.dev, get_ip_offset(0x204_0200, args.dcmac), gpio_index=0) + gtdatapath = AxiGpioMMIO(args.dev, get_ip_offset(0x204_0400, args.dcmac)) + + # Set GT Tx analog front-end swing and pre/post-emphasis: + # TODO: Fine-tune the following configuration. In general, this achieves alignment, + # 24 dB SNR and seems to stay aligned for a couple of days + # These values are now set by default in the GPIO + #gt_gpio.txprecursor = 6 + #gt_gpio.txmaincursor = 52 + #gt_gpio.txpostcursor = 6 + + if args.verbose > 0: + print(f'{dcmac._base_offset=:#x}') + print(f'{gt_gpio._base_offset=:#x}') + print(f'{monitor._base_offset=:#x}') + print(f'{gtdatapath._base_offset=:#x}') + print(f'{monitor.dual_dcmac=}') + print(f'{gt_gpio.txprecursor=}') + print(f'{gt_gpio.txmaincursor=}') + print(f'{gt_gpio.txpostcursor=}') + + if args.loopback is not None: + if args.loopback != args.loopback: + gt_gpio.loopback = args.loopback + time.sleep(0.1) + print(f'Loopback mode set to: {gt_gpio.loopback}') + args.init = True + + if args.keep_alive: + print('Keep ALIVE path') + iters = 0 + init_time = time.time() + prev_link_up = dcmac.link_up + while True: + iters += 1 + if dcmac.link_up: + if iters % 100 == 0: + print(f"\rDCMAC {args.dcmac} link still up after {time.time() - init_time:.1f} s", end="", flush=True) + else: + if prev_link_up: + print(f" | Link Down |") + dcmac_reset_procedure(not dcmac.tx_aligned, args.dcmac) + if dcmac.link_up: + print(" | Link up again") + init_time = time.time() + prev_link_up = dcmac.link_up + time.sleep(0.05) + + # TODO, we need an independent reset TX code + if args.init or args.align_rx: + print(f'INIT or ALIGN RX. {args.init=} {args.align_rx=}') + if args.verbose > 1: + dcmac.print_config(False) + print(f"{gt_gpio.loopback=}") + print(f"{gt_gpio.txprecursor=}") + print(f"{gt_gpio.txmaincursor=}") + print(f"{gt_gpio.txpostcursor=}") + print('\nResetting GT -> DCMAC Tx -> DCMAC Rx') + + NUM_OF_RETRIES = 10 + reset_tx = args.init + # Iterate through reset routine until MAC is ready or we run out of retries + for retry_id in range(NUM_OF_RETRIES): + tx_rst_success, rx_rst_success = dcmac_reset_procedure(reset_tx, args.dcmac) + tx_rst_success = tx_rst_success if reset_tx else True + reset_tx = tx_rst_success + if tx_rst_success and rx_rst_success: + print(f"DCMAC initialization successful after {retry_id} retries") + break + else: + print(f"DCMAC initialization failed after {NUM_OF_RETRIES} retries. DCMAC state:") + dcmac.print_status(only_modified_fields=True) + print(f"Exiting...") + exit(1) + + if args.verbose > 0: + dcmac.print_status(only_modified_fields=args.verbose < 2) + + dcmac.tx_stats(0, True, verbose=args.verbose) + dcmac.rx_stats(0, True, verbose=args.verbose) + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-i', '--init', action='store_true', + help='Initialize system') + parser.add_argument('-a', '--align_rx', action='store_true',help='Align RX') + parser.add_argument('-k', '--keep_alive', action='store_true',help='Keep link alive') + parser.add_argument('-l', '--loopback', type=hex_or_int, + help="Set GT Loopback", default=None) + parser.add_argument('-t', '--traffic_test', action='store_true', + help='Run traffic test') + # default only status + parser.add_argument('-p', '--print', action='store_true', + help='Print stats') + parser = add_common_args(parser, verbose=True) + + args = parser.parse_args() + dcmac_logic_init(args) diff --git a/linker/resources/dcmac/driver/dcmac_mmio.py b/linker/resources/dcmac/driver/dcmac_mmio.py new file mode 100644 index 00000000..f6245438 --- /dev/null +++ b/linker/resources/dcmac/driver/dcmac_mmio.py @@ -0,0 +1,437 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +import pprint +import time +from tabulate import tabulate +from generic_mmio import GenericMMIO +from dcmac_reg import registers, tx_stats_base_reg, rx_stats_base_reg +from utils import rshift, add_common_args, get_ip_offset + +class DCMAC(GenericMMIO): + """"DCMAC MMIO Driver""" + + def __init__(self, device: str = 'e2', base_offset: int = 0x0): + super().__init__(device, base_offset) + self.set_pm_tick_trigger() + + def write(self, offset, value): + if isinstance(offset, str): + offset = registers[offset]['offset'] + super().write(offset, value) + + def read(self, offset): + if isinstance(offset, str): + offset = registers[offset]['offset'] + return super().read(offset) + + #TODO: __getattr__ and __setattr__ need more validation + def __getattr__(self, name): + """Get the value of a register""" + if name in registers: + val = self.read(name) + if registers[name].get('fields'): + field_dict = dict() + for k, v in registers[name]['fields'].items(): + field_dict[k] = rshift(val, v['start'], v['length']) + return field_dict + else: + return val + else: + raise AttributeError(f"'{self.__class__.__name__}' object has " + f"no attribute '{name}'") + + #TODO: validate + def __setattr__(self, name, value): + """Set the value of a register""" + if name in registers: + # TODO: accept value as a dictionary to set individual fields + if isinstance(value, dict): + values_dict = value + value = self.read(name) + reg_fields = registers[name].get('fields', {}) + for field_name, field_value in values_dict.items(): + if field_name in reg_fields: + field = registers[name]['fields'][field_name] + start, length = field['start'], field['length'] + mask = ((1 << length) - 1) << start + value &= ~ mask # clear the bits + value |= (field_value << start) & mask # set the bits + else: + raise ValueError(f"Field '{field_name}' not found " + f"in register '{name}'") + + self.write(name, value) + else: + super().__setattr__(name, value) + + # TODO: implement functions to read and write channel registers without + # having to specify the channel offset, just the channel number + # def read_chn_reg(self, chn_reg_name, channel): + # offset = registers['C0_' + chn_reg_name]['offset'] + # return self._pciemmio.read(self._offset + offset) + + def read_reg_field(self, reg_name: str, field: str): + """Read a field from reg'""" + field = registers[reg_name]['fields'][field] + val = self.read(reg_name) + return rshift(val, field['start'], field['length']) + + def read_long(self, offset) -> int: + """Read 8 bytes from BAR 'offset'""" + if isinstance(offset, str): + offset = registers[offset]['offset'] + val_low = self.read(offset) + val_high = self.read(offset + 4) + return int((val_high << 32) + val_low) + + @property + def revision(self): + return self.read('CONFIGURATION_REVISION') + + @property + def ip_dict(self): + vals = {} + for k, v in registers.items(): + readval = self.read(v['offset']) + vals[k] = {'value': readval} + if v.get('fields'): + vals[k]['fields'] = {} + for k1, v1 in v['fields'].items(): + vals[k]['fields'][k1] = rshift(readval, v1['start'], v1['length']) + + return vals + + @property + def status(self): + status_dict = {} + for reg_name, spec in registers.items(): + if "STATUS" in reg_name: + fields = spec.get('fields', False) + readval = self.read(reg_name) + subkey = "real-time" if "_RT_" in reg_name else "latched" + entry_name = reg_name if "_RT_" not in reg_name else reg_name.replace("_RT", "") + if entry_name not in status_dict: + if fields: + status_dict[entry_name] = {} + for f in fields: + + status_dict[entry_name][f] = {"latched": "-", "real-time": "-", "default": fields[f]['default']} + else: + status_dict[entry_name] = {"latched": "-", "real-time": "-", "default": "-"} + + if fields: + for f_name, f_spec in fields.items(): + status_dict[entry_name][f_name][subkey] = rshift(readval, f_spec['start'], f_spec['length']) + else: + status_dict[entry_name][subkey] = readval + return status_dict + + def print_status(self, only_modified_fields: bool = False): + status_dict = self.status + table = [] + table += [["Register", "Field", "Latched", "Real-Time", "Default"]] + for reg_name, fields in status_dict.items(): + row_count = 0 + for field_name, field in fields.items(): + default_val = field["default"] + if only_modified_fields: + if field["latched"] == default_val and field["real-time"] == default_val: + continue + table += [[reg_name if row_count == 0 else "", field_name, field["latched"], field["real-time"], default_val]] + row_count += 1 + if row_count > 0: + table += [["--------------------", "--------------------", "--------", "--------", "--------"]] + if only_modified_fields: + if len(table) == 1: + print("All status Registers have default values") + return + print("Status Registers with non-default values") + else: + print("Status Registers") + print(tabulate(table, headers="firstrow", tablefmt="pretty")) + + @property + def config(self): + config_dict = {} + config_regs = ['GLOBAL_MODE', 'C0_TX_MODE_REG', 'C0_RX_MODE_REG'] + for reg_name in config_regs: + spec = registers[reg_name] + fields = spec.get('fields', False) + readval = self.read(spec['offset']) + config_dict[reg_name] = {} + for f_name, f_spec in fields.items(): + val = rshift(readval, f_spec['start'], f_spec['length']) + config_dict[reg_name][f_name] = {"value": val, "default": fields[f_name]['default']} + + return config_dict + + def print_config(self, only_modified_fields: bool = False): + config_dict = self.config + table = [] + table += [["Register", "Field", "Value", "Default"]] + for reg_name, fields in config_dict.items(): + row_count = 0 + for field_name, field in fields.items(): + default_val = field["default"] + if only_modified_fields: + if field["value"] == default_val: + continue + table += [[reg_name if row_count == 0 else "", field_name, field["value"], default_val]] + row_count += 1 + if row_count > 0: + table += [["--------------------", "--------------------", "--------", "--------", "--------"]] + if only_modified_fields: + print("Configuration Registers with non-default values") + else: + print("Configuration Registers") + print(tabulate(table, headers="firstrow", tablefmt="pretty")) + + def tx_stats(self, port: int = 0, debug: bool = False, + verbose: int = 0): + """Reads and print TX stats for the given port""" + + if isinstance(port, int) and not 0 <= port < 1: + raise ValueError("'port' must be either 0 or 1") + + baseoffset = 0x1000 * (port + 1) + 0x0200 + + # Sets pm tick to be triggered by registers + value = self.read(baseoffset - 0x200 + 0x40) + pm_tick_bit = registers['C0_TX_MODE_REG']['fields']['c0_ctl_tx_tick_reg_mode_sel']['start'] + value |= (1 * (2**pm_tick_bit)) + self.write(baseoffset - 0x200 + 0x40, value) + + # trigger ALL_CHANNEL_MAC_TICK_REG_TX + #offset = registers['ALL_CHANNEL_MAC_TICK_REG_TX']['offset'] + #self.write(offset, 0) + #self.write(offset, 1) + #self.write(offset, 0) + + # trigger pm tick + self.write(baseoffset - 0x200 + 0xFC, 0) + self.write(baseoffset - 0x200 + 0xFC, 1) + + for i in range(10): + val = self.read(baseoffset - 0x200 + 0x808) + if val != 0: + break + + heading = [[f"TX Stats {port=}", "Value"]] + if debug: + heading[0].append('Offset Address') + table = self._stats(baseoffset, 'tx', heading, debug, verbose) + print(tabulate(table, headers="firstrow", tablefmt="pretty")) + + def rx_stats(self, port: int = 0, debug: bool = False, + verbose: int = 0): + """Reads and print RX stats for the given port""" + + if isinstance(port, int) and not 0 <= port < 1: + raise ValueError("'port' must be either 0 or 1") + + baseoffset = 0x1000 * (port + 1) + 0x0400 + + # Sets pm tick to be triggered by registers + value = self.read(baseoffset - 0x400 + 0x44) + pm_tick_bit = registers['C0_RX_MODE_REG']['fields']['c0_ctl_rx_tick_reg_mode_sel']['start'] + value |= (1 * (2**pm_tick_bit)) + self.write(baseoffset - 0x400 + 0x44, value) + + # trigger ALL_CHANNEL_MAC_TICK_REG_RX + #offset = registers['ALL_CHANNEL_MAC_TICK_REG_RX']['offset'] + #self.write(offset, 0) + #self.write(offset, 1) + #self.write(offset, 0) + + # trigger pm tick + self.write(baseoffset - 0x400 + 0xF4, 0) + self.write(baseoffset - 0x400 + 0xF4, 1) + + for i in range(10): + val = self.read(baseoffset - 0x400 + 0xC08) + if val != 0: + break + + heading = [[f"RX Stats {port=}", "Value"]] + if debug: + heading[0].append('Offset Address') + table = self._stats(baseoffset, 'rx', heading, debug, verbose) + print(tabulate(table, headers="firstrow", tablefmt="pretty")) + + def _stats(self, baseoffset: int, dir: str, tableheading: str, + debug: bool, verbose: int = 0): + + table = tableheading + stats_base_reg = tx_stats_base_reg if dir == 'tx' else rx_stats_base_reg + for k, v in stats_base_reg.items(): + if 'LSB' in k: + readval = self.read_long(baseoffset + v['offset']) + elif 'MSB' in k: + continue + else: + readval = self.read(baseoffset + v['offset']) + + if readval == 0 and verbose < 1: + continue + key = k.replace('_LSB', '') + ltable = [key, readval] + if debug: + ltable.append(f"0x{(baseoffset + v['offset']):X}") + table.append(ltable) + + return table + + def clear_latched_flags(self): + MASK = (1 << 32) - 1 + for reg_name, spec in registers.items(): + if "STATUS" in reg_name: + self.write(spec['offset'], MASK) + + def set_pm_tick_trigger(self) -> int: + """Sets pm tick to be triggered by registers""" + value = self.read(registers['GLOBAL_MODE']['offset']) + tx_reg_bit = registers['GLOBAL_MODE']['fields']['ctl_tx_all_ch_tick_reg_mode_sel']['start'] + rx_reg_bit = registers['GLOBAL_MODE']['fields']['ctl_rx_all_ch_tick_reg_mode_sel']['start'] + + val_tx = 1 * (2**tx_reg_bit) + val_rx = 1 * (2**rx_reg_bit) + val_tx += val_rx + + value |= val_tx + self.write(registers['GLOBAL_MODE']['offset'], value) + return self.read(registers['GLOBAL_MODE']['offset']) + + def reset_tx(self, clear_status_history: bool = True): + """Forces a resets on the transmitting DCMAC core + It Follows the reset procedure outlined in the DCMAC user guide pg369, + page 161 ("Transmit Fixed Ethernet Startup Procedure when Using tx_core_reset") + """ + rst_successful = True + offset = lambda x: registers[x]['offset'] + rst_core_regs = [offset('GLOBAL_CONTROL_REG_TX')] + rst_serdes_regs = [offset('C0_PORT_CONTROL_REG_TX') + 0x1000 * i for i in range(6)] + rst_flush_regs = [offset('C0_CHANNEL_CONTROL_REG_TX') + 0x1000 * i for i in range(6)] + for reg in rst_core_regs + rst_serdes_regs + rst_flush_regs: + self.write(reg, 2**32-1) + time.sleep(0.1) + # first release port RSTs, then core reset + for reg in rst_serdes_regs + rst_core_regs: + self.write(reg, 0x0) + + # wait for tx_local_fault + for _ in range(10): + if self.tx_aligned: + # print('TX status: OK') + break + time.sleep(0.2) + else: + print('TX status: local fault') + rst_successful = False + + # release flush + for reg in rst_flush_regs: + self.write(reg, 0x0) + + if clear_status_history: + self.clear_latched_flags() + return rst_successful + + def reset_rx(self, clear_status_history: bool = True): + """Forces a resets on the receiving DCMAC core + It Follows the reset procedure outlined in the DCMAC user guide pg369, + page 162 ("Receive Fixed Ethernet Startup Procedure when Using rx_core_reset") + """ + ACTIVE_PORTS = 6 # TODO: this should be set by the user + offset = lambda x: registers[x]['offset'] + rst_core_regs = [(offset('GLOBAL_CONTROL_REG_RX'), 7)] + rst_serdes_regs = [(offset('C0_PORT_CONTROL_REG_RX') + 0x1000 * i, 2) for i in range(6)] + rst_flush_regs = [(offset('C0_CHANNEL_CONTROL_REG_RX') + 0x1000 * i, 1) for i in range(6)] + for reg,reset_code in rst_core_regs + rst_serdes_regs + rst_flush_regs: + self.write(reg, reset_code) + + time.sleep(0.5) + # first release core resets, then flush and finally serdes resets + for reg,_ in rst_core_regs + rst_flush_regs[:ACTIVE_PORTS] + rst_serdes_regs[:ACTIVE_PORTS]: + self.write(reg, 0) + + # check Rx alignment + rst_successful = True + for i in range(10): + if self.rx_aligned: + break + print(".", end= "", flush=True) + time.sleep(0.25) + else: + print('WARN: Chn 0 RX failed to achieve alignment') + rst_successful = False + + if clear_status_history: + self.clear_latched_flags() + return rst_successful + + @property + def tx_aligned(self): + # TODO: this should take the channel number as an argument and + # return the corresponding channel status + return self.C0_STAT_CHAN_TX_MAC_RT_STATUS_REG['c0_stat_tx_local_fault'] == 0 + + @property + def rx_aligned(self): + # TODO: this should take the channel number as an argument and + # return the corresponding channel status + chn_status_dict = self.C0_STAT_PORT_RX_PHY_RT_STATUS_REG + return chn_status_dict['c0_stat_rx_status'] == 1 and \ + chn_status_dict['c0_stat_rx_aligned'] == 1 + + @property + def link_up(self): + return self.rx_aligned and self.tx_aligned + +def main(args): + offset = get_ip_offset(0x200_0000, args.dcmac) + obj = DCMAC(args.dev, offset) + + if args.tx: + obj.reset_tx() + + if args.rx: + obj.reset_rx() + + if args.rx or args.tx or args.clear: + time.sleep(0.5) + obj.clear_latched_flags() + + if args.status or not (args.rx or args.tx or args.print or args.show_config): + obj.print_status(only_modified_fields=args.verbose < 1) + + if args.show_config: + obj.print_config(only_modified_fields=args.verbose < 1) + + if args.print: + # pprint.pp(obj.ip_dict) + obj.tx_stats(0, True, verbose=args.verbose) + obj.rx_stats(0, True, verbose=args.verbose) + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-r', '--rx', action='store_true', + help='Reset RX') + parser.add_argument('-t', '--tx', action='store_true', + help='Reset TX') + parser.add_argument('-s', '--status', action='store_true', + help='Print status') + # default only status + parser.add_argument('-p', '--print', action='store_true', + help='Print stats') + parser.add_argument('-c', '--clear', action='store_true', + help='Clear latched flags') + parser.add_argument('-C', '--show-config', action='store_true', + help='Show configuration') + parser = add_common_args(parser, verbose=True) + + args = parser.parse_args() + main(args) \ No newline at end of file diff --git a/linker/resources/dcmac/driver/dcmac_reg.py b/linker/resources/dcmac/driver/dcmac_reg.py new file mode 100644 index 00000000..cdcb2bb0 --- /dev/null +++ b/linker/resources/dcmac/driver/dcmac_reg.py @@ -0,0 +1,623 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +registers = { + 'CONFIGURATION_REVISION': {'offset': 0x0, 'type': 'ro'}, + 'GLOBAL_MODE': { + 'offset': 0x4, 'type': 'rw', + 'fields': { + 'ctl_tx_independent_tsmac_and_phy_mode': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_tx_all_ch_tick_reg_mode_sel': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_rx_independent_tsmac_and_phy_mode': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_rx_all_ch_tick_reg_mode_sel': {'start': 5, 'length': 1, 'default': '0', 'type': 'rw'}, + 'ctl_tx_axis_cfg': {'start': 8, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_rx_axis_cfg': {'start': 12, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_tx_pcs_active_ports': {'start': 16, 'length': 3, 'default': 5, 'type': 'rw'}, + 'ctl_rx_pcs_active_ports': {'start': 20, 'length': 3, 'default': 5, 'type': 'rw'}, + 'ctl_rx_fec_errind_mode': {'start': 24, 'length': 1, 'default': 1, 'type': 'rw'}, + 'ctl_tx_fec_ck_unique_flip': {'start': 25, 'length': 1, 'default': 1, 'type': 'rw'}, + 'ctl_rx_fec_ck_unique_flip': {'start': 26, 'length': 1, 'default': 1, 'type': 'rw'} + } + }, + 'TEST_DEBUG': { + 'offset': 0x8, 'type': 'rw', + 'fields': { + 'ctl_test_mode_pin_char': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_test_mode_memcel': {'start': 4, 'length': 4, 'default': 0, 'type': 'rw'}, + 'ctl_rx_phy_debug_select': {'start': 8, 'length': 5, 'default': 0, 'type': 'rw'}, + 'ctl_rx_mac_debug_select': {'start': 13, 'length': 4, 'default': 0, 'type': 'rw'}, + 'ctl_tx_phy_debug_select': {'start': 17, 'length': 4, 'default': 0, 'type': 'rw'}, + 'ctl_tx_mac_debug_select': {'start': 21, 'length': 4, 'default': 0, 'type': 'rw'}, + 'ctl_rx_ecc_err_clear': {'start': 25, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_tx_ecc_err_clear': {'start': 26, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_tx_ecc_err_count_tick': {'start': 27, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_axi_af_thresh_override': {'start': 28, 'length': 4, 'default': 8, 'type': 'rw'} + } + }, + 'EMA_CONFIGURATION': { + 'offset': 0xC, 'type': 'rw', + 'fields': { + 'ctl_mem_ctrl': {'start': 0, 'length': 10, 'default': 0x11b, 'type': 'rw'}, + 'emaa': {'start': 0, 'length': 3, 'default': 0x3, 'type': 'rw'}, + 'emab': {'start': 3, 'length': 3, 'default': 0x3, 'type': 'rw'}, + 'emasa': {'start': 6, 'length': 1, 'default': 0x0, 'type': 'rw'}, + 'stov': {'start': 7, 'length': 1, 'default': 0x0, 'type': 'rw'}, + 'mc_mem_ctrl_enable': {'start': 8, 'length': 1, 'default': 0x1, 'type': 'rw'} + } + }, + 'CLOCK_DISABLE': { + 'offset': 0x10, 'type': 'rw', + 'fields': { + 'ctl_mem_disable_rx_axi_clk': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_axi_clk': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_macif_clk': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_macif_clk': {'start': 3, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_core_clk': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_core_clk': {'start': 5, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_flexif_clk': {'start': 6, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_flexif_clk': {'start': 12, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_serdes_clk': {'start': 18, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_serdes_clk': {'start': 24, 'length': 6, 'default': 0, 'type': 'rw'} + } + }, + 'BLOCK_DISABLE': { + 'offset': 0x14, 'type': 'rw', + 'fields': { + 'ctl_mem_disable_rx_pcs_cpcs': {'start': 0, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_pcs_align_buffer': {'start': 6, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_pcs_decoder': {'start': 12, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_pcs_cpcs': {'start': 16, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_ts2phy': {'start': 22, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_pcs_encoder': {'start': 23, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY0': { + 'offset': 0x18, 'type': 'rw', + 'fields': { + 'ctl_rsvd0': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY1': { + 'offset': 0x1C, 'type': 'rw', + 'fields': { + 'ctl_rsvd1': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY2': { + 'offset': 0x20, 'type': 'rw', + 'fields': { + 'ctl_rsvd2': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY3': { + 'offset': 0x24, 'type': 'rw', + 'fields': { + 'ctl_rsvd3': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY4': { + 'offset': 0x28, 'type': 'rw', + 'fields': { + 'ctl_rsvd4': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY5': { + 'offset': 0x2C, 'type': 'rw', + 'fields': { + 'ctl_rsvd5': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY6': { + 'offset': 0x30, 'type': 'rw', + 'fields': { + 'ctl_rsvd6': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY7': { + 'offset': 0x34, 'type': 'rw', + 'fields': { + 'ctl_rsvd7': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'MAC_CONFIG_REG_TX_WR': { + 'offset': 0x38, 'type': 'rw', + 'fields': { + 'mac_tx_cfg_data': {'start': 0, 'length': 8, 'default': 0, 'type': 'rw'}, + 'mac_tx_cfg_index': {'start': 8, 'length': 5, 'default': 0, 'type': 'rw'}, + 'mac_tx_cfg_channel': {'start': 16, 'length': 6, 'default': 0, 'type': 'rw'}, + 'mac_tx_cfg_wr': {'start': 24, 'length': 1, 'default': 0, 'type': 'rw'}, + 'mac_tx_cfg_enable': {'start': 28, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'MAC_CONFIG_REG_TX_RD': { + 'offset': 0x3C, 'type': 'rw', + 'fields': { + 'mac_tx_cfg_data_rd': {'start': 0, 'length': 8, 'default': 0, 'type': 'rw'} + } + }, + 'GLOBAL_CONTROL_REG_RX': { + 'offset': 0xF0, 'type': 'rw', + 'fields': { + 'soft_rx_core_reset': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'soft_rx_macif_reset': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'}, + 'soft_rx_axi_reset': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + }, + }, + 'ALL_CHANNEL_MAC_TICK_REG_RX': { + 'offset': 0xF4, 'type': 'rw', + 'fields': { + 'rx_all_channel_mac_soft_pm_tick': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'} + }, + }, + 'GLOBAL_CONTROL_REG_TX': { + 'offset': 0xF8, 'type': 'rw', + 'fields': { + 'soft_tx_core_reset': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'soft_tx_macif_reset': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'}, + 'soft_tx_axi_reset': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'} + }, + }, + 'ALL_CHANNEL_MAC_TICK_REG_TX': { + 'offset': 0xFC, 'type': 'rw', + 'fields': { + 'rx_all_channel_mac_soft_pm_tick': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'} + }, + }, + 'STAT_TX_ECC_ERR_REG': { + 'offset': 0x1B0, 'type': 'ro', + 'fields': { + 'stat_tx_ecc0_err0': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc0_err1': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc1_err0': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc1_err1': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc2_err0': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc2_err1': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + }, + }, + 'C0_CHANNEL_CONFIGURATION_TX': { + 'offset': 0x1000, 'type': 'rw', + 'fields': { + 'c0_ctl_tx_fcs_ins_enable': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_ctl_tx_ignore_fcs': {'start': 1, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_ctl_tx_send_lfi': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_send_rfi': {'start': 3, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_send_idle': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_custom_preamble_enable': {'start': 5, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_ipg_value': {'start': 8, 'length': 4, 'default': 0xC, 'type': 'rw'}, + 'c0_ctl_tx_corrupt_fcs_on_err': {'start': 16, 'length': 2, 'default': 0, 'type': 'rw'}, + } + }, + 'C0_CHANNEL_CONFIGURATION_RX': { + 'offset': 0x1004, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_is_clause_49': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_delete_fcs': {'start': 1, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_ignore_fcs': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_process_lfi': {'start': 3, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_check_sfd': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_check_preamble': {'start': 5, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_ignore_inrange': {'start': 6, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_max_packet_len': {'start': 16, 'length': 14, 'default': 0x2580, 'type': 'rw'}, + } + }, + 'C0_CHANNEL_CONTROL_REG_RX': { + 'offset': 0x1030, 'type': 'rw', + 'fields': { + 'c0_soft_rx_mac_channel_flush': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_CHANNEL_CONTROL_REG_TX': { + 'offset': 0x1038, 'type': 'rw', + 'fields': { + 'c0_soft_tx_mac_channel_flush': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_TX_MODE_REG': { + 'offset': 0x1040, 'type': 'rw', + 'fields': { + 'c0_ctl_tx_data_rate': {'start': 0, 'length': 2, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_use_custom_vl_length_minus1': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_use_custom_vl_marker_ids': {'start': 3, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_tick_reg_mode_sel': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_flexif_select': {'start': 5, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_tx_flexif_am_mode': {'start': 7, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_flexif_pcs_wide_mode': {'start': 8, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_pma_lane_mux': {'start': 9, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_tx_alt_serdes_clk_mux_disable': {'start': 11, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_fec_mode': {'start': 16, 'length': 5, 'default': 4, 'type': 'rw'}, + 'c0_ctl_tx_fec_transcode_bypass': {'start': 21, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_fec_four_lane_pmd': {'start': 22, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_RX_MODE_REG': { + 'offset': 0x1044, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_data_rate': {'start': 0, 'length': 2, 'default': 0, 'type': 'rw'}, + 'c0_ctl_pcs_rx_ts_en': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_test_pattern': {'start': 8, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_use_custom_vl_length_minus1': {'start': 9, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_use_custom_vl_marker_ids': {'start': 10, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_tick_reg_mode_sel': {'start': 11, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_pma_lane_mux': {'start': 12, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_fec_mode': {'start': 16, 'length': 4, 'default': 4, 'type': 'rw'}, + 'c0_ctl_rx_fec_bypass_indication': {'start': 21, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_bypass_correction': {'start': 22, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_transcode_clause49': {'start': 23, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_alignment_bypass': {'start': 24, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_transcode_bypass': {'start': 25, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_degrade_enable': {'start': 26, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_ext_align_buff_enable': {'start': 27, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_RX_FEC_SLICE_CONFIGURATION1': { + 'offset': 0x1048, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_degrade_interval': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'C0_RX_FEC_SLICE_CONFIGURATION2': { + 'offset': 0x104C, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_degrade_act_thresh': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'C0_RX_FEC_SLICE_CONFIGURATION3': { + 'offset': 0x1050, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_degrade_deact_thresh': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'C0_CONFIGURATION_RX': { + 'offset': 0x10A0, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_flexif_select': {'start': 0, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_flexif_pcs_wide_mode': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_PORT_CONTROL_REG_RX': { + 'offset': 0x10F0, 'type': 'rw', + 'fields': { + 'c0_soft_rx_flexif_reset': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_soft_rx_serdes_reset': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_PORT_TICK_REG_RX': { + 'offset': 0x10F4, 'type': 'rw', + 'fields': { + 'c0_rx_port_soft_pm_tick': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'} + } + }, + 'C0_PORT_CONTROL_REG_TX': { + 'offset': 0x10F8, 'type': 'rw', + 'fields': { + 'c0_soft_tx_flexif_reset': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_soft_tx_serdes_reset': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_PORT_TICK_REG_TX': { + 'offset': 0x10FC, 'type': 'rw', + 'fields': { + 'c0_tx_port_soft_pm_tick': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'} + } + }, + 'C0_STAT_CHAN_TX_MAC_STATUS_REG': { + 'offset': 0x1100, 'type': 'ro', + 'fields': { + 'c0_stat_tx_local_fault': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_tsmac_ovf': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_tsmac_unf': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_packet_small': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_sic_overflow': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_CHAN_TX_MAC_RT_STATUS_REG': { + 'offset': 0x1104, 'type': 'ro', + 'fields': { + 'c0_stat_tx_local_fault': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_tsmac_ovf': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_tsmac_unf': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_packet_small': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_sic_overflow': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_CHAN_TX_STATISTICS_READY': { + 'offset': 0x1108, 'type': 'ro', + 'fields': { + 'c0_stat_tx_channel_mac_statistics_ready': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'} + } + }, + 'C0_STAT_CHAN_RX_MAC_STATUS_REG': { + 'offset': 0x1140, 'type': 'ro', + 'fields': { + 'c0_stat_rx_remote_fault': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_local_fault': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_internal_local_fault': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_received_local_fault': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_preamble': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_sfd': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_got_signal_os': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_invalid_start': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_code': {'start': 8, 'length': 1, 'default': 0, 'type': 'ro'}, + } + }, + 'C0_STAT_CHAN_RX_MAC_RT_STATUS_REG': { + 'offset': 0x1144, 'type': 'ro', + 'fields': { + 'c0_stat_rx_remote_fault': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_local_fault': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_internal_local_fault': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_received_local_fault': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_preamble': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_sfd': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_got_signal_os': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_invalid_start': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_code': {'start': 8, 'length': 1, 'default': 0, 'type': 'ro'}, + } + }, + 'C0_STAT_CHAN_RX_STATISTICS_READY': { + 'offset': 0x1148, 'type': 'ro', + 'fields': { + 'c0_stat_tx_channel_mac_statistics_ready': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'} + } + }, + + 'C0_STAT_PORT_TX_MAC_STATUS_REG': { + 'offset': 0x1180, 'type': 'ro', + 'fields': { + 'c0_stat_tx_axis_unf': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_axis_err': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_MAC_RT_STATUS_REG': { + 'offset': 0x1184, 'type': 'ro', + 'fields': { + 'c0_stat_tx_axis_unf': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_axis_err': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_RX_MAC_STATUS_REG': { + 'offset': 0x11C0, 'type': 'ro', + 'fields': { + 'c0_stat_rx_axis_fifo_overflow': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_axis_err': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_phy2ts_buf_err': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_macif_fifo_ovf': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_RX_MAC_RT_STATUS_REG': { + 'offset': 0x11C4, 'type': 'ro', + 'fields': { + 'c0_stat_rx_axis_fifo_overflow': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_axis_err': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_phy2ts_buf_err': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_macif_fifo_ovf': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_PHY_STATUS_REG': { + 'offset': 0x1800, 'type': 'ro', + 'fields': { + 'c0_stat_tx_pcs_bad_code': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_flex_fifo_err': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_flex_coa': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_PHY_RT_STATUS_REG': { + 'offset': 0x1804, 'type': 'ro', + 'fields': { + 'c0_stat_tx_pcs_bad_code': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_flex_fifo_err': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_flex_coa': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_STATISTICS_READY': { + 'offset': 0x1808, 'type': 'ro' + }, + 'C0_STAT_PORT_TX_FEC_STATUS_REG': { + 'offset': 0x180C, 'type': 'ro', + 'fields': { + 'c0_stat_tx_fec_pcs_lane_align': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_tx_fec_pcs_block_lock': {'start': 1, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_tx_fec_pcs_am_lock': {'start': 2, 'length': 1, 'default': 1, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_FEC_RT_STATUS_REG': { + 'offset': 0x1810, 'type': 'ro', + 'fields': { + 'c0_stat_tx_fec_pcs_lane_align': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_tx_fec_pcs_block_lock': {'start': 1, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_tx_fec_pcs_am_lock': {'start': 2, 'length': 1, 'default': 1, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_RX_PHY_STATUS_REG': { + 'offset': 0x1C00, 'type': 'ro', + 'fields': { + 'c0_stat_rx_status': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_block_lock': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_aligned': {'start': 2, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_misaligned': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_aligned_err': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_hi_ber': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_framing_err': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_pcs_bad_code': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_synced': {'start': 8, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_synced_err': {'start': 9, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bip_err': {'start': 10, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_flex_fifo_err': {'start': 11, 'length': 1, 'default': 0, 'type': 'ro'}, + } + }, + 'C0_STAT_PORT_RX_PHY_RT_STATUS_REG': { + 'offset': 0x1C04, 'type': 'ro', + 'fields': { + 'c0_stat_rx_status': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_block_lock': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_aligned': {'start': 2, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_misaligned': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_aligned_err': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_hi_ber': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_framing_err': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_pcs_bad_code': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_synced': {'start': 8, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_synced_err': {'start': 9, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bip_err': {'start': 10, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_flex_fifo_err': {'start': 11, 'length': 1, 'default': 0, 'type': 'ro'}, + } + }, + 'C0_STAT_PORT_RX_STATISTICS_READY': { + 'offset': 0x1C08, 'type': 'ro' + }, + 'C0_STAT_PORT_RX_BLOCK_LOCK_REG': { + 'offset': 0x1C0C, 'type': 'ro' + }, + 'C0_STAT_PORT_RX_LANE_SYNC_REG': { + 'offset': 0x1C10, 'type': 'ro' + }, + 'C0_STAT_PORT_RX_LANE_SYNC_ERR_REG': { + 'offset': 0x1C14, 'type': 'ro' + }, + + 'C0_STAT_PORT_RX_FEC_STATUS_REG': { + 'offset': 0x1C34, 'type': 'ro', + 'fields': { + 'c0_stat_rx_fec_aligned': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_fec_hi_ser': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_lane_lock': {'start': 2, 'length': 4, 'default': 15, 'type': 'ro'}, + 'c0_stat_rx_fec_degraded_ser': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_rm_degraded': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_RX_FEC_RT_STATUS_REG': { + 'offset': 0x1C38, 'type': 'ro', + 'fields': { + 'c0_stat_rx_fec_aligned': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_fec_hi_ser': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_lane_lock': {'start': 2, 'length': 4, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_degraded_ser': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_rm_degraded': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, +} + + +tx_stats_base_reg = { + 'TOTAL_BYTES_LSB': {'offset': 0x00, 'type': 'ro'}, + 'TOTAL_BYTES_MSB': {'offset': 0x04, 'type': 'ro'}, + 'TOTAL_GOOD_BYTES_LSB': {'offset': 0x08, 'type': 'ro'}, + 'TOTAL_GOOD_BYTES_MSB': {'offset': 0x0C, 'type': 'ro'}, + 'TOTAL_PACKETS_LSB': {'offset': 0x10, 'type': 'ro'}, + 'TOTAL_PACKETS_MSB': {'offset': 0x14, 'type': 'ro'}, + 'TOTAL_GOOD_PACKETS_LSB': {'offset': 0x18, 'type': 'ro'}, + 'TOTAL_GOOD_PACKETS_MSB': {'offset': 0x1C, 'type': 'ro'}, + 'FRAME_ERROR_LSB': {'offset': 0x20, 'type': 'ro'}, + 'FRAME_ERROR_MSB': {'offset': 0x24, 'type': 'ro'}, + 'BAD_FCS_LSB': {'offset': 0x28, 'type': 'ro'}, + 'BAD_FCS_MSB': {'offset': 0x2C, 'type': 'ro'}, + 'PACKET_64_BYTES_LSB': {'offset': 0x30, 'type': 'ro'}, + 'PACKET_64_BYTES_MSB': {'offset': 0x34, 'type': 'ro'}, + 'PACKET_65_127_BYTES_LSB': {'offset': 0x38, 'type': 'ro'}, + 'PACKET_65_127_BYTES_MSB': {'offset': 0x3C, 'type': 'ro'}, + 'PACKET_128_255_BYTES_LSB': {'offset': 0x40, 'type': 'ro'}, + 'PACKET_128_255_BYTES_MSB': {'offset': 0x44, 'type': 'ro'}, + 'PACKET_256_511_BYTES_LSB': {'offset': 0x48, 'type': 'ro'}, + 'PACKET_256_511_BYTES_MSB': {'offset': 0x4C, 'type': 'ro'}, + 'PACKET_512_1023_BYTES_LSB': {'offset': 0x50, 'type': 'ro'}, + 'PACKET_512_1023_BYTES_MSB': {'offset': 0x54, 'type': 'ro'}, + 'PACKET_1024_1518_BYTES_LSB': {'offset': 0x58, 'type': 'ro'}, + 'PACKET_1024_1518_BYTES_MSB': {'offset': 0x5C, 'type': 'ro'}, + 'PACKET_1519_1522_BYTES_LSB': {'offset': 0x60, 'type': 'ro'}, + 'PACKET_1519_1522_BYTES_MSB': {'offset': 0x64, 'type': 'ro'}, + 'PACKET_1523_1548_BYTES_LSB': {'offset': 0x68, 'type': 'ro'}, + 'PACKET_1523_1548_BYTES_MSB': {'offset': 0x6C, 'type': 'ro'}, + 'PACKET_1549_2047_BYTES_LSB': {'offset': 0x70, 'type': 'ro'}, + 'PACKET_1549_2047_BYTES_MSB': {'offset': 0x74, 'type': 'ro'}, + 'PACKET_2048_4095_BYTES_LSB': {'offset': 0x78, 'type': 'ro'}, + 'PACKET_2048_4095_BYTES_MSB': {'offset': 0x7C, 'type': 'ro'}, + 'PACKET_4096_8191_BYTES_LSB': {'offset': 0x80, 'type': 'ro'}, + 'PACKET_4096_8191_BYTES_MSB': {'offset': 0x84, 'type': 'ro'}, + 'PACKET_8192_9215_BYTES_LSB': {'offset': 0x88, 'type': 'ro'}, + 'PACKET_8192_9215_BYTES_MSB': {'offset': 0x8C, 'type': 'ro'}, + 'PACKET_LARGE': {'offset': 0x90, 'type': 'ro'}, + 'UNICAST_LSB': {'offset': 0x98, 'type': 'ro'}, + 'UNICAST_MSB': {'offset': 0x9C, 'type': 'ro'}, + 'MULTICAST_LSB': {'offset': 0xA0, 'type': 'ro'}, + 'MULTICAST_MSB': {'offset': 0xA4, 'type': 'ro'}, + 'BROADCAST_LSB': {'offset': 0xA8, 'type': 'ro'}, + 'BROADCAST_MSB': {'offset': 0xAC, 'type': 'ro'}, + 'VLAN_LSB': {'offset': 0xB0, 'type': 'ro'}, + 'VLAN_MSB': {'offset': 0xB4, 'type': 'ro'}, + 'PAUSE_LSB': {'offset': 0xB8, 'type': 'ro'}, + 'PAUSE_MSB': {'offset': 0xBC, 'type': 'ro'}, + 'USER_PAUSE_LSB': {'offset': 0xC0, 'type': 'ro'}, + 'USER_PAUSE_MSB': {'offset': 0xC4, 'type': 'ro'}, + 'MAC_CYCLE_COUNT_LSB': {'offset': 0xC8, 'type': 'ro'}, + 'MAC_CYCLE_COUNT_MSB': {'offset': 0xCC, 'type': 'ro'}, + 'ECC_CORRECTABLE_COUNT': {'offset': 0xD0, 'type': 'ro'}, + 'ECC_UNCORRECTABLE_COUNT': {'offset': 0xD8, 'type': 'ro'}, +} + + +rx_stats_base_reg = { + 'TOTAL_BYTES_LSB': {'offset': 0x00, 'type': 'ro'}, + 'TOTAL_BYTES_MSB': {'offset': 0x04, 'type': 'ro'}, + 'TOTAL_GOOD_BYTES_LSB': {'offset': 0x08, 'type': 'ro'}, + 'TOTAL_GOOD_BYTES_MSB': {'offset': 0x0C, 'type': 'ro'}, + 'TOTAL_PACKETS_LSB': {'offset': 0x10, 'type': 'ro'}, + 'TOTAL_PACKETS_MSB': {'offset': 0x14, 'type': 'ro'}, + 'TOTAL_GOOD_PACKETS_LSB': {'offset': 0x18, 'type': 'ro'}, + 'TOTAL_GOOD_PACKETS_MSB': {'offset': 0x1C, 'type': 'ro'}, + 'PACKET_SMALL_LSB': {'offset': 0x20, 'type': 'ro'}, + 'PACKET_SMALL_MSB': {'offset': 0x24, 'type': 'ro'}, + 'BAD_CODE_COUNT_LSB': {'offset': 0x28, 'type': 'ro'}, + 'BAD_CODE_COUNT_MSB': {'offset': 0x2C, 'type': 'ro'}, + 'BAD_FCS_LSB': {'offset': 0x30, 'type': 'ro'}, + 'BAD_FCS_MSB': {'offset': 0x34, 'type': 'ro'}, + 'PACKET_BAD_FCS_LSB': {'offset': 0x38, 'type': 'ro'}, + 'PACKET_BAD_FCS_MSB': {'offset': 0x3C, 'type': 'ro'}, + 'STOMPED_FCS_LSB': {'offset': 0x40, 'type': 'ro'}, + 'STOMPED_FCS_MSB': {'offset': 0x44, 'type': 'ro'}, + 'TRUNCATED_LSB': {'offset': 0x48, 'type': 'ro'}, + 'TRUNCATED_MSB': {'offset': 0x4C, 'type': 'ro'}, + 'PACKET_64_BYTES_LSB': {'offset': 0x50, 'type': 'ro'}, + 'PACKET_64_BYTES_MSB': {'offset': 0x54, 'type': 'ro'}, + 'PACKET_65_127_BYTES_LSB': {'offset': 0x58, 'type': 'ro'}, + 'PACKET_65_127_BYTES_MSB': {'offset': 0x5C, 'type': 'ro'}, + 'PACKET_128_255_BYTES_LSB': {'offset': 0x60, 'type': 'ro'}, + 'PACKET_128_255_BYTES_MSB': {'offset': 0x64, 'type': 'ro'}, + 'PACKET_256_511_BYTES_LSB': {'offset': 0x68, 'type': 'ro'}, + 'PACKET_256_511_BYTES_MSB': {'offset': 0x6C, 'type': 'ro'}, + 'PACKET_512_1023_BYTES_LSB': {'offset': 0x70, 'type': 'ro'}, + 'PACKET_512_1023_BYTES_MSB': {'offset': 0x74, 'type': 'ro'}, + 'PACKET_1024_1518_BYTES_LSB': {'offset': 0x78, 'type': 'ro'}, + 'PACKET_1024_1518_BYTES_MSB': {'offset': 0x7C, 'type': 'ro'}, + 'PACKET_1519_1522_BYTES_LSB': {'offset': 0x80, 'type': 'ro'}, + 'PACKET_1519_1522_BYTES_MSB': {'offset': 0x84, 'type': 'ro'}, + 'PACKET_1523_1548_BYTES_LSB': {'offset': 0x88, 'type': 'ro'}, + 'PACKET_1523_1548_BYTES_MSB': {'offset': 0x8C, 'type': 'ro'}, + 'PACKET_1549_2047_BYTES_LSB': {'offset': 0x90, 'type': 'ro'}, + 'PACKET_1549_2047_BYTES_MSB': {'offset': 0x94, 'type': 'ro'}, + 'PACKET_2048_4095_BYTES_LSB': {'offset': 0x98, 'type': 'ro'}, + 'PACKET_2048_4095_BYTES_MSB': {'offset': 0x9C, 'type': 'ro'}, + 'PACKET_4096_8191_BYTES_LSB': {'offset': 0xA0, 'type': 'ro'}, + 'PACKET_4096_8191_BYTES_MSB': {'offset': 0xA4, 'type': 'ro'}, + 'PACKET_8192_9215_BYTES_LSB': {'offset': 0xA8, 'type': 'ro'}, + 'PACKET_8192_9215_BYTES_MSB': {'offset': 0xAC, 'type': 'ro'}, + 'TOOLONG': {'offset': 0xB0, 'type': 'ro'}, + 'PACKET_LARGE': {'offset': 0xB8, 'type': 'ro'}, + 'JABBER': {'offset': 0xC0, 'type': 'ro'}, + 'OVERSIZE': {'offset': 0xC8, 'type': 'ro'}, + 'UNICAST_LSB': {'offset': 0xD0, 'type': 'ro'}, + 'UNICAST_MSB': {'offset': 0xD4, 'type': 'ro'}, + 'MULTICAST_LSB': {'offset': 0xD8, 'type': 'ro'}, + 'MULTICAST_MSB': {'offset': 0xDC, 'type': 'ro'}, + 'BROADCAST_LSB': {'offset': 0xE0, 'type': 'ro'}, + 'BROADCAST_MSB': {'offset': 0xE4, 'type': 'ro'}, + 'VLAN_LSB': {'offset': 0xE8, 'type': 'ro'}, + 'VLAN_MSB': {'offset': 0xEC, 'type': 'ro'}, + 'PAUSE_LSB': {'offset': 0xF0, 'type': 'ro'}, + 'PAUSE_MSB': {'offset': 0xF4, 'type': 'ro'}, + 'USER_PAUSE_LSB': {'offset': 0xF8, 'type': 'ro'}, + 'USER_PAUSE_MSB': {'offset': 0xFC, 'type': 'ro'}, + 'INRANGEERR_LSB': {'offset': 0x100, 'type': 'ro'}, + 'INRANGEERR_MSB': {'offset': 0x104, 'type': 'ro'}, + 'MAC_CYCLE_COUNT_LSB': {'offset': 0x108, 'type': 'ro'}, + 'MAC_CYCLE_COUNT_MSB': {'offset': 0x10C, 'type': 'ro'}, +} diff --git a/linker/resources/dcmac/driver/default_ip.py b/linker/resources/dcmac/driver/default_ip.py new file mode 100644 index 00000000..db50ad69 --- /dev/null +++ b/linker/resources/dcmac/driver/default_ip.py @@ -0,0 +1,76 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +from generic_mmio import GenericMMIO +from utils import rshift + + +def decode_control_register(value: int) -> dict: + cregister = {} + cregister['ap_start': bool(rshift(value))] + cregister['ap_done': bool(rshift(value, 1))] + cregister['ap_idle': bool(rshift(value, 2))] + cregister['ap_ready': bool(rshift(value, 3))] + cregister['ap_continue': bool(rshift(value, 4))] + cregister['auto_restart': bool(rshift(value, 7))] + return cregister + +cregs = { + "controlreg": {'offset': 0x0, 'type': 'rw', + 'fields': {'ap_start': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ap_done': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'ap_idle': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'ap_ready': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'ap_continue': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'auto_restart': {'start': 7, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + "globalintreg": {'offset': 0x4, 'type': 'rw'}, + "intenable": {'offset': 0x8, 'type': 'rw'}, + "intstatus": {'offset': 0x10, 'type': 'rw'}, +} + + +class DefaultIP(GenericMMIO): + """Generic IP Driver""" + _controlreg = 0x00 + _globalintreg = 0x04 + _intenable = 0x08 + _intstatus = 0x10 + + def __init__(self, device: str = 'e2', base_offset: int = 0x0, + debug: bool = False, regs: dict = None): + super().__init__(device, base_offset, debug) + self.registers = cregs if regs is None else regs + + def start(self, value: int = 1): + """Start IP once""" + self.write(self._controlreg, value) + + def autostart(self): + """Autostart IP""" + self.start(0x81) + + def controlreg(self) -> dict: + value = self.read(self._controlreg) + cregisters = decode_control_register(value) + print(cregisters) + return cregisters + + def global_interrupt(self): + value = self.read(self._globalintreg) + gintenable = {'global_interrupt_enable': bool(rshift(value))} + print(gintenable) + return gintenable + + def interrupt_enable(self): + value = self.read(self._intenable) + intenable = {'interrupt_enable': bool(rshift(value))} + print(intenable) + return intenable + + def interrupt_status(self): + value = self.read(self._intstatus) + intstatus = {'interrupt_status': bool(rshift(value))} + print(intstatus) + return intstatus diff --git a/linker/resources/dcmac/driver/generic_mmio.py b/linker/resources/dcmac/driver/generic_mmio.py new file mode 100644 index 00000000..1d5fcee8 --- /dev/null +++ b/linker/resources/dcmac/driver/generic_mmio.py @@ -0,0 +1,70 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +from pcie_bar import PCIeMapBar +from utils import int_types, hex_or_int, add_common_args + + +class GenericMMIO: + def __init__(self, device: str = 'e2', base_offset: int = 0x0, + debug: bool = False): + self._base_offset = base_offset + self._pciemmio = PCIeMapBar(device, debug=debug) + self._pciemmio.open() + if debug: + print(f"Base address: {hex(self._base_offset)}") + + def write(self, reg_offset: int = 0, value: int = 0): + if not isinstance(value, int_types): + raise ValueError(f"'{value=}' is not a {int_types} type") + self._pciemmio.write(self._base_offset + reg_offset, value) + + def read(self, reg_offset: int = 0): + return self._pciemmio.read(self._base_offset + reg_offset) + + def read_long(self, offset) -> int: + """Read 8 bytes from BAR 'offset'""" + val_low = self.read(offset) + val_high = self.read(offset + 4) + return int((val_high << 32) + val_low) + + def __del__(self): + self._pciemmio.close() + + @property + def base_address(self): + return self._base_offset + + +def main(args): + obj = GenericMMIO(args.dev, args.baseoffset) + + if args.write: + obj.write(args.offset, args.value) + + if args.read: + val = obj.read(args.offset) + print(f'Offset: 0x{obj._base_offset + args.offset:X}, value=0x{val:X}') + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + + parser.add_argument('-b', '--baseoffset', type=hex_or_int, + help='Base Offset', required=True) + + parser.add_argument('-o', '--offset', type=hex_or_int, + help='Offset', required=True) + + parser.add_argument('-r', '--read', action='store_true', + help='Read') + parser.add_argument('-w', '--write', action='store_true', + help='Write') + parser.add_argument('-v', '--value', type=hex_or_int, + help='Value to be written', default=0) + + parser = add_common_args(parser, False) + args = parser.parse_args() + main(args) diff --git a/linker/resources/dcmac/driver/gpio_monitor.py b/linker/resources/dcmac/driver/gpio_monitor.py new file mode 100644 index 00000000..e1c57565 --- /dev/null +++ b/linker/resources/dcmac/driver/gpio_monitor.py @@ -0,0 +1,66 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +from axigpio_mmio import AxiGpioMMIO +from utils import add_common_args, get_ip_offset + + +shift_map = { + 'gt0_tx_reset_done': {'shift': 0, 'bits': 4}, + 'gt1_tx_reset_done': {'shift': 4, 'bits': 4}, + 'gt0_rx_reset_done': {'shift': 8, 'bits': 4}, + 'gt1_rx_reset_done': {'shift': 12, 'bits': 4}, + 'gtpowergood': {'shift': 16, 'bits': 1}, + 'dual_dcmac': {'shift': 18, 'bits': 1}, +} + + +def _get_shift_and_mask(key: str) -> tuple[int, int]: + """Return the shift and mask give the key""" + map = shift_map[key] + return map['shift'], (1 << map['bits']) - 1 + + +class AxiGPIOMonitor(AxiGpioMMIO): + + def __init__(self, device: str = 'e2', base_offset: int = 0x0, + gpio_index: int = 0): + self._gpio_index = gpio_index + super().__init__(device, base_offset) + + def _get(self, key: str, gpio: int = 0): + shift, mask = _get_shift_and_mask(key) + return (self.read(gpio) >> shift) & mask + + def _create_property(key: str, gpio: int = 0): + """Create property getter and setter for given key.""" + return property( + lambda self: self._get(key, gpio) + ) + + gt0_tx_reset_done = _create_property('gt0_tx_reset_done') + gt1_tx_reset_done = _create_property('gt1_tx_reset_done') + gt0_rx_reset_done = _create_property('gt0_rx_reset_done') + gt1_rx_reset_done = _create_property('gt1_rx_reset_done') + gtpowergood = _create_property('gtpowergood') + dual_dcmac = _create_property('dual_dcmac') + + +def main(args): + offset = get_ip_offset(0x204_0200, args.dcmac) + obj = AxiGPIOMonitor(args.dev, offset, gpio_index=0) + + print(f'{obj.gt0_tx_reset_done=}') + print(f'{obj.gt0_rx_reset_done=}') + print(f'{obj.gt1_tx_reset_done=}') + print(f'{obj.gt1_rx_reset_done=}') + print(f'{obj.gtpowergood=}') + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser = add_common_args(parser) + + main(parser.parse_args()) diff --git a/linker/resources/dcmac/driver/netlayer_regs.py b/linker/resources/dcmac/driver/netlayer_regs.py new file mode 100644 index 00000000..9a94003a --- /dev/null +++ b/linker/resources/dcmac/driver/netlayer_regs.py @@ -0,0 +1,58 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +nl_regs = { + "mac_address": {'offset': 0x0010, 'size': 8, 'type': 'rw'}, + "ip_address": {'offset': 0x0018, 'size': 4, 'type': 'rw'}, + "gateway": {'offset': 0x001C, 'size': 4, 'type': 'rw'}, + "ip_mask": {'offset': 0x0020, 'size': 4, 'type': 'rw'}, + "eth_in_cycles": {'offset': 0x0400, 'size': 8, 'type': 'ro'}, + "eth_in_bytes": {'offset': 0x0408, 'size': 8, 'type': 'ro'}, + "eth_in_packets": {'offset': 0x0410, 'size': 8, 'type': 'ro'}, + "pkth_in_cycles": {'offset': 0x0418, 'size': 8, 'type': 'ro'}, + "pkth_in_bytes": {'offset': 0x0420, 'size': 8, 'type': 'ro'}, + "pkth_in_packets": {'offset': 0x0428, 'size': 8, 'type': 'ro'}, + "arp_in_cycles": {'offset': 0x0430, 'size': 8, 'type': 'ro'}, + "arp_in_bytes": {'offset': 0x0438, 'size': 8, 'type': 'ro'}, + "arp_in_packets": {'offset': 0x0440, 'size': 8, 'type': 'ro'}, + "arp_out_cycles": {'offset': 0x0448, 'size': 8, 'type': 'ro'}, + "arp_out_bytes": {'offset': 0x0450, 'size': 8, 'type': 'ro'}, + "arp_out_packets": {'offset': 0x0458, 'size': 8, 'type': 'ro'}, + "icmp_in_cycles": {'offset': 0x0460, 'size': 8, 'type': 'ro'}, + "icmp_in_bytes": {'offset': 0x0468, 'size': 8, 'type': 'ro'}, + "icmp_in_packets": {'offset': 0x0470, 'size': 8, 'type': 'ro'}, + "icmp_out_cycles": {'offset': 0x0478, 'size': 8, 'type': 'ro'}, + "icmp_out_bytes": {'offset': 0x0480, 'size': 8, 'type': 'ro'}, + "icmp_out_packets": {'offset': 0x0488, 'size': 8, 'type': 'ro'}, + "ethhi_out_cycles": {'offset': 0x0490, 'size': 8, 'type': 'ro'}, + "ethhi_out_bytes": {'offset': 0x0498, 'size': 8, 'type': 'ro'}, + "ethhi_out_packets": {'offset': 0x04A0, 'size': 8, 'type': 'ro'}, + "eth_out_cycles": {'offset': 0x04A8, 'size': 8, 'type': 'ro'}, + "eth_out_bytes": {'offset': 0x04B0, 'size': 8, 'type': 'ro'}, + "eth_out_packets": {'offset': 0x04B8, 'size': 8, 'type': 'ro'}, + "udp_in_cycles": {'offset': 0x04C0, 'size': 8, 'type': 'ro'}, + "udp_in_bytes": {'offset': 0x04C8, 'size': 8, 'type': 'ro'}, + "udp_in_packets": {'offset': 0x04D0, 'size': 8, 'type': 'ro'}, + "app_out_cycles": {'offset': 0x04D8, 'size': 8, 'type': 'ro'}, + "app_out_bytes": {'offset': 0x04E0, 'size': 8, 'type': 'ro'}, + "app_out_packets": {'offset': 0x04E8, 'size': 8, 'type': 'ro'}, + "udp_out_cycles": {'offset': 0x04F0, 'size': 8, 'type': 'ro'}, + "udp_out_bytes": {'offset': 0x04F8, 'size': 8, 'type': 'ro'}, + "udp_out_packets": {'offset': 0x0500, 'size': 8, 'type': 'ro'}, + "app_in_cycles": {'offset': 0x0508, 'size': 8, 'type': 'ro'}, + "app_in_bytes": {'offset': 0x0510, 'size': 8, 'type': 'ro'}, + "app_in_packets": {'offset': 0x0518, 'size': 8, 'type': 'ro'}, + "debug_reset_counters": {'offset': 0x05F0, 'size': 4, 'type': 'rw'}, + "frequency": {'offset': 0x05F4, 'size': 4, 'type': 'ro'}, + "probes_ports": {'offset': 0x05F8, 'size': 4, 'type': 'ro'}, + "probes_mode": {'offset': 0x05FC, 'size': 4, 'type': 'ro'}, + "udp_number_sockets": {'offset': 0x0810, 'size': 4, 'type': 'ro'}, + "udp_theirIP_offset": {'offset': 0x0820, 'size': 4, 'type': 'rw'}, + "udp_theirPort_offset": {'offset': 0x08A0, 'size': 4, 'type': 'rw'}, + "udp_myPort_offset": {'offset': 0x0920, 'size': 4, 'type': 'rw'}, + "udp_valid_offset": {'offset': 0x09A0, 'size': 4, 'type': 'rw'}, + "arp_discovery": {'offset': 0x1010, 'size': 4, 'type': 'rw'}, + "arp_valid_offset": {'offset': 0x1100, 'size': 4, 'type': 'rw'}, + "arp_ip_addr_offset": {'offset': 0x1400, 'size': 4, 'type': 'rw'}, + "arp_mac_addr_offset": {'offset': 0x1800, 'size': 4, 'type': 'rw'}, +} \ No newline at end of file diff --git a/linker/resources/dcmac/driver/network_end2end_test.py b/linker/resources/dcmac/driver/network_end2end_test.py new file mode 100644 index 00000000..f00ae0dd --- /dev/null +++ b/linker/resources/dcmac/driver/network_end2end_test.py @@ -0,0 +1,128 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +import time +from dcmac_init import dcmac_logic_init +from dcmac_mmio import DCMAC +from utils import add_common_args, get_ip_offset +from udp_utils import NetworkLayer +from trafficgen import TrafficGenerator + +"""This file aims at doing a test of the Ethernet or UDP layer between two interfaces in +board, interface 0 and 2. It will initialize the DCMAC and then setup the +interfaces IP, MAC addresses as well as the UDP socket table. +""" + +DCMAC_BASEADDR = 0x200_0000 +TRAFFICGEN_BASEADDR = 0x400_2000 +NL_BASEADDR = 0x400_0000 + + +class ArgsClass: + dcmac = 0 + init = False + print = 1 + dev = None + verbose = 1 + loopback = None + keep_alive = 0 + align_rx = 1 + traffic_test = 0 + + +def main(args): + """Initialize DCMAC in each interface""" + init_args = ArgsClass() + init_args.dev = args.dev + """Init DCMAC 0""" + dcmac_logic_init(init_args) + + """Init DCMAC 0""" + init_args.dcmac = 1 + dcmac_logic_init(init_args) + + # reset TX first then RX + if args.udp: + """Basic network layer config""" + nl0 = NetworkLayer(args.dev, get_ip_offset(NL_BASEADDR, 0)) + nl1 = NetworkLayer(args.dev, get_ip_offset(NL_BASEADDR, 2)) + + print(f'nl0._base_offset=0x{nl0._base_offset:0X}') + print(f'nl1._base_offset=0x{nl1._base_offset:0X}') + + ip_if0 = '192.168.10.5' + ip_if1 = '192.168.10.6' + nl0.set_ip_address(ip_if0) + nl1.set_ip_address(ip_if1) + nl0.set_mac_address('b8:3f:d2:24:51:c0') + nl1.set_mac_address('b8:3f:d2:24:51:c1') + + print(f'NL0: {nl0.get_network_info()}') + print(f'NL1: {nl1.get_network_info()}') + + """Reset debug stats""" + nl0.reset_debug_stats() + nl1.reset_debug_stats() + + """Start ARP Discovery""" + nl0.arp_discovery() + time.sleep(1) + nl1.arp_discovery() + time.sleep(1) + + print(f'NL0 ARP Table: {nl0.get_arp_table(12, verbose=1)}') + print(f'NL1 ARP Table: {nl1.get_arp_table(12, verbose=1)}') + + """Populate socket table""" + port_tx = 50446 + port_rx = 60133 + nl0.sockets[0] = (ip_if1, port_tx, port_rx, True) + nl0.populate_socket_table(debug=True) + nl1.sockets[0] = (ip_if0, port_rx, port_tx, True) + nl1.populate_socket_table(debug=True) + + """Now we can generate some traffic""" + + tgen0 = TrafficGenerator(args.dev, 0x00) + tgen1 = TrafficGenerator(args.dev, 0x80) + + tgen0.flits = 22 + tgen0.dest = 0 + tgen0.start() + time.sleep(1) + + tgen1.flits = 22 + tgen1.dest = 0 + tgen1.start() + time.sleep(1) + + if args.udp: + """Get Statistics""" + print('\n') + nl0.get_debug_stats(True) + print('\n') + nl1.get_debug_stats(True) + print('\n') + + dcmac0 = DCMAC(args.dev, get_ip_offset(DCMAC_BASEADDR, 0)) + dcmac1 = DCMAC(args.dev, get_ip_offset(DCMAC_BASEADDR, 1)) + + print(f'{dcmac0.tx_stats(verbose=1)=}') + print(f'{dcmac0.rx_stats(verbose=1)=}') + + print(f'{dcmac1.tx_stats(verbose=1)=}') + print(f'{dcmac1.rx_stats(verbose=1)=}') + + if args.udp: + print(f'{nl0.get_freq=}') + print(f'{nl1.get_freq=}') + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-u', '--udp', action='store_true', + help='Use UDP logic') + parser = add_common_args(parser, verbose=True) + args = parser.parse_args() + main(args) diff --git a/linker/resources/dcmac/driver/pcie_bar.py b/linker/resources/dcmac/driver/pcie_bar.py new file mode 100644 index 00000000..1537e874 --- /dev/null +++ b/linker/resources/dcmac/driver/pcie_bar.py @@ -0,0 +1,62 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import mmap +from warnings import warn +import numpy as np +BAR_SIZE = 256 * 1024 * 1024 # 256 MB + + +def _get_bar_path(dev, debug=True): + """Generate BAR path based on the PCIe Bus ID""" + dev_path = f"/sys/bus/pci/devices/0000:{dev}:00.0/resource0" + if debug: + print(f"Using BDF: {dev_path}") + return dev_path + + +class PCIeMapBar: + """Wrapper class to allows MMIO read and write operations from PCIe BAR""" + def __init__(self, device: str = 'e2', barsize: int = BAR_SIZE, + debug: bool = True): + self._bar = None + self._barpath = _get_bar_path(device, debug) + self._barsize = barsize + + def open(self): + """Open BAR""" + with open(self._barpath, "r+b") as f: + self._bar = mmap.mmap(f.fileno(), self._barsize, mmap.MAP_SHARED, + mmap.PROT_READ | mmap.PROT_WRITE) + self.mem = np.frombuffer(self._bar, np.uint32, (self._barsize+3) >> 2) + + def close(self): + """Close BAR""" + if self._bar is not None: + del self.mem + self._bar.close() + self._bar = None + + def read(self, byte_offset: int) -> int: + """Read 4 bytes from BAR 'byte_offset'""" + if byte_offset & 0x3: + warn(f"Byte offset {byte_offset} is not aligned to 32-bit words." + + "Aligning to previous 32-bit boundary") + if self._bar is None: + raise RuntimeError('BAR is not opened') + + return int(self.mem[byte_offset >> 2]) + + def write(self, byte_offset: int, value: int): + """Write 4 bytes to BAR 'byte_offset'""" + if byte_offset & 0x3: + warn(f"Byte offset {byte_offset} is not aligned to 32-bit words." + + "Aligning to previous 32-bit boundary") + if self._bar is None: + raise RuntimeError('BAR is not opened') + value_32 = value & 0xFFFFFFFF + if value_32 != value: + warn("Trying to write a value larger than 32 bits to the PCIe " + + "device, truncating to 32 bits") + + self.mem[byte_offset >> 2] = value_32 diff --git a/linker/resources/dcmac/driver/requirements.txt b/linker/resources/dcmac/driver/requirements.txt new file mode 100644 index 00000000..8b48365f --- /dev/null +++ b/linker/resources/dcmac/driver/requirements.txt @@ -0,0 +1,3 @@ +numpy +tabulate +IPython diff --git a/linker/resources/dcmac/driver/trafficgen.py b/linker/resources/dcmac/driver/trafficgen.py new file mode 100644 index 00000000..018f8171 --- /dev/null +++ b/linker/resources/dcmac/driver/trafficgen.py @@ -0,0 +1,63 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +from default_ip import DefaultIP +from utils import add_common_args, get_ip_offset + + +class TrafficGenerator(DefaultIP): + """Specialization to support TrafficGenerator IP""" + + _flits_offset = 0x10 + _dest_offset = 0x18 + + @property + def dest(self): + value = self.read(self._dest_offset) + return value + + @dest.setter + def dest(self, value: int): + if not isinstance(value, int): + raise ValueError(f"{value=} must be an integer") + elif value < 0: + raise ValueError(f"{value=} must be a positive integer") + + self.write(self._dest_offset, value) + + @property + def flits(self): + value = self.read(self._flits_offset) + return value + + @flits.setter + def flits(self, value: int): + if not isinstance(value, int): + raise ValueError(f"{value=} must be an integer") + elif value < 1: + raise ValueError(f"{value=} must be bigger than 0") + + self.write(self._flits_offset, value) + + +def main(args): + intf = 0 + offset = get_ip_offset(0x400_0000, args.dcmac*2 +intf) + tgen = TrafficGenerator(args.dev, offset) + + tgen.flits = args.flits + tgen.dest = 0 + tgen.start() + del tgen + + +if __name__ == '__main__': + parser = argparse.ArgumentParser() + parser.add_argument('-f', '--flits', type=int, default=10, + help='Number of 64-Byte flits', required=False) + + parser = add_common_args(parser) + args = parser.parse_args() + + main(args) diff --git a/linker/resources/dcmac/driver/udp_utils.py b/linker/resources/dcmac/driver/udp_utils.py new file mode 100644 index 00000000..8fc5ed97 --- /dev/null +++ b/linker/resources/dcmac/driver/udp_utils.py @@ -0,0 +1,637 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import ipaddress +import numpy as np +from enum import Enum +from tabulate import tabulate +from IPython.display import JSON +from default_ip import DefaultIP +from netlayer_regs import nl_regs + + +def _byte_ordering_endianess(num, length=4): + """ + Convert from little endian to big endian and vice versa + + Parameters + ---------- + num: int + input number + + length: + number of bytes of the input number + + Returns + ------- + An integer with the endianness changed with respect to input number + + """ + if not isinstance(num, int): + raise ValueError("num must be an integer") + + if not isinstance(length, int): + raise ValueError("length must be an positive integer") + elif length < 0: + raise ValueError("length cannot be negative") + + aux = 0 + for i in range(length): + byte_index = num >> ((length - 1 - i) * 8) & 0xFF + aux += byte_index << (i * 8) + return aux + + +class NetworkLayer(DefaultIP): + """This class wraps the common function of the Network Layer IP + + """ + + bindto = ["xilinx.com:kernel:networklayer:1.0"] + + _socketType = np.dtype( + [ + ("theirIP", str, 16), + ("theirPort", np.uint16), + ("myPort", np.uint16), + ("valid", bool), + ] + ) + + def __init__(self, device: str = 'e2', base_offset: int = 0x0, + debug: bool = False): + super().__init__(device, base_offset, debug) + self.registers = nl_regs + self.sockets = np.zeros(16, dtype=self._socketType) + self.freq = None + + def populate_socket_table(self, debug: bool = False): + """ + Populate a socket table + + Optionals + --------- + debug: bool + If enables read the current status of the UDP Table + + Returns + ------- + If debug is enable read the current status of the UDP Table + + """ + + theirIP_offset = self.registers['udp_theirIP_offset']['offset'] + theirPort_offset = self.registers['udp_theirPort_offset']['offset'] + udp_myPort_offset = self.registers['udp_myPort_offset']['offset'] + udp_valid_offset = self.registers['udp_valid_offset']['offset'] + numSocketsHW = int(self.read(self.registers['udp_number_sockets']['offset'])) + + if numSocketsHW < len(self.sockets): + raise Exception(f"Socket list length ({len(self.sockets)}) is " + "bigger than the number of sockets in hardware " + f"({numSocketsHW})") + + # Iterate over the socket object + for i in range(numSocketsHW): + ti_offset = theirIP_offset + i * 8 + tp_offset = theirPort_offset + i * 8 + mp_offset = udp_myPort_offset + i * 8 + v_offset = udp_valid_offset + i * 8 + + theirIP = 0 + if self.sockets[i]["theirIP"]: + theirIP = int(ipaddress.IPv4Address(self.sockets[i] + ["theirIP"])) + + self.write(ti_offset, theirIP) + self.write(tp_offset, int(self.sockets[i]["theirPort"])) + self.write(mp_offset, int(self.sockets[i]["myPort"])) + self.write(v_offset, int(self.sockets[i]["valid"])) + + if debug: + return self.get_socket_table() + + def get_socket_table(self) -> dict: + """ Reads the socket table + + Returns + ------- + Returns socket table + """ + + theirIP_offset = self.registers['udp_theirIP_offset']['offset'] + theirPort_offset = self.registers['udp_theirPort_offset']['offset'] + udp_myPort_offset = self.registers['udp_myPort_offset']['offset'] + udp_valid_offset = self.registers['udp_valid_offset']['offset'] + numSocketsHW = int(self.read(self.registers['udp_number_sockets']['offset'])) + + socket_dict = dict() + socket_dict['Number of Sockets'] = numSocketsHW + socket_dict['socket'] = dict() + # Iterate over all the UDP table + for i in range(numSocketsHW): + ti_offset = theirIP_offset + i * 8 + tp_offset = theirPort_offset + i * 8 + mp_offset = udp_myPort_offset + i * 8 + v_offset = udp_valid_offset + i * 8 + isvalid = self.read(v_offset) + if isvalid: + ti = self.read(ti_offset) + tp = self.read(tp_offset) + mp = self.read(mp_offset) + socket_dict['socket'][i] = dict() + socket_dict['socket'][i]['theirIP'] = \ + str(ipaddress.IPv4Address(ti)) + socket_dict['socket'][i]['theirPort'] = tp + socket_dict['socket'][i]['myPort'] = mp + + print(f'{socket_dict=}') + return JSON(socket_dict, rootname='socket_table') + + def invalidate_socket_table(self): + """ Clear the Socket table """ + + udp_valid_offset = self.registers['udp_valid_offset']['offset'] + numSocketsHW = int(self.registers['udp_number_sockets']) + for i in range(numSocketsHW): + self.write(int(udp_valid_offset + i * 8), 0) + + def get_arp_table(self, num_entries: int=256, verbose: int=0) -> dict: + """Read the ARP table from the FPGA return a dict + + Parameters + ---------- + Optionals + --------- + num_entries: int + number of entries in the table to be consider when printing + + Returns + ------- + Prints the content of valid entries in the ARP in a friendly way + """ + + if not isinstance(num_entries, int): + raise ValueError("Number of entries must be integer.") + elif num_entries < 0: + raise ValueError("Number of entries cannot be negative.") + elif num_entries > 256: + raise ValueError("Number of entries cannot be bigger than 256.") + + mac_addr_offset = self.registers['arp_mac_addr_offset']['offset'] + ip_addr_offset = self.registers['arp_ip_addr_offset']['offset'] + valid_addr_offset = self.registers['arp_valid_offset']['offset'] + + arptable = dict() + + valid_entry = None + for i in range(num_entries): + if (i % 4) == 0: + valid_entry = self.read(valid_addr_offset + (i // 4) * 4) + + isvalid = (valid_entry >> ((i % 4) * 8)) & 0x1 + if isvalid or verbose > 0: + mac_lsb = self.read(mac_addr_offset + (i * 2 * 4)) + mac_msb = self.read(mac_addr_offset + ((i * 2 + 1) * 4)) + ip_addr = self.read(ip_addr_offset + (i * 4)) + mac_addr = (2 ** 32) * mac_msb + mac_lsb + mac_hex = "{:012x}".format( + _byte_ordering_endianess(mac_addr, 6)) + mac_str = ":".join( + mac_hex[i: i + 2] for i in range(0, len(mac_hex), 2) + ) + ip_addr_print = _byte_ordering_endianess(ip_addr) + arptable[i] = { + "MAC address": mac_str, + "IP address": str(ipaddress.IPv4Address(ip_addr_print)) + } + + headers = ["Index", "MAC Address", "IP Address"] + table_data = [] + for key, value in arptable.items(): + mac_address = value["MAC address"] + ip_address = value["IP address"] + table_data.append([key, mac_address, ip_address]) + + print(tabulate(table_data, headers=headers, tablefmt="pretty")) + #return JSON(arptable, rootname='ARP Table') + + def write_arp_entry(self, mac: str, ip: str): + """ + Add an entry to the ARP table + + Parameters + ---------- + mac: str + MAC address in the format XX:XX:XX:XX:XX:XX + ip: str + IP address in the format XXX.XXX.XXX.XXX + + Note, VNx requires all IPs in the ARP table to be in the same + /24 subnet (mask 255.255.255.0) as the IP assigned to the FPGA port. + + There are 256 entries in the ARP table, one for each possible IP + in the subnet, the least significant 8 bits of the IP are used to + index into the ARP table. + """ + + if not isinstance(mac, str): + raise ValueError("MAC address must be a string.") + elif not isinstance(ip, str): + raise ValueError("IP address must be a string.") + + mac_int = int("0x{}".format(mac.replace(":", "")), 16) + big_mac_int = _byte_ordering_endianess(mac_int, 6) + mac_msb = (big_mac_int >> 32) & 0xFFFFFFFF + mac_lsb = big_mac_int & 0xFFFFFFFF + + ip_int = int(ipaddress.IPv4Address(ip)) + big_ip_int = _byte_ordering_endianess(ip_int, 4) + + mac_addr_offset = self.registers['arp_mac_addr_offset']['offset'] + ip_addr_offset = self.registers['arp_ip_addr_offset']['offset'] + valid_addr_offset = self.registers['arp_valid_offset']['offset'] + + i = ip_int % 256 + self.write(ip_addr_offset + (i * 4), big_ip_int) + self.write(mac_addr_offset + (i * 2 * 4), mac_lsb) + self.write(mac_addr_offset + ((i * 2 + 1) * 4), mac_msb) + + # Valid + old_valid_entry = self.read(valid_addr_offset + (i // 4) * 4) + this_valid = 1 << ((i % 4) * 8) + self.write(valid_addr_offset + (i // 4) * 4, + old_valid_entry | this_valid) + + def invalidate_arp_table(self): + """ + Clear the ARP table + """ + valid_addr_offset = self.registers['arp_valid_offset']['offset'] + + for i in range(0, 256//4, 4): + self.write(valid_addr_offset + i, 0) + + def arp_discovery(self): + """ + Launch ARP discovery + """ + + # The ARP discovery is trigger with the rising edge + self.write(self.registers['arp_discovery']['offset'], 0) + self.write(self.registers['arp_discovery']['offset'], 1) + self.write(self.registers['arp_discovery']['offset'], 0) + + def get_network_info(self) -> dict: + """Returns a dictionary with the current configuration + """ + mac_addr = int(self.read_long(self.registers['mac_address']['offset'])) + ip_addr = int(self.read(self.registers['ip_address']['offset'])) + ip_gw = int(self.read(self.registers['gateway']['offset'])) + ip_mask = int(self.read(self.registers['ip_mask']['offset'])) + + mac_hex = "{:012x}".format(mac_addr) + mac_str = ":".join(mac_hex[i: i + 2] + for i in range(0, len(mac_hex), 2)) + + config = { + "HWaddr": mac_str, + "inet addr": str(ipaddress.IPv4Address(ip_addr)), + "gateway addr": str(ipaddress.IPv4Address(ip_gw)), + "Mask": str(ipaddress.IPv4Address(ip_mask)), + } + print(f'{config=}') + return JSON(config, rootname='Network Information') + + def set_ip_address(self, ipaddrsrt, gwaddr="None", debug=False): + """ + Update IP address as well as least significant octet of the + MAC address with the least significant octet of the IP address + + Parameters + ---------- + ipaddrsrt : string + New IP address + + gwaddr : string + New IP gateway address, if not defined a default gateway is used + debug: bool + if enable it will return the current configuration + + Returns + ------- + Current interface configuration only if debug == True + + """ + + if not isinstance(ipaddrsrt, str): + raise ValueError("ipaddrsrt must be an string type") + + if not isinstance(gwaddr, str): + raise ValueError("gwaddr must be an string type") + + if not isinstance(debug, bool): + raise ValueError("debug must be a bool type") + + ipaddr = int(ipaddress.IPv4Address(ipaddrsrt)) + self.write(self.registers['ip_address']['offset'], ipaddr) + if gwaddr == "None": + self.write(self.registers['gateway']['offset'], (ipaddr & 0xFFFFFF00) + 1) + else: + self.write(self.registers['gateway']['offset'], int(ipaddress.IPv4Address(gwaddr))) + + + #currentMAC = int(self.read(self.registers['mac_address']['offset'])) + #newMAC = (currentMAC & 0xFFFFFFFFF00) + (ipaddr & 0xFF) + #self.write(self.registers['mac_address']['offset'], newMAC) + + if debug: + return self.get_network_info() + + def set_mac_address(self, mac_addr: str): + """ Update the MAC address of the interface + + Parameters + ---------- + mac_addr : str + MAC address in the format XX:XX:XX:XX:XX:XX + """ + if not isinstance(mac_addr, str): + raise ValueError("MAC address must be a string.") + + mac_int = int("0x{}".format(mac_addr.replace(":", "")), 16) + mac_low = mac_int & 0xFFFFFFFF + mac_high = (mac_int >> 32) & 0xFFFFFFFF + self.write(self.registers['mac_address']['offset'], mac_low) + self.write(self.registers['mac_address']['offset'] + 4, mac_high) + + def reset_debug_stats(self) -> None: + """Reset debug probes + """ + + self.write(self.registers['debug_reset_counters']['offset'], 1) + + def get_debug_stats(self, debug: bool=True) -> dict: + """Return a dictionary with the value of the Network Layer probes""" + + rmap = self.registers + probes = dict() + probes["tx_path"] = dict() + probes["rx_path"] = dict() + + probes["rx_path"] = { + "ethernet": { + "packets": int(self.read(rmap['eth_in_packets']['offset'])), + "bytes": int(self.read(rmap['eth_in_bytes']['offset'])), + "cycles": int(self.read(rmap['eth_in_cycles']['offset'])) + }, + "packet_handler": { + "packets": int(self.read(rmap['pkth_in_packets']['offset'])), + "bytes": int(self.read(rmap['pkth_in_bytes']['offset'])), + "cycles": int(self.read(rmap['pkth_in_cycles']['offset'])) + }, + "arp": { + "packets": int(self.read(rmap['arp_in_packets']['offset'])), + "bytes": int(self.read(rmap['arp_in_bytes']['offset'])), + "cycles": int(self.read(rmap['arp_in_cycles']['offset'])) + }, + "icmp": { + "packets": int(self.read(rmap['icmp_in_packets']['offset'])), + "bytes": int(self.read(rmap['icmp_in_bytes']['offset'])), + "cycles": int(self.read(rmap['icmp_in_cycles']['offset'])) + }, + "udp": { + "packets": int(self.read(rmap['udp_in_packets']['offset'])), + "bytes": int(self.read(rmap['udp_in_bytes']['offset'])), + "cycles": int(self.read(rmap['udp_in_cycles']['offset'])) + }, + "app": { + "packets": int(self.read(rmap['app_in_packets']['offset'])), + "bytes": int(self.read(rmap['app_in_bytes']['offset'])), + "cycles": int(self.read(rmap['app_in_cycles']['offset'])) + } + } + + probes['tx_path'] = { + "arp": { + "packets": int(self.read(rmap['arp_out_packets']['offset'])), + "bytes": int(self.read(rmap['arp_out_bytes']['offset'])), + "cycles": int(self.read(rmap['arp_out_cycles']['offset'])) + }, + "icmp": { + "packets": int(self.read(rmap['icmp_out_packets']['offset'])), + "bytes": int(self.read(rmap['icmp_out_bytes']['offset'])), + "cycles": int(self.read(rmap['icmp_out_cycles']['offset'])) + }, + "ethernet_header_inserter": { + "packets": int(self.read(rmap['ethhi_out_packets']['offset'])), + "bytes": int(self.read(rmap['ethhi_out_bytes']['offset'])), + "cycles": int(self.read(rmap['ethhi_out_cycles']['offset'])) + }, + "ethernet": { + "packets": int(self.read(rmap['eth_out_packets']['offset'])), + "bytes": int(self.read(rmap['eth_out_bytes']['offset'])), + "cycles": int(self.read(rmap['eth_out_cycles']['offset'])) + }, + "udp": { + "packets": int(self.read(rmap['udp_out_packets']['offset'])), + "bytes": int(self.read(rmap['udp_out_bytes']['offset'])), + "cycles": int(self.read(rmap['udp_out_cycles']['offset'])) + }, + "app": { + "packets": int(self.read(rmap['app_out_packets']['offset'])), + "bytes": int(self.read(rmap['app_out_bytes']['offset'])), + "cycles": int(self.read(rmap['app_out_cycles']['offset'])) + } + } + + for path, stats in probes.items(): + table_data = [] + for protocol, v in stats.items(): + tot_bytes = v['bytes'] + tot_cycles = v['cycles'] + thr_bs = 0 + if tot_cycles != 0: + tot_time = (1 / (390.625 * 10 ** 6)) * tot_cycles + thr_bs = (tot_bytes * 8) / tot_time + table_data.append([protocol, v['packets'], tot_bytes, tot_cycles, f'{thr_bs/10**6:.2f}']) + + print(f"Debug {path} probes") + print(tabulate(table_data, headers=[f'Probe {path}', 'Packets', 'Bytes', 'Cycles', 'BW (Mb/s)'], tablefmt='pretty')) + + return JSON(probes, rootname='debug_probes') + + @property + def get_freq(self): + return int(self.read(self.registers['frequency']['offset'])) + + +class TgMode(Enum): + """Supported Traffic generator Modes""" + PRODUCER = 0 + LATENCY = 1 + LOOPBACK = 2 + CONSUMER = 3 + + +class TrafficGenerator(DefaultIP): + """ This class wraps the common function of the Traffic Generator IP + """ + + bindto = ["xilinx.com:kernel:traffic_generator:1.0"] + + def __init__(self, description): + super().__init__(description=description) + self.start = self._call = self._start_sw = self.start_sw = self.call = self._start_ert + self.freq = None + + def _start_ert(self, mode: TgMode, dest: int=0, packets: int=None, + beats: int=None, tbwp: int=None): + """Starts the Traffic generator + + Parameters + ---------- + mode: TgMode + Operation mode + dest: int + Index in the socket table + + Optional + -------- + packets: int + Number of packets + num_beats: int + Number of transactions per piece of payload + tbwp: + Clock ticks between two consecutive payload packets + """ + if mode == TgMode.PRODUCER or mode == TgMode.LATENCY: + if packets is None: + raise RuntimeError("packets must be specified when mode is {}" + .format(mode)) + elif beats is None: + raise RuntimeError("beats must be specified when mode is {}" + .format(mode)) + elif tbwp is None: + raise RuntimeError("tbwp must be specified when mode is {}" + .format(mode)) + + self.register_map.number_packets = packets + self.register_map.number_beats = beats + self.register_map.time_between_packets = tbwp + + self.register_map.mode = int(mode.value) + self.register_map.dest_id = dest + self.register_map.CTRL.AP_START = 1 + + def reset_fsm(self): + """Reset internal FSM""" + self.register_map.reset_fsm = 1 + + def compute_app_throughput(self, direction: str="rx") -> float: + """ + Read the application monitoring registers and compute + throughput, it also returns other useful information + + Parameters + ---------- + direction: string + 'rx' or 'tx' + + Returns + ------- + Total number of packets seen by the monitoring probe, + throughput and total time + """ + + if direction not in ["rx", "tx"]: + raise ValueError( + "Only 'rx' and 'tx' strings are supported \ + on direction argument" + ) + + if direction == "rx": + tot_bytes = int(self.register_map.in_traffic_bytes) + tot_cycles = int(self.register_map.in_traffic_cycles) + tot_pkts = int(self.register_map.in_traffic_packets) + else: + tot_bytes = int(self.register_map.out_traffic_bytes) + tot_cycles = int(self.register_map.out_traffic_cycles) + tot_pkts = int(self.register_map.out_traffic_packets) + + tot_time = (1 / (self.freq * 10 ** 6)) * tot_cycles + thr_bs = (tot_bytes * 8) / tot_time + + return tot_pkts, thr_bs / (10 ** 9), tot_time + + def reset_stats(self): + """ + Reset embedded probes + """ + self.register_map.debug_reset = 1 + + +class CounterIP(DefaultIP): + """ This class wraps the common function of counter IP + + """ + + bindto = ["xilinx.com:hls:krnl_counters:1.0"] + + def __init__(self, description): + super().__init__(description=description) + self._fullpath = description['fullpath'] + self.start = self.start_sw = self.start_none = \ + self.start_ert = self.call + + def _setup_packet_prototype(self): + pass + + def call(self, *args, **kwargs): + raise RuntimeError("{} is a free running kernel and cannot be " + "starter or called".format(self._fullpath)) + + @property + def counters(self): + """ Return counters + + """ + + counters = { + 'packets': int(self.register_map.packets), + 'beats': int(self.register_map.beats), + 'bytes': int(self.register_map.bytes), + } + + return counters + + def reset_counters(self): + """ Reset internal counters + + """ + + self.register_map.reset = 0 + self.register_map.reset = 1 + self.register_map.reset = 0 + + +class CollectorIP(DefaultIP): + """ This class wraps the common function the collector Kernel + + """ + + bindto = ["xilinx.com:hls:collector:1.0"] + + def __init__(self, description): + super().__init__(description=description) + + @property + def received_packets(self): + # When a register is written by the kernel for non free running kernels + # the default offset refers to the value that the kernel reads + # the actual register where the kernel writes is not exposed in the + # signature, so we need to compute the offset and use mmio to read it + + rx_pkts_offset = self.register_map.received_packets.address + \ + self.register_map.received_packets.width//8 + 4 + return self.read(rx_pkts_offset) \ No newline at end of file diff --git a/linker/resources/dcmac/driver/utils.py b/linker/resources/dcmac/driver/utils.py new file mode 100644 index 00000000..15fe50d7 --- /dev/null +++ b/linker/resources/dcmac/driver/utils.py @@ -0,0 +1,47 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +import numpy as np +import os + +int_types = (int, np.int8, np.int16, np.int32, np.uint8, np.uint16, np.uint32) + + +def hex_or_int(value): + try: + if value.startswith(('0x', '0X')): + return int(value, 16) + return int(value) + except ValueError: + raise argparse.ArgumentTypeError(f"Invalid value: {value}. Must be an " + "integer or hexadecimal.") + + +def rshift(value: int, shift: int = 0, bitwidth: int = 1): + """Right shift value and mask with 'bitwidth'""" + value = value >> shift + mask = (2**bitwidth)-1 + return int(value & mask) + + +def get_ip_offset(baseoffset: int, mac_id: int): + """Get IP offset based on 'baseoffset' and 'mac_id'""" + + return baseoffset + (0x100_0000 * mac_id) + + +def add_common_args(parser, enable_mac: bool = True, verbose: bool = False): + """Add common arguments to the parser""" + default_dev = os.environ['V80_DEV'] if 'V80_DEV' in os.environ else 'e2' + parser.add_argument('-d', '--dev', help=f"PCIe device Bus ID, e.g., '{default_dev}'", + default=default_dev) + if enable_mac: + default_dcmac_id = os.environ['V80_DCMAC_ID'] if 'V80_DCMAC_ID' in os.environ else '0' + parser.add_argument('-m', '--dcmac', help="DCMAC ID either 0 or 1", + default=default_dcmac_id, choices=[0, 1], type=int) + if verbose: + parser.add_argument('-v', '--verbose', type=int, default=0, + choices=[0, 1], help='Verbosity mode') + + return parser diff --git a/linker/resources/dcmac/hdl/axis_seg_to_unseg_converter.v b/linker/resources/dcmac/hdl/axis_seg_to_unseg_converter.v new file mode 100644 index 00000000..0a4c1585 --- /dev/null +++ b/linker/resources/dcmac/hdl/axis_seg_to_unseg_converter.v @@ -0,0 +1,5438 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright © 2015-2025 Advanced Micro Devices, Inc. All rights reserved. + +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the “Software”), +// to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +// IN THE SOFTWARE. +////////////////////////////////////////////////////////////////////////////// +// +// DO NOT MODIFY THIS FILE. +////////////////////////////////////////////////////////////////////////////// +// +// Company : Advanced Micro Devices +// +// Create Date : 13/02/2024 10:36:53 AM +// Design Name : AXIS segmented <=> unsegmented interface converter +// Module Name : axis_seg_and_unseg_converter +// Project Name : +// Target Devices : +// Tool Versions : +// Description : Segmented AXI stream <-> unsegmented AXI stream converter for DCMAC +// : Supported mode - Coupled MAC+PHY mode (FixedE) +// : Supported data rates - 100 or 200 or 400Gbps +// : Data width of each segment of segmented axis interface is considered as 128bits +// : Unsegmented AXIS interface configuration as below, +// : 100G - 1x256b @ >=450MHz, higher clock is needed to accomodate packet rate (considering 65Byte packets) +// : 200G - 1x1024b @391MHz, data width is doubled to accomodate packet rate (considering 65Byte packets) +// : 400G - 2x1024b @391MHz, two ports are used to accomodate packet rate (considering 129Byte packets) +// +// Revision : 1.00 - Initial version +// : 1.01 - Critical path optimization and design improvements +// : 1.02 - Added error transfer between seg & unseg interfaces( seg err <-> unseg tuser ) +// +// Additional Notes : +// : 1. Backpressure is not supported by DCMAC at the segmented interface of RX side. Data must be consumed +// : when the rx_tvalid signal is available. User need to consider required buffering at the input/output +// : of the seg to unseg converter. Overflow of the input buffer in the seg to unseg converter will lead +// : to packet loss and/or data corruption. To avoid this, input packets will be dropped when the packet +// : buffer of the seg to unseg converter becomes full(tail drop performed). This feature can be disabled +// : when using with other traffic masters which support back pressure. +// +// : 2. At the TX side of the DCMAC, packets should not be sent with broken Valid signal (seg_val should +// : not go low in between a SoP and EoP. seg_val deassertion should aligned with an EoP and seg_val +// : assertion should aligned with SoP). Violation of this leads to packet loss and corruption at the +// : DCMAC. To overcome this limitation and also to improve segment packing efficiency, packets are processed as a +// : block(of packets) and sent to DCMAC when tx_tready signal of DCMAC segmented is available. +// : This makes the unsegmented to segmented converter bulky and uses deep FIFOs aligned with the +// : block size used. For optimal performance, preferred block size is 512 +// +// : 3. For 100G mode, the 2x128 segments are mapped to 1x256 bit AXI Stream interface. To accomodate the Packet +// : rate, considering the worst case packet size of 65Bytes, the converter is designed to run at a +// : higher clock than the DCMAC segmented interface clock(>=450MHz is preferred, least minimum is 425 MHz). +// +// : 4. For 200G mode, the 4x128 segments are mapped to 1x1024 bit AXI Stream interface. Direct mapping of 4x128 +// : segments to 1x512 bit AXIS would need atleast 562MHz for the converter to accomodate the packet rate +// : considering the worst case packet size of 65Bytes. Timing closure would be difficult for such high clocks +// : and most of the AXIS based IPs would not support such high clocks. To accomodate the packet rate, +// : 4x128 segments are mapped to 1x1024 bit AXI stream. The converter can run at the same DCMAC clock of the +// : segmented interface +// +// : 5. For 400G operation 8x128 segments are mapped to 2x1024 bit AXI Stream interfaces to accomodate the packet +// : rate considering the worst case packet size of 129Bytes. Direct mapping of 8x128 segments to 1x1024 bit +// : AXIS would need atleast 654MHz for the converter. To overcome the similar limitations mentioned +// : for the 200G case, 8x128 segments are mapped to 2x1024 bit AXI Streams and the converter is designed to run +// : at the same DCMAC clock of the segmented interface(391MHz).The first packet received from the DCMAC +// : segmented interface is sent to the first AXIS port and next packet to the second AXIS port and so on +// : in a Round Robin fashion. At the unsegmented to segmented side, packets are taken from the AXIS ports based +// : on the availabily of packets and follow round robin arbitration. +// +// : 6. Array based mechanism is implemented for packing and unpacking of segments in the converter. The design +// : consumes considerable logic for the 200G and 400G configuration and also have timing closure challenges. +// +// : 7. Critical path optimizations done and timing improved for all the configurations (with the DCMAC example design). +// : however 400G & 200G configuration may have timing closure challenges when integrating with large designs. +// +// : 8. Debug logic and statistic counters are included in the converter but it is recommened to disable them for +// : synthesis/implementation to avoid timing violations. They were added only for simulation/verification purpose. +// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// User configuration defines; please refer IP documentation for more details + +`define data_rate_200 // data rate of DCMAC port (update the suffix as per the requirement; 100,200 or 400) +`define en_seg_to_unseg_cnv // Enable/disable segmented to unsegmented axi stream converter +`define en_unseg_to_seg_cnv // Enable/disable unsegmented to segmented axi stream converter +`define max_packet_size 9216 // Maximum packet size expeted/to be supported +`define max_pkt_size_above_1k // Comment off if max packet size is less than 1024Bytes +`define en_flow_control // Enable/Disable flow control at the seg to unseg converter. + // Enable if backpressure is not supported by the traffic source. Incomimg packets are dropped when + // downstream ports backpressures and buffers become full. Disable if backpressure is supported by + // the traffic master + +// Enabling bleow defines is not recommended (shall be enabled for simulation) + +//`define statistics_en // Enable Input & output port statistic (packet & byte counters) +//`define debug_en // Enable error checks in the design + +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// Do not change the below derived defines except "independant_clk" + +// derived Converter defines + +`define segment_width 128 // data width of each segment of segmented axis interface +`ifdef data_rate_100 + `define num_segments 2 // number of segments of input segmented axis interface + `define num_axis_ports 1 // number of ports of output unsegmented axis interface + `define unseg_axis_w 256 // data width of output unsegmented axis interface + `define pktarray_depth 4 // depth of the segment array used to unpack/pack the segments + `define independant_clk // if defined segmented and the unsegmented interface runs at different clocks. + // for applications other than DCMAC and data rate less then 100Gbps user can run the interfaces + // at the desired clock frequency, either single clock or dual clock as per the need. Same applies for + // 200G and 400G configurations also +`elsif data_rate_200 + `define num_segments 4 + `define en_port1 + `define num_axis_ports 1 + `define unseg_axis_w 1024 + `define pktarray_depth 16 +`elsif data_rate_400 + `define num_segments 8 + `define num_axis_ports 2 + `define en_port1 + `define en_port2 + `define en_port3 + `define en_axis1 + `define pktarray_depth 16 + `define unseg_axis_w 1024 +`else + `define invalid_config // only 100, 200 or 400 data rate with the above configurations allowed + // For other rates user can choose the nearest configuration and drive the clocks as needed + // to meet the data rate +`endif + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +`ifndef invalid_config + +module axis_seg_and_unseg_converter + ( + `ifdef independant_clk + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_unseg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_pktout, ASSOCIATED_RESET aresetn_axis_unseg_in" *) + input aclk_axis_unseg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_unseg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_unseg_in, + `endif + + `ifdef en_seg_to_unseg_cnv + // AXIS Segment to Unsegment converter ports + // Clock & Resets + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_rx_seg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET aresetn_rx_seg_in" *) + input aclk_rx_seg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_rx_seg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_rx_seg_in, + + // Input Segmented stream interface + // Port0 (segments 0 & 1) is active for all valid configurations + // Segment 0 input + input Seg2UnSegEna0_in, + input [`segment_width-1:0] Seg2UnSegDat0_in, + input Seg2UnSegSop0_in, + input Seg2UnSegEop0_in, + input Seg2UnSegErr0_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty0_in, + // Segment 1 input + input Seg2UnSegEna1_in, + input [`segment_width-1:0] Seg2UnSegDat1_in, + input Seg2UnSegSop1_in, + input Seg2UnSegEop1_in, + input Seg2UnSegErr1_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty1_in, + `ifdef en_port1 + // Segment 2 input + input Seg2UnSegEna2_in, + input [`segment_width-1:0] Seg2UnSegDat2_in, + input Seg2UnSegSop2_in, + input Seg2UnSegEop2_in, + input Seg2UnSegErr2_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty2_in, + // Segment 3 input + input Seg2UnSegEna3_in, + input [`segment_width-1:0] Seg2UnSegDat3_in, + input Seg2UnSegSop3_in, + input Seg2UnSegEop3_in, + input Seg2UnSegErr3_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty3_in, + `endif + `ifdef en_port2 + // Segment 4 input + input Seg2UnSegEna4_in, + input [`segment_width-1:0] Seg2UnSegDat4_in, + input Seg2UnSegSop4_in, + input Seg2UnSegEop4_in, + input Seg2UnSegErr4_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty4_in, + // Segment 5 input + input Seg2UnSegEna5_in, + input [`segment_width-1:0] Seg2UnSegDat5_in, + input Seg2UnSegSop5_in, + input Seg2UnSegEop5_in, + input Seg2UnSegErr5_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty5_in, + `endif + `ifdef en_port3 + // Segment 6 input + input Seg2UnSegEna6_in, + input [`segment_width-1:0] Seg2UnSegDat6_in, + input Seg2UnSegSop6_in, + input Seg2UnSegEop6_in, + input Seg2UnSegErr6_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty6_in, + // Segment 7 input + input Seg2UnSegEna7_in, + input [`segment_width-1:0] Seg2UnSegDat7_in, + input Seg2UnSegSop7_in, + input Seg2UnSegEop7_in, + input Seg2UnSegErr7_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty7_in, + `endif + input wire Seg2UnSeg_tvalid_in, + + // Packet output interface - Unsegmented AXI Stream + // AXIS-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TDATA" *) + output [`unseg_axis_w-1:0] m_axis0_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TKEEP" *) + output [(`unseg_axis_w/8)-1:0] m_axis0_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TLAST" *) + output m_axis0_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TVALID" *) + output m_axis0_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TUSER" *) + output m_axis0_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TREADY" *) + input m_axis0_tready, + + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TDATA" *) + output [`unseg_axis_w-1:0] m_axis1_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TKEEP" *) + output [(`unseg_axis_w/8)-1:0] m_axis1_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TLAST" *) + output m_axis1_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TVALID" *) + output m_axis1_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TUSER" *) + output m_axis1_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TREADY" *) + input m_axis1_tready, + `endif + + `ifdef en_flow_control + output wire seg2unseg_buff_full, + `else + output wire seg2unseg_inbuff_overflow, + output wire seg2unseg_inbuff_afull, + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + output wire [63: 0] stat_rx_p1_pkt_out_cnt, + output wire [63: 0] stat_rx_p1_err_pkt_out_cnt, + output wire [63: 0] stat_rx_p1_pkt_out_byte_cnt, + output wire [63: 0] stat_rx_p0_pkt_out_cnt, + output wire [63: 0] stat_rx_p0_err_pkt_out_cnt, + output wire [63: 0] stat_rx_p0_pkt_out_byte_cnt, + `endif + output wire [63: 0] stat_rx_total_pkt_in_cnt, + output wire [63: 0] stat_rx_total_err_pkt_in_cnt, + output wire [63: 0] stat_rx_total_pkt_in_byte_cnt, + output wire [63: 0] stat_rx_total_pkt_out_cnt, + output wire [63: 0] stat_rx_total_err_pkt_out_cnt, + output wire [63: 0] stat_rx_total_pkt_out_byte_cnt, + `endif + `endif + + `ifdef debug_en + output wire seg2unseg_broken_packet_out_error, + output wire seg2unseg_rx_packet_error, + `endif + + `ifdef en_unseg_to_seg_cnv + // AXIS Segment to Unsegment converter ports + + // Clock & Resets + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_tx_seg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET aresetn_tx_seg_in" *) + input aclk_tx_seg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_tx_seg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_tx_seg_in, + + // Output Segmented stream interface + // Port0 (segments 0 & 1) is active for all valid configurations + // Segment 0 output + output Unseg2SegEna0_out, + output [`segment_width-1:0] Unseg2SegDat0_out, + output Unseg2SegSop0_out, + output Unseg2SegEop0_out, + output Unseg2SegErr0_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty0_out, + // Segment 1 output + output Unseg2SegEna1_out, + output [`segment_width-1:0] Unseg2SegDat1_out, + output Unseg2SegSop1_out, + output Unseg2SegEop1_out, + output Unseg2SegErr1_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty1_out, + `ifdef en_port1 + // Segment 2 output + output Unseg2SegEna2_out, + output [`segment_width-1:0] Unseg2SegDat2_out, + output Unseg2SegSop2_out, + output Unseg2SegEop2_out, + output Unseg2SegErr2_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty2_out, + // Segment 3 output + output Unseg2SegEna3_out, + output [`segment_width-1:0] Unseg2SegDat3_out, + output Unseg2SegSop3_out, + output Unseg2SegEop3_out, + output Unseg2SegErr3_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty3_out, + `endif + `ifdef en_port2 + // Segment 4 output + output Unseg2SegEna4_out, + output [`segment_width-1:0] Unseg2SegDat4_out, + output Unseg2SegSop4_out, + output Unseg2SegEop4_out, + output Unseg2SegErr4_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty4_out, + // Segment 5 output + output Unseg2SegEna5_out, + output [`segment_width-1:0] Unseg2SegDat5_out, + output Unseg2SegSop5_out, + output Unseg2SegEop5_out, + output Unseg2SegErr5_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty5_out, + `endif + `ifdef en_port3 + // Segment 6 output + output Unseg2SegEna6_out, + output [`segment_width-1:0] Unseg2SegDat6_out, + output Unseg2SegSop6_out, + output Unseg2SegEop6_out, + output Unseg2SegErr6_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty6_out, + // Segment 7 output + output Unseg2SegEna7_out, + output [`segment_width-1:0] Unseg2SegDat7_out, + output Unseg2SegSop7_out, + output Unseg2SegEop7_out, + output Unseg2SegErr7_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty7_out, + `endif + + // Packet input interface - Unsegmented AXI Stream + // AXI-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TDATA" *) + input [`unseg_axis_w-1:0] s_axis0_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TKEEP" *) + input [(`unseg_axis_w/8)-1:0] s_axis0_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TLAST" *) + input s_axis0_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TVALID" *) + input s_axis0_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TUSER" *) + input s_axis0_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TREADY" *) + output s_axis0_tready, + + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TDATA" *) + input [`unseg_axis_w-1:0] s_axis1_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TKEEP" *) + input [(`unseg_axis_w/8)-1:0] s_axis1_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TLAST" *) + input s_axis1_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TVALID" *) + input s_axis1_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TUSER" *) + input s_axis1_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TREADY" *) + output s_axis1_tready, + `endif + + `ifdef debug_en + output wire unseg2seg_missing_sop_error, + output wire unseg2seg_broken_pkt_out_error, + output wire unseg2seg_broken_pkt_in_error, + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + output wire [63: 0] stat_tx_p1_pkt_in_cnt, + output wire [63: 0] stat_tx_p1_err_pkt_in_cnt, + output wire [63: 0] stat_tx_p1_pkt_in_byte_cnt, + output wire [63: 0] stat_tx_p0_pkt_in_cnt, + output wire [63: 0] stat_tx_p0_err_pkt_in_cnt, + output wire [63: 0] stat_tx_p0_pkt_in_byte_cnt, + `endif + output wire [63: 0] stat_tx_total_pkt_in_cnt, + output wire [63: 0] stat_tx_total_err_pkt_in_cnt, + output wire [63: 0] stat_tx_total_pkt_in_byte_cnt, + output wire [63: 0] stat_tx_total_pkt_out_cnt, + output wire [63: 0] stat_tx_total_err_pkt_out_cnt, + output wire [63: 0] stat_tx_total_pkt_out_byte_cnt, + `endif + + input wire Unseg2Seg_tready_in, + output wire Unseg2Seg_tvalid_out + `endif + ); + +//----------------------------------------------------------------------------------------------------------------------- + +//------------------- AXIS Segment to Unsegment Converter + +`ifdef en_seg_to_unseg_cnv + +axis_seg_to_unseg_converter u_axis_seg_to_unseg_converter + ( + // Clock & Resets + .aclk_axis_seg_in(aclk_rx_seg_in), + .aresetn_axis_seg_in(aresetn_rx_seg_in), + `ifdef independant_clk + .aclk_axis_unseg_in(aclk_axis_unseg_in), + .aresetn_axis_unseg_in(aresetn_axis_unseg_in), + `endif + // Segmented interface + // Port0 (segments 0 & 1) is active for all valid configurations + // Segment 0 input + .Seg2UnSegEna0_in(Seg2UnSegEna0_in), + .Seg2UnSegDat0_in(Seg2UnSegDat0_in), + .Seg2UnSegSop0_in(Seg2UnSegSop0_in), + .Seg2UnSegEop0_in(Seg2UnSegEop0_in), + .Seg2UnSegErr0_in(Seg2UnSegErr0_in), + .Seg2UnSegMty0_in(Seg2UnSegMty0_in), + // Segment 1 input + .Seg2UnSegEna1_in(Seg2UnSegEna1_in), + .Seg2UnSegDat1_in(Seg2UnSegDat1_in), + .Seg2UnSegSop1_in(Seg2UnSegSop1_in), + .Seg2UnSegEop1_in(Seg2UnSegEop1_in), + .Seg2UnSegErr1_in(Seg2UnSegErr1_in), + .Seg2UnSegMty1_in(Seg2UnSegMty1_in), + `ifdef en_port1 + // Segment 2 input + .Seg2UnSegEna2_in(Seg2UnSegEna2_in), + .Seg2UnSegDat2_in(Seg2UnSegDat2_in), + .Seg2UnSegSop2_in(Seg2UnSegSop2_in), + .Seg2UnSegEop2_in(Seg2UnSegEop2_in), + .Seg2UnSegErr2_in(Seg2UnSegErr2_in), + .Seg2UnSegMty2_in(Seg2UnSegMty2_in), + // Segment 3 input + .Seg2UnSegEna3_in(Seg2UnSegEna3_in), + .Seg2UnSegDat3_in(Seg2UnSegDat3_in), + .Seg2UnSegSop3_in(Seg2UnSegSop3_in), + .Seg2UnSegEop3_in(Seg2UnSegEop3_in), + .Seg2UnSegErr3_in(Seg2UnSegErr3_in), + .Seg2UnSegMty3_in(Seg2UnSegMty3_in), + `endif + `ifdef en_port2 + // Segment 4 input + .Seg2UnSegEna4_in(Seg2UnSegEna4_in), + .Seg2UnSegDat4_in(Seg2UnSegDat4_in), + .Seg2UnSegSop4_in(Seg2UnSegSop4_in), + .Seg2UnSegEop4_in(Seg2UnSegEop4_in), + .Seg2UnSegErr4_in(Seg2UnSegErr4_in), + .Seg2UnSegMty4_in(Seg2UnSegMty4_in), + // Segment 5 input + .Seg2UnSegEna5_in(Seg2UnSegEna5_in), + .Seg2UnSegDat5_in(Seg2UnSegDat5_in), + .Seg2UnSegSop5_in(Seg2UnSegSop5_in), + .Seg2UnSegEop5_in(Seg2UnSegEop5_in), + .Seg2UnSegErr5_in(Seg2UnSegErr5_in), + .Seg2UnSegMty5_in(Seg2UnSegMty5_in), + `endif + `ifdef en_port3 + // Segment 6 input + .Seg2UnSegEna6_in(Seg2UnSegEna6_in), + .Seg2UnSegDat6_in(Seg2UnSegDat6_in), + .Seg2UnSegSop6_in(Seg2UnSegSop6_in), + .Seg2UnSegEop6_in(Seg2UnSegEop6_in), + .Seg2UnSegErr6_in(Seg2UnSegErr6_in), + .Seg2UnSegMty6_in(Seg2UnSegMty6_in), + // Segment 7 input + .Seg2UnSegEna7_in(Seg2UnSegEna7_in), + .Seg2UnSegDat7_in(Seg2UnSegDat7_in), + .Seg2UnSegSop7_in(Seg2UnSegSop7_in), + .Seg2UnSegEop7_in(Seg2UnSegEop7_in), + .Seg2UnSegErr7_in(Seg2UnSegErr7_in), + .Seg2UnSegMty7_in(Seg2UnSegMty7_in), + `endif + // Packet output interface - Unsegmented AXI Stream + // AXI-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + .m_axis0_tdata(m_axis0_tdata), + .m_axis0_tkeep(m_axis0_tkeep), + .m_axis0_tlast(m_axis0_tlast), + .m_axis0_tvalid(m_axis0_tvalid), + .m_axis0_tuser(m_axis0_tuser), + .m_axis0_tready(m_axis0_tready), + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + .m_axis1_tdata(m_axis1_tdata), + .m_axis1_tkeep(m_axis1_tkeep), + .m_axis1_tlast(m_axis1_tlast), + .m_axis1_tvalid(m_axis1_tvalid), + .m_axis1_tuser(m_axis1_tuser), + .m_axis1_tready(m_axis1_tready), + `endif + + `ifdef en_flow_control + .buff_full(seg2unseg_buff_full), + `else + .inbuff_overflow(seg2unseg_inbuff_overflow), + .inbuff_afull(seg2unseg_inbuff_afull), + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + .p1_pkt_out_cnt(stat_rx_p1_pkt_out_cnt), + .p1_err_pkt_out_cnt(stat_rx_p1_err_pkt_out_cnt), + .p1_pkt_out_byte_cnt(stat_rx_p1_pkt_out_byte_cnt), + .p0_pkt_out_cnt(stat_rx_p0_pkt_out_cnt), + .p0_err_pkt_out_cnt(stat_rx_p0_err_pkt_out_cnt), + .p0_pkt_out_byte_cnt(stat_rx_p0_pkt_out_byte_cnt), + `endif + .total_pkt_in_cnt(stat_rx_total_pkt_in_cnt), + .total_err_pkt_in_cnt(stat_rx_total_err_pkt_in_cnt), + .total_pkt_in_byte_cnt(stat_rx_total_pkt_in_byte_cnt), + .total_pkt_out_cnt(stat_rx_total_pkt_out_cnt), + .total_err_pkt_out_cnt(stat_rx_total_err_pkt_out_cnt), + .total_pkt_out_byte_cnt(stat_rx_total_pkt_out_byte_cnt), + `endif + + `ifdef debug_en + .error_broken_packet_out(seg2unseg_broken_packet_out_error), + .seg_rx_err_packet(seg2unseg_rx_packet_error), + `endif + + .rx_axis_tvalid_i(Seg2UnSeg_tvalid_in) + ); + `endif + +`ifdef en_unseg_to_seg_cnv + +axis_unseg_to_seg_converter u_axis_unseg_to_seg_converter + ( + // AXIS Segment to Unsegment converter ports + // Clock & Resets + .aclk_axis_seg_in(aclk_tx_seg_in), + .aresetn_axis_seg_in(aresetn_tx_seg_in), + `ifdef independant_clk + .aclk_axis_unseg_in(aclk_axis_unseg_in), + .aresetn_axis_unseg_in(aresetn_axis_unseg_in), + `endif + // Segmented interface + // port0 is active for all valid configurations + // Segment 0 input + .Unseg2SegEna0_out(Unseg2SegEna0_out), + .Unseg2SegDat0_out(Unseg2SegDat0_out), + .Unseg2SegSop0_out(Unseg2SegSop0_out), + .Unseg2SegEop0_out(Unseg2SegEop0_out), + .Unseg2SegErr0_out(Unseg2SegErr0_out), + .Unseg2SegMty0_out(Unseg2SegMty0_out), + // Segment 1 input + .Unseg2SegEna1_out(Unseg2SegEna1_out), + .Unseg2SegDat1_out(Unseg2SegDat1_out), + .Unseg2SegSop1_out(Unseg2SegSop1_out), + .Unseg2SegEop1_out(Unseg2SegEop1_out), + .Unseg2SegErr1_out(Unseg2SegErr1_out), + .Unseg2SegMty1_out(Unseg2SegMty1_out), + `ifdef en_port1 + // Segment 2 input + .Unseg2SegEna2_out(Unseg2SegEna2_out), + .Unseg2SegDat2_out(Unseg2SegDat2_out), + .Unseg2SegSop2_out(Unseg2SegSop2_out), + .Unseg2SegEop2_out(Unseg2SegEop2_out), + .Unseg2SegErr2_out(Unseg2SegErr2_out), + .Unseg2SegMty2_out(Unseg2SegMty2_out), + // Segment 3 input + .Unseg2SegEna3_out(Unseg2SegEna3_out), + .Unseg2SegDat3_out(Unseg2SegDat3_out), + .Unseg2SegSop3_out(Unseg2SegSop3_out), + .Unseg2SegEop3_out(Unseg2SegEop3_out), + .Unseg2SegErr3_out(Unseg2SegErr3_out), + .Unseg2SegMty3_out(Unseg2SegMty3_out), + `endif + `ifdef en_port2 + // Segment 4 input + .Unseg2SegEna4_out(Unseg2SegEna4_out), + .Unseg2SegDat4_out(Unseg2SegDat4_out), + .Unseg2SegSop4_out(Unseg2SegSop4_out), + .Unseg2SegEop4_out(Unseg2SegEop4_out), + .Unseg2SegErr4_out(Unseg2SegErr4_out), + .Unseg2SegMty4_out(Unseg2SegMty4_out), + // Segment 5 input + .Unseg2SegEna5_out(Unseg2SegEna5_out), + .Unseg2SegDat5_out(Unseg2SegDat5_out), + .Unseg2SegSop5_out(Unseg2SegSop5_out), + .Unseg2SegEop5_out(Unseg2SegEop5_out), + .Unseg2SegErr5_out(Unseg2SegErr5_out), + .Unseg2SegMty5_out(Unseg2SegMty5_out), + `endif + `ifdef en_port3 + // Segment 6 input + .Unseg2SegEna6_out(Unseg2SegEna6_out), + .Unseg2SegDat6_out(Unseg2SegDat6_out), + .Unseg2SegSop6_out(Unseg2SegSop6_out), + .Unseg2SegEop6_out(Unseg2SegEop6_out), + .Unseg2SegErr6_out(Unseg2SegErr6_out), + .Unseg2SegMty6_out(Unseg2SegMty6_out), + // Segment 7 input + .Unseg2SegEna7_out(Unseg2SegEna7_out), + .Unseg2SegDat7_out(Unseg2SegDat7_out), + .Unseg2SegSop7_out(Unseg2SegSop7_out), + .Unseg2SegEop7_out(Unseg2SegEop7_out), + .Unseg2SegErr7_out(Unseg2SegErr7_out), + .Unseg2SegMty7_out(Unseg2SegMty7_out), + `endif + + // Packet input interface - Unsegmented AXI Stream + // AXI-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + .s_axis0_tdata(s_axis0_tdata), + .s_axis0_tkeep(s_axis0_tkeep), + .s_axis0_tlast(s_axis0_tlast), + .s_axis0_tvalid(s_axis0_tvalid), + .s_axis0_tuser(s_axis0_tuser), + .s_axis0_tready(s_axis0_tready), + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + .s_axis1_tdata(s_axis1_tdata), + .s_axis1_tkeep(s_axis1_tkeep), + .s_axis1_tlast(s_axis1_tlast), + .s_axis1_tvalid(s_axis1_tvalid), + .s_axis1_tuser(s_axis1_tuser), + .s_axis1_tready(s_axis1_tready), + `endif + + `ifdef debug_en + .error_missing_sop(unseg2seg_missing_sop_error), + .error_broken_pkt_out(unseg2seg_broken_pkt_out_error), + .error_broken_pkt_in(unseg2seg_broken_pkt_in_error), + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + .p1_pkt_in_cnt(stat_tx_p1_pkt_in_cnt), + .p1_err_pkt_in_cnt(stat_tx_p1_err_pkt_in_cnt), + .p1_pkt_in_byte_cnt(stat_tx_p1_pkt_in_byte_cnt), + .p0_pkt_in_cnt(stat_tx_p0_pkt_in_cnt), + .p0_err_pkt_in_cnt(stat_tx_p0_err_pkt_in_cnt), + .p0_pkt_in_byte_cnt(stat_tx_p0_pkt_in_byte_cnt), + `endif + .total_pkt_in_cnt(stat_tx_total_pkt_in_cnt), + .total_err_pkt_in_cnt(stat_tx_total_err_pkt_in_cnt), + .total_pkt_in_byte_cnt(stat_tx_total_pkt_in_byte_cnt), + .total_pkt_out_cnt(stat_tx_total_pkt_out_cnt), + .total_err_pkt_out_cnt(stat_tx_total_err_pkt_out_cnt), + .total_pkt_out_byte_cnt(stat_tx_total_pkt_out_byte_cnt), + `endif + + .tx_axis_tready_in(Unseg2Seg_tready_in), + .tx_axis_tvalid_out(Unseg2Seg_tvalid_out) + ); + +`endif + +endmodule + +`endif + +//######################################################################################################################## + +//------------------------------------ AXIS Segmented to Unsegmented Stream Converter ------------------------------------ + +module axis_seg_to_unseg_converter + ( + // Clock & Resets + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_seg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET aresetn_axis_seg_in" *) + input aclk_axis_seg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_seg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_seg_in, + `ifdef independant_clk + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_unseg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_pktout, ASSOCIATED_RESET aresetn_axis_unseg_in" *) + input aclk_axis_unseg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_unseg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_unseg_in, + `endif + // Segmented interface + // port0 is active for all valid configurations + // Segment 0 input + input Seg2UnSegEna0_in, + input [`segment_width-1:0] Seg2UnSegDat0_in, + input Seg2UnSegSop0_in, + input Seg2UnSegEop0_in, + input Seg2UnSegErr0_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty0_in, + // Segment 1 input + input Seg2UnSegEna1_in, + input [`segment_width-1:0] Seg2UnSegDat1_in, + input Seg2UnSegSop1_in, + input Seg2UnSegEop1_in, + input Seg2UnSegErr1_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty1_in, + `ifdef en_port1 + // Segment 2 input + input Seg2UnSegEna2_in, + input [`segment_width-1:0] Seg2UnSegDat2_in, + input Seg2UnSegSop2_in, + input Seg2UnSegEop2_in, + input Seg2UnSegErr2_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty2_in, + // Segment 3 input + input Seg2UnSegEna3_in, + input [`segment_width-1:0] Seg2UnSegDat3_in, + input Seg2UnSegSop3_in, + input Seg2UnSegEop3_in, + input Seg2UnSegErr3_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty3_in, + `endif + `ifdef en_port2 + // Segment 4 input + input Seg2UnSegEna4_in, + input [`segment_width-1:0] Seg2UnSegDat4_in, + input Seg2UnSegSop4_in, + input Seg2UnSegEop4_in, + input Seg2UnSegErr4_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty4_in, + // Segment 5 input + input Seg2UnSegEna5_in, + input [`segment_width-1:0] Seg2UnSegDat5_in, + input Seg2UnSegSop5_in, + input Seg2UnSegEop5_in, + input Seg2UnSegErr5_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty5_in, + `endif + `ifdef en_port3 + // Segment 6 input + input Seg2UnSegEna6_in, + input [`segment_width-1:0] Seg2UnSegDat6_in, + input Seg2UnSegSop6_in, + input Seg2UnSegEop6_in, + input Seg2UnSegErr6_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty6_in, + // Segment 7 input + input Seg2UnSegEna7_in, + input [`segment_width-1:0] Seg2UnSegDat7_in, + input Seg2UnSegSop7_in, + input Seg2UnSegEop7_in, + input Seg2UnSegErr7_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty7_in, + `endif + + // Packet output interface - Unsegmented AXI Stream + // AXI-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TDATA" *) + output [`unseg_axis_w-1:0] m_axis0_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TKEEP" *) + output [(`unseg_axis_w/8)-1:0] m_axis0_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TLAST" *) + output m_axis0_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TVALID" *) + output m_axis0_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TUSER" *) + output m_axis0_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TREADY" *) + input m_axis0_tready, + + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TDATA" *) + output [`unseg_axis_w-1:0] m_axis1_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TKEEP" *) + output [(`unseg_axis_w/8)-1:0] m_axis1_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TLAST" *) + output m_axis1_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TVALID" *) + output m_axis1_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TUSER" *) + output m_axis1_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TREADY" *) + input m_axis1_tready, + `endif + + `ifdef en_flow_control + output wire buff_full, + `else + output wire inbuff_overflow, + output wire inbuff_afull, + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + output wire [63: 0] p1_pkt_out_cnt, + output wire [63: 0] p1_err_pkt_out_cnt, + output wire [63: 0] p1_pkt_out_byte_cnt, + output wire [63: 0] p0_pkt_out_cnt, + output wire [63: 0] p0_err_pkt_out_cnt, + output wire [63: 0] p0_pkt_out_byte_cnt, + `endif + output wire [63: 0] total_pkt_in_cnt, + output wire [63: 0] total_err_pkt_in_cnt, + output wire [63: 0] total_pkt_in_byte_cnt, + output wire [63: 0] total_pkt_out_cnt, + output wire [63: 0] total_err_pkt_out_cnt, + output wire [63: 0] total_pkt_out_byte_cnt, + `endif + + `ifdef debug_en + output wire error_broken_packet_out, + output reg seg_rx_err_packet, + `endif + + input wire rx_axis_tvalid_i + ); + +//----------------------------------------------------------------------------------------------------------------------- + +localparam P_MARK_DEBUG = "false"; + +// Derive local parameters + +localparam seg_mty_w = $clog2(`segment_width/8); +localparam pkt_array_depth = `pktarray_depth; +localparam local_buff_depth = 32; +localparam max_pkt_burst_size = $ceil(`max_packet_size/((`pktarray_depth/2)*(`segment_width/8))); +localparam max_pkt_burst_size_p2 = $ceil($clog2(`max_packet_size)); + +`ifdef max_pkt_size_above_1k + localparam pktarry_buff_depth = $ceil((2**(max_pkt_burst_size_p2+1))/((`pktarray_depth/2)*(`segment_width/8))); + localparam pktarry_buff_pfull_thresh = pktarry_buff_depth - max_pkt_burst_size; +`else + localparam pktarry_buff_depth = 32; + localparam pktarry_buff_pfull_thresh = pktarry_buff_depth-7; +`endif + +localparam in_buff_depth = pktarry_buff_depth/2; +localparam out_buff_depth = pktarry_buff_depth*4; +localparam out_buff_pfull_thresh = out_buff_depth - max_pkt_burst_size; + +//----------------------------------------------------------------------------------------------------------------------- + +wire [`num_segments-1:0] seg2unseg_val; +wire [`num_segments-1:0] seg2unseg_sop; +wire [`num_segments-1:0] seg2unseg_eop; +wire [`num_segments-1:0] seg2unseg_err; +wire [`segment_width-1:0] seg2unseg_dat [`num_segments-1:0]; +wire [seg_mty_w-1:0] seg2unseg_mty [`num_segments-1:0]; + +assign seg2unseg_val[0] = Seg2UnSegEna0_in & rx_axis_tvalid_i; assign seg2unseg_sop[0] = Seg2UnSegSop0_in; assign seg2unseg_eop[0] = Seg2UnSegEop0_in; assign seg2unseg_err[0] = Seg2UnSegErr0_in; assign seg2unseg_dat[0] = Seg2UnSegDat0_in; assign seg2unseg_mty[0] = Seg2UnSegMty0_in; +assign seg2unseg_val[1] = Seg2UnSegEna1_in & rx_axis_tvalid_i; assign seg2unseg_sop[1] = Seg2UnSegSop1_in; assign seg2unseg_eop[1] = Seg2UnSegEop1_in; assign seg2unseg_err[1] = Seg2UnSegErr1_in; assign seg2unseg_dat[1] = Seg2UnSegDat1_in; assign seg2unseg_mty[1] = Seg2UnSegMty1_in; +`ifdef en_port1 +assign seg2unseg_val[2] = Seg2UnSegEna2_in & rx_axis_tvalid_i; assign seg2unseg_sop[2] = Seg2UnSegSop2_in; assign seg2unseg_eop[2] = Seg2UnSegEop2_in; assign seg2unseg_err[2] = Seg2UnSegErr2_in; assign seg2unseg_dat[2] = Seg2UnSegDat2_in; assign seg2unseg_mty[2] = Seg2UnSegMty2_in; +assign seg2unseg_val[3] = Seg2UnSegEna3_in & rx_axis_tvalid_i; assign seg2unseg_sop[3] = Seg2UnSegSop3_in; assign seg2unseg_eop[3] = Seg2UnSegEop3_in; assign seg2unseg_err[3] = Seg2UnSegErr3_in; assign seg2unseg_dat[3] = Seg2UnSegDat3_in; assign seg2unseg_mty[3] = Seg2UnSegMty3_in; +`endif +`ifdef en_port2 +assign seg2unseg_val[4] = Seg2UnSegEna4_in & rx_axis_tvalid_i; assign seg2unseg_sop[4] = Seg2UnSegSop4_in; assign seg2unseg_eop[4] = Seg2UnSegEop4_in; assign seg2unseg_err[4] = Seg2UnSegErr4_in; assign seg2unseg_dat[4] = Seg2UnSegDat4_in; assign seg2unseg_mty[4] = Seg2UnSegMty4_in; +assign seg2unseg_val[5] = Seg2UnSegEna5_in & rx_axis_tvalid_i; assign seg2unseg_sop[5] = Seg2UnSegSop5_in; assign seg2unseg_eop[5] = Seg2UnSegEop5_in; assign seg2unseg_err[5] = Seg2UnSegErr5_in; assign seg2unseg_dat[5] = Seg2UnSegDat5_in; assign seg2unseg_mty[5] = Seg2UnSegMty5_in; +`endif +`ifdef en_port3 +assign seg2unseg_val[6] = Seg2UnSegEna6_in & rx_axis_tvalid_i; assign seg2unseg_sop[6] = Seg2UnSegSop6_in; assign seg2unseg_eop[6] = Seg2UnSegEop6_in; assign seg2unseg_err[6] = Seg2UnSegErr6_in; assign seg2unseg_dat[6] = Seg2UnSegDat6_in; assign seg2unseg_mty[6] = Seg2UnSegMty6_in; +assign seg2unseg_val[7] = Seg2UnSegEna7_in & rx_axis_tvalid_i; assign seg2unseg_sop[7] = Seg2UnSegSop7_in; assign seg2unseg_eop[7] = Seg2UnSegEop7_in; assign seg2unseg_err[7] = Seg2UnSegErr7_in; assign seg2unseg_dat[7] = Seg2UnSegDat7_in; assign seg2unseg_mty[7] = Seg2UnSegMty7_in; +`endif + +wire aclk_axis_unseg; +wire aresetn_axis_unseg; + +`ifdef independant_clk + assign aclk_axis_unseg = aclk_axis_unseg_in; + assign aresetn_axis_unseg = aresetn_axis_unseg_in; +`else + assign aclk_axis_unseg = aclk_axis_seg_in; + assign aresetn_axis_unseg = aresetn_axis_seg_in; +`endif + +`ifdef debug_en + + always @ (posedge aclk_axis_unseg) begin + seg_rx_err_packet <= |(seg2unseg_err & seg2unseg_val); + end + +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Input buffer + +reg [`num_segments-1:0] seg2unseg_val_1; +reg [`num_segments-1:0] seg2unseg_sop_1; +reg [`num_segments-1:0] seg2unseg_eop_1; +reg [`num_segments-1:0] seg2unseg_err_1; +reg [`segment_width-1:0] seg2unseg_dat_1 [`num_segments-1:0]; +reg [seg_mty_w-1:0] seg2unseg_mty_1 [`num_segments-1:0]; + +wire [`num_segments-1:0] seg2unseg_val_c; +wire [`num_segments-1:0] seg2unseg_sop_c; +wire [`num_segments-1:0] seg2unseg_eop_c; +wire [`num_segments-1:0] seg2unseg_err_c; +wire [(`segment_width*`num_segments)-1:0] seg2unseg_dat_c; +wire [(seg_mty_w*`num_segments)-1:0] seg2unseg_mty_c; + +genvar a0; +generate + for (a0=0; a0<`num_segments; a0=a0+1) begin + assign seg2unseg_val_c[a0] = seg2unseg_val[a0]; + assign seg2unseg_sop_c[a0] = seg2unseg_sop[a0]; + assign seg2unseg_eop_c[a0] = seg2unseg_eop[a0]; + assign seg2unseg_err_c[a0] = seg2unseg_err[a0]; + assign seg2unseg_dat_c[((a0+1)*`segment_width)-1:a0*`segment_width] = seg2unseg_dat[a0]; + assign seg2unseg_mty_c[((a0+1)*seg_mty_w)-1:a0*seg_mty_w] = seg2unseg_mty[a0]; + end +endgenerate + +wire wr_rst_busy; +wire rd_rst_busy; +wire seg_in_aempty; +wire seg_in_empty; +wire data_valid; +wire seg_inbuff_afull; +wire seg_inbuff_overflow; + +wire ports_not_rdy; +wire [`num_axis_ports-1:0] port_unseg_out_pfull; + +`ifdef independant_clk // Input segmented intreface stream clock domain to unsegmented axis clock domain + +wire [`num_segments-1:0] seg2unseg_val_cdc; +wire [`num_segments-1:0] seg2unseg_sop_cdc; +wire [`num_segments-1:0] seg2unseg_eop_cdc; +wire [`num_segments-1:0] seg2unseg_err_cdc; +wire [(`segment_width*`num_segments)-1:0] seg2unseg_dat_cdc; +wire [(seg_mty_w*`num_segments)-1:0] seg2unseg_mty_cdc; + +xpm_fifo_async #( + .CASCADE_HEIGHT(0), + .CDC_SYNC_STAGES(3), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(2), + .FIFO_WRITE_DEPTH(in_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(in_buff_depth-5), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH((`segment_width+seg_mty_w+4)*`num_segments), + .READ_MODE("std"), + .RELATED_CLOCKS(0), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("1009"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH((`segment_width+seg_mty_w+4)*`num_segments), + .WR_DATA_COUNT_WIDTH(1) + ) +xpm_fifo_async_seg_in ( + .almost_empty(seg_in_aempty), + .almost_full(seg_inbuff_afull), + .data_valid(data_valid), + .dbiterr(), + .dout({seg2unseg_val_cdc,seg2unseg_sop_cdc,seg2unseg_eop_cdc,seg2unseg_err_cdc,seg2unseg_mty_cdc,seg2unseg_dat_cdc}), + .empty(seg_in_empty), + .full(), + .overflow(seg_inbuff_overflow), + .prog_empty(), + .prog_full(), + .rd_data_count(), + .rd_rst_busy(rd_rst_busy), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(wr_rst_busy), + .din({seg2unseg_val_c,seg2unseg_sop_c,seg2unseg_eop_c,seg2unseg_err_c,seg2unseg_mty_c,seg2unseg_dat_c}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_clk(aclk_axis_unseg), + `ifdef en_flow_control + .rd_en(!seg_in_empty & !rd_rst_busy), + `else + .rd_en(!ports_not_rdy & !seg_in_empty & !rd_rst_busy), + `endif + .rst(!aresetn_axis_seg_in), + .sleep(1'b0), + .wr_clk(aclk_axis_seg_in), + .wr_en(|seg2unseg_val_c & !wr_rst_busy) + ); + +genvar i; +generate + for (i=0; i<`num_segments; i=i+1) begin + always @ (posedge aclk_axis_unseg) begin + seg2unseg_val_1[i] <= seg2unseg_val_cdc[i] & data_valid; + seg2unseg_sop_1[i] <= seg2unseg_sop_cdc[i]; + seg2unseg_eop_1[i] <= seg2unseg_eop_cdc[i]; + seg2unseg_err_1[i] <= seg2unseg_err_cdc[i]; + seg2unseg_dat_1[i] <= seg2unseg_dat_cdc[((i+1)*`segment_width)-1:i*`segment_width]; + seg2unseg_mty_1[i] <= seg2unseg_mty_cdc[((i+1)*seg_mty_w)-1:i*seg_mty_w]; + end + end +endgenerate + +`else // Input segmented stream intreface and unsegmented axis interface runs at same clock domain + +wire [`num_segments-1:0] seg2unseg_val_ibuf; +wire [`num_segments-1:0] seg2unseg_sop_ibuf; +wire [`num_segments-1:0] seg2unseg_eop_ibuf; +wire [`num_segments-1:0] seg2unseg_err_ibuf; +wire [(`segment_width*`num_segments)-1:0] seg2unseg_dat_ibuf; +wire [(seg_mty_w*`num_segments)-1:0] seg2unseg_mty_ibuf; + +xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(2), + .FIFO_WRITE_DEPTH(in_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(in_buff_depth-5), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH((`segment_width+seg_mty_w+4)*`num_segments), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("1009"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH((`segment_width+seg_mty_w+4)*`num_segments), + .WR_DATA_COUNT_WIDTH(1) + ) +xpm_fifo_sync_seg_in ( + .almost_empty(seg_in_aempty), + .almost_full(seg_inbuff_afull), + .data_valid(data_valid), + .dbiterr(), + .dout({seg2unseg_val_ibuf,seg2unseg_sop_ibuf,seg2unseg_eop_ibuf,seg2unseg_err_ibuf,seg2unseg_mty_ibuf,seg2unseg_dat_ibuf}), + .empty(seg_in_empty), + .full(), + .overflow(seg_inbuff_overflow), + .prog_empty(), + .prog_full(), + .rd_data_count(), + .rd_rst_busy(rd_rst_busy), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(wr_rst_busy), + .din({seg2unseg_val_c,seg2unseg_sop_c,seg2unseg_eop_c,seg2unseg_err_c,seg2unseg_mty_c,seg2unseg_dat_c}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + `ifdef en_flow_control + .rd_en(!seg_in_empty & !rd_rst_busy), + `else + .rd_en(!ports_not_rdy & !seg_in_empty & !rd_rst_busy), + `endif + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(|seg2unseg_val_c & !wr_rst_busy) +); + +genvar j; +generate + for (j=0; j < `num_segments; j = j+1) begin + always @ (posedge aclk_axis_unseg) begin + seg2unseg_val_1[j] <= seg2unseg_val_ibuf[j] & data_valid; + seg2unseg_sop_1[j] <= seg2unseg_sop_ibuf[j]; + seg2unseg_eop_1[j] <= seg2unseg_eop_ibuf[j]; + seg2unseg_err_1[j] <= seg2unseg_err_ibuf[j]; + seg2unseg_dat_1[j] <= seg2unseg_dat_ibuf[((j+1)*`segment_width)-1:j*`segment_width]; + seg2unseg_mty_1[j] <= seg2unseg_mty_ibuf[((j+1)*seg_mty_w)-1:j*seg_mty_w]; + end + end +endgenerate + +`endif + +assign inbuff_overflow = seg_inbuff_overflow; +assign inbuff_afull = seg_inbuff_afull; + +//----------------------------------------------------------------------------------------------------------------------- + +// Arbitrate packets to different channels based on number of output axis ports (applicable for 400G with 2 AXIS ports) + +reg [`segment_width-1:0] pkt_data [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [seg_mty_w-1:0] pkt_mty [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [`num_segments-1:0] pkt_val [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_eop [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_err [`num_axis_ports-1:0]; + +`ifdef data_rate_400 // two output AXI stream ports available for 400G + +genvar k, l; +generate +for (k=0; k < `num_axis_ports; k = k+1) begin + for(l=0; l < `num_segments; l = l+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_data [k][l] <= seg2unseg_dat_1[l]; + pkt_mty [k][l] <= seg2unseg_mty_1[l]; + pkt_eop [k][l] <= seg2unseg_eop_1[l]; + pkt_err [k][l] <= seg2unseg_err_1[l]; + end + end +end +endgenerate + +// Probe output AXI ports (after power ON / system reset), to initialize the port pointer for port arbiter + +reg [12:0] cnt_port_init; +reg port_init_q, port_init_qq; +wire port_init_rp; + +reg [11:0] out_port_idle_cnt [`num_axis_ports-1:0]; +reg [11:0] out_port_active_cnt [`num_axis_ports-1:0]; +reg [`num_axis_ports-1:0] out_port_active_q; +reg [`num_axis_ports-1:0] out_port_idle_q; +wire [`num_axis_ports-1:0] out_port_active_rp; +wire [`num_axis_ports-1:0] out_port_idle_rp; +wire [`num_axis_ports-1:0] out_port_rdy; +reg [`num_axis_ports-1:0] out_port_not_active; + +assign out_port_rdy[0] = m_axis0_tready; +`ifdef en_axis1 +assign out_port_rdy[1] = m_axis1_tready; +`endif + +reg only_port1_active, only_port0_active; + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + cnt_port_init <= 'd0; + else if (cnt_port_init[12]) + cnt_port_init <= cnt_port_init; + else + cnt_port_init <= cnt_port_init + 1; +end + +always @ (posedge aclk_axis_unseg) begin + port_init_q <= cnt_port_init[12]; + port_init_qq <= port_init_q; +end + +assign port_init_rp = port_init_q & ~port_init_qq; + +genvar kk; + +generate + for (kk=0; kk < `num_axis_ports; kk = kk+1) begin + always @ (posedge aclk_axis_unseg) begin + out_port_active_q[kk] <= out_port_active_cnt[kk][11]; + if (!aresetn_axis_unseg) + out_port_active_cnt[kk] <= 'd0; + else if (out_port_idle_rp[kk]) + out_port_active_cnt[kk] <= 'd0; + else if (!out_port_rdy[kk]) + out_port_active_cnt[kk] <= 'd0; + else if (out_port_active_q[kk]) + out_port_active_cnt[kk] <= out_port_active_cnt[kk]; + else + out_port_active_cnt[kk] <= out_port_active_cnt[kk] + 1; + end + + assign out_port_active_rp[kk] = out_port_active_cnt[kk][11] & ~out_port_active_q[kk]; + + always @ (posedge aclk_axis_unseg) begin + out_port_not_active[kk] <= out_port_idle_cnt[kk][11]; + out_port_idle_q[kk] <= out_port_idle_cnt[kk][11]; + if (!aresetn_axis_unseg) + out_port_idle_cnt[kk] <= 'd0; + else if (out_port_active_rp[kk]) + out_port_idle_cnt[kk] <= 'd0; + else if (out_port_rdy[kk]) + out_port_idle_cnt[kk] <= 'd0; + else if (out_port_idle_q[kk]) + out_port_idle_cnt[kk] <= out_port_idle_cnt[kk]; + else + out_port_idle_cnt[kk] <= out_port_idle_cnt[kk] + 1; + end + + assign out_port_idle_rp[kk] = out_port_idle_cnt[kk][11] & ~out_port_idle_q[kk]; + end +endgenerate + +always @ (posedge aclk_axis_unseg) begin // Update port status when input stream is not active + if (!seg2unseg_val_1[0]) + if (out_port_not_active == 2'b01) + only_port1_active <= 1'b1; + else + only_port1_active <= 1'b0; + else + only_port1_active <= only_port1_active; +end + +always @ (posedge aclk_axis_unseg) begin + if (!seg2unseg_val_1[0]) + if (out_port_not_active == 2'b10) + only_port0_active <= 1'b1; + else + only_port0_active <= 1'b0; + else + only_port0_active <= only_port0_active; +end + +integer m, n; + +reg [$clog2(`num_axis_ports)-1:0] cur_port; +reg nxt_pkt_vld; + +`ifdef en_flow_control // port arbitration with flow control + +generate + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + cur_port = 1'b0; + nxt_pkt_vld = 1'b1; + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + end else if (port_init_rp) begin // Initialize with the active port after power On/systen reset + if (only_port1_active) + cur_port = 1'b1; + else + cur_port = 1'b0; + end else begin + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [cur_port][n] <= 1'b0; + if(seg2unseg_val_1[n]) begin + pkt_val [cur_port][n] <= nxt_pkt_vld; + if (seg2unseg_eop_1[n]) begin // Arbitrate at current packet end + if (only_port1_active) begin // Only out port1 is active + cur_port = 1'b1; + if (port_unseg_out_pfull[1]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end else if (only_port0_active) begin // Only out port0 is active + cur_port = 1'b0; + if (port_unseg_out_pfull[0]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end else begin // Both output ports are active + if (cur_port == (`num_axis_ports-1)) begin + if (port_unseg_out_pfull[0]) begin + cur_port = 1'b1; + if (port_unseg_out_pfull[1]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end else begin + cur_port = 1'b0; + nxt_pkt_vld = 1'b1; + end + end else begin + if (port_unseg_out_pfull[1]) begin + cur_port = 1'b0; + if (port_unseg_out_pfull[0]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end else begin + cur_port = 1'b1; + nxt_pkt_vld = 1'b1; + end + end + end + end + end + end + end +end +endgenerate + +assign buff_full = |port_unseg_out_pfull; + +`else // port arbitration without flow control + +generate + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + cur_port = 1'b0; + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + end else if (port_init_rp) begin // Initialize with the active port after power On/systen reset + if (only_port1_active) + cur_port = 1'b1; + else + cur_port = 1'b0; + end else begin + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [cur_port][n] <= 1'b0; + if(seg2unseg_val_1[n]) begin + pkt_val [cur_port][n] <= 1'b1; + if (seg2unseg_eop_1[n]) begin + if (only_port1_active) begin + cur_port = 1'b1; + end else if (only_port0_active) begin + cur_port = 1'b0; + end else begin + if (cur_port == (`num_axis_ports-1)) begin + if (port_unseg_out_pfull[0]) begin + cur_port = 1'b1; + end else + cur_port = 1'b0; + end else begin + if (port_unseg_out_pfull[1]) begin + cur_port = 1'b0; + end else + cur_port = 1'b1; + end + end + end + end + end + end +end +endgenerate + +`endif + +`else // data rate 100 or 200 Gbps, only one output AXI stream port is available + +`ifdef en_flow_control + +genvar k, l; +generate +for (k=0; k < `num_axis_ports; k = k+1) begin + for(l=0; l < `num_segments; l = l+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_data [k][l] <= seg2unseg_dat_1[l]; + pkt_mty [k][l] <= seg2unseg_mty_1[l]; + pkt_eop [k][l] <= seg2unseg_eop_1[l]; + pkt_err [k][l] <= seg2unseg_err_1[l]; + end + end +end +endgenerate + +reg [$clog2(`num_axis_ports)-1:0] cur_port; +reg nxt_pkt_vld; + +integer m, n; + +generate + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + nxt_pkt_vld = 1'b1; + cur_port <= 1'b0; + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + cur_port <= 1'b0; + end + end + end else begin + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + for(n=0; n < `num_segments; n = n+1) begin + if(seg2unseg_val_1[n]) begin + pkt_val [cur_port][n] <= nxt_pkt_vld; + if (seg2unseg_eop_1[n]) + if (port_unseg_out_pfull[0]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end + end + end + end +endgenerate + +assign buff_full = port_unseg_out_pfull[0]; + +`else + +genvar k,l; + +generate +for (k=0; k < `num_axis_ports; k = k+1) begin + for(l=0; l < `num_segments; l = l+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_data [k][l] <= seg2unseg_dat_1[l]; + pkt_mty [k][l] <= seg2unseg_mty_1[l]; + pkt_eop [k][l] <= seg2unseg_eop_1[l]; + pkt_err [k][l] <= seg2unseg_err_1[l]; + pkt_val [k][l] <= seg2unseg_val_1[l]; + end + end +end +endgenerate + +`endif + +`endif + +reg [`segment_width-1:0] pkt_data1 [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [seg_mty_w-1:0] pkt_mty1 [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [`num_segments-1:0] pkt_val1 [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_eop1 [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_err1 [`num_axis_ports-1:0]; + +reg [`segment_width-1:0] pkt_data2 [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [seg_mty_w-1:0] pkt_mty2 [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [`num_segments-1:0] pkt_val2 [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_eop2 [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_err2 [`num_axis_ports-1:0]; + +genvar o, p; +generate +for (o=0; o < `num_axis_ports; o = o+1) begin + for(p=0; p < `num_segments; p = p+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_data1[o][p] <= pkt_data [o][p]; + pkt_mty1 [o][p] <= pkt_mty [o][p]; + pkt_eop1 [o][p] <= pkt_eop [o][p]; + pkt_err1 [o][p] <= pkt_err [o][p]; + pkt_val1 [o][p] <= pkt_val [o][p]; + end + always @ (posedge aclk_axis_unseg) begin + pkt_data2[o][p] <= pkt_data1 [o][p]; + pkt_mty2 [o][p] <= pkt_mty1 [o][p]; + pkt_eop2 [o][p] <= pkt_eop1 [o][p]; + pkt_err2 [o][p] <= pkt_err1 [o][p]; + pkt_val2 [o][p] <= pkt_val1 [o][p]; + end + end +end +endgenerate + +reg [`segment_width-1:0] pkt_tdata [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(`segment_width/8)-1:0] pkt_tkeep [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_tvalid [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_tuser [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_tlast [`num_axis_ports-1:0]; +reg [(`segment_width*(pkt_array_depth/2))-1:0] axis_tdata_buf_in [`num_axis_ports-1:0]; +reg [((`segment_width/8)*(pkt_array_depth/2))-1:0] axis_tkeep_buf_in [`num_axis_ports-1:0]; +reg [`num_axis_ports-1:0] axis_tvalid_buf_in; +reg [`num_axis_ports-1:0] axis_tlast_buf_in; +reg [`num_axis_ports-1:0] axis_tuser_buf_in; +wire [`num_axis_ports-1:0] axis_tready_buf_in; +reg [`segment_width-1:0] pkt_data_out_0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pkt_mty_out_0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_val_out_0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_eop_out_0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_err_out_0 [`num_axis_ports-1:0]; + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Segment array + +// pack the packet segments in array (to align with unsegmented axis stream data width) + +wire [`num_axis_ports-1:0] outbuff_pfull; + +`ifdef data_rate_400 + +reg [`segment_width-1:0] pkt_data_array [`num_axis_ports-1:0] [pkt_array_depth-1:0]; +reg [seg_mty_w-1:0] pkt_mty_array [`num_axis_ports-1:0] [pkt_array_depth-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array0 [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array00 [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array1 [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array2 [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_eop_array [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_err_array [`num_axis_ports-1:0]; + +reg [$clog2(pkt_array_depth)-1:0] pkt_array_ptr [`num_axis_ports-1:0]; +reg [$clog2(pkt_array_depth)-1:0] pkt_seg_sel_reg [`num_axis_ports-1:0] [pkt_array_depth-1:0]; +reg [$clog2(pkt_array_depth)-1:0] pkt_seg_sel_reg1 [`num_axis_ports-1:0] [pkt_array_depth-1:0]; + +wire [`num_axis_ports-1:0] wr_en_c0; +wire [`num_axis_ports-1:0] wr_en_c1; + +reg [`num_axis_ports-1:0] wr_en_0; +reg [`num_axis_ports-1:0] wr_en_1; + +genvar q; +integer r, rr; +generate +for (q=0; q < `num_axis_ports; q = q+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_array_ptr[q] = 0; + for(r=0; r < pkt_array_depth/2; r = r+1) begin + pkt_val_array0 [q][r] <= 1'b0; + pkt_val_array1 [q][r] <= 1'b0; + pkt_seg_sel_reg[q][r] <= 'd0; + end + for(rr=pkt_array_depth/2; rr < pkt_array_depth; rr = rr+1) begin + pkt_val_array0 [q][rr] <= 1'b0; + pkt_val_array1 [q][rr] <= 1'b0; + pkt_seg_sel_reg[q][rr] <= 'd0; + end + end else begin + for(r=0; r < pkt_array_depth/2; r = r+1) begin + pkt_val_array0 [q][r] <= 1'b0; + end + for(rr=pkt_array_depth/2; rr < pkt_array_depth; rr = rr+1) begin + pkt_val_array0 [q][rr] <= 1'b0; + end + if (wr_en_c0[q]) begin + for(rr=0; rr < pkt_array_depth/2; rr = rr+1) begin + pkt_val_array1 [q][rr] <= 1'b0; + end + end + if (wr_en_c1[q]) begin + for(rr=pkt_array_depth/2; rr < pkt_array_depth; rr = rr+1) begin + pkt_val_array1 [q][rr] <= 1'b0; + end + end + for(r=0; r < `num_segments; r = r+1) begin + if (pkt_val[q][r]) begin + pkt_val_array0 [q][pkt_array_ptr[q]] <= 1'b1; + pkt_val_array1 [q][pkt_array_ptr[q]] <= 1'b1; + pkt_seg_sel_reg[q][pkt_array_ptr[q]] <= r; + if (pkt_eop[q][r]) begin + if (pkt_array_ptr[q][$clog2(pkt_array_depth)-1] == 1) + pkt_array_ptr[q] = 0; + else + pkt_array_ptr[q] = pkt_array_depth/2; + end else + pkt_array_ptr[q] = pkt_array_ptr[q] + 1; + end + end + end + end +end +endgenerate + +genvar s, array_depth; +generate +for (s=0; s < `num_axis_ports; s = s+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_val_array2[s] <= pkt_val_array1[s]; + pkt_val_array[s] <= pkt_val_array2[s]; + pkt_val_array00[s] <= pkt_val_array0[s]; + end + for (array_depth=0; array_depth < pkt_array_depth; array_depth = array_depth+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_seg_sel_reg1[s][array_depth] <= pkt_seg_sel_reg[s][array_depth]; + end + end + for (array_depth=0; array_depth < pkt_array_depth; array_depth = array_depth+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_eop_array[s][array_depth] <= 1'b0; + pkt_err_array[s][array_depth] <= 1'b0; + pkt_mty_array[s][array_depth] <= 'd0; + pkt_data_array[s][array_depth] <= 'd0; + end else begin + if (pkt_val_array00[s][array_depth]) begin + pkt_eop_array[s][array_depth] <= pkt_eop2 [s][pkt_seg_sel_reg1[s][array_depth]]; + pkt_err_array[s][array_depth] <= pkt_err2 [s][pkt_seg_sel_reg1[s][array_depth]]; + pkt_mty_array[s][array_depth] <= pkt_mty2 [s][pkt_seg_sel_reg1[s][array_depth]]; + pkt_data_array[s][array_depth] <= pkt_data2[s][pkt_seg_sel_reg1[s][array_depth]]; + end else begin + pkt_eop_array[s][array_depth] <= 1'b0; + pkt_err_array[s][array_depth] <= 1'b0; + end + end + end + end +end +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Buffering packed segments + +reg [`num_axis_ports-1:0] rd_en_0; +reg [`num_axis_ports-1:0] rd_en_1; + +genvar t; + +generate +for (t=0; t<`num_axis_ports; t=t+1) begin + assign wr_en_c0[t] = pkt_val_array1[t][(pkt_array_depth/2)-1] | (|pkt_eop_array[t][(pkt_array_depth/2)-1:0]); + assign wr_en_c1[t] = pkt_val_array1[t][pkt_array_depth-1] | (|pkt_eop_array[t][pkt_array_depth-1:(pkt_array_depth/2)]); + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + wr_en_0[t] <= 1'b0; + wr_en_1[t] <= 1'b0; + end else begin + wr_en_0[t] <= pkt_val_array[t][(pkt_array_depth/2)-1] | (|pkt_eop_array[t][(pkt_array_depth/2)-1:0]); + wr_en_1[t] <= pkt_val_array[t][pkt_array_depth-1] | (|pkt_eop_array[t][pkt_array_depth-1:(pkt_array_depth/2)]); + end + end +end +endgenerate + +reg [`segment_width-1:0] pkt_data_buf_in_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pkt_mty_buf_in_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_val_buf_in_p0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_eop_buf_in_p0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_err_buf_in_p0 [`num_axis_ports-1:0]; +reg [`segment_width-1:0] pkt_data_buf_in_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pkt_mty_buf_in_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_val_buf_in_p1 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_eop_buf_in_p1 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_err_buf_in_p1 [`num_axis_ports-1:0]; + +wire [(pkt_array_depth/2)-1:0] unseg_buf1_aempty_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_buf1_aempty_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_buf1_empty_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_buf1_empty_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_data_valid_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_data_valid_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_rd_rst_busy_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_rd_rst_busy_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_wr_rst_busy_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_wr_rst_busy_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_1 [`num_axis_ports-1:0]; + +wire [`segment_width-1:0] pkt_data_buf_out_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pkt_mty_buf_out_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_val_buf_out_p0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_eop_buf_out_p0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_err_buf_out_p0 [`num_axis_ports-1:0]; +wire [`segment_width-1:0] pkt_data_buf_out_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pkt_mty_buf_out_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_val_buf_out_p1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_eop_buf_out_p1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_err_buf_out_p1 [`num_axis_ports-1:0]; + +genvar u,v; + +generate +for (u=0; u<`num_axis_ports; u=u+1) begin + for (v=0; v<(pkt_array_depth/2); v=v+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_val_buf_in_p0[u][v] <= 1'b0; + pkt_eop_buf_in_p0[u][v] <= 1'b0; + pkt_err_buf_in_p0[u][v] <= 1'b0; + pkt_val_buf_in_p1[u][v] <= 1'b0; + pkt_eop_buf_in_p1[u][v] <= 1'b0; + pkt_err_buf_in_p1[u][v] <= 1'b0; + end else begin + pkt_val_buf_in_p0[u][v] <= pkt_val_array[u][v]; + pkt_data_buf_in_p0[u][v] <= pkt_data_array[u][v]; + pkt_mty_buf_in_p0[u][v] <= pkt_mty_array[u][v]; + pkt_eop_buf_in_p0[u][v] <= pkt_eop_array[u][v]; + pkt_err_buf_in_p0[u][v] <= pkt_err_array[u][v]; + pkt_val_buf_in_p1[u][v] <= pkt_val_array[u][v+(pkt_array_depth/2)]; + pkt_data_buf_in_p1[u][v] <= pkt_data_array[u][v+(pkt_array_depth/2)]; + pkt_mty_buf_in_p1[u][v] <= pkt_mty_array[u][v+(pkt_array_depth/2)]; + pkt_eop_buf_in_p1[u][v] <= pkt_eop_array[u][v+(pkt_array_depth/2)]; + pkt_err_buf_in_p1[u][v] <= pkt_err_array[u][v+(pkt_array_depth/2)]; + end + end + end +end +endgenerate + +genvar w,x; +generate +for (w=0; w<`num_axis_ports; w=w+1) begin + for (x=0; x<(pkt_array_depth/2); x=x+1) begin + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("1002"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_stage1_p0 ( + .almost_empty(unseg_buf1_aempty_0[w][x]), + .almost_full(), + .data_valid(unseg_data_valid_0[w][x]), + .dbiterr(), + .dout({pkt_mty_buf_out_p0[w][x],pkt_err_buf_out_p0[w][x],pkt_eop_buf_out_p0[w][x],pkt_val_buf_out_p0[w][x],pkt_data_buf_out_p0[w][x]}), + .empty(unseg_buf1_empty_0[w][x]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_0[w][x]), + .rd_data_count(), + .rd_rst_busy(unseg_rd_rst_busy_0[w][x]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_wr_rst_busy_0[w][x]), + .din({pkt_mty_buf_in_p0[w][x],pkt_err_buf_in_p0[w][x],pkt_eop_buf_in_p0[w][x],pkt_val_buf_in_p0[w][x],pkt_data_buf_in_p0[w][x]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en_0[w] & !outbuff_pfull[w] & !unseg_data_valid_0[w][x]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en_0[w] & !unseg_wr_rst_busy_0[w][x]) + ); + + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("1002"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_stage1_p1 ( + .almost_empty(unseg_buf1_aempty_1[w][x]), + .almost_full(), + .data_valid(unseg_data_valid_1[w][x]), + .dbiterr(), + .dout({pkt_mty_buf_out_p1[w][x],pkt_err_buf_out_p1[w][x],pkt_eop_buf_out_p1[w][x],pkt_val_buf_out_p1[w][x],pkt_data_buf_out_p1[w][x]}), + .empty(unseg_buf1_empty_1[w][x]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_1[w][x]), + .rd_data_count(), + .rd_rst_busy(unseg_rd_rst_busy_1[w][x]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_wr_rst_busy_1[w][x]), + .din({pkt_mty_buf_in_p1[w][x],pkt_err_buf_in_p1[w][x],pkt_eop_buf_in_p1[w][x],pkt_val_buf_in_p1[w][x],pkt_data_buf_in_p1[w][x]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en_1[w] & !outbuff_pfull[w] & !unseg_data_valid_1[w][x]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en_1[w] & !unseg_wr_rst_busy_1[w][x]) + ); + end + assign port_unseg_out_pfull[w] = (|unseg_out_buf1_pfull_0[w]) | (|unseg_out_buf1_pfull_1[w]); +end +endgenerate + +assign ports_not_rdy = &port_unseg_out_pfull; + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Packet readout / array port arbitration + +reg [`num_axis_ports-1:0] port_sel; +reg [`num_axis_ports-1:0] port_sel_1; + +genvar y; + +generate +for (y=0; y<`num_axis_ports; y=y+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + rd_en_0[y] <= 1'b0; + rd_en_1[y] <= 1'b0; + port_sel[y] <= 1'b0; + port_sel_1[y] <= 1'b0; + end else if (!outbuff_pfull[y]) begin + rd_en_0[y] <= 1'b0; + rd_en_1[y] <= 1'b0; + port_sel_1[y] <= port_sel[y]; + if (port_sel[y]) begin + rd_en_0[y] <= 1'b0; + if (!(|unseg_buf1_empty_1[y]) && !(|unseg_rd_rst_busy_1[y])) begin + rd_en_1[y] <= 1'b1; + port_sel[y] <= 1'b0; + end else begin + rd_en_1[y] <= 1'b0; + port_sel[y] <= port_sel[y]; + end + end else begin + rd_en_1[y] <= 1'b0; + if (!(|unseg_buf1_empty_0[y]) && !(|unseg_rd_rst_busy_0[y])) begin + rd_en_0[y] <= 1'b1; + port_sel[y] <= 1'b1; + end else begin + rd_en_0[y] <= 1'b0; + port_sel[y] <= port_sel[y]; + end + end + end + end +end +endgenerate + +genvar z, zz; + +generate +for (z=0; z<`num_axis_ports; z=z+1) begin :packet_out_mux + for (zz=0; zz<(pkt_array_depth/2); zz=zz+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_val_out_0[z][zz] <= 1'b0; + pkt_mty_out_0[z][zz] <= {seg_mty_w{1'b1}}; + pkt_eop_out_0[z][zz] <= 1'b0; + pkt_err_out_0[z][zz] <= 1'b0; + end else begin + pkt_val_out_0[z][zz] <= 1'b0; + if (port_sel_1[z]) begin + pkt_val_out_0[z][zz] <= pkt_val_buf_out_p0[z][zz] & unseg_data_valid_0[z][zz]; + pkt_mty_out_0[z][zz] <= pkt_mty_buf_out_p0[z][zz]; + pkt_eop_out_0[z][zz] <= pkt_eop_buf_out_p0[z][zz]; + pkt_err_out_0[z][zz] <= pkt_err_buf_out_p0[z][zz]; + pkt_data_out_0[z][zz] <= pkt_data_buf_out_p0[z][zz]; + end else begin + pkt_val_out_0[z][zz] <= pkt_val_buf_out_p1[z][zz] & unseg_data_valid_1[z][zz]; + pkt_mty_out_0[z][zz] <= pkt_mty_buf_out_p1[z][zz]; + pkt_eop_out_0[z][zz] <= pkt_eop_buf_out_p1[z][zz]; + pkt_err_out_0[z][zz] <= pkt_err_buf_out_p1[z][zz]; + pkt_data_out_0[z][zz] <= pkt_data_buf_out_p1[z][zz]; + end + end + end + end +end +endgenerate + +`else // 100G or 200G + +reg [`segment_width-1:0] pktout_data_array [`num_axis_ports-1:0] [pkt_array_depth*2-1:0]; +reg [seg_mty_w-1:0] pktout_mty_array [`num_axis_ports-1:0] [pkt_array_depth*2-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array0 [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array00 [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array1 [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array2 [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_eop_array [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_err_array [`num_axis_ports-1:0]; + +reg [$clog2(pkt_array_depth*2)-1:0] pktout_array_ptr [`num_axis_ports-1:0]; +reg [$clog2(pkt_array_depth)-1:0] pktout_seg_sel_reg [`num_axis_ports-1:0] [pkt_array_depth*2-1:0]; +reg [$clog2(pkt_array_depth)-1:0] pktout_seg_sel_reg1 [`num_axis_ports-1:0] [pkt_array_depth*2-1:0]; + +wire [`num_axis_ports-1:0] wr_en_c0; +wire [`num_axis_ports-1:0] wr_en_c1; +wire [`num_axis_ports-1:0] wr_en_c2; +wire [`num_axis_ports-1:0] wr_en_c3; + +reg [`num_axis_ports-1:0] wr_en0; +reg [`num_axis_ports-1:0] wr_en1; +reg [`num_axis_ports-1:0] wr_en2; +reg [`num_axis_ports-1:0] wr_en3; + +genvar q; +integer r, rr; +generate +for (q=0; q < `num_axis_ports; q = q+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pktout_array_ptr[q] = 0; + for(r=0; r < pkt_array_depth/2; r = r+1) begin + pktout_val_array0 [q][r] <= 1'b0; + pktout_val_array1 [q][r] <= 1'b0; + pktout_seg_sel_reg[q][r] <= 'd0; + pktout_val_array0 [q][r+pkt_array_depth/2] <= 1'b0; + pktout_val_array1 [q][r+pkt_array_depth/2] <= 1'b0; + pktout_seg_sel_reg[q][r+pkt_array_depth/2] <= 'd0; + pktout_val_array0 [q][r+(pkt_array_depth/2)*2] <= 1'b0; + pktout_val_array1 [q][r+(pkt_array_depth/2)*2] <= 1'b0; + pktout_seg_sel_reg[q][r+(pkt_array_depth/2)*2] <= 'd0; + pktout_val_array0 [q][r+(pkt_array_depth/2)*3] <= 1'b0; + pktout_val_array1 [q][r+(pkt_array_depth/2)*3] <= 1'b0; + pktout_seg_sel_reg[q][r+(pkt_array_depth/2)*3] <= 'd0; + end + end else begin + for(r=0; r < pkt_array_depth/2; r = r+1) begin + pktout_val_array0 [q][r] <= 1'b0; + pktout_val_array0 [q][r+pkt_array_depth/2] <= 1'b0; + pktout_val_array0 [q][r+(pkt_array_depth/2)*2] <= 1'b0; + pktout_val_array0 [q][r+(pkt_array_depth/2)*3] <= 1'b0; + end + if (wr_en_c0[q]) begin + for(rr=0; rr < pkt_array_depth/2; rr = rr+1) begin + pktout_val_array1 [q][rr] <= 1'b0; + end + end + if (wr_en_c1[q]) begin + for(rr=pkt_array_depth/2; rr < pkt_array_depth; rr = rr+1) begin + pktout_val_array1 [q][rr] <= 1'b0; + end + end + if (wr_en_c2[q]) begin + for(rr=pkt_array_depth; rr < (pkt_array_depth/2)*3; rr = rr+1) begin + pktout_val_array1 [q][rr] <= 1'b0; + end + end + if (wr_en_c3[q]) begin + for(rr=(pkt_array_depth/2)*3; rr < (pkt_array_depth/2)*4; rr = rr+1) begin + pktout_val_array1 [q][rr] <= 1'b0; + end + end + for(r=0; r < `num_segments; r = r+1) begin + if (pkt_val[q][r]) begin + pktout_val_array0 [q][pktout_array_ptr[q]] <= 1'b1; + pktout_val_array1 [q][pktout_array_ptr[q]] <= 1'b1; + pktout_seg_sel_reg[q][pktout_array_ptr[q]] <= r; + if (pkt_eop[q][r]) begin + if (pktout_array_ptr[q][$clog2(pkt_array_depth*2)-1:$clog2(pkt_array_depth*2)-2] == 2'b11) + pktout_array_ptr[q] = 0; + else if (pktout_array_ptr[q][$clog2(pkt_array_depth*2)-1:$clog2(pkt_array_depth*2)-2] == 2'b10) + pktout_array_ptr[q] = (pkt_array_depth/2)*3; + else if (pktout_array_ptr[q][$clog2(pkt_array_depth*2)-1:$clog2(pkt_array_depth*2)-2] == 2'b01) + pktout_array_ptr[q] = pkt_array_depth; + else + pktout_array_ptr[q] = pkt_array_depth/2; + end else + pktout_array_ptr[q] = pktout_array_ptr[q] + 1; + end + end + end + end +end +endgenerate + +genvar s, array_depth0; +generate +for (s=0; s < `num_axis_ports; s = s+1) begin + always @ (posedge aclk_axis_unseg) begin + pktout_val_array2[s] <= pktout_val_array1[s]; + pktout_val_array[s] <= pktout_val_array2[s]; + pktout_val_array00[s] <= pktout_val_array0[s]; + end + for (array_depth0=0; array_depth0 < pkt_array_depth*2; array_depth0 = array_depth0+1) begin + always @ (posedge aclk_axis_unseg) begin + pktout_seg_sel_reg1[s][array_depth0] <= pktout_seg_sel_reg[s][array_depth0]; + end + end + for (array_depth0=0; array_depth0 < pkt_array_depth*2; array_depth0 = array_depth0+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pktout_eop_array[s][array_depth0] <= 1'b0; + pktout_err_array[s][array_depth0] <= 1'b0; + pktout_mty_array[s][array_depth0] <= 'd0; + pktout_data_array[s][array_depth0] <= 'd0; + end else begin + if (pktout_val_array00[s][array_depth0]) begin + pktout_eop_array[s][array_depth0] <= pkt_eop2 [s][pktout_seg_sel_reg1[s][array_depth0]]; + pktout_err_array[s][array_depth0] <= pkt_err2 [s][pktout_seg_sel_reg1[s][array_depth0]]; + pktout_mty_array[s][array_depth0] <= pkt_mty2 [s][pktout_seg_sel_reg1[s][array_depth0]]; + pktout_data_array[s][array_depth0] <= pkt_data2[s][pktout_seg_sel_reg1[s][array_depth0]]; + end else begin + pktout_eop_array[s][array_depth0] <= 1'b0; + pktout_err_array[s][array_depth0] <= 1'b0; + end + end + end + end +end +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Buffering packed segments + +reg rd_en0; +reg rd_en1; +reg rd_en2; +reg rd_en3; + +genvar t; + +generate +for (t=0; t<`num_axis_ports; t=t+1) begin + assign wr_en_c0[t] = pktout_val_array1[t][(pkt_array_depth/2)-1] | (|pktout_eop_array[t][(pkt_array_depth/2)-1:0]); + assign wr_en_c1[t] = pktout_val_array1[t][((pkt_array_depth/2)*2)-1] | (|pktout_eop_array[t][((pkt_array_depth/2)*2)-1:(pkt_array_depth/2)]); + assign wr_en_c2[t] = pktout_val_array1[t][((pkt_array_depth/2)*3)-1] | (|pktout_eop_array[t][((pkt_array_depth/2)*3)-1:((pkt_array_depth/2)*2)]); + assign wr_en_c3[t] = pktout_val_array1[t][(pkt_array_depth*2)-1] | (|pktout_eop_array[t][(pkt_array_depth*2)-1:((pkt_array_depth/2)*3)]); + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + wr_en0[t] <= 1'b0; + wr_en1[t] <= 1'b0; + wr_en2[t] <= 1'b0; + wr_en3[t] <= 1'b0; + end else begin + wr_en0[t] <= pktout_val_array[t][(pkt_array_depth/2)-1] | (|pktout_eop_array[t][(pkt_array_depth/2)-1:0]); + wr_en1[t] <= pktout_val_array[t][((pkt_array_depth/2)*2)-1] | (|pktout_eop_array[t][((pkt_array_depth/2)*2)-1:(pkt_array_depth/2)]); + wr_en2[t] <= pktout_val_array[t][((pkt_array_depth/2)*3)-1] | (|pktout_eop_array[t][((pkt_array_depth/2)*3)-1:((pkt_array_depth/2)*2)]); + wr_en3[t] <= pktout_val_array[t][(pkt_array_depth*2)-1] | (|pktout_eop_array[t][(pkt_array_depth*2)-1:((pkt_array_depth/2)*3)]); + end + end +end +endgenerate + +reg [`segment_width-1:0] pktout_data_buf_in_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pktout_mty_buf_in_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_val_buf_in_p0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_eop_buf_in_p0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_err_buf_in_p0 [`num_axis_ports-1:0]; +reg [`segment_width-1:0] pktout_data_buf_in_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pktout_mty_buf_in_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_val_buf_in_p1 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_eop_buf_in_p1 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_err_buf_in_p1 [`num_axis_ports-1:0]; +reg [`segment_width-1:0] pktout_data_buf_in_p2 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pktout_mty_buf_in_p2 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_val_buf_in_p2 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_eop_buf_in_p2 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_err_buf_in_p2 [`num_axis_ports-1:0]; +reg [`segment_width-1:0] pktout_data_buf_in_p3 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pktout_mty_buf_in_p3 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_val_buf_in_p3 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_eop_buf_in_p3 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_err_buf_in_p3 [`num_axis_ports-1:0]; + +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_aempty_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_aempty_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_empty_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_empty_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_data_valid_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_data_valid_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_rd_rst_busy_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_rd_rst_busy_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_wr_rst_busy_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_wr_rst_busy_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_aempty_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_aempty_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_empty_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_empty_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_data_valid_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_data_valid_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_rd_rst_busy_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_rd_rst_busy_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_wr_rst_busy_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_wr_rst_busy_3 [`num_axis_ports-1:0]; + +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_afull_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_afull_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_afull_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_afull_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_3 [`num_axis_ports-1:0]; + +wire [`segment_width-1:0] pktout_data_buf_out_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pktout_mty_buf_out_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_val_buf_out_p0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_eop_buf_out_p0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_err_buf_out_p0 [`num_axis_ports-1:0]; +wire [`segment_width-1:0] pktout_data_buf_out_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pktout_mty_buf_out_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_val_buf_out_p1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_eop_buf_out_p1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_err_buf_out_p1 [`num_axis_ports-1:0]; +wire [`segment_width-1:0] pktout_data_buf_out_p2 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pktout_mty_buf_out_p2 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_val_buf_out_p2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_eop_buf_out_p2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_err_buf_out_p2 [`num_axis_ports-1:0]; +wire [`segment_width-1:0] pktout_data_buf_out_p3 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pktout_mty_buf_out_p3 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_val_buf_out_p3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1: 0] pktout_eop_buf_out_p3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1: 0] pktout_err_buf_out_p3 [`num_axis_ports-1:0]; + +genvar u1,v1; + +generate +for (u1=0; u1<`num_axis_ports; u1=u1+1) begin + for (v1=0; v1<(pkt_array_depth/2); v1=v1+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pktout_val_buf_in_p0[u1][v1] <= 1'b0; + pktout_eop_buf_in_p0[u1][v1] <= 1'b0; + pktout_err_buf_in_p0[u1][v1] <= 1'b0; + pktout_val_buf_in_p1[u1][v1] <= 1'b0; + pktout_eop_buf_in_p1[u1][v1] <= 1'b0; + pktout_err_buf_in_p1[u1][v1] <= 1'b0; + pktout_val_buf_in_p2[u1][v1] <= 1'b0; + pktout_eop_buf_in_p2[u1][v1] <= 1'b0; + pktout_err_buf_in_p2[u1][v1] <= 1'b0; + pktout_val_buf_in_p3[u1][v1] <= 1'b0; + pktout_eop_buf_in_p3[u1][v1] <= 1'b0; + pktout_err_buf_in_p3[u1][v1] <= 1'b0; + end else begin + pktout_val_buf_in_p0[u1][v1] <= pktout_val_array[u1][v1]; + pktout_data_buf_in_p0[u1][v1] <= pktout_data_array[u1][v1]; + pktout_mty_buf_in_p0[u1][v1] <= pktout_mty_array[u1][v1]; + pktout_eop_buf_in_p0[u1][v1] <= pktout_eop_array[u1][v1]; + pktout_err_buf_in_p0[u1][v1] <= pktout_err_array[u1][v1]; + pktout_val_buf_in_p1[u1][v1] <= pktout_val_array[u1][v1+(pkt_array_depth/2)]; + pktout_data_buf_in_p1[u1][v1] <= pktout_data_array[u1][v1+(pkt_array_depth/2)]; + pktout_mty_buf_in_p1[u1][v1] <= pktout_mty_array[u1][v1+(pkt_array_depth/2)]; + pktout_eop_buf_in_p1[u1][v1] <= pktout_eop_array[u1][v1+(pkt_array_depth/2)]; + pktout_err_buf_in_p1[u1][v1] <= pktout_err_array[u1][v1+(pkt_array_depth/2)]; + pktout_val_buf_in_p2[u1][v1] <= pktout_val_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_data_buf_in_p2[u1][v1] <= pktout_data_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_mty_buf_in_p2[u1][v1] <= pktout_mty_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_eop_buf_in_p2[u1][v1] <= pktout_eop_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_err_buf_in_p2[u1][v1] <= pktout_err_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_val_buf_in_p3[u1][v1] <= pktout_val_array[u1][v1+((pkt_array_depth/2)*3)]; + pktout_data_buf_in_p3[u1][v1] <= pktout_data_array[u1][v1+((pkt_array_depth/2)*3)]; + pktout_mty_buf_in_p3[u1][v1] <= pktout_mty_array[u1][v1+((pkt_array_depth/2)*3)]; + pktout_eop_buf_in_p3[u1][v1] <= pktout_eop_array[u1][v1+((pkt_array_depth/2)*3)]; + pktout_err_buf_in_p3[u1][v1] <= pktout_err_array[u1][v1+((pkt_array_depth/2)*3)]; + end + end + end +end +endgenerate + +genvar w1,x1; +generate +for (w1=0; w1<`num_axis_ports; w1=w1+1) begin + for (x1=0; x1<(pkt_array_depth/2); x1=x1+1) begin + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(3), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_out_stage1_p0 ( + .almost_empty(unseg_out_buf1_aempty_0[w1][x1]), + .almost_full(unseg_out_buf1_afull_0[w1][x1]), + .data_valid(unseg_out_data_valid_0[w1][x1]), + .dbiterr(), + .dout({pktout_mty_buf_out_p0[w1][x1],pktout_err_buf_out_p0[w1][x1],pktout_eop_buf_out_p0[w1][x1],pktout_val_buf_out_p0[w1][x1],pktout_data_buf_out_p0[w1][x1]}), + .empty(unseg_out_buf1_empty_0[w1][x1]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_0[w1][x1]), + .rd_data_count(), + .rd_rst_busy(unseg_out_rd_rst_busy_0[w1][x1]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_out_wr_rst_busy_0[w1][x1]), + .din({pktout_mty_buf_in_p0[w1][x1],pktout_err_buf_in_p0[w1][x1],pktout_eop_buf_in_p0[w1][x1],pktout_val_buf_in_p0[w1][x1],pktout_data_buf_in_p0[w1][x1]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en0 & !outbuff_pfull & !unseg_out_data_valid_0[w1][x1]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en0[w1] & !unseg_out_wr_rst_busy_0[w1][x1]) + ); + + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(3), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_out_stage1_p1 ( + .almost_empty(unseg_out_buf1_aempty_1[w1][x1]), + .almost_full(unseg_out_buf1_afull_1[w1][x1]), + .data_valid(unseg_out_data_valid_1[w1][x1]), + .dbiterr(), + .dout({pktout_mty_buf_out_p1[w1][x1],pktout_err_buf_out_p1[w1][x1],pktout_eop_buf_out_p1[w1][x1],pktout_val_buf_out_p1[w1][x1],pktout_data_buf_out_p1[w1][x1]}), + .empty(unseg_out_buf1_empty_1[w1][x1]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_1[w1][x1]), + .rd_data_count(), + .rd_rst_busy(unseg_out_rd_rst_busy_1[w1][x1]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_out_wr_rst_busy_1[w1][x1]), + .din({pktout_mty_buf_in_p1[w1][x1],pktout_err_buf_in_p1[w1][x1],pktout_eop_buf_in_p1[w1][x1],pktout_val_buf_in_p1[w1][x1],pktout_data_buf_in_p1[w1][x1]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en1 & !outbuff_pfull & !unseg_out_data_valid_1[w1][x1]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en1[w1] & !unseg_out_wr_rst_busy_1[w1][x1]) + ); + + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(3), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_out_stage1_p2 ( + .almost_empty(unseg_out_buf1_aempty_2[w1][x1]), + .almost_full(unseg_out_buf1_afull_2[w1][x1]), + .data_valid(unseg_out_data_valid_2[w1][x1]), + .dbiterr(), + .dout({pktout_mty_buf_out_p2[w1][x1],pktout_err_buf_out_p2[w1][x1],pktout_eop_buf_out_p2[w1][x1],pktout_val_buf_out_p2[w1][x1],pktout_data_buf_out_p2[w1][x1]}), + .empty(unseg_out_buf1_empty_2[w1][x1]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_2[w1][x1]), + .rd_data_count(), + .rd_rst_busy(unseg_out_rd_rst_busy_2[w1][x1]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_out_wr_rst_busy_2[w1][x1]), + .din({pktout_mty_buf_in_p2[w1][x1],pktout_err_buf_in_p2[w1][x1],pktout_eop_buf_in_p2[w1][x1],pktout_val_buf_in_p2[w1][x1],pktout_data_buf_in_p2[w1][x1]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en2 & !outbuff_pfull & !unseg_out_data_valid_2[w1][x1]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en2[w1] & !unseg_out_wr_rst_busy_2[w1][x1]) + ); + + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(3), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_out_stage1_p3 ( + .almost_empty(unseg_out_buf1_aempty_3[w1][x1]), + .almost_full(unseg_out_buf1_afull_3[w1][x1]), + .data_valid(unseg_out_data_valid_3[w1][x1]), + .dbiterr(), + .dout({pktout_mty_buf_out_p3[w1][x1],pktout_err_buf_out_p3[w1][x1],pktout_eop_buf_out_p3[w1][x1],pktout_val_buf_out_p3[w1][x1],pktout_data_buf_out_p3[w1][x1]}), + .empty(unseg_out_buf1_empty_3[w1][x1]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_3[w1][x1]), + .rd_data_count(), + .rd_rst_busy(unseg_out_rd_rst_busy_3[w1][x1]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_out_wr_rst_busy_3[w1][x1]), + .din({pktout_mty_buf_in_p3[w1][x1],pktout_err_buf_in_p3[w1][x1],pktout_eop_buf_in_p3[w1][x1],pktout_val_buf_in_p3[w1][x1],pktout_data_buf_in_p3[w1][x1]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en3 & !outbuff_pfull & !unseg_out_data_valid_3[w1][x1]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en3[w1] & !unseg_out_wr_rst_busy_3[w1][x1]) + ); + + end + assign port_unseg_out_pfull[w1] = (|unseg_out_buf1_pfull_0[w1]) | (|unseg_out_buf1_pfull_1[w1]) | (|unseg_out_buf1_pfull_2[w1]) | (|unseg_out_buf1_pfull_3[w1]); +end +endgenerate + +assign ports_not_rdy = &port_unseg_out_pfull; + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Packet readout / array port arbitration + +reg [1:0] outport_sel; +reg [1:0] outport_sel_1; +reg [1:0] outport_sel_2; + +wire pktout_buff_rdy; + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + rd_en0 <= 1'b0; + rd_en1 <= 1'b0; + rd_en2 <= 1'b0; + rd_en3 <= 1'b0; + outport_sel <= 2'b00; + outport_sel_1 <= 2'b00; + outport_sel_2 <= 2'b00; + end else if (!outbuff_pfull) begin + rd_en0 <= 1'b0; + rd_en1 <= 1'b0; + rd_en2 <= 1'b0; + rd_en3 <= 1'b0; + outport_sel_1 <= outport_sel; + outport_sel_2 <= outport_sel_1; + if (outport_sel == 2'b11) begin + rd_en0 <= 1'b0; + rd_en1 <= 1'b0; + rd_en2 <= 1'b0; + if (!(|unseg_out_buf1_empty_3[0]) && !(|unseg_out_rd_rst_busy_3[0])) begin + rd_en3 <= 1'b1; + outport_sel <= outport_sel+1; + end else begin + rd_en3 <= 1'b0; + outport_sel <= outport_sel; + end + end else if (outport_sel == 2'b10) begin + rd_en0 <= 1'b0; + rd_en1 <= 1'b0; + rd_en3 <= 1'b0; + if (!(|unseg_out_buf1_empty_2[0]) && !(|unseg_out_rd_rst_busy_2[0])) begin + rd_en2 <= 1'b1; + outport_sel <= outport_sel+1; + end else begin + rd_en2 <= 1'b0; + outport_sel <= outport_sel; + end + end else if (outport_sel == 2'b01) begin + rd_en0 <= 1'b0; + rd_en2 <= 1'b0; + rd_en3 <= 1'b0; + if (!(|unseg_out_buf1_empty_1[0]) && !(|unseg_out_rd_rst_busy_1[0])) begin + rd_en1 <= 1'b1; + outport_sel <= outport_sel+1; + end else begin + rd_en1 <= 1'b0; + outport_sel <= outport_sel; + end + end else begin + rd_en1 <= 1'b0; + rd_en2 <= 1'b0; + rd_en3 <= 1'b0; + if (!(|unseg_out_buf1_empty_0[0]) && !(|unseg_out_rd_rst_busy_0[0])) begin + rd_en0 <= 1'b1; + outport_sel <= outport_sel+1; + end else begin + rd_en0 <= 1'b0; + outport_sel <= outport_sel; + end + end + end +end + +genvar z1, z2; + +generate +for (z1=0; z1<`num_axis_ports; z1=z1+1) begin : packetout_mux + for (z2=0; z2<(pkt_array_depth/2); z2=z2+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_val_out_0[z1][z2] <= 1'b0; + pkt_mty_out_0[z1][z2] <= {seg_mty_w{1'b1}}; + pkt_eop_out_0[z1][z2] <= 1'b0; + pkt_err_out_0[z1][z2] <= 1'b0; + end else begin + pkt_val_out_0[z1][z2] <= 1'b0; + if (outport_sel_2 == 2'b11) begin + pkt_val_out_0[z1][z2] <= pktout_val_buf_out_p3[z1][z2] & unseg_out_data_valid_3[z1][z2]; + pkt_mty_out_0[z1][z2] <= pktout_mty_buf_out_p3[z1][z2]; + pkt_eop_out_0[z1][z2] <= pktout_eop_buf_out_p3[z1][z2]; + pkt_err_out_0[z1][z2] <= pktout_err_buf_out_p3[z1][z2]; + pkt_data_out_0[z1][z2] <= pktout_data_buf_out_p3[z1][z2]; + end else if (outport_sel_2 == 2'b10) begin + pkt_val_out_0[z1][z2] <= pktout_val_buf_out_p2[z1][z2] & unseg_out_data_valid_2[z1][z2]; + pkt_mty_out_0[z1][z2] <= pktout_mty_buf_out_p2[z1][z2]; + pkt_eop_out_0[z1][z2] <= pktout_eop_buf_out_p2[z1][z2]; + pkt_err_out_0[z1][z2] <= pktout_err_buf_out_p2[z1][z2]; + pkt_data_out_0[z1][z2] <= pktout_data_buf_out_p2[z1][z2]; + end else if (outport_sel_2 == 2'b01) begin + pkt_val_out_0[z1][z2] <= pktout_val_buf_out_p1[z1][z2] & unseg_out_data_valid_1[z1][z2]; + pkt_mty_out_0[z1][z2] <= pktout_mty_buf_out_p1[z1][z2]; + pkt_eop_out_0[z1][z2] <= pktout_eop_buf_out_p1[z1][z2]; + pkt_err_out_0[z1][z2] <= pktout_err_buf_out_p1[z1][z2]; + pkt_data_out_0[z1][z2] <= pktout_data_buf_out_p1[z1][z2]; + end else begin + pkt_val_out_0[z1][z2] <= pktout_val_buf_out_p0[z1][z2] & unseg_out_data_valid_0[z1][z2]; + pkt_mty_out_0[z1][z2] <= pktout_mty_buf_out_p0[z1][z2]; + pkt_eop_out_0[z1][z2] <= pktout_eop_buf_out_p0[z1][z2]; + pkt_err_out_0[z1][z2] <= pktout_err_buf_out_p0[z1][z2]; + pkt_data_out_0[z1][z2] <= pktout_data_buf_out_p0[z1][z2]; + end + end + end + end +end +endgenerate + +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Packet segments to axi stream conversion (each segments as independant streams) + +integer a, b; +reg [`num_axis_ports-1:0] eop_flag; + +generate +always @ (posedge aclk_axis_unseg) begin : packet_to_axi_stream + if (!aresetn_axis_unseg) begin + for (a=0; a<`num_axis_ports; a=a+1) begin + eop_flag[a] = 0; + for (b=0; b<(pkt_array_depth/2); b=b+1) begin + pkt_tvalid[a][b] <= 1'b0; + pkt_tkeep[a][b] <= {(`segment_width/8){1'b0}}; + pkt_tlast[a][b] <= 1'b0; + pkt_tuser[a][b] <= 1'b0; + end + end + end else begin + for (a=0; a<`num_axis_ports; a=a+1) begin + eop_flag[a] = 0; + for (b=0; b<(pkt_array_depth/2); b=b+1) begin + pkt_tvalid[a][b] <= pkt_val_out_0[a][b]; + pkt_tdata[a][b] <= pkt_data_out_0[a][b]; + pkt_tlast[a][b] <= pkt_eop_out_0[a][b]; + pkt_tuser[a][b] <= pkt_err_out_0[a][b]; + pkt_tkeep[a][b] <= {(`segment_width/8){1'b0}}; + if (eop_flag[a]) + pkt_tkeep[a][b] <= {(`segment_width/8){1'b0}}; + else begin + pkt_tkeep[a][b] <= (2**((2**(seg_mty_w)) - pkt_mty_out_0[a][b]))-1; + if (pkt_eop_out_0[a][b]) + eop_flag[a] = 1; + else + eop_flag[a] = 0; + end + end + end + end +end +endgenerate + +//----------------- Combine to single axi stream + +genvar c, d; +generate +for (c=0; c<`num_axis_ports; c=c+1) begin : axi_stream_combine + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + axis_tvalid_buf_in[c] <= 1'b0; + axis_tlast_buf_in[c] <= 1'b0; + axis_tuser_buf_in[c] <= 1'b0; + end else begin + if (axis_tready_buf_in[c]) begin + axis_tvalid_buf_in[c] <= | pkt_tvalid[c]; + axis_tlast_buf_in[c] <= | pkt_tlast[c]; + axis_tuser_buf_in[c] <= | pkt_tuser[c]; + end + end + end + for (d=0; d<(pkt_array_depth/2); d=d+1) begin + always @ (posedge aclk_axis_unseg) begin + axis_tdata_buf_in[c][(`segment_width+(`segment_width*d))-1:(`segment_width*d)] <= pkt_tdata[c][d]; + axis_tkeep_buf_in[c][((`segment_width/8)+((`segment_width/8)*d))-1:((`segment_width/8)*d)] <= pkt_tkeep[c][d]; + end + end +end +endgenerate + +//----------------- Output buffer + +wire [(`segment_width*(pkt_array_depth/2))-1:0] axis_tdata_buf_out [`num_axis_ports-1:0]; +wire [((`segment_width/8)*(pkt_array_depth/2))-1:0] axis_tkeep_buf_out [`num_axis_ports-1:0]; +wire [`num_axis_ports-1:0] axis_tvalid_buf_out; +wire [`num_axis_ports-1:0] axis_tlast_buf_out; +wire [`num_axis_ports-1:0] axis_tuser_buf_out; +wire [`num_axis_ports-1:0] axis_tready_buf_out; +wire [`num_axis_ports-1:0] axis_out_buff_pfull; + +genvar e; + +generate +for (e=0; e<`num_axis_ports; e=e+1) begin : axis_out_buffer + xpm_fifo_axis #( + .CASCADE_HEIGHT(0), + .CDC_SYNC_STAGES(3), + .CLOCKING_MODE("common_clock"), + .ECC_MODE("no_ecc"), + .FIFO_DEPTH(out_buff_depth), + .FIFO_MEMORY_TYPE("auto"), + .PACKET_FIFO("true"), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(out_buff_depth-5), + .RD_DATA_COUNT_WIDTH(1), + .RELATED_CLOCKS(0), + .SIM_ASSERT_CHK(0), + .TDATA_WIDTH((pkt_array_depth/2)*`segment_width), + .TDEST_WIDTH(1), + .TID_WIDTH(1), + .TUSER_WIDTH(1), + .USE_ADV_FEATURES("0003"), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_axis_unseg_out ( + .m_aclk(aclk_axis_unseg), + .m_axis_tready(axis_tready_buf_out[e]), + .m_axis_tdata(axis_tdata_buf_out[e]), + .m_axis_tkeep(axis_tkeep_buf_out[e]), + .m_axis_tlast(axis_tlast_buf_out[e]), + .m_axis_tuser(axis_tuser_buf_out[e]), + .m_axis_tvalid(axis_tvalid_buf_out[e]), + .s_aclk(aclk_axis_unseg), + .s_aresetn(aresetn_axis_unseg), + .prog_full_axis(axis_out_buff_pfull[e]), + .injectdbiterr_axis(1'b0), + .injectsbiterr_axis(1'b0), + .s_axis_tready(axis_tready_buf_in[e]), + .s_axis_tdata(axis_tdata_buf_in[e]), + .s_axis_tkeep(axis_tkeep_buf_in[e]), + .s_axis_tlast(axis_tlast_buf_in[e]), + .s_axis_tuser(axis_tuser_buf_in[e]), + .s_axis_tvalid(axis_tvalid_buf_in[e]) + ); +end +endgenerate + +assign outbuff_pfull = axis_out_buff_pfull; + +assign m_axis0_tdata = axis_tdata_buf_out[0]; +assign m_axis0_tkeep = axis_tkeep_buf_out[0]; +assign m_axis0_tlast = axis_tlast_buf_out[0]; +assign m_axis0_tuser = axis_tuser_buf_out[0]; +assign m_axis0_tvalid = axis_tvalid_buf_out[0]; +assign axis_tready_buf_out[0] = m_axis0_tready; + +`ifdef en_axis1 +assign m_axis1_tdata = axis_tdata_buf_out[1]; +assign m_axis1_tkeep = axis_tkeep_buf_out[1]; +assign m_axis1_tlast = axis_tlast_buf_out[1]; +assign m_axis1_tuser = axis_tuser_buf_out[1]; +assign m_axis1_tvalid = axis_tvalid_buf_out[1]; +assign axis_tready_buf_out[1] = m_axis1_tready; +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Port Statistics + +`ifdef statistics_en + localparam statistics_en = 1; +`else + localparam statistics_en = 0; +`endif + +generate + +if (statistics_en) begin + +//----------------- Input packet count + +reg [63:0] segment_pkt_cnt [`num_segments-1:0]; +reg [63:0] segment_err_cnt [`num_segments-1:0]; +reg [63:0] segment_byte_cnt [`num_segments-1:0]; +wire [($clog2(`segment_width/8)):0] segment_validbytes [`num_segments-1:0]; +reg [63:0] total_pktin_cnt; +reg [63:0] total_err_pktin_cnt; +reg [63:0] total_pktin_byte_cnt; + +genvar ab; + +for (ab=0; ab<`num_segments; ab=ab+1) begin + mty_to_validbytes u_mty_to_valbytes + ( + .mty_in(seg2unseg_mty[ab]), + .valid_bytes_out(segment_validbytes[ab]) + ); +end + +genvar cd; + +for (cd=0; cd<`num_segments; cd=cd+1) begin + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_byte_cnt[cd] <= 'd0; + else if (seg2unseg_val[cd]) + segment_byte_cnt[cd] <= segment_byte_cnt[cd] + segment_validbytes[cd]; + end +end + +integer ef; + +always @ (*) begin + total_pktin_byte_cnt = 'd0; + for (ef=0; ef<`num_segments; ef=ef+1) begin + total_pktin_byte_cnt = total_pktin_byte_cnt + segment_byte_cnt[ef]; + end +end + +genvar gh; + +for (gh=0; gh<`num_segments; gh=gh+1) begin + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_pkt_cnt[gh] <= 'd0; + else if (seg2unseg_val[gh] && seg2unseg_eop[gh]) + segment_pkt_cnt[gh] <= segment_pkt_cnt[gh] + 1; + end + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_err_cnt[gh] <= 'd0; + else if (seg2unseg_val[gh] && seg2unseg_eop[gh] && seg2unseg_err[gh]) + segment_err_cnt[gh] <= segment_err_cnt[gh] + 1; + end +end + +integer ij; + +always @ (*) begin + total_pktin_cnt = 'd0; + total_err_pktin_cnt = 'd0; + for (ij=0; ij<`num_segments; ij=ij+1) begin + total_pktin_cnt = total_pktin_cnt + segment_pkt_cnt[ij]; + total_err_pktin_cnt = total_err_pktin_cnt + segment_err_cnt[ij]; + end +end + +//----------------- Output packet count + +reg [63:0] port_pkt_out_cnt [`num_axis_ports-1:0]; +reg [63:0] port_err_out_cnt [`num_axis_ports-1:0]; +reg [63:0] port_pkt_byte_cnt [`num_axis_ports-1:0]; +reg [63:0] total_pktout_cnt; +reg [63:0] total_err_pktout_cnt; +reg [63:0] total_pktout_byte_cnt; + +wire [($clog2(`unseg_axis_w/8)):0] port_valid_bytes [`num_axis_ports-1:0]; + +genvar g; +for (g=0; g<`num_axis_ports; g=g+1) begin + tkeep_to_validbytes u_tkeep_to_valbytes + ( + .tkeep_in(axis_tkeep_buf_out[g]), + .valid_bytes_out(port_valid_bytes[g]) + ); +end + +genvar i; +for (i=0; i<`num_axis_ports; i=i+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_pkt_out_cnt[i] <= 'd0; + else + if (axis_tvalid_buf_out[i] && axis_tready_buf_out[i] && axis_tlast_buf_out[i]) + port_pkt_out_cnt[i] <= port_pkt_out_cnt[i] + 'd1; + end + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_err_out_cnt[i] <= 'd0; + else + if (axis_tvalid_buf_out[i] && axis_tready_buf_out[i] && axis_tlast_buf_out[i] && axis_tuser_buf_out[i]) + port_err_out_cnt[i] <= port_err_out_cnt[i] + 'd1; + end +end + +genvar j; +for (j=0; j<`num_axis_ports; j=j+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_pkt_byte_cnt[j] <= 'd0; + else + if (axis_tvalid_buf_out[j] && axis_tready_buf_out[j]) + port_pkt_byte_cnt[j] <= port_pkt_byte_cnt[j] + port_valid_bytes[j]; + end +end + +integer k; +always @ (*) begin + total_pktout_cnt = 'd0; + total_err_pktout_cnt = 'd0; + total_pktout_byte_cnt = 'd0; + for (k=0; k<`num_axis_ports; k=k+1) begin + total_pktout_cnt = total_pktout_cnt + port_pkt_out_cnt[k]; + total_err_pktout_cnt = total_err_pktout_cnt + port_err_out_cnt[k]; + total_pktout_byte_cnt = total_pktout_byte_cnt + port_pkt_byte_cnt[k]; + end +end + +assign total_pkt_in_cnt = total_pktin_cnt; +assign total_err_pkt_in_cnt = total_err_pktin_cnt; +assign total_pkt_in_byte_cnt = total_pktin_byte_cnt; +assign total_pkt_out_cnt = total_pktout_cnt; +assign total_err_pkt_out_cnt = total_err_pktout_cnt; +assign total_pkt_out_byte_cnt = total_pktout_byte_cnt; +`ifdef en_axis1 +assign p1_pkt_out_cnt = port_pkt_out_cnt[1]; +assign p1_err_pkt_out_cnt = port_err_out_cnt[1]; +assign p1_pkt_out_byte_cnt = port_pkt_byte_cnt[1]; +assign p0_pkt_out_cnt = port_pkt_out_cnt[0]; +assign p0_err_pkt_out_cnt = port_err_out_cnt[0]; +assign p0_pkt_out_byte_cnt = port_pkt_byte_cnt[0]; +`endif + +end + +endgenerate + +`ifdef debug_en + +reg [`num_axis_ports-1:0] err_boken_pkt, err_boken_pkt_tlst; + +genvar k0; +integer k1; + +generate + +for (k0=0; k0<`num_axis_ports; k0=k0+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + err_boken_pkt[k0] <= 1'b0; + else + err_boken_pkt[k0] <= axis_tvalid_buf_out[k0] & axis_tready_buf_out[k0] & ~axis_tlast_buf_out[k0] & ~(&axis_tkeep_buf_out[k0]); + end +end + +for (k0=0; k0<`num_axis_ports; k0=k0+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + err_boken_pkt_tlst[k0] = 1'b0; + else begin + err_boken_pkt_tlst[k0] = 1'b0; + if (axis_tlast_buf_out[k0]) begin + if (!err_boken_pkt_tlst[k0]) begin + for (k1=0; k1<(`unseg_axis_w/8)-2; k1=k1+1) begin + if (axis_tkeep_buf_out[k0][k1+1] && !axis_tkeep_buf_out[k0][k1]) + err_boken_pkt_tlst[k0] = 1'b1; + else + err_boken_pkt_tlst[k0] = 1'b0; + end + end + end else + err_boken_pkt_tlst[k0] = 1'b0; + end + end +end + + +endgenerate + +assign error_broken_packet_out = (|err_boken_pkt) | (|(err_boken_pkt_tlst & axis_tlast_buf_out & axis_tvalid_buf_out & axis_tready_buf_out)); + +`endif + +endmodule + +//----------------------------------------------------------------------------------------------------------------------- + +module tkeep_to_validbytes + ( + input [(`unseg_axis_w/8)-1:0] tkeep_in, + output wire [($clog2(`unseg_axis_w/8)):0] valid_bytes_out + ); + +integer i; + +reg [($clog2(`unseg_axis_w/8)):0] valid_bytes; + +always @ (tkeep_in) begin + valid_bytes = 0; + for (i=0; i<(`unseg_axis_w/8); i=i+1) + valid_bytes = valid_bytes + tkeep_in[i]; +end + +assign valid_bytes_out = valid_bytes; + +endmodule + +//----------------------------------------------------------------------------------------------------------------------- + +module mty_to_validbytes + ( + input [($clog2(`segment_width/8))-1:0] mty_in, + output wire [($clog2(`segment_width/8)):0] valid_bytes_out + ); + +integer i; + +reg [($clog2(`segment_width/8)):0] valid_bytes; + +always @ (mty_in) begin + valid_bytes <= (2**($clog2(`segment_width/8))) - mty_in; +end + +assign valid_bytes_out = valid_bytes; + +endmodule + + +//######################################################################################################################## + +//------------------------------------ AXIS Unsegmented to Segmented stream Converter ------------------------------------ + +module axis_unseg_to_seg_converter + ( + // AXIS Segment to Unsegment converter ports + // Clock & Resets + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_seg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET aresetn_axis_seg_in" *) + input aclk_axis_seg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_seg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_seg_in, + `ifdef independant_clk + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_unseg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_pktout, ASSOCIATED_RESET aresetn_axis_unseg_in" *) + input aclk_axis_unseg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_unseg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_unseg_in, + `endif + // Segmented interface + // port0 is active for all valid configurations + // Segment 0 input + output Unseg2SegEna0_out, + output [`segment_width-1:0] Unseg2SegDat0_out, + output Unseg2SegSop0_out, + output Unseg2SegEop0_out, + output Unseg2SegErr0_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty0_out, + // Segment 1 input + output Unseg2SegEna1_out, + output [`segment_width-1:0] Unseg2SegDat1_out, + output Unseg2SegSop1_out, + output Unseg2SegEop1_out, + output Unseg2SegErr1_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty1_out, + `ifdef en_port1 + // Segment 2 input + output Unseg2SegEna2_out, + output [`segment_width-1:0] Unseg2SegDat2_out, + output Unseg2SegSop2_out, + output Unseg2SegEop2_out, + output Unseg2SegErr2_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty2_out, + // Segment 3 input + output Unseg2SegEna3_out, + output [`segment_width-1:0] Unseg2SegDat3_out, + output Unseg2SegSop3_out, + output Unseg2SegEop3_out, + output Unseg2SegErr3_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty3_out, + `endif + `ifdef en_port2 + // Segment 4 input + output Unseg2SegEna4_out, + output [`segment_width-1:0] Unseg2SegDat4_out, + output Unseg2SegSop4_out, + output Unseg2SegEop4_out, + output Unseg2SegErr4_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty4_out, + // Segment 5 input + output Unseg2SegEna5_out, + output [`segment_width-1:0] Unseg2SegDat5_out, + output Unseg2SegSop5_out, + output Unseg2SegEop5_out, + output Unseg2SegErr5_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty5_out, + `endif + `ifdef en_port3 + // Segment 6 input + output Unseg2SegEna6_out, + output [`segment_width-1:0] Unseg2SegDat6_out, + output Unseg2SegSop6_out, + output Unseg2SegEop6_out, + output Unseg2SegErr6_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty6_out, + // Segment 7 input + output Unseg2SegEna7_out, + output [`segment_width-1:0] Unseg2SegDat7_out, + output Unseg2SegSop7_out, + output Unseg2SegEop7_out, + output Unseg2SegErr7_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty7_out, + `endif + + // Packet output interface - Unsegmented AXI Stream + // axis0 is active for all valid configurations + // unsegmented AXIS0 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TDATA" *) + input [`unseg_axis_w-1:0] s_axis0_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TKEEP" *) + input [(`unseg_axis_w/8)-1:0] s_axis0_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TLAST" *) + input s_axis0_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TUSER" *) + input s_axis0_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TVALID" *) + input s_axis0_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TREADY" *) + output s_axis0_tready, + + `ifdef en_axis1 + // unsegmented AXIS1 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TDATA" *) + input [`unseg_axis_w-1:0] s_axis1_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TKEEP" *) + input [(`unseg_axis_w/8)-1:0] s_axis1_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TLAST" *) + input s_axis1_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TUSER" *) + input s_axis1_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TVALID" *) + input s_axis1_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TREADY" *) + output s_axis1_tready, + `endif + + // Statistics + `ifdef debug_en + output wire error_missing_sop, + output wire error_broken_pkt_out, + output wire error_broken_pkt_in, + `endif + `ifdef statistics_en + `ifdef en_axis1 + output wire [63: 0] p1_pkt_in_cnt, + output wire [63: 0] p1_err_pkt_in_cnt, + output wire [63: 0] p1_pkt_in_byte_cnt, + output wire [63: 0] p0_pkt_in_cnt, + output wire [63: 0] p0_err_pkt_in_cnt, + output wire [63: 0] p0_pkt_in_byte_cnt, + `endif + output wire [63: 0] total_pkt_in_cnt, + output wire [63: 0] total_err_pkt_in_cnt, + output wire [63: 0] total_pkt_in_byte_cnt, + output wire [63: 0] total_pkt_out_cnt, + output wire [63: 0] total_err_pkt_out_cnt, + output wire [63: 0] total_pkt_out_byte_cnt, + `endif + input wire tx_axis_tready_in, + output wire tx_axis_tvalid_out + ); + +//----------------------------------------------------------------------------------------------------------------------- + +localparam P_MARK_DEBUG = "false"; + +localparam seg_mty_w = $clog2(`segment_width/8); +`ifdef data_rate_200 +localparam pkt_array_depth = `pktarray_depth/2; +`else +localparam pkt_array_depth = `pktarray_depth; +`endif +localparam local_buff_depth = 16; +localparam io_buff_depth = 32; + +// Packet block size +// Block size should be sufficient to hold atleast one complete packet of the maximum expected size. +// Also block size should be a power of 2 + +`ifdef data_rate_200 +localparam pkt_blk_depth = 512; +localparam input_buffer_depth = pkt_blk_depth; +localparam output_buffer_depth = input_buffer_depth*8*`num_axis_ports; +`else +localparam pkt_blk_depth = 512; +localparam input_buffer_depth = pkt_blk_depth; +localparam output_buffer_depth = input_buffer_depth*4*`num_axis_ports; +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +wire aclk_axis_unseg; +wire aresetn_axis_unseg; + +`ifdef independant_clk + assign aclk_axis_unseg = aclk_axis_unseg_in; + assign aresetn_axis_unseg = aresetn_axis_unseg_in; +`else + assign aclk_axis_unseg = aclk_axis_seg_in; + assign aresetn_axis_unseg = aresetn_axis_seg_in; +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Input Stream buffer + +wire [`unseg_axis_w-1:0] s_axis_tdata_in [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/8)-1:0] s_axis_tkeep_in [`num_axis_ports-1:0]; +wire [`num_axis_ports-1:0] s_axis_tvalid_in; +wire [`num_axis_ports-1:0] s_axis_tlast_in; +wire [`num_axis_ports-1:0] s_axis_tuser_in; +wire [`num_axis_ports-1:0] s_axis_tready_in; + +wire axis_pkt_blk_rdy_flg; +wire axis_pkt_blk_rdy_p; +reg axis_pkt_blk_rdy_flg_clr; + +assign s_axis_tdata_in[0] = s_axis0_tdata; +assign s_axis_tkeep_in[0] = s_axis0_tkeep; +assign s_axis_tvalid_in[0] = s_axis0_tvalid & (~axis_pkt_blk_rdy_flg); +assign s_axis_tlast_in[0] = s_axis0_tlast; +assign s_axis_tuser_in[0] = s_axis0_tuser; +assign s_axis0_tready = s_axis_tready_in[0] & (~axis_pkt_blk_rdy_flg); + +`ifdef en_axis1 +assign s_axis_tdata_in[1] = s_axis1_tdata; +assign s_axis_tkeep_in[1] = s_axis1_tkeep; +assign s_axis_tvalid_in[1] = s_axis1_tvalid & (~axis_pkt_blk_rdy_flg); +assign s_axis_tlast_in[1] = s_axis1_tlast; +assign s_axis_tuser_in[1] = s_axis1_tuser; +assign s_axis1_tready = s_axis_tready_in[1] & (~axis_pkt_blk_rdy_flg); +`endif + +wire [`unseg_axis_w-1:0] axis_tdata_c [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/8)-1:0] axis_tkeep_c [`num_axis_ports-1:0]; +wire [`num_axis_ports-1:0] axis_tvalid_c; +wire [`num_axis_ports-1:0] axis_tlast_c; +wire [`num_axis_ports-1:0] axis_tuser_c; +wire [`num_axis_ports-1:0] axis_tready_c; + +wire [`num_axis_ports-1:0] axis_in_buff_pfull; +wire [`num_axis_ports-1:0] axis_in_buff_pempty; +wire [`num_axis_ports-1:0] almost_full_axis; +wire [`num_axis_ports-1:0] almost_empty_axis; + +wire [`num_axis_ports-1:0] axis_inbuff_pfull; +wire [`num_axis_ports-1:0] axis_inbuff_aempty; + +wire [$clog2(input_buffer_depth):0] axis_inbuff_wrcnt [`num_axis_ports-1:0]; + +`ifdef debug_en + +reg [`num_axis_ports-1:0] err_boken_pkt, err_boken_pkt_tlst; + +genvar a1; +integer a2; + +generate + +for (a1=0; a1<`num_axis_ports; a1=a1+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + err_boken_pkt[a1] <= 1'b0; + else + err_boken_pkt[a1] <= s_axis_tvalid_in[a1] & s_axis_tready_in[a1] & ~axis_pkt_blk_rdy_flg & ~s_axis_tlast_in[a1] & ~(&s_axis_tkeep_in[a1]); + end +end + +for (a1=0; a1<`num_axis_ports; a1=a1+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + err_boken_pkt_tlst[a1] = 1'b0; + else begin + err_boken_pkt_tlst[a1] = 1'b0; + if (s_axis_tlast_in[a1]) begin + if (!err_boken_pkt_tlst[a1]) begin + for (a2=0; a2<(`unseg_axis_w/8)-2; a2=a2+1) begin + if (s_axis_tkeep_in[a1][a2+1] && !s_axis_tkeep_in[a1][a2]) + err_boken_pkt_tlst[a1] = 1'b1; + else + err_boken_pkt_tlst[a1] = 1'b0; + end + end + end else + err_boken_pkt_tlst[a1] = 1'b0; + end + end +end + + +endgenerate + +assign error_broken_pkt_in = (|err_boken_pkt) | (|(err_boken_pkt_tlst & s_axis_tvalid_in & s_axis_tready_in & ~axis_pkt_blk_rdy_flg)); + +`endif + +genvar a; +generate + for (a=0; a<`num_axis_ports; a=a+1) begin + assign axis_inbuff_pfull[a] = axis_in_buff_pfull[a]; + assign axis_inbuff_aempty[a] = almost_empty_axis[a]; + xpm_fifo_axis #( + .CASCADE_HEIGHT(0), + .CDC_SYNC_STAGES(3), + .CLOCKING_MODE("common_clock"), + .ECC_MODE("no_ecc"), + .FIFO_DEPTH(input_buffer_depth), + .FIFO_MEMORY_TYPE("auto"), + .PACKET_FIFO("true"), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(input_buffer_depth-5), + .RD_DATA_COUNT_WIDTH($clog2(input_buffer_depth)+1), + .RELATED_CLOCKS(0), + .SIM_ASSERT_CHK(0), + .TDATA_WIDTH(`unseg_axis_w), + .TDEST_WIDTH(1), + .TID_WIDTH(1), + .TUSER_WIDTH(1), + .USE_ADV_FEATURES("0803"), + .WR_DATA_COUNT_WIDTH($clog2(input_buffer_depth)+1) + ) + xpm_fifo_axis_unseg_in ( + .m_aclk(aclk_axis_unseg), + .m_axis_tready(axis_tready_c[a]), + .m_axis_tdata(axis_tdata_c[a]), + .m_axis_tkeep(axis_tkeep_c[a]), + .m_axis_tlast(axis_tlast_c[a]), + .m_axis_tuser(axis_tuser_c[a]), + .m_axis_tvalid(axis_tvalid_c[a]), + .s_aclk(aclk_axis_unseg), + .s_aresetn(aresetn_axis_unseg), + .prog_full_axis(axis_in_buff_pfull[a]), + .prog_empty_axis(axis_in_buff_pempty[a]), + .almost_full_axis(almost_full_axis[a]), + .almost_empty_axis(almost_empty_axis[a]), + .s_axis_tready(s_axis_tready_in[a]), + .s_axis_tdata(s_axis_tdata_in[a]), + .s_axis_tkeep(s_axis_tkeep_in[a]), + .s_axis_tlast(s_axis_tlast_in[a]), + .s_axis_tuser(s_axis_tuser_in[a]), + .s_axis_tvalid(s_axis_tvalid_in[a]), + .wr_data_count_axis(axis_inbuff_wrcnt[a]) + ); + end +endgenerate + +wire [`segment_width-1:0] axis_tdata_buff [`num_axis_ports-1:0][(`unseg_axis_w/`segment_width)-1:0]; +wire [(`segment_width/8)-1:0] axis_tkeep_buff [`num_axis_ports-1:0][(`unseg_axis_w/`segment_width)-1:0]; +wire [`num_axis_ports-1:0] axis_tvalid_buff; +wire [`num_axis_ports-1:0] axis_tlast_buff; +wire [`num_axis_ports-1:0] axis_tuser_buff; +wire [`num_axis_ports-1:0] axis_tready_buff; + +genvar aa, ab; +generate + for (aa=0; aa<`num_axis_ports; aa=aa+1) begin + assign axis_tready_c[aa] = axis_tready_buff[aa]; + assign axis_tvalid_buff[aa] = axis_tvalid_c[aa]; + assign axis_tlast_buff[aa] = axis_tlast_c[aa]; + assign axis_tuser_buff[aa] = axis_tuser_c[aa]; + for (ab=0; ab<(`unseg_axis_w/`segment_width); ab=ab+1) begin + assign axis_tdata_buff[aa][ab] = axis_tdata_c[aa][((ab+1)*`segment_width)-1:(ab*`segment_width)]; + assign axis_tkeep_buff[aa][ab] = axis_tkeep_c[aa][((ab+1)*(`segment_width/8))-1:(ab*(`segment_width/8))]; + end + end +endgenerate + +//----------------- Read packets as a block + +reg [$clog2(input_buffer_depth):0] axis_pkt_in_cnt [`num_axis_ports-1:0]; +reg [$clog2(input_buffer_depth)+1:0] num_pkt_to_rd_reg [`num_axis_ports-1:0]; +reg axis_in_buff_pfull_q, axis_in_buff_pfull_qq; + +wire out_buff_afull; +wire out_buff_pfull; + +genvar b; +for (b=0; b<`num_axis_ports; b=b+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + axis_pkt_in_cnt[b] <= 'd0; + else if (axis_pkt_blk_rdy_p) + axis_pkt_in_cnt[b] <= 'd0; + else if (s_axis_tvalid_in[b] && s_axis_tready_in[b] && s_axis_tlast_in[b]) + axis_pkt_in_cnt[b] <= axis_pkt_in_cnt[b] + 'd1; + end +end + +reg [$clog2(pkt_blk_depth*4):0] axis_pkt_flush_cnt; + +`ifdef en_axis1 + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + axis_pkt_flush_cnt <= 'd0; + else if (axis_pkt_blk_rdy_p) + axis_pkt_flush_cnt <= 'd0; + else if ((|axis_pkt_in_cnt[1] || |axis_pkt_in_cnt[0]) && !out_buff_pfull) + axis_pkt_flush_cnt <= axis_pkt_flush_cnt + 1; + else + axis_pkt_flush_cnt <= 'd0; +end + +`else + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + axis_pkt_flush_cnt <= 'd0; + else if (axis_pkt_blk_rdy_p) + axis_pkt_flush_cnt <= 'd0; + else if (|axis_pkt_in_cnt[0] && !out_buff_pfull) + axis_pkt_flush_cnt <= axis_pkt_flush_cnt + 1; + else + axis_pkt_flush_cnt <= 'd0; +end + +`endif + +reg [`num_axis_ports-1:0] axis_pkt_blk_rd; +reg unseg_pkt_blk_rd; + +assign axis_pkt_blk_rdy_flg = axis_in_buff_pfull_q; + +wire [`num_axis_ports-1:0] unseg_buff_empty; + +always @ (posedge aclk_axis_unseg) begin + axis_pkt_blk_rdy_flg_clr <= axis_pkt_blk_rdy_p; + axis_in_buff_pfull_qq <= axis_in_buff_pfull_q; + if (!aresetn_axis_unseg) + axis_in_buff_pfull_q <= 1'b0; + else if (axis_pkt_blk_rdy_flg_clr | (|axis_pkt_blk_rd)) + axis_in_buff_pfull_q <= 1'b0; + else + axis_in_buff_pfull_q <= ((~(&axis_inbuff_aempty) & |axis_inbuff_pfull) | axis_pkt_flush_cnt[$clog2(pkt_blk_depth*4)]) & ~out_buff_pfull & (&unseg_buff_empty); +end + +assign axis_pkt_blk_rdy_p = axis_in_buff_pfull_q & ~axis_in_buff_pfull_qq; + +reg axis_pkt_blk_rdy_rp_q; + +always @ (posedge aclk_axis_unseg) begin + axis_pkt_blk_rdy_rp_q <= axis_pkt_blk_rdy_p; +end + +reg [$clog2(input_buffer_depth):0] axis_pkt_rd_cnt [`num_axis_ports-1:0]; +wire [`num_axis_ports-1:0] axis_pkt_blk_rd_end; + +genvar b0; +generate +for (b0=0; b0<`num_axis_ports; b0=b0+1) begin +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + num_pkt_to_rd_reg[b0] <= 'd0; + axis_pkt_blk_rd[b0] <= 1'b0; + end else if (axis_pkt_blk_rdy_p) begin + num_pkt_to_rd_reg[b0] <= axis_pkt_in_cnt[b0]; + axis_pkt_blk_rd[b0] <= |axis_pkt_in_cnt[b0]; + end else begin + num_pkt_to_rd_reg[b0] <= num_pkt_to_rd_reg[b0]; + if (axis_pkt_blk_rd_end[b0]) + axis_pkt_blk_rd[b0] <= 1'b0; + else + axis_pkt_blk_rd[b0] <= axis_pkt_blk_rd[b0]; + end +end +end +endgenerate + +genvar b1; +generate +for (b1=0; b1<`num_axis_ports; b1=b1+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + axis_pkt_rd_cnt[b1] <= 'd0; + else if (axis_pkt_blk_rd_end[b1]) + axis_pkt_rd_cnt[b1] <= 'd0; + else if (axis_tvalid_buff[b1] && axis_tready_buff[b1] && axis_tlast_buff[b1]) + axis_pkt_rd_cnt[b1] <= axis_pkt_rd_cnt[b1] + 'd1; + end +end +endgenerate + +genvar b3; +generate +for (b3=0; b3<`num_axis_ports; b3=b3+1) begin + assign axis_pkt_blk_rd_end[b3] = (axis_pkt_blk_rd[b3] && axis_pkt_rd_cnt[b3] >= num_pkt_to_rd_reg[b3]) ? 1'b1 : 1'b0; +end + +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Stream to segment conversion + +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_sop [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_eop [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_err [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_val [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_blk_end [`num_axis_ports-1:0]; +wire [seg_mty_w-1:0] unseg_mty_c [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; +reg [seg_mty_w-1:0] unseg_mty [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; +reg [`segment_width-1:0] unseg_dat [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; + +reg [`num_axis_ports-1:0] pkt_start; + +genvar c, cc; +generate +for (c=0; c<`num_axis_ports; c=c+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + pkt_start[c] <= 1'b1; + else begin + if(axis_tvalid_buff[c] & !axis_tlast_buff[c] & axis_tready_buff[c]) + pkt_start[c] <= 1'b0; + else if (axis_tvalid_buff[c] & axis_tlast_buff[c] & axis_tready_buff[c]) + pkt_start[c] <= 1'b1; + end + unseg_sop[c][0] <= (axis_tready_buff[c] & pkt_start[c] & axis_tvalid_buff[c]); + end + for (cc=0; cc<((`unseg_axis_w/`segment_width)-1); cc=cc+1) begin + always @ (posedge aclk_axis_unseg) + unseg_sop[c][cc+1] <= 1'b0; + end +end +endgenerate + +wire tdata_available [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; + +genvar d, dd; +generate +for (d=0; d<`num_axis_ports; d=d+1) begin + for (dd=0; dd<(`unseg_axis_w/`segment_width); dd=dd+1) begin + assign tdata_available[d][dd] = |axis_tkeep_buff[d][dd] & axis_tvalid_buff[d]; + end +end +endgenerate + +genvar e, ee; +generate +for (e=0; e<`num_axis_ports; e=e+1) begin + always @ (posedge aclk_axis_unseg) begin + unseg_eop[e][(`unseg_axis_w/`segment_width)-1] <= tdata_available[e][(`unseg_axis_w/`segment_width)-1] & axis_tlast_buff[e]; + unseg_err[e][(`unseg_axis_w/`segment_width)-1] <= tdata_available[e][(`unseg_axis_w/`segment_width)-1] & axis_tlast_buff[e] & axis_tuser_buff[e]; + end + for (ee=0; ee<((`unseg_axis_w/`segment_width)-1); ee=ee+1) begin + always @ (posedge aclk_axis_unseg) begin + unseg_eop[e][ee] <= tdata_available[e][ee] & ~tdata_available[e][ee+1] & axis_tlast_buff[e]; + unseg_err[e][ee] <= tdata_available[e][ee] & ~tdata_available[e][ee+1] & axis_tlast_buff[e] & axis_tuser_buff[e]; + end + end +end +endgenerate + +genvar f, ff; +generate +for (f=0; f<`num_axis_ports; f=f+1) begin + for (ff=0; ff<((`unseg_axis_w/`segment_width)); ff=ff+1) begin + tkeep_to_mty u_tkeep_to_mty + ( + .tkeep_in(axis_tkeep_buff[f][ff]), + .mty_out(unseg_mty_c[f][ff]) + ); + always @ (posedge aclk_axis_unseg) begin + unseg_dat[f][ff] <= axis_tdata_buff[f][ff]; + unseg_val[f][ff] <= tdata_available[f][ff] & axis_tvalid_buff[f] & axis_tready_buff[f]; + unseg_mty[f][ff] <= unseg_mty_c[f][ff]; + end + end +end +endgenerate + +genvar f1, f2; +generate +for (f1=0; f1<`num_axis_ports; f1=f1+1) begin + for (f2=0; f2<((`unseg_axis_w/`segment_width)); f2=f2+1) begin + assign unseg_blk_end[f1][f2] = unseg_eop[f1][f2] & axis_pkt_blk_rd_end[f1]; + end +end +endgenerate + +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_sop_q [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_eop_q [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_err_q [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_val_q [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_blk_end_q [`num_axis_ports-1:0]; +reg [`segment_width-1:0] unseg_dat_q [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; +reg [seg_mty_w-1:0] unseg_mty_q [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; + +genvar f3, f4; +generate +for (f3=0; f3<`num_axis_ports; f3=f3+1) begin + for (f4=0; f4<((`unseg_axis_w/`segment_width)); f4=f4+1) begin + always @ (posedge aclk_axis_unseg) begin + unseg_sop_q[f3][f4] <= unseg_sop[f3][f4]; + unseg_eop_q[f3][f4] <= unseg_eop[f3][f4]; + unseg_err_q[f3][f4] <= unseg_err[f3][f4]; + unseg_dat_q[f3][f4] <= unseg_dat[f3][f4]; + unseg_val_q[f3][f4] <= unseg_val[f3][f4]; + unseg_mty_q[f3][f4] <= unseg_mty[f3][f4]; + unseg_blk_end_q[f3][f4] <= unseg_eop[f3][f4] & axis_pkt_blk_rd_end[f3]; + end + end +end +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Segment Buffer + +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_aempty [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_afull [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_pfull [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_empty [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_data_valid [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_rd_rst_busy [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_wr_rst_busy [`num_axis_ports-1:0]; + +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_sop_buf [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_eop_buf [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_err_buf [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_val_buf_c [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_val_buf [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_blk_end_buf [`num_axis_ports-1:0]; +wire [seg_mty_w-1:0] unseg_mty_buf [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; +wire [`segment_width-1:0] unseg_dat_buf [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; + +wire [`num_axis_ports-1:0] unseg_buf_wr_en; +reg [`num_axis_ports-1:0] unseg_buf_rd_en; + +wire pkt_array_buf_pfull; + +wire [`num_axis_ports-1:0] unseg_buf_rd_en_c; + +reg axis_blk_rd_q, axis_blk_rd_qq; +wire axis_blk_rd_rp; +wire unseg_pkt_blk_end; + +always @ (posedge aclk_axis_unseg) begin + axis_blk_rd_q <= |axis_pkt_blk_rd; + axis_blk_rd_qq <= axis_blk_rd_q; +end + +assign axis_blk_rd_rp = axis_blk_rd_q & ~axis_blk_rd_qq; + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + unseg_pkt_blk_rd <= 1'b0; + else if (unseg_pkt_blk_end) + unseg_pkt_blk_rd <= 1'b0; + else if (axis_blk_rd_rp) + unseg_pkt_blk_rd <= 1'b1; + else + unseg_pkt_blk_rd <= unseg_pkt_blk_rd; +end + +genvar g, gg; +generate +for (g=0; g<`num_axis_ports; g=g+1) begin + assign unseg_buf_wr_en[g] = unseg_val_q[g][0]; + assign axis_tready_buff[g] = axis_pkt_blk_rd[g] & ~axis_pkt_blk_rd_end[g] & ~(|unseg_buf_pfull[g]); + assign unseg_buff_empty[g] = &unseg_buf_empty[g]; + for (gg=0; gg<((`unseg_axis_w/`segment_width)); gg=gg+1) begin + assign unseg_val_buf[g][gg] = unseg_val_buf_c[g][gg] & unseg_buf_data_valid[g][gg]; + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(local_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(local_buff_depth-5), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+5), + .READ_MODE("fwft"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+5), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_seg_buff ( + .almost_empty(unseg_buf_aempty[g][gg]), + .almost_full(unseg_buf_afull[g][gg]), + .data_valid(unseg_buf_data_valid[g][gg]), + .dbiterr(), + .dout({unseg_blk_end_buf[g][gg],unseg_err_buf[g][gg],unseg_eop_buf[g][gg],unseg_sop_buf[g][gg],unseg_mty_buf[g][gg],unseg_val_buf_c[g][gg],unseg_dat_buf[g][gg]}), + .empty(unseg_buf_empty[g][gg]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_buf_pfull[g][gg]), + .rd_data_count(), + .rd_rst_busy(unseg_buf_rd_rst_busy[g][gg]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_buf_wr_rst_busy[g][gg]), + .din({unseg_blk_end_q[g][gg],unseg_err_q[g][gg],unseg_eop_q[g][gg],unseg_sop_q[g][gg],unseg_mty_q[g][gg],unseg_val_q[g][gg],unseg_dat_q[g][gg]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(unseg_buf_rd_en_c[g]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(unseg_buf_wr_en[g]) + ); + end +end +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----- Packet read enable generation, (read arbitration, based on packet availability in input ports) + +reg only_port1_active, only_port0_active; + +`ifdef en_axis1 // Below logic assumes max no of ports is 2 (applicable for 400G) + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + only_port0_active <= 1'b0; + else if (axis_pkt_blk_rdy_p) + if (axis_inbuff_aempty[1]) + only_port0_active <= 1'b1; + else + only_port0_active <= 1'b0; + else + only_port0_active <= only_port0_active; +end + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + only_port1_active <= 1'b0; + else if (axis_pkt_blk_rdy_p) + if (axis_inbuff_aempty[0]) + only_port1_active <= 1'b1; + else + only_port1_active <= 1'b0; + else + only_port1_active <= only_port1_active; +end + +reg pkt_port_sel; + +assign unseg_buf_rd_en_c[0] = (unseg_buf_rd_en[0] | ((|unseg_eop_buf[1] & (|unseg_val_buf[1])) & !(|unseg_buf_empty[0])) & ~pkt_array_buf_pfull); +assign unseg_buf_rd_en_c[1] = (unseg_buf_rd_en[1] | ((|unseg_eop_buf[0] & (|unseg_val_buf[0])) & !(|unseg_buf_empty[1])) & ~pkt_array_buf_pfull); + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_port_sel <= 1'b0; + unseg_buf_rd_en[0] <= 1'b0; + unseg_buf_rd_en[1] <= 1'b0; + end else if (axis_pkt_blk_rdy_rp_q) begin + if (only_port1_active) begin + pkt_port_sel <= 1'b1; + unseg_buf_rd_en[0] <= 1'b0; + unseg_buf_rd_en[1] <= 1'b0; + end else if (only_port0_active) begin + pkt_port_sel <= 1'b0; + unseg_buf_rd_en[1] <= 1'b0; + unseg_buf_rd_en[1] <= 1'b0; + end else + pkt_port_sel <= pkt_port_sel; + end else if (!pkt_array_buf_pfull) begin + if (pkt_port_sel) begin + unseg_buf_rd_en[0] <= 1'b0; + if (|unseg_eop_buf[1] && |unseg_val_buf[1]) begin + if (|unseg_buf_empty[1]) begin + unseg_buf_rd_en[0] <= 1'b1; + unseg_buf_rd_en[1] <= 1'b0; + pkt_port_sel <= 1'b0; + end else if (!(|unseg_buf_empty[0])) begin + unseg_buf_rd_en[0] <= 1'b1; + unseg_buf_rd_en[1] <= 1'b0; + pkt_port_sel <= 1'b0; + end else + unseg_buf_rd_en[1] <= 1'b1; + end else if (|unseg_eop_buf[1] && !(|unseg_buf_empty[0])) begin + unseg_buf_rd_en[0] <= 1'b1; + unseg_buf_rd_en[1] <= 1'b0; + pkt_port_sel <= 1'b0; + end else if(!(|unseg_buf_empty[1])) begin + unseg_buf_rd_en[1] <= 1'b1; + end else begin + unseg_buf_rd_en[1] <= 1'b0; + end + end else begin + unseg_buf_rd_en[1] <= 1'b0; + if (|unseg_eop_buf[0] && |unseg_val_buf[0]) begin + if (|unseg_buf_empty[0]) begin + unseg_buf_rd_en[1] <= 1'b1; + unseg_buf_rd_en[0] <= 1'b0; + pkt_port_sel <= 1'b1; + end else if (!(|unseg_buf_empty[1])) begin + unseg_buf_rd_en[1] <= 1'b1; + unseg_buf_rd_en[0] <= 1'b0; + pkt_port_sel <= 1'b1; + end else + unseg_buf_rd_en[0] <= 1'b1; + end else if (|unseg_eop_buf[0] && !(|unseg_buf_empty[1])) begin + unseg_buf_rd_en[1] <= 1'b1; + unseg_buf_rd_en[0] <= 1'b0; + pkt_port_sel <= 1'b1; + end else if(!(|unseg_buf_empty[0])) begin + unseg_buf_rd_en[0] <= 1'b1; + end else begin + unseg_buf_rd_en[0] <= 1'b0; + end + end + end +end + +`else // only one port available + +assign unseg_buf_rd_en_c[0] = unseg_buf_rd_en[0] & ~pkt_array_buf_pfull; + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + unseg_buf_rd_en[0] <= 1'b0; + else if (!pkt_array_buf_pfull) begin + if (|unseg_buf_empty[0]) + unseg_buf_rd_en[0] <= 1'b0; + else + unseg_buf_rd_en[0] <= 1'b1; + end +end + +`endif + +`ifdef en_axis1 + +reg [`segment_width-1:0] seg_data_array [pkt_array_depth-1:0]; +reg [seg_mty_w-1:0] seg_mty_array [pkt_array_depth-1:0]; +reg [pkt_array_depth-1:0] seg_val_array; +reg [pkt_array_depth-1:0] seg_sop_array; +reg [pkt_array_depth-1:0] seg_eop_array; +reg [pkt_array_depth-1:0] seg_err_array; +reg [pkt_array_depth-1:0] seg_blk_end_array; + +`else + +reg [`segment_width-1:0] seg_data_array [(`unseg_axis_w/`segment_width)-1:0]; +reg [seg_mty_w-1:0] seg_mty_array [(`unseg_axis_w/`segment_width)-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_val_array; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_sop_array; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_eop_array; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_err_array; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_blk_end_array; + +`endif + +// Generate a flag indicate the end of a block(aligned with the eop of the last packet in the block) + +wire [`num_axis_ports-1:0] unseg_blk_end_buf_val; + +`ifdef en_axis1 + +reg [`num_axis_ports-1:0] unseg_blk_end_flg; + +genvar h; +generate +for (h=0; h<`num_axis_ports; h=h+1) begin + if (h == 0) + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg | unseg_pkt_blk_end) + unseg_blk_end_flg[h] <= 1'b0; + else if (only_port1_active) + unseg_blk_end_flg[h] <= 1'b0; + else if (unseg_blk_end_flg[h]) + if (|unseg_blk_end_buf[h+1] && |unseg_val_buf[h+1] && unseg_buf_rd_en_c[h+1]) + unseg_blk_end_flg[h] <= 1'b0; + else + unseg_blk_end_flg[h] <= unseg_blk_end_flg[h]; + else if (|unseg_blk_end_buf[h] && |unseg_val_buf[h] && unseg_buf_rd_en_c[h]) + if (|unseg_blk_end_buf[h+1] && |unseg_val_buf[h+1] && unseg_buf_rd_en_c[h+1]) + unseg_blk_end_flg[h] <= 1'b0; + else if (unseg_blk_end_flg[h+1]) + unseg_blk_end_flg[h] <= 1'b0; + else + unseg_blk_end_flg[h] <= 1'b1; + else + unseg_blk_end_flg[h] <= unseg_blk_end_flg[h]; + end + else + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg | unseg_pkt_blk_end) + unseg_blk_end_flg[h] <= 1'b0; + else if (only_port0_active) + unseg_blk_end_flg[h] <= 1'b0; + else if (unseg_blk_end_flg[h]) + if (|unseg_blk_end_buf[h-1] && |unseg_val_buf[h-1] && unseg_buf_rd_en_c[h-1]) + unseg_blk_end_flg[h] <= 1'b0; + else + unseg_blk_end_flg[h] <= unseg_blk_end_flg[h]; + else if (|unseg_blk_end_buf[h] && |unseg_val_buf[h] && unseg_buf_rd_en_c[h]) + if (|unseg_blk_end_buf[h-1] && |unseg_val_buf[h-1] && unseg_buf_rd_en_c[h-1]) + unseg_blk_end_flg[h] <= 1'b0; + else if (unseg_blk_end_flg[h-1]) + unseg_blk_end_flg[h] <= 1'b0; + else + unseg_blk_end_flg[h] <= 1'b1; + else + unseg_blk_end_flg[h] <= unseg_blk_end_flg[h]; + end +end +endgenerate + +`endif + +`ifdef en_axis1 + +genvar h0; +generate +for (h0=0; h0<`num_axis_ports; h0=h0+1) begin + if (h0 == 0) + assign unseg_blk_end_buf_val[h0] = (unseg_blk_end_flg[h0+1] && (|unseg_blk_end_buf[h0] && unseg_buf_rd_en_c[h0] && |unseg_val_buf[h0])) ? 1'b1 : (|unseg_blk_end_buf[h0] && unseg_buf_rd_en_c[h0] && |unseg_val_buf[h0] && !(|unseg_val_buf[h0+1])) ? 1'b1 : (|unseg_blk_end_buf[h0] & unseg_buf_rd_en_c[h0] & |unseg_val_buf[h0]) & (|unseg_blk_end_buf[h0+1] & unseg_buf_rd_en_c[h0+1] & |unseg_val_buf[h0+1]); + else + assign unseg_blk_end_buf_val[h0] = (unseg_blk_end_flg[h0-1] && (|unseg_blk_end_buf[h0] && unseg_buf_rd_en_c[h0] && |unseg_val_buf[h0])) ? 1'b1 : (|unseg_blk_end_buf[h0] && unseg_buf_rd_en_c[h0] && |unseg_val_buf[h0] && !(|unseg_val_buf[h0-1])) ? 1'b1 : (|unseg_blk_end_buf[h0] & unseg_buf_rd_en_c[h0] & |unseg_val_buf[h0]) & (|unseg_blk_end_buf[h0-1] & unseg_buf_rd_en_c[h0-1] & |unseg_val_buf[h0-1]); +end +endgenerate + +`else + assign unseg_blk_end_buf_val[0] = (|unseg_blk_end_buf[0] & |unseg_val_buf[0]); +`endif + +assign unseg_pkt_blk_end = |unseg_blk_end_buf_val; + +genvar hh; + +`ifdef en_axis1 + +generate +for (hh=0; hh < (pkt_array_depth/2); hh = hh+1) begin + always @ (posedge aclk_axis_unseg) begin + if (pkt_port_sel) begin + seg_data_array[hh] <= unseg_dat_buf[1][hh]; + seg_mty_array[hh] <= unseg_mty_buf[1][hh]; + seg_val_array[hh] <= unseg_val_buf[1][hh] & unseg_buf_rd_en_c[1]; + seg_sop_array[hh] <= unseg_sop_buf[1][hh]; + seg_eop_array[hh] <= unseg_eop_buf[1][hh]; + seg_err_array[hh] <= unseg_err_buf[1][hh]; + seg_blk_end_array[hh] <= unseg_blk_end_buf[1][hh] & unseg_blk_end_buf_val[1]; + seg_data_array[hh+(pkt_array_depth/2)] <= unseg_dat_buf[0][hh]; + seg_mty_array[hh+(pkt_array_depth/2)] <= unseg_mty_buf[0][hh]; + seg_val_array[hh+(pkt_array_depth/2)] <= unseg_val_buf[0][hh] & unseg_buf_rd_en_c[0]; + seg_sop_array[hh+(pkt_array_depth/2)] <= unseg_sop_buf[0][hh]; + seg_eop_array[hh+(pkt_array_depth/2)] <= unseg_eop_buf[0][hh]; + seg_err_array[hh+(pkt_array_depth/2)] <= unseg_err_buf[0][hh]; + seg_blk_end_array[hh+(pkt_array_depth/2)] <= unseg_blk_end_buf[0][hh] & unseg_blk_end_buf_val[0]; + end else begin + seg_data_array[hh] <= unseg_dat_buf[0][hh]; + seg_mty_array[hh] <= unseg_mty_buf[0][hh]; + seg_val_array[hh] <= unseg_val_buf[0][hh] & unseg_buf_rd_en_c[0]; + seg_sop_array[hh] <= unseg_sop_buf[0][hh]; + seg_eop_array[hh] <= unseg_eop_buf[0][hh]; + seg_err_array[hh] <= unseg_err_buf[0][hh]; + seg_blk_end_array[hh] <= unseg_blk_end_buf[0][hh] & unseg_blk_end_buf_val[0]; + seg_data_array[hh+(pkt_array_depth/2)] <= unseg_dat_buf[1][hh]; + seg_mty_array[hh+(pkt_array_depth/2)] <= unseg_mty_buf[1][hh]; + seg_val_array[hh+(pkt_array_depth/2)] <= unseg_val_buf[1][hh] & unseg_buf_rd_en_c[1]; + seg_sop_array[hh+(pkt_array_depth/2)] <= unseg_sop_buf[1][hh]; + seg_eop_array[hh+(pkt_array_depth/2)] <= unseg_eop_buf[1][hh]; + seg_err_array[hh+(pkt_array_depth/2)] <= unseg_err_buf[1][hh]; + seg_blk_end_array[hh+(pkt_array_depth/2)] <= unseg_blk_end_buf[1][hh] & unseg_blk_end_buf_val[1]; + end + end +end +endgenerate + +`else + +generate +for (hh=0; hh < pkt_array_depth; hh = hh+1) begin + always @ (posedge aclk_axis_unseg) begin + seg_data_array[hh] <= unseg_dat_buf[0][hh]; + seg_mty_array[hh] <= unseg_mty_buf[0][hh]; + seg_val_array[hh] <= unseg_val_buf[0][hh] & unseg_buf_rd_en_c[0]; + seg_sop_array[hh] <= unseg_sop_buf[0][hh]; + seg_eop_array[hh] <= unseg_eop_buf[0][hh]; + seg_err_array[hh] <= unseg_err_buf[0][hh]; + seg_blk_end_array[hh] <= unseg_blk_end_buf[0][hh]; + end +end +endgenerate + +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Segment array + +// Pack the segments + +reg [`segment_width-1:0] pkt_data_array [(pkt_array_depth*2)-1:0]; +reg [seg_mty_w-1:0] pkt_mty_array [(pkt_array_depth*2)-1:0]; +reg [(pkt_array_depth*2)-1:0] pkt_val_array0; +reg [(pkt_array_depth*2)-1:0] pkt_val_array00; +reg [(pkt_array_depth*2)-1:0] pkt_val_array1; +reg [(pkt_array_depth*2)-1:0] pkt_val_array2; +reg [(pkt_array_depth*2)-1:0] pkt_val_array; +reg [(pkt_array_depth*2)-1:0] pkt_sop_array; +reg [(pkt_array_depth*2)-1:0] pkt_eop_array; +reg [(pkt_array_depth*2)-1:0] pkt_err_array; +reg [(pkt_array_depth*2)-1:0] pkt_blk_end_array; +reg [(pkt_array_depth*2)-1:0] pkt_blk_end_array1; + +reg [$clog2((pkt_array_depth*2))-1:0] pkt_seg_sel_reg [(pkt_array_depth*2)-1:0]; +reg [$clog2((pkt_array_depth*2))-1:0] pkt_seg_sel_reg1 [(pkt_array_depth*2)-1:0]; + +wire pkt_arry_clr_p0; +wire pkt_arry_clr_p1; +wire pkt_arry_clr_p2; +wire pkt_arry_clr_p3; + +reg [$clog2((pkt_array_depth*2))-1:0] pkt_array_ptr1; +reg [$clog2((pkt_array_depth*2))-1:0] pkt_array_ptr2; + +wire p0_flushout_c; +wire p1_flushout_c; +wire p2_flushout_c; +wire p3_flushout_c; + +assign p0_flushout_c = pkt_val_array1[0] & |(pkt_blk_end_array1[((pkt_array_depth/2)*1)-1:0]); +assign p1_flushout_c = pkt_val_array1[((pkt_array_depth/2)*1)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*2)-1:(pkt_array_depth/2)*1]); +assign p2_flushout_c = pkt_val_array1[((pkt_array_depth/2)*2)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*3)-1:(pkt_array_depth/2)*2]); +assign p3_flushout_c = pkt_val_array1[((pkt_array_depth/2)*3)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*4)-1:(pkt_array_depth/2)*3]); + +assign pkt_arry_clr_p0 = pkt_val_array1[((pkt_array_depth/2)*1)-1] | (pkt_val_array1[0] & |(pkt_blk_end_array1[((pkt_array_depth/2)*1)-1:0])); +assign pkt_arry_clr_p1 = pkt_val_array1[((pkt_array_depth/2)*2)-1] | (pkt_val_array1[((pkt_array_depth/2)*1)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*2)-1:(pkt_array_depth/2)*1])); +assign pkt_arry_clr_p2 = pkt_val_array1[((pkt_array_depth/2)*3)-1] | (pkt_val_array1[((pkt_array_depth/2)*2)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*3)-1:(pkt_array_depth/2)*2])); +assign pkt_arry_clr_p3 = pkt_val_array1[((pkt_array_depth/2)*4)-1] | (pkt_val_array1[((pkt_array_depth/2)*3)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*4)-1:(pkt_array_depth/2)*3])); + +wire pkt_array_rst; +wire pkt_seg_sel_reg_rst; + +assign pkt_array_rst = !aresetn_axis_unseg | p0_flushout_c | p1_flushout_c | p2_flushout_c | p3_flushout_c; +assign pkt_seg_sel_reg_rst = !aresetn_axis_unseg | p0_flushout_c | p1_flushout_c | p2_flushout_c | p3_flushout_c; + +integer i, ii; +generate + always @ (posedge aclk_axis_unseg) begin + if (pkt_array_rst) begin + pkt_array_ptr1 = 0; + for(i=0; i < pkt_array_depth*2; i = i+1) begin + pkt_val_array0 [i] <= 1'b0; + pkt_val_array1 [i] <= 1'b0; + pkt_blk_end_array1 [i] <= 1'b0; + end + end else begin + for(i=0; i eop_cnt) + pkt_open <= 1'b1; + else + pkt_open <= 1'b0; + else + pkt_open <= pkt_open; +end + +assign error_broken_pkt0 = pkt_open & ~unseg_val0_q; // Indicates a missing eop + +integer z0; + +reg error_broken_pkt1; + +reg last_seg_eop; + +always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) begin + error_broken_pkt1 <= 1'b0; + last_seg_eop = 1'b1; + end else begin + for (z0=0; z0<`num_segments; z0=z0+1) begin + if (unseg2seg_out_Val[z0] & seg_buf_out_rd_en) begin + if (unseg2seg_out_Sop[z0] && !last_seg_eop) begin // indicates a gap between eop & next sop within valid segments + error_broken_pkt1 = 1'b1; // packet get corrupted + end else if (unseg2seg_out_Sop[z0] && last_seg_eop) begin // next valid packet boundary detected + error_broken_pkt1 = 1'b0; + end else begin + error_broken_pkt1 = error_broken_pkt1; + end + last_seg_eop = unseg2seg_out_Eop[z0]; + end + end + end +end + +// #3 Corrupted data/mty values + +reg err_data_mismatch; +reg [15:0] seg_last_data; +reg err_mty_nonzero; + +integer z1; + +always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) begin + err_data_mismatch = 1'b0; + seg_last_data = 'd0; + err_mty_nonzero = 1'b0; + end else begin + for (z1=0; z1<`num_segments; z1=z1+1) begin + if (unseg2seg_out_Val[z1] & seg_buf_out_rd_en) begin + if(unseg2seg_out_Dat[z1][15:0] - seg_last_data != 15'h0001) begin + err_data_mismatch = 1'b1; + end else begin + err_data_mismatch = 1'b0; + end + seg_last_data = unseg2seg_out_Dat[z1][15:0]; + if(!unseg2seg_out_Eop[z1] && |unseg2seg_out_Mty[z1]) begin + err_mty_nonzero = 1'b1; + end else begin + err_mty_nonzero = 1'b0; + end + end + end + end +end + +// in the below assignment "err_data_mismatch" could be included only when checking with incrementing/counter data as packet input and at less rate(flow_control disabled) + +assign error_broken_pkt_out = error_broken_pkt0 | error_broken_pkt1 | err_mty_nonzero; // | err_data_mismatch; + +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Port Statistics + +`ifdef statistics_en + localparam statistics_en = 1; +`else + localparam statistics_en = 0; +`endif + +generate + +if (statistics_en) begin + +//----------------- Ouput packet count + +reg [63:0] segment_pkt_cnt [`num_segments-1:0]; +reg [63:0] segment_err_cnt [`num_segments-1:0]; +reg [63:0] segment_pkt_sop_cnt [`num_segments-1:0]; +reg [63:0] segment_byte_cnt [`num_segments-1:0]; +wire [($clog2(`segment_width/8)):0] segment_validbytes [`num_segments-1:0]; +reg [63:0] total_pktout_cnt; +reg [63:0] total_err_pktout_cnt; +reg [63:0] total_pktout_byte_cnt; + +genvar ab; + +for (ab=0; ab<`num_segments; ab=ab+1) begin + mty_to_validbytes u_mty_to_valbytes + ( + .mty_in(unseg2seg_out_Mty[ab]), + .valid_bytes_out(segment_validbytes[ab]) + ); +end + +genvar cd; + +for (cd=0; cd<`num_segments; cd=cd+1) begin + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_byte_cnt[cd] <= 'd0; + else if (unseg2seg_out_Val[cd] & seg_data_out_valid & seg_buf_out_rd_en) + segment_byte_cnt[cd] <= segment_byte_cnt[cd] + segment_validbytes[cd]; + end +end + +integer ef; + +always @ (*) begin + total_pktout_byte_cnt = 'd0; + for (ef=0; ef<`num_segments; ef=ef+1) begin + total_pktout_byte_cnt = total_pktout_byte_cnt + segment_byte_cnt[ef]; + end +end + +genvar gh; + +for (gh=0; gh<`num_segments; gh=gh+1) begin + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_pkt_cnt[gh] <= 'd0; + else if (unseg2seg_out_Val[gh] && seg_data_out_valid && unseg2seg_out_Eop[gh] && seg_buf_out_rd_en) + segment_pkt_cnt[gh] <= segment_pkt_cnt[gh] + 1; + end + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_err_cnt[gh] <= 'd0; + else if (unseg2seg_out_Val[gh] && seg_data_out_valid && unseg2seg_out_Eop[gh] && unseg2seg_out_Err[gh] && seg_buf_out_rd_en) + segment_err_cnt[gh] <= segment_err_cnt[gh] + 1; + end +end + +integer ij; + +always @ (*) begin + total_pktout_cnt = 'd0; + total_err_pktout_cnt = 'd0; + for (ij=0; ij<`num_segments; ij=ij+1) begin + total_pktout_cnt = total_pktout_cnt + segment_pkt_cnt[ij]; + total_err_pktout_cnt = total_err_pktout_cnt + segment_err_cnt[ij]; + end +end + +//----------------- Input packet count + +reg [63:0] port_pkt_in_cnt [`num_axis_ports-1:0]; +reg [63:0] port_err_pkt_in_cnt [`num_axis_ports-1:0]; +reg [63:0] port_pkt_in_byte_cnt [`num_axis_ports-1:0]; +reg [63:0] total_pktin_cnt; +reg [63:0] total_err_pktin_cnt; +reg [63:0] total_pktin_byte_cnt; + +wire [($clog2(`unseg_axis_w/8)):0] port_valid_bytes [`num_axis_ports-1:0]; + +genvar g; +for (g=0; g<`num_axis_ports; g=g+1) begin + tkeep_to_validbytes u_tkeep_to_valbytes + ( + .tkeep_in(s_axis_tkeep_in[g]), + .valid_bytes_out(port_valid_bytes[g]) + ); +end + +genvar i; +for (i=0; i<`num_axis_ports; i=i+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_pkt_in_cnt[i] <= 'd0; + else if (s_axis_tvalid_in[i] && (s_axis_tready_in[i] && !axis_pkt_blk_rdy_flg) && s_axis_tlast_in[i]) + port_pkt_in_cnt[i] <= port_pkt_in_cnt[i] + 'd1; + end + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_err_pkt_in_cnt[i] <= 'd0; + else if (s_axis_tvalid_in[i] && (s_axis_tready_in[i] && !axis_pkt_blk_rdy_flg) && s_axis_tlast_in[i] && s_axis_tuser_in[i]) + port_err_pkt_in_cnt[i] <= port_err_pkt_in_cnt[i] + 'd1; + end +end + +genvar j; +for (j=0; j<`num_axis_ports; j=j+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_pkt_in_byte_cnt[j] <= 'd0; + else if (s_axis_tvalid_in[j] && (s_axis_tready_in[j] && !axis_pkt_blk_rdy_flg)) + port_pkt_in_byte_cnt[j] <= port_pkt_in_byte_cnt[j] + port_valid_bytes[j]; + end +end + +integer k; +always @ (*) begin + total_pktin_cnt = 'd0; + total_err_pktin_cnt = 'd0; + total_pktin_byte_cnt = 'd0; + for (k=0; k<`num_axis_ports; k=k+1) begin + total_pktin_cnt = total_pktin_cnt + port_pkt_in_cnt[k]; + total_err_pktin_cnt = total_err_pktin_cnt + port_err_pkt_in_cnt[k]; + total_pktin_byte_cnt = total_pktin_byte_cnt + port_pkt_in_byte_cnt[k]; + end +end + +assign total_pkt_in_cnt = total_pktin_cnt; +assign total_err_pkt_in_cnt = total_err_pktin_cnt; +assign total_pkt_in_byte_cnt = total_pktin_byte_cnt; +assign total_pkt_out_cnt = total_pktout_cnt; +assign total_err_pkt_out_cnt = total_err_pktout_cnt; +assign total_pkt_out_byte_cnt = total_pktout_byte_cnt; +`ifdef en_axis1 +assign p1_pkt_in_cnt = port_pkt_in_cnt[1]; +assign p1_err_pkt_in_cnt = port_err_pkt_in_cnt[1]; +assign p1_pkt_in_byte_cnt = port_pkt_in_byte_cnt[1]; +assign p0_pkt_in_cnt = port_pkt_in_cnt[0]; +assign p0_err_pkt_in_cnt = port_err_pkt_in_cnt[0]; +assign p0_pkt_in_byte_cnt = port_pkt_in_byte_cnt[0]; +`endif + +end +endgenerate + +endmodule + +//----------------------------------------------------------------------------------------------------------------------- + +module tkeep_to_mty + ( + input [(`segment_width/8)-1:0] tkeep_in, + output wire [($clog2(`segment_width/8))-1:0] mty_out + ); + +integer i; +reg [($clog2(`segment_width/8)):0] valid; + +always @ (tkeep_in) begin + valid = 0; + for (i=0; i<(`segment_width/8); i=i+1) + valid = valid + tkeep_in[i]; +end + +assign mty_out = (`segment_width/8) - valid; + +endmodule + +//----------------------------------------------------------------------------------------------------------------------- +//----------------------------------------------------------------------------------------------------------------------- + diff --git a/linker/resources/dcmac/hdl/clock_to_clock_bus.v b/linker/resources/dcmac/hdl/clock_to_clock_bus.v new file mode 100644 index 00000000..3410398d --- /dev/null +++ b/linker/resources/dcmac/hdl/clock_to_clock_bus.v @@ -0,0 +1,14 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +`timescale 1ns / 1ps + +module clock_to_clock_bus ( + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) + input clk, + output wire [5:0] clockbus + ); + + assign clockbus = {6{clk}}; + +endmodule \ No newline at end of file diff --git a/linker/resources/dcmac/hdl/dcmac200g_ctl_port.v b/linker/resources/dcmac/hdl/dcmac200g_ctl_port.v new file mode 100644 index 00000000..8cc38c77 --- /dev/null +++ b/linker/resources/dcmac/hdl/dcmac200g_ctl_port.v @@ -0,0 +1,54 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +`timescale 1ps/1ps + +module dcmac200g_ctl_port ( + output wire [15:0] default_vl_length_100GE, + output wire [15:0] default_vl_length_200GE_or_400GE, + output wire [63:0] ctl_tx_vl_marker_id0, + output wire [63:0] ctl_tx_vl_marker_id1, + output wire [63:0] ctl_tx_vl_marker_id2, + output wire [63:0] ctl_tx_vl_marker_id3, + output wire [63:0] ctl_tx_vl_marker_id4, + output wire [63:0] ctl_tx_vl_marker_id5, + output wire [63:0] ctl_tx_vl_marker_id6, + output wire [63:0] ctl_tx_vl_marker_id7, + output wire [63:0] ctl_tx_vl_marker_id8, + output wire [63:0] ctl_tx_vl_marker_id9, + output wire [63:0] ctl_tx_vl_marker_id10, + output wire [63:0] ctl_tx_vl_marker_id11, + output wire [63:0] ctl_tx_vl_marker_id12, + output wire [63:0] ctl_tx_vl_marker_id13, + output wire [63:0] ctl_tx_vl_marker_id14, + output wire [63:0] ctl_tx_vl_marker_id15, + output wire [63:0] ctl_tx_vl_marker_id16, + output wire [63:0] ctl_tx_vl_marker_id17, + output wire [63:0] ctl_tx_vl_marker_id18, + output wire [63:0] ctl_tx_vl_marker_id19 +); + + assign default_vl_length_100GE = 16'd255; + assign default_vl_length_200GE_or_400GE = 16'd256; + assign ctl_tx_vl_marker_id0 = 64'hc16821003e97de00; + assign ctl_tx_vl_marker_id1 = 64'h9d718e00628e7100; + assign ctl_tx_vl_marker_id2 = 64'h594be800a6b41700; + assign ctl_tx_vl_marker_id3 = 64'h4d957b00b26a8400; + assign ctl_tx_vl_marker_id4 = 64'hf50709000af8f600; + assign ctl_tx_vl_marker_id5 = 64'hdd14c20022eb3d00; + assign ctl_tx_vl_marker_id6 = 64'h9a4a260065b5d900; + assign ctl_tx_vl_marker_id7 = 64'h7b45660084ba9900; + assign ctl_tx_vl_marker_id8 = 64'ha02476005fdb8900; + assign ctl_tx_vl_marker_id9 = 64'h68c9fb0097360400; + assign ctl_tx_vl_marker_id10 = 64'hfd6c990002936600; + assign ctl_tx_vl_marker_id11 = 64'hb9915500466eaa00; + assign ctl_tx_vl_marker_id12 = 64'h5cb9b200a3464d00; + assign ctl_tx_vl_marker_id13 = 64'h1af8bd00e5074200; + assign ctl_tx_vl_marker_id14 = 64'h83c7ca007c383500; + assign ctl_tx_vl_marker_id15 = 64'h3536cd00cac93200; + assign ctl_tx_vl_marker_id16 = 64'hc4314c003bceb300; + assign ctl_tx_vl_marker_id17 = 64'hadd6b70052294800; + assign ctl_tx_vl_marker_id18 = 64'h5f662a00a099d500; + assign ctl_tx_vl_marker_id19 = 64'hc0f0e5003f0f1a00; + +endmodule \ No newline at end of file diff --git a/linker/resources/dcmac/hdl/serdes_clock.v b/linker/resources/dcmac/hdl/serdes_clock.v new file mode 100644 index 00000000..3d1eec10 --- /dev/null +++ b/linker/resources/dcmac/hdl/serdes_clock.v @@ -0,0 +1,14 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +`timescale 1ns / 1ps + +module clock_to_serdes ( + input usrclk, + (* X_INTERFACE_INFO = "xilinx.com:signal:gt_usrclk:1.0 GT_USRCLK.RX_ALT_SERDES_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME GT_USRCLK.RX_ALT_SERDES_CLK, CLK_DOMAIN dcmac_200g_exdes_support_rx_alt_serdes_clk, FREQ_HZ 156250000, PARENT_ID undef, PHASE 0.0" *) + output wire [5:0] serdes_clk + ); + + assign serdes_clk = {1'b0, 1'b0, 1'b0, 1'b0, usrclk, usrclk}; + +endmodule \ No newline at end of file diff --git a/linker/resources/dcmac/hdl/syncer_reset.v b/linker/resources/dcmac/hdl/syncer_reset.v new file mode 100644 index 00000000..1b0e5933 --- /dev/null +++ b/linker/resources/dcmac/hdl/syncer_reset.v @@ -0,0 +1,37 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +`timescale 1ps/1ps + +module dcmac_syncer_reset #( + parameter RESET_PIPE_LEN = 3 +) +( + input wire clk, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 clk_wizard_lock,resetn_async RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input wire clk_wizard_lock, + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input wire resetn_async, + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + output wire resetn +); + + (* ASYNC_REG = "TRUE" *) reg [RESET_PIPE_LEN-1:0] reset_pipe_retime; + reg reset_pipe_out = 1'b0; + assign resetn_async_inv = resetn_async & clk_wizard_lock; + + always @(posedge clk or negedge resetn_async_inv) begin + if (resetn_async_inv == 1'b0) begin + reset_pipe_retime <= {RESET_PIPE_LEN{1'b0}}; + reset_pipe_out <= 1'b0; + end + else begin + reset_pipe_retime <= {reset_pipe_retime[RESET_PIPE_LEN-2:0], 1'b1}; + reset_pipe_out <= reset_pipe_retime[RESET_PIPE_LEN-1]; + end + end + + assign resetn = reset_pipe_out; + +endmodule \ No newline at end of file diff --git a/linker/resources/dcmac/tcl/dcmac.tcl b/linker/resources/dcmac/tcl/dcmac.tcl new file mode 100644 index 00000000..94169ee7 --- /dev/null +++ b/linker/resources/dcmac/tcl/dcmac.tcl @@ -0,0 +1,1347 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +# hdl files from resources will be available in this script when running at "$src_dir/dcmac/hdl/..." + + +# Hierarchical cell: dcmac_gt_wrapper +proc create_hier_cell_dcmac_gt_wrapper { parentCell nameHier dcmac_index dual_dcmac } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_dcmac_gt_wrapper() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp_clk_322mhz + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX0_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX1_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX2_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX3_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX0_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX1_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX2_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX3_GT0_IP_Interface + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 GT0_Serial + + if { ${dual_dcmac} == "1" } { + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX0_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX1_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX2_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX3_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX0_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX1_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX2_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX3_GT1_IP_Interface + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 GT1_Serial + } + + # Create pins + create_bd_pin -dir I -from 0 -to 0 MBUFG_GT_CLR + create_bd_pin -dir I -from 0 -to 0 MBUFG_GT_CLRB_LEAF + create_bd_pin -dir O -from 0 -to 0 -type gt_usrclk qsfp0_rx_usr_clk_664mhz + create_bd_pin -dir O -from 0 -to 0 -type gt_usrclk qsfp0_rx_usr_clk_332mhz + create_bd_pin -dir I -from 0 -to 0 MBUFG_GT_CLR1 + create_bd_pin -dir I -from 0 -to 0 MBUFG_GT_CLRB_LEAF1 + create_bd_pin -dir O -from 0 -to 0 -type gt_usrclk qsfp0_tx_usr_clk_664mhz + create_bd_pin -dir O -from 0 -to 0 -type gt_usrclk qsfp0_tx_usr_clk_332mhz + create_bd_pin -dir I -type rst hsclk_pllreset0 + create_bd_pin -dir O hsclk_plllock0 + create_bd_pin -dir O gtpowergood_0 + create_bd_pin -dir I -type rst gt0_ch0_iloreset + create_bd_pin -dir I -type rst gt0_ch1_iloreset + create_bd_pin -dir I -type rst gt0_ch2_iloreset + create_bd_pin -dir I -type rst gt0_ch3_iloreset + create_bd_pin -dir O gt0_ch0_iloresetdone + create_bd_pin -dir O gt0_ch1_iloresetdone + create_bd_pin -dir O gt0_ch2_iloresetdone + create_bd_pin -dir O gt0_ch3_iloresetdone + create_bd_pin -dir I -type clk apb3clk_quad + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -type gt_usrclk GT0_ref_clk + create_bd_pin -dir I -from 31 -to 0 gt_control_pins + + if { ${dual_dcmac} == "1" } { + create_bd_pin -dir I -type rst hsclk_pllreset1 + create_bd_pin -dir O hsclk_plllock1 + create_bd_pin -dir I -type rst gt1_ch0_iloreset + create_bd_pin -dir I -type rst gt1_ch1_iloreset + create_bd_pin -dir I -type rst gt1_ch2_iloreset + create_bd_pin -dir I -type rst gt1_ch3_iloreset + create_bd_pin -dir O gt1_ch0_iloresetdone + create_bd_pin -dir O gt1_ch1_iloresetdone + create_bd_pin -dir O gt1_ch2_iloresetdone + create_bd_pin -dir O gt1_ch3_iloresetdone + create_bd_pin -dir O gtpowergood_1 + } + + # Create instance: util_ds_buf_0, and set properties + set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_0 ] + set_property CONFIG.C_BUF_TYPE {IBUFDS_GTME5} $util_ds_buf_0 + + set top_dcmac_name "top_dcmac_${dcmac_index}_core_0" + set dcmac_name "dcmac_${dcmac_index}_core" + + set list_quad_index { 0 } + if { ${dual_dcmac} == "1" } { + lappend list_quad_index 1 + } + + foreach idx ${list_quad_index} { + # Create instance: gt0_quad, and set properties + set quad_name "gt${idx}_quad" + set gt_quad [ create_bd_cell -type ip -vlnv xilinx.com:ip:gt_quad_base ${quad_name} ] + + set channel_ordering {} + foreach dirid {TX RX} { + for {set lane 0} {$lane < 4} {incr lane} { + set new_idx ${lane} + if { ${idx} == "1" } { + set new_idx "[expr {$lane + 4}]" + } + + set ord " ${oldCurInst}/${quad_name}/${dirid}${lane}_GT_IP_Interface top_dcmac_${idx}_core_0.${oldCurInst}/dcmac_${idx}_core/gtm_tx_serdes_interface_${new_idx}.${new_idx}" + append channel_ordering ${ord} + } + } + + set quad_usage {} + foreach dirid {TX_QUAD_CH RX_QUAD_CH} { + set list_quad_index_ii { 0 } + if { ${dual_dcmac} == "1" } { + lappend list_quad_index_ii 1 + } + append quad_usage " ${dirid} {" + foreach idxii ${list_quad_index_ii} { + set quad_name_ii "gt${idxii}_quad" + set q0 [expr {${idx} == ${idxii}}] + #set q1 [expr {!$q0}] + if { ${idxii} == "0" } { + set conf " ${oldCurInst}/dcmac_gt${idxii}_wrapper/${quad_name_ii} {${oldCurInst}/dcmac_gt${dcmac_index}_wrapper/${quad_name_ii}\ + top_dcmac_${dcmac_index}_core_0.IP_CH0,top_dcmac_${dcmac_index}_core_0.IP_CH1,top_dcmac_${dcmac_index}_core_0.IP_CH2,top_dcmac_${dcmac_index}_core_0.IP_CH3 MSTRCLK 1,0,0,0 IS_CURRENT_QUAD ${q0}}" + } else { + set conf " ${oldCurInst}/dcmac_gt${idxii}_wrapper/${quad_name_ii} {${oldCurInst}/dcmac_gt${dcmac_index}_wrapper/${quad_name_ii}\ + top_dcmac_${dcmac_index}_core_0.IP_CH4,top_dcmac_${dcmac_index}_core_0.IP_CH5,top_dcmac_${dcmac_index}_core_0.IP_CH6,top_dcmac_${dcmac_index}_core_0.IP_CH7 MSTRCLK 1,0,0,0 IS_CURRENT_QUAD ${q0}}" + } + append quad_usage "${conf}" + } + append quad_usage "}" + } + + set_property -dict [list \ + CONFIG.APB3_CLK_FREQUENCY {100.0} \ + CONFIG.CHANNEL_ORDERING {${channel_ordering}} \ + CONFIG.GT_TYPE {GTM} \ + CONFIG.PORTS_INFO_DICT {LANE_SEL_DICT {PROT0 {RX0 RX1 RX2 RX3 TX0 TX1 TX2 TX3}} GT_TYPE GTM REG_CONF_INTF APB3_INTF BOARD_PARAMETER { }} \ + CONFIG.PROT0_ENABLE {true} \ + CONFIG.PROT0_GT_DIRECTION {DUPLEX} \ + CONFIG.PROT0_LR0_SETTINGS {GT_DIRECTION DUPLEX TX_PAM_SEL PAM4 TX_HD_EN 0 TX_GRAY_BYP false TX_GRAY_LITTLEENDIAN false TX_PRECODE_BYP true TX_PRECODE_LITTLEENDIAN false TX_LINE_RATE 53.125 TX_PLL_TYPE\ +LCPLL TX_REFCLK_FREQUENCY 322.265625 TX_ACTUAL_REFCLK_FREQUENCY 322.265625183611 TX_FRACN_ENABLED true TX_FRACN_OVRD false TX_FRACN_NUMERATOR 0 TX_REFCLK_SOURCE R0 TX_DATA_ENCODING RAW TX_USER_DATA_WIDTH\ +160 TX_INT_DATA_WIDTH 128 TX_BUFFER_MODE 1 TX_BUFFER_BYPASS_MODE Fast_Sync TX_PIPM_ENABLE false TX_OUTCLK_SOURCE TXPROGDIVCLK TXPROGDIV_FREQ_ENABLE true TXPROGDIV_FREQ_SOURCE LCPLL TXPROGDIV_FREQ_VAL 664.062\ +TX_DIFF_SWING_EMPH_MODE CUSTOM TX_64B66B_SCRAMBLER false TX_64B66B_ENCODER false TX_64B66B_CRC false TX_RATE_GROUP A TX_LANE_DESKEW_HDMI_ENABLE false TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE PRESET GTM-PAM4_Ethernet_53G\ +RX_PAM_SEL PAM4 RX_HD_EN 0 RX_GRAY_BYP false RX_GRAY_LITTLEENDIAN false RX_PRECODE_BYP true RX_PRECODE_LITTLEENDIAN false INTERNAL_PRESET PAM4_Ethernet_53G RX_LINE_RATE 53.125 RX_PLL_TYPE LCPLL RX_REFCLK_FREQUENCY\ +322.265625 RX_ACTUAL_REFCLK_FREQUENCY 322.265625183611 RX_FRACN_ENABLED true RX_FRACN_OVRD false RX_FRACN_NUMERATOR 0 RX_REFCLK_SOURCE R0 RX_DATA_DECODING RAW RX_USER_DATA_WIDTH 160 RX_INT_DATA_WIDTH 128\ +RX_BUFFER_MODE 1 RX_OUTCLK_SOURCE RXPROGDIVCLK RXPROGDIV_FREQ_ENABLE true RXPROGDIV_FREQ_SOURCE LCPLL RXPROGDIV_FREQ_VAL 664.062 RXRECCLK_FREQ_ENABLE false RXRECCLK_FREQ_VAL 0 INS_LOSS_NYQ 20 RX_EQ_MODE\ +AUTO RX_COUPLING AC RX_TERMINATION VCOM_VREF RX_RATE_GROUP A RX_TERMINATION_PROG_VALUE 800 RX_PPM_OFFSET 200 RX_64B66B_DESCRAMBLER false RX_64B66B_DECODER false RX_64B66B_CRC false OOB_ENABLE false RX_COMMA_ALIGN_WORD\ +1 RX_COMMA_SHOW_REALIGN_ENABLE true PCIE_ENABLE false RX_COMMA_P_ENABLE false RX_COMMA_M_ENABLE false RX_COMMA_DOUBLE_ENABLE false RX_COMMA_P_VAL 0101111100 RX_COMMA_M_VAL 1010000011 RX_COMMA_MASK 0000000000\ +RX_SLIDE_MODE OFF RX_SSC_PPM 0 RX_CB_NUM_SEQ 0 RX_CB_LEN_SEQ 1 RX_CB_MAX_SKEW 1 RX_CB_MAX_LEVEL 1 RX_CB_MASK 00000000 RX_CB_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000\ +RX_CB_K 00000000 RX_CB_DISP 00000000 RX_CB_MASK_0_0 false RX_CB_VAL_0_0 0000000000 RX_CB_K_0_0 false RX_CB_DISP_0_0 false RX_CB_MASK_0_1 false RX_CB_VAL_0_1 0000000000 RX_CB_K_0_1 false RX_CB_DISP_0_1\ +false RX_CB_MASK_0_2 false RX_CB_VAL_0_2 0000000000 RX_CB_K_0_2 false RX_CB_DISP_0_2 false RX_CB_MASK_0_3 false RX_CB_VAL_0_3 0000000000 RX_CB_K_0_3 false RX_CB_DISP_0_3 false RX_CB_MASK_1_0 false RX_CB_VAL_1_0\ +0000000000 RX_CB_K_1_0 false RX_CB_DISP_1_0 false RX_CB_MASK_1_1 false RX_CB_VAL_1_1 0000000000 RX_CB_K_1_1 false RX_CB_DISP_1_1 false RX_CB_MASK_1_2 false RX_CB_VAL_1_2 0000000000 RX_CB_K_1_2 false RX_CB_DISP_1_2\ +false RX_CB_MASK_1_3 false RX_CB_VAL_1_3 0000000000 RX_CB_K_1_3 false RX_CB_DISP_1_3 false RX_CC_NUM_SEQ 0 RX_CC_LEN_SEQ 1 RX_CC_PERIODICITY 5000 RX_CC_KEEP_IDLE DISABLE RX_CC_PRECEDENCE ENABLE RX_CC_REPEAT_WAIT\ +0 RX_CC_MASK 00000000 RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 RX_CC_K 00000000 RX_CC_DISP 00000000 RX_CC_MASK_0_0 false RX_CC_VAL_0_0 0000000000 RX_CC_K_0_0\ +false RX_CC_DISP_0_0 false RX_CC_MASK_0_1 false RX_CC_VAL_0_1 0000000000 RX_CC_K_0_1 false RX_CC_DISP_0_1 false RX_CC_MASK_0_2 false RX_CC_VAL_0_2 0000000000 RX_CC_K_0_2 false RX_CC_DISP_0_2 false RX_CC_MASK_0_3\ +false RX_CC_VAL_0_3 0000000000 RX_CC_K_0_3 false RX_CC_DISP_0_3 false RX_CC_MASK_1_0 false RX_CC_VAL_1_0 0000000000 RX_CC_K_1_0 false RX_CC_DISP_1_0 false RX_CC_MASK_1_1 false RX_CC_VAL_1_1 0000000000\ +RX_CC_K_1_1 false RX_CC_DISP_1_1 false RX_CC_MASK_1_2 false RX_CC_VAL_1_2 0000000000 RX_CC_K_1_2 false RX_CC_DISP_1_2 false RX_CC_MASK_1_3 false RX_CC_VAL_1_3 0000000000 RX_CC_K_1_3 false RX_CC_DISP_1_3\ +false PCIE_USERCLK2_FREQ 250 PCIE_USERCLK_FREQ 250 RX_JTOL_FC 10 RX_JTOL_LF_SLOPE -20 RX_BUFFER_BYPASS_MODE Fast_Sync RX_BUFFER_BYPASS_MODE_LANE MULTI RX_BUFFER_RESET_ON_CB_CHANGE ENABLE RX_BUFFER_RESET_ON_COMMAALIGN\ +DISABLE RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE RESET_SEQUENCE_INTERVAL 0 RX_COMMA_PRESET NONE RX_COMMA_VALID_ONLY 0 GT_TYPE GTM} \ + CONFIG.PROT0_LR10_SETTINGS {NA NA} \ + CONFIG.PROT0_LR11_SETTINGS {NA NA} \ + CONFIG.PROT0_LR12_SETTINGS {NA NA} \ + CONFIG.PROT0_LR13_SETTINGS {NA NA} \ + CONFIG.PROT0_LR14_SETTINGS {NA NA} \ + CONFIG.PROT0_LR15_SETTINGS {NA NA} \ + CONFIG.PROT0_LR1_SETTINGS {NA NA} \ + CONFIG.PROT0_LR2_SETTINGS {NA NA} \ + CONFIG.PROT0_LR3_SETTINGS {NA NA} \ + CONFIG.PROT0_LR4_SETTINGS {NA NA} \ + CONFIG.PROT0_LR5_SETTINGS {NA NA} \ + CONFIG.PROT0_LR6_SETTINGS {NA NA} \ + CONFIG.PROT0_LR7_SETTINGS {NA NA} \ + CONFIG.PROT0_LR8_SETTINGS {NA NA} \ + CONFIG.PROT0_LR9_SETTINGS {NA NA} \ + CONFIG.PROT0_NO_OF_LANES {4} \ + CONFIG.PROT0_RX_MASTERCLK_SRC {RX0} \ + CONFIG.PROT0_TX_MASTERCLK_SRC {TX0} \ + CONFIG.REFCLK_LIST {{/qsfp0_322mhz_clk_p[0]}} \ + CONFIG.REFCLK_STRING {HSCLK0_LCPLLGTREFCLK0 refclk_PROT0_R0_322.265625183611_MHz_unique1} \ + CONFIG.RX0_LANE_SEL {PROT0} \ + CONFIG.RX1_LANE_SEL {PROT0} \ + CONFIG.RX2_LANE_SEL {PROT0} \ + CONFIG.RX3_LANE_SEL {PROT0} \ + CONFIG.TX0_LANE_SEL {PROT0} \ + CONFIG.TX1_LANE_SEL {PROT0} \ + CONFIG.TX2_LANE_SEL {PROT0} \ + CONFIG.TX3_LANE_SEL {PROT0} \ + ] $gt_quad + + #CONFIG.QUAD_USAGE {${quad_usage}} \ + + set_property -dict [list \ + CONFIG.APB3_CLK_FREQUENCY.VALUE_MODE {auto} \ + CONFIG.CHANNEL_ORDERING.VALUE_MODE {auto} \ + CONFIG.GT_TYPE.VALUE_MODE {auto} \ + CONFIG.PROT0_ENABLE.VALUE_MODE {auto} \ + CONFIG.PROT0_GT_DIRECTION.VALUE_MODE {auto} \ + CONFIG.PROT0_LR0_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR10_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR11_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR12_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR13_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR14_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR15_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR1_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR2_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR3_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR4_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR5_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR6_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR7_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR8_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR9_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_NO_OF_LANES.VALUE_MODE {auto} \ + CONFIG.PROT0_RX_MASTERCLK_SRC.VALUE_MODE {auto} \ + CONFIG.PROT0_TX_MASTERCLK_SRC.VALUE_MODE {auto} \ + CONFIG.QUAD_USAGE.VALUE_MODE {auto} \ + CONFIG.REFCLK_LIST.VALUE_MODE {auto} \ + CONFIG.RX0_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.RX1_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.RX2_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.RX3_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.TX0_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.TX1_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.TX2_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.TX3_LANE_SEL.VALUE_MODE {auto} \ + ] $gt_quad + + } + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant xlconstant_0 ] + set_property -dict [list \ + CONFIG.CONST_VAL {1} \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_0 + + # Create instance: bufg_gt_odiv2, and set properties + set bufg_gt_odiv2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:bufg_gt bufg_gt_odiv2 ] + + # Create instance: util_ds_buf_mbufg_rx_0, and set properties + set util_ds_buf_mbufg_rx_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_mbufg_rx_0 ] + set_property -dict [list \ + CONFIG.C_BUFG_GT_SYNC {true} \ + CONFIG.C_BUF_TYPE {MBUFG_GT} \ + ] $util_ds_buf_mbufg_rx_0 + + + # Create instance: util_ds_buf_mbufg_tx_0, and set properties + set util_ds_buf_mbufg_tx_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_mbufg_tx_0 ] + set_property -dict [list \ + CONFIG.C_BUFGCE_DIV {1} \ + CONFIG.C_BUFG_GT_SYNC {true} \ + CONFIG.C_BUF_TYPE {MBUFG_GT} \ + ] $util_ds_buf_mbufg_tx_0 + + + # Create instance: xlslice_gt_txpostcursor, and set properties + set xlslice_gt_txpostcursor [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_txpostcursor ] + set_property -dict [list \ + CONFIG.DIN_FROM {23} \ + CONFIG.DIN_TO {18} \ + ] $xlslice_gt_txpostcursor + + + # Create instance: xlslice_gt_txprecursor, and set properties + set xlslice_gt_txprecursor [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_txprecursor ] + set_property -dict [list \ + CONFIG.DIN_FROM {17} \ + CONFIG.DIN_TO {12} \ + ] $xlslice_gt_txprecursor + + + # Create instance: xlslice_gt_txmaincursor, and set properties + set xlslice_gt_txmaincursor [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_txmaincursor ] + set_property -dict [list \ + CONFIG.DIN_FROM {30} \ + CONFIG.DIN_TO {24} \ + ] $xlslice_gt_txmaincursor + + + # Create instance: xlslice_gt_line_rate, and set properties + set xlslice_gt_line_rate [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_line_rate ] + set_property -dict [list \ + CONFIG.DIN_FROM {8} \ + CONFIG.DIN_TO {1} \ + ] $xlslice_gt_line_rate + + + # Create instance: xlslice_gt_rxcdrhold, and set properties + set xlslice_gt_rxcdrhold [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice: xlslice_gt_rxcdrhold ] + set_property -dict [list \ + CONFIG.DIN_FROM {31} \ + CONFIG.DIN_TO {31} \ + ] $xlslice_gt_rxcdrhold + + + # Create instance: xlslice_gt_loopback, and set properties + set xlslice_gt_loopback [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_loopback ] + set_property -dict [list \ + CONFIG.DIN_FROM {11} \ + CONFIG.DIN_TO {9} \ + ] $xlslice_gt_loopback + + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins qsfp_clk_322mhz] [get_bd_intf_pins util_ds_buf_0/CLK_IN_D1] + + # Create port connections + connect_bd_net [get_bd_pins gt_control_pins] [get_bd_pins xlslice_gt_txpostcursor/Din] [get_bd_pins xlslice_gt_txprecursor/Din] [get_bd_pins xlslice_gt_txmaincursor/Din] [get_bd_pins xlslice_gt_line_rate/Din] [get_bd_pins xlslice_gt_rxcdrhold/Din] [get_bd_pins xlslice_gt_loopback/Din] + connect_bd_net [get_bd_pins bufg_gt_odiv2/usrclk] [get_bd_pins GT0_ref_clk] + connect_bd_net [get_bd_pins MBUFG_GT_CLR] [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_CLR] + connect_bd_net [get_bd_pins MBUFG_GT_CLRB_LEAF] [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_CLRB_LEAF] + connect_bd_net [get_bd_pins MBUFG_GT_CLR1] [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_CLR] + connect_bd_net [get_bd_pins MBUFG_GT_CLRB_LEAF1] [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_CLRB_LEAF] + connect_bd_net [get_bd_pins gt0_quad/ch0_rxoutclk] [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_I] + connect_bd_net [get_bd_pins gt0_quad/ch0_txoutclk] [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_I] + connect_bd_net [get_bd_pins util_ds_buf_0/IBUFDS_GTME5_ODIV2] [get_bd_pins bufg_gt_odiv2/outclk] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_O1] [get_bd_pins qsfp0_rx_usr_clk_664mhz] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_O2] [get_bd_pins qsfp0_rx_usr_clk_332mhz] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_O1] [get_bd_pins qsfp0_tx_usr_clk_664mhz] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_O2] [get_bd_pins qsfp0_tx_usr_clk_332mhz] + connect_bd_net [get_bd_pins xlconstant_0/dout] [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_CE] [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_CE] + + foreach idx ${list_quad_index} { + connect_bd_net [get_bd_pins apb3clk_quad] [get_bd_pins gt${idx}_quad/apb3clk] + connect_bd_net [get_bd_pins gt${idx}_ch0_iloreset] [get_bd_pins gt${idx}_quad/ch0_iloreset] + connect_bd_net [get_bd_pins gt${idx}_ch1_iloreset] [get_bd_pins gt${idx}_quad/ch1_iloreset] + connect_bd_net [get_bd_pins gt${idx}_ch2_iloreset] [get_bd_pins gt${idx}_quad/ch2_iloreset] + connect_bd_net [get_bd_pins gt${idx}_ch3_iloreset] [get_bd_pins gt${idx}_quad/ch3_iloreset] + connect_bd_net [get_bd_pins hsclk_pllreset${idx}] [get_bd_pins gt${idx}_quad/hsclk1_lcpllreset] [get_bd_pins gt${idx}_quad/hsclk0_rpllreset] [get_bd_pins gt${idx}_quad/hsclk1_rpllreset] [get_bd_pins gt${idx}_quad/hsclk0_lcpllreset] + + connect_bd_net [get_bd_pins gt${idx}_quad/ch0_iloresetdone] [get_bd_pins gt${idx}_ch0_iloresetdone] + connect_bd_net [get_bd_pins gt${idx}_quad/ch1_iloresetdone] [get_bd_pins gt${idx}_ch1_iloresetdone] + connect_bd_net [get_bd_pins gt${idx}_quad/ch2_iloresetdone] [get_bd_pins gt${idx}_ch2_iloresetdone] + connect_bd_net [get_bd_pins gt${idx}_quad/ch3_iloresetdone] [get_bd_pins gt${idx}_ch3_iloresetdone] + connect_bd_net [get_bd_pins gt${idx}_quad/gtpowergood] [get_bd_pins gtpowergood_${idx}] + connect_bd_net [get_bd_pins gt${idx}_quad/hsclk0_lcplllock] [get_bd_pins hsclk_plllock${idx}] + connect_bd_net [get_bd_pins xlslice_gt_rxcdrhold/Dout] [get_bd_pins gt${idx}_quad/ch1_rxcdrhold] [get_bd_pins gt${idx}_quad/ch2_rxcdrhold] [get_bd_pins gt${idx}_quad/ch3_rxcdrhold] [get_bd_pins gt${idx}_quad/ch0_rxcdrhold] + connect_bd_net [get_bd_pins xlslice_gt_txmaincursor/Dout] [get_bd_pins gt${idx}_quad/ch1_txmaincursor] [get_bd_pins gt${idx}_quad/ch2_txmaincursor] [get_bd_pins gt${idx}_quad/ch3_txmaincursor] [get_bd_pins gt${idx}_quad/ch0_txmaincursor] + connect_bd_net [get_bd_pins xlslice_gt_txpostcursor/Dout] [get_bd_pins gt${idx}_quad/ch1_txpostcursor] [get_bd_pins gt${idx}_quad/ch2_txpostcursor] [get_bd_pins gt${idx}_quad/ch3_txpostcursor] [get_bd_pins gt${idx}_quad/ch0_txpostcursor] + connect_bd_net [get_bd_pins xlslice_gt_txprecursor/Dout] [get_bd_pins gt${idx}_quad/ch1_txprecursor] [get_bd_pins gt${idx}_quad/ch2_txprecursor] [get_bd_pins gt${idx}_quad/ch3_txprecursor] [get_bd_pins gt${idx}_quad/ch0_txprecursor] + connect_bd_net [get_bd_pins s_axi_aresetn] [get_bd_pins gt${idx}_quad/apb3presetn] + connect_bd_net [get_bd_pins xlslice_gt_line_rate/Dout] [get_bd_pins gt${idx}_quad/ch0_rxrate] [get_bd_pins gt${idx}_quad/ch3_txrate] [get_bd_pins gt${idx}_quad/ch3_rxrate] [get_bd_pins gt${idx}_quad/ch2_txrate] [get_bd_pins gt${idx}_quad/ch2_rxrate] [get_bd_pins gt${idx}_quad/ch1_txrate] [get_bd_pins gt${idx}_quad/ch1_rxrate] [get_bd_pins gt${idx}_quad/ch0_txrate] + connect_bd_net [get_bd_pins xlslice_gt_loopback/Dout] [get_bd_pins gt${idx}_quad/ch3_loopback] [get_bd_pins gt${idx}_quad/ch2_loopback] [get_bd_pins gt${idx}_quad/ch1_loopback] [get_bd_pins gt${idx}_quad/ch0_loopback] + + connect_bd_net [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_O2] [get_bd_pins gt${idx}_quad/ch0_txusrclk] [get_bd_pins gt${idx}_quad/ch1_txusrclk] [get_bd_pins gt${idx}_quad/ch2_txusrclk] [get_bd_pins gt${idx}_quad/ch3_txusrclk] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_O2] [get_bd_pins gt${idx}_quad/ch0_rxusrclk] [get_bd_pins gt${idx}_quad/ch1_rxusrclk] [get_bd_pins gt${idx}_quad/ch2_rxusrclk] [get_bd_pins gt${idx}_quad/ch3_rxusrclk] + connect_bd_net [get_bd_pins util_ds_buf_0/IBUFDS_GTME5_O] [get_bd_pins gt${idx}_quad/GT_REFCLK0] + + connect_bd_intf_net [get_bd_intf_pins RX0_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/RX0_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins RX1_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/RX1_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins RX2_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/RX2_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins RX3_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/RX3_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins TX0_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/TX0_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins TX1_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/TX1_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins TX2_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/TX2_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins TX3_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/TX3_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins GT${idx}_Serial] [get_bd_intf_pins gt${idx}_quad/GT_Serial] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Hierarchical cell: control_intf +proc create_hier_cell_control_intf { parentCell nameHier dual_dcmac} { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_control_intf() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_DCMAC + + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type clk clk_out_390 + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -from 31 -to 0 control_gt_rst + create_bd_pin -dir O -from 31 -to 0 tx_datapath_ctrl + create_bd_pin -dir O -from 31 -to 0 rx_datapath_ctrl + create_bd_pin -dir O -from 31 -to 0 reset_txrx_path + create_bd_pin -dir I -from 7 -to 0 gt0_tx_reset_done + create_bd_pin -dir I -from 7 -to 0 gt0_rx_reset_done + create_bd_pin -dir I -from 1 -to 0 gt0powergood + + # Create instance: smartconnect, and set properties + set smartconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect smartconnect ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {5} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect + + # GT dynamic configuration parameters, setting up sensible values + set txmaincursor 52 + set txprecursor 6 + set txpostcursor 6 + + set gt_conf_value [format 0x%X [expr {(${txmaincursor} << 24) + (${txpostcursor} << 18) + (${txprecursor} << 12)}]] + + # Create instance: axi_gpio_gt_control, and set properties + set axi_gpio_gt_control [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_gt_control ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT ${gt_conf_value} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_gt_control + + # Create instance: axi_gpio_datapath, and set properties + set axi_gpio_datapath [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_datapath ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT {0x00000000} \ + CONFIG.C_ALL_OUTPUTS_2 {1} \ + CONFIG.C_IS_DUAL {1} \ + CONFIG.C_DOUT_DEFAULT_2 {0x00000000} \ + ] $axi_gpio_datapath + + # Create instance: axi_gpio_monitor, and set properties + set axi_gpio_monitor [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_monitor ] + set_property -dict [list \ + CONFIG.C_ALL_INPUTS {1} + ] $axi_gpio_monitor + + # Create instance: axi_gpio_reset_txrx, and set properties + set axi_gpio_reset_txrx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_reset_txrx ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT {0x00000000} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_reset_txrx + + set xlconcat_monitor [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_monitor ] + set_property -dict [list \ + CONFIG.IN0_WIDTH {8} \ + CONFIG.IN1_WIDTH {8} \ + CONFIG.IN2_WIDTH {2} \ + CONFIG.IN3_WIDTH {1} \ + CONFIG.NUM_PORTS {4} \ + ] $xlconcat_monitor + + set dualdcmac [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant dualdcmac ] + set_property CONFIG.CONST_VAL {0} $dualdcmac + + if { ${dual_dcmac} == "1" } { + set_property CONFIG.CONST_VAL {1} $dualdcmac + } + + # Create interface connections + connect_bd_intf_net -intf_net m_axi_0 [get_bd_intf_pins M_AXI_DCMAC] [get_bd_intf_pins smartconnect/M00_AXI] + connect_bd_intf_net -intf_net m_axi_1 [get_bd_intf_pins smartconnect/M01_AXI] [get_bd_intf_pins axi_gpio_datapath/S_AXI] + connect_bd_intf_net -intf_net m_axi_2 [get_bd_intf_pins smartconnect/M02_AXI] [get_bd_intf_pins axi_gpio_gt_control/S_AXI] + connect_bd_intf_net -intf_net m_axi_3 [get_bd_intf_pins smartconnect/M03_AXI] [get_bd_intf_pins axi_gpio_monitor/S_AXI] + connect_bd_intf_net -intf_net m_axi_4 [get_bd_intf_pins smartconnect/M04_AXI] [get_bd_intf_pins axi_gpio_reset_txrx/S_AXI] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins smartconnect/S00_AXI] + + # Create port connections + connect_bd_net -net control_gt_rst_gpio_io_o [get_bd_pins axi_gpio_gt_control/gpio_io_o] [get_bd_pins control_gt_rst] + connect_bd_net -net axi_gpio_datapath_gpio_io_o [get_bd_pins axi_gpio_datapath/gpio_io_o] [get_bd_pins rx_datapath_ctrl] + connect_bd_net -net axi_gpio_datapath_gpio2_io_o [get_bd_pins axi_gpio_datapath/gpio2_io_o] [get_bd_pins tx_datapath_ctrl] + connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins clk_out_390] [get_bd_pins smartconnect/aclk1] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins smartconnect/aclk] [get_bd_pins axi_gpio_datapath/s_axi_aclk] [get_bd_pins axi_gpio_monitor/s_axi_aclk] [get_bd_pins axi_gpio_gt_control/s_axi_aclk] [get_bd_pins axi_gpio_reset_txrx/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins smartconnect/aresetn] [get_bd_pins axi_gpio_datapath/s_axi_aresetn] [get_bd_pins axi_gpio_monitor/s_axi_aresetn] [get_bd_pins axi_gpio_gt_control/s_axi_aresetn] [get_bd_pins axi_gpio_reset_txrx/s_axi_aresetn] + connect_bd_net -net qsfp_leds_gpio_io_o [get_bd_pins axi_gpio_reset_txrx/gpio_io_o] [get_bd_pins reset_txrx_path] + + connect_bd_net [get_bd_pins gt0_tx_reset_done] [get_bd_pins xlconcat_monitor/In0] + connect_bd_net [get_bd_pins gt0_rx_reset_done] [get_bd_pins xlconcat_monitor/In1] + connect_bd_net [get_bd_pins gt0powergood] [get_bd_pins xlconcat_monitor/In2] + connect_bd_net [get_bd_pins xlconcat_monitor/dout] [get_bd_pins axi_gpio_monitor/gpio_io_i] + connect_bd_net [get_bd_pins dualdcmac/dout] [get_bd_pins xlconcat_monitor/In3] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: DCMAC_subsys +proc create_hier_cell_DCMAC_subsys { parentCell nameHier dcmac_index dual_dcmac} { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_DCMAC_subsys() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp_clk_322mhz + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp_gt0 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_0 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_0 + + # Additional interfaces for dual DCMAC + if { ${dual_dcmac} == "1" } { + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp_gt1 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_1 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_1 + } + + # Create pins + create_bd_pin -dir I -from 31 -to 0 control_gt_rst + create_bd_pin -dir I -from 31 -to 0 control_rx_datapath + create_bd_pin -dir I -type clk axi_clk_390mhz + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk core_clk_782mhz + create_bd_pin -dir I -from 5 -to 0 -type clk ts_clk_bus_350mhz + create_bd_pin -dir I -from 31 -to 0 control_tx_datapath + create_bd_pin -dir O -from 7 -to 0 gt0_rx_reset_done + create_bd_pin -dir O -from 7 -to 0 gt0_tx_reset_done + create_bd_pin -dir I -type rst aresetn_rx_390mhz + create_bd_pin -dir I -type rst aresetn_tx_390mhz + create_bd_pin -dir O -type gt_usrclk GT0_ref_clk + create_bd_pin -dir O -from 1 -to 0 gt0powergood + + # Create instance: xlslice_gt_reset, and set properties + set xlslice_gt_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_reset ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + ] $xlslice_gt_reset + + # Create instance: rx_alt_serdes, and set properties + set rx_alt_serdes [create_bd_cell -type module -reference clock_to_serdes rx_alt_serdes] + + # Create instance: xlslice_rx_datapath_2, and set properties + set xlslice_rx_datapath_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_rx_datapath_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + ] $xlslice_rx_datapath_2 + + # Create instance: rx_flexif_clk_clock_bus, and set properties + set rx_flexif_clk_clock_bus [create_bd_cell -type module -reference clock_to_clock_bus rx_flexif_clk_clock_bus] + + # Create instance: tx_alt_serdes, and set properties + set tx_alt_serdes [create_bd_cell -type module -reference clock_to_serdes tx_alt_serdes] + + # Create instance: tx_serdes, and set properties + set tx_serdes [create_bd_cell -type module -reference clock_to_serdes tx_serdes] + + set dcmac_name "dcmac_${dcmac_index}_core" + + if { ${dcmac_index} == "1" } { + set dcmac_loc "DCMAC_X0Y2" + } else { + set dcmac_loc "DCMAC_X1Y1" + } + + # Create instance: dcmac_core, and set properties + set dcmac_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:dcmac ${dcmac_name} ] + + set_property -dict [list \ + CONFIG.DCMAC_CONFIGURATION_TYPE {Static Configuration} \ + CONFIG.DCMAC_DATA_PATH_INTERFACE_C0 {391MHz Upto 6 Ports} \ + CONFIG.DCMAC_LOCATION_C0 $dcmac_loc \ + CONFIG.DCMAC_MODE_C0 {Coupled MAC+PCS} \ + CONFIG.FAST_SIM_MODE {0} \ + CONFIG.FEC_SLICE0_CFG_C0 {RS(544) CL119} \ + CONFIG.GT_PIPELINE_STAGES {7} \ + CONFIG.GT_REF_CLK_FREQ_C0 {322.265625} \ + CONFIG.GT_TYPE_C0 {GTM} \ + CONFIG.MAC_PORT0_CONFIG_C0 {200GAUI-4} \ + CONFIG.MAC_PORT0_ENABLE_C0 {1} \ + CONFIG.MAC_PORT0_ENABLE_TIME_STAMPING_C0 {0} \ + CONFIG.MAC_PORT0_RX_FLOW_C0 {0} \ + CONFIG.MAC_PORT0_RX_STRIP_C0 {1} \ + CONFIG.MAC_PORT0_TX_FLOW_C0 {0} \ + CONFIG.MAC_PORT0_TX_INSERT_C0 {1} \ + CONFIG.MAC_PORT1_ENABLE_C0 {1} \ + CONFIG.MAC_PORT1_RX_STRIP_C0 {1} \ + CONFIG.MAC_PORT2_ENABLE_C0 {0} \ + CONFIG.MAC_PORT3_ENABLE_C0 {0} \ + CONFIG.MAC_PORT4_ENABLE_C0 {0} \ + CONFIG.MAC_PORT5_ENABLE_C0 {0} \ + CONFIG.NUM_GT_CHANNELS {4} \ + CONFIG.PHY_OPERATING_MODE_C0 {N/A} \ + CONFIG.PORT0_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT0_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT1_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT1_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT2_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT2_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT3_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT3_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT4_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT4_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT5_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT5_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.TIMESTAMP_CLK_PERIOD_NS {4.0000} \ + ] $dcmac_core + + if { ${dual_dcmac} == "1" } { + set_property -dict [list \ + CONFIG.MAC_PORT2_ENABLE_C0 {1} \ + CONFIG.MAC_PORT2_RX_STRIP_C0 {1} \ + CONFIG.MAC_PORT3_ENABLE_C0 {1} \ + CONFIG.MAC_PORT3_RX_STRIP_C0 {1} \ + ] $dcmac_core + } + + # Create instance: dcmac200g_ctl_port + set dcmac200g_ctl_port [create_bd_cell -type module -reference dcmac200g_ctl_port dcmac200g_ctl_port] + + # Create instance: xlslice_tx_datapath_0, and set properties + set xlslice_tx_datapath_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_tx_datapath_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + ] $xlslice_tx_datapath_0 + + # Create instance: xlslice_tx_datapath_1, and set properties + set xlslice_tx_datapath_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_tx_datapath_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + ] $xlslice_tx_datapath_1 + + # Create instance: xlslice_tx_datapath_2, and set properties + set xlslice_tx_datapath_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_tx_datapath_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + ] $xlslice_tx_datapath_2 + + # Create instance: xlslice_rx_datapath_0, and set properties + set xlslice_rx_datapath_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_rx_datapath_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + ] $xlslice_rx_datapath_0 + + # Create instance: tx_flexif_clk_clock_bus, and set properties + set tx_flexif_clk_clock_bus [create_bd_cell -type module -reference clock_to_clock_bus tx_flexif_clk_clock_bus] + + # Create instance: xlslice_tx_datapath_3, and set properties + set xlslice_tx_datapath_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_tx_datapath_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + ] $xlslice_tx_datapath_3 + + # Create instance: rx_serdes, and set properties + set rx_serdes [create_bd_cell -type module -reference clock_to_serdes rx_serdes] + + # Create instance: xlslice_rx_datapath_1, and set properties + set xlslice_rx_datapath_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_rx_datapath_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + ] $xlslice_rx_datapath_1 + + # Create instance: xlslice_rx_datapath_3, and set properties + set xlslice_rx_datapath_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_rx_datapath_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + ] $xlslice_rx_datapath_3 + + # Create instance: gt0_rx_reset_done, and set properties + set gt0_rx_reset_done [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat gt0_rx_reset_done ] + set_property CONFIG.NUM_PORTS {4} $gt0_rx_reset_done + + # Create instance: gt0_tx_reset_done, and set properties + set gt0_tx_reset_done [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat gt0_tx_reset_done ] + set_property CONFIG.NUM_PORTS {4} $gt0_tx_reset_done + + set num_loops [expr {$dual_dcmac}] + + for {set i 0} {$i <= $num_loops} {incr i} { + # Create instance: seg_to_axis, and set properties + create_bd_cell -type module -reference axis_seg_to_unseg_converter "seg_to_axis${i}" + # Create instance: axis_to_seg, and set properties + create_bd_cell -type module -reference axis_unseg_to_seg_converter "axis_to_seg${i}" + + set_property CONFIG.FREQ_HZ 390998840 [get_bd_intf_pins "seg_to_axis${i}/m_axis0_pkt_out"] + set_property CONFIG.FREQ_HZ 390998840 [get_bd_intf_pins "axis_to_seg${i}/s_axis0_pkt_in"] + } + + # Create instance: dcmac_gt0_wrapper + set dcmac_wrapper_name "dcmac_gt${dcmac_index}_wrapper" + create_hier_cell_dcmac_gt_wrapper $hier_obj ${dcmac_wrapper_name} ${dcmac_index} ${dual_dcmac} + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/qsfp_clk_322mhz] [get_bd_intf_pins qsfp_clk_322mhz] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_0] [get_bd_intf_pins ${dcmac_wrapper_name}/RX0_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_1] [get_bd_intf_pins ${dcmac_wrapper_name}/RX1_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_2] [get_bd_intf_pins ${dcmac_wrapper_name}/RX2_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_3] [get_bd_intf_pins ${dcmac_wrapper_name}/RX3_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_0] [get_bd_intf_pins ${dcmac_wrapper_name}/TX0_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_1] [get_bd_intf_pins ${dcmac_wrapper_name}/TX1_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_2] [get_bd_intf_pins ${dcmac_wrapper_name}/TX2_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_3] [get_bd_intf_pins ${dcmac_wrapper_name}/TX3_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins s_axi] [get_bd_intf_pins ${dcmac_name}/s_axi] + + if { ${dual_dcmac} == "1" } { + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_4] [get_bd_intf_pins ${dcmac_wrapper_name}/RX0_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_5] [get_bd_intf_pins ${dcmac_wrapper_name}/RX1_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_6] [get_bd_intf_pins ${dcmac_wrapper_name}/RX2_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_7] [get_bd_intf_pins ${dcmac_wrapper_name}/RX3_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_4] [get_bd_intf_pins ${dcmac_wrapper_name}/TX0_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_5] [get_bd_intf_pins ${dcmac_wrapper_name}/TX1_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_6] [get_bd_intf_pins ${dcmac_wrapper_name}/TX2_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_7] [get_bd_intf_pins ${dcmac_wrapper_name}/TX3_GT1_IP_Interface] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/hsclk_plllock1] [get_bd_pins ${dcmac_name}/plllock_in_1] + connect_bd_net [get_bd_pins ${dcmac_name}/pllreset_out_1] [get_bd_pins ${dcmac_wrapper_name}/hsclk_pllreset1] + + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_4] [get_bd_pins ${dcmac_wrapper_name}/gt1_ch0_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_5] [get_bd_pins ${dcmac_wrapper_name}/gt1_ch1_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_6] [get_bd_pins ${dcmac_wrapper_name}/gt1_ch2_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_7] [get_bd_pins ${dcmac_wrapper_name}/gt1_ch3_iloreset] + + # We need to swap the GT connections for DCMAC1 to make sure the GT aligment is correct + if { ${dcmac_index} == "1" } { + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT1_Serial] [get_bd_intf_pins qsfp_gt0] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT0_Serial] [get_bd_intf_pins qsfp_gt1] + + connect_bd_intf_net [get_bd_intf_pins seg_to_axis1/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg1/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins seg_to_axis0/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg0/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_1] + } else { + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT0_Serial] [get_bd_intf_pins qsfp_gt0] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT1_Serial] [get_bd_intf_pins qsfp_gt1] + + connect_bd_intf_net [get_bd_intf_pins seg_to_axis0/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg0/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins seg_to_axis1/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg1/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_1] + } + } else { + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT0_Serial] [get_bd_intf_pins qsfp_gt0] + connect_bd_intf_net [get_bd_intf_pins seg_to_axis0/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg0/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_0] + } + + # Create port connections + connect_bd_net -net aresetn_axis_seg_in1_1 [get_bd_pins aresetn_tx_390mhz] [get_bd_pins axis_to_seg0/aresetn_axis_seg_in] + connect_bd_net -net aresetn_axis_seg_in_1 [get_bd_pins aresetn_rx_390mhz] [get_bd_pins seg_to_axis0/aresetn_axis_seg_in] + connect_bd_net -net axi_gpio_gt_control_gpio_io_o [get_bd_pins control_gt_rst] [get_bd_pins xlslice_gt_reset/Din] [get_bd_pins ${dcmac_wrapper_name}/gt_control_pins] + connect_bd_net -net axi_gpio_rx_datapath_gpio_io_o [get_bd_pins control_rx_datapath] [get_bd_pins xlslice_rx_datapath_0/Din] [get_bd_pins xlslice_rx_datapath_1/Din] [get_bd_pins xlslice_rx_datapath_3/Din] [get_bd_pins xlslice_rx_datapath_2/Din] + connect_bd_net -net axi_gpio_tx_datapath_gpio_io_o [get_bd_pins control_tx_datapath] [get_bd_pins xlslice_tx_datapath_1/Din] [get_bd_pins xlslice_tx_datapath_2/Din] [get_bd_pins xlslice_tx_datapath_3/Din] [get_bd_pins xlslice_tx_datapath_0/Din] + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins core_clk_782mhz] [get_bd_pins ${dcmac_name}/tx_core_clk] [get_bd_pins ${dcmac_name}/rx_core_clk] + connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins axi_clk_390mhz] [get_bd_pins ${dcmac_name}/rx_axi_clk] [get_bd_pins ${dcmac_name}/tx_axi_clk] [get_bd_pins tx_flexif_clk_clock_bus/clk] [get_bd_pins ${dcmac_name}/rx_macif_clk] [get_bd_pins ${dcmac_name}/tx_macif_clk] [get_bd_pins rx_flexif_clk_clock_bus/clk] [get_bd_pins seg_to_axis0/aclk_axis_seg_in] [get_bd_pins axis_to_seg0/aclk_axis_seg_in] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_0] [get_bd_pins ${dcmac_wrapper_name}/gt0_ch0_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_1] [get_bd_pins ${dcmac_wrapper_name}/gt0_ch1_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_2] [get_bd_pins ${dcmac_wrapper_name}/gt0_ch2_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_3] [get_bd_pins ${dcmac_wrapper_name}/gt0_ch3_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/pllreset_out_0] [get_bd_pins ${dcmac_wrapper_name}/hsclk_pllreset0] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_clr_out_0] [get_bd_pins ${dcmac_wrapper_name}/MBUFG_GT_CLR] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_clrb_leaf_out_0] [get_bd_pins ${dcmac_wrapper_name}/MBUFG_GT_CLRB_LEAF] + connect_bd_net [get_bd_pins ${dcmac_name}/tx_clr_out_0] [get_bd_pins ${dcmac_wrapper_name}/MBUFG_GT_CLR1] + connect_bd_net [get_bd_pins ${dcmac_name}/tx_clrb_leaf_out_0] [get_bd_pins ${dcmac_wrapper_name}/MBUFG_GT_CLRB_LEAF1] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/GT0_ref_clk] [get_bd_pins GT0_ref_clk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/qsfp0_rx_usr_clk_332mhz] [get_bd_pins rx_alt_serdes/usrclk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/qsfp0_rx_usr_clk_664mhz] [get_bd_pins rx_serdes/usrclk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/qsfp0_tx_usr_clk_332mhz] [get_bd_pins tx_alt_serdes/usrclk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/qsfp0_tx_usr_clk_664mhz] [get_bd_pins tx_serdes/usrclk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/hsclk_plllock0] [get_bd_pins ${dcmac_name}/plllock_in_0] + connect_bd_net -net gt_reset_rx_datapath_in_0_1 [get_bd_pins xlslice_rx_datapath_0/Dout] [get_bd_pins ${dcmac_name}/gt_reset_rx_datapath_in_0] + connect_bd_net -net gt_reset_rx_datapath_in_1_1 [get_bd_pins xlslice_rx_datapath_1/Dout] [get_bd_pins ${dcmac_name}/gt_reset_rx_datapath_in_1] + connect_bd_net -net gt_reset_rx_datapath_in_2_1 [get_bd_pins xlslice_rx_datapath_2/Dout] [get_bd_pins ${dcmac_name}/gt_reset_rx_datapath_in_2] + connect_bd_net -net gt_reset_rx_datapath_in_3_1 [get_bd_pins xlslice_rx_datapath_3/Dout] [get_bd_pins ${dcmac_name}/gt_reset_rx_datapath_in_3] + connect_bd_net -net gt_reset_tx_datapath_in_0_1 [get_bd_pins xlslice_tx_datapath_0/Dout] [get_bd_pins ${dcmac_name}/gt_reset_tx_datapath_in_0] + connect_bd_net -net gt_reset_tx_datapath_in_1_1 [get_bd_pins xlslice_tx_datapath_1/Dout] [get_bd_pins ${dcmac_name}/gt_reset_tx_datapath_in_1] + connect_bd_net -net gt_reset_tx_datapath_in_2_1 [get_bd_pins xlslice_tx_datapath_2/Dout] [get_bd_pins ${dcmac_name}/gt_reset_tx_datapath_in_2] + connect_bd_net -net gt_reset_tx_datapath_in_3_1 [get_bd_pins xlslice_tx_datapath_3/Dout] [get_bd_pins ${dcmac_name}/gt_reset_tx_datapath_in_3] + connect_bd_net -net gt0_rx_reset_done_dout [get_bd_pins gt0_rx_reset_done/dout] [get_bd_pins gt0_rx_reset_done] + connect_bd_net -net gt0_tx_reset_done_dout [get_bd_pins gt0_tx_reset_done/dout] [get_bd_pins gt0_tx_reset_done] + connect_bd_net -net rx_flexif_clk_clock_bus_clockbus [get_bd_pins rx_flexif_clk_clock_bus/clockbus] [get_bd_pins ${dcmac_name}/rx_flexif_clk] + connect_bd_net -net rx_serdes_clk2_1 [get_bd_pins rx_alt_serdes/serdes_clk] [get_bd_pins ${dcmac_name}/rx_alt_serdes_clk] + connect_bd_net -net rx_serdes_clk_1 [get_bd_pins rx_serdes/serdes_clk] [get_bd_pins ${dcmac_name}/rx_serdes_clk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins ${dcmac_name}/s_axi_aresetn] [get_bd_pins ${dcmac_wrapper_name}/s_axi_aresetn] + connect_bd_net -net ts_clk_clk_clock_bus_clockbus [get_bd_pins ts_clk_bus_350mhz] [get_bd_pins ${dcmac_name}/ts_clk] + connect_bd_net -net tx_flexif_clk_clock_bus_clockbus [get_bd_pins tx_flexif_clk_clock_bus/clockbus] [get_bd_pins ${dcmac_name}/tx_flexif_clk] + connect_bd_net -net tx_serdes_clk2_1 [get_bd_pins tx_alt_serdes/serdes_clk] [get_bd_pins ${dcmac_name}/tx_alt_serdes_clk] + connect_bd_net -net tx_serdes_clk_1 [get_bd_pins tx_serdes/serdes_clk] [get_bd_pins ${dcmac_name}/tx_serdes_clk] + + for {set i 0} {$i <= $num_loops} {incr i} { + # AXI4 stream converter connections + for {set lane 0} {$lane <= 3} {incr lane} { + set lane_dcmac ${lane} + if { ${i} == "1" } { + set lane_dcmac "[expr {$lane + 4}]" + + } + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegEna${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_ena${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegDat${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tdata${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegSop${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_sop${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegEop${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_eop${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegErr${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_err${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegMty${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_mty${lane_dcmac}] + + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tdata${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegDat${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_ena${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegEna${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_eop${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegEop${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_err${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegErr${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_mty${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegMty${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_sop${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegSop${lane}_in] + save_bd_design + } + } + + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tvalid_0] [get_bd_pins seg_to_axis0/rx_axis_tvalid_i] + connect_bd_net [get_bd_pins ${dcmac_name}/tx_axis_tready_0] [get_bd_pins axis_to_seg0/tx_axis_tready_in] + connect_bd_net [get_bd_pins axis_to_seg0/tx_axis_tvalid_out] [get_bd_pins ${dcmac_name}/tx_axis_tvalid_0] + + for {set lane 0} {$lane <= 3} {incr lane} { + connect_bd_net [get_bd_pins ${dcmac_name}/gt_tx_reset_done_out_${lane}] [get_bd_pins gt0_tx_reset_done/In${lane}] + connect_bd_net [get_bd_pins ${dcmac_name}/gt_rx_reset_done_out_${lane}] [get_bd_pins gt0_rx_reset_done/In${lane}] + } + + for {set id 0} {$id <= 19} {incr id} { + connect_bd_net [get_bd_pins dcmac200g_ctl_port/ctl_tx_vl_marker_id${id}] [get_bd_pins ${dcmac_name}/ctl_vl_marker_id${id}] + } + + if { ${dual_dcmac} == "1" } { + connect_bd_net [get_bd_pins aresetn_tx_390mhz] [get_bd_pins axis_to_seg1/aresetn_axis_seg_in] + connect_bd_net [get_bd_pins aresetn_rx_390mhz] [get_bd_pins seg_to_axis1/aresetn_axis_seg_in] + connect_bd_net [get_bd_pins axi_clk_390mhz] [get_bd_pins seg_to_axis1/aclk_axis_seg_in] [get_bd_pins axis_to_seg1/aclk_axis_seg_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tvalid_2] [get_bd_pins seg_to_axis1/rx_axis_tvalid_i] + connect_bd_net [get_bd_pins ${dcmac_name}/tx_axis_tready_2] [get_bd_pins axis_to_seg1/tx_axis_tready_in] + connect_bd_net [get_bd_pins axis_to_seg1/tx_axis_tvalid_out] [get_bd_pins ${dcmac_name}/tx_axis_tvalid_2] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt1_ch0_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_4] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt1_ch1_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_5] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt1_ch2_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_6] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt1_ch3_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_7] + } + + connect_bd_net [get_bd_pins dcmac200g_ctl_port/default_vl_length_200GE_or_400GE] [get_bd_pins ${dcmac_name}/ctl_rx_custom_vl_length_minus1] [get_bd_pins ${dcmac_name}/ctl_tx_custom_vl_length_minus1] + + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gtpowergood_0] [get_bd_pins ${dcmac_name}/gtpowergood_in] [get_bd_pins gt0powergood] + connect_bd_net [get_bd_pins xlslice_gt_reset/Dout] [get_bd_pins ${dcmac_name}/gt_reset_all_in] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt0_ch0_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_0] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt0_ch1_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_1] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt0_ch2_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_2] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt0_ch3_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_3] + + connect_bd_net [get_bd_pins s_axi_aclk] [get_bd_pins ${dcmac_name}/s_axi_aclk] [get_bd_pins ${dcmac_wrapper_name}/apb3clk_quad] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: clk_n_resets +proc create_hier_cell_clk_n_resets { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_clk_n_resets() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + + # Create pins + create_bd_pin -dir O -type clk clk_out_390 + create_bd_pin -dir I -from 7 -to 0 gt0_tx_reset_done + create_bd_pin -dir I -type clk gt_ref_clk_322mhz + create_bd_pin -dir O -type clk clk_out_782 + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -from 0 -to 0 -type rst aresetn_tx_390mhz + create_bd_pin -dir O -from 0 -to 0 -type rst aresetn_rx_390mhz + create_bd_pin -dir I -from 7 -to 0 gt0_rx_reset_done + create_bd_pin -dir O -from 5 -to 0 clockbus_350 + create_bd_pin -dir I -from 31 -to 0 reset_txrx_path + + # Create instance: syncer_tx_reset, and set properties + set syncer_tx_reset [create_bd_cell -type module -reference dcmac_syncer_reset syncer_tx_reset] + + # Create instance: clk_wizard_0, and set properties + set clk_wizard_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard clk_wizard_0 ] + set_property -dict [list \ + CONFIG.CLKOUT_DRIVES {BUFG,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG} \ + CONFIG.CLKOUT_DYN_PS {None,None,None,None,None,None,None} \ + CONFIG.CLKOUT_GROUPING {Auto,Auto,Auto,Auto,Auto,Auto,Auto} \ + CONFIG.CLKOUT_MATCHED_ROUTING {false,false,false,false,false,false,false} \ + CONFIG.CLKOUT_PORT {clk_out1,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7} \ + CONFIG.CLKOUT_REQUESTED_DUTY_CYCLE {50.000,50.000,50.000,50.000,50.000,50.000,50.000} \ + CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY {782,390.625,350,100.000,100.000,100.000,100.000} \ + CONFIG.CLKOUT_REQUESTED_PHASE {0.000,0.000,0.000,0.000,0.000,0.000,0.000} \ + CONFIG.CLKOUT_USED {true,true,true,false,false,false,false} \ + CONFIG.OVERRIDE_PRIMITIVE {false} \ + CONFIG.PRIM_IN_FREQ {322.265625} \ + CONFIG.PRIM_SOURCE {Global_buffer} \ + CONFIG.USE_LOCKED {true} \ + ] $clk_wizard_0 + + + # Create instance: sys_reset_tx, and set properties + set sys_reset_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_tx ] + + # Create instance: sys_reset_rx, and set properties + set sys_reset_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_rx ] + + # Create instance: syncer_rx_reset, and set properties + set syncer_rx_reset [create_bd_cell -type module -reference dcmac_syncer_reset syncer_rx_reset] + + # Create instance: ts_clk_clk_clock_bus, and set properties + set ts_clk_clk_clock_bus [create_bd_cell -type module -reference clock_to_clock_bus ts_clk_clk_clock_bus] + + # Create instance: util_vector_logic_not, and set properties + set util_vector_logic_not [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic util_vector_logic_not] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {32} \ + ] $util_vector_logic_not + + set xlslice_reset_rx0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_reset_rx0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + ] $xlslice_reset_rx0 + + set xlslice_reset_tx0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_reset_tx0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + ] $xlslice_reset_tx0 + + set xlslice_reset_rx1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_reset_rx1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + ] $xlslice_reset_rx1 + + set xlslice_reset_tx1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_reset_tx1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + ] $xlslice_reset_tx1 + + set xlconcat_rx0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_rx0 ] + set_property -dict [list \ + CONFIG.IN0_WIDTH.VALUE_SRC USER \ + CONFIG.IN1_WIDTH.VALUE_SRC USER \ + CONFIG.IN0_WIDTH {4} \ + CONFIG.IN1_WIDTH {1} \ + ] $xlconcat_rx0 + + set xlconcat_tx0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_tx0 ] + set_property -dict [list \ + CONFIG.IN0_WIDTH.VALUE_SRC USER \ + CONFIG.IN1_WIDTH.VALUE_SRC USER \ + CONFIG.IN0_WIDTH {4} \ + CONFIG.IN1_WIDTH {1} \ + ] $xlconcat_tx0 + + + set and_reduced_rx [create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilreduced_logic and_reduced_rx] + set_property -dict [list \ + CONFIG.C_SIZE {5} \ + ] $and_reduced_rx + + set and_reduced_tx [create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilreduced_logic and_reduced_tx] + set_property -dict [list \ + CONFIG.C_SIZE {5} \ + ] $and_reduced_tx + + # Create port connections + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins clk_wizard_0/clk_out1] [get_bd_pins clk_out_782] + connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins clk_wizard_0/clk_out2] [get_bd_pins clk_out_390] [get_bd_pins sys_reset_tx/slowest_sync_clk] [get_bd_pins sys_reset_rx/slowest_sync_clk] [get_bd_pins syncer_rx_reset/clk] [get_bd_pins syncer_tx_reset/clk] + connect_bd_net -net clk_wizard_0_clk_out3 [get_bd_pins clk_wizard_0/clk_out3] [get_bd_pins ts_clk_clk_clock_bus/clk] + connect_bd_net -net clk_wizard_0_locked [get_bd_pins clk_wizard_0/locked] [get_bd_pins syncer_rx_reset/clk_wizard_lock] [get_bd_pins syncer_tx_reset/clk_wizard_lock] + connect_bd_net -net dcmac_0_gt_wrapper_IBUFDS_ODIV2 [get_bd_pins gt_ref_clk_322mhz] [get_bd_pins clk_wizard_0/clk_in1] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins sys_reset_rx/aux_reset_in] [get_bd_pins sys_reset_tx/aux_reset_in] + connect_bd_net -net syncer_rx_reset_resetn [get_bd_pins syncer_rx_reset/resetn] [get_bd_pins sys_reset_rx/ext_reset_in] + connect_bd_net -net syncer_tx_reset_resetn [get_bd_pins syncer_tx_reset/resetn] [get_bd_pins sys_reset_tx/ext_reset_in] + connect_bd_net -net sys_reset_rx_peripheral_aresetn [get_bd_pins sys_reset_rx/peripheral_aresetn] [get_bd_pins aresetn_rx_390mhz] + connect_bd_net -net sys_reset_tx_peripheral_aresetn [get_bd_pins sys_reset_tx/peripheral_aresetn] [get_bd_pins aresetn_tx_390mhz] + connect_bd_net -net ts_clk_clk_clock_bus_clockbus [get_bd_pins ts_clk_clk_clock_bus/clockbus] [get_bd_pins clockbus_350] + + connect_bd_net [get_bd_pins gt0_rx_reset_done] [get_bd_pins xlconcat_rx0/In0] + connect_bd_net [get_bd_pins xlslice_reset_rx0/Dout] [get_bd_pins xlconcat_rx0/In1] + connect_bd_net [get_bd_pins xlconcat_rx0/dout] [get_bd_pins and_reduced_rx/Op1] + connect_bd_net [get_bd_pins and_reduced_rx/Res] [get_bd_pins syncer_rx_reset/resetn_async] + connect_bd_net [get_bd_pins gt0_tx_reset_done] [get_bd_pins xlconcat_tx0/In0] + connect_bd_net [get_bd_pins xlslice_reset_tx0/Dout] [get_bd_pins xlconcat_tx0/In1] + connect_bd_net [get_bd_pins xlconcat_tx0/dout] [get_bd_pins and_reduced_tx/Op1] + connect_bd_net [get_bd_pins and_reduced_tx/Res] [get_bd_pins syncer_tx_reset/resetn_async] + connect_bd_net [get_bd_pins reset_txrx_path] [get_bd_pins util_vector_logic_not/Op1] + connect_bd_net [get_bd_pins util_vector_logic_not/Res] [get_bd_pins xlslice_reset_rx0/Din] + connect_bd_net [get_bd_pins util_vector_logic_not/Res] [get_bd_pins xlslice_reset_rx1/Din] + connect_bd_net [get_bd_pins util_vector_logic_not/Res] [get_bd_pins xlslice_reset_tx0/Din] + connect_bd_net [get_bd_pins util_vector_logic_not/Res] [get_bd_pins xlslice_reset_tx1/Din] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: qsfp_0_n_1 +proc create_hier_cell_qsfp { parentCell nameHier dcmac_index dual_dcmac} { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_qsfp() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp_clk_322mhz + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp_gt0 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_0 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_0 + + # Additional port for dual DCMAC + if { ${dual_dcmac} == "1" } { + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp_gt1 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_1 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_1 + } + + # Create pins + create_bd_pin -dir I -type clk ap_clk + #create_bd_pin -dir I -type clk ap_clk_eth0 + create_bd_pin -dir I -type rst ap_rst_n + + set num_loops [expr {$dual_dcmac}] + + for {set i 0} {$i <= $num_loops} {incr i} { + # Create instance: adwc0_512_1024, and set properties + set adwc_512_1024 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter "adwc${i}_512_1024" ] + set_property -dict [list \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.M_TDATA_NUM_BYTES {128} \ + CONFIG.S_TDATA_NUM_BYTES {64} \ + CONFIG.TUSER_BITS_PER_BYTE {1} \ + ] $adwc_512_1024 + + # Create instance: adwc0_1024_512, and set properties + set adwc_1024_512 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter "adwc${i}_1024_512" ] + set_property -dict [list \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.M_TDATA_NUM_BYTES {64} \ + CONFIG.S_TDATA_NUM_BYTES {128} \ + CONFIG.TUSER_BITS_PER_BYTE {1} \ + ] $adwc_1024_512 + + # Create instance: tx_packet_fifo_cdc, and set properties + set tx_packet_fifo_cdc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo "tx${i}_packet_fifo_cdc" ] + set_property -dict [list \ + CONFIG.HAS_TLAST.VALUE_SRC USER \ + CONFIG.FIFO_DEPTH {512} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.IS_ACLK_ASYNC {1} \ + ] $tx_packet_fifo_cdc + + # Create instance: rx_fifo_cdc, and set properties + set rx_fifo_cdc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo "rx${i}_fifo_cdc" ] + set_property -dict [list \ + CONFIG.FIFO_DEPTH {128} \ + CONFIG.FIFO_MODE {1} \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.IS_ACLK_ASYNC {1} \ + ] $rx_fifo_cdc + } + # Create instance: clk_n_resets + create_hier_cell_clk_n_resets $hier_obj clk_n_resets + + # Create instance: DCMAC_subsys + create_hier_cell_DCMAC_subsys $hier_obj DCMAC_subsys ${dcmac_index} ${dual_dcmac} + + # Create instance: control_intf + create_hier_cell_control_intf $hier_obj control_intf ${dual_dcmac} + + # Create interface connections + connect_bd_intf_net -intf_net DCMAC_subsys_M_AXIS_0 [get_bd_intf_pins adwc0_1024_512/S_AXIS] [get_bd_intf_pins DCMAC_subsys/M_AXIS_0] + connect_bd_intf_net -intf_net DCMAC_subsys_qsfp_gt [get_bd_intf_pins qsfp_gt0] [get_bd_intf_pins DCMAC_subsys/qsfp_gt0] + connect_bd_intf_net -intf_net adwc0_1024_512_M_AXIS [get_bd_intf_pins adwc0_1024_512/M_AXIS] [get_bd_intf_pins rx0_fifo_cdc/S_AXIS] + connect_bd_intf_net -intf_net rx0_fifo_cdc_M_AXIS [get_bd_intf_pins rx0_fifo_cdc/M_AXIS] [get_bd_intf_pins M_AXIS_0] + connect_bd_intf_net -intf_net adwc0_512_1024_M_AXIS [get_bd_intf_pins adwc0_512_1024/M_AXIS] [get_bd_intf_pins DCMAC_subsys/S_AXIS_0] + connect_bd_intf_net -intf_net m_axi_0 [get_bd_intf_pins control_intf/M_AXI_DCMAC] [get_bd_intf_pins DCMAC_subsys/s_axi] + connect_bd_intf_net -intf_net packet_fifo_M_AXIS [get_bd_intf_pins tx0_packet_fifo_cdc/M_AXIS] [get_bd_intf_pins adwc0_512_1024/S_AXIS] + connect_bd_intf_net -intf_net qsfp_clk_322mhz_1 [get_bd_intf_pins qsfp_clk_322mhz] [get_bd_intf_pins DCMAC_subsys/qsfp_clk_322mhz] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins control_intf/S_AXI] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins control_intf/S_AXI] + connect_bd_intf_net [get_bd_intf_pins S_AXIS_0] [get_bd_intf_pins tx0_packet_fifo_cdc/S_AXIS] + + # Create port connections + connect_bd_net -net axi_gpio_gt_control_gpio_io_o [get_bd_pins control_intf/control_gt_rst] [get_bd_pins DCMAC_subsys/control_gt_rst] + connect_bd_net -net axi_gpio_rx_datapath_gpio_io_o [get_bd_pins control_intf/rx_datapath_ctrl] [get_bd_pins DCMAC_subsys/control_rx_datapath] + connect_bd_net -net axi_gpio_tx_datapath_gpio_io_o [get_bd_pins control_intf/tx_datapath_ctrl] [get_bd_pins DCMAC_subsys/control_tx_datapath] + connect_bd_net [get_bd_pins control_intf/gt0powergood] [get_bd_pins DCMAC_subsys/gt0powergood] + connect_bd_net [get_bd_pins control_intf/reset_txrx_path] [get_bd_pins clk_n_resets/reset_txrx_path] + + connect_bd_net -net gt_ref_clk_322mhz_1 [get_bd_pins DCMAC_subsys/GT0_ref_clk] [get_bd_pins clk_n_resets/gt_ref_clk_322mhz] + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins clk_n_resets/clk_out_782] [get_bd_pins DCMAC_subsys/core_clk_782mhz] + connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins clk_n_resets/clk_out_390] [get_bd_pins adwc0_512_1024/aclk] [get_bd_pins adwc0_1024_512/aclk] [get_bd_pins tx0_packet_fifo_cdc/m_axis_aclk] [get_bd_pins DCMAC_subsys/axi_clk_390mhz] [get_bd_pins control_intf/clk_out_390] [get_bd_pins rx0_fifo_cdc/s_axis_aclk] + connect_bd_net -net gt0_rx_reset_done_dout [get_bd_pins DCMAC_subsys/gt0_rx_reset_done] [get_bd_pins clk_n_resets/gt0_rx_reset_done] [get_bd_pins control_intf/gt0_rx_reset_done] + connect_bd_net -net gt0_tx_reset_done_dout [get_bd_pins DCMAC_subsys/gt0_tx_reset_done] [get_bd_pins clk_n_resets/gt0_tx_reset_done] [get_bd_pins control_intf/gt0_tx_reset_done] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins ap_clk] [get_bd_pins DCMAC_subsys/s_axi_aclk] [get_bd_pins control_intf/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins ap_rst_n] [get_bd_pins clk_n_resets/s_axi_aresetn] [get_bd_pins DCMAC_subsys/s_axi_aresetn] [get_bd_pins control_intf/s_axi_aresetn] + connect_bd_net -net sys_reset_rx_peripheral_aresetn [get_bd_pins clk_n_resets/aresetn_rx_390mhz] [get_bd_pins DCMAC_subsys/aresetn_rx_390mhz] [get_bd_pins adwc0_1024_512/aresetn] [get_bd_pins rx0_fifo_cdc/s_axis_aresetn] + connect_bd_net -net sys_reset_tx_peripheral_aresetn [get_bd_pins clk_n_resets/aresetn_tx_390mhz] [get_bd_pins adwc0_512_1024/aresetn] [get_bd_pins tx0_packet_fifo_cdc/s_axis_aresetn] [get_bd_pins DCMAC_subsys/aresetn_tx_390mhz] + connect_bd_net -net ts_clk_clk_clock_bus_clockbus [get_bd_pins clk_n_resets/clockbus_350] [get_bd_pins DCMAC_subsys/ts_clk_bus_350mhz] + + connect_bd_net [get_bd_pins ap_clk] [get_bd_pins tx0_packet_fifo_cdc/s_axis_aclk] [get_bd_pins rx0_fifo_cdc/m_axis_aclk] + + if { ${dual_dcmac} == "1" } { + connect_bd_intf_net [get_bd_intf_pins qsfp_gt1] [get_bd_intf_pins DCMAC_subsys/qsfp_gt1] + connect_bd_intf_net [get_bd_intf_pins adwc1_1024_512/S_AXIS] [get_bd_intf_pins DCMAC_subsys/M_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins adwc1_512_1024/M_AXIS] [get_bd_intf_pins DCMAC_subsys/S_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins rx1_fifo_cdc/M_AXIS] [get_bd_intf_pins M_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins tx1_packet_fifo_cdc/M_AXIS] [get_bd_intf_pins adwc1_512_1024/S_AXIS] + connect_bd_intf_net [get_bd_intf_pins adwc1_1024_512/M_AXIS] [get_bd_intf_pins rx1_fifo_cdc/S_AXIS] + connect_bd_intf_net [get_bd_intf_pins S_AXIS_1] [get_bd_intf_pins tx1_packet_fifo_cdc/S_AXIS] + + connect_bd_net [get_bd_pins clk_n_resets/clk_out_390] [get_bd_pins adwc1_512_1024/aclk] [get_bd_pins adwc1_1024_512/aclk] [get_bd_pins tx1_packet_fifo_cdc/m_axis_aclk] [get_bd_pins rx1_fifo_cdc/s_axis_aclk] + connect_bd_net [get_bd_pins ap_clk] [get_bd_pins tx1_packet_fifo_cdc/s_axis_aclk] [get_bd_pins rx1_fifo_cdc/m_axis_aclk] + connect_bd_net [get_bd_pins clk_n_resets/aresetn_tx_390mhz] [get_bd_pins adwc1_512_1024/aresetn] [get_bd_pins tx1_packet_fifo_cdc/s_axis_aresetn] + connect_bd_net [get_bd_pins clk_n_resets/aresetn_rx_390mhz] [get_bd_pins adwc1_1024_512/aresetn] [get_bd_pins rx1_fifo_cdc/s_axis_aresetn] + } + + save_bd_design + # Restore current instance + current_bd_instance $oldCurInst +} + +# Generic function that creates the qsfp block +proc create_qsfp_hierarchy { dcmac_index dual_dcmac} { + + if {![string is integer -strict $dcmac_index] || !($dcmac_index == 0 || $dcmac_index == 1)} { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "dcmac_index (with value $dcmac_index) is not correct. Valid values are 0 and 1"} + return + } + + if {![string is integer -strict $dual_dcmac] || !($dual_dcmac == 0 || $dual_dcmac == 1)} { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "dual_dcmac (with value $dual_dcmac) is not correct. Valid values are 0 or 1"} + return + } + + # TODO use dual_dcmac + if { ${dcmac_index} == "0" } { + set new_index $dcmac_index + set offset_increment 0 + } else { + set new_index "[expr {$dcmac_index + 1}]" + set offset_increment 0x1000000 + } + + set qsfp_hier_name "qsfp_${new_index}_n_[expr {$new_index + 1}]" + + create_hier_cell_qsfp [current_bd_instance .] ${qsfp_hier_name} ${dcmac_index} ${dual_dcmac} + save_bd_design + + set qsfp_gt0_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 "qsfp${new_index}_4x" ] + + set qsfp_gt_clk_name [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 "qsfp${new_index}_322mhz" ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {322265625} \ + ] $qsfp_gt_clk_name + save_bd_design + + connect_bd_intf_net [get_bd_intf_ports ${qsfp_gt0_4x}] [get_bd_intf_pins ${qsfp_hier_name}/qsfp_gt0] + if { ${dual_dcmac} == "1" } { + set qsfp_gt1_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 "qsfp[expr {$new_index + 1}]_4x" ] + connect_bd_intf_net [get_bd_intf_ports ${qsfp_gt1_4x}] [get_bd_intf_pins ${qsfp_hier_name}/qsfp_gt1] + } + connect_bd_intf_net [get_bd_intf_ports ${qsfp_gt_clk_name}] [get_bd_intf_pins ${qsfp_hier_name}/qsfp_clk_322mhz] + save_bd_design + + foreach pcie_noc {CPM_PCIE_NOC_0 CPM_PCIE_NOC_1} { + assign_bd_address -offset [expr {0x020302000000 + ${offset_increment}}] -range 256K -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ${qsfp_hier_name}/DCMAC_subsys/dcmac_${dcmac_index}_core/s_axi/Reg] -force + assign_bd_address -offset [expr {0x020302040000 + ${offset_increment}}] -range 256 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ${qsfp_hier_name}/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset [expr {0x020302040200 + ${offset_increment}}] -range 256 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ${qsfp_hier_name}/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset [expr {0x020302040400 + ${offset_increment}}] -range 256 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ${qsfp_hier_name}/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset [expr {0x020302040600 + ${offset_increment}}] -range 256 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ${qsfp_hier_name}/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + save_bd_design + } +} + +# proc add_dcmac {} { +# source "src/dcmac/tcl/dcmac_config.tcl" +# import_files -fileset sources_1 -norecurse "src/dcmac/hdl/axis_seg_to_unseg_converter.v" +# import_files -fileset sources_1 -norecurse "src/dcmac/hdl/clock_to_clock_bus.v" +# import_files -fileset sources_1 -norecurse "src/dcmac/hdl/dcmac200g_ctl_port.v" +# import_files -fileset sources_1 -norecurse "src/dcmac/hdl/serdes_clock.v" +# import_files -fileset sources_1 -norecurse "src/dcmac/hdl/syncer_reset.v" + +# # Create network hierarchy +# if { ${DCMAC0_ENABLED} == "1" } { +# create_qsfp_hierarchy 0 ${DUAL_QSFP_DCMAC0} +# } +# if { ${DCMAC1_ENABLED} == "1" } { +# create_qsfp_hierarchy 1 ${DUAL_QSFP_DCMAC1} +# } +# } + +#add_dcmac \ No newline at end of file diff --git a/linker/resources/dcmac/tcl/dcmac_config.tcl b/linker/resources/dcmac/tcl/dcmac_config.tcl new file mode 100644 index 00000000..82b0afea --- /dev/null +++ b/linker/resources/dcmac/tcl/dcmac_config.tcl @@ -0,0 +1,27 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +# A front view of the V80 and QSFP56 index and associated DCMAC +# Use this diagram to guide the configuration +# +# _________________________ +# | 0 | 1 | 2 | 3 | +# ----------------------------> PCIe +# +# \___________/\__________/ +# | | +# DCMAC0 DCMAC1 + + +### Enable the DCMAC core(s) that you wish to use +set DCMAC0_ENABLED 1 +set DCMAC1_ENABLED 1 + +## Each DCMAC can support 2 QSFP56 interfaces +## select how many QSFP56 you want for each DCMAC, provided they are enabled + +## Setup number of QSFP56 interfaces for DCMAC0 +set DUAL_QSFP_DCMAC0 0 + +## Setup number of QSFP56 interfaces for DCMAC1 +set DUAL_QSFP_DCMAC1 0 diff --git a/linker/resources/service_layer.tcl b/linker/resources/service_layer.tcl new file mode 100644 index 00000000..f56c544a --- /dev/null +++ b/linker/resources/service_layer.tcl @@ -0,0 +1,927 @@ +# Clone /service_layer into {{ service_layer_bd_name }} +set cur_design [current_bd_design] +create_bd_design -boundary_from_container [get_bd_cells /service_layer] {{ service_layer_bd_name }} +current_bd_design $cur_design +set_property -dict [list \ + CONFIG.LIST_SYNTH_BD {service_layer.bd:{{ service_layer_bd_name }}.bd} \ + CONFIG.LIST_SIM_BD {service_layer.bd:{{ service_layer_bd_name }}.bd} \ +] [get_bd_cells /service_layer] +current_bd_design {{ service_layer_bd_name }} + +update_compile_order -fileset sources_1 + + set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_0 + +{% raw %} + set_property -dict [ list \ + CONFIG.APERTURES {{0x203_0000_0000 128M}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_0/M00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_0/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI:S_QDMA_SLAVE_BRIDGE:M_QDMA_SLAVE_BRIDGE:S_VIRT_3:S_VIRT_2:S_VIRT_1:S_VIRT_0} \ + ] [get_bd_pins /axi_noc_0/aclk0] + set_property APERTURES {{0x203_0000_0000 128M}} [get_bd_intf_ports S_AXILITE_INI] + {% endraw %} + + # Create instance: dummy_noc_0, and set properties + set dummy_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_0 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_0/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_0/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_0/aclk0] + + # Create instance: dummy_noc_1, and set properties + set dummy_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_1 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_1/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_1/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_1/aclk0] + + # Create instance: dummy_noc_2, and set properties + set dummy_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_2 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_2/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_2/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_2/aclk0] + + # Create instance: dummy_noc_3, and set properties + set dummy_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_3 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_3/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_3/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_3/aclk0] + + # Create instance: dummy_noc_4, and set properties + set dummy_noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_4 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_4 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_4/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_4/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_4/aclk0] + + # Create instance: dummy_noc_5, and set properties + set dummy_noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_5 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_5 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_5/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_5/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_5/aclk0] + + # Create instance: dummy_noc_6, and set properties + set dummy_noc_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_6 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_6 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_6/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_6/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_6/aclk0] + + # Create instance: dummy_noc_7, and set properties + set dummy_noc_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_7 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_7 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_7/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_7/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_7/aclk0] + + # Create instance: dummy_noc_m_0, and set properties + set dummy_noc_m_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_0/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_0/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_0/aclk0] + + # Create instance: dummy_noc_m_1, and set properties + set dummy_noc_m_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_1/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_1/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_1/aclk0] + + # Create instance: dummy_noc_m_2, and set properties + set dummy_noc_m_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_2/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_2/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_2/aclk0] + + # Create instance: dummy_noc_m_3, and set properties + set dummy_noc_m_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_3/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_3/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_3/aclk0] + + # Create instance: dummy_noc_m_4, and set properties + set dummy_noc_m_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_4/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_4/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_4/aclk0] + + # Create instance: dummy_noc_m_5, and set properties + set dummy_noc_m_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_5/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_5/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_5/aclk0] + + # Create instance: dummy_noc_m_6, and set properties + set dummy_noc_m_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_6/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_6/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_6/aclk0] + + # Create instance: dummy_noc_m_7, and set properties + set dummy_noc_m_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_7/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_7/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_7/aclk0] + +# Create instance: sl2noc_0, and set properties + set sl2noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_0 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_0/aclk0] + + # Create instance: sl2noc_1, and set properties + set sl2noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_1 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_1/aclk0] + + # Create instance: sl2noc_2, and set properties + set sl2noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_2 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_2/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_2/aclk0] + + # Create instance: sl2noc_3, and set properties + set sl2noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_3 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_3/aclk0] + + # Create instance: sl2noc_4, and set properties + set sl2noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_4 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_4/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_4/aclk0] + + # Create instance: sl2noc_5, and set properties + set sl2noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_5 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_5/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_5/aclk0] + + # Create instance: sl2noc_6, and set properties + set sl2noc_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_6 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_6/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_6/aclk0] + + # Create instance: sl2noc_7, and set properties + set sl2noc_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_7 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_7/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_7/aclk0] + +# Create instance: sl2noc_virt_0, and set properties + set sl2noc_virt_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_virt_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_virt_0 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_virt_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_virt_0/aclk0] + + # Create instance: sl2noc_virt_1, and set properties + set sl2noc_virt_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_virt_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_virt_1 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_virt_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_virt_1/aclk0] + + # Create instance: sl2noc_virt_2, and set properties + set sl2noc_virt_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_virt_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_virt_2 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_virt_2/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_virt_2/aclk0] + + # Create instance: sl2noc_virt_3, and set properties + set sl2noc_virt_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 sl2noc_virt_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_virt_3 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_virt_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_virt_3/aclk0] + + set axi_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_4 ] + + + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins dummy_noc_m_0/M00_INIS] [get_bd_intf_pins M_DCMAC_INIS0] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins dummy_noc_m_1/M00_INIS] [get_bd_intf_pins M_DCMAC_INIS1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins dummy_noc_m_2/M00_INIS] [get_bd_intf_pins M_DCMAC_INIS2] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins dummy_noc_m_3/M00_INIS] [get_bd_intf_pins M_DCMAC_INIS3] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins dummy_noc_m_4/M00_INIS] [get_bd_intf_pins M_DCMAC_INIS4] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins dummy_noc_m_5/M00_INIS] [get_bd_intf_pins M_DCMAC_INIS5] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins dummy_noc_m_6/M00_INIS] [get_bd_intf_pins M_DCMAC_INIS6] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins dummy_noc_m_7/M00_INIS] [get_bd_intf_pins M_DCMAC_INIS7] + connect_bd_intf_net -intf_net Conn9 [get_bd_intf_pins dummy_noc_0/S00_INIS] [get_bd_intf_pins S_DCMAC_INIS0] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins dummy_noc_1/S00_INIS] [get_bd_intf_pins S_DCMAC_INIS1] + connect_bd_intf_net -intf_net Conn11 [get_bd_intf_pins dummy_noc_2/S00_INIS] [get_bd_intf_pins S_DCMAC_INIS2] + connect_bd_intf_net -intf_net Conn12 [get_bd_intf_pins dummy_noc_3/S00_INIS] [get_bd_intf_pins S_DCMAC_INIS3] + connect_bd_intf_net -intf_net Conn13 [get_bd_intf_pins dummy_noc_4/S00_INIS] [get_bd_intf_pins S_DCMAC_INIS4] + connect_bd_intf_net -intf_net Conn14 [get_bd_intf_pins dummy_noc_5/S00_INIS] [get_bd_intf_pins S_DCMAC_INIS5] + connect_bd_intf_net -intf_net Conn15 [get_bd_intf_pins dummy_noc_6/S00_INIS] [get_bd_intf_pins S_DCMAC_INIS6] + connect_bd_intf_net -intf_net Conn16 [get_bd_intf_pins dummy_noc_7/S00_INIS] [get_bd_intf_pins S_DCMAC_INIS7] + + connect_bd_intf_net -intf_net sl2noc_virt_0_M00_INI [get_bd_intf_pins M_VIRT_0] [get_bd_intf_pins sl2noc_virt_0/M00_INI] + connect_bd_intf_net -intf_net sl2noc_virt_1_M00_INI [get_bd_intf_pins M_VIRT_1] [get_bd_intf_pins sl2noc_virt_1/M00_INI] + connect_bd_intf_net -intf_net sl2noc_virt_2_M00_INI [get_bd_intf_pins M_VIRT_2] [get_bd_intf_pins sl2noc_virt_2/M00_INI] + connect_bd_intf_net -intf_net sl2noc_virt_3_M00_INI [get_bd_intf_pins M_VIRT_3] [get_bd_intf_pins sl2noc_virt_3/M00_INI] + + connect_bd_intf_net -intf_net sl2noc_0_M00_INI [get_bd_intf_pins SL2NOC_0] [get_bd_intf_pins sl2noc_0/M00_INI] + connect_bd_intf_net -intf_net sl2noc_1_M00_INI [get_bd_intf_pins SL2NOC_1] [get_bd_intf_pins sl2noc_1/M00_INI] + connect_bd_intf_net -intf_net sl2noc_2_M00_INI [get_bd_intf_pins SL2NOC_2] [get_bd_intf_pins sl2noc_2/M00_INI] + connect_bd_intf_net -intf_net sl2noc_3_M00_INI [get_bd_intf_pins SL2NOC_3] [get_bd_intf_pins sl2noc_3/M00_INI] + connect_bd_intf_net -intf_net sl2noc_4_M00_INI [get_bd_intf_pins SL2NOC_4] [get_bd_intf_pins sl2noc_4/M00_INI] + connect_bd_intf_net -intf_net sl2noc_5_M00_INI [get_bd_intf_pins SL2NOC_5] [get_bd_intf_pins sl2noc_5/M00_INI] + connect_bd_intf_net -intf_net sl2noc_6_M00_INI [get_bd_intf_pins SL2NOC_6] [get_bd_intf_pins sl2noc_6/M00_INI] + connect_bd_intf_net -intf_net sl2noc_7_M00_INI [get_bd_intf_pins SL2NOC_7] [get_bd_intf_pins sl2noc_7/M00_INI] + connect_bd_intf_net -intf_net S_AXILITE_INI_1 [get_bd_intf_ports S_AXILITE_INI] [get_bd_intf_pins axi_noc_0/S00_INI] + connect_bd_intf_net -intf_net S_AXI_0_1 [get_bd_intf_ports S_QDMA_SLAVE_BRIDGE] [get_bd_intf_pins axi_register_slice_4/S_AXI] + connect_bd_intf_net -intf_net axi_register_slice_4_M_AXI [get_bd_intf_ports M_QDMA_SLAVE_BRIDGE] [get_bd_intf_pins axi_register_slice_4/M_AXI] + connect_bd_net -net aresetn0_1 [get_bd_pins ap_rst_n] \ + [get_bd_pins axi_register_slice_4/aresetn] + + connect_bd_net -net aclk0_1 [get_bd_pins aclk0] \ + [get_bd_pins dummy_noc_0/aclk0] \ + [get_bd_pins dummy_noc_1/aclk0] \ + [get_bd_pins dummy_noc_2/aclk0] \ + [get_bd_pins dummy_noc_3/aclk0] \ + [get_bd_pins dummy_noc_4/aclk0] \ + [get_bd_pins dummy_noc_5/aclk0] \ + [get_bd_pins dummy_noc_6/aclk0] \ + [get_bd_pins dummy_noc_7/aclk0] \ + [get_bd_pins dummy_noc_m_0/aclk0] \ + [get_bd_pins dummy_noc_m_1/aclk0] \ + [get_bd_pins dummy_noc_m_2/aclk0] \ + [get_bd_pins dummy_noc_m_3/aclk0] \ + [get_bd_pins dummy_noc_m_4/aclk0] \ + [get_bd_pins dummy_noc_m_5/aclk0] \ + [get_bd_pins dummy_noc_m_6/aclk0] \ + [get_bd_pins dummy_noc_m_7/aclk0] \ + [get_bd_pins sl2noc_0/aclk0] \ + [get_bd_pins sl2noc_1/aclk0] \ + [get_bd_pins sl2noc_2/aclk0] \ + [get_bd_pins sl2noc_3/aclk0] \ + [get_bd_pins sl2noc_4/aclk0] \ + [get_bd_pins sl2noc_5/aclk0] \ + [get_bd_pins sl2noc_6/aclk0] \ + [get_bd_pins sl2noc_7/aclk0] \ + [get_bd_pins sl2noc_virt_0/aclk0] \ + [get_bd_pins sl2noc_virt_1/aclk0] \ + [get_bd_pins sl2noc_virt_2/aclk0] \ + [get_bd_pins sl2noc_virt_3/aclk0] \ + [get_bd_pins axi_noc_0/aclk0] \ + [get_bd_pins axi_register_slice_4/aclk] + + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_0/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_0/S00_AXI] + + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_1/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_1/S00_AXI] + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_2/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_2/S00_AXI] + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_3/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_3/S00_AXI] + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_4/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_4/S00_AXI] + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_5/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_5/S00_AXI] + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_6/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_6/S00_AXI] + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_7/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_7/S00_AXI] + + + +proc add_dcmac_inst {} { + + set DCMAC0_ENABLED 1 + set DCMAC1_ENABLED 1 + + ## Each DCMAC can support 2 QSFP56 interfaces + ## select how many QSFP56 you want for each DCMAC, provided they are enabled + + ## Setup number of QSFP56 interfaces for DCMAC0 + set DUAL_QSFP_DCMAC0 0 + + ## Setup number of QSFP56 interfaces for DCMAC1 + set DUAL_QSFP_DCMAC1 0 + + # Create network hierarchy + if { ${DCMAC0_ENABLED} == "1" } { + create_qsfp_hierarchy 0 ${DUAL_QSFP_DCMAC0} + } + if { ${DCMAC1_ENABLED} == "1" } { + create_qsfp_hierarchy 1 ${DUAL_QSFP_DCMAC1} + } +} +# ===== Service Layer (generated) ===== +# create_service_layer "" + +# Absolute paths (normalized) +set ::slash_proj_root [file normalize "{{ proj_root }}"] +set ::slash_dcmac_tcl [file normalize "{{ dcmac_tcl }}"] +set ::slash_dcmac_hdl [file normalize "{{ dcmac_hdl_dir }}"] + +# Source the DCMAC Tcl helpers +source $::slash_dcmac_tcl + +# Optional HDL imports (comment out lines below to skip) +{% for vf in dcmac_hdl_files %} +#import_files -fileset sources_1 -norecurse [file normalize "{{ vf }}"] +{% endfor %} + +# --- Drive DCMAC creation based on config --- +{% if needs_dcmac %} + set DCMAC0_ENABLED {{ dc_enable_0 }} + set DCMAC1_ENABLED {{ dc_enable_1 }} + set DUAL_QSFP_DCMAC0 {{ dual_qsfp_0 }} + set DUAL_QSFP_DCMAC1 {{ dual_qsfp_1 }} + + # Calls proc add_dcmac_inst which expects the above variables + add_dcmac_inst +{% else %} + set DCMAC0_ENABLED 0 + set DCMAC1_ENABLED 0 + set DUAL_QSFP_DCMAC0 0 + set DUAL_QSFP_DCMAC1 0 + # Ethernet disabled; no DCMAC hierarchy created. +{% endif %} + +# === AXI-Lite SmartConnect for service_layer control === +# === AXI-Lite SmartConnect for service_layer control === +{% if sl_have_xbar %} + current_bd_design service_layer_user + + # Create SmartConnect inside the service_layer BD with a local name + create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 + set_property -dict [list \ + CONFIG.NUM_CLKS {{ "{" ~ sl_num_clks ~ "}" }} \ + CONFIG.NUM_MI {{ "{" ~ sl_num_mi ~ "}" }} \ + CONFIG.NUM_SI {{ "{" ~ sl_num_si ~ "}" }} \ + ] [get_bd_cells smartconnect_0] + # Rename for convenience + set_property name {{ sl_smartconnect_name }} [get_bd_cells smartconnect_0] + + # Clocks & reset (design pins to SC pins) + connect_bd_net [get_bd_pins {{ sl_clk0 }}] [get_bd_pins {{ sl_smartconnect_name }}/aclk] + connect_bd_net [get_bd_pins {{ sl_clk1 }}] [get_bd_pins {{ sl_smartconnect_name }}/aclk1] + connect_bd_net [get_bd_pins {{ sl_rstn }}] [get_bd_pins {{ sl_smartconnect_name }}/aresetn] + + # SI: service_layer design's S_AXILITE -> SmartConnect S00_AXI + connect_bd_intf_net \ + [get_bd_intf_pins {{ sl_si_src_if }}] \ + [get_bd_intf_pins {{ sl_smartconnect_name }}/S00_AXI] + + # MI: fan-out to DCMAC hierarchies' s_axi + {% for tgt in sl_mi_targets %} + {% set idx = "%02d"|format(loop.index0) %} + connect_bd_intf_net \ + [get_bd_intf_pins {{ sl_smartconnect_name }}/M{{ idx }}_AXI] \ + [get_bd_intf_pins {{ tgt }}] + {% endfor %} + + # Tie QSFP block clocks/resets: ap_clk -> aclk0, ap_rst_n -> service ap_rst_n + {% for q in sl_qsfp_blocks %} + connect_bd_net [get_bd_pins {{ sl_clk0 }}] [get_bd_pins {{ q }}/ap_clk] + connect_bd_net [get_bd_pins {{ sl_rstn }}] [get_bd_pins {{ q }}/ap_rst_n] + {% endfor %} + +{% else %} + # No AXI-Lite users: create a dummy SmartConnect with clocks+reset, + # connect S_AXILITE -> S00_AXI, but leave the single M00_AXI unconnected. + # current_bd_design service_layer_user + + # create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 + # set_property -dict [list \ + # CONFIG.NUM_CLKS {2} \ + # CONFIG.NUM_MI {1} \ + # CONFIG.NUM_SI {1} \ + # ] [get_bd_cells smartconnect_0] + # set_property name {{ sl_smartconnect_name }} [get_bd_cells smartconnect_0] + + # # Clocks & reset + # connect_bd_net [get_bd_pins aclk0] [get_bd_pins {{ sl_smartconnect_name }}/aclk] + # connect_bd_net [get_bd_pins aclk1] [get_bd_pins {{ sl_smartconnect_name }}/aclk1] + # connect_bd_net [get_bd_pins ap_rst_n] [get_bd_pins {{ sl_smartconnect_name }}/aresetn] + + # # SI: service_layer design's S_AXILITE -> SmartConnect S00_AXI + # connect_bd_intf_net \ + # [get_bd_intf_pins axi_noc_0/M00_AXI] \ + # [get_bd_intf_pins {{ sl_smartconnect_name }}/S00_AXI] + + # M00_AXI intentionally left unconnected + +{% endif %} + + +# === QSFP <-> NoC AXIS links (inside service_layer) === +{% if sl_axis_noc_links %} + # Enter service_layer hierarchy + set __oldCurInst [current_bd_instance .] + current_bd_instance [get_bd_cells /service_layer] + + {% for L in sl_axis_noc_links %} + # Link: {{ L.src_pin }} -> {{ L.dst_pin }} + set __src [get_bd_intf_pins {{ L.src_pin }}] + set __dst [get_bd_intf_pins {{ L.dst_pin }}] + if { $__src eq "" } { + error "AXIS source pin '{{ L.src_pin }}' not found in service_layer." + } + if { $__dst eq "" } { + error "AXIS dest pin '{{ L.dst_pin }}' not found in service_layer." + } + connect_bd_intf_net $__src $__dst + {% endfor %} + + # Restore previous instance + current_bd_instance $__oldCurInst +{% else %} + # No QSFP <-> NoC links required +{% endif %} + +# @TODO: change this when virtualization core is available. +# === Temporary VIRT wiring: S_VIRT_x -> sl2noc_virt_x/S00_AXI === +current_bd_design service_layer_user +for {set i 0} {$i < 4} {incr i} { + set sv [get_bd_intf_pins S_VIRT_$i] + set noc_in [get_bd_intf_pins sl2noc_virt_$i/S00_AXI] + + if { $sv eq "" } { + puts "Info: service_layer: S_VIRT_$i not present; skipping." + continue + } + if { $noc_in eq "" } { + puts "Info: service_layer: sl2noc_virt_$i/S00_AXI not present; skipping." + continue + } + connect_bd_intf_net $sv $noc_in +} + +assign_bd_address +validate_bd_design +save_bd_design +current_bd_design [get_bd_designs top] +validate_bd_design +save_bd_design + +# ===== End Service Layer ===== diff --git a/linker/resources/slash.tcl b/linker/resources/slash.tcl new file mode 100644 index 00000000..90ba5930 --- /dev/null +++ b/linker/resources/slash.tcl @@ -0,0 +1,1066 @@ +# Clone /slash into {{ slash_bd_name }} +set cur_design [current_bd_design] +create_bd_design -boundary_from_container [get_bd_cells /slash] {{ slash_bd_name }} +current_bd_design $cur_design +set_property -dict [list \ + CONFIG.LIST_SYNTH_BD {slash_base.bd:{{ slash_bd_name }}.bd} \ + CONFIG.LIST_SIM_BD {slash_base.bd:{{ slash_bd_name }}.bd} \ +] [get_bd_cells /slash] +current_bd_design {{ slash_bd_name }} + +update_compile_order -fileset sources_1 +# Create instance: ddr_noc_0, and set properties + set ddr_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 ddr_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_0/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_0/aclk0] + + # Create instance: ddr_noc_1, and set properties + set ddr_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 ddr_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_1/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_1/aclk0] + + # Create instance: ddr_noc_2, and set properties + set ddr_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 ddr_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_2/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_2/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_2/aclk0] + + # Create instance: ddr_noc_3, and set properties + set ddr_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 ddr_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_3/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_3/aclk0] + + # Create instance: hbm_vnoc_00, and set properties + set hbm_vnoc_00 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_00 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_00 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_00/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_00/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_00/aclk0] + + # Create instance: hbm_vnoc_01, and set properties + set hbm_vnoc_01 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_01 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_01 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_01/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_01/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_01/aclk0] + + # Create instance: hbm_vnoc_02, and set properties + set hbm_vnoc_02 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_02 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_02 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_02/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_02/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_02/aclk0] + + # Create instance: hbm_vnoc_03, and set properties + set hbm_vnoc_03 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_03 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_03 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_03/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_03/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_03/aclk0] + + # Create instance: hbm_vnoc_04, and set properties + set hbm_vnoc_04 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_04 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_04 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_04/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_04/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_04/aclk0] + + # Create instance: hbm_vnoc_05, and set properties + set hbm_vnoc_05 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_05 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_05 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_05/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_05/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_05/aclk0] + + # Create instance: hbm_vnoc_06, and set properties + set hbm_vnoc_06 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_06 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_06 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_06/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_06/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_06/aclk0] + + # Create instance: hbm_vnoc_07, and set properties + set hbm_vnoc_07 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_07 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_07 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_07/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_07/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_07/aclk0] + + # Create instance: dcmac_axis_noc_0, and set properties + set dcmac_axis_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_0/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_0/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_0/aclk0] + + # Create instance: dcmac_axis_noc_1, and set properties + set dcmac_axis_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_1/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_1/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_1/aclk0] + + # Create instance: dcmac_axis_noc_2, and set properties + set dcmac_axis_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_2/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_2/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_2/aclk0] + + # Create instance: dcmac_axis_noc_3, and set properties + set dcmac_axis_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_3/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_3/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_3/aclk0] + + # Create instance: dcmac_axis_noc_4, and set properties + set dcmac_axis_noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_4/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_4/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_4/aclk0] + + # Create instance: dcmac_axis_noc_5, and set properties + set dcmac_axis_noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_5/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_5/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_5/aclk0] + + # Create instance: dcmac_axis_noc_6, and set properties + set dcmac_axis_noc_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_6/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_6/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_6/aclk0] + + # Create instance: dcmac_axis_noc_7, and set properties + set dcmac_axis_noc_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_7/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_7/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_7/aclk0] + + # Create instance: dcmac_axis_noc_s_0, and set properties + set dcmac_axis_noc_s_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_0 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_0/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_0/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_0/aclk0] + + # Create instance: dcmac_axis_noc_s_1, and set properties + set dcmac_axis_noc_s_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_1 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_1 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_1/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_1/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_1/aclk0] + + # Create instance: dcmac_axis_noc_s_2, and set properties + set dcmac_axis_noc_s_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_2 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_2 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_2/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_2/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_2/aclk0] + + # Create instance: dcmac_axis_noc_s_3, and set properties + set dcmac_axis_noc_s_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_3 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_3 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_3/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_3/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_3/aclk0] + + # Create instance: dcmac_axis_noc_s_4, and set properties + set dcmac_axis_noc_s_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_4 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_4 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_4/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_4/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_4/aclk0] + + # Create instance: dcmac_axis_noc_s_5, and set properties + set dcmac_axis_noc_s_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_5 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_5 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_5/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_5/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_5/aclk0] + + # Create instance: dcmac_axis_noc_s_6, and set properties + set dcmac_axis_noc_s_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_6 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_6 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_6/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_6/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_6/aclk0] + + # Create instance: dcmac_axis_noc_s_7, and set properties + set dcmac_axis_noc_s_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_7 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_7 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_7/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_7/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_7/aclk0] + + set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_0 + +{% raw %} +set_property -dict [ list \ + CONFIG.APERTURES {{0x202_0000_0000 128M}} \ + CONFIG.CATEGORY {pl} \ +] [get_bd_intf_pins /axi_noc_0/M00_AXI] +{% endraw %} + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_0/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_0/aclk0] + + connect_bd_intf_net -intf_net S_AXILITE_INI_1 [get_bd_intf_ports S_AXILITE_INI] [get_bd_intf_pins axi_noc_0/S00_INI] + connect_bd_intf_net -intf_net S00_INIS_0_1 [get_bd_intf_ports S_DCMAC_INIS0] [get_bd_intf_pins dcmac_axis_noc_s_0/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_1_1 [get_bd_intf_ports S_DCMAC_INIS1] [get_bd_intf_pins dcmac_axis_noc_s_1/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_2_1 [get_bd_intf_ports S_DCMAC_INIS2] [get_bd_intf_pins dcmac_axis_noc_s_2/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_3_1 [get_bd_intf_ports S_DCMAC_INIS3] [get_bd_intf_pins dcmac_axis_noc_s_3/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_4_1 [get_bd_intf_ports S_DCMAC_INIS4] [get_bd_intf_pins dcmac_axis_noc_s_4/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_5_1 [get_bd_intf_ports S_DCMAC_INIS5] [get_bd_intf_pins dcmac_axis_noc_s_5/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_6_1 [get_bd_intf_ports S_DCMAC_INIS6] [get_bd_intf_pins dcmac_axis_noc_s_6/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_7_1 [get_bd_intf_ports S_DCMAC_INIS7] [get_bd_intf_pins dcmac_axis_noc_s_7/S00_INIS] + + connect_bd_intf_net -intf_net ddr_noc_0_M00_INI [get_bd_intf_ports M00_INI] [get_bd_intf_pins ddr_noc_0/M00_INI] + connect_bd_intf_net -intf_net ddr_noc_1_M00_INI [get_bd_intf_ports M01_INI] [get_bd_intf_pins ddr_noc_1/M00_INI] + connect_bd_intf_net -intf_net ddr_noc_2_M00_INI [get_bd_intf_ports M02_INI] [get_bd_intf_pins ddr_noc_2/M00_INI] + connect_bd_intf_net -intf_net ddr_noc_3_M00_INI [get_bd_intf_ports M03_INI] [get_bd_intf_pins ddr_noc_3/M00_INI] + + connect_bd_intf_net -intf_net hbm_vnoc_00_M00_INI [get_bd_intf_ports HBM_VNOC_INI_00] [get_bd_intf_pins hbm_vnoc_00/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_01_M00_INI [get_bd_intf_ports HBM_VNOC_INI_01] [get_bd_intf_pins hbm_vnoc_01/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_02_M00_INI [get_bd_intf_ports HBM_VNOC_INI_02] [get_bd_intf_pins hbm_vnoc_02/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_03_M00_INI [get_bd_intf_ports HBM_VNOC_INI_03] [get_bd_intf_pins hbm_vnoc_03/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_04_M00_INI [get_bd_intf_ports HBM_VNOC_INI_04] [get_bd_intf_pins hbm_vnoc_04/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_05_M00_INI [get_bd_intf_ports HBM_VNOC_INI_05] [get_bd_intf_pins hbm_vnoc_05/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_06_M00_INI [get_bd_intf_ports HBM_VNOC_INI_06] [get_bd_intf_pins hbm_vnoc_06/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_07_M00_INI [get_bd_intf_ports HBM_VNOC_INI_07] [get_bd_intf_pins hbm_vnoc_07/M00_INI] + + connect_bd_intf_net -intf_net dcmac_axis_noc_0_M00_INIS [get_bd_intf_ports M_DCMAC_INIS0] [get_bd_intf_pins dcmac_axis_noc_0/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_1_M00_INIS [get_bd_intf_ports M_DCMAC_INIS1] [get_bd_intf_pins dcmac_axis_noc_1/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_2_M00_INIS [get_bd_intf_ports M_DCMAC_INIS2] [get_bd_intf_pins dcmac_axis_noc_2/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_3_M00_INIS [get_bd_intf_ports M_DCMAC_INIS3] [get_bd_intf_pins dcmac_axis_noc_3/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_4_M00_INIS [get_bd_intf_ports M_DCMAC_INIS4] [get_bd_intf_pins dcmac_axis_noc_4/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_5_M00_INIS [get_bd_intf_ports M_DCMAC_INIS5] [get_bd_intf_pins dcmac_axis_noc_5/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_6_M00_INIS [get_bd_intf_ports M_DCMAC_INIS6] [get_bd_intf_pins dcmac_axis_noc_6/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_7_M00_INIS [get_bd_intf_ports M_DCMAC_INIS7] [get_bd_intf_pins dcmac_axis_noc_7/M00_INIS] + + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_ports aclk1] \ + [get_bd_pins ddr_noc_0/aclk0] \ + [get_bd_pins ddr_noc_3/aclk0] \ + [get_bd_pins ddr_noc_2/aclk0] \ + [get_bd_pins ddr_noc_1/aclk0] \ + [get_bd_pins hbm_vnoc_00/aclk0] \ + [get_bd_pins hbm_vnoc_01/aclk0] \ + [get_bd_pins hbm_vnoc_02/aclk0] \ + [get_bd_pins hbm_vnoc_03/aclk0] \ + [get_bd_pins hbm_vnoc_04/aclk0] \ + [get_bd_pins hbm_vnoc_05/aclk0] \ + [get_bd_pins hbm_vnoc_06/aclk0] \ + [get_bd_pins hbm_vnoc_07/aclk0] \ + [get_bd_pins dcmac_axis_noc_0/aclk0] \ + [get_bd_pins dcmac_axis_noc_1/aclk0] \ + [get_bd_pins dcmac_axis_noc_2/aclk0] \ + [get_bd_pins dcmac_axis_noc_3/aclk0] \ + [get_bd_pins dcmac_axis_noc_4/aclk0] \ + [get_bd_pins dcmac_axis_noc_5/aclk0] \ + [get_bd_pins dcmac_axis_noc_6/aclk0] \ + [get_bd_pins dcmac_axis_noc_7/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_0/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_1/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_2/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_3/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_4/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_5/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_6/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_7/aclk0] \ + [get_bd_pins axi_noc_0/aclk0] + +# === Instantiate kernel IPs === +{% for name, inst in instances.items() %} +set {{ name }} [ create_bd_cell -type ip -vlnv {{ inst.kernel.vlnv }} {{ name }} ] +{% endfor %} + +# === Per-kernel AXI-MM data width tweaks for HBM/VIRT === +{% for p in data_width_params %} +set_property {{ p.param }} {{ "{" ~ p.value ~ "}" }} [get_bd_cells {{ p.inst }}] +{% endfor %} + + +# === Connect kernel clocks to aclk1 === +{% for c in clocks %} +connect_bd_net [get_bd_pins {{ c.src_pin }}] [get_bd_ports aclk1] +{% endfor %} + +# === Connect kernel resets to ap_rst_n === +{% for r in resets %} +connect_bd_net [get_bd_pins {{ r.src_pin }}] [get_bd_ports ap_rst_n] +{% endfor %} + +# === SmartConnects for AXI-Lite control === +{% for sc in smartconnects %} +# Create {{ sc.name }} +set {{ sc.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ sc.name }} ] +set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + CONFIG.NUM_MI {{ '{' ~ sc.num_mi ~ '}' }} \ +] ${{ sc.name }} + +# Clocks/Reset +connect_bd_net [get_bd_pins {{ sc.name }}/aclk] [get_bd_ports s_axi_aclk] +connect_bd_net [get_bd_pins {{ sc.name }}/aclk1] [get_bd_ports aclk1] +connect_bd_net [get_bd_pins {{ sc.name }}/aresetn] [get_bd_ports arstn] + +# SI (slave) connection +{% if sc.si_from.type == 'bd_port' %} +connect_bd_intf_net [get_bd_intf_pins {{ sc.si_from.name }}] [get_bd_intf_pins {{ sc.name }}/S00_AXI] +{% else %} +connect_bd_intf_net [get_bd_intf_pins {{ sc.si_from.prev }}/M{{ "%02d"|format(sc.chain_slot) }}_AXI] [get_bd_intf_pins {{ sc.name }}/S00_AXI] +{% endif %} + +# MI (master) connections to kernel AXI-Lite pins +{% for m in sc.mi %} +connect_bd_intf_net [get_bd_intf_pins {{ sc.name }}/M{{ "%02d"|format(m.slot) }}_AXI] [get_bd_intf_pins {{ m.dst_pin }}] +{% endfor %} + +{% endfor %} + +# === HBM AXI-MM connections === + +# Direct connections (single writer per HBMx) +{% for c in hbm_direct|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ c.src_pin }}] [get_bd_intf_ports {{ c.dst_port }}] +{% endfor %} + +# SmartConnect reduction nodes (NUM_CLKS=1, aclk→aclk1, aresetn→ap_rst_n) +{% for n in hbm_smart_nodes|default([]) %} +# {{ n.name }} (NUM_SI={{ n.num_si }}, NUM_MI=1) +set {{ n.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ n.name }} ] +set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {{ '{' ~ n.num_si ~ '}' }} \ +] ${{ n.name }} + +# Clocks/Reset +connect_bd_net [get_bd_pins {{ n.name }}/aclk] [get_bd_ports aclk1] +connect_bd_net [get_bd_pins {{ n.name }}/aresetn] [get_bd_ports ap_rst_n] + +# Slave interfaces (sources into this node) +{% for si in n.si %} +connect_bd_intf_net [get_bd_intf_pins {{ si.src }}] [get_bd_intf_pins {{ n.name }}/S{{ "%02d"|format(si.slot) }}_AXI] +{% endfor %} + +{% endfor %} + +# Root outputs to HBM ports +{% for r in hbm_smart_roots|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ r.sc_name }}/M00_AXI] [get_bd_intf_ports {{ r.dst_port }}] +{% endfor %} + +# === DDR AXI-MM connections (via Versal NoC) === + +# Direct connects: single writer to a DDRx NoC slave +{% for c in ddr_direct|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ c.src_pin }}] [get_bd_intf_pins {{ c.dst_pin }}] +{% endfor %} + +# SmartConnect reduction nodes (NUM_CLKS=1, aclk→aclk1, aresetn→ap_rst_n) +{% for n in ddr_smart_nodes|default([]) %} +# {{ n.name }} (NUM_SI={{ n.num_si }}, NUM_MI=1) +set {{ n.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ n.name }} ] +set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {{ '{' ~ n.num_si ~ '}' }} \ +] ${{ n.name }} + +# Clocks/Reset +connect_bd_net [get_bd_pins {{ n.name }}/aclk] [get_bd_ports aclk1] +connect_bd_net [get_bd_pins {{ n.name }}/aresetn] [get_bd_ports ap_rst_n] + +# SIs into this SmartConnect +{% for si in n.si %} +connect_bd_intf_net [get_bd_intf_pins {{ si.src }}] [get_bd_intf_pins {{ n.name }}/S{{ "%02d"|format(si.slot) }}_AXI] +{% endfor %} + +{% endfor %} + +# Root outputs to DDR NoC slaves +{% for r in ddr_smart_roots|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ r.sc_name }}/M00_AXI] [get_bd_intf_pins {{ r.dst_pin }}] +{% endfor %} + +# === MEM AXI-MM connections (via VNOC) === + +# Direct connects: single writer to a MEMx VNOC slave +{% for c in mem_direct|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ c.src_pin }}] [get_bd_intf_pins {{ c.dst_pin }}] +{% endfor %} + +# SmartConnect reduction nodes for MEMx (NUM_CLKS=1, aclk→aclk1, aresetn→ap_rst_n) +{% for n in mem_smart_nodes|default([]) %} +# {{ n.name }} (NUM_SI={{ n.num_si }}, NUM_MI=1) +set {{ n.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ n.name }} ] +set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {{ '{' ~ n.num_si ~ '}' }} \ +] ${{ n.name }} + +# Clocks/Reset +connect_bd_net [get_bd_pins {{ n.name }}/aclk] [get_bd_ports aclk1] +connect_bd_net [get_bd_pins {{ n.name }}/aresetn] [get_bd_ports ap_rst_n] + +# SIs into this SmartConnect +{% for si in n.si %} +connect_bd_intf_net [get_bd_intf_pins {{ si.src }}] [get_bd_intf_pins {{ n.name }}/S{{ "%02d"|format(si.slot) }}_AXI] +{% endfor %} + +{% endfor %} + +# Root outputs to VNOC slaves +{% for r in mem_smart_roots|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ r.sc_name }}/M00_AXI] [get_bd_intf_pins {{ r.dst_pin }}] +{% endfor %} + +# === VIRT AXI-MM connections (direct to BD interface ports, like HBM) === + +# Direct connects +{% for c in virt_direct|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ c.src_pin }}] [get_bd_intf_ports {{ c.dst_pin }}] +{% endfor %} + +# SmartConnect reduction nodes (NUM_CLKS=1, aclk→aclk1, aresetn→ap_rst_n) +{% for n in virt_smart_nodes|default([]) %} +# {{ n.name }} (NUM_SI={{ n.num_si }}, NUM_MI=1) +set {{ n.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ n.name }} ] +set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {{ '{' ~ n.num_si ~ '}' }} \ +] ${{ n.name }} + +# Clocks/Reset +connect_bd_net [get_bd_pins {{ n.name }}/aclk] [get_bd_ports aclk1] +connect_bd_net [get_bd_pins {{ n.name }}/aresetn] [get_bd_ports ap_rst_n] + +# SIs +{% for si in n.si %} +connect_bd_intf_net [get_bd_intf_pins {{ si.src }}] [get_bd_intf_pins {{ n.name }}/S{{ "%02d"|format(si.slot) }}_AXI] +{% endfor %} + +# Root output to the VIRT interface **port** +connect_bd_intf_net [get_bd_intf_pins {{ n.name }}/M00_AXI] [get_bd_intf_ports {{ (virt_smart_roots | selectattr('sc_name','equalto', n.name) | map(attribute='dst_pin') | list | first) }}] + +{% endfor %} + +# === AXIS stream connections from config === +{% for e in axis_streams|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ e.src_pin }}] [get_bd_intf_pins {{ e.dst_pin }}] +{% endfor %} + +# === AXIS network: instance -> fabric TX === +{% for e in axis_to_fabric|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ e.src_pin }}] [get_bd_intf_pins {{ e.dst_pin }}] +{% endfor %} + +# === AXIS network: fabric RX -> instance === +{% for e in axis_from_fabric|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ e.src_pin }}] [get_bd_intf_pins {{ e.dst_pin }}] +{% endfor %} + +# === Regular AXIS streams (instance <-> instance) === +{% for e in axis_streams|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ e.src_pin }}] [get_bd_intf_pins {{ e.dst_pin }}] +{% endfor %} + + +# === AXI Register Slice terminators for UNUSED memory endpoints === +{% for t in axi_terminators|default([]) %} +# {{ t.name }} -> {{ t.dst_kind }} {{ t.dst }} +set {{ t.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 {{ t.name }} ] + +# Clock / Reset +connect_bd_net [get_bd_pins {{ t.name }}/aclk] [get_bd_ports aclk1] +connect_bd_net [get_bd_pins {{ t.name }}/aresetn] [get_bd_ports ap_rst_n] + +# Leave S_AXI unconnected on purpose + +# Connect M_AXI to the free destination +{% if t.dst_kind == 'port' %} +connect_bd_intf_net [get_bd_intf_pins {{ t.name }}/M_AXI] [get_bd_intf_ports {{ t.dst }}] +{% else %} +connect_bd_intf_net [get_bd_intf_pins {{ t.name }}/M_AXI] [get_bd_intf_pins {{ t.dst }}] +{% endif %} + +{% endfor %} + +# === HOST aggregation: SmartConnect tree -> QDMA_SLAVE_BRIDGE === +{% if host_sc_defs and host_sc_defs|length > 0 %} + # Create SmartConnect nodes + {% for sc in host_sc_defs %} + create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ sc.name }} + set_property -dict [list \ + CONFIG.NUM_CLKS {{ "{2}" if host_use_two_clks else "{1}" }} \ + CONFIG.NUM_SI {{ "{" ~ sc.num_si ~ "}" }} \ + CONFIG.NUM_MI {1} \ + ] [get_bd_cells {{ sc.name }}] + {% if host_use_two_clks %} + connect_bd_net [get_bd_ports {{ host_clk }}] [get_bd_pins {{ sc.name }}/aclk] + connect_bd_net [get_bd_ports {{ host_clk_aux }}] [get_bd_pins {{ sc.name }}/aclk1] + {% else %} + connect_bd_net [get_bd_ports {{ host_clk }}] [get_bd_pins {{ sc.name }}/aclk] + {% endif %} + connect_bd_net [get_bd_ports {{ host_rstn }}] [get_bd_pins {{ sc.name }}/aresetn] + + # Wire SIs for this stage + {% if sc.si_srcs %} + {% for src in sc.si_srcs %} + {% set idx = "%02d"|format(loop.index0) %} + connect_bd_intf_net \ + [get_bd_intf_pins {{ src }}] \ + [get_bd_intf_pins {{ sc.name }}/S{{ idx }}_AXI] + {% endfor %} + {% elif sc.si_up %} + {% for up in sc.si_up %} + {% set idx = "%02d"|format(loop.index0) %} + connect_bd_intf_net \ + [get_bd_intf_pins {{ up }}] \ + [get_bd_intf_pins {{ sc.name }}/S{{ idx }}_AXI] + {% endfor %} + {% endif %} + {% endfor %} + + # Final M00_AXI -> QDMA_SLAVE_BRIDGE + connect_bd_intf_net \ + [get_bd_intf_pins {{ host_final }}/M00_AXI] \ + [get_bd_intf_ports {{ host_target_rtl }}] + +{% elif host_need_term %} + # No HOST-mapped sources → park QDMA_SLAVE_BRIDGE with an AXI register slice + create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 {{ host_term_name }} + # Clocks & reset + connect_bd_net [get_bd_ports {{ host_clk }}] [get_bd_pins {{ host_term_name }}/aclk] + connect_bd_net [get_bd_ports {{ host_rstn }}] [get_bd_pins {{ host_term_name }}/aresetn] + # Leave S_AXI unconnected, drive M_AXI to QDMA_SLAVE_BRIDGE + connect_bd_intf_net \ + [get_bd_intf_pins {{ host_term_name }}/M_AXI] \ + [get_bd_intf_ports {{ host_target_rtl }}] +{% else %} + # HOST section: nothing to do +{% endif %} + +# === AXI-Lite address map === +{% for a in axilite_addr %} +assign_bd_address -offset {{ "0x%012X"|format(a.offset) }} -range {{ "0x%08X"|format(a.range) }} -target_address_space [get_bd_addr_spaces {{ a.addr_space }}] [get_bd_addr_segs {{ a.inst }}/{{ a.busif }}/{{ a.segment }}] -force +{% endfor %} + +# === Assign all other addresses === +assign_bd_address +validate_bd_design +save_bd_design + +current_bd_design [get_bd_designs top] +validate_bd_design +save_bd_design \ No newline at end of file diff --git a/linker/src/core/bd_ports.py b/linker/src/core/bd_ports.py new file mode 100644 index 00000000..a6500028 --- /dev/null +++ b/linker/src/core/bd_ports.py @@ -0,0 +1,271 @@ +# platform/bd_ports.py +from __future__ import annotations +from dataclasses import dataclass, field +from typing import Dict, Iterable, Optional, List, Tuple +import re + +from core.port import PortType + + +# ----------------------------- +# Data classes +# ----------------------------- + +@dataclass(frozen=True) +class BdPort: + """ + A top-level Block Design port / shell endpoint. + + Attributes: + name: Logical name used by your tool (e.g., "HBM0", "DDR0", "VIRT0", "MEM", "clock", "reset"). + ptype: PortType (AXI4FULL, AXILITE, AXIS, CLOCK, RESET, INTERRUPT). + rtl_name: Actual BD interface/pin name in Vivado (e.g., "HBM_AXI_00", "M00_INI", "VIRT_AXI_00", "ap_clk"). + width: Optional data width (AXI/AXIS). For CLOCK/RESET/INTERRUPT, this is forced to 1. + domain: Optional grouping, inferred from logical name for memory ports ("HBM", "DDR", "VIRT", "MEM"). + index: Optional index for memory groups (e.g., HBM0..63 → 0..63, DDR0..3 → 0..3, VIRT0..3 → 0..3). + For MEM lines, usually None (MEM acts as a multi-entry wildcard). + """ + name: str + ptype: PortType + rtl_name: Optional[str] = None + width: Optional[int] = None + domain: Optional[str] = None + index: Optional[int] = None + + +@dataclass +class BlockDesignPorts: + """ + Registry of BD ports with support for multiple RTL endpoints per logical name + (e.g., a single logical 'MEM' mapping to multiple vNOC INI ports). + """ + ports: Dict[str, List[BdPort]] = field(default_factory=dict) + + # ---- registration ---- + + def add(self, port: BdPort) -> None: + lst = self.ports.setdefault(port.name, []) + # Avoid exact duplicate RTL entry under the same logical name & type + if any(p.rtl_name == port.rtl_name and p.ptype == port.ptype for p in lst): + raise ValueError( + f"BD port '{port.name}' already has RTL '{port.rtl_name}' of type {port.ptype.name}." + ) + lst.append(port) + + def add_many(self, ports: Iterable[BdPort]) -> None: + for p in ports: + self.add(p) + + # ---- lookups ---- + + def get(self, name: str) -> BdPort: + """Return a single port for 'name'. Error if zero or more than one exist.""" + lst = self.ports.get(name, []) + if not lst: + raise KeyError(f"BD port '{name}' not found.") + if len(lst) > 1: + raise ValueError(f"Multiple BD ports registered for '{name}'. Use get_all('{name}').") + return lst[0] + + def get_all(self, name: str) -> List[BdPort]: + """Return all ports for 'name' (useful for 'MEM').""" + lst = self.ports.get(name, []) + if not lst: + raise KeyError(f"BD port '{name}' not found.") + return lst + + def iter_type(self, ptype: PortType): + """Iterate all BdPort entries of a given type across all logical names.""" + for lst in self.ports.values(): + for p in lst: + if p.ptype == ptype: + yield p + + # ---- memory resolution ---- + + def mem_targets(self, domain: str, index: Optional[int] = None) -> List[BdPort]: + """ + Resolve memory target(s) to BdPort(s): + - ('HBM', i) -> [ 'HBM{i}' ] + - ('DDR', i) -> [ 'DDR{i}' ] + - ('VIRT', i) -> [ 'VIRT{i}' ] + - ('MEM', None) -> all 'MEM' entries (file order) + - ('MEM', i) -> the i-th 'MEM' entry (by file order) + """ + d = domain.upper() + if d in ("HBM", "DDR", "VIRT"): + if index is None: + raise ValueError(f"{d} requires an index.") + return [self.get(f"{d}{index}")] + if d == "MEM": + mems = self.get_all("MEM") + if index is None: + return mems + if not (0 <= index < len(mems)): + raise IndexError(f"MEM index {index} out of range (0..{len(mems)-1}).") + return [mems[index]] + if d == "HOST": + # single logical endpoint named 'HOST' in bd_ports.txt + return [self.get("HOST")] + raise ValueError(f"Unknown memory domain '{domain}'.") + + def mem(self, domain: str, index: Optional[int]) -> BdPort: + """ + Back-compat convenience: return a single BdPort. + For MEM, you must pass an index; otherwise use mem_targets('MEM'). + """ + targets = self.mem_targets(domain, index) + if len(targets) != 1: + raise ValueError( + f"mem('{domain}', index={index}) resolved to {len(targets)} ports. " + f"Use mem_targets('{domain}', index) instead." + ) + return targets[0] + + +# ----------------------------- +# Loader from text file +# ----------------------------- + +_TYPE_MAP = { + "AXI4FULL": PortType.AXI4FULL, + "AXILITE": PortType.AXILITE, + "AXIS": PortType.AXIS, + "CLOCK": PortType.CLOCK, + "RESET": PortType.RESET, + "INTERRUPT":PortType.INTERRUPT, +} + +# HBM / DDR / VIRT with trailing index, e.g. HBM12, DDR3, VIRT2 +_RE_LOGICAL_MEM = re.compile(r"^(HBM|DDR|VIRT)(\d+)$", re.IGNORECASE) + +def _parse_ptype(s: str) -> PortType: + try: + return _TYPE_MAP[s.strip().upper()] + except KeyError: + raise ValueError(f"Unknown port type '{s}'. Expected one of {list(_TYPE_MAP)}.") + +def _infer_domain_index(logical_name: str) -> Tuple[Optional[str], Optional[int]]: + """ + Best-effort inference from logical name: + HBM0..HBM63 -> ('HBM', 0..63) + DDR0..DDR3 -> ('DDR', 0..3) + VIRT0..VIRT3 -> ('VIRT', 0..3) + MEM -> ('MEM', None) + HOST -> ('HOST', None) + """ + ln = logical_name.strip() + if ln.upper() == "MEM": + return "MEM", None + if ln.upper() == "HOST": + return "HOST", None + m = _RE_LOGICAL_MEM.match(ln) + if m: + return m.group(1).upper(), int(m.group(2)) + return None, None + +def _parse_width(s: Optional[str]) -> Optional[int]: + if not s: + return None + try: + return int(s, 0) # supports "32", "0x20" + except ValueError: + return None + +def load_bd_ports_from_file(path: str) -> BlockDesignPorts: + """ + File format (one entry per line; comments with # or ; are ignored): + + : [width] + + Examples: + HBM0:HBM_AXI_00 AXI4FULL + DDR0:M00_INI AXI4FULL + VIRT0:VIRT_AXI_00 AXI4FULL + S_AXI_CTRL:S_AXI_CTRL AXILITE 32 + clock:ap_clk CLOCK + reset:ap_rst_n RESET + + # 'MEM' repeated N times (single logical, many RTL endpoints) + MEM:HBM_VNOC_INI_00 AXI4FULL + MEM:HBM_VNOC_INI_01 AXI4FULL + ... + MEM:HBM_VNOC_INI_07 AXI4FULL + """ + bd = BlockDesignPorts() + with open(path, "r", encoding="utf-8") as f: + for ln, raw in enumerate(f, start=1): + line = raw.strip() + if not line or line.startswith("#") or line.startswith(";"): + continue + + # Split ":" and " [width]" + try: + lhs, rhs = line.split(None, 1) + except ValueError: + raise ValueError(f"{path}:{ln}: Expected ': [width]'. Got: {line!r}") + + if ":" not in lhs: + raise ValueError(f"{path}:{ln}: Missing ':' in '{lhs}'. Expected ':'.") + + logical, rtl = [t.strip() for t in lhs.split(":", 1)] + parts = rhs.split() + if len(parts) not in (1, 2): + raise ValueError(f"{path}:{ln}: Invalid RHS. Expected ' [width]'. Got: {rhs!r}") + + ptype = _parse_ptype(parts[0]) + width = _parse_width(parts[1]) if len(parts) == 2 else None + + # Force scalar width for these types + if ptype in (PortType.CLOCK, PortType.RESET, PortType.INTERRUPT): + width = 1 + + domain, index = _infer_domain_index(logical) + bd.add(BdPort( + name=logical, + ptype=ptype, + rtl_name=rtl, + width=width, + domain=domain, + index=index + )) + + return bd + + +# ----------------------------- +# Optional helpers +# ----------------------------- + +def generate_bd_port_lines( + num_hbm: int = 64, + num_ddr: int = 4, + num_mem_vnoc: int = 8, + num_virt: int = 4, +) -> List[str]: + """ + Utility to prefill a mapping file for common shells. + + Returns a list of lines ready to write to a file. Note that 'MEM' is + repeated num_mem_vnoc times with different RTL names, by design. + """ + lines: List[str] = [] + # HBM + for i in range(num_hbm): + lines.append(f"HBM{i}:HBM_AXI_{i:02d} AXI4FULL") + # DDR + for i in range(num_ddr): + lines.append(f"DDR{i}:M{i:02d}_INI AXI4FULL") + # VIRT + for i in range(num_virt): + lines.append(f"VIRT{i}:VIRT_AXI_{i:02d} AXI4FULL") + # Control + clocks/resets + lines += [ + "S_AXI_CTRL:S_AXI_CTRL AXILITE 32", + "clock:ap_clk CLOCK", + "reset:ap_rst_n RESET", + ] + # MEM (vNOC INI) + for i in range(num_mem_vnoc): + lines.append(f"MEM:HBM_VNOC_INI_{i:02d} AXI4FULL") + return lines diff --git a/linker/src/core/connectivity.py b/linker/src/core/connectivity.py new file mode 100644 index 00000000..e077c50e --- /dev/null +++ b/linker/src/core/connectivity.py @@ -0,0 +1,48 @@ +from __future__ import annotations +from dataclasses import dataclass, field +from typing import List + +# ----------------------------- +# Data structures +# ----------------------------- + +@dataclass(frozen=True) +class NKSpec: + kernel_type: str + count: int + instance_names: List[str] + + +@dataclass(frozen=True) +class StreamConnect: + src_inst: str + src_port: str + dst_inst: str + dst_port: str + + +@dataclass(frozen=True) +class MemoryTarget: + domain: str + index: int + + +@dataclass(frozen=True) +class SpMapping: + inst: str + port: str + target: MemoryTarget + + +@dataclass(frozen=True) +class ClockSpec: + inst: str + freq_hz: int + + +@dataclass +class ConnectivityConfig: + nk: List[NKSpec] = field(default_factory=list) + streams: List[StreamConnect] = field(default_factory=list) + sps: List[SpMapping] = field(default_factory=list) + clocks: List[ClockSpec] = field(default_factory=list) diff --git a/linker/src/core/kernel.py b/linker/src/core/kernel.py new file mode 100644 index 00000000..f102fbcf --- /dev/null +++ b/linker/src/core/kernel.py @@ -0,0 +1,74 @@ +from __future__ import annotations +from dataclasses import dataclass, field +from typing import Dict, Iterable, Optional, List + +from core.port import Port, PortType +from core.regs import MemoryMap + +@dataclass(frozen=True) +class Kernel: + """ + Generic kernel/IP *type* definition. + Contains only port definitions — not instance-specific data. + """ + name: str + ports: Dict[str, Port] = field(default_factory=dict) + vlnv: Optional[str] = None + memory_maps: List[MemoryMap] = field(default_factory=list) # NEW + + def port(self, name: str) -> Port: + """Retrieve a port by name.""" + try: + return self.ports[name] + except KeyError as e: + raise KeyError(f"Kernel '{self.name}' has no port named '{name}'.") from e + + def ports_of_type(self, ptype: PortType) -> Iterable[Port]: + """Iterate over all ports of a given type.""" + return (p for p in self.ports.values() if p.ptype == ptype) + + @staticmethod + def from_spec(name: str, spec: Dict[str, Dict]) -> "Kernel": + """ + Build a Kernel from a spec dictionary, for example: + spec = { + "ap_clk": {"ptype": "CLOCK"}, + "ap_rst_n": {"ptype": "RESET"}, + "s_axilite": {"ptype": "AXILITE", "width": 32}, + "m_axi_gmem": {"ptype": "AXI4FULL", "width": 128}, + "axis_in": {"ptype": "AXIS", "width": 64}, + } + """ + type_map = { + "CLOCK": PortType.CLOCK, + "RESET": PortType.RESET, + "AXILITE": PortType.AXILITE, + "AXI4FULL": PortType.AXI4FULL, + "AXIS": PortType.AXIS, + "INTERRUPT": PortType.INTERRUPT, + } + + ports: Dict[str, Port] = {} + for pname, attrs in spec.items(): + ptype = type_map[attrs["ptype"].strip().upper()] + width = attrs.get("width") + ports[pname] = Port(name=pname, ptype=ptype, width=width) + + return Kernel(name=name, ports=ports) + + +@dataclass +class KernelInstance: + """ + A specific instance of a Kernel (e.g., 'dma_0'). + Holds a pointer to the Kernel type and optional parameters. + """ + name: str + kernel: Kernel + params: Dict[str, object] = field(default_factory=dict) + + def port(self, name: str) -> Port: + return self.kernel.port(name) + + def __repr__(self) -> str: + return f"" diff --git a/linker/src/core/port.py b/linker/src/core/port.py new file mode 100644 index 00000000..86f43032 --- /dev/null +++ b/linker/src/core/port.py @@ -0,0 +1,33 @@ +from __future__ import annotations +from dataclasses import dataclass +from enum import Enum, auto +from typing import Optional + + +class PortType(Enum): + """Enumerates the supported port types in the design.""" + CLOCK = auto() + RESET = auto() + AXILITE = auto() + AXI4FULL = auto() + AXIS = auto() + INTERRUPT = auto() # present, but currently unused + + +@dataclass(frozen=True) +class Port: + """ + Represents a single port belonging to a kernel definition. + For AXI/AXIS, width refers to data width (e.g., 32/64/128). + For CLOCK, RESET, and INTERRUPT, width is forced to 1. + """ + name: str + ptype: PortType + width: Optional[int] = None + + def __post_init__(self): + if self.ptype in {PortType.CLOCK, PortType.RESET, PortType.INTERRUPT}: + object.__setattr__(self, "width", 1) + + def __repr__(self) -> str: + return f"" diff --git a/linker/src/core/regs.py b/linker/src/core/regs.py new file mode 100644 index 00000000..6723ea23 --- /dev/null +++ b/linker/src/core/regs.py @@ -0,0 +1,43 @@ +# core/regs.py +from __future__ import annotations +from dataclasses import dataclass, field +from typing import List, Optional + +@dataclass +class RegField: + name: str + description: Optional[str] + bit_offset: int + bit_width: int + access: Optional[str] = None + modified_write_value: Optional[str] = None + read_action: Optional[str] = None + reset_value: Optional[int] = None + +@dataclass +class Register: + name: str + display_name: Optional[str] + description: Optional[str] + address_offset: int + size: int + access: Optional[str] = None + reset_value: Optional[int] = None + fields: List[RegField] = field(default_factory=list) + +@dataclass +class AddressBlock: + name: str + base_address: int + range: int + width: int + usage: Optional[str] = None + access: Optional[str] = None + offset_base_param: Optional[str] = None + offset_high_param: Optional[str] = None + registers: List[Register] = field(default_factory=list) + +@dataclass +class MemoryMap: + name: str + address_blocks: List[AddressBlock] = field(default_factory=list) diff --git a/linker/src/emit/addr_ctx.py b/linker/src/emit/addr_ctx.py new file mode 100644 index 00000000..bb037a69 --- /dev/null +++ b/linker/src/emit/addr_ctx.py @@ -0,0 +1,76 @@ +# emit/addr_ctx.py +from __future__ import annotations +from typing import Dict, List, Optional +from core.kernel import KernelInstance +from core.port import PortType + +def _align_up(x: int, a: int) -> int: + return (x + (a - 1)) & ~(a - 1) + +def _range_for_axilite(inst: KernelInstance, busif: str, default_range: int) -> int: + """ + Try to find a 'register' usage addressBlock under a memoryMap that matches the busif. + Heuristics: + - memoryMap.name equals busif (case-insensitive) → use its first 'register' addressBlock.range + - otherwise, first 'register' block in any map + - fallback to default_range + """ + k = inst.kernel + mmaps = getattr(k, "memory_maps", []) or [] + + # Try exact map by name (case-insensitive) + for mm in mmaps: + if mm.name and mm.name.lower() == busif.lower(): + for ab in mm.address_blocks: + if (ab.usage or "").lower() == "register" and ab.range: + return int(ab.range) + # Otherwise first register block anywhere + for mm in mmaps: + for ab in mm.address_blocks: + if (ab.usage or "").lower() == "register" and ab.range: + return int(ab.range) + + return default_range + +def build_axilite_address_context( + instances: Dict[str, KernelInstance], + *, + addr_space: str = "S_AXILITE_INI", + base_offset: int = 0x0202_0000_0000, # your example + min_align: int = 0x0001_0000 # 64KB alignment +) -> dict: + """ + Returns: + { + "axilite_addr": [ + { "inst": "...", "busif": "S_AXI_CONTROL", "segment": "Reg", + "offset": 0x..., "range": 0x..., "addr_space": "S_AXILITE_INI" }, + ... + ] + } + """ + # Build a stable list (sorted for determinism) + items: List[dict] = [] + next_off = base_offset + + for iname in sorted(instances.keys()): + inst = instances[iname] + # For each AXI-Lite interface on this kernel + for p in inst.kernel.ports_of_type(PortType.AXILITE): + # Decide the range from memory maps (or fallback) + rg = _range_for_axilite(inst, p.name, default_range=min_align) + # Hardware address windows should be aligned to their size (and at least min_align) + align = max(min_align, rg) + next_off = _align_up(next_off, align) + + items.append({ + "inst": iname, + "busif": p.name, + "segment": "Reg", # IP integrator segment for control regs + "offset": next_off, + "range": rg, + "addr_space": addr_space, + }) + next_off += _align_up(rg, align) + + return {"axilite_addr": items} diff --git a/linker/src/emit/ddr_ctx.py b/linker/src/emit/ddr_ctx.py new file mode 100644 index 00000000..db3cd24a --- /dev/null +++ b/linker/src/emit/ddr_ctx.py @@ -0,0 +1,78 @@ +# emit/ddr_ctx.py +from __future__ import annotations +from collections import defaultdict +from typing import Dict, List +from core.kernel import KernelInstance +from core.port import PortType + +def build_ddr_smartconnect_context( + instances: Dict[str, KernelInstance], + *, + max_si: int = 16, + base_name: str = "sc_ddr", + noc_pin_fmt: str = "/ddr_noc_{index}/S00_AXI", # absolute path to NoC slave pin +) -> dict: + """ + Plan SmartConnect reduction per DDR. If only 1 source -> direct connect to + '/ddr_noc_/S00_AXI'. If >1, build a reduction tree with nodes having up to + 'max_si' SIs and 1 MI. + + Returns keys for the template: + - ddr_direct: [{src_pin, dst_pin}] + - ddr_smart_nodes: [{name, num_si, si:[{slot, src}], ...}] + - ddr_smart_roots: [{sc_name, dst_pin}] + """ + # 1) Collect all AXI4FULL kernel pins targeting DDR + by_ddr: Dict[int, List[str]] = defaultdict(list) + for inst in instances.values(): + mem_sp = inst.params.get("mem_sp", {}) + for k_port, tgt in mem_sp.items(): + if tgt.get("domain") == "DDR" and tgt.get("index") is not None: + if inst.kernel.port(k_port).ptype == PortType.AXI4FULL: + by_ddr[int(tgt["index"])].append(f"{inst.name}/{k_port}") + + ddr_direct: List[dict] = [] + ddr_smart_nodes: List[dict] = [] + ddr_smart_roots: List[dict] = [] + + # 2) For each DDR, either direct connect or build a reduction tree + for d_idx in sorted(by_ddr.keys()): + dst_pin = noc_pin_fmt.format(index=d_idx) + sources = by_ddr[d_idx] + + if len(sources) == 1: + ddr_direct.append({"src_pin": sources[0], "dst_pin": dst_pin}) + continue + + # Build reduction tree with <= max_si SIs per node + level = 0 + current = [{"src": s} for s in sources] + root_sc_name = None + + while len(current) > 1: + groups = [current[i:i + max_si] for i in range(0, len(current), max_si)] + next_level = [] + + for g_idx, group in enumerate(groups): + sc_name = f"{base_name}_{d_idx}_{level}_{g_idx}" + node = { + "name": sc_name, + "num_si": len(group), + "si": [{"slot": i, "src": g["src"]} for i, g in enumerate(group)], + } + ddr_smart_nodes.append(node) + # Output of this SC is M00_AXI + next_level.append({"src": f"{sc_name}/M00_AXI"}) + root_sc_name = sc_name + + current = next_level + level += 1 + + if root_sc_name: + ddr_smart_roots.append({"sc_name": root_sc_name, "dst_pin": dst_pin}) + + return { + "ddr_direct": ddr_direct, + "ddr_smart_nodes": ddr_smart_nodes, + "ddr_smart_roots": ddr_smart_roots, + } diff --git a/linker/src/emit/hbm_ctx.py b/linker/src/emit/hbm_ctx.py new file mode 100644 index 00000000..ac8c8ad4 --- /dev/null +++ b/linker/src/emit/hbm_ctx.py @@ -0,0 +1,80 @@ +# emit/hbm_ctx.py +from __future__ import annotations +from collections import defaultdict +from typing import Dict, List +from core.kernel import KernelInstance +from core.port import PortType +from core.bd_ports import BlockDesignPorts + +def build_hbm_smartconnect_context( + instances: Dict[str, KernelInstance], + bd: BlockDesignPorts, + *, + max_si: int = 16, + base_name: str = "sc_hbm", +) -> dict: + """ + SmartConnect reduction per HBM. If only 1 source -> direct connect. + If >1, build a tree with nodes having up to 'max_si' SIs, 1 MI. + + Returns keys for the template: + - hbm_direct: [{src_pin, dst_port}] + - hbm_smart_nodes: [{name, num_si, si:[{slot, src}], ...}] + - hbm_smart_roots: [{sc_name, dst_port}] + """ + # Gather AXI4FULL kernel pins targeting HBM + by_hbm: Dict[int, List[str]] = defaultdict(list) + for inst in instances.values(): + mem_sp = inst.params.get("mem_sp", {}) + for k_port, tgt in mem_sp.items(): + if tgt.get("domain") == "HBM" and tgt.get("index") is not None: + if inst.kernel.port(k_port).ptype == PortType.AXI4FULL: + by_hbm[int(tgt["index"])].append(f"{inst.name}/{k_port}") + + hbm_direct: List[dict] = [] + hbm_smart_nodes: List[dict] = [] + hbm_smart_roots: List[dict] = [] + + for h_idx in sorted(by_hbm.keys()): + dst_bd = bd.mem("HBM", h_idx) + dst_port = dst_bd.rtl_name or dst_bd.name + + sources = by_hbm[h_idx] + if len(sources) == 1: + hbm_direct.append({"src_pin": sources[0], "dst_port": dst_port}) + continue + + # Build reduction tree + level = 0 + current = [{"src": s} for s in sources] + root_sc_name = None + + while len(current) > 1: + groups = [current[i:i + max_si] for i in range(0, len(current), max_si)] + next_level = [] + + for g_idx, group in enumerate(groups): + sc_name = f"{base_name}_{h_idx:02d}_{level}_{g_idx}" + node = { + "name": sc_name, + "num_si": len(group), + "si": [{"slot": i, "src": g["src"]} for i, g in enumerate(group)], + } + hbm_smart_nodes.append(node) + # Output of this SC is single MI M00_AXI + next_level.append({"src": f"{sc_name}/M00_AXI"}) + root_sc_name = sc_name + + current = next_level + level += 1 + + # Root SC connects to HBM port + if root_sc_name: + hbm_smart_roots.append({"sc_name": root_sc_name, "dst_port": dst_port}) + + return { + "hbm_direct": hbm_direct, + "hbm_smart_nodes": hbm_smart_nodes, + "hbm_smart_roots": hbm_smart_roots, + } + \ No newline at end of file diff --git a/linker/src/emit/host_ctx.py b/linker/src/emit/host_ctx.py new file mode 100644 index 00000000..f3241df4 --- /dev/null +++ b/linker/src/emit/host_ctx.py @@ -0,0 +1,123 @@ +from __future__ import annotations +from typing import Dict, List, Tuple +from collections import defaultdict + +from core.kernel import KernelInstance +from core.port import PortType +from core.bd_ports import BlockDesignPorts + +def _collect_host_sources(instances: Dict[str, KernelInstance]) -> List[str]: + """ + Find all AXI4FULL master ports mapped to HOST. Return list of 'inst/port' pin names. + """ + si: List[str] = [] + for inst in instances.values(): + mem_map = inst.params.get("mem_sp", {}) + for p in inst.kernel.ports_of_type(PortType.AXI4FULL): + tgt = mem_map.get(p.name) + if not tgt: + continue + if str(tgt.get("domain", "")).upper() == "HOST": + si.append(f"{inst.name}/{p.name}") + return si + +def _stage_smartconnects(prefix: str, sources: List[str], max_si: int) -> Tuple[List[dict], str]: + """ + Build a reduction tree of SmartConnects: + - inputs: list of SI endpoints (inst/port) + - max_si: SmartConnect SI capacity (e.g., 16) + Returns: + (smartconnect_defs, final_sc_name) + where smartconnect_defs is a list of dicts: + { + "name": "host_sc_0", + "num_si": N, + "si_srcs": ["inst/port", ...] # if leaf level + "si_up": ["host_sc_X/M00_AXI", ...] # if fed by previous stage + } + """ + if not sources: + return [], "" + + level = 0 + leaves = [] + # chunk into groups of max_si + def chunks(lst, n): + for i in range(0, len(lst), n): + yield lst[i:i+n] + + current_inputs = [sources] + sc_defs: List[dict] = [] + + current = sources[:] + + while len(current) > max_si: + next_level_inputs: List[str] = [] + for idx, group in enumerate(chunks(current, max_si)): + sc_name = f"{prefix}_lvl{level}_{idx}" + sc_defs.append({ + "name": sc_name, + "num_si": len(group), + "si_srcs": group, # raw inst/port sources at this level + "si_up": None, + }) + next_level_inputs.append(f"{sc_name}/M00_AXI") + current = next_level_inputs + level += 1 + + # final toppest SC (or single-level if <= max_si) + final_sc = f"{prefix}_lvl{level}_0" + if len(current) == 1 and current[0].count("/") == 1 and current[0].endswith("/M00_AXI"): + # degenerate case: exactly one upstream SC output, no need for a final SC + # but to keep TCL simple/regular, we still add a 1-SI node to connect clocks/reset uniformly + sc_defs.append({ + "name": final_sc, + "num_si": 1, + "si_srcs": None, + "si_up": current, + }) + else: + sc_defs.append({ + "name": final_sc, + "num_si": len(current), + "si_srcs": current if current and "/" in current[0] else None, + "si_up": None if (current and "/" not in current[0]) else current, + }) + + return sc_defs, final_sc + + +def build_host_smartconnect_context( + instances: Dict[str, KernelInstance], + bd: BlockDesignPorts, + max_si: int = 16 +) -> dict: + si_sources = _collect_host_sources(instances) + host_target_rtl = bd.get("HOST").rtl_name # "QDMA_SLAVE_BRIDGE" + + if not si_sources: + # Nothing to aggregate → request a terminator + return { + "host_sc_defs": [], + "host_final": "", + "host_target_rtl": host_target_rtl, + "host_clk": "aclk1", + "host_clk_aux": "s_axi_aclk", + "host_rstn": "ap_rst_n", + "host_use_two_clks": True, + "host_need_term": True, + "host_term_name": "qdma_host_term_0", + } + + sc_defs, final_sc = _stage_smartconnects("host_sc", si_sources, max_si=max_si) + return { + "host_sc_defs": sc_defs, + "host_final": final_sc, + "host_target_rtl": host_target_rtl, + "host_clk": "aclk1", + "host_clk_aux": "s_axi_aclk", + "host_rstn": "ap_rst_n", + "host_use_two_clks": True, + "host_need_term": False, + "host_term_name": "qdma_host_term_0", + } diff --git a/linker/src/emit/kernel_ctx.py b/linker/src/emit/kernel_ctx.py new file mode 100644 index 00000000..4b88a213 --- /dev/null +++ b/linker/src/emit/kernel_ctx.py @@ -0,0 +1,25 @@ +# emit/build_ctx.py +from __future__ import annotations +from collections import OrderedDict +from typing import Dict +from core.kernel import KernelInstance +from core.port import PortType + +def build_kernel_add_context(instances: Dict[str, KernelInstance]) -> dict: + """ + Context for your Jinja template: + - instances: OrderedDict[name -> KernelInstance] + - clocks: [{"src_pin": "/"} ...] + """ + ordered = OrderedDict((name, instances[name]) for name in sorted(instances.keys())) + + clocks = [] + resets = [] + for name, inst in ordered.items(): + for p in inst.kernel.ports_of_type(PortType.CLOCK): + clocks.append({"src_pin": f"{inst.name}/{p.name}"}) + + for p in inst.kernel.ports_of_type(PortType.RESET): + resets.append({"src_pin": f"{inst.name}/{p.name}"}) + + return {"instances": ordered, "clocks": clocks, "resets": resets} diff --git a/linker/src/emit/mem_ctx.py b/linker/src/emit/mem_ctx.py new file mode 100644 index 00000000..a2c509f2 --- /dev/null +++ b/linker/src/emit/mem_ctx.py @@ -0,0 +1,118 @@ +# emit/mem_ctx.py +from __future__ import annotations +from collections import defaultdict +from typing import Dict, List, Optional, Tuple, Any +from core.kernel import KernelInstance +from core.port import PortType + +def _coerce_optional_int(v: Any) -> Optional[int]: + """Return int(v) if v is not None and looks like an int (decimal or 0x..), else None.""" + if v is None: + return None + if isinstance(v, int): + return v + if isinstance(v, str): + s = v.strip() + try: + return int(s, 0) + except ValueError: + return None + return None + +def build_mem_smartconnect_context( + instances: Dict[str, KernelInstance], + *, + num_mem_ports: int = 8, + max_si: int = 16, + base_name: str = "sc_mem", + noc_pin_fmt: str = "/hbm_vnoc_0{index}/S00_AXI" +) -> dict: + """ + Map all AXI4FULL masters targeting MEM to 8 VNOC slaves using round-robin, + unless a MEM index is explicitly specified in the config (sp=...:MEM). + If a VNOC bucket has >1 masters, build a SmartConnect reduction tree with + <= max_si SIs per node (NUM_CLKS=1, NUM_MI=1). + + Returns: + { + "mem_direct": [{src_pin, dst_pin}], + "mem_smart_nodes": [{name, num_si, si:[{slot, src}], ...}], + "mem_smart_roots": [{sc_name, dst_pin}], + } + """ + # 1) Collect all AXI4FULL kernel pins that target MEM + # Also capture an optional explicit index (if provided by config). + mem_sources: List[Tuple[str, Optional[int]]] = [] # (src_pin, explicit_index or None) + + for inst in instances.values(): + mem_sp = inst.params.get("mem_sp", {}) + for k_port, tgt in mem_sp.items(): + if tgt.get("domain") == "MEM": + # Only AXI4FULL should be in mem_sp for memory mapping + if inst.kernel.port(k_port).ptype == PortType.AXI4FULL: + src_pin = f"{inst.name}/{k_port}" + # Some configs may carry an explicit MEM index; usually None. + idx = _coerce_optional_int(tgt.get("index")) + if idx is not None and not (0 <= idx < num_mem_ports): + raise ValueError(f"MEM index {idx} out of range (0..{num_mem_ports-1}) for {src_pin}") + mem_sources.append((src_pin, idx)) + + if not mem_sources: + return {"mem_direct": [], "mem_smart_nodes": [], "mem_smart_roots": []} + + # 2) Round-robin assign to MEM buckets (respect explicit indices when present) + buckets: Dict[int, List[str]] = {i: [] for i in range(num_mem_ports)} + rr = 0 + for src_pin, explicit in mem_sources: + if explicit is not None: + buckets[explicit].append(src_pin) + else: + buckets[rr % num_mem_ports].append(src_pin) + rr += 1 + + mem_direct: List[dict] = [] + mem_smart_nodes: List[dict] = [] + mem_smart_roots: List[dict] = [] + + # 3) For each MEM bucket, either direct-connect or reduce via SmartConnect tree + for m_idx in range(num_mem_ports): + dst_pin = noc_pin_fmt.format(index=m_idx) + sources = buckets[m_idx] + if len(sources) == 0: + continue + if len(sources) == 1: + mem_direct.append({"src_pin": sources[0], "dst_pin": dst_pin}) + continue + + # Reduction tree (≤ max_si SIs per node) + level = 0 + current = [{"src": s} for s in sources] + root_sc_name = None + + while len(current) > 1: + groups = [current[i:i + max_si] for i in range(0, len(current), max_si)] + next_level: List[dict] = [] + + for g_idx, group in enumerate(groups): + sc_name = f"{base_name}_{m_idx}_{level}_{g_idx}" + node = { + "name": sc_name, + "num_si": len(group), + "si": [{"slot": i, "src": g["src"]} for i, g in enumerate(group)], + } + mem_smart_nodes.append(node) + # Output of this SC is single MI: M00_AXI + next_level.append({"src": f"{sc_name}/M00_AXI"}) + root_sc_name = sc_name + + current = next_level + level += 1 + + if root_sc_name: + mem_smart_roots.append({"sc_name": root_sc_name, "dst_pin": dst_pin}) + + return { + "mem_direct": mem_direct, + "mem_smart_nodes": mem_smart_nodes, + "mem_smart_roots": mem_smart_roots, + } diff --git a/linker/src/emit/network_ctx.py b/linker/src/emit/network_ctx.py new file mode 100644 index 00000000..406e42c9 --- /dev/null +++ b/linker/src/emit/network_ctx.py @@ -0,0 +1,131 @@ +# emit/network_ctx.py +from __future__ import annotations +import re +from typing import Dict, List, Tuple +from core.kernel import KernelInstance +from core.port import PortType + +# eth_.(tx0|tx1|rx0|rx1) +_ETH_EP_RE = re.compile(r"^eth_(\d+)\.(tx0|tx1|rx0|rx1)$", re.IGNORECASE) + +def _map_eth_tx_pin(eth_idx: int, lane: int) -> str: + k = eth_idx * 2 + lane + return f"/dcmac_axis_noc_{k}/S00_AXIS" + +def _map_eth_rx_pin(eth_idx: int, lane: int) -> str: + k = eth_idx * 2 + lane + return f"/dcmac_axis_noc_s_{k}/M00_AXIS" + +def _is_eth_endpoint(s: str) -> bool: + return _ETH_EP_RE.match(s or "") is not None + +def _parse_eth_endpoint(s: str) -> Tuple[int, str]: + m = _ETH_EP_RE.match(s) + if not m: + raise ValueError(f"Invalid eth endpoint '{s}'. Expected eth_<0..3>.(tx0|tx1|rx0|rx1)") + return int(m.group(1)), m.group(2).lower() + +_port_norm = lambda s: re.sub(r"[^a-z0-9]", "", s.lower()) + +def _resolve_port_name(kernel, requested: str) -> str: + # exact + if requested in kernel.ports: + return requested + # case-insensitive + low = {n.lower(): n for n in kernel.ports.keys()} + rlow = requested.lower() + if rlow in low: + return low[rlow] + # underscore/char-insensitive (remove non-alnum) + norm_map = {_port_norm(n): n for n in kernel.ports.keys()} + rnorm = _port_norm(requested) + if rnorm in norm_map: + return norm_map[rnorm] + raise KeyError( + f"Kernel '{kernel.name}' has no port named '{requested}'. " + f"Available: {list(kernel.ports.keys())}" + ) + +# -------------------------------------------------------------------- + +def build_network_axis_context( + instances: Dict[str, KernelInstance], + streams, + net, # cfg.network with .enabled_eth +): + """ + Returns: + { + "axis_to_fabric": [{ "src_pin": "/", "dst_pin": ""}], + "axis_from_fabric": [{ "src_pin": "", "dst_pin": "/"}], + "streams_leftover": [ non-eth streams ] + } + """ + to_fabric: List[dict] = [] + from_fabric: List[dict] = [] + leftover = [] + + for s in streams: + src_is_eth = _is_eth_endpoint(f"{s.src_inst}.{s.src_port}") + dst_is_eth = _is_eth_endpoint(f"{s.dst_inst}.{s.dst_port}") + + if not src_is_eth and not dst_is_eth: + leftover.append(s) + continue + if src_is_eth and dst_is_eth: + raise ValueError(f"stream_connect cannot be eth->eth: '{s.src_inst}.{s.src_port} : {s.dst_inst}.{s.dst_port}'") + + if dst_is_eth: + # inst -> fabric TX + if s.src_inst not in instances: + raise KeyError(f"Unknown instance '{s.src_inst}' in stream '{s.src_inst}.{s.src_port} -> {s.dst_inst}.{s.dst_port}'") + src_inst = instances[s.src_inst] + # robust port resolution + src_port = _resolve_port_name(src_inst.kernel, s.src_port) + src_p = src_inst.kernel.port(src_port) + if src_p.ptype != PortType.AXIS: + raise ValueError(f"{s.src_inst}.{src_port} is not AXIS (got {src_p.ptype.name})") + + eth_idx, lane_name = _parse_eth_endpoint(f"{s.dst_inst}.{s.dst_port}") + if eth_idx not in getattr(net, "enabled_eth", set()): + raise ValueError(f"eth_{eth_idx} is not enabled in [network] but is referenced in stream_connect") + + lane = 0 if lane_name == "tx0" else 1 if lane_name == "tx1" else None + if lane is None: + raise ValueError(f"Only tx0/tx1 valid on fabric TX, got '{lane_name}'") + + dst_pin = _map_eth_tx_pin(eth_idx, lane) + to_fabric.append({ + "src_pin": f"{s.src_inst}/{src_port}", + "dst_pin": dst_pin, + }) + + else: + # fabric RX -> inst + if s.dst_inst not in instances: + raise KeyError(f"Unknown instance '{s.dst_inst}' in stream '{s.src_inst}.{s.src_port} -> {s.dst_inst}.{s.dst_port}'") + dst_inst = instances[s.dst_inst] + dst_port = _resolve_port_name(dst_inst.kernel, s.dst_port) + dst_p = dst_inst.kernel.port(dst_port) + if dst_p.ptype != PortType.AXIS: + raise ValueError(f"{s.dst_inst}.{dst_port} is not AXIS (got {dst_p.ptype.name})") + + eth_idx, lane_name = _parse_eth_endpoint(f"{s.src_inst}.{s.src_port}") + if eth_idx not in getattr(net, "enabled_eth", set()): + raise ValueError(f"eth_{eth_idx} is not enabled in [network] but is referenced in stream_connect") + + lane = 0 if lane_name == "rx0" else 1 if lane_name == "rx1" else None + if lane is None: + raise ValueError(f"Only rx0/rx1 valid on fabric RX, got '{lane_name}'") + + src_pin = _map_eth_rx_pin(eth_idx, lane) + from_fabric.append({ + "src_pin": src_pin, + "dst_pin": f"{s.dst_inst}/{dst_port}", + }) + + return { + "axis_to_fabric": to_fabric, + "axis_from_fabric": from_fabric, + "streams_leftover": leftover, + } diff --git a/linker/src/emit/param_ctx.py b/linker/src/emit/param_ctx.py new file mode 100644 index 00000000..3b3938f9 --- /dev/null +++ b/linker/src/emit/param_ctx.py @@ -0,0 +1,61 @@ +# emit/param_ctx.py +from __future__ import annotations +from typing import Dict, List +from core.kernel import KernelInstance +from core.port import PortType + +def _param_name_for_busif(busif: str) -> str: + # HLS/packager convention: C__DATA_WIDTH + # e.g., M_AXI_GMEM0 -> C_M_AXI_GMEM0_DATA_WIDTH + return f"C_{busif.upper()}_DATA_WIDTH" + +def build_data_width_param_context( + instances: Dict[str, KernelInstance], + *, + domains_of_interest = ("HBM", "VIRT"), + default_width_by_domain = {"HBM": 256, "VIRT": 512} +) -> dict: + """ + For every instance and each AXI4FULL port that is mapped (via cfg.sps/defaults) + to a memory domain in 'domains_of_interest', emit a param set: + set_property CONFIG.C__DATA_WIDTH {} [get_bd_cells ] + + Width resolution order: + 1) Use the port width parsed from component.xml if present (Port.width). + 2) Fallback to default_width_by_domain[domain]. + """ + out: List[dict] = [] + + for inst in instances.values(): + # mem_sp filled earlier by apply_config_to_instances() + mem_map = inst.params.get("mem_sp", {}) or {} + for busif, tgt in mem_map.items(): + dom = str(tgt.get("domain", "")).upper() + if dom not in domains_of_interest: + continue + # Only for AXI4FULL ports + try: + p = inst.kernel.port(busif) + except KeyError: + continue + if p.ptype != PortType.AXI4FULL: + continue + + # Decide width + width = p.width if p.width else default_width_by_domain.get(dom) + if not width: + # If still unknown, skip silently (or raise if you prefer) + continue + + out.append({ + "inst": inst.name, + "param": f"CONFIG.{_param_name_for_busif(busif)}", + "value": int(width), + }) + + # Optional de-dup if multiple entries set the same param for an inst + dedup = {} + for e in out: + key = (e["inst"], e["param"]) + dedup[key] = e # last wins + return {"data_width_params": list(dedup.values())} diff --git a/linker/src/emit/render.py b/linker/src/emit/render.py new file mode 100644 index 00000000..6c6550f9 --- /dev/null +++ b/linker/src/emit/render.py @@ -0,0 +1,15 @@ +# emit/render_min.py +from __future__ import annotations +from pathlib import Path +from jinja2 import Environment, FileSystemLoader, StrictUndefined + +def render_template(template_dir: str | Path, template_name: str, out_path: str | Path, context: dict) -> None: + env = Environment( + loader=FileSystemLoader(str(template_dir)), + undefined=StrictUndefined, + trim_blocks=True, + lstrip_blocks=True, + ) + env.filters["zip"] = lambda a, b: zip(a, b) + tmpl = env.get_template(template_name) + Path(out_path).write_text(tmpl.render(**context), encoding="utf-8") diff --git a/linker/src/emit/service_layer_ctx.py b/linker/src/emit/service_layer_ctx.py new file mode 100644 index 00000000..dadeba46 --- /dev/null +++ b/linker/src/emit/service_layer_ctx.py @@ -0,0 +1,148 @@ +# emit/service_layer_ctx.py +from __future__ import annotations +from dataclasses import dataclass +from pathlib import Path +from typing import Set, Dict, Any + +@dataclass(frozen=True) +class NetworkSpecView: + enabled_eth: Set[int] + +def build_service_layer_context(net) -> dict: + """ + Map enabled eth_* to DCMAC enables: + qsfp_0_n_1 -> DCMAC0 ⇔ eth_0 + qsfp_2_n_3 -> DCMAC1 ⇔ eth_2 + Dual-QSFP knobs remain 0 for now. + """ + enabled = getattr(net, "enabled_eth", set()) + dc0 = 1 if 0 in enabled else 0 + dc1 = 1 if 2 in enabled else 0 + return { + "needs_dcmac": (dc0 == 1 or dc1 == 1), + "dc_enable_0": dc0, + "dc_enable_1": dc1, + "dual_qsfp_0": 0, + "dual_qsfp_1": 0, + } + +def compute_paths(proj_root: Path | None = None) -> Dict[str, Any]: + """ + Resolve absolute paths for service-layer assets regardless of CWD. + Assumes main.py is /src/main.py if proj_root not provided. + """ + if proj_root is None: + # main.py is /src/main.py -> go up two levels + proj_root = Path(__file__).resolve().parents[2] + + dcmac_dir = proj_root / "resources" / "dcmac" + dcmac_tcl = dcmac_dir / "tcl" / "dcmac.tcl" + dcmac_hdl = dcmac_dir / "hdl" + + # add/remove files as needed + hdl_files = [ + "axis_seg_to_unseg_converter.v", + "clock_to_clock_bus.v", + "dcmac200g_ctl_port.v", + "serdes_clock.v", + "syncer_reset.v", + ] + + return { + "proj_root": str(proj_root), + "dcmac_tcl": str(dcmac_tcl), + "dcmac_hdl_dir": str(dcmac_hdl), + "dcmac_hdl_files": [str(dcmac_hdl / f) for f in hdl_files], + } + +from typing import Dict, Any + +def build_service_axilite_ctx(net) -> Dict[str, Any]: + """ + Build SmartConnect context for service_layer: + - NUM_CLKS: 2 (aclk0, aclk1) + - NUM_SI: 1 (drives from top 'S_AXILITE') + - NUM_MI: # of enabled DCMAC hier blocks (qsfp_0_n_1, qsfp_2_n_3) + - MI targets: /s_axi + + We map eth_0 -> qsfp_0_n_1, eth_2 -> qsfp_2_n_3 (as per your convention). + """ + enabled = getattr(net, "enabled_eth", set()) + + qsfp_blocks: list[str] = [] + mi_targets: list[str] = [] + + if 0 in enabled: + qsfp_blocks.append("qsfp_0_n_1") + mi_targets.append("qsfp_0_n_1/s_axi") + if 2 in enabled: + qsfp_blocks.append("qsfp_2_n_3") + mi_targets.append("qsfp_2_n_3/s_axi") + + num_mi = len(mi_targets) + + return { + # smartconnect presence + "sl_have_xbar": num_mi > 0, + + # properties + "sl_num_clks": 2, + "sl_num_si": 1, + "sl_num_mi": num_mi, + + # wiring + "sl_si_src_if": "axi_noc_0/M00_AXI", # top-level service_layer AXI-Lite interface + "sl_clk0": "aclk0", # service_layer clock pins + "sl_clk1": "aclk1", + "sl_rstn": "ap_rst_n", + + # MI endpoints and qsfp blocks for clk/rst tie-off + "sl_mi_targets": mi_targets, # e.g. ["qsfp_0_n_1/s_axi", "qsfp_2_n_3/s_axi"] + "sl_qsfp_blocks": qsfp_blocks, # e.g. ["qsfp_0_n_1", "qsfp_2_n_3"] + + # preferred instance names + "sl_smartconnect_path": "smartconnect_0", + "sl_smartconnect_name": "sl_xbar", + } + + +# emit/service_layer_ctx.py + +from typing import Dict, Any, List + +def build_service_noc_axis_ctx(net) -> Dict[str, Any]: + """ + Build AXIS links between qsfp_* and dummy NoC endpoints inside 'service_layer'. + + Mapping (even indices only): + - eth_0 -> qsfp_0_n_1 uses X = 0 + - eth_2 -> qsfp_2_n_3 uses X = 4 + + Connections: + Fabric -> MAC: dummy_noc_X/M00_AXIS -> qsfp_*/S_AXIS_0 + MAC -> Fabric: qsfp_*/M_AXIS_0 -> dummy_noc_m_X/S00_AXIS + """ + enabled = getattr(net, "enabled_eth", set()) + links: List[dict] = [] + + if 0 in enabled: + links.append({ # fabric -> MAC + "src_pin": "dummy_noc_0/M00_AXIS", + "dst_pin": "qsfp_0_n_1/S_AXIS_0", + }) + links.append({ # MAC -> fabric + "src_pin": "qsfp_0_n_1/M_AXIS_0", + "dst_pin": "dummy_noc_m_0/S00_AXIS", + }) + + if 2 in enabled: + links.append({ + "src_pin": "dummy_noc_4/M00_AXIS", + "dst_pin": "qsfp_2_n_3/S_AXIS_0", + }) + links.append({ + "src_pin": "qsfp_2_n_3/M_AXIS_0", + "dst_pin": "dummy_noc_m_4/S00_AXIS", + }) + + return {"sl_axis_noc_links": links} diff --git a/linker/src/emit/smartconnect_ctx.py b/linker/src/emit/smartconnect_ctx.py new file mode 100644 index 00000000..841448e7 --- /dev/null +++ b/linker/src/emit/smartconnect_ctx.py @@ -0,0 +1,76 @@ +# emit/smartconnect_ctx.py +from __future__ import annotations +from collections import OrderedDict +from typing import Dict, List +from core.kernel import KernelInstance +from core.port import PortType + +def build_axilite_smartconnect_context( + instances: Dict[str, KernelInstance], + *, + si_bd_port: str = "axi_noc_0/M00_AXI", + max_mi: int = 16, + chain_slot: int = 15, + base_name: str = "smartconnect", +) -> dict: + """ + SmartConnects to fan out AXI-Lite control to all kernel AXI-Lite ports. + + Returns: + {"smartconnects": [ + { + "index": 0, + "name": "smartconnect_0", + "num_mi": 64 or N, + "chain_slot": 63, + "si_from": {"type":"bd_port","name":"s_axilite"} or {"type":"smartconnect","prev":"smartconnect_0"}, + "mi": [{"slot": 0, "dst_pin": "inst/AXILITE_PIN"}, ...] + }, + ... + ]} + """ + # 1) Collect all AXI-Lite endpoints in a stable order + ordered = OrderedDict((name, instances[name]) for name in sorted(instances.keys())) + endpoints: List[str] = [] + for inst in ordered.values(): + for p in sorted((pp for pp in inst.kernel.ports.values() if pp.ptype == PortType.AXILITE), key=lambda x: x.name): + endpoints.append(f"{inst.name}/{p.name}") + + N = len(endpoints) + if N == 0: + return {"smartconnects": []} + + # 2) Pack endpoints into one-or-more SCs + smartconnects = [] + remaining = endpoints[:] + idx = 0 + prev_name = None + + while remaining: + sc_name = f"{base_name}_{idx}" + is_last = len(remaining) <= max_mi + if is_last: + payload = remaining[:max_mi] + remaining = [] + num_mi = len(payload) + else: + payload = remaining[: (max_mi - 1)] + remaining = remaining[(max_mi - 1):] + num_mi = max_mi + + sc = { + "index": idx, + "name": sc_name, + "num_mi": num_mi, + "chain_slot": chain_slot, + "si_from": ( + {"type": "bd_port", "name": si_bd_port} if prev_name is None + else {"type": "smartconnect", "prev": prev_name} + ), + "mi": [{"slot": slot, "dst_pin": dst} for slot, dst in enumerate(payload)], + } + smartconnects.append(sc) + prev_name = sc_name + idx += 1 + + return {"smartconnects": smartconnects} diff --git a/linker/src/emit/stream_ctx.py b/linker/src/emit/stream_ctx.py new file mode 100644 index 00000000..2b59515a --- /dev/null +++ b/linker/src/emit/stream_ctx.py @@ -0,0 +1,70 @@ +# emit/stream_ctx.py +from __future__ import annotations +import re +from typing import Dict, List +from core.kernel import KernelInstance +from core.port import PortType + +_ETH_EP_RE = re.compile(r"^eth_(\d+)\.(tx0|tx1|rx0|rx1)$", re.IGNORECASE) +_port_norm = lambda s: re.sub(r"[^a-z0-9]", "", s.lower()) + +def _resolve_port_name(kernel, requested: str) -> str: + if requested in kernel.ports: + return requested + low = {n.lower(): n for n in kernel.ports.keys()} + rlow = requested.lower() + if rlow in low: + return low[rlow] + norm_map = {_port_norm(n): n for n in kernel.ports.keys()} + rnorm = _port_norm(requested) + if rnorm in norm_map: + return norm_map[rnorm] + raise KeyError( + f"Kernel '{kernel.name}' has no port named '{requested}'. " + f"Available: {list(kernel.ports.keys())}" + ) + +def build_stream_connect_context( + instances: Dict[str, KernelInstance], + streams: List[object], +) -> dict: + """ + Convert config 'stream_connect=src_inst.src_port:dst_inst.dst_port' + into {src_pin, dst_pin}, validating AXIS. + NOTE: pass ONLY non-eth streams here (use build_network_axis_context first). + """ + out: List[dict] = [] + + for s in streams: + # prevent accidental eth_* usage here + if _ETH_EP_RE.match(f"{s.src_inst}.{s.src_port}") or _ETH_EP_RE.match(f"{s.dst_inst}.{s.dst_port}"): + raise ValueError( + "eth_* endpoint seen in generic builder. " + "Call build_network_axis_context() first and pass only its 'streams_leftover' here." + ) + + if s.src_inst not in instances: + raise KeyError(f"stream_connect: unknown instance '{s.src_inst}'") + if s.dst_inst not in instances: + raise KeyError(f"stream_connect: unknown instance '{s.dst_inst}'") + + src_inst = instances[s.src_inst] + dst_inst = instances[s.dst_inst] + + src_port = _resolve_port_name(src_inst.kernel, s.src_port) + dst_port = _resolve_port_name(dst_inst.kernel, s.dst_port) + + src_p = src_inst.kernel.port(src_port) + dst_p = dst_inst.kernel.port(dst_port) + + if src_p.ptype != PortType.AXIS: + raise ValueError(f"stream_connect: {s.src_inst}.{src_port} is not AXIS (got {src_p.ptype.name})") + if dst_p.ptype != PortType.AXIS: + raise ValueError(f"stream_connect: {s.dst_inst}.{dst_port} is not AXIS (got {dst_p.ptype.name})") + + out.append({ + "src_pin": f"{s.src_inst}/{src_port}", + "dst_pin": f"{s.dst_inst}/{dst_port}", + }) + + return {"axis_streams": out} diff --git a/linker/src/emit/terminator_ctx.py b/linker/src/emit/terminator_ctx.py new file mode 100644 index 00000000..da612715 --- /dev/null +++ b/linker/src/emit/terminator_ctx.py @@ -0,0 +1,102 @@ +# emit/terminators_ctx.py +from __future__ import annotations +from typing import Dict, List, Set +import re +from core.port import PortType +from core.bd_ports import BlockDesignPorts, BdPort + +_RX_SKIP_TOP = re.compile(r"^(M\d{2}_INI|HBM_VNOC_INI_\d{2})$", re.IGNORECASE) + +def _is_bd_port(p: BdPort) -> bool: + """True if destination is a *BD interface port* (not a NoC/pin path).""" + return not ((p.rtl_name or "").startswith("/")) + +def _want_generic_term(p: BdPort) -> bool: + """ + Only terminate HBM & VIRT BD ports here. + Skip DDR/MEM top ports (Mxx_INI, HBM_VNOC_INI_xx) – they get NoC-side terminators. + """ + if p.ptype != PortType.AXI4FULL: + return False + dom = (p.domain or "").upper() + if dom not in {"HBM", "VIRT"}: + return False + if not _is_bd_port(p): + return False + rtl = (p.rtl_name or p.name) + if _RX_SKIP_TOP.match(rtl): + return False + return True + +def build_axi_terminators_context( + bd: BlockDesignPorts, + used_targets: Set[str], + *, + base_name: str = "axi_register_slice_term", +) -> dict: + """ + Plan AXI Register Slices ONLY for unused HBM/VIRT BD ports. + DDR and MEM are handled by NoC-specific builders. + """ + terms: List[dict] = [] + seq = 0 + + for lst in bd.ports.values(): + for p in lst: + if not _want_generic_term(p): + continue + dst = (p.rtl_name or p.name) + if dst in used_targets: + continue + terms.append({ + "name": f"{base_name}_{seq}", + "dst": dst, + "dst_kind": "port", # generic covers only BD ports + }) + seq += 1 + + return {"axi_terminators": terms} + +def build_ddr_noc_terminators( + used_targets: Set[str], + *, + num_ddr: int = 4, + noc_pin_fmt: str = "/ddr_noc_{index}/S00_AXI", + base_name: str = "axi_register_slice_ddrterm", +) -> dict: + """Terminate unused DDR NoC pins.""" + axi_terms: List[dict] = [] + seq = 0 + for i in range(num_ddr): + dst = noc_pin_fmt.format(index=i) + if dst in used_targets: + continue + axi_terms.append({ + "name": f"{base_name}_{seq}", + "dst": dst, + "dst_kind": "pin", + }) + seq += 1 + return {"axi_terminators": axi_terms} + +def build_mem_noc_terminators( + used_targets: Set[str], + *, + num_mem: int = 8, + noc_pin_fmt: str = "/hbm_vnoc_0{index}/S00_AXI", + base_name: str = "axi_register_slice_memterm", +) -> dict: + """Terminate unused MEM (VNOC) NoC pins.""" + axi_terms: List[dict] = [] + seq = 0 + for i in range(num_mem): + dst = noc_pin_fmt.format(index=i) + if dst in used_targets: + continue + axi_terms.append({ + "name": f"{base_name}_{seq}", + "dst": dst, + "dst_kind": "pin", + }) + seq += 1 + return {"axi_terminators": axi_terms} diff --git a/linker/src/emit/virt_ctx.py b/linker/src/emit/virt_ctx.py new file mode 100644 index 00000000..9f1510e4 --- /dev/null +++ b/linker/src/emit/virt_ctx.py @@ -0,0 +1,80 @@ +# emit/virt_ctx.py +from __future__ import annotations +from collections import defaultdict +from typing import Dict, List +from core.kernel import KernelInstance +from core.port import PortType +from core.bd_ports import BlockDesignPorts + +def build_virt_smartconnect_context( + instances: Dict[str, KernelInstance], + bd: BlockDesignPorts, + *, + max_si: int = 16, + base_name: str = "sc_virt", + domain: str = "VIRT", # logical domain name in bd_ports.txt (VIRT0..VIRT3) +) -> dict: + """ + Plan SmartConnect fan-in per VIRT. If only 1 source targets a VIRT, + connect directly to the BD pin from bd_ports; else build a reduction tree + with SmartConnect nodes (<= max_si SIs, NUM_MI=1, NUM_CLKS=1). + + Returns: + - virt_direct: [{src_pin, dst_pin}] + - virt_smart_nodes: [{name, num_si, si:[{slot, src}], ...}] + - virt_smart_roots: [{sc_name, dst_pin}] + """ + # 1) Collect all AXI4FULL masters targeting VIRT + by_virt: Dict[int, List[str]] = defaultdict(list) + for inst in instances.values(): + mem_sp = inst.params.get("mem_sp", {}) + for k_port, tgt in mem_sp.items(): + if tgt.get("domain") == domain and tgt.get("index") is not None: + if inst.kernel.port(k_port).ptype == PortType.AXI4FULL: + by_virt[int(tgt["index"])].append(f"{inst.name}/{k_port}") + + virt_direct: List[dict] = [] + virt_smart_nodes: List[dict] = [] + virt_smart_roots: List[dict] = [] + + # 2) For each VIRT, either direct connect or reduction tree + for v_idx in sorted(by_virt.keys()): + dst_bd = bd.mem(domain, v_idx) # resolves VIRT from bd_ports.txt + dst_pin = dst_bd.rtl_name or dst_bd.name + + sources = by_virt[v_idx] + if len(sources) == 1: + virt_direct.append({"src_pin": sources[0], "dst_pin": dst_pin}) + continue + + # Reduction tree (max_si SIs per node) + level = 0 + current = [{"src": s} for s in sources] + root_sc_name = None + + while len(current) > 1: + groups = [current[i:i + max_si] for i in range(0, len(current), max_si)] + next_level: List[dict] = [] + + for g_idx, group in enumerate(groups): + sc_name = f"{base_name}_{v_idx}_{level}_{g_idx}" + node = { + "name": sc_name, + "num_si": len(group), + "si": [{"slot": i, "src": g["src"]} for i, g in enumerate(group)], + } + virt_smart_nodes.append(node) + next_level.append({"src": f"{sc_name}/M00_AXI"}) + root_sc_name = sc_name + + current = next_level + level += 1 + + if root_sc_name: + virt_smart_roots.append({"sc_name": root_sc_name, "dst_pin": dst_pin}) + + return { + "virt_direct": virt_direct, + "virt_smart_nodes": virt_smart_nodes, + "virt_smart_roots": virt_smart_roots, + } diff --git a/linker/src/main.py b/linker/src/main.py new file mode 100644 index 00000000..f966fd13 --- /dev/null +++ b/linker/src/main.py @@ -0,0 +1,303 @@ +# main.py +import argparse +from collections import OrderedDict +from pathlib import Path +import re + +from emit.kernel_ctx import build_kernel_add_context +from emit.smartconnect_ctx import build_axilite_smartconnect_context +from emit.hbm_ctx import build_hbm_smartconnect_context +from emit.ddr_ctx import build_ddr_smartconnect_context +from emit.mem_ctx import build_mem_smartconnect_context +from emit.render import render_template +from emit.virt_ctx import build_virt_smartconnect_context +from emit.terminator_ctx import build_axi_terminators_context +from emit.terminator_ctx import build_ddr_noc_terminators +from emit.terminator_ctx import build_mem_noc_terminators +from parser.component_parser import parse_component_xml +from emit.network_ctx import build_network_axis_context +from emit.stream_ctx import build_stream_connect_context +from emit.host_ctx import build_host_smartconnect_context +from emit.addr_ctx import build_axilite_address_context +from emit.param_ctx import build_data_width_param_context + +# Service layer +from emit.service_layer_ctx import * + +from parser.config_parser import ( + parse_connectivity_file, + apply_config_to_instances, +) +from core.bd_ports import load_bd_ports_from_file +from core.port import PortType + +def _sanitize_bd_name(s: str) -> str: + # BD names: keep letters/digits/underscore; don’t start with a digit + s2 = re.sub(r'[^A-Za-z0-9_]+', '_', s.strip()) + if not s2: + s2 = "proj" + if s2[0].isdigit(): + s2 = "_" + s2 + return s2 + + +def _collect_used_targets(ctx: dict) -> set[str]: + used: set[str] = set() + + # HBM uses ports + for item in ctx.get("hbm_direct", []): + used.add(item["dst_port"]) + for item in ctx.get("hbm_smart_roots", []): + used.add(item["dst_port"]) + + # DDR uses NoC pins + for item in ctx.get("ddr_direct", []): + used.add(item["dst_pin"]) + for item in ctx.get("ddr_smart_roots", []): + used.add(item["dst_pin"]) + + # MEM uses NoC pins + for item in ctx.get("mem_direct", []): + used.add(item["dst_pin"]) + for item in ctx.get("mem_smart_roots", []): + used.add(item["dst_pin"]) + + # VIRT uses ports (like HBM) + for item in ctx.get("virt_direct", []): + used.add(item["dst_pin"]) + for item in ctx.get("virt_smart_roots", []): + used.add(item["dst_pin"]) + + return used + +# --- add this helper somewhere in main.py --- +def print_memory_maps(k): + if not getattr(k, "memory_maps", None): + print(" (no memory maps)") + return + print(" Memory maps:") + for mm in k.memory_maps: + print(f" - map: {mm.name}") + for ab in mm.address_blocks: + ba = f"0x{ab.base_address:X}" + rg = f"0x{ab.range:X}" + print(f" block {ab.name}: base={ba} range={rg} width={ab.width} usage={ab.usage or '-'} access={ab.access or '-'}") + if ab.offset_base_param or ab.offset_high_param: + print(f" params: base_param={ab.offset_base_param or '-'} high_param={ab.offset_high_param or '-'}") + if ab.registers: + for r in ab.registers: + off = f"0x{r.address_offset:X}" + print(f" reg {r.name}: off={off} size={r.size} access={r.access or '-'} reset={('0x%X' % r.reset_value) if r.reset_value is not None else '-'}") + if r.fields: + for f in r.fields: + rng = f"[{f.bit_offset + f.bit_width - 1}:{f.bit_offset}]" + print(f" - {f.name} {rng} access={f.access or '-'}" + f" reset={('0x%X' % f.reset_value) if f.reset_value is not None else '-'}") + + +def print_kernel(k): + print(f"\nKernel: {k.name}") + for p in k.ports.values(): + print(f" - {p.name:24s} {p.ptype.name:9s} width={p.width}") + print_memory_maps(k) + + + +def print_cfg(cfg): + print("\n[connectivity] nk entries:") + if cfg.nk: + for nk in cfg.nk: + print(f" - {nk.kernel_type}: count={nk.count}, names={nk.instance_names}") + else: + print(" (none)") + + print("\n[connectivity] stream_connect:") + if cfg.streams: + for s in cfg.streams: + print(f" - {s.src_inst}.{s.src_port} -> {s.dst_inst}.{s.dst_port}") + else: + print(" (none)") + + print("\n[connectivity] sp mappings:") + if cfg.sps: + for sp in cfg.sps: + print(f" - {sp.inst}.{sp.port} -> {sp.target.domain}{sp.target.index}") + else: + print(" (none)") + + print("\n[clock] specs:") + if cfg.clocks: + for c in cfg.clocks: + print(f" - {c.inst}: {c.freq_hz} Hz") + else: + print(" (none)") + + +def print_instances(instances, stream_edges): + print("\nInstances created:") + if not instances: + print(" (none)") + return + for name, inst in instances.items(): + print(f" - {name} : kernel={inst.kernel.name}") + if inst.params: + clk = inst.params.get("clock_hz") + if clk is not None: + print(f" clock_hz: {clk}") + mem_sp = inst.params.get("mem_sp") + if mem_sp: + for port, tgt in mem_sp.items(): + idx = "" if tgt.get("index") is None else str(tgt["index"]) + print(f" sp: {port} -> {tgt['domain']}{idx}") + others = {k: v for k, v in inst.params.items() if k not in {"clock_hz", "mem_sp"}} + for k, v in others.items(): + print(f" {k}: {v}") + + print("\nStream connections to wire:") + if stream_edges: + for s in stream_edges: + print(f" - {s.src_inst}.{s.src_port} -> {s.dst_inst}.{s.dst_port}") + else: + print(" (none)") + + +def print_bd_ports(bd): + print("\nBlock Design Ports:") + if not bd.ports: + print(" (none)") + return + for logical in sorted(bd.ports.keys()): + for p in bd.get_all(logical): + dom = "" if p.domain is None else str(p.domain) + idx = "" if p.index is None else str(p.index) + wid = "" if p.width is None else str(p.width) + rtl = "" if p.rtl_name is None else p.rtl_name + print(f" - {logical:12s} -> rtl={rtl:20s} {p.ptype.name:9s} width={wid:>4s} domain={dom:>4s} index={idx:>2s}") + +def main(): + ap = argparse.ArgumentParser( + description="Parse kernels (component.xml), connectivity config, BD port map, and render Tcl." + ) + ap.add_argument("--cfg", required=True, help="Path to connectivity config file (e.g., config.cfg).") + ap.add_argument("--kernels", required=True, nargs="+", + help="List of component.xml files to load as kernel types.") + ap.add_argument("--bd-ports", required=False, default="../resources/bd_ports.txt", + help="Path to BD ports mapping file (logical:rtl TYPE [width]).") + ap.add_argument("--template", default="../resources/slash.tcl", + help="Path to Jinja2 Tcl template (default: ../resources/slash.tcl).") + ap.add_argument("--out", default="slash.tcl", + help="Path to write rendered Tcl (default: slash.tcl).") + ap.add_argument("--service-template", required=False, default="../resources/service_layer.tcl", + help="Path to service layer Jinja2 template (e.g., resources/service_layer.tcl)") + ap.add_argument("--service-out", required=False, default="service_layer_gen.tcl", + help="Path to write rendered service layer Tcl (e.g., build/service_layer.tcl)") + ap.add_argument("--proj-root", default=None, + help="Project root (defaults to parent of src/).") + ap.add_argument("-p", "--project", required=True, help="Project name to suffix TCLs and BD clones.") + + args = ap.parse_args() + project = _sanitize_bd_name(args.project) + default_slash_out = f"../results/{project}/bd/slash_{project}.tcl" + default_service_out = f"../results/{project}/bd/service_layer_{project}.tcl" + # If user didn’t override --out / --service-out, generate suffixed names: + if args.out == "slash.tcl": + args.out = default_slash_out + if args.service_out == "service_layer_gen.tcl": + args.service_out = default_service_out + + # 0) Load BD ports and print + bd = load_bd_ports_from_file(args.bd_ports) + print_bd_ports(bd) + + # 1) Parse kernels + kernel_library = {} + print("\nLoading kernels:") + for kpath in args.kernels: + kfile = Path(kpath) + if not kfile.exists(): + raise FileNotFoundError(f"Kernel file not found: {kfile}") + k = parse_component_xml(kfile) + kernel_library[k.name] = k + print_kernel(k) + + # 2) Parse connectivity config + cfg = parse_connectivity_file(args.cfg) + print_cfg(cfg) + + # 3) Make instances & stream edges + instances, streams = apply_config_to_instances(cfg, kernel_library) + print_instances(instances, streams) + + # 4) Build context for kernel adds (+clocks/resets) and render + ctx = build_kernel_add_context(instances) + ctx.update(build_data_width_param_context(instances)) + ctx.update(build_axilite_smartconnect_context(instances)) + ctx.update(build_hbm_smartconnect_context(instances, bd, max_si=16)) + ctx.update(build_ddr_smartconnect_context(instances, max_si=16)) + ctx.update(build_mem_smartconnect_context(instances, num_mem_ports=8, max_si=16)) + ctx.update(build_host_smartconnect_context(instances, bd, max_si=16)) + ctx.update(build_virt_smartconnect_context(instances, bd, max_si=16)) + net_ctx = build_network_axis_context(instances, streams, cfg.network) + ctx.update({ + "axis_to_fabric": net_ctx["axis_to_fabric"], # inst.AXIS -> /dcmac_axis_noc_k/S00_AXIS + "axis_from_fabric": net_ctx["axis_from_fabric"], # /dcmac_axis_noc_s_k/M00_AXIS -> inst.AXIS + }) + + ctx.update(build_stream_connect_context(instances, net_ctx["streams_leftover"])) + + used_targets = _collect_used_targets(ctx) + + terms_generic = build_axi_terminators_context(bd, used_targets) # HBM/VIRT BD ports only + terms_ddr_noc = build_ddr_noc_terminators(used_targets, num_ddr=4, noc_pin_fmt="/ddr_noc_{index}/S00_AXI") + terms_mem_noc = build_mem_noc_terminators(used_targets, num_mem=8, noc_pin_fmt="/hbm_vnoc_0{index}/S00_AXI") + ctx["axi_terminators"] = ( + terms_generic.get("axi_terminators", []) + + terms_ddr_noc.get("axi_terminators", []) + + terms_mem_noc.get("axi_terminators", []) + ) + ctx.update( + build_axilite_address_context( + instances, + addr_space="S_AXILITE_INI", + base_offset=0x0202_0000_0000, + min_align=0x0001_0000, + ) +) + #ctx.update(build_axi_terminators_context(bd, used_targets)) + ctx["project_name"] = project + ctx["slash_bd_name"] = f"slash_{project}" + template_path = Path(args.template) # resources/slash.tcl + out_path = Path(args.out) # slash.tcl + out_path.parent.mkdir(parents=True, exist_ok=True) + render_template( + template_dir=template_path.parent, + template_name=template_path.name, + out_path=out_path, + context=ctx, + ) + print(f"\nRendered Tcl to {out_path}") + + paths_ctx = compute_paths(Path(args.proj_root).resolve() if args.proj_root else None) + svc_ctx = {} + svc_ctx.update(build_service_layer_context(cfg.network)) + svc_ctx.update(build_service_axilite_ctx(cfg.network)) # SmartConnect + MI targets + svc_ctx.update(build_service_noc_axis_ctx(cfg.network)) + svc_ctx.update(paths_ctx) # absolute paths for dcmac sources + + svc_ctx["project_name"] = project + svc_ctx["service_layer_bd_name"] = f"service_layer_{project}" + # --- Render service-layer Tcl --- + svc_template = Path(args.service_template) + svc_out = Path(args.service_out) + svc_out.parent.mkdir(parents=True, exist_ok=True) + render_template( + template_dir=svc_template.parent, + template_name=svc_template.name, + out_path=svc_out, + context=svc_ctx, + ) + + print(f"Rendered service layer Tcl to {svc_out}") + +if __name__ == "__main__": + main() diff --git a/linker/src/parser/component_parser.py b/linker/src/parser/component_parser.py new file mode 100644 index 00000000..6b6da8cf --- /dev/null +++ b/linker/src/parser/component_parser.py @@ -0,0 +1,192 @@ +# parser/component_parser.py +from __future__ import annotations +from pathlib import Path +from typing import Dict, Optional, List +import xml.etree.ElementTree as ET + +from core.port import Port, PortType +from core.kernel import Kernel +from core.regs import MemoryMap, AddressBlock, Register, RegField # NEW + +# Namespaces used in Xilinx IP-XACT component.xml +NS = { + "spirit": "http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009", + "xilinx": "http://www.xilinx.com", +} + +def _is_slave(busif: ET.Element) -> bool: + return busif.find("spirit:slave", NS) is not None + +def _text(el: Optional[ET.Element]) -> Optional[str]: + return el.text.strip() if el is not None and el.text is not None else None + +def _int(el: Optional[ET.Element]) -> Optional[int]: + t = _text(el) + if t is None: + return None + try: + return int(t, 0) # supports hex/dec + except ValueError: + return None + +def _param_map(busif: ET.Element) -> Dict[str, str]: + params = {} + for p in busif.findall("spirit:parameters/spirit:parameter", NS): + name = _text(p.find("spirit:name", NS)) + val = _text(p.find("spirit:value", NS)) + if name and val is not None: + params[name.strip().upper()] = val.strip() + return params + +def _bus_type(busif: ET.Element) -> tuple[str, str, str, str]: + b = busif.find("spirit:busType", NS) + return ( + b.get(f"{{{NS['spirit']}}}vendor", ""), + b.get(f"{{{NS['spirit']}}}library", ""), + b.get(f"{{{NS['spirit']}}}name", ""), + b.get(f"{{{NS['spirit']}}}version", ""), + ) + +def _to_port_type(bus_vendor: str, bus_lib: str, bus_name: str, + params: Dict[str, str], is_slave: bool) -> Optional[PortType]: + key = (bus_vendor, bus_lib, bus_name) + + if key == ("xilinx.com", "interface", "axis"): + return PortType.AXIS + + if key == ("xilinx.com", "interface", "aximm"): + if params.get("PROTOCOL", "").strip().upper() == "AXI4LITE": + return PortType.AXILITE + if is_slave: + return PortType.AXILITE + return PortType.AXI4FULL + + if key == ("xilinx.com", "signal", "clock"): + return PortType.CLOCK + if key == ("xilinx.com", "signal", "reset"): + return PortType.RESET + if key == ("xilinx.com", "signal", "interrupt"): + return PortType.INTERRUPT + + return None + +def _axis_width_from_params(params: Dict[str, str]) -> Optional[int]: + tbytes = params.get("TDATA_NUM_BYTES") + if tbytes and tbytes.isdigit(): + return int(tbytes) * 8 + return None + +def _aximm_width_from_params(params: Dict[str, str]) -> Optional[int]: + dw = params.get("DATA_WIDTH") + if dw and dw.isdigit(): + return int(dw) + return None + +# ---------- NEW: memory map parsing ---------- + +def _parse_fields(reg_el: ET.Element) -> List[RegField]: + fields: List[RegField] = [] + for f in reg_el.findall("spirit:field", NS): + fields.append(RegField( + name=_text(f.find("spirit:name", NS)) or "", + description=_text(f.find("spirit:description", NS)), + bit_offset=_int(f.find("spirit:bitOffset", NS)) or 0, + bit_width=_int(f.find("spirit:bitWidth", NS)) or 1, + access=_text(f.find("spirit:access", NS)), + modified_write_value=_text(f.find("spirit:modifiedWriteValue", NS)), + read_action=_text(f.find("spirit:readAction", NS)), + reset_value=_int(f.find("spirit:reset/spirit:value", NS)), + )) + return fields + +def _parse_registers(ab_el: ET.Element) -> List[Register]: + regs: List[Register] = [] + for r in ab_el.findall("spirit:register", NS): + regs.append(Register( + name=_text(r.find("spirit:name", NS)) or "", + display_name=_text(r.find("spirit:displayName", NS)), + description=_text(r.find("spirit:description", NS)), + address_offset=_int(r.find("spirit:addressOffset", NS)) or 0, + size=_int(r.find("spirit:size", NS)) or 32, + access=_text(r.find("spirit:access", NS)), + reset_value=_int(r.find("spirit:reset/spirit:value", NS)), + fields=_parse_fields(r), + )) + return regs + +def _parse_address_blocks(mm_el: ET.Element) -> List[AddressBlock]: + blocks: List[AddressBlock] = [] + for ab in mm_el.findall("spirit:addressBlock", NS): + # Optional named params inside addressBlock/parameters + obp = None + ohp = None + for p in ab.findall("spirit:parameters/spirit:parameter", NS): + pname = _text(p.find("spirit:name", NS)) + pval = _text(p.find("spirit:value", NS)) + if pname == "OFFSET_BASE_PARAM": + obp = pval + elif pname == "OFFSET_HIGH_PARAM": + ohp = pval + + blocks.append(AddressBlock( + name=_text(ab.find("spirit:name", NS)) or "unnamed", + base_address=_int(ab.find("spirit:baseAddress", NS)) or 0, + range=_int(ab.find("spirit:range", NS)) or 0, + width=_int(ab.find("spirit:width", NS)) or 32, + usage=_text(ab.find("spirit:usage", NS)), + access=_text(ab.find("spirit:access", NS)), + offset_base_param=obp, + offset_high_param=ohp, + registers=_parse_registers(ab), + )) + return blocks + +def _parse_memory_maps(root: ET.Element) -> List[MemoryMap]: + maps: List[MemoryMap] = [] + for mm in root.findall("spirit:memoryMaps/spirit:memoryMap", NS): + maps.append(MemoryMap( + name=_text(mm.find("spirit:name", NS)) or "unnamed", + address_blocks=_parse_address_blocks(mm), + )) + return maps + +# ---------- main entry ---------- + +def parse_component_xml(path: str | Path) -> Kernel: + path = Path(path) + tree = ET.parse(path) + root = tree.getroot() + + k_vendor = _text(root.find("spirit:vendor", NS)) or "" + k_lib = _text(root.find("spirit:library", NS)) or "" + k_name = _text(root.find("spirit:name", NS)) or "unknown" + k_ver = _text(root.find("spirit:version", NS)) or "" + vlnv = f"{k_vendor}:{k_lib}:{k_name}:{k_ver}" + + kernel_name = k_name + ports: Dict[str, Port] = {} + + for busif in root.findall("spirit:busInterfaces/spirit:busInterface", NS): + busif_name = _text(busif.find("spirit:name", NS)) + if not busif_name: + continue + params = _param_map(busif) + vendor, lib, bname, _ = _bus_type(busif) + is_slave = _is_slave(busif) + ptype = _to_port_type(vendor, lib, bname, params, is_slave) + if ptype is None: + continue + + width: Optional[int] = None + if ptype == PortType.AXIS: + width = _axis_width_from_params(params) + elif ptype in (PortType.AXILITE, PortType.AXI4FULL): + width = _aximm_width_from_params(params) + else: + width = 1 + + ports[busif_name] = Port(name=busif_name, ptype=ptype, width=width) + + memory_maps = _parse_memory_maps(root) # NEW + + return Kernel(name=kernel_name, ports=ports, vlnv=vlnv, memory_maps=memory_maps) diff --git a/linker/src/parser/config_parser.py b/linker/src/parser/config_parser.py new file mode 100644 index 00000000..395e76ba --- /dev/null +++ b/linker/src/parser/config_parser.py @@ -0,0 +1,244 @@ +from __future__ import annotations +from dataclasses import dataclass +from pathlib import Path +from typing import Dict, List, Optional, Tuple +import re + +from core.kernel import Kernel, KernelInstance +from core.connectivity import * +from core.port import PortType, Port + +# ----------------------------- +# Network model (local) +# ----------------------------- + +@dataclass +class NetworkSpec: + enabled_eth: set[int] + +# ----------------------------- +# Parsing helpers +# ----------------------------- + +_RE_TARGET = re.compile(r"^\s*([A-Za-z]+)\s*(\d*)\s*$") +_RE_NK = re.compile(r"^\s*([^:]+)\s*:\s*(\d+)(?::(.*))?\s*$") +_RE_ETH_KEY = re.compile(r"^eth_(\d+)$", re.IGNORECASE) + +def _parse_target(s: str) -> MemoryTarget: + m = _RE_TARGET.match(s) + if not m: + raise ValueError(f"Invalid memory target '{s}'. Expected e.g. HBM0, DDR3, MEM, HOST.") + domain, idx_str = m.group(1).upper(), m.group(2) + if domain not in {"HBM", "DDR", "MEM", "VIRT", "HOST"}: + raise ValueError(f"Unsupported memory domain '{domain}'. Use HBM, DDR, MEM, VIRT or HOST.") + # HOST (and MEM) have no numeric index + idx = int(idx_str) if (idx_str and domain not in {"MEM", "HOST"}) else "" + return MemoryTarget(domain=domain, index=idx) + + +def _split_instance_names(s: str) -> list[str]: + return [x for x in re.split(r"[.\s,]+", s.strip()) if x] + +def _parse_nk_value(val: str) -> NKSpec: + """ + Accepts: + nk=perf:15:perf_0.perf_1....perf_14 + nk=dma:2:dma_0 dma_1 + nk=offset:1:offset_0 + nk=foo:3 # auto-names: foo_0..foo_2 + """ + m = _RE_NK.match(val) + if not m: + raise ValueError(f"Invalid nk entry: '{val}' (expected ':[:]').") + + kernel_type = m.group(1).strip() + count = int(m.group(2)) + names_str = (m.group(3) or "").strip() + + names = _split_instance_names(names_str) if names_str else [] + if len(names) != count: + # Auto-fill or trim to match 'count' + base = kernel_type + names = (names + [f"{base}_{i}" for i in range(len(names), count)])[:count] + + return NKSpec(kernel_type=kernel_type, count=count, instance_names=names) + +def _parse_stream_connect_value(val: str) -> StreamConnect: + """ + Expects: 'srcInst.srcPort:dstInst.dstPort' + """ + try: + left, right = val.split(":") + src_inst, src_port = left.split(".", 1) + dst_inst, dst_port = right.split(".", 1) + return StreamConnect(src_inst.strip(), src_port.strip(), + dst_inst.strip(), dst_port.strip()) + except Exception as e: + raise ValueError(f"Invalid stream_connect '{val}'. Expected 'a.b:c.d'") from e + +def _parse_sp_value(val: str) -> SpMapping: + """ + Expects: 'inst.port:HBM0' or 'inst.port:DDR3' + """ + try: + left, right = val.split(":") + inst, port = left.split(".", 1) + except Exception as e: + raise ValueError(f"Invalid sp '{val}'. Expected 'inst.port:TARGET'") from e + target = _parse_target(right.strip()) + return SpMapping(inst=inst.strip(), port=port.strip(), target=target) + +# ----------------------------- +# Main parser +# ----------------------------- + +def parse_connectivity_file(path: str | Path) -> ConnectivityConfig: + """ + Custom parser that supports repeated [clock] sections, [network] section, + and a single [connectivity] section. + Lines beginning with '#' or ';' are ignored as comments. + """ + cfg = ConnectivityConfig() + path = Path(path) + lines = path.read_text(encoding="utf-8").splitlines() + + section: Optional[str] = None + pending_clock: Dict[str, str] = {} + enabled_eth: set[int] = set() + + def _commit_clock(): + nonlocal pending_clock + if not pending_clock: + return + krnl = pending_clock.get("krnl") + freq = pending_clock.get("freqhz") + if krnl and freq: + try: + cfg.clocks.append(ClockSpec(inst=krnl.strip(), freq_hz=int(freq.strip()))) + except ValueError: + raise ValueError(f"Invalid freqhz value in [clock]: '{freq}'") + elif krnl or freq: + raise ValueError("Incomplete [clock] block: both 'krnl' and 'freqhz' are required.") + pending_clock = {} + + for raw in lines: + line = raw.strip() + if not line or line.startswith("#") or line.startswith(";"): + continue + + if line.startswith("[") and line.endswith("]"): + # New section starting — commit any pending clock + _commit_clock() + section = line[1:-1].strip().lower() + continue + + if section == "connectivity": + if line.startswith("nk="): + cfg.nk.append(_parse_nk_value(line.split("=", 1)[1].strip())) + elif line.startswith("stream_connect="): + cfg.streams.append(_parse_stream_connect_value(line.split("=", 1)[1].strip())) + elif line.startswith("sp="): + cfg.sps.append(_parse_sp_value(line.split("=", 1)[1].strip())) + else: + pass + + elif section == "clock": + # Accumulate key-value pairs for this clock block + if "=" in line: + k, v = line.split("=", 1) + pending_clock[k.strip().lower()] = v.strip() + else: + raise ValueError(f"Invalid line in [clock] section: '{line}'") + + elif section == "network": + # Parse eth_=<0|1> (nonzero means enabled) + if "=" not in line: + raise ValueError(f"Invalid line in [network] section: '{line}'") + k, v = [t.strip() for t in line.split("=", 1)] + m = _RE_ETH_KEY.match(k) + if not m: + # ignore unknown keys in [network] to be lenient + continue + idx = int(m.group(1)) + try: + val = int(v, 0) + except ValueError: + val = 0 + if val != 0: + enabled_eth.add(idx) + + else: + pass + + # End of file: commit any trailing clock block + _commit_clock() + + # Attach network spec (works even if ConnectivityConfig has no typed field) + net = NetworkSpec(enabled_eth=enabled_eth) + try: + cfg.network = net # type: ignore[attr-defined] + except Exception: + setattr(cfg, "network", net) + + return cfg + +def _resolve_port_name_for_kernel(kernel: Kernel, requested: str) -> str: + # Case-insensitive resolution to the canonical name from component.xml + if requested in kernel.ports: + return requested + low_map = {n.lower(): n for n in kernel.ports.keys()} + req = requested.lower() + if req in low_map: + return low_map[req] + raise KeyError( + f"Port '{requested}' not found on kernel '{kernel.name}'. " + f"Available: {list(kernel.ports.keys())}" + ) + +def apply_config_to_instances( + cfg: ConnectivityConfig, + kernel_library: Dict[str, Kernel], + *, + default_ddr_index: int = 0 # DDR0 fallback for missing AXI4FULL ports +) -> Tuple[Dict[str, KernelInstance], List[StreamConnect]]: + instances: Dict[str, KernelInstance] = {} + + # 1) Instantiate from nk + for nk in cfg.nk: + if nk.kernel_type not in kernel_library: + raise KeyError(f"Kernel type '{nk.kernel_type}' not found in kernel_library.") + k = kernel_library[nk.kernel_type] + for name in nk.instance_names: + if name in instances: + raise ValueError(f"Duplicate instance name '{name}'.") + instances[name] = KernelInstance(name=name, kernel=k) + + # 2) Attach clock frequencies + for c in cfg.clocks: + if c.inst not in instances: + raise KeyError(f"[clock] refers to unknown instance '{c.inst}'.") + instances[c.inst].params["clock_hz"] = c.freq_hz + + # 3) Apply explicit sp mappings (store with CANONICAL port names) + for sp in cfg.sps: + if sp.inst not in instances: + raise KeyError(f"[connectivity] sp refers to unknown instance '{sp.inst}'.") + inst = instances[sp.inst] + canon_port = _resolve_port_name_for_kernel(inst.kernel, sp.port) + if inst.kernel.port(canon_port).ptype != PortType.AXI4FULL: + raise ValueError( + f"[connectivity] sp '{sp.inst}.{sp.port}' is not an AXI4FULL port on kernel '{inst.kernel.name}'." + ) + mem_map: Dict[str, dict] = inst.params.setdefault("mem_sp", {}) + mem_map[canon_port] = {"domain": sp.target.domain, "index": sp.target.index} + + # 4) Per-instance fallback: fill ONLY the missing AXI4FULL ports with MEM (round-robin later) + for inst in instances.values(): + mem_map: Dict[str, dict] = inst.params.setdefault("mem_sp", {}) + axi_full_ports = [p.name for p in inst.kernel.ports_of_type(PortType.AXI4FULL)] + for pname in axi_full_ports: + if pname not in mem_map: + mem_map[pname] = {"domain": "MEM", "index": ""} + + # return streams as-is; networking layer will split eth_* endpoints later + return instances, cfg.streams diff --git a/submodules/v80-vitis-flow/iprepo/.gitkeep b/linker/submodules/.gitkeep similarity index 100% rename from submodules/v80-vitis-flow/iprepo/.gitkeep rename to linker/submodules/.gitkeep diff --git a/submodules/pcie-hotplug-drv/Makefile b/submodules/pcie-hotplug-drv/Makefile index 0c12e538..8c3ddd1a 100644 --- a/submodules/pcie-hotplug-drv/Makefile +++ b/submodules/pcie-hotplug-drv/Makefile @@ -17,11 +17,14 @@ KMOD := pcie_hotplug KDIR := /lib/modules/$(shell uname -r)/build PWD := $(shell pwd) CC := g++ +QDMA_DIR_ABS := $(shell cd $(PWD)/../qdma_drv/QDMA/linux-kernel/driver && pwd) + +export KBUILD_EXTRA_SYMBOLS := $(QDMA_DIR_ABS)/src/Module.symvers all: $(KMOD).ko $(KMOD).ko: driver/$(KMOD).c - $(MAKE) -C $(KDIR) M=$(PWD)/driver modules + $(MAKE) -C $(KDIR) M=$(PWD)/driver QDMA_DIR_ABS=$(QDMA_DIR_ABS) modules clean: $(MAKE) -C $(KDIR) M=$(PWD)/driver clean diff --git a/submodules/pcie-hotplug-drv/driver/Makefile b/submodules/pcie-hotplug-drv/driver/Makefile index 32ce55d5..fc5c9682 100644 --- a/submodules/pcie-hotplug-drv/driver/Makefile +++ b/submodules/pcie-hotplug-drv/driver/Makefile @@ -16,8 +16,11 @@ obj-m := pcie_hotplug.o KDIR := /lib/modules/$(shell uname -r)/build PWD := $(shell pwd) +EXTRA_CFLAGS += -I$(QDMA_DIR_ABS)/libqdma \ + -I$(QDMA_DIR_ABS)/libqdma/qdma_access + all: - $(MAKE) -C $(KDIR) M=$(PWD) modules + $(MAKE) -C $(KDIR) M=$(PWD) modules EXTRA_CFLAGS="$(EXTRA_CFLAGS)" clean: - $(MAKE) -C $(KDIR) M=$(PWD) clean \ No newline at end of file + $(MAKE) -C $(KDIR) M=$(PWD) clean diff --git a/submodules/pcie-hotplug-drv/driver/pcie_hotplug.c b/submodules/pcie-hotplug-drv/driver/pcie_hotplug.c index a60e1fa9..03e19189 100644 --- a/submodules/pcie-hotplug-drv/driver/pcie_hotplug.c +++ b/submodules/pcie-hotplug-drv/driver/pcie_hotplug.c @@ -15,6 +15,10 @@ #include "pcie_hotplug.h" #include +#ifdef RHEL_RELEASE_CODE +#include +#endif + #if (defined(LINUX_VERSION_CODE) && defined(KERNEL_VERSION) && \ (LINUX_VERSION_CODE >= KERNEL_VERSION(6,4,0))) || \ (defined(RHEL_RELEASE_CODE) && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(9,0))) @@ -365,60 +369,250 @@ static int pcie_hotplug_release(struct inode *inode, struct file *file) { return 0; } -static ssize_t pcie_hotplug_write(struct file* file, const char __user* buffer, size_t len, loff_t* offset) { - char cmd[16]; +static long pcie_hotplug_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { struct pcie_hotplug_device *dev = file->private_data; - if(len > 15) { - return -EINVAL; - } + switch (cmd) { + case PCIE_IOCTL_RESCAN: + handle_rescan(); + break; + case PCIE_IOCTL_REMOVE: + handle_pcie_remove(dev); + break; + case PCIE_IOCTL_TOGGLE_SBR: + toggle_sbr(dev); + break; + case PCIE_IOCTL_HOTPLUG: + handle_pcie_hotplug(dev); + break; + case PCIE_IOCTL_GET_BAR_VAL: { + struct pcie_bar_read barreq; + void __iomem *mapped; + struct pci_dev *pdev = get_pci_dev_by_bdf(dev->bdf); + if (!pdev) + return -ENODEV; + + if (copy_from_user(&barreq, (void __user *)arg, sizeof(barreq))) + return -EFAULT; + + if (barreq.bar_index >= PCI_STD_NUM_BARS) + return -EINVAL; + + // Sanity check: BAR must exist + if (!(pci_resource_flags(pdev, barreq.bar_index) & IORESOURCE_MEM)) + return -EINVAL; + + if (barreq.offset >= pci_resource_len(pdev, barreq.bar_index)) + return -EINVAL; + + // Map BAR temporarily + mapped = pci_iomap(pdev, barreq.bar_index, 0); + if (!mapped) + return -ENOMEM; + + barreq.value = ioread32(mapped + barreq.offset); + pci_iounmap(pdev, mapped); + + if (copy_to_user((void __user *)arg, &barreq, sizeof(barreq))) + return -EFAULT; + + return 0; + } - if(copy_from_user(cmd, buffer, len)) { - return -EFAULT; - } + case PCIE_IOCTL_SET_BAR_VAL: { + struct pcie_bar_write barreq; + void __iomem *mapped; + struct pci_dev *pdev = get_pci_dev_by_bdf(dev->bdf); + if (!pdev) + return -ENODEV; - cmd[len] = '\0'; - printk(KERN_INFO "Received command: %s\n", cmd); + if (copy_from_user(&barreq, (void __user *)arg, sizeof(barreq))) + return -EFAULT; - if(strncmp(cmd, "rescan", 6) == 0) { - handle_rescan(); - } else if(strncmp(cmd, "remove", 6) == 0) { - handle_pcie_remove(dev); - } else if(strncmp(cmd, "toggle_sbr", 10) == 0) { - toggle_sbr(dev); - } else if(strncmp(cmd, "hotplug", 7) == 0) { - handle_pcie_hotplug(dev); - } else { - printk(KERN_WARNING "Invalid command\n"); + if (barreq.bar_index >= PCI_STD_NUM_BARS) + return -EINVAL; + + if (!(pci_resource_flags(pdev, barreq.bar_index) & IORESOURCE_MEM)) + return -EINVAL; + + if (barreq.offset >= pci_resource_len(pdev, barreq.bar_index)) + return -EINVAL; + + mapped = pci_iomap(pdev, barreq.bar_index, 0); + if (!mapped) + return -ENOMEM; + + iowrite32(barreq.value, mapped + barreq.offset); + + pci_iounmap(pdev, mapped); + return 0; + } + + case PCIE_IOCTL_READ_BAR_RANGE: { + struct pcie_bar_range range; + void __iomem *mapped; + struct pci_dev *pdev = get_pci_dev_by_bdf(dev->bdf); + if (!pdev) + return -ENODEV; + + if (copy_from_user(&range, (void __user *)arg, sizeof(range))) + return -EFAULT; + + if (range.bar_index >= PCI_STD_NUM_BARS || + range.size > MAX_BAR_RW_SIZE || + range.offset + range.size > pci_resource_len(pdev, range.bar_index)) + return -EINVAL; + + mapped = pci_iomap(pdev, range.bar_index, 0); + if (!mapped) + return -ENOMEM; + + memcpy_fromio(range.data, mapped + range.offset, range.size); + pci_iounmap(pdev, mapped); + + if (copy_to_user((void __user *)arg, &range, sizeof(range))) + return -EFAULT; + + return 0; + } + + case PCIE_IOCTL_WRITE_BAR_RANGE: { + struct pcie_bar_range range; + void __iomem *mapped; + struct pci_dev *pdev = get_pci_dev_by_bdf(dev->bdf); + if (!pdev) + return -ENODEV; + + if (copy_from_user(&range, (void __user *)arg, sizeof(range))) + return -EFAULT; + + if (range.bar_index >= PCI_STD_NUM_BARS || + range.size > MAX_BAR_RW_SIZE || + range.offset + range.size > pci_resource_len(pdev, range.bar_index)) + return -EINVAL; + + mapped = pci_iomap(pdev, range.bar_index, 0); + if (!mapped) + return -ENOMEM; + + memcpy_toio(mapped + range.offset, range.data, range.size); + pci_iounmap(pdev, mapped); + + return 0; + } + + + + default: + printk(KERN_WARNING "Invalid IOCTL command: 0x%x\n", cmd); + return -EINVAL; } - return len; + return 0; } static struct file_operations fops = { .owner = THIS_MODULE, .open = pcie_hotplug_open, .release = pcie_hotplug_release, - .write = pcie_hotplug_write, + .unlocked_ioctl = pcie_hotplug_ioctl, }; -static void discover_and_add_devices(void) { - struct pci_dev *pdev = NULL; +static int pcie_hotplug_probe(struct pci_dev *pdev, const struct pci_device_id *id) { + int ret; char bdf[16]; - const struct pci_device_id *id; + struct pcie_hotplug_device *dev; + struct qdma_dev_conf conf; - for_each_pci_dev(pdev) { - for (id = pcie_hotplug_ids; id->vendor != 0; id++) { - if (pdev->vendor == id->vendor && pdev->device == id->device && PCI_FUNC(pdev->devfn) == 0) { - snprintf(bdf, sizeof(bdf), "%04x:%02x:%02x.%x", - pci_domain_nr(pdev->bus), - pdev->bus->number, - PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn)); - add_device(bdf); - } - } + pci_enable_device(pdev); + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + snprintf(bdf, sizeof(bdf), "%04x:%02x:%02x.%x", + pci_domain_nr(pdev->bus), + pdev->bus->number, + PCI_SLOT(pdev->devfn), + PCI_FUNC(pdev->devfn)); + + dev->bdf = kstrdup(bdf, GFP_KERNEL); + if (!dev->bdf) { + kfree(dev); + return -ENOMEM; + } + + ret = get_bdfs(dev->bdf, dev->rootport_bdf); + if (ret < 0) + goto err_bdf; + + ret = alloc_chrdev_region(&dev->devt, 0, 1, DEVICE_NAME); + if (ret < 0) + goto err_bdf; + + cdev_init(&dev->cdev, &fops); + dev->cdev.owner = THIS_MODULE; + + ret = cdev_add(&dev->cdev, dev->devt, 1); + if (ret < 0) + goto err_chrdev; + + device_create(pcie_hotplug_class, NULL, dev->devt, NULL, "pcie_hotplug_%s", dev->bdf); + + pci_set_drvdata(pdev, dev); // link device struct to PCI dev + list_add(&dev->list, &device_list); + device_count++; + + printk(KERN_INFO "PCIe hotplug probe: %s\n", dev->bdf); + // printk((KERN_INFO "Probing QDMA for device: %s\n", dev->bdf)); + + memset(&conf, 0, sizeof(conf)); + conf.qdma_drv_mode = POLL_MODE; + conf.intr_rngsz = QDMA_INTR_COAL_RING_SIZE; + conf.pdev = get_next_function_pci_dev(dev->bdf); + if (!conf.pdev) { + printk(KERN_ERR "Failed to get next function PCI device for %s\n", dev->bdf); + ret = -ENODEV; + goto err_chrdev; + } + conf.bar_num_config = -1; + conf.bar_num_user = -1; + conf.bar_num_bypass = -1; + + conf.bar_num_config = 2; // @TODO fix //extract_mod_param(pdev, CONFIG_BAR); + conf.qsets_max = 0; + conf.qsets_base = -1; + conf.msix_qvec_max = 32; + conf.user_msix_qvec_max = 1; + ret = qdma_device_open("pcie_hotplug", &conf, &dev->dev_hndl); + if (ret < 0 && ret != -ENODEV) { + printk(KERN_ERR "Failed to open QDMA device: %d\n", ret); + goto err_chrdev; } + return 0; + +err_chrdev: + unregister_chrdev_region(dev->devt, 1); +err_bdf: + kfree(dev->bdf); + kfree(dev); + return ret; + +} + +static void pcie_hotplug_remove(struct pci_dev *pdev) { + struct pcie_hotplug_device *dev = pci_get_drvdata(pdev); + + if (!dev) + return; + + device_destroy(pcie_hotplug_class, dev->devt); + cdev_del(&dev->cdev); + unregister_chrdev_region(dev->devt, 1); + kfree(dev->bdf); + kfree(dev); + + printk(KERN_INFO "PCIe hotplug remove\n"); } static void add_device(const char *bdf) { @@ -469,8 +663,35 @@ static void add_device(const char *bdf) { printk(KERN_INFO "Added PCIe hotplug device: %s, root port: %s\n", dev->bdf, dev->rootport_bdf); } -static int __init pcie_hotplug_init(void) { +static void discover_and_add_devices(void) { + struct pci_dev *pdev = NULL; + char bdf[16]; + const struct pci_device_id *id; + + for_each_pci_dev(pdev) { + for (id = pcie_hotplug_ids; id->vendor != 0; id++) { + if (pdev->vendor == id->vendor && pdev->device == id->device && PCI_FUNC(pdev->devfn) == 0) { + snprintf(bdf, sizeof(bdf), "%04x:%02x:%02x.%x", + pci_domain_nr(pdev->bus), + pdev->bus->number, + PCI_SLOT(pdev->devfn), + PCI_FUNC(pdev->devfn)); + add_device(bdf); + } + } + } +} + +static struct pci_driver pcie_hotplug_driver = { + .name = "pcie_hotplug", + .id_table = pcie_hotplug_ids, + .probe = pcie_hotplug_probe, + .remove = pcie_hotplug_remove, +}; + +static int __init pcie_hotplug_init(void) { + int ret; // Register character device major_number = register_chrdev(0, DEVICE_NAME, &fops); if (major_number < 0) { @@ -478,6 +699,7 @@ static int __init pcie_hotplug_init(void) { return major_number; } + // Initialize class pcie_hotplug_class = CLASS_CREATE(CLASS_NAME); if (IS_ERR(pcie_hotplug_class)) { @@ -486,16 +708,32 @@ static int __init pcie_hotplug_init(void) { return PTR_ERR(pcie_hotplug_class); } - // Discover and add devices with the specified vendor ID + ret = pci_register_driver(&pcie_hotplug_driver); + if (ret < 0) { + class_destroy(pcie_hotplug_class); + unregister_chrdev(major_number, DEVICE_NAME); + return ret; + } + discover_and_add_devices(); printk(KERN_INFO "PCIe hotplug initialized\n"); + + ret = libqdma_init(8, NULL); + if (ret < 0) { + printk(KERN_ERR "Failed to initialize libqdma\n"); + pci_unregister_driver(&pcie_hotplug_driver); + class_destroy(pcie_hotplug_class); + unregister_chrdev(major_number, DEVICE_NAME); + return ret; + } return 0; } static void __exit pcie_hotplug_exit(void) { struct pcie_hotplug_device *dev, *tmp; - + + pci_unregister_driver(&pcie_hotplug_driver); list_for_each_entry_safe(dev, tmp, &device_list, list) { device_destroy(pcie_hotplug_class, dev->devt); cdev_del(&dev->cdev); @@ -507,6 +745,7 @@ static void __exit pcie_hotplug_exit(void) { class_unregister(pcie_hotplug_class); class_destroy(pcie_hotplug_class); unregister_chrdev(major_number, DEVICE_NAME); + libqdma_exit(); printk(KERN_INFO "pcie_hotplug module unloaded\n"); } diff --git a/submodules/pcie-hotplug-drv/driver/pcie_hotplug.h b/submodules/pcie-hotplug-drv/driver/pcie_hotplug.h index 11285a71..4a022e89 100644 --- a/submodules/pcie-hotplug-drv/driver/pcie_hotplug.h +++ b/submodules/pcie-hotplug-drv/driver/pcie_hotplug.h @@ -26,21 +26,13 @@ #include #include #include +#include #include "pcie_hotplug_ids.h" +#include "pcie_hotplug_ioctl.h" +#include "libqdma_export.h" -static int major_number; -static struct class* pcie_hotplug_class = NULL; - -struct pcie_hotplug_device { - char *bdf; - char rootport_bdf[32]; - dev_t devt; - struct cdev cdev; - struct list_head list; -}; - static LIST_HEAD(device_list); static int device_count = 0; @@ -56,7 +48,7 @@ static int device_count = 0; * Returns the PCI device corresponding to the given BDF. */ static struct pci_dev *get_pci_dev_by_bdf(const char* bdf); - + /** * get_bdfs - Get BDFs for the device and root port * @@ -102,36 +94,27 @@ static int device_count = 0; * Kernel Specific Functions */ - /** - * pcie_hotplug_write - Write handler for the character device - * @file: File structure - * @buffer: User buffer - * @len: Length of the buffer - * @offset: Offset in the file - * - * Handles write operations to the character device. - * - * Returns the number of bytes written on success, negative error code on failure. - */ - static ssize_t pcie_hotplug_write(struct file* file, const char __user* buffer, size_t len, loff_t* offset); - - // /** - // * @brief Store function for adding a new PCIe hotplug device. - // * - // * This function is called when a new device BDF is written to the sysfs entry. - // * It allocates and initializes a new `pcie_hotplug_device` structure, finds the - // * root port for the device, allocates a character device region, and creates - // * the character device. - // * - // * @param kobj Pointer to the kobject. - // * @param attr Pointer to the kobj_attribute. - // * @param buf Buffer containing the BDF string. - // * @param count Number of bytes in the buffer. - // * @return Number of bytes processed on success, negative error code on failure. - // */ - // static ssize_t add_device_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count); - - static void add_device(const char *bdf); + static int pcie_hotplug_probe(struct pci_dev *pdev, const struct pci_device_id *id); + + static void pcie_hotplug_remove(struct pci_dev *pdev); + + // // /** + // // * @brief Store function for adding a new PCIe hotplug device. + // // * + // // * This function is called when a new device BDF is written to the sysfs entry. + // // * It allocates and initializes a new `pcie_hotplug_device` structure, finds the + // // * root port for the device, allocates a character device region, and creates + // // * the character device. + // // * + // // * @param kobj Pointer to the kobject. + // // * @param attr Pointer to the kobj_attribute. + // // * @param buf Buffer containing the BDF string. + // // * @param count Number of bytes in the buffer. + // // * @return Number of bytes processed on success, negative error code on failure. + // // */ + // // static ssize_t add_device_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count); + + // static void add_device(const char *bdf); /** * pcie_hotplug_init - Module initialization function diff --git a/submodules/pcie-hotplug-drv/driver/pcie_hotplug_ids.h b/submodules/pcie-hotplug-drv/driver/pcie_hotplug_ids.h index 952d3b43..ac9a0701 100644 --- a/submodules/pcie-hotplug-drv/driver/pcie_hotplug_ids.h +++ b/submodules/pcie-hotplug-drv/driver/pcie_hotplug_ids.h @@ -40,4 +40,5 @@ static const struct pci_device_id pcie_hotplug_ids[] = { } /**< End of list */ }; + #endif // PCIE_HOTPLUG_IDS \ No newline at end of file diff --git a/submodules/pcie-hotplug-drv/driver/pcie_hotplug_ioctl.h b/submodules/pcie-hotplug-drv/driver/pcie_hotplug_ioctl.h new file mode 100644 index 00000000..3e0215d8 --- /dev/null +++ b/submodules/pcie-hotplug-drv/driver/pcie_hotplug_ioctl.h @@ -0,0 +1,68 @@ +#ifndef PCIE_HOTPLUG_IOCTL_H +#define PCIE_HOTPLUG_IOCTL_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define PCIE_IOCTL_MAGIC 0xB5 + +#define PCIE_IOCTL_RESCAN _IO(PCIE_IOCTL_MAGIC, 0x01) +#define PCIE_IOCTL_REMOVE _IO(PCIE_IOCTL_MAGIC, 0x02) +#define PCIE_IOCTL_TOGGLE_SBR _IO(PCIE_IOCTL_MAGIC, 0x03) +#define PCIE_IOCTL_HOTPLUG _IO(PCIE_IOCTL_MAGIC, 0x04) + +struct pcie_bar_read { + unsigned int bar_index; // IN: BAR number (0-5) + unsigned int offset; // IN: Offset in BAR to read + u32 value; // OUT: Value read (32-bit) +}; +#define PCIE_IOCTL_GET_BAR_VAL _IOWR(PCIE_IOCTL_MAGIC, 0x05, struct pcie_bar_read) + +struct pcie_bar_write { + uint8_t bar_index; + uint32_t offset; + uint32_t value; +}; + +#define PCIE_IOCTL_SET_BAR_VAL _IOWR(PCIE_IOCTL_MAGIC, 0x06, struct pcie_bar_write) + + +static int major_number; +static struct class* pcie_hotplug_class = NULL; + +struct pcie_hotplug_device { + char *bdf; + char rootport_bdf[32]; + dev_t devt; + struct cdev cdev; + struct list_head list; + unsigned long dev_hndl; // Handle for libqdma +}; + +#define MAX_BAR_RW_SIZE 128 // Adjust as needed + +struct pcie_bar_range { + uint8_t bar_index; + uint32_t offset; + uint32_t size; + uint8_t data[MAX_BAR_RW_SIZE]; // For both read & write +}; + +#define PCIE_IOCTL_READ_BAR_RANGE _IOWR(PCIE_IOCTL_MAGIC, 0x07, struct pcie_bar_range) +#define PCIE_IOCTL_WRITE_BAR_RANGE _IOWR(PCIE_IOCTL_MAGIC, 0x08, struct pcie_bar_range) + + +static long pcie_hotplug_ioctl(struct file *file, unsigned int cmd, unsigned long arg); + +#endif // PCIE_HOTPLUG_IOCTL_H \ No newline at end of file diff --git a/submodules/pcie-hotplug-drv/main.c b/submodules/pcie-hotplug-drv/main.c new file mode 100644 index 00000000..dac0f2cd --- /dev/null +++ b/submodules/pcie-hotplug-drv/main.c @@ -0,0 +1,216 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCIE_IOCTL_MAGIC 0xB5 +#define PCIE_IOCTL_RESCAN _IO(PCIE_IOCTL_MAGIC, 0x01) +#define PCIE_IOCTL_REMOVE _IO(PCIE_IOCTL_MAGIC, 0x02) +#define PCIE_IOCTL_TOGGLE_SBR _IO(PCIE_IOCTL_MAGIC, 0x03) +#define PCIE_IOCTL_HOTPLUG _IO(PCIE_IOCTL_MAGIC, 0x04) + +struct pcie_bar_read { + uint32_t bar_index; + uint32_t offset; + uint32_t value; +}; + +struct pcie_bar_write { + uint8_t bar_index; + uint32_t offset; + uint32_t value; +}; + +#define PCIE_IOCTL_GET_BAR_VAL _IOWR(PCIE_IOCTL_MAGIC, 0x05, struct pcie_bar_read) +#define PCIE_IOCTL_SET_BAR_VAL _IOWR(PCIE_IOCTL_MAGIC, 0x06, struct pcie_bar_write) + +#define MAX_BAR_RW_SIZE 128 + +struct pcie_bar_range { + uint8_t bar_index; + uint32_t offset; + uint32_t size; + uint8_t data[MAX_BAR_RW_SIZE]; +}; + +#define PCIE_IOCTL_READ_BAR_RANGE _IOWR(PCIE_IOCTL_MAGIC, 0x07, struct pcie_bar_range) +#define PCIE_IOCTL_WRITE_BAR_RANGE _IOWR(PCIE_IOCTL_MAGIC, 0x08, struct pcie_bar_range) + + +void usage(const char *prog) { + fprintf(stderr, + "Usage:\n" + " %s \n" + " %s bar_read \n" + " %s bar_write \n" + "Example:\n" + " %s /dev/pcie_hotplug_0000:c4:00.0 remove\n" + " %s /dev/pcie_hotplug_0000:c4:00.0 bar_read 0 0x10\n" + " %s /dev/pcie_hotplug_0000:c4:00.0 bar_write 0 0x10 0xdeadbeef\n", + prog, prog, prog, prog, prog, prog); +} + +int main(int argc, char *argv[]) { + int fd, ret; + unsigned long cmd = 0; + + if (argc < 3) { + usage(argv[0]); + return EXIT_FAILURE; + } + + const char *devnode = argv[1]; + const char *action = argv[2]; + + fd = open(devnode, O_RDWR); + if (fd < 0) { + perror("Failed to open device"); + return EXIT_FAILURE; + } + + if (strcmp(action, "rescan") == 0) + cmd = PCIE_IOCTL_RESCAN; + else if (strcmp(action, "remove") == 0) + cmd = PCIE_IOCTL_REMOVE; + else if (strcmp(action, "toggle_sbr") == 0) + cmd = PCIE_IOCTL_TOGGLE_SBR; + else if (strcmp(action, "hotplug") == 0) + cmd = PCIE_IOCTL_HOTPLUG; + else if (strcmp(action, "bar_read") == 0) { + if (argc != 5) { + fprintf(stderr, "Usage: %s bar_read \n", argv[0]); + close(fd); + return EXIT_FAILURE; + } + + struct pcie_bar_read bar = {0}; + bar.bar_index = strtoul(argv[3], NULL, 0); + bar.offset = strtoul(argv[4], NULL, 0); + + ret = ioctl(fd, PCIE_IOCTL_GET_BAR_VAL, &bar); + if (ret < 0) { + if (errno == EINVAL) + fprintf(stderr, "Invalid BAR index or offset\n"); + else + perror("ioctl failed"); + close(fd); + return EXIT_FAILURE; + } + + printf("BAR[%u] offset 0x%x: value = 0x%08x\n", + bar.bar_index, bar.offset, bar.value); + close(fd); + return EXIT_SUCCESS; + } else if (strcmp(action, "bar_write") == 0) { + if (argc != 6) { + fprintf(stderr, "Usage: %s bar_write \n", argv[0]); + close(fd); + return EXIT_FAILURE; + } + + struct pcie_bar_write bar = {0}; + bar.bar_index = strtoul(argv[3], NULL, 0); + bar.offset = strtoul(argv[4], NULL, 0); + bar.value = strtoul(argv[5], NULL, 0); + + ret = ioctl(fd, PCIE_IOCTL_SET_BAR_VAL, &bar); + if (ret < 0) { + if (errno == EINVAL) + fprintf(stderr, "Invalid BAR index or offset\n"); + else + perror("ioctl failed"); + close(fd); + return EXIT_FAILURE; + } + + printf("Wrote 0x%08x to BAR[%u] offset 0x%x\n", + bar.value, bar.bar_index, bar.offset); + close(fd); + return EXIT_SUCCESS; + } else if (strcmp(action, "bar_read_range") == 0) { + if (argc != 6) { + fprintf(stderr, "Usage: %s bar_read_range \n", argv[0]); + close(fd); + return EXIT_FAILURE; + } + + struct pcie_bar_range range = {0}; + range.bar_index = strtoul(argv[3], NULL, 0); + range.offset = strtoul(argv[4], NULL, 0); + range.size = strtoul(argv[5], NULL, 0); + if (range.size > MAX_BAR_RW_SIZE) { + fprintf(stderr, "Max range read size is %d bytes\n", MAX_BAR_RW_SIZE); + close(fd); + return EXIT_FAILURE; + } + + ret = ioctl(fd, PCIE_IOCTL_READ_BAR_RANGE, &range); + if (ret < 0) { + perror("ioctl failed"); + close(fd); + return EXIT_FAILURE; + } + + printf("BAR[%u] offset 0x%x, size %u:\n", range.bar_index, range.offset, range.size); + for (uint32_t i = 0; i < range.size; i++) { + printf("%02x ", range.data[i]); + if ((i + 1) % 16 == 0) printf("\n"); + } + if (range.size % 16 != 0) printf("\n"); + + close(fd); + return EXIT_SUCCESS; + } else if (strcmp(action, "bar_write_range") == 0) { + if (argc < 7) { + fprintf(stderr, "Usage: %s bar_write_range [byte1 ...]\n", argv[0]); + close(fd); + return EXIT_FAILURE; + } + + struct pcie_bar_range range = {0}; + range.bar_index = strtoul(argv[3], NULL, 0); + range.offset = strtoul(argv[4], NULL, 0); + range.size = strtoul(argv[5], NULL, 0); + + if (range.size > MAX_BAR_RW_SIZE || argc != 6 + range.size) { + fprintf(stderr, "Provide exactly %u bytes\n", range.size); + close(fd); + return EXIT_FAILURE; + } + + for (uint32_t i = 0; i < range.size; i++) { + range.data[i] = (uint8_t)strtoul(argv[6 + i], NULL, 0); + } + + ret = ioctl(fd, PCIE_IOCTL_WRITE_BAR_RANGE, &range); + if (ret < 0) { + perror("ioctl failed"); + close(fd); + return EXIT_FAILURE; + } + + printf("Wrote %u bytes to BAR[%u] offset 0x%x\n", range.size, range.bar_index, range.offset); + close(fd); + return EXIT_SUCCESS; + } else { + fprintf(stderr, "Unknown command: %s\n", action); + usage(argv[0]); + close(fd); + return EXIT_FAILURE; + } + + ret = ioctl(fd, cmd); + if (ret < 0) { + perror("ioctl failed"); + close(fd); + return EXIT_FAILURE; + } + + printf("Command '%s' executed successfully on %s\n", action, devnode); + close(fd); + return EXIT_SUCCESS; +} \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/arg_parser/arg_parser.hpp b/submodules/v80-vitis-flow/include/arg_parser/arg_parser.hpp index cc8d07a0..842080d0 100644 --- a/submodules/v80-vitis-flow/include/arg_parser/arg_parser.hpp +++ b/submodules/v80-vitis-flow/include/arg_parser/arg_parser.hpp @@ -156,6 +156,11 @@ class ArgParser { std::vector getKernelPaths(); /** + * @brief Sets the network interface flags. + * @param networkInterfaces Array of booleans indicating the status of enablement of each + * network interface. + */ + std::array getNetworkInterfaces() const; * @brief Gets the set of Tcl files to inject. * @return Structure representing the set of Tcl files to inject. */ @@ -171,6 +176,7 @@ class ArgParser { uint64_t freqHz; ///< Clock frequency in Hz bool segmented; ///< Flag indicating if the design is segmented Platform platform; ///< Target platform + std::array networkInterfaces = {false, false, false, false}; ///< Network interface flags TclInjections tclInjections; ///< Tcl files to inject /** @@ -183,6 +189,8 @@ class ArgParser { * @brief Parses the configuration file. */ void parseConfig(); + + bool isNetworkKernel(const std::string& kernelName); }; -#endif // ARG_PARSER_HPP \ No newline at end of file +#endif // ARG_PARSER_HPP diff --git a/submodules/v80-vitis-flow/include/bd_builder/bd_builder.hpp b/submodules/v80-vitis-flow/include/bd_builder/bd_builder.hpp index 616bcda7..09489da5 100644 --- a/submodules/v80-vitis-flow/include/bd_builder/bd_builder.hpp +++ b/submodules/v80-vitis-flow/include/bd_builder/bd_builder.hpp @@ -52,10 +52,12 @@ class BdBuilder { std::string INPUT_FILE_HW = "../resources/base_bd.tcl"; ///< Base TCL file for hardware platform std::string INPUT_FILE_SIM = - "../resources/sim_prj.tcl"; ///< Base TCL file for simulation platform - std::string PRE_OUTPUT_FILE = "run_pre.tcl"; ///< Output pre TCL file name - std::string POST_OUTPUT_FILE = "run_post.tcl"; ///< Output post TCL file name + "../resources/sim_prj.tcl"; ///< Base TCL file for simulation platform + std::string OUTPUT_FILE = "run_pre.tcl"; ///< Output TCL file name + std::string NET_CONFIG_FILE = "dcmac_config.tcl"; ///< Network configuration file std::string NOC_SOLUTION = "../resources/noc_sol_compute.ncr"; ///< NoC solution file path + std::string DCMAC_NOC_SOLUTION = + "../resources/noc_sol_dcmac.ncr"; ///< NoC solution file path for DCMAC std::string NOC0_ADDR_STR = " -target_address_space [get_bd_addr_spaces cips/CPM_PCIE_NOC_0] [get_bd_addr_segs " "base_logic/"; ///< NoC 0 address space TCL string @@ -70,10 +72,12 @@ class BdBuilder { 400; ///< Maximum allocable bandwidth for HBM per channel in MBps std::vector kernels; ///< List of kernels to include in the design std::vector streamConnections; ///< List of streaming connections between kernels + std::vector netConnections; ///< List of network connections between kernels uint64_t targetClockFreq; ///< Target clock frequency in Hz SystemMap systemMap; ///< System memory map for the design bool segmented; ///< Flag indicating if design is segmented - Platform platform; ///< Target platform (hardware, simulation, emulation) + Platform platform; ///< Target platform (hardware, simulation, emulation) + std::array netInterfaces; ///< Array indicating which network interfaces to use TclInjections tclInjections; ///< Set of Tcl files to inject /** @@ -98,11 +102,13 @@ class BdBuilder { * @param targetClockFreq Target clock frequency in Hz. * @param segmented Flag indicating if design is segmented. * @param platform Target platform (hardware, simulation, emulation). - * @param tclInjections Set of Tcl files to inject. + * @param netInterfaces Array indicating which network interfaces to use. + * @note The netInterfaces array should have 4 elements, each representing a network interface. + * The elements can be true (enabled) or false (disabled). */ BdBuilder(std::vector kernels, std::vector connections, double targetClockFreq, bool segmented, Platform platform, - TclInjections tclInjections); + std::array netInterfaces, TclInjections tclInjections); /** * @brief Builds the block design by generating TCL commands. @@ -355,4 +361,23 @@ class BdBuilder { * @return String containing TCL commands for script header. */ std::string addRunPreHeader(); + + /** + * @brief Generates TCL commands to configure network interfaces. + * @return String containing TCL commands for network interface configuration. + */ + std::string configNetInterfaces(); + + /** + * @brief Generates TCL commands to connect dummy traffic generator. + * @return String containing TCL commands for dummy traffic generator connection. + */ + std::string connectDummyTrafficGen(); + + /** + * @brief Generates TCL commands to add a crossbar for the design. + * @brief This is needed for projects where no dcmac is used, for NoC solution compatibility. + * @return String containing TCL commands for crossbar addition. + */ + std::string addBarCrossbar(); }; \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/xml_parser/kernel.hpp b/submodules/v80-vitis-flow/include/xml_parser/kernel.hpp index 3572c6ef..a6e221e7 100644 --- a/submodules/v80-vitis-flow/include/xml_parser/kernel.hpp +++ b/submodules/v80-vitis-flow/include/xml_parser/kernel.hpp @@ -57,6 +57,7 @@ class Kernel { AreaEstimates estimates; ///< Resource utilization estimates std::vector interfaces; ///< List of kernel interfaces std::vector registers; ///< List of registers in the kernel + bool networkKernel; ///< Flag indicating if the kernel is a network kernel public: /** @@ -217,4 +218,17 @@ class Kernel { * and registers for debugging or documentation. */ void print(); + + /** + * @brief Checks if the kernel is a network kernel. + * @return True if the kernel is a network kernel, false otherwise. + */ + void setNetworkKernel(); + + /** + * @brief Checks if the kernel is a network kernel. + * @return True if the kernel is a network kernel, false otherwise. + */ + bool isNetworkKernel(); + }; \ No newline at end of file diff --git a/submodules/v80-vitis-flow/iprepo/traffic_producer/Makefile b/submodules/v80-vitis-flow/iprepo/traffic_producer/Makefile new file mode 100644 index 00000000..e926c7d7 --- /dev/null +++ b/submodules/v80-vitis-flow/iprepo/traffic_producer/Makefile @@ -0,0 +1,11 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +all: ip/*.zip + +ip/*.zip: *.cpp + v++ -c --mode hls --config hls_config.cfg --work_dir ip + vitis-run --mode hls --package --config hls_config.cfg --work_dir ip + +clean: + rm -rf ip/ .Xil *.json \ No newline at end of file diff --git a/submodules/v80-vitis-flow/iprepo/traffic_producer/hls_config.cfg b/submodules/v80-vitis-flow/iprepo/traffic_producer/hls_config.cfg new file mode 100644 index 00000000..d12bf3e2 --- /dev/null +++ b/submodules/v80-vitis-flow/iprepo/traffic_producer/hls_config.cfg @@ -0,0 +1,12 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado +package.output.format=ip_catalog +package.output.syn=false +syn.top=traffic_producer +syn.file=traffic_producer.cpp +clock=300 \ No newline at end of file diff --git a/submodules/v80-vitis-flow/iprepo/traffic_producer/traffic_producer.cpp b/submodules/v80-vitis-flow/iprepo/traffic_producer/traffic_producer.cpp new file mode 100644 index 00000000..992cb9ec --- /dev/null +++ b/submodules/v80-vitis-flow/iprepo/traffic_producer/traffic_producer.cpp @@ -0,0 +1,35 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +#include "ap_axi_sdata.h" +#include "ap_int.h" +#include "hls_stream.h" + +#define DWIDTH 512 +#define TDWIDTH 3 + +typedef ap_axiu pkt; + +void traffic_producer(hls::stream &out, + ap_uint<32> flits, + ap_uint dest){ + +#pragma HLS INTERFACE mode=axis port=out depth=16 +#pragma HLS INTERFACE mode=s_axilite port=dest bundle=control +#pragma HLS INTERFACE mode=s_axilite port=flits bundle=control +#pragma HLS INTERFACE mode=s_axilite port=return bundle=control + + pkt axi_word; +generator: + for(unsigned int i=0; i< flits; i++){ + #pragma HLS PIPELINE II=1 + for(unsigned int j=0; j tuple[int, int]: + """Return the shift and mask give the key""" + map = shift_map[key] + return map['shift'], (1 << map['bits']) - 1 + + +def _get_updated_value(key: str, cval: int, nval: int) -> int: + """Generate the updated 32-bit value applying a shift and mask""" + + shift, mask = _get_shift_and_mask(key) + shiftedmask = np.uint32(mask << shift & 0xFFFF_FFFF) + cval_cleared = np.uint32(cval & ~shiftedmask) + shiftedval = np.uint32(((nval & mask) << shift) & 0xFFFF_FFFF) + + return np.uint32(shiftedval | cval_cleared) + + +class AxiGTController(AxiGpioMMIO): + + def __init__(self, device: str = 'e2', base_offset: int = 0x0, + gpio_index: int = 0): + self._gpio_index = gpio_index + super().__init__(device, base_offset) + + def _get(self, key: str, gpio: int = 0): + shift, mask = _get_shift_and_mask(key) + return (self.read(gpio) >> shift) & mask + + def _set(self, key: str, gpio: int, val: int): + if not isinstance(val, int_types): + raise ValueError(f"'{val=}' is not a '{int_types}' type") + + cval = self.read(gpio) + uval = _get_updated_value(key, cval, val) + self.write(gpio, uval) + + def _create_property(key: str, gpio: int = 0): + """Create property getter and setter for given key.""" + return property( + lambda self: self._get(key, gpio), + lambda self, val: self._set(key, gpio, val) + ) + + gt_reset = _create_property('gt_reset') + gt_line_rate = _create_property('gt_line_rate') + loopback = _create_property('loopback') + txprecursor = _create_property('txprecursor') + txpostcursor = _create_property('txpostcursor') + txmaincursor = _create_property('txmaincursor') + rxcdrhold = _create_property('rxcdrhold') + + +def main(args): + offset = get_ip_offset(0x204_0000, args.dcmac) + obj = AxiGTController(args.dev, offset, gpio_index=0) + + if args.reset: + print('Resetting GT') + obj.gt_reset = 1 + time.sleep(0.1) + obj.gt_reset = 0 + return + + if args.loopback is not None: + obj.loopback = args.loopback + time.sleep(0.1) + print(f'Loopback mode set to: {obj.loopback}') + return + + if args.linerate: + obj.gt_line_rate = args.linerate + time.sleep(0.1) + print(f'Line rate mode set to: {obj.gt_line_rate}') + return + + print(f'{obj.gt_reset=}') + print(f'{obj.gt_line_rate=}') + print(f'{obj.loopback=}') + print(f'{obj.txprecursor=}') + print(f'{obj.txpostcursor=}') + print(f'{obj.txmaincursor=}') + print(f'{obj.rxcdrhold=}') + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-l', '--loopback', type=hex_or_int, help="Loopback " + f" mode, a {shift_map['loopback']['bits']}-bit value", + default=None) + parser.add_argument('-r', '--reset', action='store_true', + help='Reset GT') + parser.add_argument('-s', '--linerate', help="Line-rate mode a " + f"{shift_map['gt_line_rate']['bits']}-bit value", + type=hex_or_int) + parser = add_common_args(parser) + + main(parser.parse_args()) diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/axigpio_mmio.py b/submodules/v80-vitis-flow/resources/dcmac/driver/axigpio_mmio.py new file mode 100644 index 00000000..80eeae77 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/axigpio_mmio.py @@ -0,0 +1,96 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + + +import argparse +from generic_mmio import GenericMMIO, int_types +from utils import add_common_args, get_ip_offset + + +key_map_offset = { + 'gpio_tri': 0x4, + 'gpio2_tri': 0xc, + 'gier': 0x11C, + 'ip_ier': 0x128, + 'ip_isr': 0x120, +} + + +class AxiGpioMMIO(GenericMMIO): + """Driver to work with AXI GPIO""" + + _data_off = 0 + _tri_off = 4 + + def write(self, gpio: int = 0, value: int = 0): + """Write to """ + offset = self._data_off + 0x8 * gpio + super().write(offset, value) + + def read(self, gpio: int = 0): + offset = self._data_off + 0x8 * gpio + return super().read(offset) + + def _get(self, key: str): + offset = key_map_offset[key] + return super().read(offset) + + def _set(self, key: str, val: int): + if not isinstance(val, int_types): + raise ValueError(f"'{val=}' is not a '{int_types}' type") + offset = key_map_offset[key] + super().write(offset, val) + + def _create_property(key: str): + """Create property getter and setter for given key.""" + return property( + lambda self: self._get(key), + lambda self, val: self._set(key, val) + ) + + gpio_tri = _create_property('gpio_tri') + gpio2_tri = _create_property('gpio2_tri') + gier = _create_property('gier') + ip_ier = _create_property('ip_ier') + ip_isr = _create_property('ip_isr') + + +def main(args): + value = 0 + if args.reset: + value = (2**32) - 1 + + offset0 = get_ip_offset(0x204_0000, args.dcmac) + obj = AxiGpioMMIO(args.dev, offset0) + obj.write(0, value) + print(f'GPIO1: 0x{obj.base_address:X}, value={obj.read(0)}') + obj.write(1, value) + print(f'GPIO2: 0x{obj.base_address:X}, value={obj.read(1)}') + del obj + + offset1 = get_ip_offset(0x204_0100, args.dcmac) + obj = AxiGpioMMIO(args.dev, offset1) + obj.write(0, value) + print(f'GPIO1: 0x{obj.base_address:X}, value={obj.read(0)}') + obj.write(1, value) + print(f'GPIO2: 0x{obj.base_address:X}, value={obj.read(1)}') + del obj + + offset2 = get_ip_offset(0x204_0300, args.dcmac) + obj = AxiGpioMMIO(args.dev, offset2) + obj.write(0, value) + print(f'GPIO1: 0x{obj.base_address:X}, value={obj.read(0)}') + obj.write(1, value) + print(f'GPIO2: 0x{obj.base_address:X}, value={obj.read(1)}') + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-r', '--reset', action='store_true', + help='Reset Logic') + parser = add_common_args(parser) + + args = parser.parse_args() + + main(args) diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/dcmac_init.py b/submodules/v80-vitis-flow/resources/dcmac/driver/dcmac_init.py new file mode 100644 index 00000000..212ef9f9 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/dcmac_init.py @@ -0,0 +1,164 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +import time +from axi_gt_controller import AxiGTController +from dcmac_mmio import DCMAC +from generic_mmio import hex_or_int +from gpio_monitor import AxiGPIOMonitor +from axigpio_mmio import AxiGpioMMIO +from utils import add_common_args, get_ip_offset + +def dcmac_reset_procedure(reset_tx: bool = True, dcmac_idx: int = 0): + """Reset DCMAC and GTs""" + global intf_id, dcmac, gt_gpio, monitor, gtdatapath + print(f'Working with {dcmac_idx=}') + # 1: reset GTs + if reset_tx: + print(" Resetting Tx GTs ", end= "", flush=True) + gt_gpio.gt_reset = 1 + time.sleep(0.001) + gt_gpio.gt_reset = 0 + else: + print(" Resetting only GTs RX datapath ", end= "", flush=True) + gtdatapath.write(0x0, 0xF) + time.sleep(0.01) + gtdatapath.write(0x0, 0x0) + + # 2: Wait for GT reset to finish + for _ in range(20): + signed_to_check = [f'gt{intf_id}_tx_reset_done',f'gt{intf_id}_rx_reset_done'] + ready = True + for signal in signed_to_check: + ready &= getattr(monitor, signal) == 0xF + if ready: + print(f"Done -> ", end= "", flush=True) + break + print(".", end= "", flush=True) + time.sleep(0.1) + else: + print(f"GTs not comming out of reset after 2 sec. Exiting...") + print(f" Debug info: {monitor.gt0_tx_reset_done=}, {monitor.gt1_tx_reset_done=}") + print(f" {monitor.gtpowergood=}") + time.sleep(0.1) + # time.sleep(0.5) + + # 3: reset DCMAC Tx + tx_rst_success = None + if reset_tx: + print("Resetting DCMAC Tx -> ", end= "", flush=True) + # status will be cleared after Rx reset, if successful + tx_rst_success = dcmac.reset_tx(clear_status_history= False) + + # 4: reset DCMAC Rx + print("Resetting DCMAC Rx ", end= "", flush=True) + rx_rst_success = dcmac.reset_rx(clear_status_history= True) + return tx_rst_success, rx_rst_success + +def dcmac_logic_init(args): + global intf_id, dcmac, gt_gpio, monitor, gtdatapath + + intf_id = 0 # TODO: in the future, we'll have 2 interfaces per DCMAC + dcmac = DCMAC(args.dev, get_ip_offset(0x200_0000, args.dcmac)) + gt_gpio = AxiGTController(args.dev, get_ip_offset(0x204_0000, args.dcmac), + gpio_index=0) + monitor = AxiGPIOMonitor(args.dev, get_ip_offset(0x204_0200, args.dcmac), gpio_index=0) + gtdatapath = AxiGpioMMIO(args.dev, get_ip_offset(0x204_0400, args.dcmac)) + + # Set GT Tx analog front-end swing and pre/post-emphasis: + # TODO: Fine-tune the following configuration. In general, this achieves alignment, + # 24 dB SNR and seems to stay aligned for a couple of days + # These values are now set by default in the GPIO + #gt_gpio.txprecursor = 6 + #gt_gpio.txmaincursor = 52 + #gt_gpio.txpostcursor = 6 + + if args.verbose > 0: + print(f'{dcmac._base_offset=:#x}') + print(f'{gt_gpio._base_offset=:#x}') + print(f'{monitor._base_offset=:#x}') + print(f'{gtdatapath._base_offset=:#x}') + print(f'{monitor.dual_dcmac=}') + print(f'{gt_gpio.txprecursor=}') + print(f'{gt_gpio.txmaincursor=}') + print(f'{gt_gpio.txpostcursor=}') + + if args.loopback is not None: + if args.loopback != args.loopback: + gt_gpio.loopback = args.loopback + time.sleep(0.1) + print(f'Loopback mode set to: {gt_gpio.loopback}') + args.init = True + + if args.keep_alive: + print('Keep ALIVE path') + iters = 0 + init_time = time.time() + prev_link_up = dcmac.link_up + while True: + iters += 1 + if dcmac.link_up: + if iters % 100 == 0: + print(f"\rDCMAC {args.dcmac} link still up after {time.time() - init_time:.1f} s", end="", flush=True) + else: + if prev_link_up: + print(f" | Link Down |") + dcmac_reset_procedure(not dcmac.tx_aligned, args.dcmac) + if dcmac.link_up: + print(" | Link up again") + init_time = time.time() + prev_link_up = dcmac.link_up + time.sleep(0.05) + + # TODO, we need an independent reset TX code + if args.init or args.align_rx: + print(f'INIT or ALIGN RX. {args.init=} {args.align_rx=}') + if args.verbose > 1: + dcmac.print_config(False) + print(f"{gt_gpio.loopback=}") + print(f"{gt_gpio.txprecursor=}") + print(f"{gt_gpio.txmaincursor=}") + print(f"{gt_gpio.txpostcursor=}") + print('\nResetting GT -> DCMAC Tx -> DCMAC Rx') + + NUM_OF_RETRIES = 10 + reset_tx = args.init + # Iterate through reset routine until MAC is ready or we run out of retries + for retry_id in range(NUM_OF_RETRIES): + tx_rst_success, rx_rst_success = dcmac_reset_procedure(reset_tx, args.dcmac) + tx_rst_success = tx_rst_success if reset_tx else True + reset_tx = tx_rst_success + if tx_rst_success and rx_rst_success: + print(f"DCMAC initialization successful after {retry_id} retries") + break + else: + print(f"DCMAC initialization failed after {NUM_OF_RETRIES} retries. DCMAC state:") + dcmac.print_status(only_modified_fields=True) + print(f"Exiting...") + exit(1) + + if args.verbose > 0: + dcmac.print_status(only_modified_fields=args.verbose < 2) + + dcmac.tx_stats(0, True, verbose=args.verbose) + dcmac.rx_stats(0, True, verbose=args.verbose) + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-i', '--init', action='store_true', + help='Initialize system') + parser.add_argument('-a', '--align_rx', action='store_true',help='Align RX') + parser.add_argument('-k', '--keep_alive', action='store_true',help='Keep link alive') + parser.add_argument('-l', '--loopback', type=hex_or_int, + help="Set GT Loopback", default=None) + parser.add_argument('-t', '--traffic_test', action='store_true', + help='Run traffic test') + # default only status + parser.add_argument('-p', '--print', action='store_true', + help='Print stats') + parser = add_common_args(parser, verbose=True) + + args = parser.parse_args() + dcmac_logic_init(args) diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/dcmac_mmio.py b/submodules/v80-vitis-flow/resources/dcmac/driver/dcmac_mmio.py new file mode 100644 index 00000000..f6245438 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/dcmac_mmio.py @@ -0,0 +1,437 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +import pprint +import time +from tabulate import tabulate +from generic_mmio import GenericMMIO +from dcmac_reg import registers, tx_stats_base_reg, rx_stats_base_reg +from utils import rshift, add_common_args, get_ip_offset + +class DCMAC(GenericMMIO): + """"DCMAC MMIO Driver""" + + def __init__(self, device: str = 'e2', base_offset: int = 0x0): + super().__init__(device, base_offset) + self.set_pm_tick_trigger() + + def write(self, offset, value): + if isinstance(offset, str): + offset = registers[offset]['offset'] + super().write(offset, value) + + def read(self, offset): + if isinstance(offset, str): + offset = registers[offset]['offset'] + return super().read(offset) + + #TODO: __getattr__ and __setattr__ need more validation + def __getattr__(self, name): + """Get the value of a register""" + if name in registers: + val = self.read(name) + if registers[name].get('fields'): + field_dict = dict() + for k, v in registers[name]['fields'].items(): + field_dict[k] = rshift(val, v['start'], v['length']) + return field_dict + else: + return val + else: + raise AttributeError(f"'{self.__class__.__name__}' object has " + f"no attribute '{name}'") + + #TODO: validate + def __setattr__(self, name, value): + """Set the value of a register""" + if name in registers: + # TODO: accept value as a dictionary to set individual fields + if isinstance(value, dict): + values_dict = value + value = self.read(name) + reg_fields = registers[name].get('fields', {}) + for field_name, field_value in values_dict.items(): + if field_name in reg_fields: + field = registers[name]['fields'][field_name] + start, length = field['start'], field['length'] + mask = ((1 << length) - 1) << start + value &= ~ mask # clear the bits + value |= (field_value << start) & mask # set the bits + else: + raise ValueError(f"Field '{field_name}' not found " + f"in register '{name}'") + + self.write(name, value) + else: + super().__setattr__(name, value) + + # TODO: implement functions to read and write channel registers without + # having to specify the channel offset, just the channel number + # def read_chn_reg(self, chn_reg_name, channel): + # offset = registers['C0_' + chn_reg_name]['offset'] + # return self._pciemmio.read(self._offset + offset) + + def read_reg_field(self, reg_name: str, field: str): + """Read a field from reg'""" + field = registers[reg_name]['fields'][field] + val = self.read(reg_name) + return rshift(val, field['start'], field['length']) + + def read_long(self, offset) -> int: + """Read 8 bytes from BAR 'offset'""" + if isinstance(offset, str): + offset = registers[offset]['offset'] + val_low = self.read(offset) + val_high = self.read(offset + 4) + return int((val_high << 32) + val_low) + + @property + def revision(self): + return self.read('CONFIGURATION_REVISION') + + @property + def ip_dict(self): + vals = {} + for k, v in registers.items(): + readval = self.read(v['offset']) + vals[k] = {'value': readval} + if v.get('fields'): + vals[k]['fields'] = {} + for k1, v1 in v['fields'].items(): + vals[k]['fields'][k1] = rshift(readval, v1['start'], v1['length']) + + return vals + + @property + def status(self): + status_dict = {} + for reg_name, spec in registers.items(): + if "STATUS" in reg_name: + fields = spec.get('fields', False) + readval = self.read(reg_name) + subkey = "real-time" if "_RT_" in reg_name else "latched" + entry_name = reg_name if "_RT_" not in reg_name else reg_name.replace("_RT", "") + if entry_name not in status_dict: + if fields: + status_dict[entry_name] = {} + for f in fields: + + status_dict[entry_name][f] = {"latched": "-", "real-time": "-", "default": fields[f]['default']} + else: + status_dict[entry_name] = {"latched": "-", "real-time": "-", "default": "-"} + + if fields: + for f_name, f_spec in fields.items(): + status_dict[entry_name][f_name][subkey] = rshift(readval, f_spec['start'], f_spec['length']) + else: + status_dict[entry_name][subkey] = readval + return status_dict + + def print_status(self, only_modified_fields: bool = False): + status_dict = self.status + table = [] + table += [["Register", "Field", "Latched", "Real-Time", "Default"]] + for reg_name, fields in status_dict.items(): + row_count = 0 + for field_name, field in fields.items(): + default_val = field["default"] + if only_modified_fields: + if field["latched"] == default_val and field["real-time"] == default_val: + continue + table += [[reg_name if row_count == 0 else "", field_name, field["latched"], field["real-time"], default_val]] + row_count += 1 + if row_count > 0: + table += [["--------------------", "--------------------", "--------", "--------", "--------"]] + if only_modified_fields: + if len(table) == 1: + print("All status Registers have default values") + return + print("Status Registers with non-default values") + else: + print("Status Registers") + print(tabulate(table, headers="firstrow", tablefmt="pretty")) + + @property + def config(self): + config_dict = {} + config_regs = ['GLOBAL_MODE', 'C0_TX_MODE_REG', 'C0_RX_MODE_REG'] + for reg_name in config_regs: + spec = registers[reg_name] + fields = spec.get('fields', False) + readval = self.read(spec['offset']) + config_dict[reg_name] = {} + for f_name, f_spec in fields.items(): + val = rshift(readval, f_spec['start'], f_spec['length']) + config_dict[reg_name][f_name] = {"value": val, "default": fields[f_name]['default']} + + return config_dict + + def print_config(self, only_modified_fields: bool = False): + config_dict = self.config + table = [] + table += [["Register", "Field", "Value", "Default"]] + for reg_name, fields in config_dict.items(): + row_count = 0 + for field_name, field in fields.items(): + default_val = field["default"] + if only_modified_fields: + if field["value"] == default_val: + continue + table += [[reg_name if row_count == 0 else "", field_name, field["value"], default_val]] + row_count += 1 + if row_count > 0: + table += [["--------------------", "--------------------", "--------", "--------", "--------"]] + if only_modified_fields: + print("Configuration Registers with non-default values") + else: + print("Configuration Registers") + print(tabulate(table, headers="firstrow", tablefmt="pretty")) + + def tx_stats(self, port: int = 0, debug: bool = False, + verbose: int = 0): + """Reads and print TX stats for the given port""" + + if isinstance(port, int) and not 0 <= port < 1: + raise ValueError("'port' must be either 0 or 1") + + baseoffset = 0x1000 * (port + 1) + 0x0200 + + # Sets pm tick to be triggered by registers + value = self.read(baseoffset - 0x200 + 0x40) + pm_tick_bit = registers['C0_TX_MODE_REG']['fields']['c0_ctl_tx_tick_reg_mode_sel']['start'] + value |= (1 * (2**pm_tick_bit)) + self.write(baseoffset - 0x200 + 0x40, value) + + # trigger ALL_CHANNEL_MAC_TICK_REG_TX + #offset = registers['ALL_CHANNEL_MAC_TICK_REG_TX']['offset'] + #self.write(offset, 0) + #self.write(offset, 1) + #self.write(offset, 0) + + # trigger pm tick + self.write(baseoffset - 0x200 + 0xFC, 0) + self.write(baseoffset - 0x200 + 0xFC, 1) + + for i in range(10): + val = self.read(baseoffset - 0x200 + 0x808) + if val != 0: + break + + heading = [[f"TX Stats {port=}", "Value"]] + if debug: + heading[0].append('Offset Address') + table = self._stats(baseoffset, 'tx', heading, debug, verbose) + print(tabulate(table, headers="firstrow", tablefmt="pretty")) + + def rx_stats(self, port: int = 0, debug: bool = False, + verbose: int = 0): + """Reads and print RX stats for the given port""" + + if isinstance(port, int) and not 0 <= port < 1: + raise ValueError("'port' must be either 0 or 1") + + baseoffset = 0x1000 * (port + 1) + 0x0400 + + # Sets pm tick to be triggered by registers + value = self.read(baseoffset - 0x400 + 0x44) + pm_tick_bit = registers['C0_RX_MODE_REG']['fields']['c0_ctl_rx_tick_reg_mode_sel']['start'] + value |= (1 * (2**pm_tick_bit)) + self.write(baseoffset - 0x400 + 0x44, value) + + # trigger ALL_CHANNEL_MAC_TICK_REG_RX + #offset = registers['ALL_CHANNEL_MAC_TICK_REG_RX']['offset'] + #self.write(offset, 0) + #self.write(offset, 1) + #self.write(offset, 0) + + # trigger pm tick + self.write(baseoffset - 0x400 + 0xF4, 0) + self.write(baseoffset - 0x400 + 0xF4, 1) + + for i in range(10): + val = self.read(baseoffset - 0x400 + 0xC08) + if val != 0: + break + + heading = [[f"RX Stats {port=}", "Value"]] + if debug: + heading[0].append('Offset Address') + table = self._stats(baseoffset, 'rx', heading, debug, verbose) + print(tabulate(table, headers="firstrow", tablefmt="pretty")) + + def _stats(self, baseoffset: int, dir: str, tableheading: str, + debug: bool, verbose: int = 0): + + table = tableheading + stats_base_reg = tx_stats_base_reg if dir == 'tx' else rx_stats_base_reg + for k, v in stats_base_reg.items(): + if 'LSB' in k: + readval = self.read_long(baseoffset + v['offset']) + elif 'MSB' in k: + continue + else: + readval = self.read(baseoffset + v['offset']) + + if readval == 0 and verbose < 1: + continue + key = k.replace('_LSB', '') + ltable = [key, readval] + if debug: + ltable.append(f"0x{(baseoffset + v['offset']):X}") + table.append(ltable) + + return table + + def clear_latched_flags(self): + MASK = (1 << 32) - 1 + for reg_name, spec in registers.items(): + if "STATUS" in reg_name: + self.write(spec['offset'], MASK) + + def set_pm_tick_trigger(self) -> int: + """Sets pm tick to be triggered by registers""" + value = self.read(registers['GLOBAL_MODE']['offset']) + tx_reg_bit = registers['GLOBAL_MODE']['fields']['ctl_tx_all_ch_tick_reg_mode_sel']['start'] + rx_reg_bit = registers['GLOBAL_MODE']['fields']['ctl_rx_all_ch_tick_reg_mode_sel']['start'] + + val_tx = 1 * (2**tx_reg_bit) + val_rx = 1 * (2**rx_reg_bit) + val_tx += val_rx + + value |= val_tx + self.write(registers['GLOBAL_MODE']['offset'], value) + return self.read(registers['GLOBAL_MODE']['offset']) + + def reset_tx(self, clear_status_history: bool = True): + """Forces a resets on the transmitting DCMAC core + It Follows the reset procedure outlined in the DCMAC user guide pg369, + page 161 ("Transmit Fixed Ethernet Startup Procedure when Using tx_core_reset") + """ + rst_successful = True + offset = lambda x: registers[x]['offset'] + rst_core_regs = [offset('GLOBAL_CONTROL_REG_TX')] + rst_serdes_regs = [offset('C0_PORT_CONTROL_REG_TX') + 0x1000 * i for i in range(6)] + rst_flush_regs = [offset('C0_CHANNEL_CONTROL_REG_TX') + 0x1000 * i for i in range(6)] + for reg in rst_core_regs + rst_serdes_regs + rst_flush_regs: + self.write(reg, 2**32-1) + time.sleep(0.1) + # first release port RSTs, then core reset + for reg in rst_serdes_regs + rst_core_regs: + self.write(reg, 0x0) + + # wait for tx_local_fault + for _ in range(10): + if self.tx_aligned: + # print('TX status: OK') + break + time.sleep(0.2) + else: + print('TX status: local fault') + rst_successful = False + + # release flush + for reg in rst_flush_regs: + self.write(reg, 0x0) + + if clear_status_history: + self.clear_latched_flags() + return rst_successful + + def reset_rx(self, clear_status_history: bool = True): + """Forces a resets on the receiving DCMAC core + It Follows the reset procedure outlined in the DCMAC user guide pg369, + page 162 ("Receive Fixed Ethernet Startup Procedure when Using rx_core_reset") + """ + ACTIVE_PORTS = 6 # TODO: this should be set by the user + offset = lambda x: registers[x]['offset'] + rst_core_regs = [(offset('GLOBAL_CONTROL_REG_RX'), 7)] + rst_serdes_regs = [(offset('C0_PORT_CONTROL_REG_RX') + 0x1000 * i, 2) for i in range(6)] + rst_flush_regs = [(offset('C0_CHANNEL_CONTROL_REG_RX') + 0x1000 * i, 1) for i in range(6)] + for reg,reset_code in rst_core_regs + rst_serdes_regs + rst_flush_regs: + self.write(reg, reset_code) + + time.sleep(0.5) + # first release core resets, then flush and finally serdes resets + for reg,_ in rst_core_regs + rst_flush_regs[:ACTIVE_PORTS] + rst_serdes_regs[:ACTIVE_PORTS]: + self.write(reg, 0) + + # check Rx alignment + rst_successful = True + for i in range(10): + if self.rx_aligned: + break + print(".", end= "", flush=True) + time.sleep(0.25) + else: + print('WARN: Chn 0 RX failed to achieve alignment') + rst_successful = False + + if clear_status_history: + self.clear_latched_flags() + return rst_successful + + @property + def tx_aligned(self): + # TODO: this should take the channel number as an argument and + # return the corresponding channel status + return self.C0_STAT_CHAN_TX_MAC_RT_STATUS_REG['c0_stat_tx_local_fault'] == 0 + + @property + def rx_aligned(self): + # TODO: this should take the channel number as an argument and + # return the corresponding channel status + chn_status_dict = self.C0_STAT_PORT_RX_PHY_RT_STATUS_REG + return chn_status_dict['c0_stat_rx_status'] == 1 and \ + chn_status_dict['c0_stat_rx_aligned'] == 1 + + @property + def link_up(self): + return self.rx_aligned and self.tx_aligned + +def main(args): + offset = get_ip_offset(0x200_0000, args.dcmac) + obj = DCMAC(args.dev, offset) + + if args.tx: + obj.reset_tx() + + if args.rx: + obj.reset_rx() + + if args.rx or args.tx or args.clear: + time.sleep(0.5) + obj.clear_latched_flags() + + if args.status or not (args.rx or args.tx or args.print or args.show_config): + obj.print_status(only_modified_fields=args.verbose < 1) + + if args.show_config: + obj.print_config(only_modified_fields=args.verbose < 1) + + if args.print: + # pprint.pp(obj.ip_dict) + obj.tx_stats(0, True, verbose=args.verbose) + obj.rx_stats(0, True, verbose=args.verbose) + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-r', '--rx', action='store_true', + help='Reset RX') + parser.add_argument('-t', '--tx', action='store_true', + help='Reset TX') + parser.add_argument('-s', '--status', action='store_true', + help='Print status') + # default only status + parser.add_argument('-p', '--print', action='store_true', + help='Print stats') + parser.add_argument('-c', '--clear', action='store_true', + help='Clear latched flags') + parser.add_argument('-C', '--show-config', action='store_true', + help='Show configuration') + parser = add_common_args(parser, verbose=True) + + args = parser.parse_args() + main(args) \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/dcmac_reg.py b/submodules/v80-vitis-flow/resources/dcmac/driver/dcmac_reg.py new file mode 100644 index 00000000..cdcb2bb0 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/dcmac_reg.py @@ -0,0 +1,623 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +registers = { + 'CONFIGURATION_REVISION': {'offset': 0x0, 'type': 'ro'}, + 'GLOBAL_MODE': { + 'offset': 0x4, 'type': 'rw', + 'fields': { + 'ctl_tx_independent_tsmac_and_phy_mode': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_tx_all_ch_tick_reg_mode_sel': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_rx_independent_tsmac_and_phy_mode': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_rx_all_ch_tick_reg_mode_sel': {'start': 5, 'length': 1, 'default': '0', 'type': 'rw'}, + 'ctl_tx_axis_cfg': {'start': 8, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_rx_axis_cfg': {'start': 12, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_tx_pcs_active_ports': {'start': 16, 'length': 3, 'default': 5, 'type': 'rw'}, + 'ctl_rx_pcs_active_ports': {'start': 20, 'length': 3, 'default': 5, 'type': 'rw'}, + 'ctl_rx_fec_errind_mode': {'start': 24, 'length': 1, 'default': 1, 'type': 'rw'}, + 'ctl_tx_fec_ck_unique_flip': {'start': 25, 'length': 1, 'default': 1, 'type': 'rw'}, + 'ctl_rx_fec_ck_unique_flip': {'start': 26, 'length': 1, 'default': 1, 'type': 'rw'} + } + }, + 'TEST_DEBUG': { + 'offset': 0x8, 'type': 'rw', + 'fields': { + 'ctl_test_mode_pin_char': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_test_mode_memcel': {'start': 4, 'length': 4, 'default': 0, 'type': 'rw'}, + 'ctl_rx_phy_debug_select': {'start': 8, 'length': 5, 'default': 0, 'type': 'rw'}, + 'ctl_rx_mac_debug_select': {'start': 13, 'length': 4, 'default': 0, 'type': 'rw'}, + 'ctl_tx_phy_debug_select': {'start': 17, 'length': 4, 'default': 0, 'type': 'rw'}, + 'ctl_tx_mac_debug_select': {'start': 21, 'length': 4, 'default': 0, 'type': 'rw'}, + 'ctl_rx_ecc_err_clear': {'start': 25, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_tx_ecc_err_clear': {'start': 26, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_tx_ecc_err_count_tick': {'start': 27, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_axi_af_thresh_override': {'start': 28, 'length': 4, 'default': 8, 'type': 'rw'} + } + }, + 'EMA_CONFIGURATION': { + 'offset': 0xC, 'type': 'rw', + 'fields': { + 'ctl_mem_ctrl': {'start': 0, 'length': 10, 'default': 0x11b, 'type': 'rw'}, + 'emaa': {'start': 0, 'length': 3, 'default': 0x3, 'type': 'rw'}, + 'emab': {'start': 3, 'length': 3, 'default': 0x3, 'type': 'rw'}, + 'emasa': {'start': 6, 'length': 1, 'default': 0x0, 'type': 'rw'}, + 'stov': {'start': 7, 'length': 1, 'default': 0x0, 'type': 'rw'}, + 'mc_mem_ctrl_enable': {'start': 8, 'length': 1, 'default': 0x1, 'type': 'rw'} + } + }, + 'CLOCK_DISABLE': { + 'offset': 0x10, 'type': 'rw', + 'fields': { + 'ctl_mem_disable_rx_axi_clk': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_axi_clk': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_macif_clk': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_macif_clk': {'start': 3, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_core_clk': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_core_clk': {'start': 5, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_flexif_clk': {'start': 6, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_flexif_clk': {'start': 12, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_serdes_clk': {'start': 18, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_serdes_clk': {'start': 24, 'length': 6, 'default': 0, 'type': 'rw'} + } + }, + 'BLOCK_DISABLE': { + 'offset': 0x14, 'type': 'rw', + 'fields': { + 'ctl_mem_disable_rx_pcs_cpcs': {'start': 0, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_pcs_align_buffer': {'start': 6, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_pcs_decoder': {'start': 12, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_pcs_cpcs': {'start': 16, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_ts2phy': {'start': 22, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_pcs_encoder': {'start': 23, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY0': { + 'offset': 0x18, 'type': 'rw', + 'fields': { + 'ctl_rsvd0': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY1': { + 'offset': 0x1C, 'type': 'rw', + 'fields': { + 'ctl_rsvd1': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY2': { + 'offset': 0x20, 'type': 'rw', + 'fields': { + 'ctl_rsvd2': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY3': { + 'offset': 0x24, 'type': 'rw', + 'fields': { + 'ctl_rsvd3': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY4': { + 'offset': 0x28, 'type': 'rw', + 'fields': { + 'ctl_rsvd4': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY5': { + 'offset': 0x2C, 'type': 'rw', + 'fields': { + 'ctl_rsvd5': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY6': { + 'offset': 0x30, 'type': 'rw', + 'fields': { + 'ctl_rsvd6': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY7': { + 'offset': 0x34, 'type': 'rw', + 'fields': { + 'ctl_rsvd7': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'MAC_CONFIG_REG_TX_WR': { + 'offset': 0x38, 'type': 'rw', + 'fields': { + 'mac_tx_cfg_data': {'start': 0, 'length': 8, 'default': 0, 'type': 'rw'}, + 'mac_tx_cfg_index': {'start': 8, 'length': 5, 'default': 0, 'type': 'rw'}, + 'mac_tx_cfg_channel': {'start': 16, 'length': 6, 'default': 0, 'type': 'rw'}, + 'mac_tx_cfg_wr': {'start': 24, 'length': 1, 'default': 0, 'type': 'rw'}, + 'mac_tx_cfg_enable': {'start': 28, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'MAC_CONFIG_REG_TX_RD': { + 'offset': 0x3C, 'type': 'rw', + 'fields': { + 'mac_tx_cfg_data_rd': {'start': 0, 'length': 8, 'default': 0, 'type': 'rw'} + } + }, + 'GLOBAL_CONTROL_REG_RX': { + 'offset': 0xF0, 'type': 'rw', + 'fields': { + 'soft_rx_core_reset': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'soft_rx_macif_reset': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'}, + 'soft_rx_axi_reset': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + }, + }, + 'ALL_CHANNEL_MAC_TICK_REG_RX': { + 'offset': 0xF4, 'type': 'rw', + 'fields': { + 'rx_all_channel_mac_soft_pm_tick': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'} + }, + }, + 'GLOBAL_CONTROL_REG_TX': { + 'offset': 0xF8, 'type': 'rw', + 'fields': { + 'soft_tx_core_reset': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'soft_tx_macif_reset': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'}, + 'soft_tx_axi_reset': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'} + }, + }, + 'ALL_CHANNEL_MAC_TICK_REG_TX': { + 'offset': 0xFC, 'type': 'rw', + 'fields': { + 'rx_all_channel_mac_soft_pm_tick': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'} + }, + }, + 'STAT_TX_ECC_ERR_REG': { + 'offset': 0x1B0, 'type': 'ro', + 'fields': { + 'stat_tx_ecc0_err0': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc0_err1': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc1_err0': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc1_err1': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc2_err0': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc2_err1': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + }, + }, + 'C0_CHANNEL_CONFIGURATION_TX': { + 'offset': 0x1000, 'type': 'rw', + 'fields': { + 'c0_ctl_tx_fcs_ins_enable': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_ctl_tx_ignore_fcs': {'start': 1, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_ctl_tx_send_lfi': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_send_rfi': {'start': 3, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_send_idle': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_custom_preamble_enable': {'start': 5, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_ipg_value': {'start': 8, 'length': 4, 'default': 0xC, 'type': 'rw'}, + 'c0_ctl_tx_corrupt_fcs_on_err': {'start': 16, 'length': 2, 'default': 0, 'type': 'rw'}, + } + }, + 'C0_CHANNEL_CONFIGURATION_RX': { + 'offset': 0x1004, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_is_clause_49': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_delete_fcs': {'start': 1, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_ignore_fcs': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_process_lfi': {'start': 3, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_check_sfd': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_check_preamble': {'start': 5, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_ignore_inrange': {'start': 6, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_max_packet_len': {'start': 16, 'length': 14, 'default': 0x2580, 'type': 'rw'}, + } + }, + 'C0_CHANNEL_CONTROL_REG_RX': { + 'offset': 0x1030, 'type': 'rw', + 'fields': { + 'c0_soft_rx_mac_channel_flush': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_CHANNEL_CONTROL_REG_TX': { + 'offset': 0x1038, 'type': 'rw', + 'fields': { + 'c0_soft_tx_mac_channel_flush': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_TX_MODE_REG': { + 'offset': 0x1040, 'type': 'rw', + 'fields': { + 'c0_ctl_tx_data_rate': {'start': 0, 'length': 2, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_use_custom_vl_length_minus1': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_use_custom_vl_marker_ids': {'start': 3, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_tick_reg_mode_sel': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_flexif_select': {'start': 5, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_tx_flexif_am_mode': {'start': 7, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_flexif_pcs_wide_mode': {'start': 8, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_pma_lane_mux': {'start': 9, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_tx_alt_serdes_clk_mux_disable': {'start': 11, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_fec_mode': {'start': 16, 'length': 5, 'default': 4, 'type': 'rw'}, + 'c0_ctl_tx_fec_transcode_bypass': {'start': 21, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_fec_four_lane_pmd': {'start': 22, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_RX_MODE_REG': { + 'offset': 0x1044, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_data_rate': {'start': 0, 'length': 2, 'default': 0, 'type': 'rw'}, + 'c0_ctl_pcs_rx_ts_en': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_test_pattern': {'start': 8, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_use_custom_vl_length_minus1': {'start': 9, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_use_custom_vl_marker_ids': {'start': 10, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_tick_reg_mode_sel': {'start': 11, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_pma_lane_mux': {'start': 12, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_fec_mode': {'start': 16, 'length': 4, 'default': 4, 'type': 'rw'}, + 'c0_ctl_rx_fec_bypass_indication': {'start': 21, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_bypass_correction': {'start': 22, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_transcode_clause49': {'start': 23, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_alignment_bypass': {'start': 24, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_transcode_bypass': {'start': 25, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_degrade_enable': {'start': 26, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_ext_align_buff_enable': {'start': 27, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_RX_FEC_SLICE_CONFIGURATION1': { + 'offset': 0x1048, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_degrade_interval': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'C0_RX_FEC_SLICE_CONFIGURATION2': { + 'offset': 0x104C, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_degrade_act_thresh': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'C0_RX_FEC_SLICE_CONFIGURATION3': { + 'offset': 0x1050, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_degrade_deact_thresh': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'C0_CONFIGURATION_RX': { + 'offset': 0x10A0, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_flexif_select': {'start': 0, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_flexif_pcs_wide_mode': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_PORT_CONTROL_REG_RX': { + 'offset': 0x10F0, 'type': 'rw', + 'fields': { + 'c0_soft_rx_flexif_reset': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_soft_rx_serdes_reset': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_PORT_TICK_REG_RX': { + 'offset': 0x10F4, 'type': 'rw', + 'fields': { + 'c0_rx_port_soft_pm_tick': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'} + } + }, + 'C0_PORT_CONTROL_REG_TX': { + 'offset': 0x10F8, 'type': 'rw', + 'fields': { + 'c0_soft_tx_flexif_reset': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_soft_tx_serdes_reset': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_PORT_TICK_REG_TX': { + 'offset': 0x10FC, 'type': 'rw', + 'fields': { + 'c0_tx_port_soft_pm_tick': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'} + } + }, + 'C0_STAT_CHAN_TX_MAC_STATUS_REG': { + 'offset': 0x1100, 'type': 'ro', + 'fields': { + 'c0_stat_tx_local_fault': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_tsmac_ovf': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_tsmac_unf': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_packet_small': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_sic_overflow': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_CHAN_TX_MAC_RT_STATUS_REG': { + 'offset': 0x1104, 'type': 'ro', + 'fields': { + 'c0_stat_tx_local_fault': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_tsmac_ovf': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_tsmac_unf': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_packet_small': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_sic_overflow': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_CHAN_TX_STATISTICS_READY': { + 'offset': 0x1108, 'type': 'ro', + 'fields': { + 'c0_stat_tx_channel_mac_statistics_ready': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'} + } + }, + 'C0_STAT_CHAN_RX_MAC_STATUS_REG': { + 'offset': 0x1140, 'type': 'ro', + 'fields': { + 'c0_stat_rx_remote_fault': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_local_fault': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_internal_local_fault': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_received_local_fault': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_preamble': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_sfd': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_got_signal_os': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_invalid_start': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_code': {'start': 8, 'length': 1, 'default': 0, 'type': 'ro'}, + } + }, + 'C0_STAT_CHAN_RX_MAC_RT_STATUS_REG': { + 'offset': 0x1144, 'type': 'ro', + 'fields': { + 'c0_stat_rx_remote_fault': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_local_fault': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_internal_local_fault': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_received_local_fault': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_preamble': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_sfd': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_got_signal_os': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_invalid_start': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_code': {'start': 8, 'length': 1, 'default': 0, 'type': 'ro'}, + } + }, + 'C0_STAT_CHAN_RX_STATISTICS_READY': { + 'offset': 0x1148, 'type': 'ro', + 'fields': { + 'c0_stat_tx_channel_mac_statistics_ready': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'} + } + }, + + 'C0_STAT_PORT_TX_MAC_STATUS_REG': { + 'offset': 0x1180, 'type': 'ro', + 'fields': { + 'c0_stat_tx_axis_unf': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_axis_err': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_MAC_RT_STATUS_REG': { + 'offset': 0x1184, 'type': 'ro', + 'fields': { + 'c0_stat_tx_axis_unf': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_axis_err': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_RX_MAC_STATUS_REG': { + 'offset': 0x11C0, 'type': 'ro', + 'fields': { + 'c0_stat_rx_axis_fifo_overflow': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_axis_err': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_phy2ts_buf_err': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_macif_fifo_ovf': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_RX_MAC_RT_STATUS_REG': { + 'offset': 0x11C4, 'type': 'ro', + 'fields': { + 'c0_stat_rx_axis_fifo_overflow': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_axis_err': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_phy2ts_buf_err': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_macif_fifo_ovf': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_PHY_STATUS_REG': { + 'offset': 0x1800, 'type': 'ro', + 'fields': { + 'c0_stat_tx_pcs_bad_code': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_flex_fifo_err': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_flex_coa': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_PHY_RT_STATUS_REG': { + 'offset': 0x1804, 'type': 'ro', + 'fields': { + 'c0_stat_tx_pcs_bad_code': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_flex_fifo_err': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_flex_coa': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_STATISTICS_READY': { + 'offset': 0x1808, 'type': 'ro' + }, + 'C0_STAT_PORT_TX_FEC_STATUS_REG': { + 'offset': 0x180C, 'type': 'ro', + 'fields': { + 'c0_stat_tx_fec_pcs_lane_align': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_tx_fec_pcs_block_lock': {'start': 1, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_tx_fec_pcs_am_lock': {'start': 2, 'length': 1, 'default': 1, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_FEC_RT_STATUS_REG': { + 'offset': 0x1810, 'type': 'ro', + 'fields': { + 'c0_stat_tx_fec_pcs_lane_align': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_tx_fec_pcs_block_lock': {'start': 1, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_tx_fec_pcs_am_lock': {'start': 2, 'length': 1, 'default': 1, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_RX_PHY_STATUS_REG': { + 'offset': 0x1C00, 'type': 'ro', + 'fields': { + 'c0_stat_rx_status': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_block_lock': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_aligned': {'start': 2, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_misaligned': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_aligned_err': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_hi_ber': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_framing_err': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_pcs_bad_code': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_synced': {'start': 8, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_synced_err': {'start': 9, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bip_err': {'start': 10, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_flex_fifo_err': {'start': 11, 'length': 1, 'default': 0, 'type': 'ro'}, + } + }, + 'C0_STAT_PORT_RX_PHY_RT_STATUS_REG': { + 'offset': 0x1C04, 'type': 'ro', + 'fields': { + 'c0_stat_rx_status': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_block_lock': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_aligned': {'start': 2, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_misaligned': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_aligned_err': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_hi_ber': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_framing_err': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_pcs_bad_code': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_synced': {'start': 8, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_synced_err': {'start': 9, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bip_err': {'start': 10, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_flex_fifo_err': {'start': 11, 'length': 1, 'default': 0, 'type': 'ro'}, + } + }, + 'C0_STAT_PORT_RX_STATISTICS_READY': { + 'offset': 0x1C08, 'type': 'ro' + }, + 'C0_STAT_PORT_RX_BLOCK_LOCK_REG': { + 'offset': 0x1C0C, 'type': 'ro' + }, + 'C0_STAT_PORT_RX_LANE_SYNC_REG': { + 'offset': 0x1C10, 'type': 'ro' + }, + 'C0_STAT_PORT_RX_LANE_SYNC_ERR_REG': { + 'offset': 0x1C14, 'type': 'ro' + }, + + 'C0_STAT_PORT_RX_FEC_STATUS_REG': { + 'offset': 0x1C34, 'type': 'ro', + 'fields': { + 'c0_stat_rx_fec_aligned': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_fec_hi_ser': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_lane_lock': {'start': 2, 'length': 4, 'default': 15, 'type': 'ro'}, + 'c0_stat_rx_fec_degraded_ser': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_rm_degraded': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_RX_FEC_RT_STATUS_REG': { + 'offset': 0x1C38, 'type': 'ro', + 'fields': { + 'c0_stat_rx_fec_aligned': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_fec_hi_ser': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_lane_lock': {'start': 2, 'length': 4, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_degraded_ser': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_rm_degraded': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, +} + + +tx_stats_base_reg = { + 'TOTAL_BYTES_LSB': {'offset': 0x00, 'type': 'ro'}, + 'TOTAL_BYTES_MSB': {'offset': 0x04, 'type': 'ro'}, + 'TOTAL_GOOD_BYTES_LSB': {'offset': 0x08, 'type': 'ro'}, + 'TOTAL_GOOD_BYTES_MSB': {'offset': 0x0C, 'type': 'ro'}, + 'TOTAL_PACKETS_LSB': {'offset': 0x10, 'type': 'ro'}, + 'TOTAL_PACKETS_MSB': {'offset': 0x14, 'type': 'ro'}, + 'TOTAL_GOOD_PACKETS_LSB': {'offset': 0x18, 'type': 'ro'}, + 'TOTAL_GOOD_PACKETS_MSB': {'offset': 0x1C, 'type': 'ro'}, + 'FRAME_ERROR_LSB': {'offset': 0x20, 'type': 'ro'}, + 'FRAME_ERROR_MSB': {'offset': 0x24, 'type': 'ro'}, + 'BAD_FCS_LSB': {'offset': 0x28, 'type': 'ro'}, + 'BAD_FCS_MSB': {'offset': 0x2C, 'type': 'ro'}, + 'PACKET_64_BYTES_LSB': {'offset': 0x30, 'type': 'ro'}, + 'PACKET_64_BYTES_MSB': {'offset': 0x34, 'type': 'ro'}, + 'PACKET_65_127_BYTES_LSB': {'offset': 0x38, 'type': 'ro'}, + 'PACKET_65_127_BYTES_MSB': {'offset': 0x3C, 'type': 'ro'}, + 'PACKET_128_255_BYTES_LSB': {'offset': 0x40, 'type': 'ro'}, + 'PACKET_128_255_BYTES_MSB': {'offset': 0x44, 'type': 'ro'}, + 'PACKET_256_511_BYTES_LSB': {'offset': 0x48, 'type': 'ro'}, + 'PACKET_256_511_BYTES_MSB': {'offset': 0x4C, 'type': 'ro'}, + 'PACKET_512_1023_BYTES_LSB': {'offset': 0x50, 'type': 'ro'}, + 'PACKET_512_1023_BYTES_MSB': {'offset': 0x54, 'type': 'ro'}, + 'PACKET_1024_1518_BYTES_LSB': {'offset': 0x58, 'type': 'ro'}, + 'PACKET_1024_1518_BYTES_MSB': {'offset': 0x5C, 'type': 'ro'}, + 'PACKET_1519_1522_BYTES_LSB': {'offset': 0x60, 'type': 'ro'}, + 'PACKET_1519_1522_BYTES_MSB': {'offset': 0x64, 'type': 'ro'}, + 'PACKET_1523_1548_BYTES_LSB': {'offset': 0x68, 'type': 'ro'}, + 'PACKET_1523_1548_BYTES_MSB': {'offset': 0x6C, 'type': 'ro'}, + 'PACKET_1549_2047_BYTES_LSB': {'offset': 0x70, 'type': 'ro'}, + 'PACKET_1549_2047_BYTES_MSB': {'offset': 0x74, 'type': 'ro'}, + 'PACKET_2048_4095_BYTES_LSB': {'offset': 0x78, 'type': 'ro'}, + 'PACKET_2048_4095_BYTES_MSB': {'offset': 0x7C, 'type': 'ro'}, + 'PACKET_4096_8191_BYTES_LSB': {'offset': 0x80, 'type': 'ro'}, + 'PACKET_4096_8191_BYTES_MSB': {'offset': 0x84, 'type': 'ro'}, + 'PACKET_8192_9215_BYTES_LSB': {'offset': 0x88, 'type': 'ro'}, + 'PACKET_8192_9215_BYTES_MSB': {'offset': 0x8C, 'type': 'ro'}, + 'PACKET_LARGE': {'offset': 0x90, 'type': 'ro'}, + 'UNICAST_LSB': {'offset': 0x98, 'type': 'ro'}, + 'UNICAST_MSB': {'offset': 0x9C, 'type': 'ro'}, + 'MULTICAST_LSB': {'offset': 0xA0, 'type': 'ro'}, + 'MULTICAST_MSB': {'offset': 0xA4, 'type': 'ro'}, + 'BROADCAST_LSB': {'offset': 0xA8, 'type': 'ro'}, + 'BROADCAST_MSB': {'offset': 0xAC, 'type': 'ro'}, + 'VLAN_LSB': {'offset': 0xB0, 'type': 'ro'}, + 'VLAN_MSB': {'offset': 0xB4, 'type': 'ro'}, + 'PAUSE_LSB': {'offset': 0xB8, 'type': 'ro'}, + 'PAUSE_MSB': {'offset': 0xBC, 'type': 'ro'}, + 'USER_PAUSE_LSB': {'offset': 0xC0, 'type': 'ro'}, + 'USER_PAUSE_MSB': {'offset': 0xC4, 'type': 'ro'}, + 'MAC_CYCLE_COUNT_LSB': {'offset': 0xC8, 'type': 'ro'}, + 'MAC_CYCLE_COUNT_MSB': {'offset': 0xCC, 'type': 'ro'}, + 'ECC_CORRECTABLE_COUNT': {'offset': 0xD0, 'type': 'ro'}, + 'ECC_UNCORRECTABLE_COUNT': {'offset': 0xD8, 'type': 'ro'}, +} + + +rx_stats_base_reg = { + 'TOTAL_BYTES_LSB': {'offset': 0x00, 'type': 'ro'}, + 'TOTAL_BYTES_MSB': {'offset': 0x04, 'type': 'ro'}, + 'TOTAL_GOOD_BYTES_LSB': {'offset': 0x08, 'type': 'ro'}, + 'TOTAL_GOOD_BYTES_MSB': {'offset': 0x0C, 'type': 'ro'}, + 'TOTAL_PACKETS_LSB': {'offset': 0x10, 'type': 'ro'}, + 'TOTAL_PACKETS_MSB': {'offset': 0x14, 'type': 'ro'}, + 'TOTAL_GOOD_PACKETS_LSB': {'offset': 0x18, 'type': 'ro'}, + 'TOTAL_GOOD_PACKETS_MSB': {'offset': 0x1C, 'type': 'ro'}, + 'PACKET_SMALL_LSB': {'offset': 0x20, 'type': 'ro'}, + 'PACKET_SMALL_MSB': {'offset': 0x24, 'type': 'ro'}, + 'BAD_CODE_COUNT_LSB': {'offset': 0x28, 'type': 'ro'}, + 'BAD_CODE_COUNT_MSB': {'offset': 0x2C, 'type': 'ro'}, + 'BAD_FCS_LSB': {'offset': 0x30, 'type': 'ro'}, + 'BAD_FCS_MSB': {'offset': 0x34, 'type': 'ro'}, + 'PACKET_BAD_FCS_LSB': {'offset': 0x38, 'type': 'ro'}, + 'PACKET_BAD_FCS_MSB': {'offset': 0x3C, 'type': 'ro'}, + 'STOMPED_FCS_LSB': {'offset': 0x40, 'type': 'ro'}, + 'STOMPED_FCS_MSB': {'offset': 0x44, 'type': 'ro'}, + 'TRUNCATED_LSB': {'offset': 0x48, 'type': 'ro'}, + 'TRUNCATED_MSB': {'offset': 0x4C, 'type': 'ro'}, + 'PACKET_64_BYTES_LSB': {'offset': 0x50, 'type': 'ro'}, + 'PACKET_64_BYTES_MSB': {'offset': 0x54, 'type': 'ro'}, + 'PACKET_65_127_BYTES_LSB': {'offset': 0x58, 'type': 'ro'}, + 'PACKET_65_127_BYTES_MSB': {'offset': 0x5C, 'type': 'ro'}, + 'PACKET_128_255_BYTES_LSB': {'offset': 0x60, 'type': 'ro'}, + 'PACKET_128_255_BYTES_MSB': {'offset': 0x64, 'type': 'ro'}, + 'PACKET_256_511_BYTES_LSB': {'offset': 0x68, 'type': 'ro'}, + 'PACKET_256_511_BYTES_MSB': {'offset': 0x6C, 'type': 'ro'}, + 'PACKET_512_1023_BYTES_LSB': {'offset': 0x70, 'type': 'ro'}, + 'PACKET_512_1023_BYTES_MSB': {'offset': 0x74, 'type': 'ro'}, + 'PACKET_1024_1518_BYTES_LSB': {'offset': 0x78, 'type': 'ro'}, + 'PACKET_1024_1518_BYTES_MSB': {'offset': 0x7C, 'type': 'ro'}, + 'PACKET_1519_1522_BYTES_LSB': {'offset': 0x80, 'type': 'ro'}, + 'PACKET_1519_1522_BYTES_MSB': {'offset': 0x84, 'type': 'ro'}, + 'PACKET_1523_1548_BYTES_LSB': {'offset': 0x88, 'type': 'ro'}, + 'PACKET_1523_1548_BYTES_MSB': {'offset': 0x8C, 'type': 'ro'}, + 'PACKET_1549_2047_BYTES_LSB': {'offset': 0x90, 'type': 'ro'}, + 'PACKET_1549_2047_BYTES_MSB': {'offset': 0x94, 'type': 'ro'}, + 'PACKET_2048_4095_BYTES_LSB': {'offset': 0x98, 'type': 'ro'}, + 'PACKET_2048_4095_BYTES_MSB': {'offset': 0x9C, 'type': 'ro'}, + 'PACKET_4096_8191_BYTES_LSB': {'offset': 0xA0, 'type': 'ro'}, + 'PACKET_4096_8191_BYTES_MSB': {'offset': 0xA4, 'type': 'ro'}, + 'PACKET_8192_9215_BYTES_LSB': {'offset': 0xA8, 'type': 'ro'}, + 'PACKET_8192_9215_BYTES_MSB': {'offset': 0xAC, 'type': 'ro'}, + 'TOOLONG': {'offset': 0xB0, 'type': 'ro'}, + 'PACKET_LARGE': {'offset': 0xB8, 'type': 'ro'}, + 'JABBER': {'offset': 0xC0, 'type': 'ro'}, + 'OVERSIZE': {'offset': 0xC8, 'type': 'ro'}, + 'UNICAST_LSB': {'offset': 0xD0, 'type': 'ro'}, + 'UNICAST_MSB': {'offset': 0xD4, 'type': 'ro'}, + 'MULTICAST_LSB': {'offset': 0xD8, 'type': 'ro'}, + 'MULTICAST_MSB': {'offset': 0xDC, 'type': 'ro'}, + 'BROADCAST_LSB': {'offset': 0xE0, 'type': 'ro'}, + 'BROADCAST_MSB': {'offset': 0xE4, 'type': 'ro'}, + 'VLAN_LSB': {'offset': 0xE8, 'type': 'ro'}, + 'VLAN_MSB': {'offset': 0xEC, 'type': 'ro'}, + 'PAUSE_LSB': {'offset': 0xF0, 'type': 'ro'}, + 'PAUSE_MSB': {'offset': 0xF4, 'type': 'ro'}, + 'USER_PAUSE_LSB': {'offset': 0xF8, 'type': 'ro'}, + 'USER_PAUSE_MSB': {'offset': 0xFC, 'type': 'ro'}, + 'INRANGEERR_LSB': {'offset': 0x100, 'type': 'ro'}, + 'INRANGEERR_MSB': {'offset': 0x104, 'type': 'ro'}, + 'MAC_CYCLE_COUNT_LSB': {'offset': 0x108, 'type': 'ro'}, + 'MAC_CYCLE_COUNT_MSB': {'offset': 0x10C, 'type': 'ro'}, +} diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/default_ip.py b/submodules/v80-vitis-flow/resources/dcmac/driver/default_ip.py new file mode 100644 index 00000000..db50ad69 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/default_ip.py @@ -0,0 +1,76 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +from generic_mmio import GenericMMIO +from utils import rshift + + +def decode_control_register(value: int) -> dict: + cregister = {} + cregister['ap_start': bool(rshift(value))] + cregister['ap_done': bool(rshift(value, 1))] + cregister['ap_idle': bool(rshift(value, 2))] + cregister['ap_ready': bool(rshift(value, 3))] + cregister['ap_continue': bool(rshift(value, 4))] + cregister['auto_restart': bool(rshift(value, 7))] + return cregister + +cregs = { + "controlreg": {'offset': 0x0, 'type': 'rw', + 'fields': {'ap_start': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ap_done': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'ap_idle': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'ap_ready': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'ap_continue': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'auto_restart': {'start': 7, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + "globalintreg": {'offset': 0x4, 'type': 'rw'}, + "intenable": {'offset': 0x8, 'type': 'rw'}, + "intstatus": {'offset': 0x10, 'type': 'rw'}, +} + + +class DefaultIP(GenericMMIO): + """Generic IP Driver""" + _controlreg = 0x00 + _globalintreg = 0x04 + _intenable = 0x08 + _intstatus = 0x10 + + def __init__(self, device: str = 'e2', base_offset: int = 0x0, + debug: bool = False, regs: dict = None): + super().__init__(device, base_offset, debug) + self.registers = cregs if regs is None else regs + + def start(self, value: int = 1): + """Start IP once""" + self.write(self._controlreg, value) + + def autostart(self): + """Autostart IP""" + self.start(0x81) + + def controlreg(self) -> dict: + value = self.read(self._controlreg) + cregisters = decode_control_register(value) + print(cregisters) + return cregisters + + def global_interrupt(self): + value = self.read(self._globalintreg) + gintenable = {'global_interrupt_enable': bool(rshift(value))} + print(gintenable) + return gintenable + + def interrupt_enable(self): + value = self.read(self._intenable) + intenable = {'interrupt_enable': bool(rshift(value))} + print(intenable) + return intenable + + def interrupt_status(self): + value = self.read(self._intstatus) + intstatus = {'interrupt_status': bool(rshift(value))} + print(intstatus) + return intstatus diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/generic_mmio.py b/submodules/v80-vitis-flow/resources/dcmac/driver/generic_mmio.py new file mode 100644 index 00000000..1d5fcee8 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/generic_mmio.py @@ -0,0 +1,70 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +from pcie_bar import PCIeMapBar +from utils import int_types, hex_or_int, add_common_args + + +class GenericMMIO: + def __init__(self, device: str = 'e2', base_offset: int = 0x0, + debug: bool = False): + self._base_offset = base_offset + self._pciemmio = PCIeMapBar(device, debug=debug) + self._pciemmio.open() + if debug: + print(f"Base address: {hex(self._base_offset)}") + + def write(self, reg_offset: int = 0, value: int = 0): + if not isinstance(value, int_types): + raise ValueError(f"'{value=}' is not a {int_types} type") + self._pciemmio.write(self._base_offset + reg_offset, value) + + def read(self, reg_offset: int = 0): + return self._pciemmio.read(self._base_offset + reg_offset) + + def read_long(self, offset) -> int: + """Read 8 bytes from BAR 'offset'""" + val_low = self.read(offset) + val_high = self.read(offset + 4) + return int((val_high << 32) + val_low) + + def __del__(self): + self._pciemmio.close() + + @property + def base_address(self): + return self._base_offset + + +def main(args): + obj = GenericMMIO(args.dev, args.baseoffset) + + if args.write: + obj.write(args.offset, args.value) + + if args.read: + val = obj.read(args.offset) + print(f'Offset: 0x{obj._base_offset + args.offset:X}, value=0x{val:X}') + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + + parser.add_argument('-b', '--baseoffset', type=hex_or_int, + help='Base Offset', required=True) + + parser.add_argument('-o', '--offset', type=hex_or_int, + help='Offset', required=True) + + parser.add_argument('-r', '--read', action='store_true', + help='Read') + parser.add_argument('-w', '--write', action='store_true', + help='Write') + parser.add_argument('-v', '--value', type=hex_or_int, + help='Value to be written', default=0) + + parser = add_common_args(parser, False) + args = parser.parse_args() + main(args) diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/gpio_monitor.py b/submodules/v80-vitis-flow/resources/dcmac/driver/gpio_monitor.py new file mode 100644 index 00000000..e1c57565 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/gpio_monitor.py @@ -0,0 +1,66 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +from axigpio_mmio import AxiGpioMMIO +from utils import add_common_args, get_ip_offset + + +shift_map = { + 'gt0_tx_reset_done': {'shift': 0, 'bits': 4}, + 'gt1_tx_reset_done': {'shift': 4, 'bits': 4}, + 'gt0_rx_reset_done': {'shift': 8, 'bits': 4}, + 'gt1_rx_reset_done': {'shift': 12, 'bits': 4}, + 'gtpowergood': {'shift': 16, 'bits': 1}, + 'dual_dcmac': {'shift': 18, 'bits': 1}, +} + + +def _get_shift_and_mask(key: str) -> tuple[int, int]: + """Return the shift and mask give the key""" + map = shift_map[key] + return map['shift'], (1 << map['bits']) - 1 + + +class AxiGPIOMonitor(AxiGpioMMIO): + + def __init__(self, device: str = 'e2', base_offset: int = 0x0, + gpio_index: int = 0): + self._gpio_index = gpio_index + super().__init__(device, base_offset) + + def _get(self, key: str, gpio: int = 0): + shift, mask = _get_shift_and_mask(key) + return (self.read(gpio) >> shift) & mask + + def _create_property(key: str, gpio: int = 0): + """Create property getter and setter for given key.""" + return property( + lambda self: self._get(key, gpio) + ) + + gt0_tx_reset_done = _create_property('gt0_tx_reset_done') + gt1_tx_reset_done = _create_property('gt1_tx_reset_done') + gt0_rx_reset_done = _create_property('gt0_rx_reset_done') + gt1_rx_reset_done = _create_property('gt1_rx_reset_done') + gtpowergood = _create_property('gtpowergood') + dual_dcmac = _create_property('dual_dcmac') + + +def main(args): + offset = get_ip_offset(0x204_0200, args.dcmac) + obj = AxiGPIOMonitor(args.dev, offset, gpio_index=0) + + print(f'{obj.gt0_tx_reset_done=}') + print(f'{obj.gt0_rx_reset_done=}') + print(f'{obj.gt1_tx_reset_done=}') + print(f'{obj.gt1_rx_reset_done=}') + print(f'{obj.gtpowergood=}') + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser = add_common_args(parser) + + main(parser.parse_args()) diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/netlayer_regs.py b/submodules/v80-vitis-flow/resources/dcmac/driver/netlayer_regs.py new file mode 100644 index 00000000..9a94003a --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/netlayer_regs.py @@ -0,0 +1,58 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +nl_regs = { + "mac_address": {'offset': 0x0010, 'size': 8, 'type': 'rw'}, + "ip_address": {'offset': 0x0018, 'size': 4, 'type': 'rw'}, + "gateway": {'offset': 0x001C, 'size': 4, 'type': 'rw'}, + "ip_mask": {'offset': 0x0020, 'size': 4, 'type': 'rw'}, + "eth_in_cycles": {'offset': 0x0400, 'size': 8, 'type': 'ro'}, + "eth_in_bytes": {'offset': 0x0408, 'size': 8, 'type': 'ro'}, + "eth_in_packets": {'offset': 0x0410, 'size': 8, 'type': 'ro'}, + "pkth_in_cycles": {'offset': 0x0418, 'size': 8, 'type': 'ro'}, + "pkth_in_bytes": {'offset': 0x0420, 'size': 8, 'type': 'ro'}, + "pkth_in_packets": {'offset': 0x0428, 'size': 8, 'type': 'ro'}, + "arp_in_cycles": {'offset': 0x0430, 'size': 8, 'type': 'ro'}, + "arp_in_bytes": {'offset': 0x0438, 'size': 8, 'type': 'ro'}, + "arp_in_packets": {'offset': 0x0440, 'size': 8, 'type': 'ro'}, + "arp_out_cycles": {'offset': 0x0448, 'size': 8, 'type': 'ro'}, + "arp_out_bytes": {'offset': 0x0450, 'size': 8, 'type': 'ro'}, + "arp_out_packets": {'offset': 0x0458, 'size': 8, 'type': 'ro'}, + "icmp_in_cycles": {'offset': 0x0460, 'size': 8, 'type': 'ro'}, + "icmp_in_bytes": {'offset': 0x0468, 'size': 8, 'type': 'ro'}, + "icmp_in_packets": {'offset': 0x0470, 'size': 8, 'type': 'ro'}, + "icmp_out_cycles": {'offset': 0x0478, 'size': 8, 'type': 'ro'}, + "icmp_out_bytes": {'offset': 0x0480, 'size': 8, 'type': 'ro'}, + "icmp_out_packets": {'offset': 0x0488, 'size': 8, 'type': 'ro'}, + "ethhi_out_cycles": {'offset': 0x0490, 'size': 8, 'type': 'ro'}, + "ethhi_out_bytes": {'offset': 0x0498, 'size': 8, 'type': 'ro'}, + "ethhi_out_packets": {'offset': 0x04A0, 'size': 8, 'type': 'ro'}, + "eth_out_cycles": {'offset': 0x04A8, 'size': 8, 'type': 'ro'}, + "eth_out_bytes": {'offset': 0x04B0, 'size': 8, 'type': 'ro'}, + "eth_out_packets": {'offset': 0x04B8, 'size': 8, 'type': 'ro'}, + "udp_in_cycles": {'offset': 0x04C0, 'size': 8, 'type': 'ro'}, + "udp_in_bytes": {'offset': 0x04C8, 'size': 8, 'type': 'ro'}, + "udp_in_packets": {'offset': 0x04D0, 'size': 8, 'type': 'ro'}, + "app_out_cycles": {'offset': 0x04D8, 'size': 8, 'type': 'ro'}, + "app_out_bytes": {'offset': 0x04E0, 'size': 8, 'type': 'ro'}, + "app_out_packets": {'offset': 0x04E8, 'size': 8, 'type': 'ro'}, + "udp_out_cycles": {'offset': 0x04F0, 'size': 8, 'type': 'ro'}, + "udp_out_bytes": {'offset': 0x04F8, 'size': 8, 'type': 'ro'}, + "udp_out_packets": {'offset': 0x0500, 'size': 8, 'type': 'ro'}, + "app_in_cycles": {'offset': 0x0508, 'size': 8, 'type': 'ro'}, + "app_in_bytes": {'offset': 0x0510, 'size': 8, 'type': 'ro'}, + "app_in_packets": {'offset': 0x0518, 'size': 8, 'type': 'ro'}, + "debug_reset_counters": {'offset': 0x05F0, 'size': 4, 'type': 'rw'}, + "frequency": {'offset': 0x05F4, 'size': 4, 'type': 'ro'}, + "probes_ports": {'offset': 0x05F8, 'size': 4, 'type': 'ro'}, + "probes_mode": {'offset': 0x05FC, 'size': 4, 'type': 'ro'}, + "udp_number_sockets": {'offset': 0x0810, 'size': 4, 'type': 'ro'}, + "udp_theirIP_offset": {'offset': 0x0820, 'size': 4, 'type': 'rw'}, + "udp_theirPort_offset": {'offset': 0x08A0, 'size': 4, 'type': 'rw'}, + "udp_myPort_offset": {'offset': 0x0920, 'size': 4, 'type': 'rw'}, + "udp_valid_offset": {'offset': 0x09A0, 'size': 4, 'type': 'rw'}, + "arp_discovery": {'offset': 0x1010, 'size': 4, 'type': 'rw'}, + "arp_valid_offset": {'offset': 0x1100, 'size': 4, 'type': 'rw'}, + "arp_ip_addr_offset": {'offset': 0x1400, 'size': 4, 'type': 'rw'}, + "arp_mac_addr_offset": {'offset': 0x1800, 'size': 4, 'type': 'rw'}, +} \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/network_end2end_test.py b/submodules/v80-vitis-flow/resources/dcmac/driver/network_end2end_test.py new file mode 100644 index 00000000..caf659c0 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/network_end2end_test.py @@ -0,0 +1,128 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +import time +from dcmac_init import dcmac_logic_init +from dcmac_mmio import DCMAC +from utils import add_common_args, get_ip_offset +from udp_utils import NetworkLayer +from trafficgen import TrafficGenerator + +"""This file aims at doing a test of the Ethernet or UDP layer between two interfaces in +board, interface 0 and 2. It will initialize the DCMAC and then setup the +interfaces IP, MAC addresses as well as the UDP socket table. +""" + +DCMAC_BASEADDR = 0x200_0000 +TRAFFICGEN_BASEADDR = 0x400_2000 +NL_BASEADDR = 0x400_0000 + + +class ArgsClass: + dcmac = 0 + init = False + print = 1 + dev = None + verbose = 1 + loopback = None + keep_alive = 0 + align_rx = 1 + traffic_test = 0 + + +def main(args): + """Initialize DCMAC in each interface""" + init_args = ArgsClass() + init_args.dev = args.dev + """Init DCMAC 0""" + dcmac_logic_init(init_args) + + """Init DCMAC 0""" + init_args.dcmac = 1 + dcmac_logic_init(init_args) + + # reset TX first then RX + if args.udp: + """Basic network layer config""" + nl0 = NetworkLayer(args.dev, get_ip_offset(NL_BASEADDR, 0)) + nl1 = NetworkLayer(args.dev, get_ip_offset(NL_BASEADDR, 2)) + + print(f'nl0._base_offset=0x{nl0._base_offset:0X}') + print(f'nl1._base_offset=0x{nl1._base_offset:0X}') + + ip_if0 = '192.168.10.5' + ip_if1 = '192.168.10.6' + nl0.set_ip_address(ip_if0) + nl1.set_ip_address(ip_if1) + nl0.set_mac_address('b8:3f:d2:24:51:c0') + nl1.set_mac_address('b8:3f:d2:24:51:c1') + + print(f'NL0: {nl0.get_network_info()}') + print(f'NL1: {nl1.get_network_info()}') + + """Reset debug stats""" + nl0.reset_debug_stats() + nl1.reset_debug_stats() + + """Start ARP Discovery""" + nl0.arp_discovery() + time.sleep(1) + nl1.arp_discovery() + time.sleep(1) + + print(f'NL0 ARP Table: {nl0.get_arp_table(12, verbose=1)}') + print(f'NL1 ARP Table: {nl1.get_arp_table(12, verbose=1)}') + + """Populate socket table""" + port_tx = 50446 + port_rx = 60133 + nl0.sockets[0] = (ip_if1, port_tx, port_rx, True) + nl0.populate_socket_table(debug=True) + nl1.sockets[0] = (ip_if0, port_rx, port_tx, True) + nl1.populate_socket_table(debug=True) + + """Now we can generate some traffic""" + + tgen0 = TrafficGenerator(args.dev, get_ip_offset(TRAFFICGEN_BASEADDR, 0)) + tgen1 = TrafficGenerator(args.dev, get_ip_offset(TRAFFICGEN_BASEADDR, 2)) + + tgen0.flits = 22 + tgen0.dest = 0 + tgen0.start() + time.sleep(1) + + tgen1.flits = 22 + tgen1.dest = 0 + tgen1.start() + time.sleep(1) + + if args.udp: + """Get Statistics""" + print('\n') + nl0.get_debug_stats(True) + print('\n') + nl1.get_debug_stats(True) + print('\n') + + dcmac0 = DCMAC(args.dev, get_ip_offset(DCMAC_BASEADDR, 0)) + dcmac1 = DCMAC(args.dev, get_ip_offset(DCMAC_BASEADDR, 1)) + + print(f'{dcmac0.tx_stats(verbose=1)=}') + print(f'{dcmac0.rx_stats(verbose=1)=}') + + print(f'{dcmac1.tx_stats(verbose=1)=}') + print(f'{dcmac1.rx_stats(verbose=1)=}') + + if args.udp: + print(f'{nl0.get_freq=}') + print(f'{nl1.get_freq=}') + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-u', '--udp', action='store_true', + help='Use UDP logic') + parser = add_common_args(parser, verbose=True) + args = parser.parse_args() + main(args) diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/pcie_bar.py b/submodules/v80-vitis-flow/resources/dcmac/driver/pcie_bar.py new file mode 100644 index 00000000..1537e874 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/pcie_bar.py @@ -0,0 +1,62 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import mmap +from warnings import warn +import numpy as np +BAR_SIZE = 256 * 1024 * 1024 # 256 MB + + +def _get_bar_path(dev, debug=True): + """Generate BAR path based on the PCIe Bus ID""" + dev_path = f"/sys/bus/pci/devices/0000:{dev}:00.0/resource0" + if debug: + print(f"Using BDF: {dev_path}") + return dev_path + + +class PCIeMapBar: + """Wrapper class to allows MMIO read and write operations from PCIe BAR""" + def __init__(self, device: str = 'e2', barsize: int = BAR_SIZE, + debug: bool = True): + self._bar = None + self._barpath = _get_bar_path(device, debug) + self._barsize = barsize + + def open(self): + """Open BAR""" + with open(self._barpath, "r+b") as f: + self._bar = mmap.mmap(f.fileno(), self._barsize, mmap.MAP_SHARED, + mmap.PROT_READ | mmap.PROT_WRITE) + self.mem = np.frombuffer(self._bar, np.uint32, (self._barsize+3) >> 2) + + def close(self): + """Close BAR""" + if self._bar is not None: + del self.mem + self._bar.close() + self._bar = None + + def read(self, byte_offset: int) -> int: + """Read 4 bytes from BAR 'byte_offset'""" + if byte_offset & 0x3: + warn(f"Byte offset {byte_offset} is not aligned to 32-bit words." + + "Aligning to previous 32-bit boundary") + if self._bar is None: + raise RuntimeError('BAR is not opened') + + return int(self.mem[byte_offset >> 2]) + + def write(self, byte_offset: int, value: int): + """Write 4 bytes to BAR 'byte_offset'""" + if byte_offset & 0x3: + warn(f"Byte offset {byte_offset} is not aligned to 32-bit words." + + "Aligning to previous 32-bit boundary") + if self._bar is None: + raise RuntimeError('BAR is not opened') + value_32 = value & 0xFFFFFFFF + if value_32 != value: + warn("Trying to write a value larger than 32 bits to the PCIe " + + "device, truncating to 32 bits") + + self.mem[byte_offset >> 2] = value_32 diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/requirements.txt b/submodules/v80-vitis-flow/resources/dcmac/driver/requirements.txt new file mode 100644 index 00000000..8b48365f --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/requirements.txt @@ -0,0 +1,3 @@ +numpy +tabulate +IPython diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/trafficgen.py b/submodules/v80-vitis-flow/resources/dcmac/driver/trafficgen.py new file mode 100644 index 00000000..018f8171 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/trafficgen.py @@ -0,0 +1,63 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +from default_ip import DefaultIP +from utils import add_common_args, get_ip_offset + + +class TrafficGenerator(DefaultIP): + """Specialization to support TrafficGenerator IP""" + + _flits_offset = 0x10 + _dest_offset = 0x18 + + @property + def dest(self): + value = self.read(self._dest_offset) + return value + + @dest.setter + def dest(self, value: int): + if not isinstance(value, int): + raise ValueError(f"{value=} must be an integer") + elif value < 0: + raise ValueError(f"{value=} must be a positive integer") + + self.write(self._dest_offset, value) + + @property + def flits(self): + value = self.read(self._flits_offset) + return value + + @flits.setter + def flits(self, value: int): + if not isinstance(value, int): + raise ValueError(f"{value=} must be an integer") + elif value < 1: + raise ValueError(f"{value=} must be bigger than 0") + + self.write(self._flits_offset, value) + + +def main(args): + intf = 0 + offset = get_ip_offset(0x400_0000, args.dcmac*2 +intf) + tgen = TrafficGenerator(args.dev, offset) + + tgen.flits = args.flits + tgen.dest = 0 + tgen.start() + del tgen + + +if __name__ == '__main__': + parser = argparse.ArgumentParser() + parser.add_argument('-f', '--flits', type=int, default=10, + help='Number of 64-Byte flits', required=False) + + parser = add_common_args(parser) + args = parser.parse_args() + + main(args) diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/udp_utils.py b/submodules/v80-vitis-flow/resources/dcmac/driver/udp_utils.py new file mode 100644 index 00000000..8fc5ed97 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/udp_utils.py @@ -0,0 +1,637 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import ipaddress +import numpy as np +from enum import Enum +from tabulate import tabulate +from IPython.display import JSON +from default_ip import DefaultIP +from netlayer_regs import nl_regs + + +def _byte_ordering_endianess(num, length=4): + """ + Convert from little endian to big endian and vice versa + + Parameters + ---------- + num: int + input number + + length: + number of bytes of the input number + + Returns + ------- + An integer with the endianness changed with respect to input number + + """ + if not isinstance(num, int): + raise ValueError("num must be an integer") + + if not isinstance(length, int): + raise ValueError("length must be an positive integer") + elif length < 0: + raise ValueError("length cannot be negative") + + aux = 0 + for i in range(length): + byte_index = num >> ((length - 1 - i) * 8) & 0xFF + aux += byte_index << (i * 8) + return aux + + +class NetworkLayer(DefaultIP): + """This class wraps the common function of the Network Layer IP + + """ + + bindto = ["xilinx.com:kernel:networklayer:1.0"] + + _socketType = np.dtype( + [ + ("theirIP", str, 16), + ("theirPort", np.uint16), + ("myPort", np.uint16), + ("valid", bool), + ] + ) + + def __init__(self, device: str = 'e2', base_offset: int = 0x0, + debug: bool = False): + super().__init__(device, base_offset, debug) + self.registers = nl_regs + self.sockets = np.zeros(16, dtype=self._socketType) + self.freq = None + + def populate_socket_table(self, debug: bool = False): + """ + Populate a socket table + + Optionals + --------- + debug: bool + If enables read the current status of the UDP Table + + Returns + ------- + If debug is enable read the current status of the UDP Table + + """ + + theirIP_offset = self.registers['udp_theirIP_offset']['offset'] + theirPort_offset = self.registers['udp_theirPort_offset']['offset'] + udp_myPort_offset = self.registers['udp_myPort_offset']['offset'] + udp_valid_offset = self.registers['udp_valid_offset']['offset'] + numSocketsHW = int(self.read(self.registers['udp_number_sockets']['offset'])) + + if numSocketsHW < len(self.sockets): + raise Exception(f"Socket list length ({len(self.sockets)}) is " + "bigger than the number of sockets in hardware " + f"({numSocketsHW})") + + # Iterate over the socket object + for i in range(numSocketsHW): + ti_offset = theirIP_offset + i * 8 + tp_offset = theirPort_offset + i * 8 + mp_offset = udp_myPort_offset + i * 8 + v_offset = udp_valid_offset + i * 8 + + theirIP = 0 + if self.sockets[i]["theirIP"]: + theirIP = int(ipaddress.IPv4Address(self.sockets[i] + ["theirIP"])) + + self.write(ti_offset, theirIP) + self.write(tp_offset, int(self.sockets[i]["theirPort"])) + self.write(mp_offset, int(self.sockets[i]["myPort"])) + self.write(v_offset, int(self.sockets[i]["valid"])) + + if debug: + return self.get_socket_table() + + def get_socket_table(self) -> dict: + """ Reads the socket table + + Returns + ------- + Returns socket table + """ + + theirIP_offset = self.registers['udp_theirIP_offset']['offset'] + theirPort_offset = self.registers['udp_theirPort_offset']['offset'] + udp_myPort_offset = self.registers['udp_myPort_offset']['offset'] + udp_valid_offset = self.registers['udp_valid_offset']['offset'] + numSocketsHW = int(self.read(self.registers['udp_number_sockets']['offset'])) + + socket_dict = dict() + socket_dict['Number of Sockets'] = numSocketsHW + socket_dict['socket'] = dict() + # Iterate over all the UDP table + for i in range(numSocketsHW): + ti_offset = theirIP_offset + i * 8 + tp_offset = theirPort_offset + i * 8 + mp_offset = udp_myPort_offset + i * 8 + v_offset = udp_valid_offset + i * 8 + isvalid = self.read(v_offset) + if isvalid: + ti = self.read(ti_offset) + tp = self.read(tp_offset) + mp = self.read(mp_offset) + socket_dict['socket'][i] = dict() + socket_dict['socket'][i]['theirIP'] = \ + str(ipaddress.IPv4Address(ti)) + socket_dict['socket'][i]['theirPort'] = tp + socket_dict['socket'][i]['myPort'] = mp + + print(f'{socket_dict=}') + return JSON(socket_dict, rootname='socket_table') + + def invalidate_socket_table(self): + """ Clear the Socket table """ + + udp_valid_offset = self.registers['udp_valid_offset']['offset'] + numSocketsHW = int(self.registers['udp_number_sockets']) + for i in range(numSocketsHW): + self.write(int(udp_valid_offset + i * 8), 0) + + def get_arp_table(self, num_entries: int=256, verbose: int=0) -> dict: + """Read the ARP table from the FPGA return a dict + + Parameters + ---------- + Optionals + --------- + num_entries: int + number of entries in the table to be consider when printing + + Returns + ------- + Prints the content of valid entries in the ARP in a friendly way + """ + + if not isinstance(num_entries, int): + raise ValueError("Number of entries must be integer.") + elif num_entries < 0: + raise ValueError("Number of entries cannot be negative.") + elif num_entries > 256: + raise ValueError("Number of entries cannot be bigger than 256.") + + mac_addr_offset = self.registers['arp_mac_addr_offset']['offset'] + ip_addr_offset = self.registers['arp_ip_addr_offset']['offset'] + valid_addr_offset = self.registers['arp_valid_offset']['offset'] + + arptable = dict() + + valid_entry = None + for i in range(num_entries): + if (i % 4) == 0: + valid_entry = self.read(valid_addr_offset + (i // 4) * 4) + + isvalid = (valid_entry >> ((i % 4) * 8)) & 0x1 + if isvalid or verbose > 0: + mac_lsb = self.read(mac_addr_offset + (i * 2 * 4)) + mac_msb = self.read(mac_addr_offset + ((i * 2 + 1) * 4)) + ip_addr = self.read(ip_addr_offset + (i * 4)) + mac_addr = (2 ** 32) * mac_msb + mac_lsb + mac_hex = "{:012x}".format( + _byte_ordering_endianess(mac_addr, 6)) + mac_str = ":".join( + mac_hex[i: i + 2] for i in range(0, len(mac_hex), 2) + ) + ip_addr_print = _byte_ordering_endianess(ip_addr) + arptable[i] = { + "MAC address": mac_str, + "IP address": str(ipaddress.IPv4Address(ip_addr_print)) + } + + headers = ["Index", "MAC Address", "IP Address"] + table_data = [] + for key, value in arptable.items(): + mac_address = value["MAC address"] + ip_address = value["IP address"] + table_data.append([key, mac_address, ip_address]) + + print(tabulate(table_data, headers=headers, tablefmt="pretty")) + #return JSON(arptable, rootname='ARP Table') + + def write_arp_entry(self, mac: str, ip: str): + """ + Add an entry to the ARP table + + Parameters + ---------- + mac: str + MAC address in the format XX:XX:XX:XX:XX:XX + ip: str + IP address in the format XXX.XXX.XXX.XXX + + Note, VNx requires all IPs in the ARP table to be in the same + /24 subnet (mask 255.255.255.0) as the IP assigned to the FPGA port. + + There are 256 entries in the ARP table, one for each possible IP + in the subnet, the least significant 8 bits of the IP are used to + index into the ARP table. + """ + + if not isinstance(mac, str): + raise ValueError("MAC address must be a string.") + elif not isinstance(ip, str): + raise ValueError("IP address must be a string.") + + mac_int = int("0x{}".format(mac.replace(":", "")), 16) + big_mac_int = _byte_ordering_endianess(mac_int, 6) + mac_msb = (big_mac_int >> 32) & 0xFFFFFFFF + mac_lsb = big_mac_int & 0xFFFFFFFF + + ip_int = int(ipaddress.IPv4Address(ip)) + big_ip_int = _byte_ordering_endianess(ip_int, 4) + + mac_addr_offset = self.registers['arp_mac_addr_offset']['offset'] + ip_addr_offset = self.registers['arp_ip_addr_offset']['offset'] + valid_addr_offset = self.registers['arp_valid_offset']['offset'] + + i = ip_int % 256 + self.write(ip_addr_offset + (i * 4), big_ip_int) + self.write(mac_addr_offset + (i * 2 * 4), mac_lsb) + self.write(mac_addr_offset + ((i * 2 + 1) * 4), mac_msb) + + # Valid + old_valid_entry = self.read(valid_addr_offset + (i // 4) * 4) + this_valid = 1 << ((i % 4) * 8) + self.write(valid_addr_offset + (i // 4) * 4, + old_valid_entry | this_valid) + + def invalidate_arp_table(self): + """ + Clear the ARP table + """ + valid_addr_offset = self.registers['arp_valid_offset']['offset'] + + for i in range(0, 256//4, 4): + self.write(valid_addr_offset + i, 0) + + def arp_discovery(self): + """ + Launch ARP discovery + """ + + # The ARP discovery is trigger with the rising edge + self.write(self.registers['arp_discovery']['offset'], 0) + self.write(self.registers['arp_discovery']['offset'], 1) + self.write(self.registers['arp_discovery']['offset'], 0) + + def get_network_info(self) -> dict: + """Returns a dictionary with the current configuration + """ + mac_addr = int(self.read_long(self.registers['mac_address']['offset'])) + ip_addr = int(self.read(self.registers['ip_address']['offset'])) + ip_gw = int(self.read(self.registers['gateway']['offset'])) + ip_mask = int(self.read(self.registers['ip_mask']['offset'])) + + mac_hex = "{:012x}".format(mac_addr) + mac_str = ":".join(mac_hex[i: i + 2] + for i in range(0, len(mac_hex), 2)) + + config = { + "HWaddr": mac_str, + "inet addr": str(ipaddress.IPv4Address(ip_addr)), + "gateway addr": str(ipaddress.IPv4Address(ip_gw)), + "Mask": str(ipaddress.IPv4Address(ip_mask)), + } + print(f'{config=}') + return JSON(config, rootname='Network Information') + + def set_ip_address(self, ipaddrsrt, gwaddr="None", debug=False): + """ + Update IP address as well as least significant octet of the + MAC address with the least significant octet of the IP address + + Parameters + ---------- + ipaddrsrt : string + New IP address + + gwaddr : string + New IP gateway address, if not defined a default gateway is used + debug: bool + if enable it will return the current configuration + + Returns + ------- + Current interface configuration only if debug == True + + """ + + if not isinstance(ipaddrsrt, str): + raise ValueError("ipaddrsrt must be an string type") + + if not isinstance(gwaddr, str): + raise ValueError("gwaddr must be an string type") + + if not isinstance(debug, bool): + raise ValueError("debug must be a bool type") + + ipaddr = int(ipaddress.IPv4Address(ipaddrsrt)) + self.write(self.registers['ip_address']['offset'], ipaddr) + if gwaddr == "None": + self.write(self.registers['gateway']['offset'], (ipaddr & 0xFFFFFF00) + 1) + else: + self.write(self.registers['gateway']['offset'], int(ipaddress.IPv4Address(gwaddr))) + + + #currentMAC = int(self.read(self.registers['mac_address']['offset'])) + #newMAC = (currentMAC & 0xFFFFFFFFF00) + (ipaddr & 0xFF) + #self.write(self.registers['mac_address']['offset'], newMAC) + + if debug: + return self.get_network_info() + + def set_mac_address(self, mac_addr: str): + """ Update the MAC address of the interface + + Parameters + ---------- + mac_addr : str + MAC address in the format XX:XX:XX:XX:XX:XX + """ + if not isinstance(mac_addr, str): + raise ValueError("MAC address must be a string.") + + mac_int = int("0x{}".format(mac_addr.replace(":", "")), 16) + mac_low = mac_int & 0xFFFFFFFF + mac_high = (mac_int >> 32) & 0xFFFFFFFF + self.write(self.registers['mac_address']['offset'], mac_low) + self.write(self.registers['mac_address']['offset'] + 4, mac_high) + + def reset_debug_stats(self) -> None: + """Reset debug probes + """ + + self.write(self.registers['debug_reset_counters']['offset'], 1) + + def get_debug_stats(self, debug: bool=True) -> dict: + """Return a dictionary with the value of the Network Layer probes""" + + rmap = self.registers + probes = dict() + probes["tx_path"] = dict() + probes["rx_path"] = dict() + + probes["rx_path"] = { + "ethernet": { + "packets": int(self.read(rmap['eth_in_packets']['offset'])), + "bytes": int(self.read(rmap['eth_in_bytes']['offset'])), + "cycles": int(self.read(rmap['eth_in_cycles']['offset'])) + }, + "packet_handler": { + "packets": int(self.read(rmap['pkth_in_packets']['offset'])), + "bytes": int(self.read(rmap['pkth_in_bytes']['offset'])), + "cycles": int(self.read(rmap['pkth_in_cycles']['offset'])) + }, + "arp": { + "packets": int(self.read(rmap['arp_in_packets']['offset'])), + "bytes": int(self.read(rmap['arp_in_bytes']['offset'])), + "cycles": int(self.read(rmap['arp_in_cycles']['offset'])) + }, + "icmp": { + "packets": int(self.read(rmap['icmp_in_packets']['offset'])), + "bytes": int(self.read(rmap['icmp_in_bytes']['offset'])), + "cycles": int(self.read(rmap['icmp_in_cycles']['offset'])) + }, + "udp": { + "packets": int(self.read(rmap['udp_in_packets']['offset'])), + "bytes": int(self.read(rmap['udp_in_bytes']['offset'])), + "cycles": int(self.read(rmap['udp_in_cycles']['offset'])) + }, + "app": { + "packets": int(self.read(rmap['app_in_packets']['offset'])), + "bytes": int(self.read(rmap['app_in_bytes']['offset'])), + "cycles": int(self.read(rmap['app_in_cycles']['offset'])) + } + } + + probes['tx_path'] = { + "arp": { + "packets": int(self.read(rmap['arp_out_packets']['offset'])), + "bytes": int(self.read(rmap['arp_out_bytes']['offset'])), + "cycles": int(self.read(rmap['arp_out_cycles']['offset'])) + }, + "icmp": { + "packets": int(self.read(rmap['icmp_out_packets']['offset'])), + "bytes": int(self.read(rmap['icmp_out_bytes']['offset'])), + "cycles": int(self.read(rmap['icmp_out_cycles']['offset'])) + }, + "ethernet_header_inserter": { + "packets": int(self.read(rmap['ethhi_out_packets']['offset'])), + "bytes": int(self.read(rmap['ethhi_out_bytes']['offset'])), + "cycles": int(self.read(rmap['ethhi_out_cycles']['offset'])) + }, + "ethernet": { + "packets": int(self.read(rmap['eth_out_packets']['offset'])), + "bytes": int(self.read(rmap['eth_out_bytes']['offset'])), + "cycles": int(self.read(rmap['eth_out_cycles']['offset'])) + }, + "udp": { + "packets": int(self.read(rmap['udp_out_packets']['offset'])), + "bytes": int(self.read(rmap['udp_out_bytes']['offset'])), + "cycles": int(self.read(rmap['udp_out_cycles']['offset'])) + }, + "app": { + "packets": int(self.read(rmap['app_out_packets']['offset'])), + "bytes": int(self.read(rmap['app_out_bytes']['offset'])), + "cycles": int(self.read(rmap['app_out_cycles']['offset'])) + } + } + + for path, stats in probes.items(): + table_data = [] + for protocol, v in stats.items(): + tot_bytes = v['bytes'] + tot_cycles = v['cycles'] + thr_bs = 0 + if tot_cycles != 0: + tot_time = (1 / (390.625 * 10 ** 6)) * tot_cycles + thr_bs = (tot_bytes * 8) / tot_time + table_data.append([protocol, v['packets'], tot_bytes, tot_cycles, f'{thr_bs/10**6:.2f}']) + + print(f"Debug {path} probes") + print(tabulate(table_data, headers=[f'Probe {path}', 'Packets', 'Bytes', 'Cycles', 'BW (Mb/s)'], tablefmt='pretty')) + + return JSON(probes, rootname='debug_probes') + + @property + def get_freq(self): + return int(self.read(self.registers['frequency']['offset'])) + + +class TgMode(Enum): + """Supported Traffic generator Modes""" + PRODUCER = 0 + LATENCY = 1 + LOOPBACK = 2 + CONSUMER = 3 + + +class TrafficGenerator(DefaultIP): + """ This class wraps the common function of the Traffic Generator IP + """ + + bindto = ["xilinx.com:kernel:traffic_generator:1.0"] + + def __init__(self, description): + super().__init__(description=description) + self.start = self._call = self._start_sw = self.start_sw = self.call = self._start_ert + self.freq = None + + def _start_ert(self, mode: TgMode, dest: int=0, packets: int=None, + beats: int=None, tbwp: int=None): + """Starts the Traffic generator + + Parameters + ---------- + mode: TgMode + Operation mode + dest: int + Index in the socket table + + Optional + -------- + packets: int + Number of packets + num_beats: int + Number of transactions per piece of payload + tbwp: + Clock ticks between two consecutive payload packets + """ + if mode == TgMode.PRODUCER or mode == TgMode.LATENCY: + if packets is None: + raise RuntimeError("packets must be specified when mode is {}" + .format(mode)) + elif beats is None: + raise RuntimeError("beats must be specified when mode is {}" + .format(mode)) + elif tbwp is None: + raise RuntimeError("tbwp must be specified when mode is {}" + .format(mode)) + + self.register_map.number_packets = packets + self.register_map.number_beats = beats + self.register_map.time_between_packets = tbwp + + self.register_map.mode = int(mode.value) + self.register_map.dest_id = dest + self.register_map.CTRL.AP_START = 1 + + def reset_fsm(self): + """Reset internal FSM""" + self.register_map.reset_fsm = 1 + + def compute_app_throughput(self, direction: str="rx") -> float: + """ + Read the application monitoring registers and compute + throughput, it also returns other useful information + + Parameters + ---------- + direction: string + 'rx' or 'tx' + + Returns + ------- + Total number of packets seen by the monitoring probe, + throughput and total time + """ + + if direction not in ["rx", "tx"]: + raise ValueError( + "Only 'rx' and 'tx' strings are supported \ + on direction argument" + ) + + if direction == "rx": + tot_bytes = int(self.register_map.in_traffic_bytes) + tot_cycles = int(self.register_map.in_traffic_cycles) + tot_pkts = int(self.register_map.in_traffic_packets) + else: + tot_bytes = int(self.register_map.out_traffic_bytes) + tot_cycles = int(self.register_map.out_traffic_cycles) + tot_pkts = int(self.register_map.out_traffic_packets) + + tot_time = (1 / (self.freq * 10 ** 6)) * tot_cycles + thr_bs = (tot_bytes * 8) / tot_time + + return tot_pkts, thr_bs / (10 ** 9), tot_time + + def reset_stats(self): + """ + Reset embedded probes + """ + self.register_map.debug_reset = 1 + + +class CounterIP(DefaultIP): + """ This class wraps the common function of counter IP + + """ + + bindto = ["xilinx.com:hls:krnl_counters:1.0"] + + def __init__(self, description): + super().__init__(description=description) + self._fullpath = description['fullpath'] + self.start = self.start_sw = self.start_none = \ + self.start_ert = self.call + + def _setup_packet_prototype(self): + pass + + def call(self, *args, **kwargs): + raise RuntimeError("{} is a free running kernel and cannot be " + "starter or called".format(self._fullpath)) + + @property + def counters(self): + """ Return counters + + """ + + counters = { + 'packets': int(self.register_map.packets), + 'beats': int(self.register_map.beats), + 'bytes': int(self.register_map.bytes), + } + + return counters + + def reset_counters(self): + """ Reset internal counters + + """ + + self.register_map.reset = 0 + self.register_map.reset = 1 + self.register_map.reset = 0 + + +class CollectorIP(DefaultIP): + """ This class wraps the common function the collector Kernel + + """ + + bindto = ["xilinx.com:hls:collector:1.0"] + + def __init__(self, description): + super().__init__(description=description) + + @property + def received_packets(self): + # When a register is written by the kernel for non free running kernels + # the default offset refers to the value that the kernel reads + # the actual register where the kernel writes is not exposed in the + # signature, so we need to compute the offset and use mmio to read it + + rx_pkts_offset = self.register_map.received_packets.address + \ + self.register_map.received_packets.width//8 + 4 + return self.read(rx_pkts_offset) \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/dcmac/driver/utils.py b/submodules/v80-vitis-flow/resources/dcmac/driver/utils.py new file mode 100644 index 00000000..15fe50d7 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/driver/utils.py @@ -0,0 +1,47 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +import numpy as np +import os + +int_types = (int, np.int8, np.int16, np.int32, np.uint8, np.uint16, np.uint32) + + +def hex_or_int(value): + try: + if value.startswith(('0x', '0X')): + return int(value, 16) + return int(value) + except ValueError: + raise argparse.ArgumentTypeError(f"Invalid value: {value}. Must be an " + "integer or hexadecimal.") + + +def rshift(value: int, shift: int = 0, bitwidth: int = 1): + """Right shift value and mask with 'bitwidth'""" + value = value >> shift + mask = (2**bitwidth)-1 + return int(value & mask) + + +def get_ip_offset(baseoffset: int, mac_id: int): + """Get IP offset based on 'baseoffset' and 'mac_id'""" + + return baseoffset + (0x100_0000 * mac_id) + + +def add_common_args(parser, enable_mac: bool = True, verbose: bool = False): + """Add common arguments to the parser""" + default_dev = os.environ['V80_DEV'] if 'V80_DEV' in os.environ else 'e2' + parser.add_argument('-d', '--dev', help=f"PCIe device Bus ID, e.g., '{default_dev}'", + default=default_dev) + if enable_mac: + default_dcmac_id = os.environ['V80_DCMAC_ID'] if 'V80_DCMAC_ID' in os.environ else '0' + parser.add_argument('-m', '--dcmac', help="DCMAC ID either 0 or 1", + default=default_dcmac_id, choices=[0, 1], type=int) + if verbose: + parser.add_argument('-v', '--verbose', type=int, default=0, + choices=[0, 1], help='Verbosity mode') + + return parser diff --git a/submodules/v80-vitis-flow/resources/dcmac/hdl/axis_seg_to_unseg_converter.v b/submodules/v80-vitis-flow/resources/dcmac/hdl/axis_seg_to_unseg_converter.v new file mode 100644 index 00000000..0a4c1585 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/hdl/axis_seg_to_unseg_converter.v @@ -0,0 +1,5438 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright © 2015-2025 Advanced Micro Devices, Inc. All rights reserved. + +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the “Software”), +// to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +// IN THE SOFTWARE. +////////////////////////////////////////////////////////////////////////////// +// +// DO NOT MODIFY THIS FILE. +////////////////////////////////////////////////////////////////////////////// +// +// Company : Advanced Micro Devices +// +// Create Date : 13/02/2024 10:36:53 AM +// Design Name : AXIS segmented <=> unsegmented interface converter +// Module Name : axis_seg_and_unseg_converter +// Project Name : +// Target Devices : +// Tool Versions : +// Description : Segmented AXI stream <-> unsegmented AXI stream converter for DCMAC +// : Supported mode - Coupled MAC+PHY mode (FixedE) +// : Supported data rates - 100 or 200 or 400Gbps +// : Data width of each segment of segmented axis interface is considered as 128bits +// : Unsegmented AXIS interface configuration as below, +// : 100G - 1x256b @ >=450MHz, higher clock is needed to accomodate packet rate (considering 65Byte packets) +// : 200G - 1x1024b @391MHz, data width is doubled to accomodate packet rate (considering 65Byte packets) +// : 400G - 2x1024b @391MHz, two ports are used to accomodate packet rate (considering 129Byte packets) +// +// Revision : 1.00 - Initial version +// : 1.01 - Critical path optimization and design improvements +// : 1.02 - Added error transfer between seg & unseg interfaces( seg err <-> unseg tuser ) +// +// Additional Notes : +// : 1. Backpressure is not supported by DCMAC at the segmented interface of RX side. Data must be consumed +// : when the rx_tvalid signal is available. User need to consider required buffering at the input/output +// : of the seg to unseg converter. Overflow of the input buffer in the seg to unseg converter will lead +// : to packet loss and/or data corruption. To avoid this, input packets will be dropped when the packet +// : buffer of the seg to unseg converter becomes full(tail drop performed). This feature can be disabled +// : when using with other traffic masters which support back pressure. +// +// : 2. At the TX side of the DCMAC, packets should not be sent with broken Valid signal (seg_val should +// : not go low in between a SoP and EoP. seg_val deassertion should aligned with an EoP and seg_val +// : assertion should aligned with SoP). Violation of this leads to packet loss and corruption at the +// : DCMAC. To overcome this limitation and also to improve segment packing efficiency, packets are processed as a +// : block(of packets) and sent to DCMAC when tx_tready signal of DCMAC segmented is available. +// : This makes the unsegmented to segmented converter bulky and uses deep FIFOs aligned with the +// : block size used. For optimal performance, preferred block size is 512 +// +// : 3. For 100G mode, the 2x128 segments are mapped to 1x256 bit AXI Stream interface. To accomodate the Packet +// : rate, considering the worst case packet size of 65Bytes, the converter is designed to run at a +// : higher clock than the DCMAC segmented interface clock(>=450MHz is preferred, least minimum is 425 MHz). +// +// : 4. For 200G mode, the 4x128 segments are mapped to 1x1024 bit AXI Stream interface. Direct mapping of 4x128 +// : segments to 1x512 bit AXIS would need atleast 562MHz for the converter to accomodate the packet rate +// : considering the worst case packet size of 65Bytes. Timing closure would be difficult for such high clocks +// : and most of the AXIS based IPs would not support such high clocks. To accomodate the packet rate, +// : 4x128 segments are mapped to 1x1024 bit AXI stream. The converter can run at the same DCMAC clock of the +// : segmented interface +// +// : 5. For 400G operation 8x128 segments are mapped to 2x1024 bit AXI Stream interfaces to accomodate the packet +// : rate considering the worst case packet size of 129Bytes. Direct mapping of 8x128 segments to 1x1024 bit +// : AXIS would need atleast 654MHz for the converter. To overcome the similar limitations mentioned +// : for the 200G case, 8x128 segments are mapped to 2x1024 bit AXI Streams and the converter is designed to run +// : at the same DCMAC clock of the segmented interface(391MHz).The first packet received from the DCMAC +// : segmented interface is sent to the first AXIS port and next packet to the second AXIS port and so on +// : in a Round Robin fashion. At the unsegmented to segmented side, packets are taken from the AXIS ports based +// : on the availabily of packets and follow round robin arbitration. +// +// : 6. Array based mechanism is implemented for packing and unpacking of segments in the converter. The design +// : consumes considerable logic for the 200G and 400G configuration and also have timing closure challenges. +// +// : 7. Critical path optimizations done and timing improved for all the configurations (with the DCMAC example design). +// : however 400G & 200G configuration may have timing closure challenges when integrating with large designs. +// +// : 8. Debug logic and statistic counters are included in the converter but it is recommened to disable them for +// : synthesis/implementation to avoid timing violations. They were added only for simulation/verification purpose. +// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// User configuration defines; please refer IP documentation for more details + +`define data_rate_200 // data rate of DCMAC port (update the suffix as per the requirement; 100,200 or 400) +`define en_seg_to_unseg_cnv // Enable/disable segmented to unsegmented axi stream converter +`define en_unseg_to_seg_cnv // Enable/disable unsegmented to segmented axi stream converter +`define max_packet_size 9216 // Maximum packet size expeted/to be supported +`define max_pkt_size_above_1k // Comment off if max packet size is less than 1024Bytes +`define en_flow_control // Enable/Disable flow control at the seg to unseg converter. + // Enable if backpressure is not supported by the traffic source. Incomimg packets are dropped when + // downstream ports backpressures and buffers become full. Disable if backpressure is supported by + // the traffic master + +// Enabling bleow defines is not recommended (shall be enabled for simulation) + +//`define statistics_en // Enable Input & output port statistic (packet & byte counters) +//`define debug_en // Enable error checks in the design + +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// Do not change the below derived defines except "independant_clk" + +// derived Converter defines + +`define segment_width 128 // data width of each segment of segmented axis interface +`ifdef data_rate_100 + `define num_segments 2 // number of segments of input segmented axis interface + `define num_axis_ports 1 // number of ports of output unsegmented axis interface + `define unseg_axis_w 256 // data width of output unsegmented axis interface + `define pktarray_depth 4 // depth of the segment array used to unpack/pack the segments + `define independant_clk // if defined segmented and the unsegmented interface runs at different clocks. + // for applications other than DCMAC and data rate less then 100Gbps user can run the interfaces + // at the desired clock frequency, either single clock or dual clock as per the need. Same applies for + // 200G and 400G configurations also +`elsif data_rate_200 + `define num_segments 4 + `define en_port1 + `define num_axis_ports 1 + `define unseg_axis_w 1024 + `define pktarray_depth 16 +`elsif data_rate_400 + `define num_segments 8 + `define num_axis_ports 2 + `define en_port1 + `define en_port2 + `define en_port3 + `define en_axis1 + `define pktarray_depth 16 + `define unseg_axis_w 1024 +`else + `define invalid_config // only 100, 200 or 400 data rate with the above configurations allowed + // For other rates user can choose the nearest configuration and drive the clocks as needed + // to meet the data rate +`endif + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +`ifndef invalid_config + +module axis_seg_and_unseg_converter + ( + `ifdef independant_clk + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_unseg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_pktout, ASSOCIATED_RESET aresetn_axis_unseg_in" *) + input aclk_axis_unseg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_unseg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_unseg_in, + `endif + + `ifdef en_seg_to_unseg_cnv + // AXIS Segment to Unsegment converter ports + // Clock & Resets + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_rx_seg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET aresetn_rx_seg_in" *) + input aclk_rx_seg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_rx_seg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_rx_seg_in, + + // Input Segmented stream interface + // Port0 (segments 0 & 1) is active for all valid configurations + // Segment 0 input + input Seg2UnSegEna0_in, + input [`segment_width-1:0] Seg2UnSegDat0_in, + input Seg2UnSegSop0_in, + input Seg2UnSegEop0_in, + input Seg2UnSegErr0_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty0_in, + // Segment 1 input + input Seg2UnSegEna1_in, + input [`segment_width-1:0] Seg2UnSegDat1_in, + input Seg2UnSegSop1_in, + input Seg2UnSegEop1_in, + input Seg2UnSegErr1_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty1_in, + `ifdef en_port1 + // Segment 2 input + input Seg2UnSegEna2_in, + input [`segment_width-1:0] Seg2UnSegDat2_in, + input Seg2UnSegSop2_in, + input Seg2UnSegEop2_in, + input Seg2UnSegErr2_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty2_in, + // Segment 3 input + input Seg2UnSegEna3_in, + input [`segment_width-1:0] Seg2UnSegDat3_in, + input Seg2UnSegSop3_in, + input Seg2UnSegEop3_in, + input Seg2UnSegErr3_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty3_in, + `endif + `ifdef en_port2 + // Segment 4 input + input Seg2UnSegEna4_in, + input [`segment_width-1:0] Seg2UnSegDat4_in, + input Seg2UnSegSop4_in, + input Seg2UnSegEop4_in, + input Seg2UnSegErr4_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty4_in, + // Segment 5 input + input Seg2UnSegEna5_in, + input [`segment_width-1:0] Seg2UnSegDat5_in, + input Seg2UnSegSop5_in, + input Seg2UnSegEop5_in, + input Seg2UnSegErr5_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty5_in, + `endif + `ifdef en_port3 + // Segment 6 input + input Seg2UnSegEna6_in, + input [`segment_width-1:0] Seg2UnSegDat6_in, + input Seg2UnSegSop6_in, + input Seg2UnSegEop6_in, + input Seg2UnSegErr6_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty6_in, + // Segment 7 input + input Seg2UnSegEna7_in, + input [`segment_width-1:0] Seg2UnSegDat7_in, + input Seg2UnSegSop7_in, + input Seg2UnSegEop7_in, + input Seg2UnSegErr7_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty7_in, + `endif + input wire Seg2UnSeg_tvalid_in, + + // Packet output interface - Unsegmented AXI Stream + // AXIS-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TDATA" *) + output [`unseg_axis_w-1:0] m_axis0_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TKEEP" *) + output [(`unseg_axis_w/8)-1:0] m_axis0_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TLAST" *) + output m_axis0_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TVALID" *) + output m_axis0_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TUSER" *) + output m_axis0_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TREADY" *) + input m_axis0_tready, + + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TDATA" *) + output [`unseg_axis_w-1:0] m_axis1_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TKEEP" *) + output [(`unseg_axis_w/8)-1:0] m_axis1_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TLAST" *) + output m_axis1_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TVALID" *) + output m_axis1_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TUSER" *) + output m_axis1_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TREADY" *) + input m_axis1_tready, + `endif + + `ifdef en_flow_control + output wire seg2unseg_buff_full, + `else + output wire seg2unseg_inbuff_overflow, + output wire seg2unseg_inbuff_afull, + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + output wire [63: 0] stat_rx_p1_pkt_out_cnt, + output wire [63: 0] stat_rx_p1_err_pkt_out_cnt, + output wire [63: 0] stat_rx_p1_pkt_out_byte_cnt, + output wire [63: 0] stat_rx_p0_pkt_out_cnt, + output wire [63: 0] stat_rx_p0_err_pkt_out_cnt, + output wire [63: 0] stat_rx_p0_pkt_out_byte_cnt, + `endif + output wire [63: 0] stat_rx_total_pkt_in_cnt, + output wire [63: 0] stat_rx_total_err_pkt_in_cnt, + output wire [63: 0] stat_rx_total_pkt_in_byte_cnt, + output wire [63: 0] stat_rx_total_pkt_out_cnt, + output wire [63: 0] stat_rx_total_err_pkt_out_cnt, + output wire [63: 0] stat_rx_total_pkt_out_byte_cnt, + `endif + `endif + + `ifdef debug_en + output wire seg2unseg_broken_packet_out_error, + output wire seg2unseg_rx_packet_error, + `endif + + `ifdef en_unseg_to_seg_cnv + // AXIS Segment to Unsegment converter ports + + // Clock & Resets + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_tx_seg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET aresetn_tx_seg_in" *) + input aclk_tx_seg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_tx_seg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_tx_seg_in, + + // Output Segmented stream interface + // Port0 (segments 0 & 1) is active for all valid configurations + // Segment 0 output + output Unseg2SegEna0_out, + output [`segment_width-1:0] Unseg2SegDat0_out, + output Unseg2SegSop0_out, + output Unseg2SegEop0_out, + output Unseg2SegErr0_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty0_out, + // Segment 1 output + output Unseg2SegEna1_out, + output [`segment_width-1:0] Unseg2SegDat1_out, + output Unseg2SegSop1_out, + output Unseg2SegEop1_out, + output Unseg2SegErr1_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty1_out, + `ifdef en_port1 + // Segment 2 output + output Unseg2SegEna2_out, + output [`segment_width-1:0] Unseg2SegDat2_out, + output Unseg2SegSop2_out, + output Unseg2SegEop2_out, + output Unseg2SegErr2_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty2_out, + // Segment 3 output + output Unseg2SegEna3_out, + output [`segment_width-1:0] Unseg2SegDat3_out, + output Unseg2SegSop3_out, + output Unseg2SegEop3_out, + output Unseg2SegErr3_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty3_out, + `endif + `ifdef en_port2 + // Segment 4 output + output Unseg2SegEna4_out, + output [`segment_width-1:0] Unseg2SegDat4_out, + output Unseg2SegSop4_out, + output Unseg2SegEop4_out, + output Unseg2SegErr4_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty4_out, + // Segment 5 output + output Unseg2SegEna5_out, + output [`segment_width-1:0] Unseg2SegDat5_out, + output Unseg2SegSop5_out, + output Unseg2SegEop5_out, + output Unseg2SegErr5_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty5_out, + `endif + `ifdef en_port3 + // Segment 6 output + output Unseg2SegEna6_out, + output [`segment_width-1:0] Unseg2SegDat6_out, + output Unseg2SegSop6_out, + output Unseg2SegEop6_out, + output Unseg2SegErr6_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty6_out, + // Segment 7 output + output Unseg2SegEna7_out, + output [`segment_width-1:0] Unseg2SegDat7_out, + output Unseg2SegSop7_out, + output Unseg2SegEop7_out, + output Unseg2SegErr7_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty7_out, + `endif + + // Packet input interface - Unsegmented AXI Stream + // AXI-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TDATA" *) + input [`unseg_axis_w-1:0] s_axis0_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TKEEP" *) + input [(`unseg_axis_w/8)-1:0] s_axis0_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TLAST" *) + input s_axis0_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TVALID" *) + input s_axis0_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TUSER" *) + input s_axis0_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TREADY" *) + output s_axis0_tready, + + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TDATA" *) + input [`unseg_axis_w-1:0] s_axis1_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TKEEP" *) + input [(`unseg_axis_w/8)-1:0] s_axis1_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TLAST" *) + input s_axis1_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TVALID" *) + input s_axis1_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TUSER" *) + input s_axis1_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TREADY" *) + output s_axis1_tready, + `endif + + `ifdef debug_en + output wire unseg2seg_missing_sop_error, + output wire unseg2seg_broken_pkt_out_error, + output wire unseg2seg_broken_pkt_in_error, + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + output wire [63: 0] stat_tx_p1_pkt_in_cnt, + output wire [63: 0] stat_tx_p1_err_pkt_in_cnt, + output wire [63: 0] stat_tx_p1_pkt_in_byte_cnt, + output wire [63: 0] stat_tx_p0_pkt_in_cnt, + output wire [63: 0] stat_tx_p0_err_pkt_in_cnt, + output wire [63: 0] stat_tx_p0_pkt_in_byte_cnt, + `endif + output wire [63: 0] stat_tx_total_pkt_in_cnt, + output wire [63: 0] stat_tx_total_err_pkt_in_cnt, + output wire [63: 0] stat_tx_total_pkt_in_byte_cnt, + output wire [63: 0] stat_tx_total_pkt_out_cnt, + output wire [63: 0] stat_tx_total_err_pkt_out_cnt, + output wire [63: 0] stat_tx_total_pkt_out_byte_cnt, + `endif + + input wire Unseg2Seg_tready_in, + output wire Unseg2Seg_tvalid_out + `endif + ); + +//----------------------------------------------------------------------------------------------------------------------- + +//------------------- AXIS Segment to Unsegment Converter + +`ifdef en_seg_to_unseg_cnv + +axis_seg_to_unseg_converter u_axis_seg_to_unseg_converter + ( + // Clock & Resets + .aclk_axis_seg_in(aclk_rx_seg_in), + .aresetn_axis_seg_in(aresetn_rx_seg_in), + `ifdef independant_clk + .aclk_axis_unseg_in(aclk_axis_unseg_in), + .aresetn_axis_unseg_in(aresetn_axis_unseg_in), + `endif + // Segmented interface + // Port0 (segments 0 & 1) is active for all valid configurations + // Segment 0 input + .Seg2UnSegEna0_in(Seg2UnSegEna0_in), + .Seg2UnSegDat0_in(Seg2UnSegDat0_in), + .Seg2UnSegSop0_in(Seg2UnSegSop0_in), + .Seg2UnSegEop0_in(Seg2UnSegEop0_in), + .Seg2UnSegErr0_in(Seg2UnSegErr0_in), + .Seg2UnSegMty0_in(Seg2UnSegMty0_in), + // Segment 1 input + .Seg2UnSegEna1_in(Seg2UnSegEna1_in), + .Seg2UnSegDat1_in(Seg2UnSegDat1_in), + .Seg2UnSegSop1_in(Seg2UnSegSop1_in), + .Seg2UnSegEop1_in(Seg2UnSegEop1_in), + .Seg2UnSegErr1_in(Seg2UnSegErr1_in), + .Seg2UnSegMty1_in(Seg2UnSegMty1_in), + `ifdef en_port1 + // Segment 2 input + .Seg2UnSegEna2_in(Seg2UnSegEna2_in), + .Seg2UnSegDat2_in(Seg2UnSegDat2_in), + .Seg2UnSegSop2_in(Seg2UnSegSop2_in), + .Seg2UnSegEop2_in(Seg2UnSegEop2_in), + .Seg2UnSegErr2_in(Seg2UnSegErr2_in), + .Seg2UnSegMty2_in(Seg2UnSegMty2_in), + // Segment 3 input + .Seg2UnSegEna3_in(Seg2UnSegEna3_in), + .Seg2UnSegDat3_in(Seg2UnSegDat3_in), + .Seg2UnSegSop3_in(Seg2UnSegSop3_in), + .Seg2UnSegEop3_in(Seg2UnSegEop3_in), + .Seg2UnSegErr3_in(Seg2UnSegErr3_in), + .Seg2UnSegMty3_in(Seg2UnSegMty3_in), + `endif + `ifdef en_port2 + // Segment 4 input + .Seg2UnSegEna4_in(Seg2UnSegEna4_in), + .Seg2UnSegDat4_in(Seg2UnSegDat4_in), + .Seg2UnSegSop4_in(Seg2UnSegSop4_in), + .Seg2UnSegEop4_in(Seg2UnSegEop4_in), + .Seg2UnSegErr4_in(Seg2UnSegErr4_in), + .Seg2UnSegMty4_in(Seg2UnSegMty4_in), + // Segment 5 input + .Seg2UnSegEna5_in(Seg2UnSegEna5_in), + .Seg2UnSegDat5_in(Seg2UnSegDat5_in), + .Seg2UnSegSop5_in(Seg2UnSegSop5_in), + .Seg2UnSegEop5_in(Seg2UnSegEop5_in), + .Seg2UnSegErr5_in(Seg2UnSegErr5_in), + .Seg2UnSegMty5_in(Seg2UnSegMty5_in), + `endif + `ifdef en_port3 + // Segment 6 input + .Seg2UnSegEna6_in(Seg2UnSegEna6_in), + .Seg2UnSegDat6_in(Seg2UnSegDat6_in), + .Seg2UnSegSop6_in(Seg2UnSegSop6_in), + .Seg2UnSegEop6_in(Seg2UnSegEop6_in), + .Seg2UnSegErr6_in(Seg2UnSegErr6_in), + .Seg2UnSegMty6_in(Seg2UnSegMty6_in), + // Segment 7 input + .Seg2UnSegEna7_in(Seg2UnSegEna7_in), + .Seg2UnSegDat7_in(Seg2UnSegDat7_in), + .Seg2UnSegSop7_in(Seg2UnSegSop7_in), + .Seg2UnSegEop7_in(Seg2UnSegEop7_in), + .Seg2UnSegErr7_in(Seg2UnSegErr7_in), + .Seg2UnSegMty7_in(Seg2UnSegMty7_in), + `endif + // Packet output interface - Unsegmented AXI Stream + // AXI-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + .m_axis0_tdata(m_axis0_tdata), + .m_axis0_tkeep(m_axis0_tkeep), + .m_axis0_tlast(m_axis0_tlast), + .m_axis0_tvalid(m_axis0_tvalid), + .m_axis0_tuser(m_axis0_tuser), + .m_axis0_tready(m_axis0_tready), + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + .m_axis1_tdata(m_axis1_tdata), + .m_axis1_tkeep(m_axis1_tkeep), + .m_axis1_tlast(m_axis1_tlast), + .m_axis1_tvalid(m_axis1_tvalid), + .m_axis1_tuser(m_axis1_tuser), + .m_axis1_tready(m_axis1_tready), + `endif + + `ifdef en_flow_control + .buff_full(seg2unseg_buff_full), + `else + .inbuff_overflow(seg2unseg_inbuff_overflow), + .inbuff_afull(seg2unseg_inbuff_afull), + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + .p1_pkt_out_cnt(stat_rx_p1_pkt_out_cnt), + .p1_err_pkt_out_cnt(stat_rx_p1_err_pkt_out_cnt), + .p1_pkt_out_byte_cnt(stat_rx_p1_pkt_out_byte_cnt), + .p0_pkt_out_cnt(stat_rx_p0_pkt_out_cnt), + .p0_err_pkt_out_cnt(stat_rx_p0_err_pkt_out_cnt), + .p0_pkt_out_byte_cnt(stat_rx_p0_pkt_out_byte_cnt), + `endif + .total_pkt_in_cnt(stat_rx_total_pkt_in_cnt), + .total_err_pkt_in_cnt(stat_rx_total_err_pkt_in_cnt), + .total_pkt_in_byte_cnt(stat_rx_total_pkt_in_byte_cnt), + .total_pkt_out_cnt(stat_rx_total_pkt_out_cnt), + .total_err_pkt_out_cnt(stat_rx_total_err_pkt_out_cnt), + .total_pkt_out_byte_cnt(stat_rx_total_pkt_out_byte_cnt), + `endif + + `ifdef debug_en + .error_broken_packet_out(seg2unseg_broken_packet_out_error), + .seg_rx_err_packet(seg2unseg_rx_packet_error), + `endif + + .rx_axis_tvalid_i(Seg2UnSeg_tvalid_in) + ); + `endif + +`ifdef en_unseg_to_seg_cnv + +axis_unseg_to_seg_converter u_axis_unseg_to_seg_converter + ( + // AXIS Segment to Unsegment converter ports + // Clock & Resets + .aclk_axis_seg_in(aclk_tx_seg_in), + .aresetn_axis_seg_in(aresetn_tx_seg_in), + `ifdef independant_clk + .aclk_axis_unseg_in(aclk_axis_unseg_in), + .aresetn_axis_unseg_in(aresetn_axis_unseg_in), + `endif + // Segmented interface + // port0 is active for all valid configurations + // Segment 0 input + .Unseg2SegEna0_out(Unseg2SegEna0_out), + .Unseg2SegDat0_out(Unseg2SegDat0_out), + .Unseg2SegSop0_out(Unseg2SegSop0_out), + .Unseg2SegEop0_out(Unseg2SegEop0_out), + .Unseg2SegErr0_out(Unseg2SegErr0_out), + .Unseg2SegMty0_out(Unseg2SegMty0_out), + // Segment 1 input + .Unseg2SegEna1_out(Unseg2SegEna1_out), + .Unseg2SegDat1_out(Unseg2SegDat1_out), + .Unseg2SegSop1_out(Unseg2SegSop1_out), + .Unseg2SegEop1_out(Unseg2SegEop1_out), + .Unseg2SegErr1_out(Unseg2SegErr1_out), + .Unseg2SegMty1_out(Unseg2SegMty1_out), + `ifdef en_port1 + // Segment 2 input + .Unseg2SegEna2_out(Unseg2SegEna2_out), + .Unseg2SegDat2_out(Unseg2SegDat2_out), + .Unseg2SegSop2_out(Unseg2SegSop2_out), + .Unseg2SegEop2_out(Unseg2SegEop2_out), + .Unseg2SegErr2_out(Unseg2SegErr2_out), + .Unseg2SegMty2_out(Unseg2SegMty2_out), + // Segment 3 input + .Unseg2SegEna3_out(Unseg2SegEna3_out), + .Unseg2SegDat3_out(Unseg2SegDat3_out), + .Unseg2SegSop3_out(Unseg2SegSop3_out), + .Unseg2SegEop3_out(Unseg2SegEop3_out), + .Unseg2SegErr3_out(Unseg2SegErr3_out), + .Unseg2SegMty3_out(Unseg2SegMty3_out), + `endif + `ifdef en_port2 + // Segment 4 input + .Unseg2SegEna4_out(Unseg2SegEna4_out), + .Unseg2SegDat4_out(Unseg2SegDat4_out), + .Unseg2SegSop4_out(Unseg2SegSop4_out), + .Unseg2SegEop4_out(Unseg2SegEop4_out), + .Unseg2SegErr4_out(Unseg2SegErr4_out), + .Unseg2SegMty4_out(Unseg2SegMty4_out), + // Segment 5 input + .Unseg2SegEna5_out(Unseg2SegEna5_out), + .Unseg2SegDat5_out(Unseg2SegDat5_out), + .Unseg2SegSop5_out(Unseg2SegSop5_out), + .Unseg2SegEop5_out(Unseg2SegEop5_out), + .Unseg2SegErr5_out(Unseg2SegErr5_out), + .Unseg2SegMty5_out(Unseg2SegMty5_out), + `endif + `ifdef en_port3 + // Segment 6 input + .Unseg2SegEna6_out(Unseg2SegEna6_out), + .Unseg2SegDat6_out(Unseg2SegDat6_out), + .Unseg2SegSop6_out(Unseg2SegSop6_out), + .Unseg2SegEop6_out(Unseg2SegEop6_out), + .Unseg2SegErr6_out(Unseg2SegErr6_out), + .Unseg2SegMty6_out(Unseg2SegMty6_out), + // Segment 7 input + .Unseg2SegEna7_out(Unseg2SegEna7_out), + .Unseg2SegDat7_out(Unseg2SegDat7_out), + .Unseg2SegSop7_out(Unseg2SegSop7_out), + .Unseg2SegEop7_out(Unseg2SegEop7_out), + .Unseg2SegErr7_out(Unseg2SegErr7_out), + .Unseg2SegMty7_out(Unseg2SegMty7_out), + `endif + + // Packet input interface - Unsegmented AXI Stream + // AXI-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + .s_axis0_tdata(s_axis0_tdata), + .s_axis0_tkeep(s_axis0_tkeep), + .s_axis0_tlast(s_axis0_tlast), + .s_axis0_tvalid(s_axis0_tvalid), + .s_axis0_tuser(s_axis0_tuser), + .s_axis0_tready(s_axis0_tready), + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + .s_axis1_tdata(s_axis1_tdata), + .s_axis1_tkeep(s_axis1_tkeep), + .s_axis1_tlast(s_axis1_tlast), + .s_axis1_tvalid(s_axis1_tvalid), + .s_axis1_tuser(s_axis1_tuser), + .s_axis1_tready(s_axis1_tready), + `endif + + `ifdef debug_en + .error_missing_sop(unseg2seg_missing_sop_error), + .error_broken_pkt_out(unseg2seg_broken_pkt_out_error), + .error_broken_pkt_in(unseg2seg_broken_pkt_in_error), + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + .p1_pkt_in_cnt(stat_tx_p1_pkt_in_cnt), + .p1_err_pkt_in_cnt(stat_tx_p1_err_pkt_in_cnt), + .p1_pkt_in_byte_cnt(stat_tx_p1_pkt_in_byte_cnt), + .p0_pkt_in_cnt(stat_tx_p0_pkt_in_cnt), + .p0_err_pkt_in_cnt(stat_tx_p0_err_pkt_in_cnt), + .p0_pkt_in_byte_cnt(stat_tx_p0_pkt_in_byte_cnt), + `endif + .total_pkt_in_cnt(stat_tx_total_pkt_in_cnt), + .total_err_pkt_in_cnt(stat_tx_total_err_pkt_in_cnt), + .total_pkt_in_byte_cnt(stat_tx_total_pkt_in_byte_cnt), + .total_pkt_out_cnt(stat_tx_total_pkt_out_cnt), + .total_err_pkt_out_cnt(stat_tx_total_err_pkt_out_cnt), + .total_pkt_out_byte_cnt(stat_tx_total_pkt_out_byte_cnt), + `endif + + .tx_axis_tready_in(Unseg2Seg_tready_in), + .tx_axis_tvalid_out(Unseg2Seg_tvalid_out) + ); + +`endif + +endmodule + +`endif + +//######################################################################################################################## + +//------------------------------------ AXIS Segmented to Unsegmented Stream Converter ------------------------------------ + +module axis_seg_to_unseg_converter + ( + // Clock & Resets + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_seg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET aresetn_axis_seg_in" *) + input aclk_axis_seg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_seg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_seg_in, + `ifdef independant_clk + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_unseg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_pktout, ASSOCIATED_RESET aresetn_axis_unseg_in" *) + input aclk_axis_unseg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_unseg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_unseg_in, + `endif + // Segmented interface + // port0 is active for all valid configurations + // Segment 0 input + input Seg2UnSegEna0_in, + input [`segment_width-1:0] Seg2UnSegDat0_in, + input Seg2UnSegSop0_in, + input Seg2UnSegEop0_in, + input Seg2UnSegErr0_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty0_in, + // Segment 1 input + input Seg2UnSegEna1_in, + input [`segment_width-1:0] Seg2UnSegDat1_in, + input Seg2UnSegSop1_in, + input Seg2UnSegEop1_in, + input Seg2UnSegErr1_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty1_in, + `ifdef en_port1 + // Segment 2 input + input Seg2UnSegEna2_in, + input [`segment_width-1:0] Seg2UnSegDat2_in, + input Seg2UnSegSop2_in, + input Seg2UnSegEop2_in, + input Seg2UnSegErr2_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty2_in, + // Segment 3 input + input Seg2UnSegEna3_in, + input [`segment_width-1:0] Seg2UnSegDat3_in, + input Seg2UnSegSop3_in, + input Seg2UnSegEop3_in, + input Seg2UnSegErr3_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty3_in, + `endif + `ifdef en_port2 + // Segment 4 input + input Seg2UnSegEna4_in, + input [`segment_width-1:0] Seg2UnSegDat4_in, + input Seg2UnSegSop4_in, + input Seg2UnSegEop4_in, + input Seg2UnSegErr4_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty4_in, + // Segment 5 input + input Seg2UnSegEna5_in, + input [`segment_width-1:0] Seg2UnSegDat5_in, + input Seg2UnSegSop5_in, + input Seg2UnSegEop5_in, + input Seg2UnSegErr5_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty5_in, + `endif + `ifdef en_port3 + // Segment 6 input + input Seg2UnSegEna6_in, + input [`segment_width-1:0] Seg2UnSegDat6_in, + input Seg2UnSegSop6_in, + input Seg2UnSegEop6_in, + input Seg2UnSegErr6_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty6_in, + // Segment 7 input + input Seg2UnSegEna7_in, + input [`segment_width-1:0] Seg2UnSegDat7_in, + input Seg2UnSegSop7_in, + input Seg2UnSegEop7_in, + input Seg2UnSegErr7_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty7_in, + `endif + + // Packet output interface - Unsegmented AXI Stream + // AXI-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TDATA" *) + output [`unseg_axis_w-1:0] m_axis0_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TKEEP" *) + output [(`unseg_axis_w/8)-1:0] m_axis0_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TLAST" *) + output m_axis0_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TVALID" *) + output m_axis0_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TUSER" *) + output m_axis0_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TREADY" *) + input m_axis0_tready, + + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TDATA" *) + output [`unseg_axis_w-1:0] m_axis1_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TKEEP" *) + output [(`unseg_axis_w/8)-1:0] m_axis1_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TLAST" *) + output m_axis1_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TVALID" *) + output m_axis1_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TUSER" *) + output m_axis1_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TREADY" *) + input m_axis1_tready, + `endif + + `ifdef en_flow_control + output wire buff_full, + `else + output wire inbuff_overflow, + output wire inbuff_afull, + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + output wire [63: 0] p1_pkt_out_cnt, + output wire [63: 0] p1_err_pkt_out_cnt, + output wire [63: 0] p1_pkt_out_byte_cnt, + output wire [63: 0] p0_pkt_out_cnt, + output wire [63: 0] p0_err_pkt_out_cnt, + output wire [63: 0] p0_pkt_out_byte_cnt, + `endif + output wire [63: 0] total_pkt_in_cnt, + output wire [63: 0] total_err_pkt_in_cnt, + output wire [63: 0] total_pkt_in_byte_cnt, + output wire [63: 0] total_pkt_out_cnt, + output wire [63: 0] total_err_pkt_out_cnt, + output wire [63: 0] total_pkt_out_byte_cnt, + `endif + + `ifdef debug_en + output wire error_broken_packet_out, + output reg seg_rx_err_packet, + `endif + + input wire rx_axis_tvalid_i + ); + +//----------------------------------------------------------------------------------------------------------------------- + +localparam P_MARK_DEBUG = "false"; + +// Derive local parameters + +localparam seg_mty_w = $clog2(`segment_width/8); +localparam pkt_array_depth = `pktarray_depth; +localparam local_buff_depth = 32; +localparam max_pkt_burst_size = $ceil(`max_packet_size/((`pktarray_depth/2)*(`segment_width/8))); +localparam max_pkt_burst_size_p2 = $ceil($clog2(`max_packet_size)); + +`ifdef max_pkt_size_above_1k + localparam pktarry_buff_depth = $ceil((2**(max_pkt_burst_size_p2+1))/((`pktarray_depth/2)*(`segment_width/8))); + localparam pktarry_buff_pfull_thresh = pktarry_buff_depth - max_pkt_burst_size; +`else + localparam pktarry_buff_depth = 32; + localparam pktarry_buff_pfull_thresh = pktarry_buff_depth-7; +`endif + +localparam in_buff_depth = pktarry_buff_depth/2; +localparam out_buff_depth = pktarry_buff_depth*4; +localparam out_buff_pfull_thresh = out_buff_depth - max_pkt_burst_size; + +//----------------------------------------------------------------------------------------------------------------------- + +wire [`num_segments-1:0] seg2unseg_val; +wire [`num_segments-1:0] seg2unseg_sop; +wire [`num_segments-1:0] seg2unseg_eop; +wire [`num_segments-1:0] seg2unseg_err; +wire [`segment_width-1:0] seg2unseg_dat [`num_segments-1:0]; +wire [seg_mty_w-1:0] seg2unseg_mty [`num_segments-1:0]; + +assign seg2unseg_val[0] = Seg2UnSegEna0_in & rx_axis_tvalid_i; assign seg2unseg_sop[0] = Seg2UnSegSop0_in; assign seg2unseg_eop[0] = Seg2UnSegEop0_in; assign seg2unseg_err[0] = Seg2UnSegErr0_in; assign seg2unseg_dat[0] = Seg2UnSegDat0_in; assign seg2unseg_mty[0] = Seg2UnSegMty0_in; +assign seg2unseg_val[1] = Seg2UnSegEna1_in & rx_axis_tvalid_i; assign seg2unseg_sop[1] = Seg2UnSegSop1_in; assign seg2unseg_eop[1] = Seg2UnSegEop1_in; assign seg2unseg_err[1] = Seg2UnSegErr1_in; assign seg2unseg_dat[1] = Seg2UnSegDat1_in; assign seg2unseg_mty[1] = Seg2UnSegMty1_in; +`ifdef en_port1 +assign seg2unseg_val[2] = Seg2UnSegEna2_in & rx_axis_tvalid_i; assign seg2unseg_sop[2] = Seg2UnSegSop2_in; assign seg2unseg_eop[2] = Seg2UnSegEop2_in; assign seg2unseg_err[2] = Seg2UnSegErr2_in; assign seg2unseg_dat[2] = Seg2UnSegDat2_in; assign seg2unseg_mty[2] = Seg2UnSegMty2_in; +assign seg2unseg_val[3] = Seg2UnSegEna3_in & rx_axis_tvalid_i; assign seg2unseg_sop[3] = Seg2UnSegSop3_in; assign seg2unseg_eop[3] = Seg2UnSegEop3_in; assign seg2unseg_err[3] = Seg2UnSegErr3_in; assign seg2unseg_dat[3] = Seg2UnSegDat3_in; assign seg2unseg_mty[3] = Seg2UnSegMty3_in; +`endif +`ifdef en_port2 +assign seg2unseg_val[4] = Seg2UnSegEna4_in & rx_axis_tvalid_i; assign seg2unseg_sop[4] = Seg2UnSegSop4_in; assign seg2unseg_eop[4] = Seg2UnSegEop4_in; assign seg2unseg_err[4] = Seg2UnSegErr4_in; assign seg2unseg_dat[4] = Seg2UnSegDat4_in; assign seg2unseg_mty[4] = Seg2UnSegMty4_in; +assign seg2unseg_val[5] = Seg2UnSegEna5_in & rx_axis_tvalid_i; assign seg2unseg_sop[5] = Seg2UnSegSop5_in; assign seg2unseg_eop[5] = Seg2UnSegEop5_in; assign seg2unseg_err[5] = Seg2UnSegErr5_in; assign seg2unseg_dat[5] = Seg2UnSegDat5_in; assign seg2unseg_mty[5] = Seg2UnSegMty5_in; +`endif +`ifdef en_port3 +assign seg2unseg_val[6] = Seg2UnSegEna6_in & rx_axis_tvalid_i; assign seg2unseg_sop[6] = Seg2UnSegSop6_in; assign seg2unseg_eop[6] = Seg2UnSegEop6_in; assign seg2unseg_err[6] = Seg2UnSegErr6_in; assign seg2unseg_dat[6] = Seg2UnSegDat6_in; assign seg2unseg_mty[6] = Seg2UnSegMty6_in; +assign seg2unseg_val[7] = Seg2UnSegEna7_in & rx_axis_tvalid_i; assign seg2unseg_sop[7] = Seg2UnSegSop7_in; assign seg2unseg_eop[7] = Seg2UnSegEop7_in; assign seg2unseg_err[7] = Seg2UnSegErr7_in; assign seg2unseg_dat[7] = Seg2UnSegDat7_in; assign seg2unseg_mty[7] = Seg2UnSegMty7_in; +`endif + +wire aclk_axis_unseg; +wire aresetn_axis_unseg; + +`ifdef independant_clk + assign aclk_axis_unseg = aclk_axis_unseg_in; + assign aresetn_axis_unseg = aresetn_axis_unseg_in; +`else + assign aclk_axis_unseg = aclk_axis_seg_in; + assign aresetn_axis_unseg = aresetn_axis_seg_in; +`endif + +`ifdef debug_en + + always @ (posedge aclk_axis_unseg) begin + seg_rx_err_packet <= |(seg2unseg_err & seg2unseg_val); + end + +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Input buffer + +reg [`num_segments-1:0] seg2unseg_val_1; +reg [`num_segments-1:0] seg2unseg_sop_1; +reg [`num_segments-1:0] seg2unseg_eop_1; +reg [`num_segments-1:0] seg2unseg_err_1; +reg [`segment_width-1:0] seg2unseg_dat_1 [`num_segments-1:0]; +reg [seg_mty_w-1:0] seg2unseg_mty_1 [`num_segments-1:0]; + +wire [`num_segments-1:0] seg2unseg_val_c; +wire [`num_segments-1:0] seg2unseg_sop_c; +wire [`num_segments-1:0] seg2unseg_eop_c; +wire [`num_segments-1:0] seg2unseg_err_c; +wire [(`segment_width*`num_segments)-1:0] seg2unseg_dat_c; +wire [(seg_mty_w*`num_segments)-1:0] seg2unseg_mty_c; + +genvar a0; +generate + for (a0=0; a0<`num_segments; a0=a0+1) begin + assign seg2unseg_val_c[a0] = seg2unseg_val[a0]; + assign seg2unseg_sop_c[a0] = seg2unseg_sop[a0]; + assign seg2unseg_eop_c[a0] = seg2unseg_eop[a0]; + assign seg2unseg_err_c[a0] = seg2unseg_err[a0]; + assign seg2unseg_dat_c[((a0+1)*`segment_width)-1:a0*`segment_width] = seg2unseg_dat[a0]; + assign seg2unseg_mty_c[((a0+1)*seg_mty_w)-1:a0*seg_mty_w] = seg2unseg_mty[a0]; + end +endgenerate + +wire wr_rst_busy; +wire rd_rst_busy; +wire seg_in_aempty; +wire seg_in_empty; +wire data_valid; +wire seg_inbuff_afull; +wire seg_inbuff_overflow; + +wire ports_not_rdy; +wire [`num_axis_ports-1:0] port_unseg_out_pfull; + +`ifdef independant_clk // Input segmented intreface stream clock domain to unsegmented axis clock domain + +wire [`num_segments-1:0] seg2unseg_val_cdc; +wire [`num_segments-1:0] seg2unseg_sop_cdc; +wire [`num_segments-1:0] seg2unseg_eop_cdc; +wire [`num_segments-1:0] seg2unseg_err_cdc; +wire [(`segment_width*`num_segments)-1:0] seg2unseg_dat_cdc; +wire [(seg_mty_w*`num_segments)-1:0] seg2unseg_mty_cdc; + +xpm_fifo_async #( + .CASCADE_HEIGHT(0), + .CDC_SYNC_STAGES(3), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(2), + .FIFO_WRITE_DEPTH(in_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(in_buff_depth-5), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH((`segment_width+seg_mty_w+4)*`num_segments), + .READ_MODE("std"), + .RELATED_CLOCKS(0), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("1009"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH((`segment_width+seg_mty_w+4)*`num_segments), + .WR_DATA_COUNT_WIDTH(1) + ) +xpm_fifo_async_seg_in ( + .almost_empty(seg_in_aempty), + .almost_full(seg_inbuff_afull), + .data_valid(data_valid), + .dbiterr(), + .dout({seg2unseg_val_cdc,seg2unseg_sop_cdc,seg2unseg_eop_cdc,seg2unseg_err_cdc,seg2unseg_mty_cdc,seg2unseg_dat_cdc}), + .empty(seg_in_empty), + .full(), + .overflow(seg_inbuff_overflow), + .prog_empty(), + .prog_full(), + .rd_data_count(), + .rd_rst_busy(rd_rst_busy), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(wr_rst_busy), + .din({seg2unseg_val_c,seg2unseg_sop_c,seg2unseg_eop_c,seg2unseg_err_c,seg2unseg_mty_c,seg2unseg_dat_c}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_clk(aclk_axis_unseg), + `ifdef en_flow_control + .rd_en(!seg_in_empty & !rd_rst_busy), + `else + .rd_en(!ports_not_rdy & !seg_in_empty & !rd_rst_busy), + `endif + .rst(!aresetn_axis_seg_in), + .sleep(1'b0), + .wr_clk(aclk_axis_seg_in), + .wr_en(|seg2unseg_val_c & !wr_rst_busy) + ); + +genvar i; +generate + for (i=0; i<`num_segments; i=i+1) begin + always @ (posedge aclk_axis_unseg) begin + seg2unseg_val_1[i] <= seg2unseg_val_cdc[i] & data_valid; + seg2unseg_sop_1[i] <= seg2unseg_sop_cdc[i]; + seg2unseg_eop_1[i] <= seg2unseg_eop_cdc[i]; + seg2unseg_err_1[i] <= seg2unseg_err_cdc[i]; + seg2unseg_dat_1[i] <= seg2unseg_dat_cdc[((i+1)*`segment_width)-1:i*`segment_width]; + seg2unseg_mty_1[i] <= seg2unseg_mty_cdc[((i+1)*seg_mty_w)-1:i*seg_mty_w]; + end + end +endgenerate + +`else // Input segmented stream intreface and unsegmented axis interface runs at same clock domain + +wire [`num_segments-1:0] seg2unseg_val_ibuf; +wire [`num_segments-1:0] seg2unseg_sop_ibuf; +wire [`num_segments-1:0] seg2unseg_eop_ibuf; +wire [`num_segments-1:0] seg2unseg_err_ibuf; +wire [(`segment_width*`num_segments)-1:0] seg2unseg_dat_ibuf; +wire [(seg_mty_w*`num_segments)-1:0] seg2unseg_mty_ibuf; + +xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(2), + .FIFO_WRITE_DEPTH(in_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(in_buff_depth-5), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH((`segment_width+seg_mty_w+4)*`num_segments), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("1009"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH((`segment_width+seg_mty_w+4)*`num_segments), + .WR_DATA_COUNT_WIDTH(1) + ) +xpm_fifo_sync_seg_in ( + .almost_empty(seg_in_aempty), + .almost_full(seg_inbuff_afull), + .data_valid(data_valid), + .dbiterr(), + .dout({seg2unseg_val_ibuf,seg2unseg_sop_ibuf,seg2unseg_eop_ibuf,seg2unseg_err_ibuf,seg2unseg_mty_ibuf,seg2unseg_dat_ibuf}), + .empty(seg_in_empty), + .full(), + .overflow(seg_inbuff_overflow), + .prog_empty(), + .prog_full(), + .rd_data_count(), + .rd_rst_busy(rd_rst_busy), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(wr_rst_busy), + .din({seg2unseg_val_c,seg2unseg_sop_c,seg2unseg_eop_c,seg2unseg_err_c,seg2unseg_mty_c,seg2unseg_dat_c}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + `ifdef en_flow_control + .rd_en(!seg_in_empty & !rd_rst_busy), + `else + .rd_en(!ports_not_rdy & !seg_in_empty & !rd_rst_busy), + `endif + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(|seg2unseg_val_c & !wr_rst_busy) +); + +genvar j; +generate + for (j=0; j < `num_segments; j = j+1) begin + always @ (posedge aclk_axis_unseg) begin + seg2unseg_val_1[j] <= seg2unseg_val_ibuf[j] & data_valid; + seg2unseg_sop_1[j] <= seg2unseg_sop_ibuf[j]; + seg2unseg_eop_1[j] <= seg2unseg_eop_ibuf[j]; + seg2unseg_err_1[j] <= seg2unseg_err_ibuf[j]; + seg2unseg_dat_1[j] <= seg2unseg_dat_ibuf[((j+1)*`segment_width)-1:j*`segment_width]; + seg2unseg_mty_1[j] <= seg2unseg_mty_ibuf[((j+1)*seg_mty_w)-1:j*seg_mty_w]; + end + end +endgenerate + +`endif + +assign inbuff_overflow = seg_inbuff_overflow; +assign inbuff_afull = seg_inbuff_afull; + +//----------------------------------------------------------------------------------------------------------------------- + +// Arbitrate packets to different channels based on number of output axis ports (applicable for 400G with 2 AXIS ports) + +reg [`segment_width-1:0] pkt_data [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [seg_mty_w-1:0] pkt_mty [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [`num_segments-1:0] pkt_val [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_eop [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_err [`num_axis_ports-1:0]; + +`ifdef data_rate_400 // two output AXI stream ports available for 400G + +genvar k, l; +generate +for (k=0; k < `num_axis_ports; k = k+1) begin + for(l=0; l < `num_segments; l = l+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_data [k][l] <= seg2unseg_dat_1[l]; + pkt_mty [k][l] <= seg2unseg_mty_1[l]; + pkt_eop [k][l] <= seg2unseg_eop_1[l]; + pkt_err [k][l] <= seg2unseg_err_1[l]; + end + end +end +endgenerate + +// Probe output AXI ports (after power ON / system reset), to initialize the port pointer for port arbiter + +reg [12:0] cnt_port_init; +reg port_init_q, port_init_qq; +wire port_init_rp; + +reg [11:0] out_port_idle_cnt [`num_axis_ports-1:0]; +reg [11:0] out_port_active_cnt [`num_axis_ports-1:0]; +reg [`num_axis_ports-1:0] out_port_active_q; +reg [`num_axis_ports-1:0] out_port_idle_q; +wire [`num_axis_ports-1:0] out_port_active_rp; +wire [`num_axis_ports-1:0] out_port_idle_rp; +wire [`num_axis_ports-1:0] out_port_rdy; +reg [`num_axis_ports-1:0] out_port_not_active; + +assign out_port_rdy[0] = m_axis0_tready; +`ifdef en_axis1 +assign out_port_rdy[1] = m_axis1_tready; +`endif + +reg only_port1_active, only_port0_active; + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + cnt_port_init <= 'd0; + else if (cnt_port_init[12]) + cnt_port_init <= cnt_port_init; + else + cnt_port_init <= cnt_port_init + 1; +end + +always @ (posedge aclk_axis_unseg) begin + port_init_q <= cnt_port_init[12]; + port_init_qq <= port_init_q; +end + +assign port_init_rp = port_init_q & ~port_init_qq; + +genvar kk; + +generate + for (kk=0; kk < `num_axis_ports; kk = kk+1) begin + always @ (posedge aclk_axis_unseg) begin + out_port_active_q[kk] <= out_port_active_cnt[kk][11]; + if (!aresetn_axis_unseg) + out_port_active_cnt[kk] <= 'd0; + else if (out_port_idle_rp[kk]) + out_port_active_cnt[kk] <= 'd0; + else if (!out_port_rdy[kk]) + out_port_active_cnt[kk] <= 'd0; + else if (out_port_active_q[kk]) + out_port_active_cnt[kk] <= out_port_active_cnt[kk]; + else + out_port_active_cnt[kk] <= out_port_active_cnt[kk] + 1; + end + + assign out_port_active_rp[kk] = out_port_active_cnt[kk][11] & ~out_port_active_q[kk]; + + always @ (posedge aclk_axis_unseg) begin + out_port_not_active[kk] <= out_port_idle_cnt[kk][11]; + out_port_idle_q[kk] <= out_port_idle_cnt[kk][11]; + if (!aresetn_axis_unseg) + out_port_idle_cnt[kk] <= 'd0; + else if (out_port_active_rp[kk]) + out_port_idle_cnt[kk] <= 'd0; + else if (out_port_rdy[kk]) + out_port_idle_cnt[kk] <= 'd0; + else if (out_port_idle_q[kk]) + out_port_idle_cnt[kk] <= out_port_idle_cnt[kk]; + else + out_port_idle_cnt[kk] <= out_port_idle_cnt[kk] + 1; + end + + assign out_port_idle_rp[kk] = out_port_idle_cnt[kk][11] & ~out_port_idle_q[kk]; + end +endgenerate + +always @ (posedge aclk_axis_unseg) begin // Update port status when input stream is not active + if (!seg2unseg_val_1[0]) + if (out_port_not_active == 2'b01) + only_port1_active <= 1'b1; + else + only_port1_active <= 1'b0; + else + only_port1_active <= only_port1_active; +end + +always @ (posedge aclk_axis_unseg) begin + if (!seg2unseg_val_1[0]) + if (out_port_not_active == 2'b10) + only_port0_active <= 1'b1; + else + only_port0_active <= 1'b0; + else + only_port0_active <= only_port0_active; +end + +integer m, n; + +reg [$clog2(`num_axis_ports)-1:0] cur_port; +reg nxt_pkt_vld; + +`ifdef en_flow_control // port arbitration with flow control + +generate + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + cur_port = 1'b0; + nxt_pkt_vld = 1'b1; + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + end else if (port_init_rp) begin // Initialize with the active port after power On/systen reset + if (only_port1_active) + cur_port = 1'b1; + else + cur_port = 1'b0; + end else begin + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [cur_port][n] <= 1'b0; + if(seg2unseg_val_1[n]) begin + pkt_val [cur_port][n] <= nxt_pkt_vld; + if (seg2unseg_eop_1[n]) begin // Arbitrate at current packet end + if (only_port1_active) begin // Only out port1 is active + cur_port = 1'b1; + if (port_unseg_out_pfull[1]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end else if (only_port0_active) begin // Only out port0 is active + cur_port = 1'b0; + if (port_unseg_out_pfull[0]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end else begin // Both output ports are active + if (cur_port == (`num_axis_ports-1)) begin + if (port_unseg_out_pfull[0]) begin + cur_port = 1'b1; + if (port_unseg_out_pfull[1]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end else begin + cur_port = 1'b0; + nxt_pkt_vld = 1'b1; + end + end else begin + if (port_unseg_out_pfull[1]) begin + cur_port = 1'b0; + if (port_unseg_out_pfull[0]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end else begin + cur_port = 1'b1; + nxt_pkt_vld = 1'b1; + end + end + end + end + end + end + end +end +endgenerate + +assign buff_full = |port_unseg_out_pfull; + +`else // port arbitration without flow control + +generate + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + cur_port = 1'b0; + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + end else if (port_init_rp) begin // Initialize with the active port after power On/systen reset + if (only_port1_active) + cur_port = 1'b1; + else + cur_port = 1'b0; + end else begin + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [cur_port][n] <= 1'b0; + if(seg2unseg_val_1[n]) begin + pkt_val [cur_port][n] <= 1'b1; + if (seg2unseg_eop_1[n]) begin + if (only_port1_active) begin + cur_port = 1'b1; + end else if (only_port0_active) begin + cur_port = 1'b0; + end else begin + if (cur_port == (`num_axis_ports-1)) begin + if (port_unseg_out_pfull[0]) begin + cur_port = 1'b1; + end else + cur_port = 1'b0; + end else begin + if (port_unseg_out_pfull[1]) begin + cur_port = 1'b0; + end else + cur_port = 1'b1; + end + end + end + end + end + end +end +endgenerate + +`endif + +`else // data rate 100 or 200 Gbps, only one output AXI stream port is available + +`ifdef en_flow_control + +genvar k, l; +generate +for (k=0; k < `num_axis_ports; k = k+1) begin + for(l=0; l < `num_segments; l = l+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_data [k][l] <= seg2unseg_dat_1[l]; + pkt_mty [k][l] <= seg2unseg_mty_1[l]; + pkt_eop [k][l] <= seg2unseg_eop_1[l]; + pkt_err [k][l] <= seg2unseg_err_1[l]; + end + end +end +endgenerate + +reg [$clog2(`num_axis_ports)-1:0] cur_port; +reg nxt_pkt_vld; + +integer m, n; + +generate + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + nxt_pkt_vld = 1'b1; + cur_port <= 1'b0; + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + cur_port <= 1'b0; + end + end + end else begin + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + for(n=0; n < `num_segments; n = n+1) begin + if(seg2unseg_val_1[n]) begin + pkt_val [cur_port][n] <= nxt_pkt_vld; + if (seg2unseg_eop_1[n]) + if (port_unseg_out_pfull[0]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end + end + end + end +endgenerate + +assign buff_full = port_unseg_out_pfull[0]; + +`else + +genvar k,l; + +generate +for (k=0; k < `num_axis_ports; k = k+1) begin + for(l=0; l < `num_segments; l = l+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_data [k][l] <= seg2unseg_dat_1[l]; + pkt_mty [k][l] <= seg2unseg_mty_1[l]; + pkt_eop [k][l] <= seg2unseg_eop_1[l]; + pkt_err [k][l] <= seg2unseg_err_1[l]; + pkt_val [k][l] <= seg2unseg_val_1[l]; + end + end +end +endgenerate + +`endif + +`endif + +reg [`segment_width-1:0] pkt_data1 [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [seg_mty_w-1:0] pkt_mty1 [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [`num_segments-1:0] pkt_val1 [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_eop1 [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_err1 [`num_axis_ports-1:0]; + +reg [`segment_width-1:0] pkt_data2 [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [seg_mty_w-1:0] pkt_mty2 [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [`num_segments-1:0] pkt_val2 [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_eop2 [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_err2 [`num_axis_ports-1:0]; + +genvar o, p; +generate +for (o=0; o < `num_axis_ports; o = o+1) begin + for(p=0; p < `num_segments; p = p+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_data1[o][p] <= pkt_data [o][p]; + pkt_mty1 [o][p] <= pkt_mty [o][p]; + pkt_eop1 [o][p] <= pkt_eop [o][p]; + pkt_err1 [o][p] <= pkt_err [o][p]; + pkt_val1 [o][p] <= pkt_val [o][p]; + end + always @ (posedge aclk_axis_unseg) begin + pkt_data2[o][p] <= pkt_data1 [o][p]; + pkt_mty2 [o][p] <= pkt_mty1 [o][p]; + pkt_eop2 [o][p] <= pkt_eop1 [o][p]; + pkt_err2 [o][p] <= pkt_err1 [o][p]; + pkt_val2 [o][p] <= pkt_val1 [o][p]; + end + end +end +endgenerate + +reg [`segment_width-1:0] pkt_tdata [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(`segment_width/8)-1:0] pkt_tkeep [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_tvalid [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_tuser [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_tlast [`num_axis_ports-1:0]; +reg [(`segment_width*(pkt_array_depth/2))-1:0] axis_tdata_buf_in [`num_axis_ports-1:0]; +reg [((`segment_width/8)*(pkt_array_depth/2))-1:0] axis_tkeep_buf_in [`num_axis_ports-1:0]; +reg [`num_axis_ports-1:0] axis_tvalid_buf_in; +reg [`num_axis_ports-1:0] axis_tlast_buf_in; +reg [`num_axis_ports-1:0] axis_tuser_buf_in; +wire [`num_axis_ports-1:0] axis_tready_buf_in; +reg [`segment_width-1:0] pkt_data_out_0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pkt_mty_out_0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_val_out_0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_eop_out_0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_err_out_0 [`num_axis_ports-1:0]; + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Segment array + +// pack the packet segments in array (to align with unsegmented axis stream data width) + +wire [`num_axis_ports-1:0] outbuff_pfull; + +`ifdef data_rate_400 + +reg [`segment_width-1:0] pkt_data_array [`num_axis_ports-1:0] [pkt_array_depth-1:0]; +reg [seg_mty_w-1:0] pkt_mty_array [`num_axis_ports-1:0] [pkt_array_depth-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array0 [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array00 [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array1 [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array2 [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_eop_array [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_err_array [`num_axis_ports-1:0]; + +reg [$clog2(pkt_array_depth)-1:0] pkt_array_ptr [`num_axis_ports-1:0]; +reg [$clog2(pkt_array_depth)-1:0] pkt_seg_sel_reg [`num_axis_ports-1:0] [pkt_array_depth-1:0]; +reg [$clog2(pkt_array_depth)-1:0] pkt_seg_sel_reg1 [`num_axis_ports-1:0] [pkt_array_depth-1:0]; + +wire [`num_axis_ports-1:0] wr_en_c0; +wire [`num_axis_ports-1:0] wr_en_c1; + +reg [`num_axis_ports-1:0] wr_en_0; +reg [`num_axis_ports-1:0] wr_en_1; + +genvar q; +integer r, rr; +generate +for (q=0; q < `num_axis_ports; q = q+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_array_ptr[q] = 0; + for(r=0; r < pkt_array_depth/2; r = r+1) begin + pkt_val_array0 [q][r] <= 1'b0; + pkt_val_array1 [q][r] <= 1'b0; + pkt_seg_sel_reg[q][r] <= 'd0; + end + for(rr=pkt_array_depth/2; rr < pkt_array_depth; rr = rr+1) begin + pkt_val_array0 [q][rr] <= 1'b0; + pkt_val_array1 [q][rr] <= 1'b0; + pkt_seg_sel_reg[q][rr] <= 'd0; + end + end else begin + for(r=0; r < pkt_array_depth/2; r = r+1) begin + pkt_val_array0 [q][r] <= 1'b0; + end + for(rr=pkt_array_depth/2; rr < pkt_array_depth; rr = rr+1) begin + pkt_val_array0 [q][rr] <= 1'b0; + end + if (wr_en_c0[q]) begin + for(rr=0; rr < pkt_array_depth/2; rr = rr+1) begin + pkt_val_array1 [q][rr] <= 1'b0; + end + end + if (wr_en_c1[q]) begin + for(rr=pkt_array_depth/2; rr < pkt_array_depth; rr = rr+1) begin + pkt_val_array1 [q][rr] <= 1'b0; + end + end + for(r=0; r < `num_segments; r = r+1) begin + if (pkt_val[q][r]) begin + pkt_val_array0 [q][pkt_array_ptr[q]] <= 1'b1; + pkt_val_array1 [q][pkt_array_ptr[q]] <= 1'b1; + pkt_seg_sel_reg[q][pkt_array_ptr[q]] <= r; + if (pkt_eop[q][r]) begin + if (pkt_array_ptr[q][$clog2(pkt_array_depth)-1] == 1) + pkt_array_ptr[q] = 0; + else + pkt_array_ptr[q] = pkt_array_depth/2; + end else + pkt_array_ptr[q] = pkt_array_ptr[q] + 1; + end + end + end + end +end +endgenerate + +genvar s, array_depth; +generate +for (s=0; s < `num_axis_ports; s = s+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_val_array2[s] <= pkt_val_array1[s]; + pkt_val_array[s] <= pkt_val_array2[s]; + pkt_val_array00[s] <= pkt_val_array0[s]; + end + for (array_depth=0; array_depth < pkt_array_depth; array_depth = array_depth+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_seg_sel_reg1[s][array_depth] <= pkt_seg_sel_reg[s][array_depth]; + end + end + for (array_depth=0; array_depth < pkt_array_depth; array_depth = array_depth+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_eop_array[s][array_depth] <= 1'b0; + pkt_err_array[s][array_depth] <= 1'b0; + pkt_mty_array[s][array_depth] <= 'd0; + pkt_data_array[s][array_depth] <= 'd0; + end else begin + if (pkt_val_array00[s][array_depth]) begin + pkt_eop_array[s][array_depth] <= pkt_eop2 [s][pkt_seg_sel_reg1[s][array_depth]]; + pkt_err_array[s][array_depth] <= pkt_err2 [s][pkt_seg_sel_reg1[s][array_depth]]; + pkt_mty_array[s][array_depth] <= pkt_mty2 [s][pkt_seg_sel_reg1[s][array_depth]]; + pkt_data_array[s][array_depth] <= pkt_data2[s][pkt_seg_sel_reg1[s][array_depth]]; + end else begin + pkt_eop_array[s][array_depth] <= 1'b0; + pkt_err_array[s][array_depth] <= 1'b0; + end + end + end + end +end +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Buffering packed segments + +reg [`num_axis_ports-1:0] rd_en_0; +reg [`num_axis_ports-1:0] rd_en_1; + +genvar t; + +generate +for (t=0; t<`num_axis_ports; t=t+1) begin + assign wr_en_c0[t] = pkt_val_array1[t][(pkt_array_depth/2)-1] | (|pkt_eop_array[t][(pkt_array_depth/2)-1:0]); + assign wr_en_c1[t] = pkt_val_array1[t][pkt_array_depth-1] | (|pkt_eop_array[t][pkt_array_depth-1:(pkt_array_depth/2)]); + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + wr_en_0[t] <= 1'b0; + wr_en_1[t] <= 1'b0; + end else begin + wr_en_0[t] <= pkt_val_array[t][(pkt_array_depth/2)-1] | (|pkt_eop_array[t][(pkt_array_depth/2)-1:0]); + wr_en_1[t] <= pkt_val_array[t][pkt_array_depth-1] | (|pkt_eop_array[t][pkt_array_depth-1:(pkt_array_depth/2)]); + end + end +end +endgenerate + +reg [`segment_width-1:0] pkt_data_buf_in_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pkt_mty_buf_in_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_val_buf_in_p0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_eop_buf_in_p0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_err_buf_in_p0 [`num_axis_ports-1:0]; +reg [`segment_width-1:0] pkt_data_buf_in_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pkt_mty_buf_in_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_val_buf_in_p1 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_eop_buf_in_p1 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_err_buf_in_p1 [`num_axis_ports-1:0]; + +wire [(pkt_array_depth/2)-1:0] unseg_buf1_aempty_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_buf1_aempty_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_buf1_empty_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_buf1_empty_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_data_valid_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_data_valid_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_rd_rst_busy_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_rd_rst_busy_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_wr_rst_busy_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_wr_rst_busy_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_1 [`num_axis_ports-1:0]; + +wire [`segment_width-1:0] pkt_data_buf_out_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pkt_mty_buf_out_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_val_buf_out_p0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_eop_buf_out_p0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_err_buf_out_p0 [`num_axis_ports-1:0]; +wire [`segment_width-1:0] pkt_data_buf_out_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pkt_mty_buf_out_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_val_buf_out_p1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_eop_buf_out_p1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_err_buf_out_p1 [`num_axis_ports-1:0]; + +genvar u,v; + +generate +for (u=0; u<`num_axis_ports; u=u+1) begin + for (v=0; v<(pkt_array_depth/2); v=v+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_val_buf_in_p0[u][v] <= 1'b0; + pkt_eop_buf_in_p0[u][v] <= 1'b0; + pkt_err_buf_in_p0[u][v] <= 1'b0; + pkt_val_buf_in_p1[u][v] <= 1'b0; + pkt_eop_buf_in_p1[u][v] <= 1'b0; + pkt_err_buf_in_p1[u][v] <= 1'b0; + end else begin + pkt_val_buf_in_p0[u][v] <= pkt_val_array[u][v]; + pkt_data_buf_in_p0[u][v] <= pkt_data_array[u][v]; + pkt_mty_buf_in_p0[u][v] <= pkt_mty_array[u][v]; + pkt_eop_buf_in_p0[u][v] <= pkt_eop_array[u][v]; + pkt_err_buf_in_p0[u][v] <= pkt_err_array[u][v]; + pkt_val_buf_in_p1[u][v] <= pkt_val_array[u][v+(pkt_array_depth/2)]; + pkt_data_buf_in_p1[u][v] <= pkt_data_array[u][v+(pkt_array_depth/2)]; + pkt_mty_buf_in_p1[u][v] <= pkt_mty_array[u][v+(pkt_array_depth/2)]; + pkt_eop_buf_in_p1[u][v] <= pkt_eop_array[u][v+(pkt_array_depth/2)]; + pkt_err_buf_in_p1[u][v] <= pkt_err_array[u][v+(pkt_array_depth/2)]; + end + end + end +end +endgenerate + +genvar w,x; +generate +for (w=0; w<`num_axis_ports; w=w+1) begin + for (x=0; x<(pkt_array_depth/2); x=x+1) begin + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("1002"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_stage1_p0 ( + .almost_empty(unseg_buf1_aempty_0[w][x]), + .almost_full(), + .data_valid(unseg_data_valid_0[w][x]), + .dbiterr(), + .dout({pkt_mty_buf_out_p0[w][x],pkt_err_buf_out_p0[w][x],pkt_eop_buf_out_p0[w][x],pkt_val_buf_out_p0[w][x],pkt_data_buf_out_p0[w][x]}), + .empty(unseg_buf1_empty_0[w][x]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_0[w][x]), + .rd_data_count(), + .rd_rst_busy(unseg_rd_rst_busy_0[w][x]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_wr_rst_busy_0[w][x]), + .din({pkt_mty_buf_in_p0[w][x],pkt_err_buf_in_p0[w][x],pkt_eop_buf_in_p0[w][x],pkt_val_buf_in_p0[w][x],pkt_data_buf_in_p0[w][x]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en_0[w] & !outbuff_pfull[w] & !unseg_data_valid_0[w][x]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en_0[w] & !unseg_wr_rst_busy_0[w][x]) + ); + + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("1002"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_stage1_p1 ( + .almost_empty(unseg_buf1_aempty_1[w][x]), + .almost_full(), + .data_valid(unseg_data_valid_1[w][x]), + .dbiterr(), + .dout({pkt_mty_buf_out_p1[w][x],pkt_err_buf_out_p1[w][x],pkt_eop_buf_out_p1[w][x],pkt_val_buf_out_p1[w][x],pkt_data_buf_out_p1[w][x]}), + .empty(unseg_buf1_empty_1[w][x]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_1[w][x]), + .rd_data_count(), + .rd_rst_busy(unseg_rd_rst_busy_1[w][x]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_wr_rst_busy_1[w][x]), + .din({pkt_mty_buf_in_p1[w][x],pkt_err_buf_in_p1[w][x],pkt_eop_buf_in_p1[w][x],pkt_val_buf_in_p1[w][x],pkt_data_buf_in_p1[w][x]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en_1[w] & !outbuff_pfull[w] & !unseg_data_valid_1[w][x]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en_1[w] & !unseg_wr_rst_busy_1[w][x]) + ); + end + assign port_unseg_out_pfull[w] = (|unseg_out_buf1_pfull_0[w]) | (|unseg_out_buf1_pfull_1[w]); +end +endgenerate + +assign ports_not_rdy = &port_unseg_out_pfull; + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Packet readout / array port arbitration + +reg [`num_axis_ports-1:0] port_sel; +reg [`num_axis_ports-1:0] port_sel_1; + +genvar y; + +generate +for (y=0; y<`num_axis_ports; y=y+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + rd_en_0[y] <= 1'b0; + rd_en_1[y] <= 1'b0; + port_sel[y] <= 1'b0; + port_sel_1[y] <= 1'b0; + end else if (!outbuff_pfull[y]) begin + rd_en_0[y] <= 1'b0; + rd_en_1[y] <= 1'b0; + port_sel_1[y] <= port_sel[y]; + if (port_sel[y]) begin + rd_en_0[y] <= 1'b0; + if (!(|unseg_buf1_empty_1[y]) && !(|unseg_rd_rst_busy_1[y])) begin + rd_en_1[y] <= 1'b1; + port_sel[y] <= 1'b0; + end else begin + rd_en_1[y] <= 1'b0; + port_sel[y] <= port_sel[y]; + end + end else begin + rd_en_1[y] <= 1'b0; + if (!(|unseg_buf1_empty_0[y]) && !(|unseg_rd_rst_busy_0[y])) begin + rd_en_0[y] <= 1'b1; + port_sel[y] <= 1'b1; + end else begin + rd_en_0[y] <= 1'b0; + port_sel[y] <= port_sel[y]; + end + end + end + end +end +endgenerate + +genvar z, zz; + +generate +for (z=0; z<`num_axis_ports; z=z+1) begin :packet_out_mux + for (zz=0; zz<(pkt_array_depth/2); zz=zz+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_val_out_0[z][zz] <= 1'b0; + pkt_mty_out_0[z][zz] <= {seg_mty_w{1'b1}}; + pkt_eop_out_0[z][zz] <= 1'b0; + pkt_err_out_0[z][zz] <= 1'b0; + end else begin + pkt_val_out_0[z][zz] <= 1'b0; + if (port_sel_1[z]) begin + pkt_val_out_0[z][zz] <= pkt_val_buf_out_p0[z][zz] & unseg_data_valid_0[z][zz]; + pkt_mty_out_0[z][zz] <= pkt_mty_buf_out_p0[z][zz]; + pkt_eop_out_0[z][zz] <= pkt_eop_buf_out_p0[z][zz]; + pkt_err_out_0[z][zz] <= pkt_err_buf_out_p0[z][zz]; + pkt_data_out_0[z][zz] <= pkt_data_buf_out_p0[z][zz]; + end else begin + pkt_val_out_0[z][zz] <= pkt_val_buf_out_p1[z][zz] & unseg_data_valid_1[z][zz]; + pkt_mty_out_0[z][zz] <= pkt_mty_buf_out_p1[z][zz]; + pkt_eop_out_0[z][zz] <= pkt_eop_buf_out_p1[z][zz]; + pkt_err_out_0[z][zz] <= pkt_err_buf_out_p1[z][zz]; + pkt_data_out_0[z][zz] <= pkt_data_buf_out_p1[z][zz]; + end + end + end + end +end +endgenerate + +`else // 100G or 200G + +reg [`segment_width-1:0] pktout_data_array [`num_axis_ports-1:0] [pkt_array_depth*2-1:0]; +reg [seg_mty_w-1:0] pktout_mty_array [`num_axis_ports-1:0] [pkt_array_depth*2-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array0 [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array00 [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array1 [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array2 [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_eop_array [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_err_array [`num_axis_ports-1:0]; + +reg [$clog2(pkt_array_depth*2)-1:0] pktout_array_ptr [`num_axis_ports-1:0]; +reg [$clog2(pkt_array_depth)-1:0] pktout_seg_sel_reg [`num_axis_ports-1:0] [pkt_array_depth*2-1:0]; +reg [$clog2(pkt_array_depth)-1:0] pktout_seg_sel_reg1 [`num_axis_ports-1:0] [pkt_array_depth*2-1:0]; + +wire [`num_axis_ports-1:0] wr_en_c0; +wire [`num_axis_ports-1:0] wr_en_c1; +wire [`num_axis_ports-1:0] wr_en_c2; +wire [`num_axis_ports-1:0] wr_en_c3; + +reg [`num_axis_ports-1:0] wr_en0; +reg [`num_axis_ports-1:0] wr_en1; +reg [`num_axis_ports-1:0] wr_en2; +reg [`num_axis_ports-1:0] wr_en3; + +genvar q; +integer r, rr; +generate +for (q=0; q < `num_axis_ports; q = q+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pktout_array_ptr[q] = 0; + for(r=0; r < pkt_array_depth/2; r = r+1) begin + pktout_val_array0 [q][r] <= 1'b0; + pktout_val_array1 [q][r] <= 1'b0; + pktout_seg_sel_reg[q][r] <= 'd0; + pktout_val_array0 [q][r+pkt_array_depth/2] <= 1'b0; + pktout_val_array1 [q][r+pkt_array_depth/2] <= 1'b0; + pktout_seg_sel_reg[q][r+pkt_array_depth/2] <= 'd0; + pktout_val_array0 [q][r+(pkt_array_depth/2)*2] <= 1'b0; + pktout_val_array1 [q][r+(pkt_array_depth/2)*2] <= 1'b0; + pktout_seg_sel_reg[q][r+(pkt_array_depth/2)*2] <= 'd0; + pktout_val_array0 [q][r+(pkt_array_depth/2)*3] <= 1'b0; + pktout_val_array1 [q][r+(pkt_array_depth/2)*3] <= 1'b0; + pktout_seg_sel_reg[q][r+(pkt_array_depth/2)*3] <= 'd0; + end + end else begin + for(r=0; r < pkt_array_depth/2; r = r+1) begin + pktout_val_array0 [q][r] <= 1'b0; + pktout_val_array0 [q][r+pkt_array_depth/2] <= 1'b0; + pktout_val_array0 [q][r+(pkt_array_depth/2)*2] <= 1'b0; + pktout_val_array0 [q][r+(pkt_array_depth/2)*3] <= 1'b0; + end + if (wr_en_c0[q]) begin + for(rr=0; rr < pkt_array_depth/2; rr = rr+1) begin + pktout_val_array1 [q][rr] <= 1'b0; + end + end + if (wr_en_c1[q]) begin + for(rr=pkt_array_depth/2; rr < pkt_array_depth; rr = rr+1) begin + pktout_val_array1 [q][rr] <= 1'b0; + end + end + if (wr_en_c2[q]) begin + for(rr=pkt_array_depth; rr < (pkt_array_depth/2)*3; rr = rr+1) begin + pktout_val_array1 [q][rr] <= 1'b0; + end + end + if (wr_en_c3[q]) begin + for(rr=(pkt_array_depth/2)*3; rr < (pkt_array_depth/2)*4; rr = rr+1) begin + pktout_val_array1 [q][rr] <= 1'b0; + end + end + for(r=0; r < `num_segments; r = r+1) begin + if (pkt_val[q][r]) begin + pktout_val_array0 [q][pktout_array_ptr[q]] <= 1'b1; + pktout_val_array1 [q][pktout_array_ptr[q]] <= 1'b1; + pktout_seg_sel_reg[q][pktout_array_ptr[q]] <= r; + if (pkt_eop[q][r]) begin + if (pktout_array_ptr[q][$clog2(pkt_array_depth*2)-1:$clog2(pkt_array_depth*2)-2] == 2'b11) + pktout_array_ptr[q] = 0; + else if (pktout_array_ptr[q][$clog2(pkt_array_depth*2)-1:$clog2(pkt_array_depth*2)-2] == 2'b10) + pktout_array_ptr[q] = (pkt_array_depth/2)*3; + else if (pktout_array_ptr[q][$clog2(pkt_array_depth*2)-1:$clog2(pkt_array_depth*2)-2] == 2'b01) + pktout_array_ptr[q] = pkt_array_depth; + else + pktout_array_ptr[q] = pkt_array_depth/2; + end else + pktout_array_ptr[q] = pktout_array_ptr[q] + 1; + end + end + end + end +end +endgenerate + +genvar s, array_depth0; +generate +for (s=0; s < `num_axis_ports; s = s+1) begin + always @ (posedge aclk_axis_unseg) begin + pktout_val_array2[s] <= pktout_val_array1[s]; + pktout_val_array[s] <= pktout_val_array2[s]; + pktout_val_array00[s] <= pktout_val_array0[s]; + end + for (array_depth0=0; array_depth0 < pkt_array_depth*2; array_depth0 = array_depth0+1) begin + always @ (posedge aclk_axis_unseg) begin + pktout_seg_sel_reg1[s][array_depth0] <= pktout_seg_sel_reg[s][array_depth0]; + end + end + for (array_depth0=0; array_depth0 < pkt_array_depth*2; array_depth0 = array_depth0+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pktout_eop_array[s][array_depth0] <= 1'b0; + pktout_err_array[s][array_depth0] <= 1'b0; + pktout_mty_array[s][array_depth0] <= 'd0; + pktout_data_array[s][array_depth0] <= 'd0; + end else begin + if (pktout_val_array00[s][array_depth0]) begin + pktout_eop_array[s][array_depth0] <= pkt_eop2 [s][pktout_seg_sel_reg1[s][array_depth0]]; + pktout_err_array[s][array_depth0] <= pkt_err2 [s][pktout_seg_sel_reg1[s][array_depth0]]; + pktout_mty_array[s][array_depth0] <= pkt_mty2 [s][pktout_seg_sel_reg1[s][array_depth0]]; + pktout_data_array[s][array_depth0] <= pkt_data2[s][pktout_seg_sel_reg1[s][array_depth0]]; + end else begin + pktout_eop_array[s][array_depth0] <= 1'b0; + pktout_err_array[s][array_depth0] <= 1'b0; + end + end + end + end +end +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Buffering packed segments + +reg rd_en0; +reg rd_en1; +reg rd_en2; +reg rd_en3; + +genvar t; + +generate +for (t=0; t<`num_axis_ports; t=t+1) begin + assign wr_en_c0[t] = pktout_val_array1[t][(pkt_array_depth/2)-1] | (|pktout_eop_array[t][(pkt_array_depth/2)-1:0]); + assign wr_en_c1[t] = pktout_val_array1[t][((pkt_array_depth/2)*2)-1] | (|pktout_eop_array[t][((pkt_array_depth/2)*2)-1:(pkt_array_depth/2)]); + assign wr_en_c2[t] = pktout_val_array1[t][((pkt_array_depth/2)*3)-1] | (|pktout_eop_array[t][((pkt_array_depth/2)*3)-1:((pkt_array_depth/2)*2)]); + assign wr_en_c3[t] = pktout_val_array1[t][(pkt_array_depth*2)-1] | (|pktout_eop_array[t][(pkt_array_depth*2)-1:((pkt_array_depth/2)*3)]); + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + wr_en0[t] <= 1'b0; + wr_en1[t] <= 1'b0; + wr_en2[t] <= 1'b0; + wr_en3[t] <= 1'b0; + end else begin + wr_en0[t] <= pktout_val_array[t][(pkt_array_depth/2)-1] | (|pktout_eop_array[t][(pkt_array_depth/2)-1:0]); + wr_en1[t] <= pktout_val_array[t][((pkt_array_depth/2)*2)-1] | (|pktout_eop_array[t][((pkt_array_depth/2)*2)-1:(pkt_array_depth/2)]); + wr_en2[t] <= pktout_val_array[t][((pkt_array_depth/2)*3)-1] | (|pktout_eop_array[t][((pkt_array_depth/2)*3)-1:((pkt_array_depth/2)*2)]); + wr_en3[t] <= pktout_val_array[t][(pkt_array_depth*2)-1] | (|pktout_eop_array[t][(pkt_array_depth*2)-1:((pkt_array_depth/2)*3)]); + end + end +end +endgenerate + +reg [`segment_width-1:0] pktout_data_buf_in_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pktout_mty_buf_in_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_val_buf_in_p0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_eop_buf_in_p0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_err_buf_in_p0 [`num_axis_ports-1:0]; +reg [`segment_width-1:0] pktout_data_buf_in_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pktout_mty_buf_in_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_val_buf_in_p1 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_eop_buf_in_p1 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_err_buf_in_p1 [`num_axis_ports-1:0]; +reg [`segment_width-1:0] pktout_data_buf_in_p2 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pktout_mty_buf_in_p2 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_val_buf_in_p2 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_eop_buf_in_p2 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_err_buf_in_p2 [`num_axis_ports-1:0]; +reg [`segment_width-1:0] pktout_data_buf_in_p3 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pktout_mty_buf_in_p3 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_val_buf_in_p3 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_eop_buf_in_p3 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_err_buf_in_p3 [`num_axis_ports-1:0]; + +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_aempty_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_aempty_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_empty_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_empty_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_data_valid_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_data_valid_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_rd_rst_busy_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_rd_rst_busy_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_wr_rst_busy_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_wr_rst_busy_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_aempty_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_aempty_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_empty_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_empty_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_data_valid_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_data_valid_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_rd_rst_busy_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_rd_rst_busy_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_wr_rst_busy_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_wr_rst_busy_3 [`num_axis_ports-1:0]; + +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_afull_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_afull_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_afull_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_afull_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_3 [`num_axis_ports-1:0]; + +wire [`segment_width-1:0] pktout_data_buf_out_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pktout_mty_buf_out_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_val_buf_out_p0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_eop_buf_out_p0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_err_buf_out_p0 [`num_axis_ports-1:0]; +wire [`segment_width-1:0] pktout_data_buf_out_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pktout_mty_buf_out_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_val_buf_out_p1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_eop_buf_out_p1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_err_buf_out_p1 [`num_axis_ports-1:0]; +wire [`segment_width-1:0] pktout_data_buf_out_p2 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pktout_mty_buf_out_p2 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_val_buf_out_p2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_eop_buf_out_p2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_err_buf_out_p2 [`num_axis_ports-1:0]; +wire [`segment_width-1:0] pktout_data_buf_out_p3 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pktout_mty_buf_out_p3 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_val_buf_out_p3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1: 0] pktout_eop_buf_out_p3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1: 0] pktout_err_buf_out_p3 [`num_axis_ports-1:0]; + +genvar u1,v1; + +generate +for (u1=0; u1<`num_axis_ports; u1=u1+1) begin + for (v1=0; v1<(pkt_array_depth/2); v1=v1+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pktout_val_buf_in_p0[u1][v1] <= 1'b0; + pktout_eop_buf_in_p0[u1][v1] <= 1'b0; + pktout_err_buf_in_p0[u1][v1] <= 1'b0; + pktout_val_buf_in_p1[u1][v1] <= 1'b0; + pktout_eop_buf_in_p1[u1][v1] <= 1'b0; + pktout_err_buf_in_p1[u1][v1] <= 1'b0; + pktout_val_buf_in_p2[u1][v1] <= 1'b0; + pktout_eop_buf_in_p2[u1][v1] <= 1'b0; + pktout_err_buf_in_p2[u1][v1] <= 1'b0; + pktout_val_buf_in_p3[u1][v1] <= 1'b0; + pktout_eop_buf_in_p3[u1][v1] <= 1'b0; + pktout_err_buf_in_p3[u1][v1] <= 1'b0; + end else begin + pktout_val_buf_in_p0[u1][v1] <= pktout_val_array[u1][v1]; + pktout_data_buf_in_p0[u1][v1] <= pktout_data_array[u1][v1]; + pktout_mty_buf_in_p0[u1][v1] <= pktout_mty_array[u1][v1]; + pktout_eop_buf_in_p0[u1][v1] <= pktout_eop_array[u1][v1]; + pktout_err_buf_in_p0[u1][v1] <= pktout_err_array[u1][v1]; + pktout_val_buf_in_p1[u1][v1] <= pktout_val_array[u1][v1+(pkt_array_depth/2)]; + pktout_data_buf_in_p1[u1][v1] <= pktout_data_array[u1][v1+(pkt_array_depth/2)]; + pktout_mty_buf_in_p1[u1][v1] <= pktout_mty_array[u1][v1+(pkt_array_depth/2)]; + pktout_eop_buf_in_p1[u1][v1] <= pktout_eop_array[u1][v1+(pkt_array_depth/2)]; + pktout_err_buf_in_p1[u1][v1] <= pktout_err_array[u1][v1+(pkt_array_depth/2)]; + pktout_val_buf_in_p2[u1][v1] <= pktout_val_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_data_buf_in_p2[u1][v1] <= pktout_data_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_mty_buf_in_p2[u1][v1] <= pktout_mty_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_eop_buf_in_p2[u1][v1] <= pktout_eop_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_err_buf_in_p2[u1][v1] <= pktout_err_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_val_buf_in_p3[u1][v1] <= pktout_val_array[u1][v1+((pkt_array_depth/2)*3)]; + pktout_data_buf_in_p3[u1][v1] <= pktout_data_array[u1][v1+((pkt_array_depth/2)*3)]; + pktout_mty_buf_in_p3[u1][v1] <= pktout_mty_array[u1][v1+((pkt_array_depth/2)*3)]; + pktout_eop_buf_in_p3[u1][v1] <= pktout_eop_array[u1][v1+((pkt_array_depth/2)*3)]; + pktout_err_buf_in_p3[u1][v1] <= pktout_err_array[u1][v1+((pkt_array_depth/2)*3)]; + end + end + end +end +endgenerate + +genvar w1,x1; +generate +for (w1=0; w1<`num_axis_ports; w1=w1+1) begin + for (x1=0; x1<(pkt_array_depth/2); x1=x1+1) begin + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(3), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_out_stage1_p0 ( + .almost_empty(unseg_out_buf1_aempty_0[w1][x1]), + .almost_full(unseg_out_buf1_afull_0[w1][x1]), + .data_valid(unseg_out_data_valid_0[w1][x1]), + .dbiterr(), + .dout({pktout_mty_buf_out_p0[w1][x1],pktout_err_buf_out_p0[w1][x1],pktout_eop_buf_out_p0[w1][x1],pktout_val_buf_out_p0[w1][x1],pktout_data_buf_out_p0[w1][x1]}), + .empty(unseg_out_buf1_empty_0[w1][x1]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_0[w1][x1]), + .rd_data_count(), + .rd_rst_busy(unseg_out_rd_rst_busy_0[w1][x1]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_out_wr_rst_busy_0[w1][x1]), + .din({pktout_mty_buf_in_p0[w1][x1],pktout_err_buf_in_p0[w1][x1],pktout_eop_buf_in_p0[w1][x1],pktout_val_buf_in_p0[w1][x1],pktout_data_buf_in_p0[w1][x1]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en0 & !outbuff_pfull & !unseg_out_data_valid_0[w1][x1]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en0[w1] & !unseg_out_wr_rst_busy_0[w1][x1]) + ); + + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(3), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_out_stage1_p1 ( + .almost_empty(unseg_out_buf1_aempty_1[w1][x1]), + .almost_full(unseg_out_buf1_afull_1[w1][x1]), + .data_valid(unseg_out_data_valid_1[w1][x1]), + .dbiterr(), + .dout({pktout_mty_buf_out_p1[w1][x1],pktout_err_buf_out_p1[w1][x1],pktout_eop_buf_out_p1[w1][x1],pktout_val_buf_out_p1[w1][x1],pktout_data_buf_out_p1[w1][x1]}), + .empty(unseg_out_buf1_empty_1[w1][x1]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_1[w1][x1]), + .rd_data_count(), + .rd_rst_busy(unseg_out_rd_rst_busy_1[w1][x1]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_out_wr_rst_busy_1[w1][x1]), + .din({pktout_mty_buf_in_p1[w1][x1],pktout_err_buf_in_p1[w1][x1],pktout_eop_buf_in_p1[w1][x1],pktout_val_buf_in_p1[w1][x1],pktout_data_buf_in_p1[w1][x1]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en1 & !outbuff_pfull & !unseg_out_data_valid_1[w1][x1]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en1[w1] & !unseg_out_wr_rst_busy_1[w1][x1]) + ); + + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(3), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_out_stage1_p2 ( + .almost_empty(unseg_out_buf1_aempty_2[w1][x1]), + .almost_full(unseg_out_buf1_afull_2[w1][x1]), + .data_valid(unseg_out_data_valid_2[w1][x1]), + .dbiterr(), + .dout({pktout_mty_buf_out_p2[w1][x1],pktout_err_buf_out_p2[w1][x1],pktout_eop_buf_out_p2[w1][x1],pktout_val_buf_out_p2[w1][x1],pktout_data_buf_out_p2[w1][x1]}), + .empty(unseg_out_buf1_empty_2[w1][x1]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_2[w1][x1]), + .rd_data_count(), + .rd_rst_busy(unseg_out_rd_rst_busy_2[w1][x1]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_out_wr_rst_busy_2[w1][x1]), + .din({pktout_mty_buf_in_p2[w1][x1],pktout_err_buf_in_p2[w1][x1],pktout_eop_buf_in_p2[w1][x1],pktout_val_buf_in_p2[w1][x1],pktout_data_buf_in_p2[w1][x1]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en2 & !outbuff_pfull & !unseg_out_data_valid_2[w1][x1]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en2[w1] & !unseg_out_wr_rst_busy_2[w1][x1]) + ); + + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(3), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_out_stage1_p3 ( + .almost_empty(unseg_out_buf1_aempty_3[w1][x1]), + .almost_full(unseg_out_buf1_afull_3[w1][x1]), + .data_valid(unseg_out_data_valid_3[w1][x1]), + .dbiterr(), + .dout({pktout_mty_buf_out_p3[w1][x1],pktout_err_buf_out_p3[w1][x1],pktout_eop_buf_out_p3[w1][x1],pktout_val_buf_out_p3[w1][x1],pktout_data_buf_out_p3[w1][x1]}), + .empty(unseg_out_buf1_empty_3[w1][x1]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_3[w1][x1]), + .rd_data_count(), + .rd_rst_busy(unseg_out_rd_rst_busy_3[w1][x1]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_out_wr_rst_busy_3[w1][x1]), + .din({pktout_mty_buf_in_p3[w1][x1],pktout_err_buf_in_p3[w1][x1],pktout_eop_buf_in_p3[w1][x1],pktout_val_buf_in_p3[w1][x1],pktout_data_buf_in_p3[w1][x1]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en3 & !outbuff_pfull & !unseg_out_data_valid_3[w1][x1]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en3[w1] & !unseg_out_wr_rst_busy_3[w1][x1]) + ); + + end + assign port_unseg_out_pfull[w1] = (|unseg_out_buf1_pfull_0[w1]) | (|unseg_out_buf1_pfull_1[w1]) | (|unseg_out_buf1_pfull_2[w1]) | (|unseg_out_buf1_pfull_3[w1]); +end +endgenerate + +assign ports_not_rdy = &port_unseg_out_pfull; + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Packet readout / array port arbitration + +reg [1:0] outport_sel; +reg [1:0] outport_sel_1; +reg [1:0] outport_sel_2; + +wire pktout_buff_rdy; + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + rd_en0 <= 1'b0; + rd_en1 <= 1'b0; + rd_en2 <= 1'b0; + rd_en3 <= 1'b0; + outport_sel <= 2'b00; + outport_sel_1 <= 2'b00; + outport_sel_2 <= 2'b00; + end else if (!outbuff_pfull) begin + rd_en0 <= 1'b0; + rd_en1 <= 1'b0; + rd_en2 <= 1'b0; + rd_en3 <= 1'b0; + outport_sel_1 <= outport_sel; + outport_sel_2 <= outport_sel_1; + if (outport_sel == 2'b11) begin + rd_en0 <= 1'b0; + rd_en1 <= 1'b0; + rd_en2 <= 1'b0; + if (!(|unseg_out_buf1_empty_3[0]) && !(|unseg_out_rd_rst_busy_3[0])) begin + rd_en3 <= 1'b1; + outport_sel <= outport_sel+1; + end else begin + rd_en3 <= 1'b0; + outport_sel <= outport_sel; + end + end else if (outport_sel == 2'b10) begin + rd_en0 <= 1'b0; + rd_en1 <= 1'b0; + rd_en3 <= 1'b0; + if (!(|unseg_out_buf1_empty_2[0]) && !(|unseg_out_rd_rst_busy_2[0])) begin + rd_en2 <= 1'b1; + outport_sel <= outport_sel+1; + end else begin + rd_en2 <= 1'b0; + outport_sel <= outport_sel; + end + end else if (outport_sel == 2'b01) begin + rd_en0 <= 1'b0; + rd_en2 <= 1'b0; + rd_en3 <= 1'b0; + if (!(|unseg_out_buf1_empty_1[0]) && !(|unseg_out_rd_rst_busy_1[0])) begin + rd_en1 <= 1'b1; + outport_sel <= outport_sel+1; + end else begin + rd_en1 <= 1'b0; + outport_sel <= outport_sel; + end + end else begin + rd_en1 <= 1'b0; + rd_en2 <= 1'b0; + rd_en3 <= 1'b0; + if (!(|unseg_out_buf1_empty_0[0]) && !(|unseg_out_rd_rst_busy_0[0])) begin + rd_en0 <= 1'b1; + outport_sel <= outport_sel+1; + end else begin + rd_en0 <= 1'b0; + outport_sel <= outport_sel; + end + end + end +end + +genvar z1, z2; + +generate +for (z1=0; z1<`num_axis_ports; z1=z1+1) begin : packetout_mux + for (z2=0; z2<(pkt_array_depth/2); z2=z2+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_val_out_0[z1][z2] <= 1'b0; + pkt_mty_out_0[z1][z2] <= {seg_mty_w{1'b1}}; + pkt_eop_out_0[z1][z2] <= 1'b0; + pkt_err_out_0[z1][z2] <= 1'b0; + end else begin + pkt_val_out_0[z1][z2] <= 1'b0; + if (outport_sel_2 == 2'b11) begin + pkt_val_out_0[z1][z2] <= pktout_val_buf_out_p3[z1][z2] & unseg_out_data_valid_3[z1][z2]; + pkt_mty_out_0[z1][z2] <= pktout_mty_buf_out_p3[z1][z2]; + pkt_eop_out_0[z1][z2] <= pktout_eop_buf_out_p3[z1][z2]; + pkt_err_out_0[z1][z2] <= pktout_err_buf_out_p3[z1][z2]; + pkt_data_out_0[z1][z2] <= pktout_data_buf_out_p3[z1][z2]; + end else if (outport_sel_2 == 2'b10) begin + pkt_val_out_0[z1][z2] <= pktout_val_buf_out_p2[z1][z2] & unseg_out_data_valid_2[z1][z2]; + pkt_mty_out_0[z1][z2] <= pktout_mty_buf_out_p2[z1][z2]; + pkt_eop_out_0[z1][z2] <= pktout_eop_buf_out_p2[z1][z2]; + pkt_err_out_0[z1][z2] <= pktout_err_buf_out_p2[z1][z2]; + pkt_data_out_0[z1][z2] <= pktout_data_buf_out_p2[z1][z2]; + end else if (outport_sel_2 == 2'b01) begin + pkt_val_out_0[z1][z2] <= pktout_val_buf_out_p1[z1][z2] & unseg_out_data_valid_1[z1][z2]; + pkt_mty_out_0[z1][z2] <= pktout_mty_buf_out_p1[z1][z2]; + pkt_eop_out_0[z1][z2] <= pktout_eop_buf_out_p1[z1][z2]; + pkt_err_out_0[z1][z2] <= pktout_err_buf_out_p1[z1][z2]; + pkt_data_out_0[z1][z2] <= pktout_data_buf_out_p1[z1][z2]; + end else begin + pkt_val_out_0[z1][z2] <= pktout_val_buf_out_p0[z1][z2] & unseg_out_data_valid_0[z1][z2]; + pkt_mty_out_0[z1][z2] <= pktout_mty_buf_out_p0[z1][z2]; + pkt_eop_out_0[z1][z2] <= pktout_eop_buf_out_p0[z1][z2]; + pkt_err_out_0[z1][z2] <= pktout_err_buf_out_p0[z1][z2]; + pkt_data_out_0[z1][z2] <= pktout_data_buf_out_p0[z1][z2]; + end + end + end + end +end +endgenerate + +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Packet segments to axi stream conversion (each segments as independant streams) + +integer a, b; +reg [`num_axis_ports-1:0] eop_flag; + +generate +always @ (posedge aclk_axis_unseg) begin : packet_to_axi_stream + if (!aresetn_axis_unseg) begin + for (a=0; a<`num_axis_ports; a=a+1) begin + eop_flag[a] = 0; + for (b=0; b<(pkt_array_depth/2); b=b+1) begin + pkt_tvalid[a][b] <= 1'b0; + pkt_tkeep[a][b] <= {(`segment_width/8){1'b0}}; + pkt_tlast[a][b] <= 1'b0; + pkt_tuser[a][b] <= 1'b0; + end + end + end else begin + for (a=0; a<`num_axis_ports; a=a+1) begin + eop_flag[a] = 0; + for (b=0; b<(pkt_array_depth/2); b=b+1) begin + pkt_tvalid[a][b] <= pkt_val_out_0[a][b]; + pkt_tdata[a][b] <= pkt_data_out_0[a][b]; + pkt_tlast[a][b] <= pkt_eop_out_0[a][b]; + pkt_tuser[a][b] <= pkt_err_out_0[a][b]; + pkt_tkeep[a][b] <= {(`segment_width/8){1'b0}}; + if (eop_flag[a]) + pkt_tkeep[a][b] <= {(`segment_width/8){1'b0}}; + else begin + pkt_tkeep[a][b] <= (2**((2**(seg_mty_w)) - pkt_mty_out_0[a][b]))-1; + if (pkt_eop_out_0[a][b]) + eop_flag[a] = 1; + else + eop_flag[a] = 0; + end + end + end + end +end +endgenerate + +//----------------- Combine to single axi stream + +genvar c, d; +generate +for (c=0; c<`num_axis_ports; c=c+1) begin : axi_stream_combine + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + axis_tvalid_buf_in[c] <= 1'b0; + axis_tlast_buf_in[c] <= 1'b0; + axis_tuser_buf_in[c] <= 1'b0; + end else begin + if (axis_tready_buf_in[c]) begin + axis_tvalid_buf_in[c] <= | pkt_tvalid[c]; + axis_tlast_buf_in[c] <= | pkt_tlast[c]; + axis_tuser_buf_in[c] <= | pkt_tuser[c]; + end + end + end + for (d=0; d<(pkt_array_depth/2); d=d+1) begin + always @ (posedge aclk_axis_unseg) begin + axis_tdata_buf_in[c][(`segment_width+(`segment_width*d))-1:(`segment_width*d)] <= pkt_tdata[c][d]; + axis_tkeep_buf_in[c][((`segment_width/8)+((`segment_width/8)*d))-1:((`segment_width/8)*d)] <= pkt_tkeep[c][d]; + end + end +end +endgenerate + +//----------------- Output buffer + +wire [(`segment_width*(pkt_array_depth/2))-1:0] axis_tdata_buf_out [`num_axis_ports-1:0]; +wire [((`segment_width/8)*(pkt_array_depth/2))-1:0] axis_tkeep_buf_out [`num_axis_ports-1:0]; +wire [`num_axis_ports-1:0] axis_tvalid_buf_out; +wire [`num_axis_ports-1:0] axis_tlast_buf_out; +wire [`num_axis_ports-1:0] axis_tuser_buf_out; +wire [`num_axis_ports-1:0] axis_tready_buf_out; +wire [`num_axis_ports-1:0] axis_out_buff_pfull; + +genvar e; + +generate +for (e=0; e<`num_axis_ports; e=e+1) begin : axis_out_buffer + xpm_fifo_axis #( + .CASCADE_HEIGHT(0), + .CDC_SYNC_STAGES(3), + .CLOCKING_MODE("common_clock"), + .ECC_MODE("no_ecc"), + .FIFO_DEPTH(out_buff_depth), + .FIFO_MEMORY_TYPE("auto"), + .PACKET_FIFO("true"), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(out_buff_depth-5), + .RD_DATA_COUNT_WIDTH(1), + .RELATED_CLOCKS(0), + .SIM_ASSERT_CHK(0), + .TDATA_WIDTH((pkt_array_depth/2)*`segment_width), + .TDEST_WIDTH(1), + .TID_WIDTH(1), + .TUSER_WIDTH(1), + .USE_ADV_FEATURES("0003"), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_axis_unseg_out ( + .m_aclk(aclk_axis_unseg), + .m_axis_tready(axis_tready_buf_out[e]), + .m_axis_tdata(axis_tdata_buf_out[e]), + .m_axis_tkeep(axis_tkeep_buf_out[e]), + .m_axis_tlast(axis_tlast_buf_out[e]), + .m_axis_tuser(axis_tuser_buf_out[e]), + .m_axis_tvalid(axis_tvalid_buf_out[e]), + .s_aclk(aclk_axis_unseg), + .s_aresetn(aresetn_axis_unseg), + .prog_full_axis(axis_out_buff_pfull[e]), + .injectdbiterr_axis(1'b0), + .injectsbiterr_axis(1'b0), + .s_axis_tready(axis_tready_buf_in[e]), + .s_axis_tdata(axis_tdata_buf_in[e]), + .s_axis_tkeep(axis_tkeep_buf_in[e]), + .s_axis_tlast(axis_tlast_buf_in[e]), + .s_axis_tuser(axis_tuser_buf_in[e]), + .s_axis_tvalid(axis_tvalid_buf_in[e]) + ); +end +endgenerate + +assign outbuff_pfull = axis_out_buff_pfull; + +assign m_axis0_tdata = axis_tdata_buf_out[0]; +assign m_axis0_tkeep = axis_tkeep_buf_out[0]; +assign m_axis0_tlast = axis_tlast_buf_out[0]; +assign m_axis0_tuser = axis_tuser_buf_out[0]; +assign m_axis0_tvalid = axis_tvalid_buf_out[0]; +assign axis_tready_buf_out[0] = m_axis0_tready; + +`ifdef en_axis1 +assign m_axis1_tdata = axis_tdata_buf_out[1]; +assign m_axis1_tkeep = axis_tkeep_buf_out[1]; +assign m_axis1_tlast = axis_tlast_buf_out[1]; +assign m_axis1_tuser = axis_tuser_buf_out[1]; +assign m_axis1_tvalid = axis_tvalid_buf_out[1]; +assign axis_tready_buf_out[1] = m_axis1_tready; +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Port Statistics + +`ifdef statistics_en + localparam statistics_en = 1; +`else + localparam statistics_en = 0; +`endif + +generate + +if (statistics_en) begin + +//----------------- Input packet count + +reg [63:0] segment_pkt_cnt [`num_segments-1:0]; +reg [63:0] segment_err_cnt [`num_segments-1:0]; +reg [63:0] segment_byte_cnt [`num_segments-1:0]; +wire [($clog2(`segment_width/8)):0] segment_validbytes [`num_segments-1:0]; +reg [63:0] total_pktin_cnt; +reg [63:0] total_err_pktin_cnt; +reg [63:0] total_pktin_byte_cnt; + +genvar ab; + +for (ab=0; ab<`num_segments; ab=ab+1) begin + mty_to_validbytes u_mty_to_valbytes + ( + .mty_in(seg2unseg_mty[ab]), + .valid_bytes_out(segment_validbytes[ab]) + ); +end + +genvar cd; + +for (cd=0; cd<`num_segments; cd=cd+1) begin + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_byte_cnt[cd] <= 'd0; + else if (seg2unseg_val[cd]) + segment_byte_cnt[cd] <= segment_byte_cnt[cd] + segment_validbytes[cd]; + end +end + +integer ef; + +always @ (*) begin + total_pktin_byte_cnt = 'd0; + for (ef=0; ef<`num_segments; ef=ef+1) begin + total_pktin_byte_cnt = total_pktin_byte_cnt + segment_byte_cnt[ef]; + end +end + +genvar gh; + +for (gh=0; gh<`num_segments; gh=gh+1) begin + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_pkt_cnt[gh] <= 'd0; + else if (seg2unseg_val[gh] && seg2unseg_eop[gh]) + segment_pkt_cnt[gh] <= segment_pkt_cnt[gh] + 1; + end + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_err_cnt[gh] <= 'd0; + else if (seg2unseg_val[gh] && seg2unseg_eop[gh] && seg2unseg_err[gh]) + segment_err_cnt[gh] <= segment_err_cnt[gh] + 1; + end +end + +integer ij; + +always @ (*) begin + total_pktin_cnt = 'd0; + total_err_pktin_cnt = 'd0; + for (ij=0; ij<`num_segments; ij=ij+1) begin + total_pktin_cnt = total_pktin_cnt + segment_pkt_cnt[ij]; + total_err_pktin_cnt = total_err_pktin_cnt + segment_err_cnt[ij]; + end +end + +//----------------- Output packet count + +reg [63:0] port_pkt_out_cnt [`num_axis_ports-1:0]; +reg [63:0] port_err_out_cnt [`num_axis_ports-1:0]; +reg [63:0] port_pkt_byte_cnt [`num_axis_ports-1:0]; +reg [63:0] total_pktout_cnt; +reg [63:0] total_err_pktout_cnt; +reg [63:0] total_pktout_byte_cnt; + +wire [($clog2(`unseg_axis_w/8)):0] port_valid_bytes [`num_axis_ports-1:0]; + +genvar g; +for (g=0; g<`num_axis_ports; g=g+1) begin + tkeep_to_validbytes u_tkeep_to_valbytes + ( + .tkeep_in(axis_tkeep_buf_out[g]), + .valid_bytes_out(port_valid_bytes[g]) + ); +end + +genvar i; +for (i=0; i<`num_axis_ports; i=i+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_pkt_out_cnt[i] <= 'd0; + else + if (axis_tvalid_buf_out[i] && axis_tready_buf_out[i] && axis_tlast_buf_out[i]) + port_pkt_out_cnt[i] <= port_pkt_out_cnt[i] + 'd1; + end + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_err_out_cnt[i] <= 'd0; + else + if (axis_tvalid_buf_out[i] && axis_tready_buf_out[i] && axis_tlast_buf_out[i] && axis_tuser_buf_out[i]) + port_err_out_cnt[i] <= port_err_out_cnt[i] + 'd1; + end +end + +genvar j; +for (j=0; j<`num_axis_ports; j=j+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_pkt_byte_cnt[j] <= 'd0; + else + if (axis_tvalid_buf_out[j] && axis_tready_buf_out[j]) + port_pkt_byte_cnt[j] <= port_pkt_byte_cnt[j] + port_valid_bytes[j]; + end +end + +integer k; +always @ (*) begin + total_pktout_cnt = 'd0; + total_err_pktout_cnt = 'd0; + total_pktout_byte_cnt = 'd0; + for (k=0; k<`num_axis_ports; k=k+1) begin + total_pktout_cnt = total_pktout_cnt + port_pkt_out_cnt[k]; + total_err_pktout_cnt = total_err_pktout_cnt + port_err_out_cnt[k]; + total_pktout_byte_cnt = total_pktout_byte_cnt + port_pkt_byte_cnt[k]; + end +end + +assign total_pkt_in_cnt = total_pktin_cnt; +assign total_err_pkt_in_cnt = total_err_pktin_cnt; +assign total_pkt_in_byte_cnt = total_pktin_byte_cnt; +assign total_pkt_out_cnt = total_pktout_cnt; +assign total_err_pkt_out_cnt = total_err_pktout_cnt; +assign total_pkt_out_byte_cnt = total_pktout_byte_cnt; +`ifdef en_axis1 +assign p1_pkt_out_cnt = port_pkt_out_cnt[1]; +assign p1_err_pkt_out_cnt = port_err_out_cnt[1]; +assign p1_pkt_out_byte_cnt = port_pkt_byte_cnt[1]; +assign p0_pkt_out_cnt = port_pkt_out_cnt[0]; +assign p0_err_pkt_out_cnt = port_err_out_cnt[0]; +assign p0_pkt_out_byte_cnt = port_pkt_byte_cnt[0]; +`endif + +end + +endgenerate + +`ifdef debug_en + +reg [`num_axis_ports-1:0] err_boken_pkt, err_boken_pkt_tlst; + +genvar k0; +integer k1; + +generate + +for (k0=0; k0<`num_axis_ports; k0=k0+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + err_boken_pkt[k0] <= 1'b0; + else + err_boken_pkt[k0] <= axis_tvalid_buf_out[k0] & axis_tready_buf_out[k0] & ~axis_tlast_buf_out[k0] & ~(&axis_tkeep_buf_out[k0]); + end +end + +for (k0=0; k0<`num_axis_ports; k0=k0+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + err_boken_pkt_tlst[k0] = 1'b0; + else begin + err_boken_pkt_tlst[k0] = 1'b0; + if (axis_tlast_buf_out[k0]) begin + if (!err_boken_pkt_tlst[k0]) begin + for (k1=0; k1<(`unseg_axis_w/8)-2; k1=k1+1) begin + if (axis_tkeep_buf_out[k0][k1+1] && !axis_tkeep_buf_out[k0][k1]) + err_boken_pkt_tlst[k0] = 1'b1; + else + err_boken_pkt_tlst[k0] = 1'b0; + end + end + end else + err_boken_pkt_tlst[k0] = 1'b0; + end + end +end + + +endgenerate + +assign error_broken_packet_out = (|err_boken_pkt) | (|(err_boken_pkt_tlst & axis_tlast_buf_out & axis_tvalid_buf_out & axis_tready_buf_out)); + +`endif + +endmodule + +//----------------------------------------------------------------------------------------------------------------------- + +module tkeep_to_validbytes + ( + input [(`unseg_axis_w/8)-1:0] tkeep_in, + output wire [($clog2(`unseg_axis_w/8)):0] valid_bytes_out + ); + +integer i; + +reg [($clog2(`unseg_axis_w/8)):0] valid_bytes; + +always @ (tkeep_in) begin + valid_bytes = 0; + for (i=0; i<(`unseg_axis_w/8); i=i+1) + valid_bytes = valid_bytes + tkeep_in[i]; +end + +assign valid_bytes_out = valid_bytes; + +endmodule + +//----------------------------------------------------------------------------------------------------------------------- + +module mty_to_validbytes + ( + input [($clog2(`segment_width/8))-1:0] mty_in, + output wire [($clog2(`segment_width/8)):0] valid_bytes_out + ); + +integer i; + +reg [($clog2(`segment_width/8)):0] valid_bytes; + +always @ (mty_in) begin + valid_bytes <= (2**($clog2(`segment_width/8))) - mty_in; +end + +assign valid_bytes_out = valid_bytes; + +endmodule + + +//######################################################################################################################## + +//------------------------------------ AXIS Unsegmented to Segmented stream Converter ------------------------------------ + +module axis_unseg_to_seg_converter + ( + // AXIS Segment to Unsegment converter ports + // Clock & Resets + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_seg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET aresetn_axis_seg_in" *) + input aclk_axis_seg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_seg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_seg_in, + `ifdef independant_clk + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_unseg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_pktout, ASSOCIATED_RESET aresetn_axis_unseg_in" *) + input aclk_axis_unseg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_unseg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_unseg_in, + `endif + // Segmented interface + // port0 is active for all valid configurations + // Segment 0 input + output Unseg2SegEna0_out, + output [`segment_width-1:0] Unseg2SegDat0_out, + output Unseg2SegSop0_out, + output Unseg2SegEop0_out, + output Unseg2SegErr0_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty0_out, + // Segment 1 input + output Unseg2SegEna1_out, + output [`segment_width-1:0] Unseg2SegDat1_out, + output Unseg2SegSop1_out, + output Unseg2SegEop1_out, + output Unseg2SegErr1_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty1_out, + `ifdef en_port1 + // Segment 2 input + output Unseg2SegEna2_out, + output [`segment_width-1:0] Unseg2SegDat2_out, + output Unseg2SegSop2_out, + output Unseg2SegEop2_out, + output Unseg2SegErr2_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty2_out, + // Segment 3 input + output Unseg2SegEna3_out, + output [`segment_width-1:0] Unseg2SegDat3_out, + output Unseg2SegSop3_out, + output Unseg2SegEop3_out, + output Unseg2SegErr3_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty3_out, + `endif + `ifdef en_port2 + // Segment 4 input + output Unseg2SegEna4_out, + output [`segment_width-1:0] Unseg2SegDat4_out, + output Unseg2SegSop4_out, + output Unseg2SegEop4_out, + output Unseg2SegErr4_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty4_out, + // Segment 5 input + output Unseg2SegEna5_out, + output [`segment_width-1:0] Unseg2SegDat5_out, + output Unseg2SegSop5_out, + output Unseg2SegEop5_out, + output Unseg2SegErr5_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty5_out, + `endif + `ifdef en_port3 + // Segment 6 input + output Unseg2SegEna6_out, + output [`segment_width-1:0] Unseg2SegDat6_out, + output Unseg2SegSop6_out, + output Unseg2SegEop6_out, + output Unseg2SegErr6_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty6_out, + // Segment 7 input + output Unseg2SegEna7_out, + output [`segment_width-1:0] Unseg2SegDat7_out, + output Unseg2SegSop7_out, + output Unseg2SegEop7_out, + output Unseg2SegErr7_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty7_out, + `endif + + // Packet output interface - Unsegmented AXI Stream + // axis0 is active for all valid configurations + // unsegmented AXIS0 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TDATA" *) + input [`unseg_axis_w-1:0] s_axis0_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TKEEP" *) + input [(`unseg_axis_w/8)-1:0] s_axis0_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TLAST" *) + input s_axis0_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TUSER" *) + input s_axis0_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TVALID" *) + input s_axis0_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TREADY" *) + output s_axis0_tready, + + `ifdef en_axis1 + // unsegmented AXIS1 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TDATA" *) + input [`unseg_axis_w-1:0] s_axis1_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TKEEP" *) + input [(`unseg_axis_w/8)-1:0] s_axis1_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TLAST" *) + input s_axis1_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TUSER" *) + input s_axis1_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TVALID" *) + input s_axis1_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TREADY" *) + output s_axis1_tready, + `endif + + // Statistics + `ifdef debug_en + output wire error_missing_sop, + output wire error_broken_pkt_out, + output wire error_broken_pkt_in, + `endif + `ifdef statistics_en + `ifdef en_axis1 + output wire [63: 0] p1_pkt_in_cnt, + output wire [63: 0] p1_err_pkt_in_cnt, + output wire [63: 0] p1_pkt_in_byte_cnt, + output wire [63: 0] p0_pkt_in_cnt, + output wire [63: 0] p0_err_pkt_in_cnt, + output wire [63: 0] p0_pkt_in_byte_cnt, + `endif + output wire [63: 0] total_pkt_in_cnt, + output wire [63: 0] total_err_pkt_in_cnt, + output wire [63: 0] total_pkt_in_byte_cnt, + output wire [63: 0] total_pkt_out_cnt, + output wire [63: 0] total_err_pkt_out_cnt, + output wire [63: 0] total_pkt_out_byte_cnt, + `endif + input wire tx_axis_tready_in, + output wire tx_axis_tvalid_out + ); + +//----------------------------------------------------------------------------------------------------------------------- + +localparam P_MARK_DEBUG = "false"; + +localparam seg_mty_w = $clog2(`segment_width/8); +`ifdef data_rate_200 +localparam pkt_array_depth = `pktarray_depth/2; +`else +localparam pkt_array_depth = `pktarray_depth; +`endif +localparam local_buff_depth = 16; +localparam io_buff_depth = 32; + +// Packet block size +// Block size should be sufficient to hold atleast one complete packet of the maximum expected size. +// Also block size should be a power of 2 + +`ifdef data_rate_200 +localparam pkt_blk_depth = 512; +localparam input_buffer_depth = pkt_blk_depth; +localparam output_buffer_depth = input_buffer_depth*8*`num_axis_ports; +`else +localparam pkt_blk_depth = 512; +localparam input_buffer_depth = pkt_blk_depth; +localparam output_buffer_depth = input_buffer_depth*4*`num_axis_ports; +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +wire aclk_axis_unseg; +wire aresetn_axis_unseg; + +`ifdef independant_clk + assign aclk_axis_unseg = aclk_axis_unseg_in; + assign aresetn_axis_unseg = aresetn_axis_unseg_in; +`else + assign aclk_axis_unseg = aclk_axis_seg_in; + assign aresetn_axis_unseg = aresetn_axis_seg_in; +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Input Stream buffer + +wire [`unseg_axis_w-1:0] s_axis_tdata_in [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/8)-1:0] s_axis_tkeep_in [`num_axis_ports-1:0]; +wire [`num_axis_ports-1:0] s_axis_tvalid_in; +wire [`num_axis_ports-1:0] s_axis_tlast_in; +wire [`num_axis_ports-1:0] s_axis_tuser_in; +wire [`num_axis_ports-1:0] s_axis_tready_in; + +wire axis_pkt_blk_rdy_flg; +wire axis_pkt_blk_rdy_p; +reg axis_pkt_blk_rdy_flg_clr; + +assign s_axis_tdata_in[0] = s_axis0_tdata; +assign s_axis_tkeep_in[0] = s_axis0_tkeep; +assign s_axis_tvalid_in[0] = s_axis0_tvalid & (~axis_pkt_blk_rdy_flg); +assign s_axis_tlast_in[0] = s_axis0_tlast; +assign s_axis_tuser_in[0] = s_axis0_tuser; +assign s_axis0_tready = s_axis_tready_in[0] & (~axis_pkt_blk_rdy_flg); + +`ifdef en_axis1 +assign s_axis_tdata_in[1] = s_axis1_tdata; +assign s_axis_tkeep_in[1] = s_axis1_tkeep; +assign s_axis_tvalid_in[1] = s_axis1_tvalid & (~axis_pkt_blk_rdy_flg); +assign s_axis_tlast_in[1] = s_axis1_tlast; +assign s_axis_tuser_in[1] = s_axis1_tuser; +assign s_axis1_tready = s_axis_tready_in[1] & (~axis_pkt_blk_rdy_flg); +`endif + +wire [`unseg_axis_w-1:0] axis_tdata_c [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/8)-1:0] axis_tkeep_c [`num_axis_ports-1:0]; +wire [`num_axis_ports-1:0] axis_tvalid_c; +wire [`num_axis_ports-1:0] axis_tlast_c; +wire [`num_axis_ports-1:0] axis_tuser_c; +wire [`num_axis_ports-1:0] axis_tready_c; + +wire [`num_axis_ports-1:0] axis_in_buff_pfull; +wire [`num_axis_ports-1:0] axis_in_buff_pempty; +wire [`num_axis_ports-1:0] almost_full_axis; +wire [`num_axis_ports-1:0] almost_empty_axis; + +wire [`num_axis_ports-1:0] axis_inbuff_pfull; +wire [`num_axis_ports-1:0] axis_inbuff_aempty; + +wire [$clog2(input_buffer_depth):0] axis_inbuff_wrcnt [`num_axis_ports-1:0]; + +`ifdef debug_en + +reg [`num_axis_ports-1:0] err_boken_pkt, err_boken_pkt_tlst; + +genvar a1; +integer a2; + +generate + +for (a1=0; a1<`num_axis_ports; a1=a1+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + err_boken_pkt[a1] <= 1'b0; + else + err_boken_pkt[a1] <= s_axis_tvalid_in[a1] & s_axis_tready_in[a1] & ~axis_pkt_blk_rdy_flg & ~s_axis_tlast_in[a1] & ~(&s_axis_tkeep_in[a1]); + end +end + +for (a1=0; a1<`num_axis_ports; a1=a1+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + err_boken_pkt_tlst[a1] = 1'b0; + else begin + err_boken_pkt_tlst[a1] = 1'b0; + if (s_axis_tlast_in[a1]) begin + if (!err_boken_pkt_tlst[a1]) begin + for (a2=0; a2<(`unseg_axis_w/8)-2; a2=a2+1) begin + if (s_axis_tkeep_in[a1][a2+1] && !s_axis_tkeep_in[a1][a2]) + err_boken_pkt_tlst[a1] = 1'b1; + else + err_boken_pkt_tlst[a1] = 1'b0; + end + end + end else + err_boken_pkt_tlst[a1] = 1'b0; + end + end +end + + +endgenerate + +assign error_broken_pkt_in = (|err_boken_pkt) | (|(err_boken_pkt_tlst & s_axis_tvalid_in & s_axis_tready_in & ~axis_pkt_blk_rdy_flg)); + +`endif + +genvar a; +generate + for (a=0; a<`num_axis_ports; a=a+1) begin + assign axis_inbuff_pfull[a] = axis_in_buff_pfull[a]; + assign axis_inbuff_aempty[a] = almost_empty_axis[a]; + xpm_fifo_axis #( + .CASCADE_HEIGHT(0), + .CDC_SYNC_STAGES(3), + .CLOCKING_MODE("common_clock"), + .ECC_MODE("no_ecc"), + .FIFO_DEPTH(input_buffer_depth), + .FIFO_MEMORY_TYPE("auto"), + .PACKET_FIFO("true"), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(input_buffer_depth-5), + .RD_DATA_COUNT_WIDTH($clog2(input_buffer_depth)+1), + .RELATED_CLOCKS(0), + .SIM_ASSERT_CHK(0), + .TDATA_WIDTH(`unseg_axis_w), + .TDEST_WIDTH(1), + .TID_WIDTH(1), + .TUSER_WIDTH(1), + .USE_ADV_FEATURES("0803"), + .WR_DATA_COUNT_WIDTH($clog2(input_buffer_depth)+1) + ) + xpm_fifo_axis_unseg_in ( + .m_aclk(aclk_axis_unseg), + .m_axis_tready(axis_tready_c[a]), + .m_axis_tdata(axis_tdata_c[a]), + .m_axis_tkeep(axis_tkeep_c[a]), + .m_axis_tlast(axis_tlast_c[a]), + .m_axis_tuser(axis_tuser_c[a]), + .m_axis_tvalid(axis_tvalid_c[a]), + .s_aclk(aclk_axis_unseg), + .s_aresetn(aresetn_axis_unseg), + .prog_full_axis(axis_in_buff_pfull[a]), + .prog_empty_axis(axis_in_buff_pempty[a]), + .almost_full_axis(almost_full_axis[a]), + .almost_empty_axis(almost_empty_axis[a]), + .s_axis_tready(s_axis_tready_in[a]), + .s_axis_tdata(s_axis_tdata_in[a]), + .s_axis_tkeep(s_axis_tkeep_in[a]), + .s_axis_tlast(s_axis_tlast_in[a]), + .s_axis_tuser(s_axis_tuser_in[a]), + .s_axis_tvalid(s_axis_tvalid_in[a]), + .wr_data_count_axis(axis_inbuff_wrcnt[a]) + ); + end +endgenerate + +wire [`segment_width-1:0] axis_tdata_buff [`num_axis_ports-1:0][(`unseg_axis_w/`segment_width)-1:0]; +wire [(`segment_width/8)-1:0] axis_tkeep_buff [`num_axis_ports-1:0][(`unseg_axis_w/`segment_width)-1:0]; +wire [`num_axis_ports-1:0] axis_tvalid_buff; +wire [`num_axis_ports-1:0] axis_tlast_buff; +wire [`num_axis_ports-1:0] axis_tuser_buff; +wire [`num_axis_ports-1:0] axis_tready_buff; + +genvar aa, ab; +generate + for (aa=0; aa<`num_axis_ports; aa=aa+1) begin + assign axis_tready_c[aa] = axis_tready_buff[aa]; + assign axis_tvalid_buff[aa] = axis_tvalid_c[aa]; + assign axis_tlast_buff[aa] = axis_tlast_c[aa]; + assign axis_tuser_buff[aa] = axis_tuser_c[aa]; + for (ab=0; ab<(`unseg_axis_w/`segment_width); ab=ab+1) begin + assign axis_tdata_buff[aa][ab] = axis_tdata_c[aa][((ab+1)*`segment_width)-1:(ab*`segment_width)]; + assign axis_tkeep_buff[aa][ab] = axis_tkeep_c[aa][((ab+1)*(`segment_width/8))-1:(ab*(`segment_width/8))]; + end + end +endgenerate + +//----------------- Read packets as a block + +reg [$clog2(input_buffer_depth):0] axis_pkt_in_cnt [`num_axis_ports-1:0]; +reg [$clog2(input_buffer_depth)+1:0] num_pkt_to_rd_reg [`num_axis_ports-1:0]; +reg axis_in_buff_pfull_q, axis_in_buff_pfull_qq; + +wire out_buff_afull; +wire out_buff_pfull; + +genvar b; +for (b=0; b<`num_axis_ports; b=b+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + axis_pkt_in_cnt[b] <= 'd0; + else if (axis_pkt_blk_rdy_p) + axis_pkt_in_cnt[b] <= 'd0; + else if (s_axis_tvalid_in[b] && s_axis_tready_in[b] && s_axis_tlast_in[b]) + axis_pkt_in_cnt[b] <= axis_pkt_in_cnt[b] + 'd1; + end +end + +reg [$clog2(pkt_blk_depth*4):0] axis_pkt_flush_cnt; + +`ifdef en_axis1 + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + axis_pkt_flush_cnt <= 'd0; + else if (axis_pkt_blk_rdy_p) + axis_pkt_flush_cnt <= 'd0; + else if ((|axis_pkt_in_cnt[1] || |axis_pkt_in_cnt[0]) && !out_buff_pfull) + axis_pkt_flush_cnt <= axis_pkt_flush_cnt + 1; + else + axis_pkt_flush_cnt <= 'd0; +end + +`else + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + axis_pkt_flush_cnt <= 'd0; + else if (axis_pkt_blk_rdy_p) + axis_pkt_flush_cnt <= 'd0; + else if (|axis_pkt_in_cnt[0] && !out_buff_pfull) + axis_pkt_flush_cnt <= axis_pkt_flush_cnt + 1; + else + axis_pkt_flush_cnt <= 'd0; +end + +`endif + +reg [`num_axis_ports-1:0] axis_pkt_blk_rd; +reg unseg_pkt_blk_rd; + +assign axis_pkt_blk_rdy_flg = axis_in_buff_pfull_q; + +wire [`num_axis_ports-1:0] unseg_buff_empty; + +always @ (posedge aclk_axis_unseg) begin + axis_pkt_blk_rdy_flg_clr <= axis_pkt_blk_rdy_p; + axis_in_buff_pfull_qq <= axis_in_buff_pfull_q; + if (!aresetn_axis_unseg) + axis_in_buff_pfull_q <= 1'b0; + else if (axis_pkt_blk_rdy_flg_clr | (|axis_pkt_blk_rd)) + axis_in_buff_pfull_q <= 1'b0; + else + axis_in_buff_pfull_q <= ((~(&axis_inbuff_aempty) & |axis_inbuff_pfull) | axis_pkt_flush_cnt[$clog2(pkt_blk_depth*4)]) & ~out_buff_pfull & (&unseg_buff_empty); +end + +assign axis_pkt_blk_rdy_p = axis_in_buff_pfull_q & ~axis_in_buff_pfull_qq; + +reg axis_pkt_blk_rdy_rp_q; + +always @ (posedge aclk_axis_unseg) begin + axis_pkt_blk_rdy_rp_q <= axis_pkt_blk_rdy_p; +end + +reg [$clog2(input_buffer_depth):0] axis_pkt_rd_cnt [`num_axis_ports-1:0]; +wire [`num_axis_ports-1:0] axis_pkt_blk_rd_end; + +genvar b0; +generate +for (b0=0; b0<`num_axis_ports; b0=b0+1) begin +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + num_pkt_to_rd_reg[b0] <= 'd0; + axis_pkt_blk_rd[b0] <= 1'b0; + end else if (axis_pkt_blk_rdy_p) begin + num_pkt_to_rd_reg[b0] <= axis_pkt_in_cnt[b0]; + axis_pkt_blk_rd[b0] <= |axis_pkt_in_cnt[b0]; + end else begin + num_pkt_to_rd_reg[b0] <= num_pkt_to_rd_reg[b0]; + if (axis_pkt_blk_rd_end[b0]) + axis_pkt_blk_rd[b0] <= 1'b0; + else + axis_pkt_blk_rd[b0] <= axis_pkt_blk_rd[b0]; + end +end +end +endgenerate + +genvar b1; +generate +for (b1=0; b1<`num_axis_ports; b1=b1+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + axis_pkt_rd_cnt[b1] <= 'd0; + else if (axis_pkt_blk_rd_end[b1]) + axis_pkt_rd_cnt[b1] <= 'd0; + else if (axis_tvalid_buff[b1] && axis_tready_buff[b1] && axis_tlast_buff[b1]) + axis_pkt_rd_cnt[b1] <= axis_pkt_rd_cnt[b1] + 'd1; + end +end +endgenerate + +genvar b3; +generate +for (b3=0; b3<`num_axis_ports; b3=b3+1) begin + assign axis_pkt_blk_rd_end[b3] = (axis_pkt_blk_rd[b3] && axis_pkt_rd_cnt[b3] >= num_pkt_to_rd_reg[b3]) ? 1'b1 : 1'b0; +end + +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Stream to segment conversion + +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_sop [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_eop [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_err [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_val [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_blk_end [`num_axis_ports-1:0]; +wire [seg_mty_w-1:0] unseg_mty_c [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; +reg [seg_mty_w-1:0] unseg_mty [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; +reg [`segment_width-1:0] unseg_dat [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; + +reg [`num_axis_ports-1:0] pkt_start; + +genvar c, cc; +generate +for (c=0; c<`num_axis_ports; c=c+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + pkt_start[c] <= 1'b1; + else begin + if(axis_tvalid_buff[c] & !axis_tlast_buff[c] & axis_tready_buff[c]) + pkt_start[c] <= 1'b0; + else if (axis_tvalid_buff[c] & axis_tlast_buff[c] & axis_tready_buff[c]) + pkt_start[c] <= 1'b1; + end + unseg_sop[c][0] <= (axis_tready_buff[c] & pkt_start[c] & axis_tvalid_buff[c]); + end + for (cc=0; cc<((`unseg_axis_w/`segment_width)-1); cc=cc+1) begin + always @ (posedge aclk_axis_unseg) + unseg_sop[c][cc+1] <= 1'b0; + end +end +endgenerate + +wire tdata_available [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; + +genvar d, dd; +generate +for (d=0; d<`num_axis_ports; d=d+1) begin + for (dd=0; dd<(`unseg_axis_w/`segment_width); dd=dd+1) begin + assign tdata_available[d][dd] = |axis_tkeep_buff[d][dd] & axis_tvalid_buff[d]; + end +end +endgenerate + +genvar e, ee; +generate +for (e=0; e<`num_axis_ports; e=e+1) begin + always @ (posedge aclk_axis_unseg) begin + unseg_eop[e][(`unseg_axis_w/`segment_width)-1] <= tdata_available[e][(`unseg_axis_w/`segment_width)-1] & axis_tlast_buff[e]; + unseg_err[e][(`unseg_axis_w/`segment_width)-1] <= tdata_available[e][(`unseg_axis_w/`segment_width)-1] & axis_tlast_buff[e] & axis_tuser_buff[e]; + end + for (ee=0; ee<((`unseg_axis_w/`segment_width)-1); ee=ee+1) begin + always @ (posedge aclk_axis_unseg) begin + unseg_eop[e][ee] <= tdata_available[e][ee] & ~tdata_available[e][ee+1] & axis_tlast_buff[e]; + unseg_err[e][ee] <= tdata_available[e][ee] & ~tdata_available[e][ee+1] & axis_tlast_buff[e] & axis_tuser_buff[e]; + end + end +end +endgenerate + +genvar f, ff; +generate +for (f=0; f<`num_axis_ports; f=f+1) begin + for (ff=0; ff<((`unseg_axis_w/`segment_width)); ff=ff+1) begin + tkeep_to_mty u_tkeep_to_mty + ( + .tkeep_in(axis_tkeep_buff[f][ff]), + .mty_out(unseg_mty_c[f][ff]) + ); + always @ (posedge aclk_axis_unseg) begin + unseg_dat[f][ff] <= axis_tdata_buff[f][ff]; + unseg_val[f][ff] <= tdata_available[f][ff] & axis_tvalid_buff[f] & axis_tready_buff[f]; + unseg_mty[f][ff] <= unseg_mty_c[f][ff]; + end + end +end +endgenerate + +genvar f1, f2; +generate +for (f1=0; f1<`num_axis_ports; f1=f1+1) begin + for (f2=0; f2<((`unseg_axis_w/`segment_width)); f2=f2+1) begin + assign unseg_blk_end[f1][f2] = unseg_eop[f1][f2] & axis_pkt_blk_rd_end[f1]; + end +end +endgenerate + +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_sop_q [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_eop_q [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_err_q [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_val_q [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_blk_end_q [`num_axis_ports-1:0]; +reg [`segment_width-1:0] unseg_dat_q [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; +reg [seg_mty_w-1:0] unseg_mty_q [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; + +genvar f3, f4; +generate +for (f3=0; f3<`num_axis_ports; f3=f3+1) begin + for (f4=0; f4<((`unseg_axis_w/`segment_width)); f4=f4+1) begin + always @ (posedge aclk_axis_unseg) begin + unseg_sop_q[f3][f4] <= unseg_sop[f3][f4]; + unseg_eop_q[f3][f4] <= unseg_eop[f3][f4]; + unseg_err_q[f3][f4] <= unseg_err[f3][f4]; + unseg_dat_q[f3][f4] <= unseg_dat[f3][f4]; + unseg_val_q[f3][f4] <= unseg_val[f3][f4]; + unseg_mty_q[f3][f4] <= unseg_mty[f3][f4]; + unseg_blk_end_q[f3][f4] <= unseg_eop[f3][f4] & axis_pkt_blk_rd_end[f3]; + end + end +end +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Segment Buffer + +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_aempty [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_afull [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_pfull [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_empty [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_data_valid [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_rd_rst_busy [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_wr_rst_busy [`num_axis_ports-1:0]; + +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_sop_buf [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_eop_buf [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_err_buf [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_val_buf_c [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_val_buf [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_blk_end_buf [`num_axis_ports-1:0]; +wire [seg_mty_w-1:0] unseg_mty_buf [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; +wire [`segment_width-1:0] unseg_dat_buf [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; + +wire [`num_axis_ports-1:0] unseg_buf_wr_en; +reg [`num_axis_ports-1:0] unseg_buf_rd_en; + +wire pkt_array_buf_pfull; + +wire [`num_axis_ports-1:0] unseg_buf_rd_en_c; + +reg axis_blk_rd_q, axis_blk_rd_qq; +wire axis_blk_rd_rp; +wire unseg_pkt_blk_end; + +always @ (posedge aclk_axis_unseg) begin + axis_blk_rd_q <= |axis_pkt_blk_rd; + axis_blk_rd_qq <= axis_blk_rd_q; +end + +assign axis_blk_rd_rp = axis_blk_rd_q & ~axis_blk_rd_qq; + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + unseg_pkt_blk_rd <= 1'b0; + else if (unseg_pkt_blk_end) + unseg_pkt_blk_rd <= 1'b0; + else if (axis_blk_rd_rp) + unseg_pkt_blk_rd <= 1'b1; + else + unseg_pkt_blk_rd <= unseg_pkt_blk_rd; +end + +genvar g, gg; +generate +for (g=0; g<`num_axis_ports; g=g+1) begin + assign unseg_buf_wr_en[g] = unseg_val_q[g][0]; + assign axis_tready_buff[g] = axis_pkt_blk_rd[g] & ~axis_pkt_blk_rd_end[g] & ~(|unseg_buf_pfull[g]); + assign unseg_buff_empty[g] = &unseg_buf_empty[g]; + for (gg=0; gg<((`unseg_axis_w/`segment_width)); gg=gg+1) begin + assign unseg_val_buf[g][gg] = unseg_val_buf_c[g][gg] & unseg_buf_data_valid[g][gg]; + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(local_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(local_buff_depth-5), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+5), + .READ_MODE("fwft"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+5), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_seg_buff ( + .almost_empty(unseg_buf_aempty[g][gg]), + .almost_full(unseg_buf_afull[g][gg]), + .data_valid(unseg_buf_data_valid[g][gg]), + .dbiterr(), + .dout({unseg_blk_end_buf[g][gg],unseg_err_buf[g][gg],unseg_eop_buf[g][gg],unseg_sop_buf[g][gg],unseg_mty_buf[g][gg],unseg_val_buf_c[g][gg],unseg_dat_buf[g][gg]}), + .empty(unseg_buf_empty[g][gg]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_buf_pfull[g][gg]), + .rd_data_count(), + .rd_rst_busy(unseg_buf_rd_rst_busy[g][gg]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_buf_wr_rst_busy[g][gg]), + .din({unseg_blk_end_q[g][gg],unseg_err_q[g][gg],unseg_eop_q[g][gg],unseg_sop_q[g][gg],unseg_mty_q[g][gg],unseg_val_q[g][gg],unseg_dat_q[g][gg]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(unseg_buf_rd_en_c[g]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(unseg_buf_wr_en[g]) + ); + end +end +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----- Packet read enable generation, (read arbitration, based on packet availability in input ports) + +reg only_port1_active, only_port0_active; + +`ifdef en_axis1 // Below logic assumes max no of ports is 2 (applicable for 400G) + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + only_port0_active <= 1'b0; + else if (axis_pkt_blk_rdy_p) + if (axis_inbuff_aempty[1]) + only_port0_active <= 1'b1; + else + only_port0_active <= 1'b0; + else + only_port0_active <= only_port0_active; +end + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + only_port1_active <= 1'b0; + else if (axis_pkt_blk_rdy_p) + if (axis_inbuff_aempty[0]) + only_port1_active <= 1'b1; + else + only_port1_active <= 1'b0; + else + only_port1_active <= only_port1_active; +end + +reg pkt_port_sel; + +assign unseg_buf_rd_en_c[0] = (unseg_buf_rd_en[0] | ((|unseg_eop_buf[1] & (|unseg_val_buf[1])) & !(|unseg_buf_empty[0])) & ~pkt_array_buf_pfull); +assign unseg_buf_rd_en_c[1] = (unseg_buf_rd_en[1] | ((|unseg_eop_buf[0] & (|unseg_val_buf[0])) & !(|unseg_buf_empty[1])) & ~pkt_array_buf_pfull); + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_port_sel <= 1'b0; + unseg_buf_rd_en[0] <= 1'b0; + unseg_buf_rd_en[1] <= 1'b0; + end else if (axis_pkt_blk_rdy_rp_q) begin + if (only_port1_active) begin + pkt_port_sel <= 1'b1; + unseg_buf_rd_en[0] <= 1'b0; + unseg_buf_rd_en[1] <= 1'b0; + end else if (only_port0_active) begin + pkt_port_sel <= 1'b0; + unseg_buf_rd_en[1] <= 1'b0; + unseg_buf_rd_en[1] <= 1'b0; + end else + pkt_port_sel <= pkt_port_sel; + end else if (!pkt_array_buf_pfull) begin + if (pkt_port_sel) begin + unseg_buf_rd_en[0] <= 1'b0; + if (|unseg_eop_buf[1] && |unseg_val_buf[1]) begin + if (|unseg_buf_empty[1]) begin + unseg_buf_rd_en[0] <= 1'b1; + unseg_buf_rd_en[1] <= 1'b0; + pkt_port_sel <= 1'b0; + end else if (!(|unseg_buf_empty[0])) begin + unseg_buf_rd_en[0] <= 1'b1; + unseg_buf_rd_en[1] <= 1'b0; + pkt_port_sel <= 1'b0; + end else + unseg_buf_rd_en[1] <= 1'b1; + end else if (|unseg_eop_buf[1] && !(|unseg_buf_empty[0])) begin + unseg_buf_rd_en[0] <= 1'b1; + unseg_buf_rd_en[1] <= 1'b0; + pkt_port_sel <= 1'b0; + end else if(!(|unseg_buf_empty[1])) begin + unseg_buf_rd_en[1] <= 1'b1; + end else begin + unseg_buf_rd_en[1] <= 1'b0; + end + end else begin + unseg_buf_rd_en[1] <= 1'b0; + if (|unseg_eop_buf[0] && |unseg_val_buf[0]) begin + if (|unseg_buf_empty[0]) begin + unseg_buf_rd_en[1] <= 1'b1; + unseg_buf_rd_en[0] <= 1'b0; + pkt_port_sel <= 1'b1; + end else if (!(|unseg_buf_empty[1])) begin + unseg_buf_rd_en[1] <= 1'b1; + unseg_buf_rd_en[0] <= 1'b0; + pkt_port_sel <= 1'b1; + end else + unseg_buf_rd_en[0] <= 1'b1; + end else if (|unseg_eop_buf[0] && !(|unseg_buf_empty[1])) begin + unseg_buf_rd_en[1] <= 1'b1; + unseg_buf_rd_en[0] <= 1'b0; + pkt_port_sel <= 1'b1; + end else if(!(|unseg_buf_empty[0])) begin + unseg_buf_rd_en[0] <= 1'b1; + end else begin + unseg_buf_rd_en[0] <= 1'b0; + end + end + end +end + +`else // only one port available + +assign unseg_buf_rd_en_c[0] = unseg_buf_rd_en[0] & ~pkt_array_buf_pfull; + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + unseg_buf_rd_en[0] <= 1'b0; + else if (!pkt_array_buf_pfull) begin + if (|unseg_buf_empty[0]) + unseg_buf_rd_en[0] <= 1'b0; + else + unseg_buf_rd_en[0] <= 1'b1; + end +end + +`endif + +`ifdef en_axis1 + +reg [`segment_width-1:0] seg_data_array [pkt_array_depth-1:0]; +reg [seg_mty_w-1:0] seg_mty_array [pkt_array_depth-1:0]; +reg [pkt_array_depth-1:0] seg_val_array; +reg [pkt_array_depth-1:0] seg_sop_array; +reg [pkt_array_depth-1:0] seg_eop_array; +reg [pkt_array_depth-1:0] seg_err_array; +reg [pkt_array_depth-1:0] seg_blk_end_array; + +`else + +reg [`segment_width-1:0] seg_data_array [(`unseg_axis_w/`segment_width)-1:0]; +reg [seg_mty_w-1:0] seg_mty_array [(`unseg_axis_w/`segment_width)-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_val_array; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_sop_array; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_eop_array; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_err_array; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_blk_end_array; + +`endif + +// Generate a flag indicate the end of a block(aligned with the eop of the last packet in the block) + +wire [`num_axis_ports-1:0] unseg_blk_end_buf_val; + +`ifdef en_axis1 + +reg [`num_axis_ports-1:0] unseg_blk_end_flg; + +genvar h; +generate +for (h=0; h<`num_axis_ports; h=h+1) begin + if (h == 0) + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg | unseg_pkt_blk_end) + unseg_blk_end_flg[h] <= 1'b0; + else if (only_port1_active) + unseg_blk_end_flg[h] <= 1'b0; + else if (unseg_blk_end_flg[h]) + if (|unseg_blk_end_buf[h+1] && |unseg_val_buf[h+1] && unseg_buf_rd_en_c[h+1]) + unseg_blk_end_flg[h] <= 1'b0; + else + unseg_blk_end_flg[h] <= unseg_blk_end_flg[h]; + else if (|unseg_blk_end_buf[h] && |unseg_val_buf[h] && unseg_buf_rd_en_c[h]) + if (|unseg_blk_end_buf[h+1] && |unseg_val_buf[h+1] && unseg_buf_rd_en_c[h+1]) + unseg_blk_end_flg[h] <= 1'b0; + else if (unseg_blk_end_flg[h+1]) + unseg_blk_end_flg[h] <= 1'b0; + else + unseg_blk_end_flg[h] <= 1'b1; + else + unseg_blk_end_flg[h] <= unseg_blk_end_flg[h]; + end + else + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg | unseg_pkt_blk_end) + unseg_blk_end_flg[h] <= 1'b0; + else if (only_port0_active) + unseg_blk_end_flg[h] <= 1'b0; + else if (unseg_blk_end_flg[h]) + if (|unseg_blk_end_buf[h-1] && |unseg_val_buf[h-1] && unseg_buf_rd_en_c[h-1]) + unseg_blk_end_flg[h] <= 1'b0; + else + unseg_blk_end_flg[h] <= unseg_blk_end_flg[h]; + else if (|unseg_blk_end_buf[h] && |unseg_val_buf[h] && unseg_buf_rd_en_c[h]) + if (|unseg_blk_end_buf[h-1] && |unseg_val_buf[h-1] && unseg_buf_rd_en_c[h-1]) + unseg_blk_end_flg[h] <= 1'b0; + else if (unseg_blk_end_flg[h-1]) + unseg_blk_end_flg[h] <= 1'b0; + else + unseg_blk_end_flg[h] <= 1'b1; + else + unseg_blk_end_flg[h] <= unseg_blk_end_flg[h]; + end +end +endgenerate + +`endif + +`ifdef en_axis1 + +genvar h0; +generate +for (h0=0; h0<`num_axis_ports; h0=h0+1) begin + if (h0 == 0) + assign unseg_blk_end_buf_val[h0] = (unseg_blk_end_flg[h0+1] && (|unseg_blk_end_buf[h0] && unseg_buf_rd_en_c[h0] && |unseg_val_buf[h0])) ? 1'b1 : (|unseg_blk_end_buf[h0] && unseg_buf_rd_en_c[h0] && |unseg_val_buf[h0] && !(|unseg_val_buf[h0+1])) ? 1'b1 : (|unseg_blk_end_buf[h0] & unseg_buf_rd_en_c[h0] & |unseg_val_buf[h0]) & (|unseg_blk_end_buf[h0+1] & unseg_buf_rd_en_c[h0+1] & |unseg_val_buf[h0+1]); + else + assign unseg_blk_end_buf_val[h0] = (unseg_blk_end_flg[h0-1] && (|unseg_blk_end_buf[h0] && unseg_buf_rd_en_c[h0] && |unseg_val_buf[h0])) ? 1'b1 : (|unseg_blk_end_buf[h0] && unseg_buf_rd_en_c[h0] && |unseg_val_buf[h0] && !(|unseg_val_buf[h0-1])) ? 1'b1 : (|unseg_blk_end_buf[h0] & unseg_buf_rd_en_c[h0] & |unseg_val_buf[h0]) & (|unseg_blk_end_buf[h0-1] & unseg_buf_rd_en_c[h0-1] & |unseg_val_buf[h0-1]); +end +endgenerate + +`else + assign unseg_blk_end_buf_val[0] = (|unseg_blk_end_buf[0] & |unseg_val_buf[0]); +`endif + +assign unseg_pkt_blk_end = |unseg_blk_end_buf_val; + +genvar hh; + +`ifdef en_axis1 + +generate +for (hh=0; hh < (pkt_array_depth/2); hh = hh+1) begin + always @ (posedge aclk_axis_unseg) begin + if (pkt_port_sel) begin + seg_data_array[hh] <= unseg_dat_buf[1][hh]; + seg_mty_array[hh] <= unseg_mty_buf[1][hh]; + seg_val_array[hh] <= unseg_val_buf[1][hh] & unseg_buf_rd_en_c[1]; + seg_sop_array[hh] <= unseg_sop_buf[1][hh]; + seg_eop_array[hh] <= unseg_eop_buf[1][hh]; + seg_err_array[hh] <= unseg_err_buf[1][hh]; + seg_blk_end_array[hh] <= unseg_blk_end_buf[1][hh] & unseg_blk_end_buf_val[1]; + seg_data_array[hh+(pkt_array_depth/2)] <= unseg_dat_buf[0][hh]; + seg_mty_array[hh+(pkt_array_depth/2)] <= unseg_mty_buf[0][hh]; + seg_val_array[hh+(pkt_array_depth/2)] <= unseg_val_buf[0][hh] & unseg_buf_rd_en_c[0]; + seg_sop_array[hh+(pkt_array_depth/2)] <= unseg_sop_buf[0][hh]; + seg_eop_array[hh+(pkt_array_depth/2)] <= unseg_eop_buf[0][hh]; + seg_err_array[hh+(pkt_array_depth/2)] <= unseg_err_buf[0][hh]; + seg_blk_end_array[hh+(pkt_array_depth/2)] <= unseg_blk_end_buf[0][hh] & unseg_blk_end_buf_val[0]; + end else begin + seg_data_array[hh] <= unseg_dat_buf[0][hh]; + seg_mty_array[hh] <= unseg_mty_buf[0][hh]; + seg_val_array[hh] <= unseg_val_buf[0][hh] & unseg_buf_rd_en_c[0]; + seg_sop_array[hh] <= unseg_sop_buf[0][hh]; + seg_eop_array[hh] <= unseg_eop_buf[0][hh]; + seg_err_array[hh] <= unseg_err_buf[0][hh]; + seg_blk_end_array[hh] <= unseg_blk_end_buf[0][hh] & unseg_blk_end_buf_val[0]; + seg_data_array[hh+(pkt_array_depth/2)] <= unseg_dat_buf[1][hh]; + seg_mty_array[hh+(pkt_array_depth/2)] <= unseg_mty_buf[1][hh]; + seg_val_array[hh+(pkt_array_depth/2)] <= unseg_val_buf[1][hh] & unseg_buf_rd_en_c[1]; + seg_sop_array[hh+(pkt_array_depth/2)] <= unseg_sop_buf[1][hh]; + seg_eop_array[hh+(pkt_array_depth/2)] <= unseg_eop_buf[1][hh]; + seg_err_array[hh+(pkt_array_depth/2)] <= unseg_err_buf[1][hh]; + seg_blk_end_array[hh+(pkt_array_depth/2)] <= unseg_blk_end_buf[1][hh] & unseg_blk_end_buf_val[1]; + end + end +end +endgenerate + +`else + +generate +for (hh=0; hh < pkt_array_depth; hh = hh+1) begin + always @ (posedge aclk_axis_unseg) begin + seg_data_array[hh] <= unseg_dat_buf[0][hh]; + seg_mty_array[hh] <= unseg_mty_buf[0][hh]; + seg_val_array[hh] <= unseg_val_buf[0][hh] & unseg_buf_rd_en_c[0]; + seg_sop_array[hh] <= unseg_sop_buf[0][hh]; + seg_eop_array[hh] <= unseg_eop_buf[0][hh]; + seg_err_array[hh] <= unseg_err_buf[0][hh]; + seg_blk_end_array[hh] <= unseg_blk_end_buf[0][hh]; + end +end +endgenerate + +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Segment array + +// Pack the segments + +reg [`segment_width-1:0] pkt_data_array [(pkt_array_depth*2)-1:0]; +reg [seg_mty_w-1:0] pkt_mty_array [(pkt_array_depth*2)-1:0]; +reg [(pkt_array_depth*2)-1:0] pkt_val_array0; +reg [(pkt_array_depth*2)-1:0] pkt_val_array00; +reg [(pkt_array_depth*2)-1:0] pkt_val_array1; +reg [(pkt_array_depth*2)-1:0] pkt_val_array2; +reg [(pkt_array_depth*2)-1:0] pkt_val_array; +reg [(pkt_array_depth*2)-1:0] pkt_sop_array; +reg [(pkt_array_depth*2)-1:0] pkt_eop_array; +reg [(pkt_array_depth*2)-1:0] pkt_err_array; +reg [(pkt_array_depth*2)-1:0] pkt_blk_end_array; +reg [(pkt_array_depth*2)-1:0] pkt_blk_end_array1; + +reg [$clog2((pkt_array_depth*2))-1:0] pkt_seg_sel_reg [(pkt_array_depth*2)-1:0]; +reg [$clog2((pkt_array_depth*2))-1:0] pkt_seg_sel_reg1 [(pkt_array_depth*2)-1:0]; + +wire pkt_arry_clr_p0; +wire pkt_arry_clr_p1; +wire pkt_arry_clr_p2; +wire pkt_arry_clr_p3; + +reg [$clog2((pkt_array_depth*2))-1:0] pkt_array_ptr1; +reg [$clog2((pkt_array_depth*2))-1:0] pkt_array_ptr2; + +wire p0_flushout_c; +wire p1_flushout_c; +wire p2_flushout_c; +wire p3_flushout_c; + +assign p0_flushout_c = pkt_val_array1[0] & |(pkt_blk_end_array1[((pkt_array_depth/2)*1)-1:0]); +assign p1_flushout_c = pkt_val_array1[((pkt_array_depth/2)*1)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*2)-1:(pkt_array_depth/2)*1]); +assign p2_flushout_c = pkt_val_array1[((pkt_array_depth/2)*2)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*3)-1:(pkt_array_depth/2)*2]); +assign p3_flushout_c = pkt_val_array1[((pkt_array_depth/2)*3)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*4)-1:(pkt_array_depth/2)*3]); + +assign pkt_arry_clr_p0 = pkt_val_array1[((pkt_array_depth/2)*1)-1] | (pkt_val_array1[0] & |(pkt_blk_end_array1[((pkt_array_depth/2)*1)-1:0])); +assign pkt_arry_clr_p1 = pkt_val_array1[((pkt_array_depth/2)*2)-1] | (pkt_val_array1[((pkt_array_depth/2)*1)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*2)-1:(pkt_array_depth/2)*1])); +assign pkt_arry_clr_p2 = pkt_val_array1[((pkt_array_depth/2)*3)-1] | (pkt_val_array1[((pkt_array_depth/2)*2)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*3)-1:(pkt_array_depth/2)*2])); +assign pkt_arry_clr_p3 = pkt_val_array1[((pkt_array_depth/2)*4)-1] | (pkt_val_array1[((pkt_array_depth/2)*3)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*4)-1:(pkt_array_depth/2)*3])); + +wire pkt_array_rst; +wire pkt_seg_sel_reg_rst; + +assign pkt_array_rst = !aresetn_axis_unseg | p0_flushout_c | p1_flushout_c | p2_flushout_c | p3_flushout_c; +assign pkt_seg_sel_reg_rst = !aresetn_axis_unseg | p0_flushout_c | p1_flushout_c | p2_flushout_c | p3_flushout_c; + +integer i, ii; +generate + always @ (posedge aclk_axis_unseg) begin + if (pkt_array_rst) begin + pkt_array_ptr1 = 0; + for(i=0; i < pkt_array_depth*2; i = i+1) begin + pkt_val_array0 [i] <= 1'b0; + pkt_val_array1 [i] <= 1'b0; + pkt_blk_end_array1 [i] <= 1'b0; + end + end else begin + for(i=0; i eop_cnt) + pkt_open <= 1'b1; + else + pkt_open <= 1'b0; + else + pkt_open <= pkt_open; +end + +assign error_broken_pkt0 = pkt_open & ~unseg_val0_q; // Indicates a missing eop + +integer z0; + +reg error_broken_pkt1; + +reg last_seg_eop; + +always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) begin + error_broken_pkt1 <= 1'b0; + last_seg_eop = 1'b1; + end else begin + for (z0=0; z0<`num_segments; z0=z0+1) begin + if (unseg2seg_out_Val[z0] & seg_buf_out_rd_en) begin + if (unseg2seg_out_Sop[z0] && !last_seg_eop) begin // indicates a gap between eop & next sop within valid segments + error_broken_pkt1 = 1'b1; // packet get corrupted + end else if (unseg2seg_out_Sop[z0] && last_seg_eop) begin // next valid packet boundary detected + error_broken_pkt1 = 1'b0; + end else begin + error_broken_pkt1 = error_broken_pkt1; + end + last_seg_eop = unseg2seg_out_Eop[z0]; + end + end + end +end + +// #3 Corrupted data/mty values + +reg err_data_mismatch; +reg [15:0] seg_last_data; +reg err_mty_nonzero; + +integer z1; + +always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) begin + err_data_mismatch = 1'b0; + seg_last_data = 'd0; + err_mty_nonzero = 1'b0; + end else begin + for (z1=0; z1<`num_segments; z1=z1+1) begin + if (unseg2seg_out_Val[z1] & seg_buf_out_rd_en) begin + if(unseg2seg_out_Dat[z1][15:0] - seg_last_data != 15'h0001) begin + err_data_mismatch = 1'b1; + end else begin + err_data_mismatch = 1'b0; + end + seg_last_data = unseg2seg_out_Dat[z1][15:0]; + if(!unseg2seg_out_Eop[z1] && |unseg2seg_out_Mty[z1]) begin + err_mty_nonzero = 1'b1; + end else begin + err_mty_nonzero = 1'b0; + end + end + end + end +end + +// in the below assignment "err_data_mismatch" could be included only when checking with incrementing/counter data as packet input and at less rate(flow_control disabled) + +assign error_broken_pkt_out = error_broken_pkt0 | error_broken_pkt1 | err_mty_nonzero; // | err_data_mismatch; + +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Port Statistics + +`ifdef statistics_en + localparam statistics_en = 1; +`else + localparam statistics_en = 0; +`endif + +generate + +if (statistics_en) begin + +//----------------- Ouput packet count + +reg [63:0] segment_pkt_cnt [`num_segments-1:0]; +reg [63:0] segment_err_cnt [`num_segments-1:0]; +reg [63:0] segment_pkt_sop_cnt [`num_segments-1:0]; +reg [63:0] segment_byte_cnt [`num_segments-1:0]; +wire [($clog2(`segment_width/8)):0] segment_validbytes [`num_segments-1:0]; +reg [63:0] total_pktout_cnt; +reg [63:0] total_err_pktout_cnt; +reg [63:0] total_pktout_byte_cnt; + +genvar ab; + +for (ab=0; ab<`num_segments; ab=ab+1) begin + mty_to_validbytes u_mty_to_valbytes + ( + .mty_in(unseg2seg_out_Mty[ab]), + .valid_bytes_out(segment_validbytes[ab]) + ); +end + +genvar cd; + +for (cd=0; cd<`num_segments; cd=cd+1) begin + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_byte_cnt[cd] <= 'd0; + else if (unseg2seg_out_Val[cd] & seg_data_out_valid & seg_buf_out_rd_en) + segment_byte_cnt[cd] <= segment_byte_cnt[cd] + segment_validbytes[cd]; + end +end + +integer ef; + +always @ (*) begin + total_pktout_byte_cnt = 'd0; + for (ef=0; ef<`num_segments; ef=ef+1) begin + total_pktout_byte_cnt = total_pktout_byte_cnt + segment_byte_cnt[ef]; + end +end + +genvar gh; + +for (gh=0; gh<`num_segments; gh=gh+1) begin + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_pkt_cnt[gh] <= 'd0; + else if (unseg2seg_out_Val[gh] && seg_data_out_valid && unseg2seg_out_Eop[gh] && seg_buf_out_rd_en) + segment_pkt_cnt[gh] <= segment_pkt_cnt[gh] + 1; + end + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_err_cnt[gh] <= 'd0; + else if (unseg2seg_out_Val[gh] && seg_data_out_valid && unseg2seg_out_Eop[gh] && unseg2seg_out_Err[gh] && seg_buf_out_rd_en) + segment_err_cnt[gh] <= segment_err_cnt[gh] + 1; + end +end + +integer ij; + +always @ (*) begin + total_pktout_cnt = 'd0; + total_err_pktout_cnt = 'd0; + for (ij=0; ij<`num_segments; ij=ij+1) begin + total_pktout_cnt = total_pktout_cnt + segment_pkt_cnt[ij]; + total_err_pktout_cnt = total_err_pktout_cnt + segment_err_cnt[ij]; + end +end + +//----------------- Input packet count + +reg [63:0] port_pkt_in_cnt [`num_axis_ports-1:0]; +reg [63:0] port_err_pkt_in_cnt [`num_axis_ports-1:0]; +reg [63:0] port_pkt_in_byte_cnt [`num_axis_ports-1:0]; +reg [63:0] total_pktin_cnt; +reg [63:0] total_err_pktin_cnt; +reg [63:0] total_pktin_byte_cnt; + +wire [($clog2(`unseg_axis_w/8)):0] port_valid_bytes [`num_axis_ports-1:0]; + +genvar g; +for (g=0; g<`num_axis_ports; g=g+1) begin + tkeep_to_validbytes u_tkeep_to_valbytes + ( + .tkeep_in(s_axis_tkeep_in[g]), + .valid_bytes_out(port_valid_bytes[g]) + ); +end + +genvar i; +for (i=0; i<`num_axis_ports; i=i+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_pkt_in_cnt[i] <= 'd0; + else if (s_axis_tvalid_in[i] && (s_axis_tready_in[i] && !axis_pkt_blk_rdy_flg) && s_axis_tlast_in[i]) + port_pkt_in_cnt[i] <= port_pkt_in_cnt[i] + 'd1; + end + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_err_pkt_in_cnt[i] <= 'd0; + else if (s_axis_tvalid_in[i] && (s_axis_tready_in[i] && !axis_pkt_blk_rdy_flg) && s_axis_tlast_in[i] && s_axis_tuser_in[i]) + port_err_pkt_in_cnt[i] <= port_err_pkt_in_cnt[i] + 'd1; + end +end + +genvar j; +for (j=0; j<`num_axis_ports; j=j+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_pkt_in_byte_cnt[j] <= 'd0; + else if (s_axis_tvalid_in[j] && (s_axis_tready_in[j] && !axis_pkt_blk_rdy_flg)) + port_pkt_in_byte_cnt[j] <= port_pkt_in_byte_cnt[j] + port_valid_bytes[j]; + end +end + +integer k; +always @ (*) begin + total_pktin_cnt = 'd0; + total_err_pktin_cnt = 'd0; + total_pktin_byte_cnt = 'd0; + for (k=0; k<`num_axis_ports; k=k+1) begin + total_pktin_cnt = total_pktin_cnt + port_pkt_in_cnt[k]; + total_err_pktin_cnt = total_err_pktin_cnt + port_err_pkt_in_cnt[k]; + total_pktin_byte_cnt = total_pktin_byte_cnt + port_pkt_in_byte_cnt[k]; + end +end + +assign total_pkt_in_cnt = total_pktin_cnt; +assign total_err_pkt_in_cnt = total_err_pktin_cnt; +assign total_pkt_in_byte_cnt = total_pktin_byte_cnt; +assign total_pkt_out_cnt = total_pktout_cnt; +assign total_err_pkt_out_cnt = total_err_pktout_cnt; +assign total_pkt_out_byte_cnt = total_pktout_byte_cnt; +`ifdef en_axis1 +assign p1_pkt_in_cnt = port_pkt_in_cnt[1]; +assign p1_err_pkt_in_cnt = port_err_pkt_in_cnt[1]; +assign p1_pkt_in_byte_cnt = port_pkt_in_byte_cnt[1]; +assign p0_pkt_in_cnt = port_pkt_in_cnt[0]; +assign p0_err_pkt_in_cnt = port_err_pkt_in_cnt[0]; +assign p0_pkt_in_byte_cnt = port_pkt_in_byte_cnt[0]; +`endif + +end +endgenerate + +endmodule + +//----------------------------------------------------------------------------------------------------------------------- + +module tkeep_to_mty + ( + input [(`segment_width/8)-1:0] tkeep_in, + output wire [($clog2(`segment_width/8))-1:0] mty_out + ); + +integer i; +reg [($clog2(`segment_width/8)):0] valid; + +always @ (tkeep_in) begin + valid = 0; + for (i=0; i<(`segment_width/8); i=i+1) + valid = valid + tkeep_in[i]; +end + +assign mty_out = (`segment_width/8) - valid; + +endmodule + +//----------------------------------------------------------------------------------------------------------------------- +//----------------------------------------------------------------------------------------------------------------------- + diff --git a/submodules/v80-vitis-flow/resources/dcmac/hdl/clock_to_clock_bus.v b/submodules/v80-vitis-flow/resources/dcmac/hdl/clock_to_clock_bus.v new file mode 100644 index 00000000..3410398d --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/hdl/clock_to_clock_bus.v @@ -0,0 +1,14 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +`timescale 1ns / 1ps + +module clock_to_clock_bus ( + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) + input clk, + output wire [5:0] clockbus + ); + + assign clockbus = {6{clk}}; + +endmodule \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/dcmac/hdl/dcmac200g_ctl_port.v b/submodules/v80-vitis-flow/resources/dcmac/hdl/dcmac200g_ctl_port.v new file mode 100644 index 00000000..8cc38c77 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/hdl/dcmac200g_ctl_port.v @@ -0,0 +1,54 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +`timescale 1ps/1ps + +module dcmac200g_ctl_port ( + output wire [15:0] default_vl_length_100GE, + output wire [15:0] default_vl_length_200GE_or_400GE, + output wire [63:0] ctl_tx_vl_marker_id0, + output wire [63:0] ctl_tx_vl_marker_id1, + output wire [63:0] ctl_tx_vl_marker_id2, + output wire [63:0] ctl_tx_vl_marker_id3, + output wire [63:0] ctl_tx_vl_marker_id4, + output wire [63:0] ctl_tx_vl_marker_id5, + output wire [63:0] ctl_tx_vl_marker_id6, + output wire [63:0] ctl_tx_vl_marker_id7, + output wire [63:0] ctl_tx_vl_marker_id8, + output wire [63:0] ctl_tx_vl_marker_id9, + output wire [63:0] ctl_tx_vl_marker_id10, + output wire [63:0] ctl_tx_vl_marker_id11, + output wire [63:0] ctl_tx_vl_marker_id12, + output wire [63:0] ctl_tx_vl_marker_id13, + output wire [63:0] ctl_tx_vl_marker_id14, + output wire [63:0] ctl_tx_vl_marker_id15, + output wire [63:0] ctl_tx_vl_marker_id16, + output wire [63:0] ctl_tx_vl_marker_id17, + output wire [63:0] ctl_tx_vl_marker_id18, + output wire [63:0] ctl_tx_vl_marker_id19 +); + + assign default_vl_length_100GE = 16'd255; + assign default_vl_length_200GE_or_400GE = 16'd256; + assign ctl_tx_vl_marker_id0 = 64'hc16821003e97de00; + assign ctl_tx_vl_marker_id1 = 64'h9d718e00628e7100; + assign ctl_tx_vl_marker_id2 = 64'h594be800a6b41700; + assign ctl_tx_vl_marker_id3 = 64'h4d957b00b26a8400; + assign ctl_tx_vl_marker_id4 = 64'hf50709000af8f600; + assign ctl_tx_vl_marker_id5 = 64'hdd14c20022eb3d00; + assign ctl_tx_vl_marker_id6 = 64'h9a4a260065b5d900; + assign ctl_tx_vl_marker_id7 = 64'h7b45660084ba9900; + assign ctl_tx_vl_marker_id8 = 64'ha02476005fdb8900; + assign ctl_tx_vl_marker_id9 = 64'h68c9fb0097360400; + assign ctl_tx_vl_marker_id10 = 64'hfd6c990002936600; + assign ctl_tx_vl_marker_id11 = 64'hb9915500466eaa00; + assign ctl_tx_vl_marker_id12 = 64'h5cb9b200a3464d00; + assign ctl_tx_vl_marker_id13 = 64'h1af8bd00e5074200; + assign ctl_tx_vl_marker_id14 = 64'h83c7ca007c383500; + assign ctl_tx_vl_marker_id15 = 64'h3536cd00cac93200; + assign ctl_tx_vl_marker_id16 = 64'hc4314c003bceb300; + assign ctl_tx_vl_marker_id17 = 64'hadd6b70052294800; + assign ctl_tx_vl_marker_id18 = 64'h5f662a00a099d500; + assign ctl_tx_vl_marker_id19 = 64'hc0f0e5003f0f1a00; + +endmodule \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/dcmac/hdl/serdes_clock.v b/submodules/v80-vitis-flow/resources/dcmac/hdl/serdes_clock.v new file mode 100644 index 00000000..3d1eec10 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/hdl/serdes_clock.v @@ -0,0 +1,14 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +`timescale 1ns / 1ps + +module clock_to_serdes ( + input usrclk, + (* X_INTERFACE_INFO = "xilinx.com:signal:gt_usrclk:1.0 GT_USRCLK.RX_ALT_SERDES_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME GT_USRCLK.RX_ALT_SERDES_CLK, CLK_DOMAIN dcmac_200g_exdes_support_rx_alt_serdes_clk, FREQ_HZ 156250000, PARENT_ID undef, PHASE 0.0" *) + output wire [5:0] serdes_clk + ); + + assign serdes_clk = {1'b0, 1'b0, 1'b0, 1'b0, usrclk, usrclk}; + +endmodule \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/dcmac/hdl/syncer_reset.v b/submodules/v80-vitis-flow/resources/dcmac/hdl/syncer_reset.v new file mode 100644 index 00000000..1b0e5933 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/hdl/syncer_reset.v @@ -0,0 +1,37 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +`timescale 1ps/1ps + +module dcmac_syncer_reset #( + parameter RESET_PIPE_LEN = 3 +) +( + input wire clk, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 clk_wizard_lock,resetn_async RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input wire clk_wizard_lock, + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input wire resetn_async, + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + output wire resetn +); + + (* ASYNC_REG = "TRUE" *) reg [RESET_PIPE_LEN-1:0] reset_pipe_retime; + reg reset_pipe_out = 1'b0; + assign resetn_async_inv = resetn_async & clk_wizard_lock; + + always @(posedge clk or negedge resetn_async_inv) begin + if (resetn_async_inv == 1'b0) begin + reset_pipe_retime <= {RESET_PIPE_LEN{1'b0}}; + reset_pipe_out <= 1'b0; + end + else begin + reset_pipe_retime <= {reset_pipe_retime[RESET_PIPE_LEN-2:0], 1'b1}; + reset_pipe_out <= reset_pipe_retime[RESET_PIPE_LEN-1]; + end + end + + assign resetn = reset_pipe_out; + +endmodule \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/dcmac/tcl/dcmac.tcl b/submodules/v80-vitis-flow/resources/dcmac/tcl/dcmac.tcl new file mode 100644 index 00000000..01065d89 --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/tcl/dcmac.tcl @@ -0,0 +1,1413 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +# hdl files from resources will be available in this script when running at "$src_dir/dcmac/hdl/..." + + +# Hierarchical cell: dcmac_gt_wrapper +proc create_hier_cell_dcmac_gt_wrapper { parentCell nameHier dcmac_index dual_dcmac } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_dcmac_gt_wrapper() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp_clk_322mhz + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX0_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX1_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX2_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX3_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX0_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX1_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX2_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX3_GT0_IP_Interface + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 GT0_Serial + + if { ${dual_dcmac} == "1" } { + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX0_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX1_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX2_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX3_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX0_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX1_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX2_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX3_GT1_IP_Interface + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 GT1_Serial + } + + # Create pins + create_bd_pin -dir I -from 0 -to 0 MBUFG_GT_CLR + create_bd_pin -dir I -from 0 -to 0 MBUFG_GT_CLRB_LEAF + create_bd_pin -dir O -from 0 -to 0 -type gt_usrclk qsfp0_rx_usr_clk_664mhz + create_bd_pin -dir O -from 0 -to 0 -type gt_usrclk qsfp0_rx_usr_clk_332mhz + create_bd_pin -dir I -from 0 -to 0 MBUFG_GT_CLR1 + create_bd_pin -dir I -from 0 -to 0 MBUFG_GT_CLRB_LEAF1 + create_bd_pin -dir O -from 0 -to 0 -type gt_usrclk qsfp0_tx_usr_clk_664mhz + create_bd_pin -dir O -from 0 -to 0 -type gt_usrclk qsfp0_tx_usr_clk_332mhz + create_bd_pin -dir I -type rst hsclk_pllreset0 + create_bd_pin -dir O hsclk_plllock0 + create_bd_pin -dir O gtpowergood_0 + create_bd_pin -dir I -type rst gt0_ch0_iloreset + create_bd_pin -dir I -type rst gt0_ch1_iloreset + create_bd_pin -dir I -type rst gt0_ch2_iloreset + create_bd_pin -dir I -type rst gt0_ch3_iloreset + create_bd_pin -dir O gt0_ch0_iloresetdone + create_bd_pin -dir O gt0_ch1_iloresetdone + create_bd_pin -dir O gt0_ch2_iloresetdone + create_bd_pin -dir O gt0_ch3_iloresetdone + create_bd_pin -dir I -type clk apb3clk_quad + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -type gt_usrclk GT0_ref_clk + create_bd_pin -dir I -from 31 -to 0 gt_control_pins + + if { ${dual_dcmac} == "1" } { + create_bd_pin -dir I -type rst hsclk_pllreset1 + create_bd_pin -dir O hsclk_plllock1 + create_bd_pin -dir I -type rst gt1_ch0_iloreset + create_bd_pin -dir I -type rst gt1_ch1_iloreset + create_bd_pin -dir I -type rst gt1_ch2_iloreset + create_bd_pin -dir I -type rst gt1_ch3_iloreset + create_bd_pin -dir O gt1_ch0_iloresetdone + create_bd_pin -dir O gt1_ch1_iloresetdone + create_bd_pin -dir O gt1_ch2_iloresetdone + create_bd_pin -dir O gt1_ch3_iloresetdone + create_bd_pin -dir O gtpowergood_1 + } + + # Create instance: util_ds_buf_0, and set properties + set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_0 ] + set_property CONFIG.C_BUF_TYPE {IBUFDS_GTME5} $util_ds_buf_0 + + set top_dcmac_name "top_dcmac_${dcmac_index}_core_0" + set dcmac_name "dcmac_${dcmac_index}_core" + + set list_quad_index { 0 } + if { ${dual_dcmac} == "1" } { + lappend list_quad_index 1 + } + + foreach idx ${list_quad_index} { + # Create instance: gt0_quad, and set properties + set quad_name "gt${idx}_quad" + set gt_quad [ create_bd_cell -type ip -vlnv xilinx.com:ip:gt_quad_base ${quad_name} ] + + set channel_ordering {} + foreach dirid {TX RX} { + for {set lane 0} {$lane < 4} {incr lane} { + set new_idx ${lane} + if { ${idx} == "1" } { + set new_idx "[expr {$lane + 4}]" + } + + set ord " ${oldCurInst}/${quad_name}/${dirid}${lane}_GT_IP_Interface top_dcmac_${idx}_core_0.${oldCurInst}/dcmac_${idx}_core/gtm_tx_serdes_interface_${new_idx}.${new_idx}" + append channel_ordering ${ord} + } + } + + set quad_usage {} + foreach dirid {TX_QUAD_CH RX_QUAD_CH} { + set list_quad_index_ii { 0 } + if { ${dual_dcmac} == "1" } { + lappend list_quad_index_ii 1 + } + append quad_usage " ${dirid} {" + foreach idxii ${list_quad_index_ii} { + set quad_name_ii "gt${idxii}_quad" + set q0 [expr {${idx} == ${idxii}}] + #set q1 [expr {!$q0}] + if { ${idxii} == "0" } { + set conf " ${oldCurInst}/dcmac_gt${idxii}_wrapper/${quad_name_ii} {${oldCurInst}/dcmac_gt${dcmac_index}_wrapper/${quad_name_ii}\ + top_dcmac_${dcmac_index}_core_0.IP_CH0,top_dcmac_${dcmac_index}_core_0.IP_CH1,top_dcmac_${dcmac_index}_core_0.IP_CH2,top_dcmac_${dcmac_index}_core_0.IP_CH3 MSTRCLK 1,0,0,0 IS_CURRENT_QUAD ${q0}}" + } else { + set conf " ${oldCurInst}/dcmac_gt${idxii}_wrapper/${quad_name_ii} {${oldCurInst}/dcmac_gt${dcmac_index}_wrapper/${quad_name_ii}\ + top_dcmac_${dcmac_index}_core_0.IP_CH4,top_dcmac_${dcmac_index}_core_0.IP_CH5,top_dcmac_${dcmac_index}_core_0.IP_CH6,top_dcmac_${dcmac_index}_core_0.IP_CH7 MSTRCLK 1,0,0,0 IS_CURRENT_QUAD ${q0}}" + } + append quad_usage "${conf}" + } + append quad_usage "}" + } + + set_property -dict [list \ + CONFIG.APB3_CLK_FREQUENCY {100.0} \ + CONFIG.CHANNEL_ORDERING {${channel_ordering}} \ + CONFIG.GT_TYPE {GTM} \ + CONFIG.PORTS_INFO_DICT {LANE_SEL_DICT {PROT0 {RX0 RX1 RX2 RX3 TX0 TX1 TX2 TX3}} GT_TYPE GTM REG_CONF_INTF APB3_INTF BOARD_PARAMETER { }} \ + CONFIG.PROT0_ENABLE {true} \ + CONFIG.PROT0_GT_DIRECTION {DUPLEX} \ + CONFIG.PROT0_LR0_SETTINGS {GT_DIRECTION DUPLEX TX_PAM_SEL PAM4 TX_HD_EN 0 TX_GRAY_BYP false TX_GRAY_LITTLEENDIAN false TX_PRECODE_BYP true TX_PRECODE_LITTLEENDIAN false TX_LINE_RATE 53.125 TX_PLL_TYPE\ +LCPLL TX_REFCLK_FREQUENCY 322.265625 TX_ACTUAL_REFCLK_FREQUENCY 322.265625183611 TX_FRACN_ENABLED true TX_FRACN_OVRD false TX_FRACN_NUMERATOR 0 TX_REFCLK_SOURCE R0 TX_DATA_ENCODING RAW TX_USER_DATA_WIDTH\ +160 TX_INT_DATA_WIDTH 128 TX_BUFFER_MODE 1 TX_BUFFER_BYPASS_MODE Fast_Sync TX_PIPM_ENABLE false TX_OUTCLK_SOURCE TXPROGDIVCLK TXPROGDIV_FREQ_ENABLE true TXPROGDIV_FREQ_SOURCE LCPLL TXPROGDIV_FREQ_VAL 664.062\ +TX_DIFF_SWING_EMPH_MODE CUSTOM TX_64B66B_SCRAMBLER false TX_64B66B_ENCODER false TX_64B66B_CRC false TX_RATE_GROUP A TX_LANE_DESKEW_HDMI_ENABLE false TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE PRESET GTM-PAM4_Ethernet_53G\ +RX_PAM_SEL PAM4 RX_HD_EN 0 RX_GRAY_BYP false RX_GRAY_LITTLEENDIAN false RX_PRECODE_BYP true RX_PRECODE_LITTLEENDIAN false INTERNAL_PRESET PAM4_Ethernet_53G RX_LINE_RATE 53.125 RX_PLL_TYPE LCPLL RX_REFCLK_FREQUENCY\ +322.265625 RX_ACTUAL_REFCLK_FREQUENCY 322.265625183611 RX_FRACN_ENABLED true RX_FRACN_OVRD false RX_FRACN_NUMERATOR 0 RX_REFCLK_SOURCE R0 RX_DATA_DECODING RAW RX_USER_DATA_WIDTH 160 RX_INT_DATA_WIDTH 128\ +RX_BUFFER_MODE 1 RX_OUTCLK_SOURCE RXPROGDIVCLK RXPROGDIV_FREQ_ENABLE true RXPROGDIV_FREQ_SOURCE LCPLL RXPROGDIV_FREQ_VAL 664.062 RXRECCLK_FREQ_ENABLE false RXRECCLK_FREQ_VAL 0 INS_LOSS_NYQ 20 RX_EQ_MODE\ +AUTO RX_COUPLING AC RX_TERMINATION VCOM_VREF RX_RATE_GROUP A RX_TERMINATION_PROG_VALUE 800 RX_PPM_OFFSET 200 RX_64B66B_DESCRAMBLER false RX_64B66B_DECODER false RX_64B66B_CRC false OOB_ENABLE false RX_COMMA_ALIGN_WORD\ +1 RX_COMMA_SHOW_REALIGN_ENABLE true PCIE_ENABLE false RX_COMMA_P_ENABLE false RX_COMMA_M_ENABLE false RX_COMMA_DOUBLE_ENABLE false RX_COMMA_P_VAL 0101111100 RX_COMMA_M_VAL 1010000011 RX_COMMA_MASK 0000000000\ +RX_SLIDE_MODE OFF RX_SSC_PPM 0 RX_CB_NUM_SEQ 0 RX_CB_LEN_SEQ 1 RX_CB_MAX_SKEW 1 RX_CB_MAX_LEVEL 1 RX_CB_MASK 00000000 RX_CB_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000\ +RX_CB_K 00000000 RX_CB_DISP 00000000 RX_CB_MASK_0_0 false RX_CB_VAL_0_0 0000000000 RX_CB_K_0_0 false RX_CB_DISP_0_0 false RX_CB_MASK_0_1 false RX_CB_VAL_0_1 0000000000 RX_CB_K_0_1 false RX_CB_DISP_0_1\ +false RX_CB_MASK_0_2 false RX_CB_VAL_0_2 0000000000 RX_CB_K_0_2 false RX_CB_DISP_0_2 false RX_CB_MASK_0_3 false RX_CB_VAL_0_3 0000000000 RX_CB_K_0_3 false RX_CB_DISP_0_3 false RX_CB_MASK_1_0 false RX_CB_VAL_1_0\ +0000000000 RX_CB_K_1_0 false RX_CB_DISP_1_0 false RX_CB_MASK_1_1 false RX_CB_VAL_1_1 0000000000 RX_CB_K_1_1 false RX_CB_DISP_1_1 false RX_CB_MASK_1_2 false RX_CB_VAL_1_2 0000000000 RX_CB_K_1_2 false RX_CB_DISP_1_2\ +false RX_CB_MASK_1_3 false RX_CB_VAL_1_3 0000000000 RX_CB_K_1_3 false RX_CB_DISP_1_3 false RX_CC_NUM_SEQ 0 RX_CC_LEN_SEQ 1 RX_CC_PERIODICITY 5000 RX_CC_KEEP_IDLE DISABLE RX_CC_PRECEDENCE ENABLE RX_CC_REPEAT_WAIT\ +0 RX_CC_MASK 00000000 RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 RX_CC_K 00000000 RX_CC_DISP 00000000 RX_CC_MASK_0_0 false RX_CC_VAL_0_0 0000000000 RX_CC_K_0_0\ +false RX_CC_DISP_0_0 false RX_CC_MASK_0_1 false RX_CC_VAL_0_1 0000000000 RX_CC_K_0_1 false RX_CC_DISP_0_1 false RX_CC_MASK_0_2 false RX_CC_VAL_0_2 0000000000 RX_CC_K_0_2 false RX_CC_DISP_0_2 false RX_CC_MASK_0_3\ +false RX_CC_VAL_0_3 0000000000 RX_CC_K_0_3 false RX_CC_DISP_0_3 false RX_CC_MASK_1_0 false RX_CC_VAL_1_0 0000000000 RX_CC_K_1_0 false RX_CC_DISP_1_0 false RX_CC_MASK_1_1 false RX_CC_VAL_1_1 0000000000\ +RX_CC_K_1_1 false RX_CC_DISP_1_1 false RX_CC_MASK_1_2 false RX_CC_VAL_1_2 0000000000 RX_CC_K_1_2 false RX_CC_DISP_1_2 false RX_CC_MASK_1_3 false RX_CC_VAL_1_3 0000000000 RX_CC_K_1_3 false RX_CC_DISP_1_3\ +false PCIE_USERCLK2_FREQ 250 PCIE_USERCLK_FREQ 250 RX_JTOL_FC 10 RX_JTOL_LF_SLOPE -20 RX_BUFFER_BYPASS_MODE Fast_Sync RX_BUFFER_BYPASS_MODE_LANE MULTI RX_BUFFER_RESET_ON_CB_CHANGE ENABLE RX_BUFFER_RESET_ON_COMMAALIGN\ +DISABLE RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE RESET_SEQUENCE_INTERVAL 0 RX_COMMA_PRESET NONE RX_COMMA_VALID_ONLY 0 GT_TYPE GTM} \ + CONFIG.PROT0_LR10_SETTINGS {NA NA} \ + CONFIG.PROT0_LR11_SETTINGS {NA NA} \ + CONFIG.PROT0_LR12_SETTINGS {NA NA} \ + CONFIG.PROT0_LR13_SETTINGS {NA NA} \ + CONFIG.PROT0_LR14_SETTINGS {NA NA} \ + CONFIG.PROT0_LR15_SETTINGS {NA NA} \ + CONFIG.PROT0_LR1_SETTINGS {NA NA} \ + CONFIG.PROT0_LR2_SETTINGS {NA NA} \ + CONFIG.PROT0_LR3_SETTINGS {NA NA} \ + CONFIG.PROT0_LR4_SETTINGS {NA NA} \ + CONFIG.PROT0_LR5_SETTINGS {NA NA} \ + CONFIG.PROT0_LR6_SETTINGS {NA NA} \ + CONFIG.PROT0_LR7_SETTINGS {NA NA} \ + CONFIG.PROT0_LR8_SETTINGS {NA NA} \ + CONFIG.PROT0_LR9_SETTINGS {NA NA} \ + CONFIG.PROT0_NO_OF_LANES {4} \ + CONFIG.PROT0_RX_MASTERCLK_SRC {RX0} \ + CONFIG.PROT0_TX_MASTERCLK_SRC {TX0} \ + CONFIG.REFCLK_LIST {{/qsfp0_322mhz_clk_p[0]}} \ + CONFIG.REFCLK_STRING {HSCLK0_LCPLLGTREFCLK0 refclk_PROT0_R0_322.265625183611_MHz_unique1} \ + CONFIG.RX0_LANE_SEL {PROT0} \ + CONFIG.RX1_LANE_SEL {PROT0} \ + CONFIG.RX2_LANE_SEL {PROT0} \ + CONFIG.RX3_LANE_SEL {PROT0} \ + CONFIG.TX0_LANE_SEL {PROT0} \ + CONFIG.TX1_LANE_SEL {PROT0} \ + CONFIG.TX2_LANE_SEL {PROT0} \ + CONFIG.TX3_LANE_SEL {PROT0} \ + ] $gt_quad + + #CONFIG.QUAD_USAGE {${quad_usage}} \ + + set_property -dict [list \ + CONFIG.APB3_CLK_FREQUENCY.VALUE_MODE {auto} \ + CONFIG.CHANNEL_ORDERING.VALUE_MODE {auto} \ + CONFIG.GT_TYPE.VALUE_MODE {auto} \ + CONFIG.PROT0_ENABLE.VALUE_MODE {auto} \ + CONFIG.PROT0_GT_DIRECTION.VALUE_MODE {auto} \ + CONFIG.PROT0_LR0_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR10_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR11_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR12_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR13_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR14_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR15_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR1_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR2_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR3_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR4_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR5_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR6_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR7_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR8_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR9_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_NO_OF_LANES.VALUE_MODE {auto} \ + CONFIG.PROT0_RX_MASTERCLK_SRC.VALUE_MODE {auto} \ + CONFIG.PROT0_TX_MASTERCLK_SRC.VALUE_MODE {auto} \ + CONFIG.QUAD_USAGE.VALUE_MODE {auto} \ + CONFIG.REFCLK_LIST.VALUE_MODE {auto} \ + CONFIG.RX0_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.RX1_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.RX2_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.RX3_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.TX0_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.TX1_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.TX2_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.TX3_LANE_SEL.VALUE_MODE {auto} \ + ] $gt_quad + + } + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant xlconstant_0 ] + set_property -dict [list \ + CONFIG.CONST_VAL {1} \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_0 + + # Create instance: bufg_gt_odiv2, and set properties + set bufg_gt_odiv2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:bufg_gt bufg_gt_odiv2 ] + + # Create instance: util_ds_buf_mbufg_rx_0, and set properties + set util_ds_buf_mbufg_rx_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_mbufg_rx_0 ] + set_property -dict [list \ + CONFIG.C_BUFG_GT_SYNC {true} \ + CONFIG.C_BUF_TYPE {MBUFG_GT} \ + ] $util_ds_buf_mbufg_rx_0 + + + # Create instance: util_ds_buf_mbufg_tx_0, and set properties + set util_ds_buf_mbufg_tx_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_mbufg_tx_0 ] + set_property -dict [list \ + CONFIG.C_BUFGCE_DIV {1} \ + CONFIG.C_BUFG_GT_SYNC {true} \ + CONFIG.C_BUF_TYPE {MBUFG_GT} \ + ] $util_ds_buf_mbufg_tx_0 + + + # Create instance: xlslice_gt_txpostcursor, and set properties + set xlslice_gt_txpostcursor [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_txpostcursor ] + set_property -dict [list \ + CONFIG.DIN_FROM {23} \ + CONFIG.DIN_TO {18} \ + ] $xlslice_gt_txpostcursor + + + # Create instance: xlslice_gt_txprecursor, and set properties + set xlslice_gt_txprecursor [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_txprecursor ] + set_property -dict [list \ + CONFIG.DIN_FROM {17} \ + CONFIG.DIN_TO {12} \ + ] $xlslice_gt_txprecursor + + + # Create instance: xlslice_gt_txmaincursor, and set properties + set xlslice_gt_txmaincursor [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_txmaincursor ] + set_property -dict [list \ + CONFIG.DIN_FROM {30} \ + CONFIG.DIN_TO {24} \ + ] $xlslice_gt_txmaincursor + + + # Create instance: xlslice_gt_line_rate, and set properties + set xlslice_gt_line_rate [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_line_rate ] + set_property -dict [list \ + CONFIG.DIN_FROM {8} \ + CONFIG.DIN_TO {1} \ + ] $xlslice_gt_line_rate + + + # Create instance: xlslice_gt_rxcdrhold, and set properties + set xlslice_gt_rxcdrhold [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice: xlslice_gt_rxcdrhold ] + set_property -dict [list \ + CONFIG.DIN_FROM {31} \ + CONFIG.DIN_TO {31} \ + ] $xlslice_gt_rxcdrhold + + + # Create instance: xlslice_gt_loopback, and set properties + set xlslice_gt_loopback [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_loopback ] + set_property -dict [list \ + CONFIG.DIN_FROM {11} \ + CONFIG.DIN_TO {9} \ + ] $xlslice_gt_loopback + + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins qsfp_clk_322mhz] [get_bd_intf_pins util_ds_buf_0/CLK_IN_D1] + + # Create port connections + connect_bd_net [get_bd_pins gt_control_pins] [get_bd_pins xlslice_gt_txpostcursor/Din] [get_bd_pins xlslice_gt_txprecursor/Din] [get_bd_pins xlslice_gt_txmaincursor/Din] [get_bd_pins xlslice_gt_line_rate/Din] [get_bd_pins xlslice_gt_rxcdrhold/Din] [get_bd_pins xlslice_gt_loopback/Din] + connect_bd_net [get_bd_pins bufg_gt_odiv2/usrclk] [get_bd_pins GT0_ref_clk] + connect_bd_net [get_bd_pins MBUFG_GT_CLR] [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_CLR] + connect_bd_net [get_bd_pins MBUFG_GT_CLRB_LEAF] [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_CLRB_LEAF] + connect_bd_net [get_bd_pins MBUFG_GT_CLR1] [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_CLR] + connect_bd_net [get_bd_pins MBUFG_GT_CLRB_LEAF1] [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_CLRB_LEAF] + connect_bd_net [get_bd_pins gt0_quad/ch0_rxoutclk] [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_I] + connect_bd_net [get_bd_pins gt0_quad/ch0_txoutclk] [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_I] + connect_bd_net [get_bd_pins util_ds_buf_0/IBUFDS_GTME5_ODIV2] [get_bd_pins bufg_gt_odiv2/outclk] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_O1] [get_bd_pins qsfp0_rx_usr_clk_664mhz] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_O2] [get_bd_pins qsfp0_rx_usr_clk_332mhz] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_O1] [get_bd_pins qsfp0_tx_usr_clk_664mhz] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_O2] [get_bd_pins qsfp0_tx_usr_clk_332mhz] + connect_bd_net [get_bd_pins xlconstant_0/dout] [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_CE] [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_CE] + + foreach idx ${list_quad_index} { + connect_bd_net [get_bd_pins apb3clk_quad] [get_bd_pins gt${idx}_quad/apb3clk] + connect_bd_net [get_bd_pins gt${idx}_ch0_iloreset] [get_bd_pins gt${idx}_quad/ch0_iloreset] + connect_bd_net [get_bd_pins gt${idx}_ch1_iloreset] [get_bd_pins gt${idx}_quad/ch1_iloreset] + connect_bd_net [get_bd_pins gt${idx}_ch2_iloreset] [get_bd_pins gt${idx}_quad/ch2_iloreset] + connect_bd_net [get_bd_pins gt${idx}_ch3_iloreset] [get_bd_pins gt${idx}_quad/ch3_iloreset] + connect_bd_net [get_bd_pins hsclk_pllreset${idx}] [get_bd_pins gt${idx}_quad/hsclk1_lcpllreset] [get_bd_pins gt${idx}_quad/hsclk0_rpllreset] [get_bd_pins gt${idx}_quad/hsclk1_rpllreset] [get_bd_pins gt${idx}_quad/hsclk0_lcpllreset] + + connect_bd_net [get_bd_pins gt${idx}_quad/ch0_iloresetdone] [get_bd_pins gt${idx}_ch0_iloresetdone] + connect_bd_net [get_bd_pins gt${idx}_quad/ch1_iloresetdone] [get_bd_pins gt${idx}_ch1_iloresetdone] + connect_bd_net [get_bd_pins gt${idx}_quad/ch2_iloresetdone] [get_bd_pins gt${idx}_ch2_iloresetdone] + connect_bd_net [get_bd_pins gt${idx}_quad/ch3_iloresetdone] [get_bd_pins gt${idx}_ch3_iloresetdone] + connect_bd_net [get_bd_pins gt${idx}_quad/gtpowergood] [get_bd_pins gtpowergood_${idx}] + connect_bd_net [get_bd_pins gt${idx}_quad/hsclk0_lcplllock] [get_bd_pins hsclk_plllock${idx}] + connect_bd_net [get_bd_pins xlslice_gt_rxcdrhold/Dout] [get_bd_pins gt${idx}_quad/ch1_rxcdrhold] [get_bd_pins gt${idx}_quad/ch2_rxcdrhold] [get_bd_pins gt${idx}_quad/ch3_rxcdrhold] [get_bd_pins gt${idx}_quad/ch0_rxcdrhold] + connect_bd_net [get_bd_pins xlslice_gt_txmaincursor/Dout] [get_bd_pins gt${idx}_quad/ch1_txmaincursor] [get_bd_pins gt${idx}_quad/ch2_txmaincursor] [get_bd_pins gt${idx}_quad/ch3_txmaincursor] [get_bd_pins gt${idx}_quad/ch0_txmaincursor] + connect_bd_net [get_bd_pins xlslice_gt_txpostcursor/Dout] [get_bd_pins gt${idx}_quad/ch1_txpostcursor] [get_bd_pins gt${idx}_quad/ch2_txpostcursor] [get_bd_pins gt${idx}_quad/ch3_txpostcursor] [get_bd_pins gt${idx}_quad/ch0_txpostcursor] + connect_bd_net [get_bd_pins xlslice_gt_txprecursor/Dout] [get_bd_pins gt${idx}_quad/ch1_txprecursor] [get_bd_pins gt${idx}_quad/ch2_txprecursor] [get_bd_pins gt${idx}_quad/ch3_txprecursor] [get_bd_pins gt${idx}_quad/ch0_txprecursor] + connect_bd_net [get_bd_pins s_axi_aresetn] [get_bd_pins gt${idx}_quad/apb3presetn] + connect_bd_net [get_bd_pins xlslice_gt_line_rate/Dout] [get_bd_pins gt${idx}_quad/ch0_rxrate] [get_bd_pins gt${idx}_quad/ch3_txrate] [get_bd_pins gt${idx}_quad/ch3_rxrate] [get_bd_pins gt${idx}_quad/ch2_txrate] [get_bd_pins gt${idx}_quad/ch2_rxrate] [get_bd_pins gt${idx}_quad/ch1_txrate] [get_bd_pins gt${idx}_quad/ch1_rxrate] [get_bd_pins gt${idx}_quad/ch0_txrate] + connect_bd_net [get_bd_pins xlslice_gt_loopback/Dout] [get_bd_pins gt${idx}_quad/ch3_loopback] [get_bd_pins gt${idx}_quad/ch2_loopback] [get_bd_pins gt${idx}_quad/ch1_loopback] [get_bd_pins gt${idx}_quad/ch0_loopback] + + connect_bd_net [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_O2] [get_bd_pins gt${idx}_quad/ch0_txusrclk] [get_bd_pins gt${idx}_quad/ch1_txusrclk] [get_bd_pins gt${idx}_quad/ch2_txusrclk] [get_bd_pins gt${idx}_quad/ch3_txusrclk] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_O2] [get_bd_pins gt${idx}_quad/ch0_rxusrclk] [get_bd_pins gt${idx}_quad/ch1_rxusrclk] [get_bd_pins gt${idx}_quad/ch2_rxusrclk] [get_bd_pins gt${idx}_quad/ch3_rxusrclk] + connect_bd_net [get_bd_pins util_ds_buf_0/IBUFDS_GTME5_O] [get_bd_pins gt${idx}_quad/GT_REFCLK0] + + connect_bd_intf_net [get_bd_intf_pins RX0_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/RX0_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins RX1_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/RX1_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins RX2_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/RX2_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins RX3_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/RX3_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins TX0_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/TX0_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins TX1_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/TX1_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins TX2_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/TX2_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins TX3_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/TX3_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins GT${idx}_Serial] [get_bd_intf_pins gt${idx}_quad/GT_Serial] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Hierarchical cell: control_intf +proc create_hier_cell_control_intf { parentCell nameHier dual_dcmac} { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_control_intf() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_DCMAC + + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type clk clk_out_390 + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -from 31 -to 0 control_gt_rst + create_bd_pin -dir O -from 31 -to 0 tx_datapath_ctrl + create_bd_pin -dir O -from 31 -to 0 rx_datapath_ctrl + create_bd_pin -dir O -from 31 -to 0 reset_txrx_path + create_bd_pin -dir I -from 7 -to 0 gt0_tx_reset_done + create_bd_pin -dir I -from 7 -to 0 gt0_rx_reset_done + create_bd_pin -dir I -from 1 -to 0 gt0powergood + + # Create instance: smartconnect, and set properties + set smartconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect smartconnect ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {5} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect + + # GT dynamic configuration parameters, setting up sensible values + set txmaincursor 52 + set txprecursor 6 + set txpostcursor 6 + + set gt_conf_value [format 0x%X [expr {(${txmaincursor} << 24) + (${txpostcursor} << 18) + (${txprecursor} << 12)}]] + + # Create instance: axi_gpio_gt_control, and set properties + set axi_gpio_gt_control [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_gt_control ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT ${gt_conf_value} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_gt_control + + # Create instance: axi_gpio_datapath, and set properties + set axi_gpio_datapath [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_datapath ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT {0x00000000} \ + CONFIG.C_ALL_OUTPUTS_2 {1} \ + CONFIG.C_IS_DUAL {1} \ + CONFIG.C_DOUT_DEFAULT_2 {0x00000000} \ + ] $axi_gpio_datapath + + # Create instance: axi_gpio_monitor, and set properties + set axi_gpio_monitor [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_monitor ] + set_property -dict [list \ + CONFIG.C_ALL_INPUTS {1} + ] $axi_gpio_monitor + + # Create instance: axi_gpio_reset_txrx, and set properties + set axi_gpio_reset_txrx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_reset_txrx ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT {0x00000000} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_reset_txrx + + set xlconcat_monitor [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_monitor ] + set_property -dict [list \ + CONFIG.IN0_WIDTH {8} \ + CONFIG.IN1_WIDTH {8} \ + CONFIG.IN2_WIDTH {2} \ + CONFIG.IN3_WIDTH {1} \ + CONFIG.NUM_PORTS {4} \ + ] $xlconcat_monitor + + set dualdcmac [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant dualdcmac ] + set_property CONFIG.CONST_VAL {0} $dualdcmac + + if { ${dual_dcmac} == "1" } { + set_property CONFIG.CONST_VAL {1} $dualdcmac + } + + # Create interface connections + connect_bd_intf_net -intf_net m_axi_0 [get_bd_intf_pins M_AXI_DCMAC] [get_bd_intf_pins smartconnect/M00_AXI] + connect_bd_intf_net -intf_net m_axi_1 [get_bd_intf_pins smartconnect/M01_AXI] [get_bd_intf_pins axi_gpio_datapath/S_AXI] + connect_bd_intf_net -intf_net m_axi_2 [get_bd_intf_pins smartconnect/M02_AXI] [get_bd_intf_pins axi_gpio_gt_control/S_AXI] + connect_bd_intf_net -intf_net m_axi_3 [get_bd_intf_pins smartconnect/M03_AXI] [get_bd_intf_pins axi_gpio_monitor/S_AXI] + connect_bd_intf_net -intf_net m_axi_4 [get_bd_intf_pins smartconnect/M04_AXI] [get_bd_intf_pins axi_gpio_reset_txrx/S_AXI] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins smartconnect/S00_AXI] + + # Create port connections + connect_bd_net -net control_gt_rst_gpio_io_o [get_bd_pins axi_gpio_gt_control/gpio_io_o] [get_bd_pins control_gt_rst] + connect_bd_net -net axi_gpio_datapath_gpio_io_o [get_bd_pins axi_gpio_datapath/gpio_io_o] [get_bd_pins rx_datapath_ctrl] + connect_bd_net -net axi_gpio_datapath_gpio2_io_o [get_bd_pins axi_gpio_datapath/gpio2_io_o] [get_bd_pins tx_datapath_ctrl] + connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins clk_out_390] [get_bd_pins smartconnect/aclk1] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins smartconnect/aclk] [get_bd_pins axi_gpio_datapath/s_axi_aclk] [get_bd_pins axi_gpio_monitor/s_axi_aclk] [get_bd_pins axi_gpio_gt_control/s_axi_aclk] [get_bd_pins axi_gpio_reset_txrx/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins smartconnect/aresetn] [get_bd_pins axi_gpio_datapath/s_axi_aresetn] [get_bd_pins axi_gpio_monitor/s_axi_aresetn] [get_bd_pins axi_gpio_gt_control/s_axi_aresetn] [get_bd_pins axi_gpio_reset_txrx/s_axi_aresetn] + connect_bd_net -net qsfp_leds_gpio_io_o [get_bd_pins axi_gpio_reset_txrx/gpio_io_o] [get_bd_pins reset_txrx_path] + + connect_bd_net [get_bd_pins gt0_tx_reset_done] [get_bd_pins xlconcat_monitor/In0] + connect_bd_net [get_bd_pins gt0_rx_reset_done] [get_bd_pins xlconcat_monitor/In1] + connect_bd_net [get_bd_pins gt0powergood] [get_bd_pins xlconcat_monitor/In2] + connect_bd_net [get_bd_pins xlconcat_monitor/dout] [get_bd_pins axi_gpio_monitor/gpio_io_i] + connect_bd_net [get_bd_pins dualdcmac/dout] [get_bd_pins xlconcat_monitor/In3] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: DCMAC_subsys +proc create_hier_cell_DCMAC_subsys { parentCell nameHier dcmac_index dual_dcmac} { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_DCMAC_subsys() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp_clk_322mhz + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp_gt0 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_0 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_0 + + # Additional interfaces for dual DCMAC + if { ${dual_dcmac} == "1" } { + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp_gt1 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_1 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_1 + } + + # Create pins + create_bd_pin -dir I -from 31 -to 0 control_gt_rst + create_bd_pin -dir I -from 31 -to 0 control_rx_datapath + create_bd_pin -dir I -type clk axi_clk_390mhz + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk core_clk_782mhz + create_bd_pin -dir I -from 5 -to 0 -type clk ts_clk_bus_350mhz + create_bd_pin -dir I -from 31 -to 0 control_tx_datapath + create_bd_pin -dir O -from 7 -to 0 gt0_rx_reset_done + create_bd_pin -dir O -from 7 -to 0 gt0_tx_reset_done + create_bd_pin -dir I -type rst aresetn_rx_390mhz + create_bd_pin -dir I -type rst aresetn_tx_390mhz + create_bd_pin -dir O -type gt_usrclk GT0_ref_clk + create_bd_pin -dir O -from 1 -to 0 gt0powergood + + # Create instance: xlslice_gt_reset, and set properties + set xlslice_gt_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_reset ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + ] $xlslice_gt_reset + + # Create instance: rx_alt_serdes, and set properties + set rx_alt_serdes [create_bd_cell -type module -reference clock_to_serdes rx_alt_serdes] + + # Create instance: xlslice_rx_datapath_2, and set properties + set xlslice_rx_datapath_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_rx_datapath_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + ] $xlslice_rx_datapath_2 + + # Create instance: rx_flexif_clk_clock_bus, and set properties + set rx_flexif_clk_clock_bus [create_bd_cell -type module -reference clock_to_clock_bus rx_flexif_clk_clock_bus] + + # Create instance: tx_alt_serdes, and set properties + set tx_alt_serdes [create_bd_cell -type module -reference clock_to_serdes tx_alt_serdes] + + # Create instance: tx_serdes, and set properties + set tx_serdes [create_bd_cell -type module -reference clock_to_serdes tx_serdes] + + set dcmac_name "dcmac_${dcmac_index}_core" + + if { ${dcmac_index} == "1" } { + set dcmac_loc "DCMAC_X0Y2" + } else { + set dcmac_loc "DCMAC_X1Y1" + } + + # Create instance: dcmac_core, and set properties + set dcmac_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:dcmac ${dcmac_name} ] + + set_property -dict [list \ + CONFIG.DCMAC_CONFIGURATION_TYPE {Static Configuration} \ + CONFIG.DCMAC_DATA_PATH_INTERFACE_C0 {391MHz Upto 6 Ports} \ + CONFIG.DCMAC_LOCATION_C0 $dcmac_loc \ + CONFIG.DCMAC_MODE_C0 {Coupled MAC+PCS} \ + CONFIG.FAST_SIM_MODE {0} \ + CONFIG.FEC_SLICE0_CFG_C0 {RS(544) CL119} \ + CONFIG.GT_PIPELINE_STAGES {7} \ + CONFIG.GT_REF_CLK_FREQ_C0 {322.265625} \ + CONFIG.GT_TYPE_C0 {GTM} \ + CONFIG.MAC_PORT0_CONFIG_C0 {200GAUI-4} \ + CONFIG.MAC_PORT0_ENABLE_C0 {1} \ + CONFIG.MAC_PORT0_ENABLE_TIME_STAMPING_C0 {0} \ + CONFIG.MAC_PORT0_RX_FLOW_C0 {0} \ + CONFIG.MAC_PORT0_RX_STRIP_C0 {1} \ + CONFIG.MAC_PORT0_TX_FLOW_C0 {0} \ + CONFIG.MAC_PORT0_TX_INSERT_C0 {1} \ + CONFIG.MAC_PORT1_ENABLE_C0 {1} \ + CONFIG.MAC_PORT1_RX_STRIP_C0 {1} \ + CONFIG.MAC_PORT2_ENABLE_C0 {0} \ + CONFIG.MAC_PORT3_ENABLE_C0 {0} \ + CONFIG.MAC_PORT4_ENABLE_C0 {0} \ + CONFIG.MAC_PORT5_ENABLE_C0 {0} \ + CONFIG.NUM_GT_CHANNELS {4} \ + CONFIG.PHY_OPERATING_MODE_C0 {N/A} \ + CONFIG.PORT0_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT0_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT1_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT1_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT2_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT2_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT3_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT3_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT4_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT4_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT5_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT5_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.TIMESTAMP_CLK_PERIOD_NS {4.0000} \ + ] $dcmac_core + + if { ${dual_dcmac} == "1" } { + set_property -dict [list \ + CONFIG.MAC_PORT2_ENABLE_C0 {1} \ + CONFIG.MAC_PORT2_RX_STRIP_C0 {1} \ + CONFIG.MAC_PORT3_ENABLE_C0 {1} \ + CONFIG.MAC_PORT3_RX_STRIP_C0 {1} \ + ] $dcmac_core + } + + # Create instance: dcmac200g_ctl_port + set dcmac200g_ctl_port [create_bd_cell -type module -reference dcmac200g_ctl_port dcmac200g_ctl_port] + + # Create instance: xlslice_tx_datapath_0, and set properties + set xlslice_tx_datapath_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_tx_datapath_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + ] $xlslice_tx_datapath_0 + + # Create instance: xlslice_tx_datapath_1, and set properties + set xlslice_tx_datapath_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_tx_datapath_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + ] $xlslice_tx_datapath_1 + + # Create instance: xlslice_tx_datapath_2, and set properties + set xlslice_tx_datapath_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_tx_datapath_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + ] $xlslice_tx_datapath_2 + + # Create instance: xlslice_rx_datapath_0, and set properties + set xlslice_rx_datapath_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_rx_datapath_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + ] $xlslice_rx_datapath_0 + + # Create instance: tx_flexif_clk_clock_bus, and set properties + set tx_flexif_clk_clock_bus [create_bd_cell -type module -reference clock_to_clock_bus tx_flexif_clk_clock_bus] + + # Create instance: xlslice_tx_datapath_3, and set properties + set xlslice_tx_datapath_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_tx_datapath_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + ] $xlslice_tx_datapath_3 + + # Create instance: rx_serdes, and set properties + set rx_serdes [create_bd_cell -type module -reference clock_to_serdes rx_serdes] + + # Create instance: xlslice_rx_datapath_1, and set properties + set xlslice_rx_datapath_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_rx_datapath_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + ] $xlslice_rx_datapath_1 + + # Create instance: xlslice_rx_datapath_3, and set properties + set xlslice_rx_datapath_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_rx_datapath_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + ] $xlslice_rx_datapath_3 + + # Create instance: gt0_rx_reset_done, and set properties + set gt0_rx_reset_done [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat gt0_rx_reset_done ] + set_property CONFIG.NUM_PORTS {4} $gt0_rx_reset_done + + # Create instance: gt0_tx_reset_done, and set properties + set gt0_tx_reset_done [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat gt0_tx_reset_done ] + set_property CONFIG.NUM_PORTS {4} $gt0_tx_reset_done + + set num_loops [expr {$dual_dcmac}] + + for {set i 0} {$i <= $num_loops} {incr i} { + # Create instance: seg_to_axis, and set properties + create_bd_cell -type module -reference axis_seg_to_unseg_converter "seg_to_axis${i}" + # Create instance: axis_to_seg, and set properties + create_bd_cell -type module -reference axis_unseg_to_seg_converter "axis_to_seg${i}" + + set_property CONFIG.FREQ_HZ 390998840 [get_bd_intf_pins "seg_to_axis${i}/m_axis0_pkt_out"] + set_property CONFIG.FREQ_HZ 390998840 [get_bd_intf_pins "axis_to_seg${i}/s_axis0_pkt_in"] + } + + # Create instance: dcmac_gt0_wrapper + set dcmac_wrapper_name "dcmac_gt${dcmac_index}_wrapper" + create_hier_cell_dcmac_gt_wrapper $hier_obj ${dcmac_wrapper_name} ${dcmac_index} ${dual_dcmac} + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/qsfp_clk_322mhz] [get_bd_intf_pins qsfp_clk_322mhz] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_0] [get_bd_intf_pins ${dcmac_wrapper_name}/RX0_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_1] [get_bd_intf_pins ${dcmac_wrapper_name}/RX1_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_2] [get_bd_intf_pins ${dcmac_wrapper_name}/RX2_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_3] [get_bd_intf_pins ${dcmac_wrapper_name}/RX3_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_0] [get_bd_intf_pins ${dcmac_wrapper_name}/TX0_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_1] [get_bd_intf_pins ${dcmac_wrapper_name}/TX1_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_2] [get_bd_intf_pins ${dcmac_wrapper_name}/TX2_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_3] [get_bd_intf_pins ${dcmac_wrapper_name}/TX3_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins s_axi] [get_bd_intf_pins ${dcmac_name}/s_axi] + + if { ${dual_dcmac} == "1" } { + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_4] [get_bd_intf_pins ${dcmac_wrapper_name}/RX0_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_5] [get_bd_intf_pins ${dcmac_wrapper_name}/RX1_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_6] [get_bd_intf_pins ${dcmac_wrapper_name}/RX2_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_7] [get_bd_intf_pins ${dcmac_wrapper_name}/RX3_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_4] [get_bd_intf_pins ${dcmac_wrapper_name}/TX0_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_5] [get_bd_intf_pins ${dcmac_wrapper_name}/TX1_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_6] [get_bd_intf_pins ${dcmac_wrapper_name}/TX2_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_7] [get_bd_intf_pins ${dcmac_wrapper_name}/TX3_GT1_IP_Interface] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/hsclk_plllock1] [get_bd_pins ${dcmac_name}/plllock_in_1] + connect_bd_net [get_bd_pins ${dcmac_name}/pllreset_out_1] [get_bd_pins ${dcmac_wrapper_name}/hsclk_pllreset1] + + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_4] [get_bd_pins ${dcmac_wrapper_name}/gt1_ch0_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_5] [get_bd_pins ${dcmac_wrapper_name}/gt1_ch1_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_6] [get_bd_pins ${dcmac_wrapper_name}/gt1_ch2_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_7] [get_bd_pins ${dcmac_wrapper_name}/gt1_ch3_iloreset] + + # We need to swap the GT connections for DCMAC1 to make sure the GT aligment is correct + if { ${dcmac_index} == "1" } { + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT1_Serial] [get_bd_intf_pins qsfp_gt0] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT0_Serial] [get_bd_intf_pins qsfp_gt1] + + connect_bd_intf_net [get_bd_intf_pins seg_to_axis1/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg1/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins seg_to_axis0/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg0/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_1] + } else { + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT0_Serial] [get_bd_intf_pins qsfp_gt0] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT1_Serial] [get_bd_intf_pins qsfp_gt1] + + connect_bd_intf_net [get_bd_intf_pins seg_to_axis0/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg0/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins seg_to_axis1/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg1/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_1] + } + } else { + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT0_Serial] [get_bd_intf_pins qsfp_gt0] + connect_bd_intf_net [get_bd_intf_pins seg_to_axis0/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg0/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_0] + } + + # Create port connections + connect_bd_net -net aresetn_axis_seg_in1_1 [get_bd_pins aresetn_tx_390mhz] [get_bd_pins axis_to_seg0/aresetn_axis_seg_in] + connect_bd_net -net aresetn_axis_seg_in_1 [get_bd_pins aresetn_rx_390mhz] [get_bd_pins seg_to_axis0/aresetn_axis_seg_in] + connect_bd_net -net axi_gpio_gt_control_gpio_io_o [get_bd_pins control_gt_rst] [get_bd_pins xlslice_gt_reset/Din] [get_bd_pins ${dcmac_wrapper_name}/gt_control_pins] + connect_bd_net -net axi_gpio_rx_datapath_gpio_io_o [get_bd_pins control_rx_datapath] [get_bd_pins xlslice_rx_datapath_0/Din] [get_bd_pins xlslice_rx_datapath_1/Din] [get_bd_pins xlslice_rx_datapath_3/Din] [get_bd_pins xlslice_rx_datapath_2/Din] + connect_bd_net -net axi_gpio_tx_datapath_gpio_io_o [get_bd_pins control_tx_datapath] [get_bd_pins xlslice_tx_datapath_1/Din] [get_bd_pins xlslice_tx_datapath_2/Din] [get_bd_pins xlslice_tx_datapath_3/Din] [get_bd_pins xlslice_tx_datapath_0/Din] + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins core_clk_782mhz] [get_bd_pins ${dcmac_name}/tx_core_clk] [get_bd_pins ${dcmac_name}/rx_core_clk] + connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins axi_clk_390mhz] [get_bd_pins ${dcmac_name}/rx_axi_clk] [get_bd_pins ${dcmac_name}/tx_axi_clk] [get_bd_pins tx_flexif_clk_clock_bus/clk] [get_bd_pins ${dcmac_name}/rx_macif_clk] [get_bd_pins ${dcmac_name}/tx_macif_clk] [get_bd_pins rx_flexif_clk_clock_bus/clk] [get_bd_pins seg_to_axis0/aclk_axis_seg_in] [get_bd_pins axis_to_seg0/aclk_axis_seg_in] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_0] [get_bd_pins ${dcmac_wrapper_name}/gt0_ch0_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_1] [get_bd_pins ${dcmac_wrapper_name}/gt0_ch1_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_2] [get_bd_pins ${dcmac_wrapper_name}/gt0_ch2_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_3] [get_bd_pins ${dcmac_wrapper_name}/gt0_ch3_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/pllreset_out_0] [get_bd_pins ${dcmac_wrapper_name}/hsclk_pllreset0] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_clr_out_0] [get_bd_pins ${dcmac_wrapper_name}/MBUFG_GT_CLR] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_clrb_leaf_out_0] [get_bd_pins ${dcmac_wrapper_name}/MBUFG_GT_CLRB_LEAF] + connect_bd_net [get_bd_pins ${dcmac_name}/tx_clr_out_0] [get_bd_pins ${dcmac_wrapper_name}/MBUFG_GT_CLR1] + connect_bd_net [get_bd_pins ${dcmac_name}/tx_clrb_leaf_out_0] [get_bd_pins ${dcmac_wrapper_name}/MBUFG_GT_CLRB_LEAF1] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/GT0_ref_clk] [get_bd_pins GT0_ref_clk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/qsfp0_rx_usr_clk_332mhz] [get_bd_pins rx_alt_serdes/usrclk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/qsfp0_rx_usr_clk_664mhz] [get_bd_pins rx_serdes/usrclk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/qsfp0_tx_usr_clk_332mhz] [get_bd_pins tx_alt_serdes/usrclk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/qsfp0_tx_usr_clk_664mhz] [get_bd_pins tx_serdes/usrclk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/hsclk_plllock0] [get_bd_pins ${dcmac_name}/plllock_in_0] + connect_bd_net -net gt_reset_rx_datapath_in_0_1 [get_bd_pins xlslice_rx_datapath_0/Dout] [get_bd_pins ${dcmac_name}/gt_reset_rx_datapath_in_0] + connect_bd_net -net gt_reset_rx_datapath_in_1_1 [get_bd_pins xlslice_rx_datapath_1/Dout] [get_bd_pins ${dcmac_name}/gt_reset_rx_datapath_in_1] + connect_bd_net -net gt_reset_rx_datapath_in_2_1 [get_bd_pins xlslice_rx_datapath_2/Dout] [get_bd_pins ${dcmac_name}/gt_reset_rx_datapath_in_2] + connect_bd_net -net gt_reset_rx_datapath_in_3_1 [get_bd_pins xlslice_rx_datapath_3/Dout] [get_bd_pins ${dcmac_name}/gt_reset_rx_datapath_in_3] + connect_bd_net -net gt_reset_tx_datapath_in_0_1 [get_bd_pins xlslice_tx_datapath_0/Dout] [get_bd_pins ${dcmac_name}/gt_reset_tx_datapath_in_0] + connect_bd_net -net gt_reset_tx_datapath_in_1_1 [get_bd_pins xlslice_tx_datapath_1/Dout] [get_bd_pins ${dcmac_name}/gt_reset_tx_datapath_in_1] + connect_bd_net -net gt_reset_tx_datapath_in_2_1 [get_bd_pins xlslice_tx_datapath_2/Dout] [get_bd_pins ${dcmac_name}/gt_reset_tx_datapath_in_2] + connect_bd_net -net gt_reset_tx_datapath_in_3_1 [get_bd_pins xlslice_tx_datapath_3/Dout] [get_bd_pins ${dcmac_name}/gt_reset_tx_datapath_in_3] + connect_bd_net -net gt0_rx_reset_done_dout [get_bd_pins gt0_rx_reset_done/dout] [get_bd_pins gt0_rx_reset_done] + connect_bd_net -net gt0_tx_reset_done_dout [get_bd_pins gt0_tx_reset_done/dout] [get_bd_pins gt0_tx_reset_done] + connect_bd_net -net rx_flexif_clk_clock_bus_clockbus [get_bd_pins rx_flexif_clk_clock_bus/clockbus] [get_bd_pins ${dcmac_name}/rx_flexif_clk] + connect_bd_net -net rx_serdes_clk2_1 [get_bd_pins rx_alt_serdes/serdes_clk] [get_bd_pins ${dcmac_name}/rx_alt_serdes_clk] + connect_bd_net -net rx_serdes_clk_1 [get_bd_pins rx_serdes/serdes_clk] [get_bd_pins ${dcmac_name}/rx_serdes_clk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins ${dcmac_name}/s_axi_aresetn] [get_bd_pins ${dcmac_wrapper_name}/s_axi_aresetn] + connect_bd_net -net ts_clk_clk_clock_bus_clockbus [get_bd_pins ts_clk_bus_350mhz] [get_bd_pins ${dcmac_name}/ts_clk] + connect_bd_net -net tx_flexif_clk_clock_bus_clockbus [get_bd_pins tx_flexif_clk_clock_bus/clockbus] [get_bd_pins ${dcmac_name}/tx_flexif_clk] + connect_bd_net -net tx_serdes_clk2_1 [get_bd_pins tx_alt_serdes/serdes_clk] [get_bd_pins ${dcmac_name}/tx_alt_serdes_clk] + connect_bd_net -net tx_serdes_clk_1 [get_bd_pins tx_serdes/serdes_clk] [get_bd_pins ${dcmac_name}/tx_serdes_clk] + + for {set i 0} {$i <= $num_loops} {incr i} { + # AXI4 stream converter connections + for {set lane 0} {$lane <= 3} {incr lane} { + set lane_dcmac ${lane} + if { ${i} == "1" } { + set lane_dcmac "[expr {$lane + 4}]" + + } + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegEna${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_ena${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegDat${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tdata${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegSop${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_sop${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegEop${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_eop${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegErr${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_err${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegMty${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_mty${lane_dcmac}] + + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tdata${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegDat${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_ena${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegEna${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_eop${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegEop${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_err${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegErr${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_mty${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegMty${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_sop${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegSop${lane}_in] + save_bd_design + } + } + + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tvalid_0] [get_bd_pins seg_to_axis0/rx_axis_tvalid_i] + connect_bd_net [get_bd_pins ${dcmac_name}/tx_axis_tready_0] [get_bd_pins axis_to_seg0/tx_axis_tready_in] + connect_bd_net [get_bd_pins axis_to_seg0/tx_axis_tvalid_out] [get_bd_pins ${dcmac_name}/tx_axis_tvalid_0] + + for {set lane 0} {$lane <= 3} {incr lane} { + connect_bd_net [get_bd_pins ${dcmac_name}/gt_tx_reset_done_out_${lane}] [get_bd_pins gt0_tx_reset_done/In${lane}] + connect_bd_net [get_bd_pins ${dcmac_name}/gt_rx_reset_done_out_${lane}] [get_bd_pins gt0_rx_reset_done/In${lane}] + } + + for {set id 0} {$id <= 19} {incr id} { + connect_bd_net [get_bd_pins dcmac200g_ctl_port/ctl_tx_vl_marker_id${id}] [get_bd_pins ${dcmac_name}/ctl_vl_marker_id${id}] + } + + if { ${dual_dcmac} == "1" } { + connect_bd_net [get_bd_pins aresetn_tx_390mhz] [get_bd_pins axis_to_seg1/aresetn_axis_seg_in] + connect_bd_net [get_bd_pins aresetn_rx_390mhz] [get_bd_pins seg_to_axis1/aresetn_axis_seg_in] + connect_bd_net [get_bd_pins axi_clk_390mhz] [get_bd_pins seg_to_axis1/aclk_axis_seg_in] [get_bd_pins axis_to_seg1/aclk_axis_seg_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tvalid_2] [get_bd_pins seg_to_axis1/rx_axis_tvalid_i] + connect_bd_net [get_bd_pins ${dcmac_name}/tx_axis_tready_2] [get_bd_pins axis_to_seg1/tx_axis_tready_in] + connect_bd_net [get_bd_pins axis_to_seg1/tx_axis_tvalid_out] [get_bd_pins ${dcmac_name}/tx_axis_tvalid_2] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt1_ch0_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_4] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt1_ch1_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_5] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt1_ch2_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_6] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt1_ch3_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_7] + } + + connect_bd_net [get_bd_pins dcmac200g_ctl_port/default_vl_length_200GE_or_400GE] [get_bd_pins ${dcmac_name}/ctl_rx_custom_vl_length_minus1] [get_bd_pins ${dcmac_name}/ctl_tx_custom_vl_length_minus1] + + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gtpowergood_0] [get_bd_pins ${dcmac_name}/gtpowergood_in] [get_bd_pins gt0powergood] + connect_bd_net [get_bd_pins xlslice_gt_reset/Dout] [get_bd_pins ${dcmac_name}/gt_reset_all_in] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt0_ch0_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_0] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt0_ch1_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_1] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt0_ch2_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_2] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt0_ch3_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_3] + + connect_bd_net [get_bd_pins s_axi_aclk] [get_bd_pins ${dcmac_name}/s_axi_aclk] [get_bd_pins ${dcmac_wrapper_name}/apb3clk_quad] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: clk_n_resets +proc create_hier_cell_clk_n_resets { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_clk_n_resets() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + + # Create pins + create_bd_pin -dir O -type clk clk_out_390 + create_bd_pin -dir I -from 7 -to 0 gt0_tx_reset_done + create_bd_pin -dir I -type clk gt_ref_clk_322mhz + create_bd_pin -dir O -type clk clk_out_782 + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -from 0 -to 0 -type rst aresetn_tx_390mhz + create_bd_pin -dir O -from 0 -to 0 -type rst aresetn_rx_390mhz + create_bd_pin -dir I -from 7 -to 0 gt0_rx_reset_done + create_bd_pin -dir O -from 5 -to 0 clockbus_350 + create_bd_pin -dir I -from 31 -to 0 reset_txrx_path + + # Create instance: syncer_tx_reset, and set properties + set syncer_tx_reset [create_bd_cell -type module -reference dcmac_syncer_reset syncer_tx_reset] + + # Create instance: clk_wizard_0, and set properties + set clk_wizard_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard clk_wizard_0 ] + set_property -dict [list \ + CONFIG.CLKOUT_DRIVES {BUFG,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG} \ + CONFIG.CLKOUT_DYN_PS {None,None,None,None,None,None,None} \ + CONFIG.CLKOUT_GROUPING {Auto,Auto,Auto,Auto,Auto,Auto,Auto} \ + CONFIG.CLKOUT_MATCHED_ROUTING {false,false,false,false,false,false,false} \ + CONFIG.CLKOUT_PORT {clk_out1,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7} \ + CONFIG.CLKOUT_REQUESTED_DUTY_CYCLE {50.000,50.000,50.000,50.000,50.000,50.000,50.000} \ + CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY {782,390.625,350,100.000,100.000,100.000,100.000} \ + CONFIG.CLKOUT_REQUESTED_PHASE {0.000,0.000,0.000,0.000,0.000,0.000,0.000} \ + CONFIG.CLKOUT_USED {true,true,true,false,false,false,false} \ + CONFIG.OVERRIDE_PRIMITIVE {false} \ + CONFIG.PRIM_IN_FREQ {322.265625} \ + CONFIG.PRIM_SOURCE {Global_buffer} \ + CONFIG.USE_LOCKED {true} \ + ] $clk_wizard_0 + + + # Create instance: sys_reset_tx, and set properties + set sys_reset_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_tx ] + + # Create instance: sys_reset_rx, and set properties + set sys_reset_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_rx ] + + # Create instance: syncer_rx_reset, and set properties + set syncer_rx_reset [create_bd_cell -type module -reference dcmac_syncer_reset syncer_rx_reset] + + # Create instance: ts_clk_clk_clock_bus, and set properties + set ts_clk_clk_clock_bus [create_bd_cell -type module -reference clock_to_clock_bus ts_clk_clk_clock_bus] + + # Create instance: util_vector_logic_not, and set properties + set util_vector_logic_not [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic util_vector_logic_not] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {32} \ + ] $util_vector_logic_not + + set xlslice_reset_rx0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_reset_rx0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + ] $xlslice_reset_rx0 + + set xlslice_reset_tx0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_reset_tx0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + ] $xlslice_reset_tx0 + + set xlslice_reset_rx1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_reset_rx1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + ] $xlslice_reset_rx1 + + set xlslice_reset_tx1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_reset_tx1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + ] $xlslice_reset_tx1 + + set xlconcat_rx0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_rx0 ] + set_property -dict [list \ + CONFIG.IN0_WIDTH.VALUE_SRC USER \ + CONFIG.IN1_WIDTH.VALUE_SRC USER \ + CONFIG.IN0_WIDTH {4} \ + CONFIG.IN1_WIDTH {1} \ + ] $xlconcat_rx0 + + set xlconcat_tx0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_tx0 ] + set_property -dict [list \ + CONFIG.IN0_WIDTH.VALUE_SRC USER \ + CONFIG.IN1_WIDTH.VALUE_SRC USER \ + CONFIG.IN0_WIDTH {4} \ + CONFIG.IN1_WIDTH {1} \ + ] $xlconcat_tx0 + + + set and_reduced_rx [create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilreduced_logic and_reduced_rx] + set_property -dict [list \ + CONFIG.C_SIZE {5} \ + ] $and_reduced_rx + + set and_reduced_tx [create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilreduced_logic and_reduced_tx] + set_property -dict [list \ + CONFIG.C_SIZE {5} \ + ] $and_reduced_tx + + # Create port connections + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins clk_wizard_0/clk_out1] [get_bd_pins clk_out_782] + connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins clk_wizard_0/clk_out2] [get_bd_pins clk_out_390] [get_bd_pins sys_reset_tx/slowest_sync_clk] [get_bd_pins sys_reset_rx/slowest_sync_clk] [get_bd_pins syncer_rx_reset/clk] [get_bd_pins syncer_tx_reset/clk] + connect_bd_net -net clk_wizard_0_clk_out3 [get_bd_pins clk_wizard_0/clk_out3] [get_bd_pins ts_clk_clk_clock_bus/clk] + connect_bd_net -net clk_wizard_0_locked [get_bd_pins clk_wizard_0/locked] [get_bd_pins syncer_rx_reset/clk_wizard_lock] [get_bd_pins syncer_tx_reset/clk_wizard_lock] + connect_bd_net -net dcmac_0_gt_wrapper_IBUFDS_ODIV2 [get_bd_pins gt_ref_clk_322mhz] [get_bd_pins clk_wizard_0/clk_in1] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins sys_reset_rx/aux_reset_in] [get_bd_pins sys_reset_tx/aux_reset_in] + connect_bd_net -net syncer_rx_reset_resetn [get_bd_pins syncer_rx_reset/resetn] [get_bd_pins sys_reset_rx/ext_reset_in] + connect_bd_net -net syncer_tx_reset_resetn [get_bd_pins syncer_tx_reset/resetn] [get_bd_pins sys_reset_tx/ext_reset_in] + connect_bd_net -net sys_reset_rx_peripheral_aresetn [get_bd_pins sys_reset_rx/peripheral_aresetn] [get_bd_pins aresetn_rx_390mhz] + connect_bd_net -net sys_reset_tx_peripheral_aresetn [get_bd_pins sys_reset_tx/peripheral_aresetn] [get_bd_pins aresetn_tx_390mhz] + connect_bd_net -net ts_clk_clk_clock_bus_clockbus [get_bd_pins ts_clk_clk_clock_bus/clockbus] [get_bd_pins clockbus_350] + + connect_bd_net [get_bd_pins gt0_rx_reset_done] [get_bd_pins xlconcat_rx0/In0] + connect_bd_net [get_bd_pins xlslice_reset_rx0/Dout] [get_bd_pins xlconcat_rx0/In1] + connect_bd_net [get_bd_pins xlconcat_rx0/dout] [get_bd_pins and_reduced_rx/Op1] + connect_bd_net [get_bd_pins and_reduced_rx/Res] [get_bd_pins syncer_rx_reset/resetn_async] + connect_bd_net [get_bd_pins gt0_tx_reset_done] [get_bd_pins xlconcat_tx0/In0] + connect_bd_net [get_bd_pins xlslice_reset_tx0/Dout] [get_bd_pins xlconcat_tx0/In1] + connect_bd_net [get_bd_pins xlconcat_tx0/dout] [get_bd_pins and_reduced_tx/Op1] + connect_bd_net [get_bd_pins and_reduced_tx/Res] [get_bd_pins syncer_tx_reset/resetn_async] + connect_bd_net [get_bd_pins reset_txrx_path] [get_bd_pins util_vector_logic_not/Op1] + connect_bd_net [get_bd_pins util_vector_logic_not/Res] [get_bd_pins xlslice_reset_rx0/Din] + connect_bd_net [get_bd_pins util_vector_logic_not/Res] [get_bd_pins xlslice_reset_rx1/Din] + connect_bd_net [get_bd_pins util_vector_logic_not/Res] [get_bd_pins xlslice_reset_tx0/Din] + connect_bd_net [get_bd_pins util_vector_logic_not/Res] [get_bd_pins xlslice_reset_tx1/Din] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: qsfp_0_n_1 +proc create_hier_cell_qsfp { parentCell nameHier dcmac_index dual_dcmac} { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_qsfp() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp_clk_322mhz + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp_gt0 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_0 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_0 + + # Additional port for dual DCMAC + if { ${dual_dcmac} == "1" } { + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp_gt1 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_1 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_1 + } + + # Create pins + create_bd_pin -dir I -type clk ap_clk + #create_bd_pin -dir I -type clk ap_clk_eth0 + create_bd_pin -dir I -type rst ap_rst_n + + set num_loops [expr {$dual_dcmac}] + + for {set i 0} {$i <= $num_loops} {incr i} { + # Create instance: adwc0_512_1024, and set properties + set adwc_512_1024 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter "adwc${i}_512_1024" ] + set_property -dict [list \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.M_TDATA_NUM_BYTES {128} \ + CONFIG.S_TDATA_NUM_BYTES {64} \ + CONFIG.TUSER_BITS_PER_BYTE {1} \ + ] $adwc_512_1024 + + # Create instance: adwc0_1024_512, and set properties + set adwc_1024_512 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter "adwc${i}_1024_512" ] + set_property -dict [list \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.M_TDATA_NUM_BYTES {64} \ + CONFIG.S_TDATA_NUM_BYTES {128} \ + CONFIG.TUSER_BITS_PER_BYTE {1} \ + ] $adwc_1024_512 + + # Create instance: tx_packet_fifo_cdc, and set properties + set tx_packet_fifo_cdc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo "tx${i}_packet_fifo_cdc" ] + set_property -dict [list \ + CONFIG.HAS_TLAST.VALUE_SRC USER \ + CONFIG.FIFO_DEPTH {512} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.IS_ACLK_ASYNC {1} \ + ] $tx_packet_fifo_cdc + + # Create instance: rx_fifo_cdc, and set properties + set rx_fifo_cdc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo "rx${i}_fifo_cdc" ] + set_property -dict [list \ + CONFIG.FIFO_DEPTH {128} \ + CONFIG.FIFO_MODE {1} \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.IS_ACLK_ASYNC {1} \ + ] $rx_fifo_cdc + } + # Create instance: clk_n_resets + create_hier_cell_clk_n_resets $hier_obj clk_n_resets + + # Create instance: DCMAC_subsys + create_hier_cell_DCMAC_subsys $hier_obj DCMAC_subsys ${dcmac_index} ${dual_dcmac} + + # Create instance: control_intf + create_hier_cell_control_intf $hier_obj control_intf ${dual_dcmac} + + # Create interface connections + connect_bd_intf_net -intf_net DCMAC_subsys_M_AXIS_0 [get_bd_intf_pins adwc0_1024_512/S_AXIS] [get_bd_intf_pins DCMAC_subsys/M_AXIS_0] + connect_bd_intf_net -intf_net DCMAC_subsys_qsfp_gt [get_bd_intf_pins qsfp_gt0] [get_bd_intf_pins DCMAC_subsys/qsfp_gt0] + connect_bd_intf_net -intf_net adwc0_1024_512_M_AXIS [get_bd_intf_pins adwc0_1024_512/M_AXIS] [get_bd_intf_pins rx0_fifo_cdc/S_AXIS] + connect_bd_intf_net -intf_net rx0_fifo_cdc_M_AXIS [get_bd_intf_pins rx0_fifo_cdc/M_AXIS] [get_bd_intf_pins M_AXIS_0] + connect_bd_intf_net -intf_net adwc0_512_1024_M_AXIS [get_bd_intf_pins adwc0_512_1024/M_AXIS] [get_bd_intf_pins DCMAC_subsys/S_AXIS_0] + connect_bd_intf_net -intf_net m_axi_0 [get_bd_intf_pins control_intf/M_AXI_DCMAC] [get_bd_intf_pins DCMAC_subsys/s_axi] + connect_bd_intf_net -intf_net packet_fifo_M_AXIS [get_bd_intf_pins tx0_packet_fifo_cdc/M_AXIS] [get_bd_intf_pins adwc0_512_1024/S_AXIS] + connect_bd_intf_net -intf_net qsfp_clk_322mhz_1 [get_bd_intf_pins qsfp_clk_322mhz] [get_bd_intf_pins DCMAC_subsys/qsfp_clk_322mhz] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins control_intf/S_AXI] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins control_intf/S_AXI] + connect_bd_intf_net [get_bd_intf_pins S_AXIS_0] [get_bd_intf_pins tx0_packet_fifo_cdc/S_AXIS] + + # Create port connections + connect_bd_net -net axi_gpio_gt_control_gpio_io_o [get_bd_pins control_intf/control_gt_rst] [get_bd_pins DCMAC_subsys/control_gt_rst] + connect_bd_net -net axi_gpio_rx_datapath_gpio_io_o [get_bd_pins control_intf/rx_datapath_ctrl] [get_bd_pins DCMAC_subsys/control_rx_datapath] + connect_bd_net -net axi_gpio_tx_datapath_gpio_io_o [get_bd_pins control_intf/tx_datapath_ctrl] [get_bd_pins DCMAC_subsys/control_tx_datapath] + connect_bd_net [get_bd_pins control_intf/gt0powergood] [get_bd_pins DCMAC_subsys/gt0powergood] + connect_bd_net [get_bd_pins control_intf/reset_txrx_path] [get_bd_pins clk_n_resets/reset_txrx_path] + + connect_bd_net -net gt_ref_clk_322mhz_1 [get_bd_pins DCMAC_subsys/GT0_ref_clk] [get_bd_pins clk_n_resets/gt_ref_clk_322mhz] + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins clk_n_resets/clk_out_782] [get_bd_pins DCMAC_subsys/core_clk_782mhz] + connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins clk_n_resets/clk_out_390] [get_bd_pins adwc0_512_1024/aclk] [get_bd_pins adwc0_1024_512/aclk] [get_bd_pins tx0_packet_fifo_cdc/m_axis_aclk] [get_bd_pins DCMAC_subsys/axi_clk_390mhz] [get_bd_pins control_intf/clk_out_390] [get_bd_pins rx0_fifo_cdc/s_axis_aclk] + connect_bd_net -net gt0_rx_reset_done_dout [get_bd_pins DCMAC_subsys/gt0_rx_reset_done] [get_bd_pins clk_n_resets/gt0_rx_reset_done] [get_bd_pins control_intf/gt0_rx_reset_done] + connect_bd_net -net gt0_tx_reset_done_dout [get_bd_pins DCMAC_subsys/gt0_tx_reset_done] [get_bd_pins clk_n_resets/gt0_tx_reset_done] [get_bd_pins control_intf/gt0_tx_reset_done] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins ap_clk] [get_bd_pins DCMAC_subsys/s_axi_aclk] [get_bd_pins control_intf/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins ap_rst_n] [get_bd_pins clk_n_resets/s_axi_aresetn] [get_bd_pins DCMAC_subsys/s_axi_aresetn] [get_bd_pins control_intf/s_axi_aresetn] + connect_bd_net -net sys_reset_rx_peripheral_aresetn [get_bd_pins clk_n_resets/aresetn_rx_390mhz] [get_bd_pins DCMAC_subsys/aresetn_rx_390mhz] [get_bd_pins adwc0_1024_512/aresetn] [get_bd_pins rx0_fifo_cdc/s_axis_aresetn] + connect_bd_net -net sys_reset_tx_peripheral_aresetn [get_bd_pins clk_n_resets/aresetn_tx_390mhz] [get_bd_pins adwc0_512_1024/aresetn] [get_bd_pins tx0_packet_fifo_cdc/s_axis_aresetn] [get_bd_pins DCMAC_subsys/aresetn_tx_390mhz] + connect_bd_net -net ts_clk_clk_clock_bus_clockbus [get_bd_pins clk_n_resets/clockbus_350] [get_bd_pins DCMAC_subsys/ts_clk_bus_350mhz] + + connect_bd_net [get_bd_pins ap_clk] [get_bd_pins tx0_packet_fifo_cdc/s_axis_aclk] [get_bd_pins rx0_fifo_cdc/m_axis_aclk] + + if { ${dual_dcmac} == "1" } { + connect_bd_intf_net [get_bd_intf_pins qsfp_gt1] [get_bd_intf_pins DCMAC_subsys/qsfp_gt1] + connect_bd_intf_net [get_bd_intf_pins adwc1_1024_512/S_AXIS] [get_bd_intf_pins DCMAC_subsys/M_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins adwc1_512_1024/M_AXIS] [get_bd_intf_pins DCMAC_subsys/S_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins rx1_fifo_cdc/M_AXIS] [get_bd_intf_pins M_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins tx1_packet_fifo_cdc/M_AXIS] [get_bd_intf_pins adwc1_512_1024/S_AXIS] + connect_bd_intf_net [get_bd_intf_pins adwc1_1024_512/M_AXIS] [get_bd_intf_pins rx1_fifo_cdc/S_AXIS] + connect_bd_intf_net [get_bd_intf_pins S_AXIS_1] [get_bd_intf_pins tx1_packet_fifo_cdc/S_AXIS] + + connect_bd_net [get_bd_pins clk_n_resets/clk_out_390] [get_bd_pins adwc1_512_1024/aclk] [get_bd_pins adwc1_1024_512/aclk] [get_bd_pins tx1_packet_fifo_cdc/m_axis_aclk] [get_bd_pins rx1_fifo_cdc/s_axis_aclk] + connect_bd_net [get_bd_pins ap_clk] [get_bd_pins tx1_packet_fifo_cdc/s_axis_aclk] [get_bd_pins rx1_fifo_cdc/m_axis_aclk] + connect_bd_net [get_bd_pins clk_n_resets/aresetn_tx_390mhz] [get_bd_pins adwc1_512_1024/aresetn] [get_bd_pins tx1_packet_fifo_cdc/s_axis_aresetn] + connect_bd_net [get_bd_pins clk_n_resets/aresetn_rx_390mhz] [get_bd_pins adwc1_1024_512/aresetn] [get_bd_pins rx1_fifo_cdc/s_axis_aresetn] + } + + save_bd_design + # Restore current instance + current_bd_instance $oldCurInst +} + +# Generic function that creates the qsfp block +proc create_qsfp_hierarchy { dcmac_index dual_dcmac} { + + if {![string is integer -strict $dcmac_index] || !($dcmac_index == 0 || $dcmac_index == 1)} { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "dcmac_index (with value $dcmac_index) is not correct. Valid values are 0 and 1"} + return + } + + if {![string is integer -strict $dual_dcmac] || !($dual_dcmac == 0 || $dual_dcmac == 1)} { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "dual_dcmac (with value $dual_dcmac) is not correct. Valid values are 0 or 1"} + return + } + + # TODO use dual_dcmac + if { ${dcmac_index} == "0" } { + set new_index $dcmac_index + set offset_increment 0 + } else { + set new_index "[expr {$dcmac_index + 1}]" + set offset_increment 0x1000000 + } + + set qsfp_hier_name "qsfp_${new_index}_n_[expr {$new_index + 1}]" + + create_hier_cell_qsfp [current_bd_instance .] ${qsfp_hier_name} ${dcmac_index} ${dual_dcmac} + save_bd_design + + set qsfp_gt0_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 "qsfp${new_index}_4x" ] + + set qsfp_gt_clk_name [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 "qsfp${new_index}_322mhz" ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {322265625} \ + ] $qsfp_gt_clk_name + save_bd_design + + connect_bd_intf_net [get_bd_intf_ports ${qsfp_gt0_4x}] [get_bd_intf_pins ${qsfp_hier_name}/qsfp_gt0] + if { ${dual_dcmac} == "1" } { + set qsfp_gt1_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 "qsfp[expr {$new_index + 1}]_4x" ] + connect_bd_intf_net [get_bd_intf_ports ${qsfp_gt1_4x}] [get_bd_intf_pins ${qsfp_hier_name}/qsfp_gt1] + } + connect_bd_intf_net [get_bd_intf_ports ${qsfp_gt_clk_name}] [get_bd_intf_pins ${qsfp_hier_name}/qsfp_clk_322mhz] + + connect_bd_net [get_bd_pins cips/pl0_ref_clk] [get_bd_pins ${qsfp_hier_name}/ap_clk] + connect_bd_net [get_bd_pins clock_reset/resetn_pl_ic] [get_bd_pins ${qsfp_hier_name}/ap_rst_n] + save_bd_design + + # Manager ports are going to be inferred from M00_AXI through a xbar + set num_managers [get_property CONFIG.NUM_MI [get_bd_cells bar_sc]] + set new_num_managers "[expr {$num_managers + 1}]" + set manager_port "M0${num_managers}_AXI" + + set_property -dict [list \ + CONFIG.NUM_MI ${new_num_managers} \ + CONFIG.NUM_SI {1} \ + ] [get_bd_cells bar_sc] + + save_bd_design + + connect_bd_intf_net [get_bd_intf_pins bar_sc/${manager_port}] [get_bd_intf_pins ${qsfp_hier_name}/s_axi] + + # Create address segments + foreach pcie_noc {CPM_PCIE_NOC_0 CPM_PCIE_NOC_1} { + assign_bd_address -offset [expr {0x020102000000 + ${offset_increment}}] -range 256K -target_address_space [get_bd_addr_spaces cips/${pcie_noc}] [get_bd_addr_segs /${qsfp_hier_name}/DCMAC_subsys/dcmac_${dcmac_index}_core/s_axi/Reg] -force + assign_bd_address -offset [expr {0x020102040000 + ${offset_increment}}] -range 256 -target_address_space [get_bd_addr_spaces cips/${pcie_noc}] [get_bd_addr_segs /${qsfp_hier_name}/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset [expr {0x020102040200 + ${offset_increment}}] -range 256 -target_address_space [get_bd_addr_spaces cips/${pcie_noc}] [get_bd_addr_segs /${qsfp_hier_name}/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset [expr {0x020102040400 + ${offset_increment}}] -range 256 -target_address_space [get_bd_addr_spaces cips/${pcie_noc}] [get_bd_addr_segs /${qsfp_hier_name}/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset [expr {0x020102040600 + ${offset_increment}}] -range 256 -target_address_space [get_bd_addr_spaces cips/${pcie_noc}] [get_bd_addr_segs /${qsfp_hier_name}/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + save_bd_design + } + + save_bd_design +} + +proc create_bar_sc { parentCell } { + variable script_folder + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + delete_bd_objs [get_bd_intf_nets axi_noc_cips_M00_AXI] + set bar_sc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 bar_sc ] + set_property -dict [list \ + CONFIG.NUM_SI {1} \ + ] [get_bd_cells bar_sc] + connect_bd_net [get_bd_pins cips/pl0_ref_clk] [get_bd_pins bar_sc/aclk] + connect_bd_net [get_bd_pins clock_reset/resetn_pl_ic] [get_bd_pins bar_sc/aresetn] + connect_bd_intf_net [get_bd_intf_pins bar_sc/S00_AXI] [get_bd_intf_pins axi_noc_cips/M00_AXI] + connect_bd_intf_net [get_bd_intf_pins bar_sc/M00_AXI] [get_bd_intf_pins base_logic/s_axi_pcie_mgmt_slr0] + + # Fix PL AXILite aperture + # Total of 256MB can be used, this command exposes all of it + set_property -dict [ list \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.APERTURES {{0x201_0000_0000 0x1000_0000}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_cips/M00_AXI] + current_bd_instance $oldCurInst +} + +proc add_dcmac {} { + source "src/dcmac/tcl/dcmac_config.tcl" + import_files -fileset sources_1 -norecurse "src/dcmac/hdl/axis_seg_to_unseg_converter.v" + import_files -fileset sources_1 -norecurse "src/dcmac/hdl/clock_to_clock_bus.v" + import_files -fileset sources_1 -norecurse "src/dcmac/hdl/dcmac200g_ctl_port.v" + import_files -fileset sources_1 -norecurse "src/dcmac/hdl/serdes_clock.v" + import_files -fileset sources_1 -norecurse "src/dcmac/hdl/syncer_reset.v" + + if { ${DCMAC0_ENABLED} == "1" || ${DCMAC1_ENABLED} == "1" } { + create_bar_sc "" + } + # Create network hierarchy + if { ${DCMAC0_ENABLED} == "1" } { + create_qsfp_hierarchy 0 ${DUAL_QSFP_DCMAC0} + } + if { ${DCMAC1_ENABLED} == "1" } { + create_qsfp_hierarchy 1 ${DUAL_QSFP_DCMAC1} + } +} + +add_dcmac \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/dcmac/tcl/dcmac_config.tcl b/submodules/v80-vitis-flow/resources/dcmac/tcl/dcmac_config.tcl new file mode 100644 index 00000000..82b0afea --- /dev/null +++ b/submodules/v80-vitis-flow/resources/dcmac/tcl/dcmac_config.tcl @@ -0,0 +1,27 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +# A front view of the V80 and QSFP56 index and associated DCMAC +# Use this diagram to guide the configuration +# +# _________________________ +# | 0 | 1 | 2 | 3 | +# ----------------------------> PCIe +# +# \___________/\__________/ +# | | +# DCMAC0 DCMAC1 + + +### Enable the DCMAC core(s) that you wish to use +set DCMAC0_ENABLED 1 +set DCMAC1_ENABLED 1 + +## Each DCMAC can support 2 QSFP56 interfaces +## select how many QSFP56 you want for each DCMAC, provided they are enabled + +## Setup number of QSFP56 interfaces for DCMAC0 +set DUAL_QSFP_DCMAC0 0 + +## Setup number of QSFP56 interfaces for DCMAC1 +set DUAL_QSFP_DCMAC1 0 diff --git a/submodules/v80-vitis-flow/resources/noc_sol.ncr b/submodules/v80-vitis-flow/resources/noc_sol.ncr index d5d00d37..4d57c6a3 100644 --- a/submodules/v80-vitis-flow/resources/noc_sol.ncr +++ b/submodules/v80-vitis-flow/resources/noc_sol.ncr @@ -4,9 +4,9 @@ "Paths": [ { "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", "ToLocked": false, "Port": "PORT2", "ReadTC": "BE", @@ -21,6 +21,366 @@ "WriteBestPossibleLatency": 300, "PathLocked": true, "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA2_in", + "NOC_NPS4_X5Y0", + "portSideB1_out", + "HBM_MC_X10Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X10Y0", + "pc1_port0_out", + "NOC_NPS4_X5Y0", + "portSideB1_in", + "NOC_NPS4_X5Y0", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port5_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, { "PhyInstanceStart": "HBM_MC_X10Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -380,10 +740,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 135 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X10Y0", + "PhyInstanceEnd": "HBM_MC_X15Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -548,33 +929,57 @@ "NOC_NPS6_X5Y1", "port0_in", "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", "port5_out", - "NOC_NPS4_X5Y0", + "NOC_NPS4_X7Y0", "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB1_out", - "HBM_MC_X10Y0", - "pc1_port0_in" + "NOC_NPS4_X7Y0", + "portSideB2_out", + "HBM_MC_X15Y0", + "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 135 + "AchievedLatency": 141 }, { - "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceStart": "HBM_MC_X15Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X10Y0", - "pc1_port0_out", - "NOC_NPS4_X5Y0", - "portSideB1_in", - "NOC_NPS4_X5Y0", + "HBM_MC_X15Y0", + "pc0_port0_out", + "NOC_NPS4_X7Y0", + "portSideB2_in", + "NOC_NPS4_X7Y0", "portSideA1_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X7Y1", "port5_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", "NOC_NPS6_X5Y1", "port0_out", "NOC_NPS5555_X7Y4", @@ -739,29 +1144,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 141 + }, { "PhyInstanceStart": "HBM_MC_X15Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -1145,10 +1529,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 141 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X15Y0", + "PhyInstanceEnd": "HBM_MC_X10Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -1313,57 +1718,33 @@ "NOC_NPS6_X5Y1", "port0_in", "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", "port5_out", - "NOC_NPS4_X7Y0", + "NOC_NPS4_X5Y0", "portSideA1_in", - "NOC_NPS4_X7Y0", - "portSideB2_out", - "HBM_MC_X15Y0", + "NOC_NPS4_X5Y0", + "portSideB0_out", + "HBM_MC_X10Y0", "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 141 + "AchievedLatency": 135 }, { - "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceStart": "HBM_MC_X10Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X15Y0", + "HBM_MC_X10Y0", "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB2_in", - "NOC_NPS4_X7Y0", + "NOC_NPS4_X5Y0", + "portSideB0_in", + "NOC_NPS4_X5Y0", "portSideA1_out", - "NOC_NPS6_X7Y1", - "port5_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", "NOC_NPS6_X5Y1", - "port3_in", + "port5_in", "NOC_NPS6_X5Y1", "port0_out", "NOC_NPS5555_X7Y4", @@ -1528,29 +1909,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 135 + }, { "PhyInstanceStart": "HBM_MC_X10Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -1562,145 +1922,145 @@ "NOC_NPS4_X5Y0", "portSideB0_in", "NOC_NPS4_X5Y0", - "portSideA2_out", - "NOC_NPS6_X5Y2", + "portSideA1_out", + "NOC_NPS6_X5Y1", "port5_in", - "NOC_NPS6_X5Y2", + "NOC_NPS6_X5Y1", "port0_out", - "NOC_NPS5555_X7Y6", + "NOC_NPS5555_X7Y4", "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", + "NOC_NPS5555_X7Y4", "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", "port0_out", - "NOC_NPS_VNOC_X2Y26", + "NOC_NPS5555_X6Y4", "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", + "NOC_NPS5555_X6Y4", "port3_out", - "NOC_NIDB_X2Y7", + "NOC_NCRB_X1Y0", "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", + "NOC_NCRB_X1Y0", "port0_out", - "NOC_NPS7575_X6Y4", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", "port3_in", - "NOC_NPS7575_X6Y4", + "NOC_NPS7575_X5Y7", "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X1Y6", "port0_in", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X1Y6", "port1_out", - "NOC_NIDB_X2Y1", + "NOC_NIDB_X1Y4", "port1_in", - "NOC_NIDB_X2Y1", + "NOC_NIDB_X1Y4", "port0_out", - "NOC_NPS7575_X6Y0", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", "port3_in", - "NOC_NPS7575_X6Y0", + "NOC_NPS7575_X5Y3", "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", - "port0_out", - "NOC_NPS_VNOC_X2Y10", - "port2_in", - "NOC_NPS_VNOC_X2Y10", - "port0_out", - "NOC_NPS_VNOC_X2Y8", - "port2_in", - "NOC_NPS_VNOC_X2Y8", - "port0_out", - "NOC_NPS_VNOC_X2Y6", - "port2_in", - "NOC_NPS_VNOC_X2Y6", - "port0_out", - "NOC_NPS_VNOC_X2Y4", - "port2_in", - "NOC_NPS_VNOC_X2Y4", - "port0_out", - "NOC_NPS_VNOC_X2Y2", - "port2_in", - "NOC_NPS_VNOC_X2Y2", - "port0_out", - "NOC_NPS_VNOC_X2Y0", - "port2_in", - "NOC_NPS_VNOC_X2Y0", - "port0_out", - "NOC_NPS5555_X17Y1", - "port2_in", - "NOC_NPS5555_X17Y1", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", - "port0_out", - "NOC_NPS5555_X15Y0", - "port2_in", - "NOC_NPS5555_X15Y0", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS5555_X13Y0", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", "port2_in", - "NOC_NPS5555_X13Y0", - "port0_out", + "NOC_NPS5555_X11Y1", + "port1_out", "NOC_NPS5555_X11Y0", - "port2_in", + "port3_in", "NOC_NPS5555_X11Y0", "port0_out", "NOC_NPS5555_X9Y0", @@ -1762,145 +2122,145 @@ "NOC_NPS5555_X11Y0", "port0_in", "NOC_NPS5555_X11Y0", - "port2_out", - "NOC_NPS5555_X13Y0", - "port0_in", - "NOC_NPS5555_X13Y0", - "port2_out", - "NOC_NPS5555_X15Y0", - "port0_in", - "NOC_NPS5555_X15Y0", - "port2_out", - "NOC_NPS5555_X17Y0", - "port0_in", - "NOC_NPS5555_X17Y0", "port3_out", - "NOC_NPS5555_X17Y1", + "NOC_NPS5555_X11Y1", "port1_in", - "NOC_NPS5555_X17Y1", - "port2_out", - "NOC_NPS_VNOC_X2Y0", - "port0_in", - "NOC_NPS_VNOC_X2Y0", - "port2_out", - "NOC_NPS_VNOC_X2Y2", - "port0_in", - "NOC_NPS_VNOC_X2Y2", - "port2_out", - "NOC_NPS_VNOC_X2Y4", - "port0_in", - "NOC_NPS_VNOC_X2Y4", - "port2_out", - "NOC_NPS_VNOC_X2Y6", - "port0_in", - "NOC_NPS_VNOC_X2Y6", - "port2_out", - "NOC_NPS_VNOC_X2Y8", - "port0_in", - "NOC_NPS_VNOC_X2Y8", - "port2_out", - "NOC_NPS_VNOC_X2Y10", - "port0_in", - "NOC_NPS_VNOC_X2Y10", - "port2_out", - "NOC_NPS_VNOC_X2Y12", - "port0_in", - "NOC_NPS_VNOC_X2Y12", + "NOC_NPS5555_X11Y1", "port2_out", - "NOC_NPS7575_X6Y0", - "port1_in", - "NOC_NPS7575_X6Y0", - "port3_out", - "NOC_NIDB_X2Y1", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NIDB_X2Y1", + "NOC_NIDB_X1Y0", "port1_out", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS7575_X6Y2", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS7575_X6Y2", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPS_VNOC_X2Y14", - "port0_in", - "NOC_NPS_VNOC_X2Y14", - "port2_out", - "NOC_NPS_VNOC_X2Y16", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NPS_VNOC_X2Y16", - "port2_out", - "NOC_NPS_VNOC_X2Y18", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", "port0_in", - "NOC_NPS_VNOC_X2Y18", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", "port2_out", - "NOC_NPS_VNOC_X2Y20", + "NOC_NPS6_X3Y1", "port0_in", - "NOC_NPS_VNOC_X2Y20", - "port2_out", - "NOC_NPS_VNOC_X2Y22", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", "port0_in", - "NOC_NPS_VNOC_X2Y22", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", "port2_out", - "NOC_NPS_VNOC_X2Y24", + "NOC_NPS6_X5Y1", "port0_in", - "NOC_NPS_VNOC_X2Y24", - "port2_out", - "NOC_NPS7575_X6Y4", - "port1_in", - "NOC_NPS7575_X6Y4", - "port3_out", - "NOC_NIDB_X2Y5", - "port0_in", - "NOC_NIDB_X2Y5", - "port1_out", - "NOC_NIDB_X2Y7", - "port1_in", - "NOC_NIDB_X2Y7", - "port0_out", - "NOC_NPS7575_X6Y6", - "port3_in", - "NOC_NPS7575_X6Y6", - "port1_out", - "NOC_NPS_VNOC_X2Y26", - "port0_in", - "NOC_NPS_VNOC_X2Y26", - "port2_out", - "NOC_NPS_VNOC_X2Y28", - "port0_in", - "NOC_NPS_VNOC_X2Y28", - "port2_out", - "NOC_NPS_VNOC_X2Y30", - "port0_in", - "NOC_NPS_VNOC_X2Y30", - "port2_out", - "NOC_NPS_VNOC_X2Y32", - "port0_in", - "NOC_NPS_VNOC_X2Y32", - "port2_out", - "NOC_NPS_VNOC_X2Y34", - "port0_in", - "NOC_NPS_VNOC_X2Y34", - "port2_out", - "NOC_NPS_VNOC_X2Y36", - "port0_in", - "NOC_NPS_VNOC_X2Y36", - "port2_out", - "NOC_NCRB_X2Y1", - "port1_in", - "NOC_NCRB_X2Y1", - "port1_out", - "NOC_NPS5555_X7Y6", - "port3_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", + "NOC_NPS6_X5Y1", "port5_out", "NOC_NPS4_X5Y0", - "portSideA2_in", + "portSideA1_in", "NOC_NPS4_X5Y0", "portSideB0_out", "HBM_MC_X10Y0", @@ -1910,10 +2270,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 135 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X10Y0", + "PhyInstanceEnd": "HBM_MC_X5Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -1934,321 +2315,289 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port2_out", - "NOC_NPS5555_X13Y0", - "port0_in", - "NOC_NPS5555_X13Y0", - "port2_out", - "NOC_NPS5555_X15Y0", - "port0_in", - "NOC_NPS5555_X15Y0", - "port2_out", - "NOC_NPS5555_X17Y0", - "port0_in", - "NOC_NPS5555_X17Y0", "port3_out", - "NOC_NPS5555_X17Y1", + "NOC_NPS5555_X7Y1", "port1_in", - "NOC_NPS5555_X17Y1", + "NOC_NPS5555_X7Y1", "port2_out", - "NOC_NPS_VNOC_X2Y0", + "NOC_NPS_VNOC_X0Y0", "port0_in", - "NOC_NPS_VNOC_X2Y0", + "NOC_NPS_VNOC_X0Y0", "port2_out", - "NOC_NPS_VNOC_X2Y2", + "NOC_NPS_VNOC_X0Y2", "port0_in", - "NOC_NPS_VNOC_X2Y2", + "NOC_NPS_VNOC_X0Y2", "port2_out", - "NOC_NPS_VNOC_X2Y4", + "NOC_NPS_VNOC_X0Y4", "port0_in", - "NOC_NPS_VNOC_X2Y4", + "NOC_NPS_VNOC_X0Y4", "port2_out", - "NOC_NPS_VNOC_X2Y6", + "NOC_NPS_VNOC_X0Y6", "port0_in", - "NOC_NPS_VNOC_X2Y6", + "NOC_NPS_VNOC_X0Y6", "port2_out", - "NOC_NPS_VNOC_X2Y8", + "NOC_NPS_VNOC_X0Y8", "port0_in", - "NOC_NPS_VNOC_X2Y8", + "NOC_NPS_VNOC_X0Y8", "port2_out", - "NOC_NPS_VNOC_X2Y10", + "NOC_NPS_VNOC_X0Y10", "port0_in", - "NOC_NPS_VNOC_X2Y10", + "NOC_NPS_VNOC_X0Y10", "port2_out", - "NOC_NPS_VNOC_X2Y12", + "NOC_NPS_VNOC_X0Y12", "port0_in", - "NOC_NPS_VNOC_X2Y12", + "NOC_NPS_VNOC_X0Y12", "port2_out", - "NOC_NPS7575_X6Y0", + "NOC_NPS7575_X0Y0", "port1_in", - "NOC_NPS7575_X6Y0", + "NOC_NPS7575_X0Y0", "port3_out", - "NOC_NIDB_X2Y1", + "NOC_NIDB_X0Y1", "port0_in", - "NOC_NIDB_X2Y1", + "NOC_NIDB_X0Y1", "port1_out", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X0Y3", "port1_in", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X0Y3", "port0_out", - "NOC_NPS7575_X6Y2", + "NOC_NPS7575_X4Y2", "port3_in", - "NOC_NPS7575_X6Y2", + "NOC_NPS7575_X4Y2", "port1_out", - "NOC_NPS_VNOC_X2Y14", + "NOC_NPS_VNOC_X0Y14", "port0_in", - "NOC_NPS_VNOC_X2Y14", + "NOC_NPS_VNOC_X0Y14", "port2_out", - "NOC_NPS_VNOC_X2Y16", + "NOC_NPS_VNOC_X0Y16", "port0_in", - "NOC_NPS_VNOC_X2Y16", + "NOC_NPS_VNOC_X0Y16", "port2_out", - "NOC_NPS_VNOC_X2Y18", + "NOC_NPS_VNOC_X0Y18", "port0_in", - "NOC_NPS_VNOC_X2Y18", + "NOC_NPS_VNOC_X0Y18", "port2_out", - "NOC_NPS_VNOC_X2Y20", + "NOC_NPS_VNOC_X0Y20", "port0_in", - "NOC_NPS_VNOC_X2Y20", + "NOC_NPS_VNOC_X0Y20", "port2_out", - "NOC_NPS_VNOC_X2Y22", + "NOC_NPS_VNOC_X0Y22", "port0_in", - "NOC_NPS_VNOC_X2Y22", + "NOC_NPS_VNOC_X0Y22", "port2_out", - "NOC_NPS_VNOC_X2Y24", + "NOC_NPS_VNOC_X0Y24", "port0_in", - "NOC_NPS_VNOC_X2Y24", + "NOC_NPS_VNOC_X0Y24", "port2_out", - "NOC_NPS7575_X6Y4", + "NOC_NPS7575_X4Y4", "port1_in", - "NOC_NPS7575_X6Y4", + "NOC_NPS7575_X4Y4", "port3_out", - "NOC_NIDB_X2Y5", + "NOC_NIDB_X0Y5", "port0_in", - "NOC_NIDB_X2Y5", + "NOC_NIDB_X0Y5", "port1_out", - "NOC_NIDB_X2Y7", + "NOC_NIDB_X0Y7", "port1_in", - "NOC_NIDB_X2Y7", + "NOC_NIDB_X0Y7", "port0_out", - "NOC_NPS7575_X6Y6", + "NOC_NPS7575_X4Y6", "port3_in", - "NOC_NPS7575_X6Y6", + "NOC_NPS7575_X4Y6", "port1_out", - "NOC_NPS_VNOC_X2Y26", + "NOC_NPS_VNOC_X0Y26", "port0_in", - "NOC_NPS_VNOC_X2Y26", + "NOC_NPS_VNOC_X0Y26", "port2_out", - "NOC_NPS_VNOC_X2Y28", + "NOC_NPS_VNOC_X0Y28", "port0_in", - "NOC_NPS_VNOC_X2Y28", + "NOC_NPS_VNOC_X0Y28", "port2_out", - "NOC_NPS_VNOC_X2Y30", + "NOC_NPS_VNOC_X0Y30", "port0_in", - "NOC_NPS_VNOC_X2Y30", + "NOC_NPS_VNOC_X0Y30", "port2_out", - "NOC_NPS_VNOC_X2Y32", + "NOC_NPS_VNOC_X0Y32", "port0_in", - "NOC_NPS_VNOC_X2Y32", + "NOC_NPS_VNOC_X0Y32", "port2_out", - "NOC_NPS_VNOC_X2Y34", + "NOC_NPS_VNOC_X0Y34", "port0_in", - "NOC_NPS_VNOC_X2Y34", + "NOC_NPS_VNOC_X0Y34", "port2_out", - "NOC_NPS_VNOC_X2Y36", + "NOC_NPS_VNOC_X0Y36", "port0_in", - "NOC_NPS_VNOC_X2Y36", + "NOC_NPS_VNOC_X0Y36", "port2_out", - "NOC_NCRB_X2Y1", + "NOC_NCRB_X0Y1", "port1_in", - "NOC_NCRB_X2Y1", + "NOC_NCRB_X0Y1", "port1_out", - "NOC_NPS5555_X7Y6", + "NOC_NPS5555_X5Y6", "port3_in", - "NOC_NPS5555_X7Y6", + "NOC_NPS5555_X5Y6", "port2_out", - "NOC_NPS6_X5Y2", + "NOC_NPS6_X1Y2", "port0_in", - "NOC_NPS6_X5Y2", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", "port5_out", - "NOC_NPS4_X5Y0", + "NOC_NPS4_X2Y0", "portSideA2_in", - "NOC_NPS4_X5Y0", - "portSideB0_out", - "HBM_MC_X10Y0", + "NOC_NPS4_X2Y0", + "portSideB2_out", + "HBM_MC_X5Y0", "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 135 + "AchievedLatency": 127 }, { - "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceStart": "HBM_MC_X5Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X10Y0", + "HBM_MC_X5Y0", "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB0_in", - "NOC_NPS4_X5Y0", + "NOC_NPS4_X2Y0", + "portSideB2_in", + "NOC_NPS4_X2Y0", "portSideA2_out", - "NOC_NPS6_X5Y2", + "NOC_NPS6_X2Y2", "port5_in", - "NOC_NPS6_X5Y2", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS5555_X7Y6", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS5555_X7Y6", + "NOC_NPS5555_X5Y6", "port3_out", - "NOC_NCRB_X2Y0", + "NOC_NCRB_X0Y0", "port1_in", - "NOC_NCRB_X2Y0", + "NOC_NCRB_X0Y0", "port1_out", - "NOC_NPS_VNOC_X2Y36", + "NOC_NPS_VNOC_X0Y36", "port2_in", - "NOC_NPS_VNOC_X2Y36", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS_VNOC_X2Y34", + "NOC_NPS_VNOC_X0Y34", "port2_in", - "NOC_NPS_VNOC_X2Y34", + "NOC_NPS_VNOC_X0Y34", "port0_out", - "NOC_NPS_VNOC_X2Y32", + "NOC_NPS_VNOC_X0Y32", "port2_in", - "NOC_NPS_VNOC_X2Y32", + "NOC_NPS_VNOC_X0Y32", "port0_out", - "NOC_NPS_VNOC_X2Y30", + "NOC_NPS_VNOC_X0Y30", "port2_in", - "NOC_NPS_VNOC_X2Y30", + "NOC_NPS_VNOC_X0Y30", "port0_out", - "NOC_NPS_VNOC_X2Y28", + "NOC_NPS_VNOC_X0Y28", "port2_in", - "NOC_NPS_VNOC_X2Y28", + "NOC_NPS_VNOC_X0Y28", "port0_out", - "NOC_NPS_VNOC_X2Y26", + "NOC_NPS_VNOC_X0Y26", "port2_in", - "NOC_NPS_VNOC_X2Y26", + "NOC_NPS_VNOC_X0Y26", "port0_out", - "NOC_NPS7575_X6Y6", + "NOC_NPS7575_X4Y6", "port1_in", - "NOC_NPS7575_X6Y6", + "NOC_NPS7575_X4Y6", "port3_out", - "NOC_NIDB_X2Y7", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NIDB_X2Y7", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NIDB_X2Y5", + "NOC_NIDB_X0Y5", "port1_in", - "NOC_NIDB_X2Y5", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS7575_X6Y4", + "NOC_NPS7575_X4Y4", "port3_in", - "NOC_NPS7575_X6Y4", + "NOC_NPS7575_X4Y4", "port1_out", - "NOC_NPS_VNOC_X2Y24", + "NOC_NPS_VNOC_X0Y24", "port2_in", - "NOC_NPS_VNOC_X2Y24", + "NOC_NPS_VNOC_X0Y24", "port0_out", - "NOC_NPS_VNOC_X2Y22", + "NOC_NPS_VNOC_X0Y22", "port2_in", - "NOC_NPS_VNOC_X2Y22", + "NOC_NPS_VNOC_X0Y22", "port0_out", - "NOC_NPS_VNOC_X2Y20", + "NOC_NPS_VNOC_X0Y20", "port2_in", - "NOC_NPS_VNOC_X2Y20", + "NOC_NPS_VNOC_X0Y20", "port0_out", - "NOC_NPS_VNOC_X2Y18", + "NOC_NPS_VNOC_X0Y18", "port2_in", - "NOC_NPS_VNOC_X2Y18", + "NOC_NPS_VNOC_X0Y18", "port0_out", - "NOC_NPS_VNOC_X2Y16", + "NOC_NPS_VNOC_X0Y16", "port2_in", - "NOC_NPS_VNOC_X2Y16", + "NOC_NPS_VNOC_X0Y16", "port0_out", - "NOC_NPS_VNOC_X2Y14", + "NOC_NPS_VNOC_X0Y14", "port2_in", - "NOC_NPS_VNOC_X2Y14", + "NOC_NPS_VNOC_X0Y14", "port0_out", - "NOC_NPS7575_X6Y2", + "NOC_NPS7575_X4Y2", "port1_in", - "NOC_NPS7575_X6Y2", + "NOC_NPS7575_X4Y2", "port3_out", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X0Y3", "port1_out", - "NOC_NIDB_X2Y1", + "NOC_NIDB_X0Y1", "port1_in", - "NOC_NIDB_X2Y1", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS7575_X6Y0", + "NOC_NPS7575_X0Y0", "port3_in", - "NOC_NPS7575_X6Y0", + "NOC_NPS7575_X0Y0", "port1_out", - "NOC_NPS_VNOC_X2Y12", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS_VNOC_X2Y12", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS_VNOC_X2Y10", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS_VNOC_X2Y10", + "NOC_NPS_VNOC_X0Y10", "port0_out", - "NOC_NPS_VNOC_X2Y8", + "NOC_NPS_VNOC_X0Y8", "port2_in", - "NOC_NPS_VNOC_X2Y8", + "NOC_NPS_VNOC_X0Y8", "port0_out", - "NOC_NPS_VNOC_X2Y6", + "NOC_NPS_VNOC_X0Y6", "port2_in", - "NOC_NPS_VNOC_X2Y6", + "NOC_NPS_VNOC_X0Y6", "port0_out", - "NOC_NPS_VNOC_X2Y4", + "NOC_NPS_VNOC_X0Y4", "port2_in", - "NOC_NPS_VNOC_X2Y4", + "NOC_NPS_VNOC_X0Y4", "port0_out", - "NOC_NPS_VNOC_X2Y2", + "NOC_NPS_VNOC_X0Y2", "port2_in", - "NOC_NPS_VNOC_X2Y2", + "NOC_NPS_VNOC_X0Y2", "port0_out", - "NOC_NPS_VNOC_X2Y0", + "NOC_NPS_VNOC_X0Y0", "port2_in", - "NOC_NPS_VNOC_X2Y0", + "NOC_NPS_VNOC_X0Y0", "port0_out", - "NOC_NPS5555_X17Y1", + "NOC_NPS5555_X7Y1", "port2_in", - "NOC_NPS5555_X17Y1", + "NOC_NPS5555_X7Y1", "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", - "port0_out", - "NOC_NPS5555_X15Y0", - "port2_in", - "NOC_NPS5555_X15Y0", - "port0_out", - "NOC_NPS5555_X13Y0", - "port2_in", - "NOC_NPS5555_X13Y0", - "port0_out", - "NOC_NPS5555_X11Y0", - "port2_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", "NOC_NPS5555_X7Y0", - "port2_in", + "port3_in", "NOC_NPS5555_X7Y0", "port0_out", "NOC_NPS5555_X5Y0", @@ -2269,29 +2618,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 127 + }, { "PhyInstanceStart": "HBM_MC_X5Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -2619,10 +2947,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 127 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X5Y0", + "PhyInstanceEnd": "HBM_MC_X15Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -2643,289 +2992,345 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", "port3_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port3_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X6Y2", "port0_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", "port5_out", - "NOC_NPS4_X2Y0", + "NOC_NPS4_X7Y0", "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB2_out", - "HBM_MC_X5Y0", - "pc0_port0_in" + "NOC_NPS4_X7Y0", + "portSideB3_out", + "HBM_MC_X15Y0", + "pc1_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 127 + "AchievedLatency": 141 }, { - "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceStart": "HBM_MC_X15Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X5Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB2_in", - "NOC_NPS4_X2Y0", + "HBM_MC_X15Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB3_in", + "NOC_NPS4_X7Y0", "portSideA2_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X7Y2", "port5_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X7Y2", "port0_out", - "NOC_NPS6_X1Y2", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", "port3_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X6Y2", "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_out", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_in", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_out", - "NOC_NPS5555_X7Y0", + "NOC_NPS5555_X17Y0", "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", "NOC_NPS5555_X7Y0", "port0_out", "NOC_NPS5555_X5Y0", @@ -2946,29 +3351,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 141 + }, { "PhyInstanceStart": "HBM_MC_X15Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -3204,137 +3588,137 @@ "NOC_NPS5555_X17Y0", "port0_in", "NOC_NPS5555_X17Y0", - "port2_out", - "NOC_NPS5555_X19Y0", - "port0_in", - "NOC_NPS5555_X19Y0", - "port2_out", - "NOC_NPS5555_X21Y0", - "port0_in", - "NOC_NPS5555_X21Y0", - "port2_out", - "NOC_NPS5555_X23Y0", - "port0_in", - "NOC_NPS5555_X23Y0", "port3_out", - "NOC_NPS5555_X23Y1", + "NOC_NPS5555_X17Y1", "port1_in", - "NOC_NPS5555_X23Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X3Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X3Y0", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X3Y2", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X3Y2", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X3Y4", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X3Y4", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X3Y6", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X3Y6", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X3Y8", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X3Y8", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X3Y10", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X3Y10", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X3Y12", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X3Y12", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS7575_X7Y0", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X7Y0", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NIDB_X3Y1", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X3Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X3Y3", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X3Y3", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X7Y2", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X7Y2", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NPS_VNOC_X3Y14", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X3Y14", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X3Y16", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X3Y16", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X3Y18", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X3Y18", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X3Y20", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X3Y20", + "NOC_NPS_VNOC_X2Y20", "port2_out", - "NOC_NPS_VNOC_X3Y22", + "NOC_NPS_VNOC_X2Y22", "port0_in", - "NOC_NPS_VNOC_X3Y22", + "NOC_NPS_VNOC_X2Y22", "port2_out", - "NOC_NPS_VNOC_X3Y24", + "NOC_NPS_VNOC_X2Y24", "port0_in", - "NOC_NPS_VNOC_X3Y24", + "NOC_NPS_VNOC_X2Y24", "port2_out", - "NOC_NPS7575_X7Y4", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X7Y4", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NIDB_X3Y5", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NIDB_X3Y5", + "NOC_NIDB_X2Y5", "port1_out", - "NOC_NIDB_X3Y7", + "NOC_NIDB_X2Y7", "port1_in", - "NOC_NIDB_X3Y7", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS7575_X7Y6", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS7575_X7Y6", + "NOC_NPS7575_X6Y6", "port1_out", - "NOC_NPS_VNOC_X3Y26", + "NOC_NPS_VNOC_X2Y26", "port0_in", - "NOC_NPS_VNOC_X3Y26", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS_VNOC_X3Y28", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS_VNOC_X3Y28", + "NOC_NPS_VNOC_X2Y28", "port2_out", - "NOC_NPS_VNOC_X3Y30", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS_VNOC_X3Y30", + "NOC_NPS_VNOC_X2Y30", "port2_out", - "NOC_NPS_VNOC_X3Y32", + "NOC_NPS_VNOC_X2Y32", "port0_in", - "NOC_NPS_VNOC_X3Y32", + "NOC_NPS_VNOC_X2Y32", "port2_out", - "NOC_NPS_VNOC_X3Y34", + "NOC_NPS_VNOC_X2Y34", "port0_in", - "NOC_NPS_VNOC_X3Y34", + "NOC_NPS_VNOC_X2Y34", "port2_out", - "NOC_NPS_VNOC_X3Y36", + "NOC_NPS_VNOC_X2Y36", "port0_in", - "NOC_NPS_VNOC_X3Y36", + "NOC_NPS_VNOC_X2Y36", "port2_out", - "NOC_NCRB_X3Y1", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NCRB_X3Y1", + "NOC_NCRB_X2Y1", "port1_out", - "NOC_NPS5555_X8Y6", + "NOC_NPS5555_X7Y6", "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", "NOC_NPS5555_X8Y6", "port2_out", "NOC_NPS6_X7Y2", @@ -3352,10 +3736,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 141 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X15Y0", + "PhyInstanceEnd": "HBM_MC_X5Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -3376,345 +3781,289 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", "port2_out", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X0Y0", "port0_in", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X0Y0", "port2_out", - "NOC_NPS5555_X11Y0", + "NOC_NPS_VNOC_X0Y2", "port0_in", - "NOC_NPS5555_X11Y0", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", "port3_out", - "NOC_NPS5555_X11Y1", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", + "NOC_NIDB_X0Y3", "port0_out", - "NOC_NPS7575_X5Y1", + "NOC_NPS7575_X4Y2", "port3_in", - "NOC_NPS7575_X5Y1", + "NOC_NPS7575_X4Y2", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS_VNOC_X0Y14", "port0_in", - "NOC_NIDB_X1Y0", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y7", "port1_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y7", "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X4Y6", "port3_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X4Y6", "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X0Y26", "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X0Y28", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X0Y30", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X0Y32", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X0Y34", "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", "port1_in", - "NOC_NPS5555_X8Y4", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", "port2_out", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X1Y2", "port0_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", "port5_out", - "NOC_NPS4_X7Y0", - "portSideA1_in", - "NOC_NPS4_X7Y0", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", "portSideB3_out", - "HBM_MC_X15Y0", + "HBM_MC_X5Y0", "pc1_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 141 + "AchievedLatency": 127 }, { - "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceStart": "HBM_MC_X5Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X15Y0", + "HBM_MC_X5Y0", "pc1_port0_out", - "NOC_NPS4_X7Y0", + "NOC_NPS4_X2Y0", "portSideB3_in", - "NOC_NPS4_X7Y0", - "portSideA1_out", - "NOC_NPS6_X7Y1", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", "port5_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS5555_X8Y4", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X0Y32", "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X0Y32", "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X0Y28", "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X0Y28", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X4Y6", "port1_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X4Y6", "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y5", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS7575_X5Y1", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", "port1_in", - "NOC_NPS7575_X5Y1", + "NOC_NPS7575_X4Y2", "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", + "NOC_NIDB_X0Y3", "port1_out", - "NOC_NPS5555_X11Y0", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", "port3_in", - "NOC_NPS5555_X11Y0", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X0Y10", "port0_out", - "NOC_NPS5555_X7Y0", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", "NOC_NPS5555_X7Y0", "port0_out", "NOC_NPS5555_X5Y0", @@ -3735,29 +4084,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 127 + }, { "PhyInstanceStart": "HBM_MC_X5Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -4085,10 +4413,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 127 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X5Y0", + "PhyInstanceEnd": "HBM_MC_X1Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -4229,49 +4578,41 @@ "NOC_NPS5555_X5Y6", "port3_in", "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", "port5_out", - "NOC_NPS4_X2Y0", + "NOC_NPS4_X0Y0", "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB3_out", - "HBM_MC_X5Y0", - "pc1_port0_in" + "NOC_NPS4_X0Y0", + "portSideB2_out", + "HBM_MC_X1Y0", + "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 127 + "AchievedLatency": 125 }, { - "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceStart": "HBM_MC_X1Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X5Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB3_in", - "NOC_NPS4_X2Y0", + "HBM_MC_X1Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB2_in", + "NOC_NPS4_X0Y0", "portSideA2_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X0Y2", "port5_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", + "NOC_NPS6_X0Y2", + "port3_out", "NOC_NPS5555_X5Y6", - "port2_in", + "port1_in", "NOC_NPS5555_X5Y6", "port3_out", "NOC_NCRB_X0Y0", @@ -4412,29 +4753,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 125 + }, { "PhyInstanceStart": "HBM_MC_X1Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -4754,7 +5074,28 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", "PhyInstanceEnd": "HBM_MC_X1Y0", @@ -4906,9 +5247,9 @@ "NOC_NPS4_X0Y0", "portSideA2_in", "NOC_NPS4_X0Y0", - "portSideB2_out", + "portSideB3_out", "HBM_MC_X1Y0", - "pc0_port0_in" + "pc1_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, @@ -4922,9 +5263,9 @@ "CommType": "WRITE_RESP", "Connections": [ "HBM_MC_X1Y0", - "pc0_port0_out", + "pc1_port0_out", "NOC_NPS4_X0Y0", - "portSideB2_in", + "portSideB3_in", "NOC_NPS4_X0Y0", "portSideA2_out", "NOC_NPS6_X0Y2", @@ -5074,28 +5415,7 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { "PhyInstanceStart": "HBM_MC_X1Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -5415,10 +5735,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X1Y0", + "PhyInstanceEnd": "HBM_MC_X6Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -5559,209 +5900,212 @@ "NOC_NPS5555_X5Y6", "port3_in", "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", "port5_out", - "NOC_NPS4_X0Y0", + "NOC_NPS4_X3Y0", "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB3_out", - "HBM_MC_X1Y0", - "pc1_port0_in" + "NOC_NPS4_X3Y0", + "portSideB0_out", + "HBM_MC_X6Y0", + "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 125 + "AchievedLatency": 131 }, { - "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceStart": "HBM_MC_X6Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X1Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB3_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", + "Connections": [ + "HBM_MC_X6Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB0_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", "Connections": [ "HBM_MC_X6Y0", "pc0_port0_out", @@ -6100,10 +6444,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 131 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X6Y0", + "PhyInstanceEnd": "HBM_MC_X12Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -6124,312 +6489,336 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", "port3_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X5Y2", "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X6Y2", "port0_in", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X6Y2", "port5_out", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X6Y0", "portSideA2_in", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X6Y0", "portSideB0_out", - "HBM_MC_X6Y0", + "HBM_MC_X12Y0", "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 131 + "AchievedLatency": 137 }, { - "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceStart": "HBM_MC_X12Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X6Y0", + "HBM_MC_X12Y0", "pc0_port0_out", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X6Y0", "portSideB0_in", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X6Y0", "portSideA2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X6Y2", "port5_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X6Y2", "port0_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port3_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_out", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_in", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_out", - "NOC_NPS5555_X7Y0", + "NOC_NPS5555_X17Y0", "port3_in", - "NOC_NPS5555_X7Y0", + "NOC_NPS5555_X17Y0", "port0_out", - "NOC_NPS5555_X5Y0", + "NOC_NPS5555_X15Y0", "port2_in", - "NOC_NPS5555_X5Y0", + "NOC_NPS5555_X15Y0", "port0_out", - "NOC_NPS5555_X3Y0", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", "port2_in", "NOC_NPS5555_X3Y0", "port0_out", @@ -6443,29 +6832,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 137 + }, { "PhyInstanceStart": "HBM_MC_X12Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -6833,10 +7201,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 137 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X12Y0", + "PhyInstanceEnd": "HBM_MC_X0Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -6857,377 +7246,148 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS5555_X7Y1", "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X7Y1", "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X0Y0", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X0Y0", "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB0_out", - "HBM_MC_X12Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X12Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB0_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X0Y2", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X0Y2", "port2_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X0Y4", "port0_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X0Y4", "port2_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X0Y6", "port0_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X0Y6", "port2_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y8", "port0_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y8", "port2_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y10", "port0_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y10", "port2_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y12", "port0_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y12", "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X0Y1", "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y3", "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y3", "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", "port0_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X0Y14", "port2_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port0_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port2_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port0_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port2_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port0_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port2_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port0_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port2_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X0Y24", "port0_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X0Y24", "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y5", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y7", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y7", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", "port0_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y26", "port2_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y28", "port0_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y28", "port2_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y30", "port0_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y30", "port2_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y32", "port0_in", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y32", "port2_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X0Y34", "port0_in", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X0Y34", "port2_out", - "NOC_NPS_VNOC_X1Y1", + "NOC_NPS_VNOC_X0Y36", "port0_in", - "NOC_NPS_VNOC_X1Y1", + "NOC_NPS_VNOC_X0Y36", "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", "port1_out", - "NOC_NPS5555_X11Y0", + "NOC_NPS5555_X5Y6", "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB1_out", + "HBM_MC_X0Y0", + "pc1_port0_in" ], - "RequiredBW": 33, - "AchievedBW": 33, + "RequiredBW": 165, + "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 125 + }, { "PhyInstanceStart": "HBM_MC_X0Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", + "VC": 7, + "CommType": "WRITE_RESP", "Connections": [ "HBM_MC_X0Y0", "pc1_port0_out", @@ -7378,43 +7538,203 @@ "NOC_NMU128_X0Y0", "resp_in" ], - "RequiredBW": 132, - "AchievedBW": 132, + "RequiredBW": 33, + "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 }, { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", + "HBM_MC_X0Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB1_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", "port3_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X5Y6", "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", "NOC_NPS_VNOC_X0Y2", "port0_in", "NOC_NPS_VNOC_X0Y2", @@ -7542,10 +7862,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X0Y0", + "PhyInstanceEnd": "HBM_MC_X6Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -7686,41 +8027,65 @@ "NOC_NPS5555_X5Y6", "port3_in", "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", "port5_out", - "NOC_NPS4_X0Y0", + "NOC_NPS4_X3Y0", "portSideA2_in", - "NOC_NPS4_X0Y0", + "NOC_NPS4_X3Y0", "portSideB1_out", - "HBM_MC_X0Y0", + "HBM_MC_X6Y0", "pc1_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 125 + "AchievedLatency": 131 }, { - "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceStart": "HBM_MC_X6Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X0Y0", + "HBM_MC_X6Y0", "pc1_port0_out", - "NOC_NPS4_X0Y0", + "NOC_NPS4_X3Y0", "portSideB1_in", - "NOC_NPS4_X0Y0", + "NOC_NPS4_X3Y0", "portSideA2_out", - "NOC_NPS6_X0Y2", + "NOC_NPS6_X3Y2", "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", "NOC_NPS5555_X5Y6", - "port1_in", + "port2_in", "NOC_NPS5555_X5Y6", "port3_out", "NOC_NCRB_X0Y0", @@ -7861,29 +8226,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 131 + }, { "PhyInstanceStart": "HBM_MC_X6Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -8079,137 +8423,137 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS5555_X9Y0", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS5555_X9Y0", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS5555_X11Y0", "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS5555_X11Y0", "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NPS5555_X11Y1", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X1Y4", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X1Y6", "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X1Y36", + "port1_in", + "NOC_NPS_VNOC_X1Y36", "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X1Y1", "port1_in", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X1Y1", "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", "NOC_NPS5555_X6Y6", - "port1_in", + "port3_in", "NOC_NPS5555_X6Y6", "port2_out", "NOC_NPS6_X3Y2", @@ -8227,10 +8571,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 131 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X6Y0", + "PhyInstanceEnd": "HBM_MC_X14Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -8251,305 +8616,345 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", "port3_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port3_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X6Y2", "port0_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X6Y2", "port3_out", - "NOC_NPS5555_X6Y6", + "NOC_NPS5555_X8Y6", "port1_in", - "NOC_NPS5555_X6Y6", + "NOC_NPS5555_X8Y6", "port2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X7Y2", "port0_in", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X7Y2", "port5_out", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X7Y0", "portSideA2_in", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X7Y0", "portSideB1_out", - "HBM_MC_X6Y0", + "HBM_MC_X14Y0", "pc1_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 131 + "AchievedLatency": 141 }, { - "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceStart": "HBM_MC_X14Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X6Y0", + "HBM_MC_X14Y0", "pc1_port0_out", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X7Y0", "portSideB1_in", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X7Y0", "portSideA2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X7Y2", "port5_in", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X7Y2", "port0_out", - "NOC_NPS5555_X6Y6", + "NOC_NPS5555_X8Y6", "port2_in", - "NOC_NPS5555_X6Y6", + "NOC_NPS5555_X8Y6", "port1_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X6Y2", "port3_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X6Y2", "port0_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port3_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_out", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_in", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_out", - "NOC_NPS5555_X7Y0", + "NOC_NPS5555_X17Y0", "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", "NOC_NPS5555_X7Y0", "port0_out", "NOC_NPS5555_X5Y0", @@ -8570,29 +8975,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 141 + }, { "PhyInstanceStart": "HBM_MC_X14Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -8976,10 +9360,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 141 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X14Y0", + "PhyInstanceEnd": "HBM_MC_X12Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -9148,49 +9553,33 @@ "NOC_NPS6_X6Y2", "port0_in", "NOC_NPS6_X6Y2", - "port3_out", - "NOC_NPS5555_X8Y6", - "port1_in", - "NOC_NPS5555_X8Y6", - "port2_out", - "NOC_NPS6_X7Y2", - "port0_in", - "NOC_NPS6_X7Y2", "port5_out", - "NOC_NPS4_X7Y0", + "NOC_NPS4_X6Y0", "portSideA2_in", - "NOC_NPS4_X7Y0", + "NOC_NPS4_X6Y0", "portSideB1_out", - "HBM_MC_X14Y0", + "HBM_MC_X12Y0", "pc1_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 141 + "AchievedLatency": 137 }, { - "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceStart": "HBM_MC_X12Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X14Y0", + "HBM_MC_X12Y0", "pc1_port0_out", - "NOC_NPS4_X7Y0", + "NOC_NPS4_X6Y0", "portSideB1_in", - "NOC_NPS4_X7Y0", + "NOC_NPS4_X6Y0", "portSideA2_out", - "NOC_NPS6_X7Y2", - "port5_in", - "NOC_NPS6_X7Y2", - "port0_out", - "NOC_NPS5555_X8Y6", - "port2_in", - "NOC_NPS5555_X8Y6", - "port1_out", "NOC_NPS6_X6Y2", - "port3_in", + "port5_in", "NOC_NPS6_X6Y2", "port0_out", "NOC_NPS6_X5Y2", @@ -9359,29 +9748,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 137 + }, { "PhyInstanceStart": "HBM_MC_X12Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -9749,10 +10117,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 137 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X12Y0", + "PhyInstanceEnd": "HBM_MC_X0Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -9773,342 +10162,294 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", "port2_out", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X0Y0", "port0_in", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X0Y0", "port2_out", - "NOC_NPS5555_X11Y0", + "NOC_NPS_VNOC_X0Y2", "port0_in", - "NOC_NPS5555_X11Y0", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", "port3_out", - "NOC_NPS5555_X11Y1", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", "port1_in", - "NOC_NPS5555_X11Y1", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", "port0_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB0_out", + "HBM_MC_X0Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X0Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB0_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", "port2_in", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y34", "port2_in", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y34", "port0_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y32", "port2_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y32", "port0_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y30", "port2_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y30", "port0_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y28", "port2_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y28", "port0_out", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X0Y26", "port2_in", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X0Y26", "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y5", "port1_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", "port2_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X0Y24", "port0_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port2_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port0_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port2_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port0_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port2_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port0_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port2_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port0_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X0Y14", "port2_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X0Y14", "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y3", "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X0Y1", "port1_in", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y10", "port0_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y8", "port2_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y8", "port0_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X0Y6", "port2_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X0Y6", "port0_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X0Y4", "port2_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X0Y4", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X0Y2", "port2_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X0Y2", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB1_out", - "HBM_MC_X12Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X12Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB1_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", "port3_out", "NOC_NMU128_X0Y0", "resp_in" @@ -10116,29 +10457,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 125 + }, { "PhyInstanceStart": "HBM_MC_X0Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -10458,10 +10778,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X0Y0", + "PhyInstanceEnd": "HBM_MC_X8Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -10602,41 +10943,73 @@ "NOC_NPS5555_X5Y6", "port3_in", "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", "port5_out", - "NOC_NPS4_X0Y0", + "NOC_NPS4_X4Y0", "portSideA2_in", - "NOC_NPS4_X0Y0", + "NOC_NPS4_X4Y0", "portSideB0_out", - "HBM_MC_X0Y0", + "HBM_MC_X8Y0", "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 125 + "AchievedLatency": 133 }, { - "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceStart": "HBM_MC_X8Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X0Y0", + "HBM_MC_X8Y0", "pc0_port0_out", - "NOC_NPS4_X0Y0", + "NOC_NPS4_X4Y0", "portSideB0_in", - "NOC_NPS4_X0Y0", + "NOC_NPS4_X4Y0", "portSideA2_out", - "NOC_NPS6_X0Y2", + "NOC_NPS6_X4Y2", "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", "NOC_NPS5555_X5Y6", - "port1_in", + "port2_in", "NOC_NPS5555_X5Y6", "port3_out", "NOC_NCRB_X0Y0", @@ -10777,29 +11150,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 133 + }, { "PhyInstanceStart": "HBM_MC_X8Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -11151,7 +11503,28 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 133 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", "PhyInstanceEnd": "HBM_MC_X8Y0", @@ -11175,169 +11548,337 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", "port3_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X11Y1", "port1_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X11Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS6_X3Y1", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA1_in", + "NOC_NPS4_X4Y0", + "portSideB1_out", + "HBM_MC_X8Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X8Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB1_in", + "NOC_NPS4_X4Y0", + "portSideA1_out", + "NOC_NPS6_X4Y1", + "port5_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", "port2_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X1Y35", "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X1Y35", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X1Y33", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X1Y33", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X1Y31", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X1Y31", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X1Y29", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X1Y29", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X1Y27", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X1Y27", "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X1Y6", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X1Y4", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X1Y4", "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X1Y25", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X1Y23", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X1Y23", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X1Y21", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X1Y21", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X1Y19", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X1Y19", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X1Y17", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X1Y17", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X1Y15", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X1Y15", "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X1Y2", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X1Y0", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X1Y13", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X1Y11", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X1Y11", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X1Y9", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X1Y9", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X1Y7", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X1Y7", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X1Y5", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X1Y5", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X1Y3", "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS_VNOC_X1Y3", "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", + "NOC_NPS_VNOC_X1Y1", "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", + "NOC_NPS_VNOC_X1Y1", "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB0_out", - "HBM_MC_X8Y0", - "pc0_port0_in" + "NOC_NMU128_X0Y0", + "resp_in" ], - "RequiredBW": 165, - "AchievedBW": 165, + "RequiredBW": 33, + "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 133 + "AchievedLatency": 131 }, { "PhyInstanceStart": "HBM_MC_X8Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", + "VC": 6, + "CommType": "READ", "Connections": [ "HBM_MC_X8Y0", - "pc0_port0_out", + "pc1_port0_out", "NOC_NPS4_X4Y0", - "portSideB0_in", + "portSideB1_in", "NOC_NPS4_X4Y0", "portSideA2_out", "NOC_NPS6_X4Y2", @@ -11499,233 +12040,36 @@ "NOC_NMU128_X0Y0", "resp_in" ], - "RequiredBW": 33, - "AchievedBW": 33, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, "AchievedLatency": 133 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 4, + "CommType": "READ_REQ", "Connections": [ - "HBM_MC_X8Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB1_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X7Y1", "port1_in", "NOC_NPS5555_X7Y1", "port2_out", @@ -11876,10 +12220,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 133 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X8Y0", + "PhyInstanceEnd": "HBM_MC_X14Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -12036,33 +12401,73 @@ "NOC_NPS6_X4Y1", "port0_in", "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", "port5_out", - "NOC_NPS4_X4Y0", + "NOC_NPS4_X7Y0", "portSideA1_in", - "NOC_NPS4_X4Y0", - "portSideB1_out", - "HBM_MC_X8Y0", - "pc1_port0_in" + "NOC_NPS4_X7Y0", + "portSideB0_out", + "HBM_MC_X14Y0", + "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 131 + "AchievedLatency": 141 }, { - "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceStart": "HBM_MC_X14Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X8Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB1_in", - "NOC_NPS4_X4Y0", + "HBM_MC_X14Y0", + "pc0_port0_out", + "NOC_NPS4_X7Y0", + "portSideB0_in", + "NOC_NPS4_X7Y0", "portSideA1_out", - "NOC_NPS6_X4Y1", + "NOC_NPS6_X7Y1", "port5_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", "NOC_NPS6_X4Y1", "port0_out", "NOC_NPS6_X3Y1", @@ -12219,29 +12624,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 141 + }, { "PhyInstanceStart": "HBM_MC_X14Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -12253,157 +12637,157 @@ "NOC_NPS4_X7Y0", "portSideB0_in", "NOC_NPS4_X7Y0", - "portSideA1_out", - "NOC_NPS6_X7Y1", + "portSideA2_out", + "NOC_NPS6_X7Y2", "port5_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X7Y2", "port0_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS5555_X8Y6", "port2_in", - "NOC_NPS5555_X8Y4", + "NOC_NPS5555_X8Y6", "port1_out", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X6Y2", "port3_in", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X6Y2", "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", "port1_out", - "NOC_NPS5555_X11Y0", + "NOC_NPS5555_X17Y0", "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", "NOC_NPS5555_X11Y0", "port0_out", "NOC_NPS5555_X9Y0", @@ -12439,198 +12823,6 @@ "PhyInstanceEnd": "HBM_MC_X14Y0", "VC": 4, "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA1_in", - "NOC_NPS4_X7Y0", - "portSideB0_out", - "HBM_MC_X14Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 5, - "CommType": "WRITE", "Connections": [ "NOC_NMU128_X0Y0", "req_out", @@ -12813,181 +13005,330 @@ "HBM_MC_X14Y0", "pc0_port0_in" ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB2_out", + "HBM_MC_X3Y0", + "pc0_port0_in" + ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 141 + "AchievedLatency": 125 }, { - "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceStart": "HBM_MC_X3Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X14Y0", + "HBM_MC_X3Y0", "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB0_in", - "NOC_NPS4_X7Y0", + "NOC_NPS4_X1Y0", + "portSideB2_in", + "NOC_NPS4_X1Y0", "portSideA2_out", - "NOC_NPS6_X7Y2", + "NOC_NPS6_X1Y2", "port5_in", - "NOC_NPS6_X7Y2", - "port0_out", - "NOC_NPS5555_X8Y6", - "port2_in", - "NOC_NPS5555_X8Y6", - "port1_out", - "NOC_NPS6_X6Y2", - "port3_in", - "NOC_NPS6_X6Y2", - "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", + "NOC_NPS6_X1Y2", "port0_out", - "NOC_NPS5555_X7Y6", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS5555_X7Y6", + "NOC_NPS5555_X5Y6", "port3_out", - "NOC_NCRB_X2Y0", + "NOC_NCRB_X0Y0", "port1_in", - "NOC_NCRB_X2Y0", + "NOC_NCRB_X0Y0", "port1_out", - "NOC_NPS_VNOC_X2Y36", + "NOC_NPS_VNOC_X0Y36", "port2_in", - "NOC_NPS_VNOC_X2Y36", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS_VNOC_X2Y34", + "NOC_NPS_VNOC_X0Y34", "port2_in", - "NOC_NPS_VNOC_X2Y34", + "NOC_NPS_VNOC_X0Y34", "port0_out", - "NOC_NPS_VNOC_X2Y32", + "NOC_NPS_VNOC_X0Y32", "port2_in", - "NOC_NPS_VNOC_X2Y32", + "NOC_NPS_VNOC_X0Y32", "port0_out", - "NOC_NPS_VNOC_X2Y30", + "NOC_NPS_VNOC_X0Y30", "port2_in", - "NOC_NPS_VNOC_X2Y30", + "NOC_NPS_VNOC_X0Y30", "port0_out", - "NOC_NPS_VNOC_X2Y28", + "NOC_NPS_VNOC_X0Y28", "port2_in", - "NOC_NPS_VNOC_X2Y28", + "NOC_NPS_VNOC_X0Y28", "port0_out", - "NOC_NPS_VNOC_X2Y26", + "NOC_NPS_VNOC_X0Y26", "port2_in", - "NOC_NPS_VNOC_X2Y26", + "NOC_NPS_VNOC_X0Y26", "port0_out", - "NOC_NPS7575_X6Y6", + "NOC_NPS7575_X4Y6", "port1_in", - "NOC_NPS7575_X6Y6", + "NOC_NPS7575_X4Y6", "port3_out", - "NOC_NIDB_X2Y7", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NIDB_X2Y7", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NIDB_X2Y5", + "NOC_NIDB_X0Y5", "port1_in", - "NOC_NIDB_X2Y5", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS7575_X6Y4", + "NOC_NPS7575_X4Y4", "port3_in", - "NOC_NPS7575_X6Y4", + "NOC_NPS7575_X4Y4", "port1_out", - "NOC_NPS_VNOC_X2Y24", + "NOC_NPS_VNOC_X0Y24", "port2_in", - "NOC_NPS_VNOC_X2Y24", + "NOC_NPS_VNOC_X0Y24", "port0_out", - "NOC_NPS_VNOC_X2Y22", + "NOC_NPS_VNOC_X0Y22", "port2_in", - "NOC_NPS_VNOC_X2Y22", + "NOC_NPS_VNOC_X0Y22", "port0_out", - "NOC_NPS_VNOC_X2Y20", + "NOC_NPS_VNOC_X0Y20", "port2_in", - "NOC_NPS_VNOC_X2Y20", + "NOC_NPS_VNOC_X0Y20", "port0_out", - "NOC_NPS_VNOC_X2Y18", + "NOC_NPS_VNOC_X0Y18", "port2_in", - "NOC_NPS_VNOC_X2Y18", + "NOC_NPS_VNOC_X0Y18", "port0_out", - "NOC_NPS_VNOC_X2Y16", + "NOC_NPS_VNOC_X0Y16", "port2_in", - "NOC_NPS_VNOC_X2Y16", + "NOC_NPS_VNOC_X0Y16", "port0_out", - "NOC_NPS_VNOC_X2Y14", + "NOC_NPS_VNOC_X0Y14", "port2_in", - "NOC_NPS_VNOC_X2Y14", + "NOC_NPS_VNOC_X0Y14", "port0_out", - "NOC_NPS7575_X6Y2", + "NOC_NPS7575_X4Y2", "port1_in", - "NOC_NPS7575_X6Y2", + "NOC_NPS7575_X4Y2", "port3_out", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X0Y3", "port1_out", - "NOC_NIDB_X2Y1", + "NOC_NIDB_X0Y1", "port1_in", - "NOC_NIDB_X2Y1", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS7575_X6Y0", + "NOC_NPS7575_X0Y0", "port3_in", - "NOC_NPS7575_X6Y0", + "NOC_NPS7575_X0Y0", "port1_out", - "NOC_NPS_VNOC_X2Y12", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS_VNOC_X2Y12", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS_VNOC_X2Y10", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS_VNOC_X2Y10", + "NOC_NPS_VNOC_X0Y10", "port0_out", - "NOC_NPS_VNOC_X2Y8", + "NOC_NPS_VNOC_X0Y8", "port2_in", - "NOC_NPS_VNOC_X2Y8", + "NOC_NPS_VNOC_X0Y8", "port0_out", - "NOC_NPS_VNOC_X2Y6", + "NOC_NPS_VNOC_X0Y6", "port2_in", - "NOC_NPS_VNOC_X2Y6", + "NOC_NPS_VNOC_X0Y6", "port0_out", - "NOC_NPS_VNOC_X2Y4", + "NOC_NPS_VNOC_X0Y4", "port2_in", - "NOC_NPS_VNOC_X2Y4", + "NOC_NPS_VNOC_X0Y4", "port0_out", - "NOC_NPS_VNOC_X2Y2", + "NOC_NPS_VNOC_X0Y2", "port2_in", - "NOC_NPS_VNOC_X2Y2", + "NOC_NPS_VNOC_X0Y2", "port0_out", - "NOC_NPS_VNOC_X2Y0", + "NOC_NPS_VNOC_X0Y0", "port2_in", - "NOC_NPS_VNOC_X2Y0", + "NOC_NPS_VNOC_X0Y0", "port0_out", - "NOC_NPS5555_X17Y1", + "NOC_NPS5555_X7Y1", "port2_in", - "NOC_NPS5555_X17Y1", + "NOC_NPS5555_X7Y1", "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", - "port0_out", - "NOC_NPS5555_X15Y0", - "port2_in", - "NOC_NPS5555_X15Y0", - "port0_out", - "NOC_NPS5555_X13Y0", - "port2_in", - "NOC_NPS5555_X13Y0", - "port0_out", - "NOC_NPS5555_X11Y0", - "port2_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", "NOC_NPS5555_X7Y0", - "port2_in", + "port3_in", "NOC_NPS5555_X7Y0", "port0_out", "NOC_NPS5555_X5Y0", @@ -13008,29 +13349,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 125 + }, { "PhyInstanceStart": "HBM_MC_X3Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -13350,7 +13670,28 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", "PhyInstanceEnd": "HBM_MC_X3Y0", @@ -13502,9 +13843,9 @@ "NOC_NPS4_X1Y0", "portSideA2_in", "NOC_NPS4_X1Y0", - "portSideB2_out", + "portSideB3_out", "HBM_MC_X3Y0", - "pc0_port0_in" + "pc1_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, @@ -13518,9 +13859,9 @@ "CommType": "WRITE_RESP", "Connections": [ "HBM_MC_X3Y0", - "pc0_port0_out", + "pc1_port0_out", "NOC_NPS4_X1Y0", - "portSideB2_in", + "portSideB3_in", "NOC_NPS4_X1Y0", "portSideA2_out", "NOC_NPS6_X1Y2", @@ -13670,28 +14011,7 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { "PhyInstanceStart": "HBM_MC_X3Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -14011,10 +14331,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X3Y0", + "PhyInstanceEnd": "HBM_MC_X4Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -14159,33 +14500,41 @@ "NOC_NPS6_X1Y2", "port0_in", "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", "port5_out", - "NOC_NPS4_X1Y0", + "NOC_NPS4_X2Y0", "portSideA2_in", - "NOC_NPS4_X1Y0", - "portSideB3_out", - "HBM_MC_X3Y0", + "NOC_NPS4_X2Y0", + "portSideB1_out", + "HBM_MC_X4Y0", "pc1_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 125 + "AchievedLatency": 127 }, { - "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceStart": "HBM_MC_X4Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X3Y0", + "HBM_MC_X4Y0", "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB3_in", - "NOC_NPS4_X1Y0", + "NOC_NPS4_X2Y0", + "portSideB1_in", + "NOC_NPS4_X2Y0", "portSideA2_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X2Y2", "port5_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", "NOC_NPS6_X1Y2", "port0_out", "NOC_NPS5555_X5Y6", @@ -14330,29 +14679,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 127 + }, { "PhyInstanceStart": "HBM_MC_X4Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -14680,7 +15008,28 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 127 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", "PhyInstanceEnd": "HBM_MC_X4Y0", @@ -14836,9 +15185,9 @@ "NOC_NPS4_X2Y0", "portSideA2_in", "NOC_NPS4_X2Y0", - "portSideB1_out", + "portSideB0_out", "HBM_MC_X4Y0", - "pc1_port0_in" + "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, @@ -14852,9 +15201,9 @@ "CommType": "WRITE_RESP", "Connections": [ "HBM_MC_X4Y0", - "pc1_port0_out", + "pc0_port0_out", "NOC_NPS4_X2Y0", - "portSideB1_in", + "portSideB0_in", "NOC_NPS4_X2Y0", "portSideA2_out", "NOC_NPS6_X2Y2", @@ -15008,28 +15357,7 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { "PhyInstanceStart": "HBM_MC_X4Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -15357,10 +15685,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 127 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X4Y0", + "PhyInstanceEnd": "HBM_MC_X9Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -15509,33 +15858,57 @@ "NOC_NPS6_X2Y2", "port0_in", "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", "port5_out", - "NOC_NPS4_X2Y0", + "NOC_NPS4_X4Y0", "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB0_out", - "HBM_MC_X4Y0", + "NOC_NPS4_X4Y0", + "portSideB2_out", + "HBM_MC_X9Y0", "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 127 + "AchievedLatency": 133 }, { - "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceStart": "HBM_MC_X9Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X4Y0", + "HBM_MC_X9Y0", "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB0_in", - "NOC_NPS4_X2Y0", + "NOC_NPS4_X4Y0", + "portSideB2_in", + "NOC_NPS4_X4Y0", "portSideA2_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X4Y2", "port5_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", "NOC_NPS6_X2Y2", "port0_out", "NOC_NPS6_X1Y2", @@ -15684,29 +16057,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 133 + }, { "PhyInstanceStart": "HBM_MC_X9Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -16058,10 +16410,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 133 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X9Y0", + "PhyInstanceEnd": "HBM_MC_X2Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -16206,237 +16579,184 @@ "NOC_NPS6_X1Y2", "port0_in", "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", "port5_out", - "NOC_NPS4_X4Y0", + "NOC_NPS4_X1Y0", "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB2_out", - "HBM_MC_X9Y0", + "NOC_NPS4_X1Y0", + "portSideB0_out", + "HBM_MC_X2Y0", "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 133 + "AchievedLatency": 125 }, { - "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceStart": "HBM_MC_X2Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X9Y0", - "pc0_port0_out", - "NOC_NPS4_X4Y0", - "portSideB2_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", + "Connections": [ + "HBM_MC_X2Y0", + "pc0_port0_out", + "NOC_NPS4_X1Y0", + "portSideB0_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", "Connections": [ "HBM_MC_X2Y0", "pc0_port0_out", @@ -16751,10 +17071,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X2Y0", + "PhyInstanceEnd": "HBM_MC_X11Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -16775,281 +17116,321 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", "port3_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port5_out", - "NOC_NPS4_X1Y0", + "NOC_NPS4_X5Y0", "portSideA2_in", - "NOC_NPS4_X1Y0", - "portSideB0_out", - "HBM_MC_X2Y0", + "NOC_NPS4_X5Y0", + "portSideB2_out", + "HBM_MC_X11Y0", "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 125 + "AchievedLatency": 135 }, { - "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceStart": "HBM_MC_X11Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X2Y0", + "HBM_MC_X11Y0", "pc0_port0_out", - "NOC_NPS4_X1Y0", - "portSideB0_in", - "NOC_NPS4_X1Y0", + "NOC_NPS4_X5Y0", + "portSideB2_in", + "NOC_NPS4_X5Y0", "portSideA2_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port5_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_out", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_in", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_out", - "NOC_NPS5555_X7Y0", + "NOC_NPS5555_X17Y0", "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", "NOC_NPS5555_X7Y0", "port0_out", "NOC_NPS5555_X5Y0", @@ -17070,29 +17451,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 135 + }, { "PhyInstanceStart": "HBM_MC_X11Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -17104,360 +17464,180 @@ "NOC_NPS4_X5Y0", "portSideB2_in", "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", + "portSideA2_out", + "NOC_NPS6_X5Y2", "port5_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X7Y6", "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NCRB_X2Y0", "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS_VNOC_X2Y36", "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS5555_X7Y0", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS5555_X7Y0", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS5555_X5Y0", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS5555_X5Y0", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS5555_X3Y0", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS5555_X3Y0", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS5555_X1Y0", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS5555_X1Y0", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS5555_X15Y0", "port2_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS5555_X15Y0", "port0_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS5555_X13Y0", "port2_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS5555_X13Y0", "port0_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X11Y0", "port2_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X11Y0", "port0_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X9Y0", "port2_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X9Y0", "port0_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X7Y0", "port2_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X7Y0", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X5Y0", "port2_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X5Y0", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB2_out", - "HBM_MC_X11Y0", - "pc0_port0_in" + "NOC_NMU128_X0Y0", + "resp_in" ], - "RequiredBW": 33, - "AchievedBW": 33, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, "AchievedLatency": 135 }, { "PhyInstanceStart": "NOC_NMU128_X0Y0", "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 5, - "CommType": "WRITE", + "VC": 4, + "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y0", "req_out", @@ -17628,169 +17808,362 @@ "HBM_MC_X11Y0", "pc0_port0_in" ], - "RequiredBW": 165, - "AchievedBW": 165, + "RequiredBW": 33, + "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 135 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X11Y0", - "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB2_in", - "NOC_NPS4_X5Y0", - "portSideA2_out", - "NOC_NPS6_X5Y2", - "port5_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", "port3_out", - "NOC_NCRB_X2Y0", + "NOC_NPS5555_X7Y1", "port1_in", - "NOC_NCRB_X2Y0", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", "port1_in", - "NOC_NPS7575_X6Y6", + "NOC_NPS7575_X4Y4", "port3_out", - "NOC_NIDB_X2Y7", + "NOC_NIDB_X0Y5", "port0_in", - "NOC_NIDB_X2Y7", + "NOC_NIDB_X0Y5", "port1_out", - "NOC_NIDB_X2Y5", + "NOC_NIDB_X0Y7", "port1_in", - "NOC_NIDB_X2Y5", + "NOC_NIDB_X0Y7", "port0_out", - "NOC_NPS7575_X6Y4", + "NOC_NPS7575_X4Y6", "port3_in", - "NOC_NPS7575_X6Y4", + "NOC_NPS7575_X4Y6", "port1_out", - "NOC_NPS_VNOC_X2Y24", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA2_in", + "NOC_NPS4_X4Y0", + "portSideB3_out", + "HBM_MC_X9Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X9Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB3_in", + "NOC_NPS4_X4Y0", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port5_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", "port2_in", - "NOC_NPS_VNOC_X2Y24", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS_VNOC_X2Y22", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS_VNOC_X2Y22", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS_VNOC_X2Y20", + "NOC_NPS_VNOC_X0Y34", "port2_in", - "NOC_NPS_VNOC_X2Y20", + "NOC_NPS_VNOC_X0Y34", "port0_out", - "NOC_NPS_VNOC_X2Y18", + "NOC_NPS_VNOC_X0Y32", "port2_in", - "NOC_NPS_VNOC_X2Y18", + "NOC_NPS_VNOC_X0Y32", "port0_out", - "NOC_NPS_VNOC_X2Y16", + "NOC_NPS_VNOC_X0Y30", "port2_in", - "NOC_NPS_VNOC_X2Y16", + "NOC_NPS_VNOC_X0Y30", "port0_out", - "NOC_NPS_VNOC_X2Y14", + "NOC_NPS_VNOC_X0Y28", "port2_in", - "NOC_NPS_VNOC_X2Y14", + "NOC_NPS_VNOC_X0Y28", "port0_out", - "NOC_NPS7575_X6Y2", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", "port1_in", - "NOC_NPS7575_X6Y2", + "NOC_NPS7575_X4Y6", "port3_out", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NIDB_X2Y1", + "NOC_NIDB_X0Y5", "port1_in", - "NOC_NIDB_X2Y1", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS7575_X6Y0", + "NOC_NPS7575_X4Y4", "port3_in", - "NOC_NPS7575_X6Y0", + "NOC_NPS7575_X4Y4", "port1_out", - "NOC_NPS_VNOC_X2Y12", + "NOC_NPS_VNOC_X0Y24", "port2_in", - "NOC_NPS_VNOC_X2Y12", + "NOC_NPS_VNOC_X0Y24", "port0_out", - "NOC_NPS_VNOC_X2Y10", + "NOC_NPS_VNOC_X0Y22", "port2_in", - "NOC_NPS_VNOC_X2Y10", + "NOC_NPS_VNOC_X0Y22", "port0_out", - "NOC_NPS_VNOC_X2Y8", + "NOC_NPS_VNOC_X0Y20", "port2_in", - "NOC_NPS_VNOC_X2Y8", + "NOC_NPS_VNOC_X0Y20", "port0_out", - "NOC_NPS_VNOC_X2Y6", + "NOC_NPS_VNOC_X0Y18", "port2_in", - "NOC_NPS_VNOC_X2Y6", + "NOC_NPS_VNOC_X0Y18", "port0_out", - "NOC_NPS_VNOC_X2Y4", + "NOC_NPS_VNOC_X0Y16", "port2_in", - "NOC_NPS_VNOC_X2Y4", + "NOC_NPS_VNOC_X0Y16", "port0_out", - "NOC_NPS_VNOC_X2Y2", + "NOC_NPS_VNOC_X0Y14", "port2_in", - "NOC_NPS_VNOC_X2Y2", + "NOC_NPS_VNOC_X0Y14", "port0_out", - "NOC_NPS_VNOC_X2Y0", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS_VNOC_X2Y0", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS5555_X17Y1", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS5555_X17Y1", - "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", + "NOC_NPS_VNOC_X0Y10", "port0_out", - "NOC_NPS5555_X15Y0", + "NOC_NPS_VNOC_X0Y8", "port2_in", - "NOC_NPS5555_X15Y0", + "NOC_NPS_VNOC_X0Y8", "port0_out", - "NOC_NPS5555_X13Y0", + "NOC_NPS_VNOC_X0Y6", "port2_in", - "NOC_NPS5555_X13Y0", + "NOC_NPS_VNOC_X0Y6", "port0_out", - "NOC_NPS5555_X11Y0", + "NOC_NPS_VNOC_X0Y4", "port2_in", - "NOC_NPS5555_X11Y0", + "NOC_NPS_VNOC_X0Y4", "port0_out", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X0Y2", "port2_in", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X0Y2", "port0_out", - "NOC_NPS5555_X7Y0", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", "NOC_NPS5555_X7Y0", "port0_out", "NOC_NPS5555_X5Y0", @@ -17811,29 +18184,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 133 + }, { "PhyInstanceStart": "HBM_MC_X9Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -18185,10 +18537,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 133 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X9Y0", + "PhyInstanceEnd": "HBM_MC_X11Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -18209,313 +18582,321 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", "port3_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X4Y2", + "NOC_NPS6_X5Y2", "port5_out", - "NOC_NPS4_X4Y0", + "NOC_NPS4_X5Y0", "portSideA2_in", - "NOC_NPS4_X4Y0", + "NOC_NPS4_X5Y0", "portSideB3_out", - "HBM_MC_X9Y0", + "HBM_MC_X11Y0", "pc1_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 133 + "AchievedLatency": 135 }, { - "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceStart": "HBM_MC_X11Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X9Y0", + "HBM_MC_X11Y0", "pc1_port0_out", - "NOC_NPS4_X4Y0", + "NOC_NPS4_X5Y0", "portSideB3_in", - "NOC_NPS4_X4Y0", + "NOC_NPS4_X5Y0", "portSideA2_out", - "NOC_NPS6_X4Y2", + "NOC_NPS6_X5Y2", "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X6Y6", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X6Y6", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_out", - "NOC_NPS5555_X7Y0", + "NOC_NPS5555_X17Y0", "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", "NOC_NPS5555_X7Y0", "port0_out", "NOC_NPS5555_X5Y0", @@ -18536,29 +18917,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 133 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 135 + }, { "PhyInstanceStart": "HBM_MC_X11Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -18918,10 +19278,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 135 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X11Y0", + "PhyInstanceEnd": "HBM_MC_X7Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -18942,321 +19323,305 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", "port2_out", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X0Y0", "port0_in", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X0Y0", "port2_out", - "NOC_NPS5555_X11Y0", + "NOC_NPS_VNOC_X0Y2", "port0_in", - "NOC_NPS5555_X11Y0", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", "port3_out", - "NOC_NPS5555_X11Y1", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", "port1_in", - "NOC_NPS5555_X11Y1", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", "port2_out", - "NOC_NPS_VNOC_X1Y1", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB3_out", + "HBM_MC_X7Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X7Y0", + "pc1_port0_out", + "NOC_NPS4_X3Y0", + "portSideB3_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", "port2_in", - "NOC_NPS_VNOC_X1Y1", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y34", "port2_in", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y34", "port0_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y32", "port2_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y32", "port0_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y30", "port2_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y30", "port0_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y28", "port2_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y28", "port0_out", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X0Y26", "port2_in", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X0Y26", "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y5", "port1_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", "port2_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X0Y24", "port0_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port2_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port0_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port2_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port0_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port2_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port0_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port2_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port0_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X0Y14", "port2_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X0Y14", "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y3", "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X0Y1", "port1_in", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y10", "port0_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y8", "port2_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y8", "port0_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X0Y6", "port2_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X0Y6", "port0_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X0Y4", "port2_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X0Y4", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X0Y2", "port2_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X0Y2", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB3_out", - "HBM_MC_X11Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X11Y0", - "pc1_port0_out", - "NOC_NPS4_X5Y0", - "portSideB3_in", - "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port5_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", "NOC_NPS5555_X7Y0", "port0_out", "NOC_NPS5555_X5Y0", @@ -19277,29 +19642,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 131 + }, { "PhyInstanceStart": "HBM_MC_X7Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -19643,10 +19987,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 131 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X7Y0", + "PhyInstanceEnd": "HBM_MC_X13Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -19667,459 +20032,278 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", "port3_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X5Y2", "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X6Y2", "port0_in", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X6Y2", "port5_out", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X6Y0", "portSideA2_in", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X6Y0", "portSideB3_out", - "HBM_MC_X7Y0", + "HBM_MC_X13Y0", "pc1_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 131 + "AchievedLatency": 137 }, { - "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceStart": "HBM_MC_X13Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X7Y0", + "HBM_MC_X13Y0", "pc1_port0_out", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X6Y0", "portSideB3_in", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X6Y0", "portSideA2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X6Y2", "port5_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X6Y2", "port0_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port3_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_out", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_in", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X13Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB3_in", - "NOC_NPS4_X6Y0", - "portSideA2_out", - "NOC_NPS6_X6Y2", - "port5_in", - "NOC_NPS6_X6Y2", - "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", - "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", - "port3_out", - "NOC_NIDB_X2Y7", - "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", - "port0_out", - "NOC_NPS7575_X6Y4", - "port3_in", - "NOC_NPS7575_X6Y4", - "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", - "port0_in", - "NOC_NIDB_X2Y3", - "port1_out", - "NOC_NIDB_X2Y1", - "port1_in", - "NOC_NIDB_X2Y1", - "port0_out", - "NOC_NPS7575_X6Y0", - "port3_in", - "NOC_NPS7575_X6Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", + "NOC_NPS_VNOC_X2Y12", "port0_out", "NOC_NPS_VNOC_X2Y10", "port2_in", @@ -20188,200 +20372,200 @@ "NOC_NMU128_X0Y0", "resp_in" ], - "RequiredBW": 132, - "AchievedBW": 132, + "RequiredBW": 33, + "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 137 }, { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 4, - "CommType": "READ_REQ", + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", + "HBM_MC_X13Y0", + "pc1_port0_out", + "NOC_NPS4_X6Y0", + "portSideB3_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port2_out", - "NOC_NPS5555_X13Y0", - "port0_in", - "NOC_NPS5555_X13Y0", - "port2_out", - "NOC_NPS5555_X15Y0", - "port0_in", - "NOC_NPS5555_X15Y0", - "port2_out", - "NOC_NPS5555_X17Y0", - "port0_in", - "NOC_NPS5555_X17Y0", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", "port3_out", - "NOC_NPS5555_X17Y1", - "port1_in", - "NOC_NPS5555_X17Y1", - "port2_out", - "NOC_NPS_VNOC_X2Y0", + "NOC_NCRB_X1Y0", "port0_in", - "NOC_NPS_VNOC_X2Y0", - "port2_out", - "NOC_NPS_VNOC_X2Y2", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", "port0_in", - "NOC_NPS_VNOC_X2Y2", + "NOC_NPS_VNOC_X1Y37", "port2_out", - "NOC_NPS_VNOC_X2Y4", + "NOC_NPS_VNOC_X1Y35", "port0_in", - "NOC_NPS_VNOC_X2Y4", + "NOC_NPS_VNOC_X1Y35", "port2_out", - "NOC_NPS_VNOC_X2Y6", + "NOC_NPS_VNOC_X1Y33", "port0_in", - "NOC_NPS_VNOC_X2Y6", + "NOC_NPS_VNOC_X1Y33", "port2_out", - "NOC_NPS_VNOC_X2Y8", + "NOC_NPS_VNOC_X1Y31", "port0_in", - "NOC_NPS_VNOC_X2Y8", + "NOC_NPS_VNOC_X1Y31", "port2_out", - "NOC_NPS_VNOC_X2Y10", + "NOC_NPS_VNOC_X1Y29", "port0_in", - "NOC_NPS_VNOC_X2Y10", + "NOC_NPS_VNOC_X1Y29", "port2_out", - "NOC_NPS_VNOC_X2Y12", + "NOC_NPS_VNOC_X1Y27", "port0_in", - "NOC_NPS_VNOC_X2Y12", + "NOC_NPS_VNOC_X1Y27", "port2_out", - "NOC_NPS7575_X6Y0", - "port1_in", - "NOC_NPS7575_X6Y0", - "port3_out", - "NOC_NIDB_X2Y1", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", "port0_in", - "NOC_NIDB_X2Y1", + "NOC_NIDB_X1Y6", "port1_out", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X1Y4", "port1_in", - "NOC_NIDB_X2Y3", + "NOC_NIDB_X1Y4", "port0_out", - "NOC_NPS7575_X6Y2", - "port3_in", - "NOC_NPS7575_X6Y2", - "port1_out", - "NOC_NPS_VNOC_X2Y14", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", "port0_in", - "NOC_NPS_VNOC_X2Y14", + "NOC_NPS_VNOC_X1Y25", "port2_out", - "NOC_NPS_VNOC_X2Y16", + "NOC_NPS_VNOC_X1Y23", "port0_in", - "NOC_NPS_VNOC_X2Y16", + "NOC_NPS_VNOC_X1Y23", "port2_out", - "NOC_NPS_VNOC_X2Y18", + "NOC_NPS_VNOC_X1Y21", "port0_in", - "NOC_NPS_VNOC_X2Y18", + "NOC_NPS_VNOC_X1Y21", "port2_out", - "NOC_NPS_VNOC_X2Y20", + "NOC_NPS_VNOC_X1Y19", "port0_in", - "NOC_NPS_VNOC_X2Y20", + "NOC_NPS_VNOC_X1Y19", "port2_out", - "NOC_NPS_VNOC_X2Y22", + "NOC_NPS_VNOC_X1Y17", "port0_in", - "NOC_NPS_VNOC_X2Y22", + "NOC_NPS_VNOC_X1Y17", "port2_out", - "NOC_NPS_VNOC_X2Y24", + "NOC_NPS_VNOC_X1Y15", "port0_in", - "NOC_NPS_VNOC_X2Y24", + "NOC_NPS_VNOC_X1Y15", "port2_out", - "NOC_NPS7575_X6Y4", - "port1_in", - "NOC_NPS7575_X6Y4", - "port3_out", - "NOC_NIDB_X2Y5", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", "port0_in", - "NOC_NIDB_X2Y5", + "NOC_NIDB_X1Y2", "port1_out", - "NOC_NIDB_X2Y7", + "NOC_NIDB_X1Y0", "port1_in", - "NOC_NIDB_X2Y7", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS7575_X6Y6", - "port3_in", - "NOC_NPS7575_X6Y6", - "port1_out", - "NOC_NPS_VNOC_X2Y26", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NPS_VNOC_X2Y26", + "NOC_NPS_VNOC_X1Y13", "port2_out", - "NOC_NPS_VNOC_X2Y28", + "NOC_NPS_VNOC_X1Y11", "port0_in", - "NOC_NPS_VNOC_X2Y28", + "NOC_NPS_VNOC_X1Y11", "port2_out", - "NOC_NPS_VNOC_X2Y30", + "NOC_NPS_VNOC_X1Y9", "port0_in", - "NOC_NPS_VNOC_X2Y30", + "NOC_NPS_VNOC_X1Y9", "port2_out", - "NOC_NPS_VNOC_X2Y32", + "NOC_NPS_VNOC_X1Y7", "port0_in", - "NOC_NPS_VNOC_X2Y32", + "NOC_NPS_VNOC_X1Y7", "port2_out", - "NOC_NPS_VNOC_X2Y34", + "NOC_NPS_VNOC_X1Y5", "port0_in", - "NOC_NPS_VNOC_X2Y34", + "NOC_NPS_VNOC_X1Y5", "port2_out", - "NOC_NPS_VNOC_X2Y36", + "NOC_NPS_VNOC_X1Y3", "port0_in", - "NOC_NPS_VNOC_X2Y36", + "NOC_NPS_VNOC_X1Y3", "port2_out", - "NOC_NCRB_X2Y1", - "port1_in", - "NOC_NCRB_X2Y1", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", "port1_out", - "NOC_NPS5555_X7Y6", + "NOC_NPS5555_X11Y0", "port3_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", "port3_out", - "NOC_NPS6_X6Y2", - "port0_in", - "NOC_NPS6_X6Y2", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA2_in", - "NOC_NPS4_X6Y0", - "portSideB3_out", - "HBM_MC_X13Y0", - "pc1_port0_in" + "NOC_NMU128_X0Y0", + "resp_in" ], - "RequiredBW": 33, - "AchievedBW": 33, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, "AchievedLatency": 137 }, { "PhyInstanceStart": "NOC_NMU128_X0Y0", "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 5, - "CommType": "WRITE", + "VC": 4, + "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y0", "req_out", @@ -20556,173 +20740,354 @@ "HBM_MC_X13Y0", "pc1_port0_in" ], - "RequiredBW": 165, - "AchievedBW": 165, + "RequiredBW": 33, + "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 137 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X13Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB3_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X5Y0", "port2_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X7Y0", "port0_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", "port2_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X0Y0", "port0_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X0Y0", "port2_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y2", "port0_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y2", "port2_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y4", "port0_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y4", "port2_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y6", "port0_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y6", "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NPS_VNOC_X0Y8", "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y3", "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y3", "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", "port0_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X0Y14", "port2_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port0_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port2_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port0_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port2_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port0_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port2_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port0_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port2_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X0Y24", "port0_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X0Y24", "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y5", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y7", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y7", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", "port0_in", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X0Y26", "port2_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y28", "port0_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y28", "port2_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y30", "port0_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y30", "port2_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y32", "port0_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y32", "port2_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y34", "port0_in", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y34", "port2_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X0Y36", "port0_in", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X0Y36", "port2_out", - "NOC_NPS_VNOC_X1Y1", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", "port0_in", - "NOC_NPS_VNOC_X1Y1", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB2_out", + "HBM_MC_X7Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X7Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB2_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", "port2_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X6Y6", "port1_out", - "NOC_NPS5555_X11Y0", + "NOC_NPS6_X2Y2", "port3_in", - "NOC_NPS5555_X11Y0", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS5555_X9Y0", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS5555_X9Y0", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS5555_X7Y0", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", "NOC_NPS5555_X7Y0", "port0_out", "NOC_NPS5555_X5Y0", @@ -20743,29 +21108,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 131 + }, { "PhyInstanceStart": "HBM_MC_X7Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -21109,10 +21453,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 131 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X7Y0", + "PhyInstanceEnd": "HBM_MC_X13Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -21133,305 +21498,329 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", "port3_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X5Y2", "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X6Y2", "port0_in", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X6Y2", "port5_out", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X6Y0", "portSideA2_in", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X6Y0", "portSideB2_out", - "HBM_MC_X7Y0", + "HBM_MC_X13Y0", "pc0_port0_in" ], "RequiredBW": 165, "AchievedBW": 165, "RequiredLatency": 300, - "AchievedLatency": 131 + "AchievedLatency": 137 }, { - "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceStart": "HBM_MC_X13Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X7Y0", + "HBM_MC_X13Y0", "pc0_port0_out", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X6Y0", "portSideB2_in", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X6Y0", "portSideA2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X6Y2", "port5_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X6Y2", "port0_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port3_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_out", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_in", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port1_out", - "NOC_NPS5555_X7Y0", + "NOC_NPS5555_X17Y0", "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", "NOC_NPS5555_X7Y0", "port0_out", "NOC_NPS5555_X5Y0", @@ -21452,29 +21841,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 137 + }, { "PhyInstanceStart": "HBM_MC_X13Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -21842,10 +22210,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 137 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X13Y0", + "PhyInstanceEnd": "HBM_MC_X2Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -21866,329 +22255,281 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", "port2_out", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X0Y0", "port0_in", - "NOC_NPS5555_X9Y0", + "NOC_NPS_VNOC_X0Y0", "port2_out", - "NOC_NPS5555_X11Y0", + "NOC_NPS_VNOC_X0Y2", "port0_in", - "NOC_NPS5555_X11Y0", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", "port3_out", - "NOC_NPS5555_X11Y1", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", "port1_in", - "NOC_NPS5555_X11Y1", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", "port0_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB1_out", + "HBM_MC_X2Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X2Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB1_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y34", "port2_in", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y34", "port0_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y32", "port2_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y32", "port0_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y30", "port2_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y30", "port0_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y28", "port2_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y28", "port0_out", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X0Y26", "port2_in", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X0Y26", "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y5", "port1_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", "port2_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X0Y24", "port0_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port2_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port0_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port2_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port0_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port2_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port0_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port2_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port0_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X0Y14", "port2_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X0Y14", "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y3", "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X0Y1", "port1_in", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y10", "port0_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y8", "port2_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y8", "port0_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X0Y6", "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X0Y6", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X0Y4", "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB2_out", - "HBM_MC_X13Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X13Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB2_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X0Y4", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X0Y2", "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X0Y2", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X0Y0", "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NPS_VNOC_X0Y0", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X7Y1", "port2_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X7Y1", "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", "NOC_NPS5555_X7Y0", - "port2_in", + "port3_in", "NOC_NPS5555_X7Y0", "port0_out", "NOC_NPS5555_X5Y0", @@ -22209,29 +22550,8 @@ "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 125 + }, { "PhyInstanceStart": "HBM_MC_X2Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -22551,10 +22871,31 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/M00_AXI_nsu/bd_6ff4_M00_AXI_nsu_0_top_INST/NOC_NSU512_INST", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 5, + "WriteBW": 5, + "ReadAchievedBW": 5, + "WriteAchievedBW": 5, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NSU512_X1Y6", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -22575,355 +22916,202 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS5555_X9Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS5555_X9Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS5555_X11Y0", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port1_out", + "NOC_NPS_VNOC_X1Y2", + "port1_in", + "NOC_NPS_VNOC_X1Y2", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X1Y4", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X1Y4", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X1Y6", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X1Y6", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X1Y8", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X1Y8", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X1Y10", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X1Y10", "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NPS_VNOC_X1Y12", "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS_VNOC_X1Y12", + "port3_out", + "NOC_NSU512_X1Y6", + "req" + ], + "RequiredBW": 5, + "AchievedBW": 5, + "RequiredLatency": 300, + "AchievedLatency": 40 + }, + { + "PhyInstanceStart": "NOC_NSU512_X1Y6", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "NOC_NSU512_X1Y6", + "resp", + "NOC_NPS_VNOC_X1Y12", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS_VNOC_X1Y12", "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X1Y13", + "port1_in", + "NOC_NPS_VNOC_X1Y13", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X1Y11", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X1Y11", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X1Y9", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X1Y9", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X1Y7", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X1Y7", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X1Y5", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X1Y5", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X1Y3", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X1Y3", "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NPS_VNOC_X1Y1", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 1, + "AchievedBW": 1, + "RequiredLatency": 300, + "AchievedLatency": 40 + }, + { + "PhyInstanceStart": "NOC_NSU512_X1Y6", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "NOC_NSU512_X1Y6", + "resp", + "NOC_NPS_VNOC_X1Y12", "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS_VNOC_X1Y12", "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X1Y13", + "port1_in", + "NOC_NPS_VNOC_X1Y13", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X1Y11", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X1Y11", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X1Y9", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X1Y9", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X1Y7", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X1Y7", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X1Y5", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X1Y5", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X1Y3", "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS_VNOC_X1Y3", "port2_out", - "NOC_NPS6_X1Y2", + "NOC_NPS_VNOC_X1Y1", "port0_in", - "NOC_NPS6_X1Y2", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA2_in", - "NOC_NPS4_X1Y0", - "portSideB1_out", - "HBM_MC_X2Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X2Y0", - "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB1_in", - "NOC_NPS4_X1Y0", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port5_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", + "NOC_NPS5555_X11Y1", "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS5555_X9Y0", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS5555_X9Y0", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS5555_X7Y0", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS5555_X7Y0", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS5555_X5Y0", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS5555_X5Y0", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS5555_X3Y0", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS5555_X3Y0", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS5555_X1Y0", "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/M00_AXI_nsu", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 5, - "WriteBW": 5, - "ReadAchievedBW": 5, - "WriteAchievedBW": 5, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "NOC_NSU512_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "NOC_NSU512_X0Y0", - "resp", - "NOC_NPS_VNOC_X0Y0", - "port3_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", + "NOC_NPS5555_X1Y0", "port3_out", "NOC_NMU128_X0Y0", "resp_in" @@ -22931,11 +23119,11 @@ "RequiredBW": 5, "AchievedBW": 5, "RequiredLatency": 300, - "AchievedLatency": 22 + "AchievedLatency": 40 }, { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "NOC_NSU512_X0Y0", + "PhyInstanceEnd": "NOC_NSU512_X1Y6", "VC": 4, "CommType": "READ_REQ", "Connections": [ @@ -22956,26 +23144,83 @@ "NOC_NPS5555_X7Y0", "port0_in", "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", "port3_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X11Y1", "port1_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X11Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port1_out", + "NOC_NPS_VNOC_X1Y4", + "port1_in", + "NOC_NPS_VNOC_X1Y4", + "port2_out", + "NOC_NPS_VNOC_X1Y6", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X1Y6", + "port2_out", + "NOC_NPS_VNOC_X1Y8", + "port0_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", "port3_out", - "NOC_NSU512_X0Y0", + "NOC_NSU512_X1Y6", "req" ], "RequiredBW": 1, "AchievedBW": 1, "RequiredLatency": 300, - "AchievedLatency": 22 - }, + "AchievedLatency": 40 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_1/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "NOC_NSU512_X0Y0", + "PhyInstanceEnd": "DDRMC_X1Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -22984,96 +23229,83 @@ "NOC_NPS5555_X1Y0", "port3_in", "NOC_NPS5555_X1Y0", + "port0_out", + "NOC_NPS5555_X0Y1", + "port0_in", + "NOC_NPS5555_X0Y1", + "port1_out", + "NOC_NPS5555_X0Y0", + "port3_in", + "NOC_NPS5555_X0Y0", "port2_out", - "NOC_NPS5555_X3Y0", + "NOC_NPS5555_X2Y0", "port0_in", - "NOC_NPS5555_X3Y0", + "NOC_NPS5555_X2Y0", "port2_out", - "NOC_NPS5555_X5Y0", + "NOC_NPS5555_X4Y0", "port0_in", - "NOC_NPS5555_X5Y0", + "NOC_NPS5555_X4Y0", "port2_out", - "NOC_NPS5555_X7Y0", + "NOC_NPS5555_X6Y0", "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X6Y0", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS5555_X8Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port3_out", - "NOC_NSU512_X0Y0", - "req" + "NOC_NPS5555_X8Y0", + "port1_out", + "DDRMC_X1Y0", + "Port0_req" ], - "RequiredBW": 5, - "AchievedBW": 5, + "RequiredBW": 850, + "AchievedBW": 850, "RequiredLatency": 300, - "AchievedLatency": 22 + "AchievedLatency": 24 }, { - "PhyInstanceStart": "NOC_NSU512_X0Y0", + "PhyInstanceStart": "DDRMC_X1Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "NOC_NSU512_X0Y0", - "resp", - "NOC_NPS_VNOC_X0Y0", - "port3_in", - "NOC_NPS_VNOC_X0Y0", + "DDRMC_X1Y0", + "Port0_resp", + "NOC_NPS5555_X8Y0", + "port1_in", + "NOC_NPS5555_X8Y0", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X6Y0", "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", + "NOC_NPS5555_X6Y0", "port0_out", - "NOC_NPS5555_X5Y0", + "NOC_NPS5555_X4Y0", "port2_in", - "NOC_NPS5555_X5Y0", + "NOC_NPS5555_X4Y0", "port0_out", - "NOC_NPS5555_X3Y0", + "NOC_NPS5555_X2Y0", "port2_in", - "NOC_NPS5555_X3Y0", + "NOC_NPS5555_X2Y0", "port0_out", - "NOC_NPS5555_X1Y0", + "NOC_NPS5555_X0Y0", "port2_in", + "NOC_NPS5555_X0Y0", + "port3_out", + "NOC_NPS5555_X0Y1", + "port1_in", + "NOC_NPS5555_X0Y1", + "port0_out", + "NOC_NPS5555_X1Y0", + "port0_in", "NOC_NPS5555_X1Y0", "port3_out", "NOC_NMU128_X0Y0", "resp_in" ], - "RequiredBW": 1, - "AchievedBW": 1, + "RequiredBW": 50, + "AchievedBW": 50, "RequiredLatency": 300, - "AchievedLatency": 22 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 24 + }, { "PhyInstanceStart": "DDRMC_X1Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -23161,10 +23393,31 @@ "AchievedBW": 50, "RequiredLatency": 300, "AchievedLatency": 24 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "DDRMC_X1Y0", + "PhyInstanceEnd": "DDRMC_X0Y0", "VC": 5, "CommType": "WRITE", "Connections": [ @@ -23185,49 +23438,25 @@ "NOC_NPS5555_X2Y0", "port0_in", "NOC_NPS5555_X2Y0", - "port2_out", - "NOC_NPS5555_X4Y0", - "port0_in", - "NOC_NPS5555_X4Y0", - "port2_out", - "NOC_NPS5555_X6Y0", - "port0_in", - "NOC_NPS5555_X6Y0", - "port2_out", - "NOC_NPS5555_X8Y0", - "port0_in", - "NOC_NPS5555_X8Y0", - "port1_out", - "DDRMC_X1Y0", + "port3_out", + "DDRMC_X0Y0", "Port0_req" ], "RequiredBW": 850, "AchievedBW": 850, "RequiredLatency": 300, - "AchievedLatency": 24 + "AchievedLatency": 18 }, { - "PhyInstanceStart": "DDRMC_X1Y0", + "PhyInstanceStart": "DDRMC_X0Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "DDRMC_X1Y0", + "DDRMC_X0Y0", "Port0_resp", - "NOC_NPS5555_X8Y0", - "port1_in", - "NOC_NPS5555_X8Y0", - "port0_out", - "NOC_NPS5555_X6Y0", - "port2_in", - "NOC_NPS5555_X6Y0", - "port0_out", - "NOC_NPS5555_X4Y0", - "port2_in", - "NOC_NPS5555_X4Y0", - "port0_out", "NOC_NPS5555_X2Y0", - "port2_in", + "port3_in", "NOC_NPS5555_X2Y0", "port0_out", "NOC_NPS5555_X0Y0", @@ -23248,29 +23477,8 @@ "RequiredBW": 50, "AchievedBW": 50, "RequiredLatency": 300, - "AchievedLatency": 24 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 18 + }, { "PhyInstanceStart": "DDRMC_X0Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y0", @@ -23334,78 +23542,14 @@ "AchievedBW": 50, "RequiredLatency": 300, "AchievedLatency": 18 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port0_out", - "NOC_NPS5555_X0Y1", - "port0_in", - "NOC_NPS5555_X0Y1", - "port1_out", - "NOC_NPS5555_X0Y0", - "port3_in", - "NOC_NPS5555_X0Y0", - "port2_out", - "NOC_NPS5555_X2Y0", - "port0_in", - "NOC_NPS5555_X2Y0", - "port3_out", - "DDRMC_X0Y0", - "Port0_req" - ], - "RequiredBW": 850, - "AchievedBW": 850, - "RequiredLatency": 300, - "AchievedLatency": 18 - }, - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "DDRMC_X0Y0", - "Port0_resp", - "NOC_NPS5555_X2Y0", - "port3_in", - "NOC_NPS5555_X2Y0", - "port0_out", - "NOC_NPS5555_X0Y0", - "port2_in", - "NOC_NPS5555_X0Y0", - "port3_out", - "NOC_NPS5555_X0Y1", - "port1_in", - "NOC_NPS5555_X0Y1", - "port0_out", - "NOC_NPS5555_X1Y0", - "port0_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 18 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", "ToLocked": false, "Port": "PORT3", "ReadTC": "BE", @@ -23421,388 +23565,28 @@ "PathLocked": true, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 1, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X10Y0", - "pc1_port1_out", - "NOC_NPS4_X5Y1", - "portSideB1_in", - "NOC_NPS4_X5Y1", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port4_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", "port2_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X3Y1", "port0_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X3Y1", "port2_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X5Y1", "port0_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X5Y1", "port2_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X7Y2", "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port4_out", - "NOC_NPS4_X5Y1", - "portSideA1_in", - "NOC_NPS4_X5Y1", - "portSideB1_out", - "HBM_MC_X10Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", + "NOC_NPS5555_X7Y2", "port2_out", "NOC_NPS5555_X9Y2", "port0_in", @@ -24139,178 +23923,157 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { "PhyInstanceStart": "HBM_MC_X10Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ "HBM_MC_X10Y0", - "pc0_port1_out", + "pc1_port1_out", "NOC_NPS4_X5Y1", - "portSideB0_in", + "portSideB1_in", "NOC_NPS4_X5Y1", - "portSideA1_out", - "NOC_NPS6_X5Y1", + "portSideA2_out", + "NOC_NPS6_X5Y2", "port4_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", "port3_out", - "NOC_NPS5555_X11Y2", + "NOC_NPS5555_X17Y2", "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", "NOC_NPS5555_X11Y2", "port0_out", "NOC_NPS5555_X9Y2", @@ -24344,7 +24107,7 @@ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 4, + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -24372,155 +24135,176 @@ "NOC_NPS5555_X11Y2", "port0_in", "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port3_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X5Y3", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port4_out", "NOC_NPS4_X5Y1", - "portSideA1_in", + "portSideA2_in", "NOC_NPS4_X5Y1", - "portSideB0_out", + "portSideB1_out", "HBM_MC_X10Y0", - "pc0_port1_in" + "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 135 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X10Y0", @@ -24880,181 +24664,176 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceStart": "HBM_MC_X10Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X5Y0", + "HBM_MC_X10Y0", "pc0_port1_out", - "NOC_NPS4_X2Y1", - "portSideB2_in", - "NOC_NPS4_X2Y1", + "NOC_NPS4_X5Y1", + "portSideB0_in", + "NOC_NPS4_X5Y1", "portSideA2_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X5Y2", "port4_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_out", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_in", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port3_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS5555_X17Y2", "port1_in", - "NOC_NPS5555_X7Y2", + "NOC_NPS5555_X17Y2", "port0_out", - "NOC_NPS5555_X5Y1", + "NOC_NPS5555_X15Y2", "port2_in", - "NOC_NPS5555_X5Y1", + "NOC_NPS5555_X15Y2", "port0_out", - "NOC_NPS5555_X3Y1", + "NOC_NPS5555_X13Y2", "port2_in", - "NOC_NPS5555_X3Y1", + "NOC_NPS5555_X13Y2", "port0_out", - "NOC_NPS5555_X1Y1", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", "port2_in", "NOC_NPS5555_X1Y1", "port1_out", @@ -25064,12 +24843,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 127 + "AchievedLatency": 135 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -25089,147 +24868,184 @@ "NOC_NPS5555_X7Y2", "port0_in", "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port3_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X5Y2", "port4_out", - "NOC_NPS4_X2Y1", + "NOC_NPS4_X5Y1", "portSideA2_in", - "NOC_NPS4_X2Y1", - "portSideB2_out", - "HBM_MC_X5Y0", + "NOC_NPS4_X5Y1", + "portSideB0_out", + "HBM_MC_X10Y0", "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 127 - }, + "AchievedLatency": 135 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X5Y0", @@ -25557,198 +25373,149 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceStart": "HBM_MC_X5Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X15Y0", - "pc1_port1_out", - "NOC_NPS4_X7Y1", - "portSideB3_in", - "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", + "HBM_MC_X5Y0", + "pc0_port1_out", + "NOC_NPS4_X2Y1", + "portSideB2_in", + "NOC_NPS4_X2Y1", + "portSideA2_out", + "NOC_NPS6_X2Y2", "port4_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS5555_X8Y4", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X0Y32", "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X0Y32", "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X0Y28", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X4Y4", "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NPS7575_X4Y4", "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", "port1_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X4Y2", "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y3", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y1", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y10", "port0_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", "NOC_NPS5555_X7Y2", "port0_out", "NOC_NPS5555_X5Y1", @@ -25769,12 +25536,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 141 + "AchievedLatency": 127 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -25794,175 +25561,168 @@ "NOC_NPS5555_X7Y2", "port0_in", "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", "port2_out", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y0", "port0_in", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y0", "port2_out", - "NOC_NPS5555_X11Y2", + "NOC_NPS_VNOC_X0Y2", "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS_VNOC_X0Y2", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS_VNOC_X0Y4", "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", "port1_in", - "NOC_NPS7575_X5Y3", + "NOC_NPS7575_X0Y0", "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y1", "port0_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y1", "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X0Y3", "port1_in", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X0Y3", "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", "port1_in", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X4Y4", "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X0Y5", "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X4Y6", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X0Y28", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X0Y30", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X0Y32", "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", "port1_in", - "NOC_NPS5555_X8Y4", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", "port2_out", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X1Y2", "port0_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", "port4_out", - "NOC_NPS4_X7Y1", - "portSideA1_in", - "NOC_NPS4_X7Y1", - "portSideB3_out", - "HBM_MC_X15Y0", - "pc1_port1_in" + "NOC_NPS4_X2Y1", + "portSideA2_in", + "NOC_NPS4_X2Y1", + "portSideB2_out", + "HBM_MC_X5Y0", + "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 141 - }, + "AchievedLatency": 127 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X15Y0", @@ -25994,157 +25754,157 @@ "NOC_NPS5555_X11Y2", "port0_in", "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port3_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X5Y3", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X6Y2", "port0_in", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X6Y2", "port3_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS5555_X8Y6", "port1_in", - "NOC_NPS5555_X8Y4", + "NOC_NPS5555_X8Y6", "port2_out", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X7Y2", "port0_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X7Y2", "port4_out", "NOC_NPS4_X7Y1", - "portSideA1_in", + "portSideA2_in", "NOC_NPS4_X7Y1", "portSideB3_out", "HBM_MC_X15Y0", @@ -26166,157 +25926,157 @@ "NOC_NPS4_X7Y1", "portSideB3_in", "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", + "portSideA2_out", + "NOC_NPS6_X7Y2", "port4_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X7Y2", "port0_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS5555_X8Y6", "port2_in", - "NOC_NPS5555_X8Y4", + "NOC_NPS5555_X8Y6", "port1_out", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X6Y2", "port3_in", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X6Y2", "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", "port3_out", - "NOC_NPS5555_X11Y2", + "NOC_NPS5555_X17Y2", "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", "NOC_NPS5555_X11Y2", "port0_out", "NOC_NPS5555_X9Y2", @@ -26346,166 +26106,177 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceStart": "HBM_MC_X15Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X0Y0", + "HBM_MC_X15Y0", "pc1_port1_out", - "NOC_NPS4_X0Y1", - "portSideB1_in", - "NOC_NPS4_X0Y1", + "NOC_NPS4_X7Y1", + "portSideB3_in", + "NOC_NPS4_X7Y1", "portSideA2_out", - "NOC_NPS6_X0Y2", + "NOC_NPS6_X7Y2", "port4_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", "port3_out", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_in", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port3_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS5555_X17Y2", "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", "NOC_NPS5555_X7Y2", "port0_out", "NOC_NPS5555_X5Y1", @@ -26526,12 +26297,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 125 + "AchievedLatency": 141 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -26551,143 +26322,196 @@ "NOC_NPS5555_X7Y2", "port0_in", "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port3_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NCRB_X2Y1", "port1_out", - "NOC_NPS6_X0Y2", + "NOC_NPS5555_X7Y6", "port3_in", - "NOC_NPS6_X0Y2", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", "port4_out", - "NOC_NPS4_X0Y1", + "NOC_NPS4_X7Y1", "portSideA2_in", - "NOC_NPS4_X0Y1", - "portSideB1_out", - "HBM_MC_X0Y0", + "NOC_NPS4_X7Y1", + "portSideB3_out", + "HBM_MC_X15Y0", "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 125 - }, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X0Y0", @@ -27007,417 +26831,353 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceStart": "HBM_MC_X0Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X15Y0", - "pc0_port1_out", - "NOC_NPS4_X7Y1", - "portSideB2_in", - "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", + "HBM_MC_X0Y0", + "pc1_port1_out", + "NOC_NPS4_X0Y1", + "portSideB1_in", + "NOC_NPS4_X0Y1", + "portSideA2_out", + "NOC_NPS6_X0Y2", "port4_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS_VNOC_X0Y34", "port2_in", - "NOC_NPS5555_X8Y4", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NPS7575_X4Y4", "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X0Y22", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NPS7575_X0Y0", "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X3Y1", "port2_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X5Y1", "port0_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X5Y1", "port2_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X7Y2", "port0_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", "port2_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y0", "port0_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y0", "port2_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y2", "port0_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y2", "port2_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y4", "port0_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y4", "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NPS_VNOC_X0Y6", "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y3", "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y3", "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", "port0_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X0Y14", "port2_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port0_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port2_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port0_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port2_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port0_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port2_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port0_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port2_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X0Y24", "port0_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X0Y24", "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y5", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y7", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y7", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", "port0_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y26", "port2_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y28", "port0_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y28", "port2_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y30", "port0_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y30", "port2_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y32", "port0_in", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y32", "port2_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X0Y34", "port0_in", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X0Y34", "port2_out", - "NOC_NPS_VNOC_X1Y1", + "NOC_NPS_VNOC_X0Y36", "port0_in", - "NOC_NPS_VNOC_X1Y1", + "NOC_NPS_VNOC_X0Y36", "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", + "NOC_NCRB_X0Y1", "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", + "NOC_NCRB_X0Y1", "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port4_out", + "NOC_NPS4_X0Y1", + "portSideA2_in", + "NOC_NPS4_X0Y1", + "portSideB1_out", + "HBM_MC_X0Y0", + "pc1_port1_in" ], - "RequiredBW": 132, - "AchievedBW": 132, + "RequiredBW": 33, + "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 141 - }, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port4_out", - "NOC_NPS4_X7Y1", - "portSideA1_in", - "NOC_NPS4_X7Y1", - "portSideB2_out", - "HBM_MC_X15Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 1, - "CommType": "WRITE", + "VC": 1, + "CommType": "WRITE", "Connections": [ "NOC_NMU128_X0Y1", "req_out", @@ -27796,166 +27556,177 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceStart": "HBM_MC_X15Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X1Y0", + "HBM_MC_X15Y0", "pc0_port1_out", - "NOC_NPS4_X0Y1", + "NOC_NPS4_X7Y1", "portSideB2_in", - "NOC_NPS4_X0Y1", + "NOC_NPS4_X7Y1", "portSideA2_out", - "NOC_NPS6_X0Y2", + "NOC_NPS6_X7Y2", "port4_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", "port3_out", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_in", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port3_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS5555_X17Y2", "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", "NOC_NPS5555_X7Y2", "port0_out", "NOC_NPS5555_X5Y1", @@ -27976,12 +27747,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 125 + "AchievedLatency": 141 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -28001,143 +27772,196 @@ "NOC_NPS5555_X7Y2", "port0_in", "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port3_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NCRB_X2Y1", "port1_out", - "NOC_NPS6_X0Y2", + "NOC_NPS5555_X7Y6", "port3_in", - "NOC_NPS6_X0Y2", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", "port4_out", - "NOC_NPS4_X0Y1", + "NOC_NPS4_X7Y1", "portSideA2_in", - "NOC_NPS4_X0Y1", + "NOC_NPS4_X7Y1", "portSideB2_out", - "HBM_MC_X1Y0", + "HBM_MC_X15Y0", "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 125 - }, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X1Y0", @@ -28457,50 +28281,25 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceStart": "HBM_MC_X1Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X5Y0", - "pc1_port1_out", - "NOC_NPS4_X2Y1", - "portSideB3_in", - "NOC_NPS4_X2Y1", + "HBM_MC_X1Y0", + "pc0_port1_out", + "NOC_NPS4_X0Y1", + "portSideB2_in", + "NOC_NPS4_X0Y1", "portSideA2_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X0Y2", "port4_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", + "NOC_NPS6_X0Y2", + "port3_out", "NOC_NPS5555_X5Y6", - "port2_in", + "port1_in", "NOC_NPS5555_X5Y6", "port3_out", "NOC_NCRB_X0Y0", @@ -28641,12 +28440,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 127 + "AchievedLatency": 125 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -28786,27 +28585,44 @@ "NOC_NPS5555_X5Y6", "port3_in", "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", "port4_out", - "NOC_NPS4_X2Y1", + "NOC_NPS4_X0Y1", "portSideA2_in", - "NOC_NPS4_X2Y1", - "portSideB3_out", - "HBM_MC_X5Y0", - "pc1_port1_in" + "NOC_NPS4_X0Y1", + "portSideB2_out", + "HBM_MC_X1Y0", + "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 127 - }, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X5Y0", @@ -29134,46 +28950,29 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceStart": "HBM_MC_X5Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X1Y0", + "HBM_MC_X5Y0", "pc1_port1_out", - "NOC_NPS4_X0Y1", + "NOC_NPS4_X2Y1", "portSideB3_in", - "NOC_NPS4_X0Y1", + "NOC_NPS4_X2Y1", "portSideA2_out", - "NOC_NPS6_X0Y2", + "NOC_NPS6_X2Y2", "port4_in", - "NOC_NPS6_X0Y2", - "port3_out", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", "NOC_NPS5555_X5Y6", - "port1_in", + "port2_in", "NOC_NPS5555_X5Y6", "port3_out", "NOC_NCRB_X0Y0", @@ -29314,12 +29113,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 125 + "AchievedLatency": 127 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -29459,23 +29258,48 @@ "NOC_NPS5555_X5Y6", "port3_in", "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", "port4_out", - "NOC_NPS4_X0Y1", + "NOC_NPS4_X2Y1", "portSideA2_in", - "NOC_NPS4_X0Y1", + "NOC_NPS4_X2Y1", "portSideB3_out", - "HBM_MC_X1Y0", + "HBM_MC_X5Y0", "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 125 - }, + "AchievedLatency": 127 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X1Y0", @@ -29795,58 +29619,25 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceStart": "HBM_MC_X1Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X6Y0", - "pc0_port1_out", - "NOC_NPS4_X3Y1", - "portSideB0_in", - "NOC_NPS4_X3Y1", + "HBM_MC_X1Y0", + "pc1_port1_out", + "NOC_NPS4_X0Y1", + "portSideB3_in", + "NOC_NPS4_X0Y1", "portSideA2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X0Y2", "port4_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", + "NOC_NPS6_X0Y2", + "port3_out", "NOC_NPS5555_X5Y6", - "port2_in", + "port1_in", "NOC_NPS5555_X5Y6", "port3_out", "NOC_NCRB_X0Y0", @@ -29987,12 +29778,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 131 + "AchievedLatency": 125 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -30132,35 +29923,44 @@ "NOC_NPS5555_X5Y6", "port3_in", "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", "port4_out", - "NOC_NPS4_X3Y1", + "NOC_NPS4_X0Y1", "portSideA2_in", - "NOC_NPS4_X3Y1", - "portSideB0_out", - "HBM_MC_X6Y0", - "pc0_port1_in" + "NOC_NPS4_X0Y1", + "portSideB3_out", + "HBM_MC_X1Y0", + "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 131 - }, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X6Y0", @@ -30496,198 +30296,157 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 129 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceStart": "HBM_MC_X6Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X14Y0", - "pc1_port1_out", - "NOC_NPS4_X7Y1", - "portSideB1_in", - "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", + "HBM_MC_X6Y0", + "pc0_port1_out", + "NOC_NPS4_X3Y1", + "portSideB0_in", + "NOC_NPS4_X3Y1", + "portSideA2_out", + "NOC_NPS6_X3Y2", "port4_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X3Y2", "port0_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS5555_X6Y6", "port2_in", - "NOC_NPS5555_X8Y4", + "NOC_NPS5555_X6Y6", "port1_out", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X2Y2", "port3_in", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X1Y2", "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X1Y2", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X0Y32", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X4Y4", "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NPS7575_X4Y4", "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", "port1_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X4Y2", "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y3", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y1", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y10", "port0_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", "NOC_NPS5555_X7Y2", "port0_out", "NOC_NPS5555_X5Y1", @@ -30708,12 +30467,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 141 + "AchievedLatency": 131 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -30793,115 +30552,116 @@ "NOC_NPS_VNOC_X1Y15", "port2_in", "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NPS_VNOC_X1Y14", "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", "port1_in", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X5Y4", "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y5", "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y6", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y28", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y30", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y32", "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", "port1_in", - "NOC_NPS5555_X8Y4", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", "port2_out", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X3Y2", "port0_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X3Y2", "port4_out", - "NOC_NPS4_X7Y1", - "portSideA1_in", - "NOC_NPS4_X7Y1", - "portSideB1_out", - "HBM_MC_X14Y0", - "pc1_port1_in" + "NOC_NPS4_X3Y1", + "portSideA2_in", + "NOC_NPS4_X3Y1", + "portSideB0_out", + "HBM_MC_X6Y0", + "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 141 - }, + "AchievedLatency": 131 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X14Y0", @@ -31285,166 +31045,177 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceStart": "HBM_MC_X14Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X0Y0", - "pc0_port1_out", - "NOC_NPS4_X0Y1", - "portSideB0_in", - "NOC_NPS4_X0Y1", - "portSideA2_out", - "NOC_NPS6_X0Y2", + "HBM_MC_X14Y0", + "pc1_port1_out", + "NOC_NPS4_X7Y1", + "portSideB1_in", + "NOC_NPS4_X7Y1", + "portSideA1_out", + "NOC_NPS6_X7Y1", "port4_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS6_X7Y1", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS5555_X8Y4", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS5555_X7Y4", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS5555_X6Y4", "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS5555_X6Y4", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NCRB_X1Y0", "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NCRB_X1Y0", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X5Y7", "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X1Y6", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X1Y6", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X1Y4", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X1Y4", "port0_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", "port3_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X5Y3", "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS5555_X9Y2", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS5555_X9Y2", "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", "NOC_NPS5555_X7Y2", - "port1_in", + "port2_in", "NOC_NPS5555_X7Y2", "port0_out", "NOC_NPS5555_X5Y1", @@ -31465,12 +31236,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 125 + "AchievedLatency": 141 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -31490,143 +31261,196 @@ "NOC_NPS5555_X7Y2", "port0_in", "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS5555_X9Y2", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS5555_X9Y2", "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NPS5555_X11Y2", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NPS5555_X11Y2", "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS5555_X11Y1", "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS5555_X11Y1", "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X1Y4", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X1Y6", "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS6_X3Y1", "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS6_X5Y1", "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS6_X7Y1", "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", + "NOC_NPS6_X7Y1", "port4_out", - "NOC_NPS4_X0Y1", - "portSideA2_in", - "NOC_NPS4_X0Y1", - "portSideB0_out", - "HBM_MC_X0Y0", - "pc0_port1_in" + "NOC_NPS4_X7Y1", + "portSideA1_in", + "NOC_NPS4_X7Y1", + "portSideB1_out", + "HBM_MC_X14Y0", + "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 125 - }, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X0Y0", @@ -31946,62 +31770,25 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceStart": "HBM_MC_X0Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X8Y0", - "pc1_port1_out", - "NOC_NPS4_X4Y1", - "portSideB1_in", - "NOC_NPS4_X4Y1", + "HBM_MC_X0Y0", + "pc0_port1_out", + "NOC_NPS4_X0Y1", + "portSideB0_in", + "NOC_NPS4_X0Y1", "portSideA2_out", - "NOC_NPS6_X4Y2", + "NOC_NPS6_X0Y2", "port4_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", + "NOC_NPS6_X0Y2", + "port3_out", "NOC_NPS5555_X5Y6", - "port2_in", + "port1_in", "NOC_NPS5555_X5Y6", "port3_out", "NOC_NCRB_X0Y0", @@ -32142,12 +31929,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 133 + "AchievedLatency": 125 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -32287,39 +32074,44 @@ "NOC_NPS5555_X5Y6", "port3_in", "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", "port4_out", - "NOC_NPS4_X4Y1", + "NOC_NPS4_X0Y1", "portSideA2_in", - "NOC_NPS4_X4Y1", - "portSideB1_out", - "HBM_MC_X8Y0", - "pc1_port1_in" + "NOC_NPS4_X0Y1", + "portSideB0_out", + "HBM_MC_X0Y0", + "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 133 - }, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X8Y0", @@ -32671,190 +32463,161 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 133 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceStart": "HBM_MC_X8Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X12Y0", - "pc0_port1_out", - "NOC_NPS4_X6Y1", - "portSideB0_in", - "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", + "HBM_MC_X8Y0", + "pc1_port1_out", + "NOC_NPS4_X4Y1", + "portSideB1_in", + "NOC_NPS4_X4Y1", + "portSideA2_out", + "NOC_NPS6_X4Y2", "port4_in", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X4Y2", "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X3Y2", "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X3Y2", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X6Y6", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X6Y6", "port1_out", - "NOC_NPS6_X4Y1", + "NOC_NPS6_X2Y2", "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X1Y2", "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X1Y2", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X5Y6", "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NCRB_X0Y0", "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", "port1_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X4Y6", "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y5", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS7575_X5Y1", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", "port1_in", - "NOC_NPS7575_X5Y1", + "NOC_NPS7575_X4Y2", "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", "port1_in", - "NOC_NPS5555_X11Y2", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS5555_X9Y2", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", "NOC_NPS5555_X7Y2", "port0_out", "NOC_NPS5555_X5Y1", @@ -32875,12 +32638,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 137 + "AchievedLatency": 133 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -32964,103 +32727,116 @@ "NOC_NPS_VNOC_X1Y17", "port2_in", "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NPS_VNOC_X1Y16", "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", "port1_in", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X5Y4", "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y5", "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y6", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y28", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X3Y2", "port0_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X3Y2", "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X4Y2", "port0_in", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X4Y2", "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB0_out", - "HBM_MC_X12Y0", - "pc0_port1_in" + "NOC_NPS4_X4Y1", + "portSideA2_in", + "NOC_NPS4_X4Y1", + "portSideB1_out", + "HBM_MC_X8Y0", + "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 137 - }, + "AchievedLatency": 133 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X12Y0", @@ -33092,149 +32868,149 @@ "NOC_NPS5555_X11Y2", "port0_in", "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port3_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X5Y3", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X6Y2", "port0_in", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X6Y2", "port4_out", "NOC_NPS4_X6Y1", - "portSideA1_in", + "portSideA2_in", "NOC_NPS4_X6Y1", "portSideB0_out", "HBM_MC_X12Y0", @@ -33256,86 +33032,270 @@ "NOC_NPS4_X6Y1", "portSideB0_in", "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", + "portSideA2_out", + "NOC_NPS6_X6Y2", "port4_in", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X6Y2", "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X12Y0", + "pc0_port1_out", + "NOC_NPS4_X6Y1", + "portSideB0_in", + "NOC_NPS4_X6Y1", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port4_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", "port2_out", "NOC_NPS_VNOC_X1Y19", "port0_in", @@ -33424,209 +33384,221 @@ "NOC_NMU128_X0Y1", "resp_in" ], - "RequiredBW": 33, - "AchievedBW": 33, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 0, + "CommType": "READ_REQ", "Connections": [ - "HBM_MC_X6Y0", - "pc1_port1_out", - "NOC_NPS4_X3Y1", - "portSideB1_in", - "NOC_NPS4_X3Y1", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port4_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", + "NOC_NPS5555_X11Y1", "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X1Y3", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X1Y5", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X1Y5", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X1Y7", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X1Y7", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X1Y9", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X1Y11", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X1Y13", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X1Y13", "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X1Y0", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X1Y17", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X1Y17", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X1Y19", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X1Y19", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X1Y21", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X1Y21", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X1Y23", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X1Y23", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X1Y25", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X1Y25", "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X1Y4", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X1Y6", "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X1Y27", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X1Y29", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X1Y29", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X1Y31", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X1Y31", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X1Y33", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X1Y33", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X1Y35", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X1Y35", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X1Y37", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X1Y37", "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", "port3_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA1_in", + "NOC_NPS4_X6Y1", + "portSideB0_out", + "HBM_MC_X12Y0", + "pc0_port1_in" ], - "RequiredBW": 132, - "AchievedBW": 132, + "RequiredBW": 33, + "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 131 - }, + "AchievedLatency": 137 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 4, - "CommType": "READ_REQ", + "VC": 1, + "CommType": "WRITE", "Connections": [ "NOC_NMU128_X0Y1", "req_out", @@ -33645,184 +33617,12 @@ "NOC_NPS5555_X7Y2", "port0_in", "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS5555_X9Y2", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS5555_X9Y2", "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port4_out", - "NOC_NPS4_X3Y1", - "portSideA2_in", - "NOC_NPS4_X3Y1", - "portSideB1_out", - "HBM_MC_X6Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", + "NOC_NPS5555_X11Y2", "port0_in", "NOC_NPS5555_X11Y2", "port1_out", @@ -34129,190 +33929,157 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 129 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceStart": "HBM_MC_X6Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X12Y0", + "HBM_MC_X6Y0", "pc1_port1_out", - "NOC_NPS4_X6Y1", + "NOC_NPS4_X3Y1", "portSideB1_in", - "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", + "NOC_NPS4_X3Y1", + "portSideA2_out", + "NOC_NPS6_X3Y2", "port4_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X3Y2", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X6Y6", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X6Y6", "port1_out", - "NOC_NPS6_X4Y1", + "NOC_NPS6_X2Y2", "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X1Y2", "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X1Y2", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X5Y6", "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NCRB_X0Y0", "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", "port1_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X4Y6", "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y5", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS7575_X5Y1", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", "port1_in", - "NOC_NPS7575_X5Y1", + "NOC_NPS7575_X4Y2", "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", "port1_in", - "NOC_NPS5555_X11Y2", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS5555_X9Y2", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", "NOC_NPS5555_X7Y2", "port0_out", "NOC_NPS5555_X5Y1", @@ -34333,12 +34100,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 137 + "AchievedLatency": 131 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -34418,107 +34185,116 @@ "NOC_NPS_VNOC_X1Y15", "port2_in", "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS_VNOC_X1Y14", "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y14", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y16", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", "port0_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", "port3_out", - "NOC_NPS5555_X7Y4", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y28", "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", "port0_in", - "NOC_NPS6_X6Y1", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", + "NOC_NPS4_X3Y1", + "portSideA2_in", + "NOC_NPS4_X3Y1", "portSideB1_out", - "HBM_MC_X12Y0", + "HBM_MC_X6Y0", "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 137 - }, + "AchievedLatency": 131 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X12Y0", @@ -34550,164 +34326,348 @@ "NOC_NPS5555_X11Y2", "port0_in", "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port3_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA2_in", + "NOC_NPS4_X6Y1", + "portSideB1_out", + "HBM_MC_X12Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X12Y0", + "pc1_port1_out", + "NOC_NPS4_X6Y1", + "portSideB1_in", + "NOC_NPS4_X6Y1", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port4_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", "port3_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X17Y2", "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB1_out", - "HBM_MC_X12Y0", - "pc1_port1_in" + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" ], - "RequiredBW": 165, - "AchievedBW": 165, + "RequiredBW": 33, + "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 137 }, { "PhyInstanceStart": "HBM_MC_X12Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", + "VC": 2, + "CommType": "READ", "Connections": [ "HBM_MC_X12Y0", "pc1_port1_out", @@ -34882,384 +34842,216 @@ "NOC_NMU128_X0Y1", "resp_in" ], - "RequiredBW": 33, - "AchievedBW": 33, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X8Y0", - "pc0_port1_out", - "NOC_NPS4_X4Y1", - "portSideB0_in", - "NOC_NPS4_X4Y1", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port4_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", + "NOC_NPS5555_X11Y1", "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X1Y3", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X1Y5", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X1Y5", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X1Y7", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X1Y7", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X1Y9", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X1Y11", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X1Y13", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X1Y13", "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X1Y0", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X1Y17", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X1Y17", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X1Y19", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X1Y19", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X1Y21", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X1Y21", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X1Y23", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X1Y23", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X1Y25", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X1Y25", "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X1Y4", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NIDB_X1Y6", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X1Y27", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X1Y29", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X1Y29", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS_VNOC_X1Y31", "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", + "NOC_NPS_VNOC_X1Y31", "port0_out", - "NOC_NPS5555_X5Y1", + "NOC_NPS_VNOC_X1Y33", "port2_in", - "NOC_NPS5555_X5Y1", + "NOC_NPS_VNOC_X1Y33", "port0_out", - "NOC_NPS5555_X3Y1", + "NOC_NPS_VNOC_X1Y35", "port2_in", - "NOC_NPS5555_X3Y1", + "NOC_NPS_VNOC_X1Y35", "port0_out", - "NOC_NPS5555_X1Y1", + "NOC_NPS_VNOC_X1Y37", "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NPS_VNOC_X1Y37", "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NCRB_X1Y1", "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NCRB_X1Y1", "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X6Y4", "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X6Y4", "port2_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X3Y1", "port0_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X3Y1", "port3_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X4Y1", "port0_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X4Y1", "port3_out", - "NOC_NPS5555_X6Y6", + "NOC_NPS5555_X7Y4", "port1_in", - "NOC_NPS5555_X6Y6", + "NOC_NPS5555_X7Y4", "port2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X5Y1", "port0_in", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X5Y1", "port3_out", - "NOC_NPS6_X4Y2", + "NOC_NPS6_X6Y1", "port0_in", - "NOC_NPS6_X4Y2", + "NOC_NPS6_X6Y1", "port4_out", - "NOC_NPS4_X4Y1", - "portSideA2_in", - "NOC_NPS4_X4Y1", - "portSideB0_out", - "HBM_MC_X8Y0", - "pc0_port1_in" + "NOC_NPS4_X6Y1", + "portSideA1_in", + "NOC_NPS4_X6Y1", + "portSideB1_out", + "HBM_MC_X12Y0", + "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 133 - }, + "AchievedLatency": 137 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X8Y0", @@ -35611,198 +35403,161 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 133 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceStart": "HBM_MC_X8Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X14Y0", + "HBM_MC_X8Y0", "pc0_port1_out", - "NOC_NPS4_X7Y1", + "NOC_NPS4_X4Y1", "portSideB0_in", - "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", + "NOC_NPS4_X4Y1", + "portSideA2_out", + "NOC_NPS6_X4Y2", "port4_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X4Y2", "port0_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", "port2_in", - "NOC_NPS5555_X8Y4", + "NOC_NPS5555_X6Y6", "port1_out", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X2Y2", "port3_in", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X1Y2", "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X1Y2", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X0Y32", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X4Y4", "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NPS7575_X4Y4", "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", "port1_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X4Y2", "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y3", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y1", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y10", "port0_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", "NOC_NPS5555_X7Y2", "port0_out", "NOC_NPS5555_X5Y1", @@ -35823,12 +35578,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 141 + "AchievedLatency": 133 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -35912,111 +35667,116 @@ "NOC_NPS_VNOC_X1Y17", "port2_in", "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NPS_VNOC_X1Y16", "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", "port1_in", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X5Y4", "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y5", "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y6", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y28", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y30", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y32", "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", "port1_in", - "NOC_NPS5555_X8Y4", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", "port2_out", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X3Y2", "port0_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", "port4_out", - "NOC_NPS4_X7Y1", - "portSideA1_in", - "NOC_NPS4_X7Y1", + "NOC_NPS4_X4Y1", + "portSideA2_in", + "NOC_NPS4_X4Y1", "portSideB0_out", - "HBM_MC_X14Y0", + "HBM_MC_X8Y0", "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 141 - }, + "AchievedLatency": 133 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X14Y0", @@ -36400,166 +36160,177 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceStart": "HBM_MC_X14Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X3Y0", + "HBM_MC_X14Y0", "pc0_port1_out", - "NOC_NPS4_X1Y1", - "portSideB2_in", - "NOC_NPS4_X1Y1", - "portSideA2_out", - "NOC_NPS6_X1Y2", + "NOC_NPS4_X7Y1", + "portSideB0_in", + "NOC_NPS4_X7Y1", + "portSideA1_out", + "NOC_NPS6_X7Y1", "port4_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X7Y1", "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X8Y4", "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", + "NOC_NPS5555_X8Y4", "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS5555_X7Y4", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS5555_X6Y4", "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS5555_X6Y4", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NCRB_X1Y0", "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NCRB_X1Y0", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X5Y7", "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X1Y6", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X1Y6", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X1Y4", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X1Y4", "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS5555_X9Y2", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS5555_X9Y2", "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", "NOC_NPS5555_X7Y2", - "port1_in", + "port2_in", "NOC_NPS5555_X7Y2", "port0_out", "NOC_NPS5555_X5Y1", @@ -36580,12 +36351,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 125 + "AchievedLatency": 141 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -36605,143 +36376,196 @@ "NOC_NPS5555_X7Y2", "port0_in", "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS5555_X9Y2", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS5555_X9Y2", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS5555_X11Y2", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X1Y0", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NCRB_X1Y1", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS5555_X6Y4", "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS5555_X6Y4", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS6_X3Y1", "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS6_X5Y1", "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X8Y4", "port2_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X7Y1", "port0_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X7Y1", "port4_out", - "NOC_NPS4_X1Y1", - "portSideA2_in", - "NOC_NPS4_X1Y1", - "portSideB2_out", - "HBM_MC_X3Y0", + "NOC_NPS4_X7Y1", + "portSideA1_in", + "NOC_NPS4_X7Y1", + "portSideB0_out", + "HBM_MC_X14Y0", "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 125 - }, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X3Y0", @@ -37061,38 +36885,17 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { "PhyInstanceStart": "HBM_MC_X3Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ "HBM_MC_X3Y0", - "pc1_port1_out", + "pc0_port1_out", "NOC_NPS4_X1Y1", - "portSideB3_in", + "portSideB2_in", "NOC_NPS4_X1Y1", "portSideA2_out", "NOC_NPS6_X1Y2", @@ -37246,7 +37049,7 @@ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 4, + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -37394,15 +37197,36 @@ "NOC_NPS4_X1Y1", "portSideA2_in", "NOC_NPS4_X1Y1", - "portSideB3_out", + "portSideB2_out", "HBM_MC_X3Y0", - "pc1_port1_in" + "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X3Y0", @@ -37722,46 +37546,21 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceStart": "HBM_MC_X3Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X4Y0", - "pc0_port1_out", - "NOC_NPS4_X2Y1", - "portSideB0_in", - "NOC_NPS4_X2Y1", + "HBM_MC_X3Y0", + "pc1_port1_out", + "NOC_NPS4_X1Y1", + "portSideB3_in", + "NOC_NPS4_X1Y1", "portSideA2_out", - "NOC_NPS6_X2Y2", - "port4_in", - "NOC_NPS6_X2Y2", - "port0_out", "NOC_NPS6_X1Y2", - "port3_in", + "port4_in", "NOC_NPS6_X1Y2", "port0_out", "NOC_NPS5555_X5Y6", @@ -37906,12 +37705,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 127 + "AchievedLatency": 125 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -38055,23 +37854,40 @@ "NOC_NPS6_X1Y2", "port0_in", "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", "port4_out", - "NOC_NPS4_X2Y1", + "NOC_NPS4_X1Y1", "portSideA2_in", - "NOC_NPS4_X2Y1", - "portSideB0_out", - "HBM_MC_X4Y0", - "pc0_port1_in" + "NOC_NPS4_X1Y1", + "portSideB3_out", + "HBM_MC_X3Y0", + "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 127 - }, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X4Y0", @@ -38399,54 +38215,21 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceStart": "HBM_MC_X4Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X9Y0", + "HBM_MC_X4Y0", "pc0_port1_out", - "NOC_NPS4_X4Y1", - "portSideB2_in", - "NOC_NPS4_X4Y1", + "NOC_NPS4_X2Y1", + "portSideB0_in", + "NOC_NPS4_X2Y1", "portSideA2_out", - "NOC_NPS6_X4Y2", - "port4_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", "NOC_NPS6_X2Y2", - "port3_in", + "port4_in", "NOC_NPS6_X2Y2", "port0_out", "NOC_NPS6_X1Y2", @@ -38595,12 +38378,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 133 + "AchievedLatency": 127 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -38748,31 +38531,40 @@ "NOC_NPS6_X2Y2", "port0_in", "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", "port4_out", - "NOC_NPS4_X4Y1", + "NOC_NPS4_X2Y1", "portSideA2_in", - "NOC_NPS4_X4Y1", - "portSideB2_out", - "HBM_MC_X9Y0", + "NOC_NPS4_X2Y1", + "portSideB0_out", + "HBM_MC_X4Y0", "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 133 - }, + "AchievedLatency": 127 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X9Y0", @@ -39124,42 +38916,33 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 133 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceStart": "HBM_MC_X9Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X4Y0", - "pc1_port1_out", - "NOC_NPS4_X2Y1", - "portSideB1_in", - "NOC_NPS4_X2Y1", + "HBM_MC_X9Y0", + "pc0_port1_out", + "NOC_NPS4_X4Y1", + "portSideB2_in", + "NOC_NPS4_X4Y1", "portSideA2_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X4Y2", "port4_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", "NOC_NPS6_X2Y2", "port0_out", "NOC_NPS6_X1Y2", @@ -39308,12 +39091,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 127 + "AchievedLatency": 133 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -39461,19 +39244,52 @@ "NOC_NPS6_X2Y2", "port0_in", "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", "port4_out", - "NOC_NPS4_X2Y1", + "NOC_NPS4_X4Y1", "portSideA2_in", - "NOC_NPS4_X2Y1", - "portSideB1_out", - "HBM_MC_X4Y0", - "pc1_port1_in" + "NOC_NPS4_X4Y1", + "portSideB2_out", + "HBM_MC_X9Y0", + "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 127 - }, + "AchievedLatency": 133 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X4Y0", @@ -39801,54 +39617,21 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceStart": "HBM_MC_X4Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X9Y0", + "HBM_MC_X4Y0", "pc1_port1_out", - "NOC_NPS4_X4Y1", - "portSideB3_in", - "NOC_NPS4_X4Y1", + "NOC_NPS4_X2Y1", + "portSideB1_in", + "NOC_NPS4_X2Y1", "portSideA2_out", - "NOC_NPS6_X4Y2", - "port4_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", "NOC_NPS6_X2Y2", - "port3_in", + "port4_in", "NOC_NPS6_X2Y2", "port0_out", "NOC_NPS6_X1Y2", @@ -39997,12 +39780,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 133 + "AchievedLatency": 127 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -40150,31 +39933,40 @@ "NOC_NPS6_X2Y2", "port0_in", "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", "port4_out", - "NOC_NPS4_X4Y1", + "NOC_NPS4_X2Y1", "portSideA2_in", - "NOC_NPS4_X4Y1", - "portSideB3_out", - "HBM_MC_X9Y0", + "NOC_NPS4_X2Y1", + "portSideB1_out", + "HBM_MC_X4Y0", "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 133 - }, + "AchievedLatency": 127 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X9Y0", @@ -40518,393 +40310,188 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceStart": "HBM_MC_X9Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X11Y0", + "HBM_MC_X9Y0", "pc1_port1_out", - "NOC_NPS4_X5Y1", + "NOC_NPS4_X4Y1", "portSideB3_in", - "NOC_NPS4_X5Y1", - "portSideA1_out", - "NOC_NPS6_X5Y1", + "NOC_NPS4_X4Y1", + "portSideA2_out", + "NOC_NPS6_X4Y2", "port4_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X4Y2", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X6Y6", "port1_out", - "NOC_NPS6_X4Y1", + "NOC_NPS6_X2Y2", "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X1Y2", "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X1Y2", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X5Y6", "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NCRB_X0Y0", "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NCRB_X0Y0", "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS_VNOC_X0Y36", "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y34", "port2_in", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y34", "port0_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS_VNOC_X0Y32", "port2_in", - "NOC_NPS5555_X7Y2", + "NOC_NPS_VNOC_X0Y32", "port0_out", - "NOC_NPS5555_X5Y1", + "NOC_NPS_VNOC_X0Y30", "port2_in", - "NOC_NPS5555_X5Y1", + "NOC_NPS_VNOC_X0Y30", "port0_out", - "NOC_NPS5555_X3Y1", + "NOC_NPS_VNOC_X0Y28", "port2_in", - "NOC_NPS5555_X3Y1", + "NOC_NPS_VNOC_X0Y28", "port0_out", - "NOC_NPS5555_X1Y1", + "NOC_NPS_VNOC_X0Y26", "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NPS5555_X11Y2", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", "port2_in", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X0Y24", "port0_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y22", "port2_in", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y22", "port0_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y20", "port2_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y20", "port0_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y18", "port2_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y18", "port0_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y16", "port2_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y16", "port0_out", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X0Y14", "port2_in", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X0Y14", "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y3", "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", + "NOC_NIDB_X0Y1", "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y10", "port0_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y8", "port2_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y8", "port0_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y6", "port2_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y6", "port0_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X0Y4", "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", + "NOC_NPS_VNOC_X0Y4", "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y2", "port2_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y2", "port0_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y0", "port2_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y0", "port0_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X7Y1", "port2_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", "port0_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X5Y1", "port2_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X5Y1", "port0_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X3Y1", "port2_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X3Y1", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X1Y1", "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port4_out", - "NOC_NPS4_X5Y1", - "portSideA1_in", - "NOC_NPS4_X5Y1", - "portSideB3_out", - "HBM_MC_X11Y0", - "pc1_port1_in" + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" ], - "RequiredBW": 33, - "AchievedBW": 33, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 135 + "AchievedLatency": 133 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 1, - "CommType": "WRITE", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 0, + "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", "req_out", @@ -40923,352 +40510,168 @@ "NOC_NPS5555_X7Y2", "port0_in", "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X7Y1", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X7Y1", "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X0Y0", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X0Y0", "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port4_out", - "NOC_NPS4_X5Y1", - "portSideA1_in", - "NOC_NPS4_X5Y1", - "portSideB3_out", - "HBM_MC_X11Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X11Y0", - "pc1_port1_out", - "NOC_NPS4_X5Y1", - "portSideB3_in", - "NOC_NPS4_X5Y1", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port4_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X0Y2", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X0Y2", "port2_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X0Y4", "port0_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X0Y4", "port2_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X0Y6", "port0_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X0Y6", "port2_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y8", "port0_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X0Y8", "port2_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y10", "port0_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X0Y10", "port2_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y12", "port0_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X0Y12", "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X0Y1", "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y3", "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y3", "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", "port0_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X0Y14", "port2_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port0_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X0Y16", "port2_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port0_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X0Y18", "port2_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port0_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X0Y20", "port2_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port0_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X0Y22", "port2_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X0Y24", "port0_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X0Y24", "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y5", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y7", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y7", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", "port0_in", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X0Y26", "port2_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y28", "port0_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X0Y28", "port2_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y30", "port0_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X0Y30", "port2_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y32", "port0_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X0Y32", "port2_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y34", "port0_in", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X0Y34", "port2_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X0Y36", "port0_in", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X0Y36", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", "port3_out", - "NOC_NPS5555_X11Y2", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port4_out", + "NOC_NPS4_X4Y1", + "portSideA2_in", + "NOC_NPS4_X4Y1", + "portSideB3_out", + "HBM_MC_X9Y0", + "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 135 + "AchievedLatency": 133 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", "ToLocked": false, - "Port": "PORT1", + "Port": "PORT3", "ReadTC": "BE", "WriteTC": "BE", "ReadBW": 132, @@ -41282,126 +40685,486 @@ "PathLocked": true, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 1, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X11Y0", - "pc0_port1_out", - "NOC_NPS4_X5Y1", - "portSideB2_in", - "NOC_NPS4_X5Y1", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port4_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X5Y1", "port2_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X7Y2", "port0_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X7Y2", "port2_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X9Y2", "port0_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X9Y2", "port2_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X11Y2", "port0_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X11Y2", "port2_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS5555_X13Y2", "port0_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS5555_X13Y2", "port2_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS5555_X15Y2", "port0_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS5555_X15Y2", "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NPS5555_X17Y2", "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X5Y1", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NPS_VNOC_X1Y13", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port4_out", + "NOC_NPS4_X5Y1", + "portSideA2_in", + "NOC_NPS4_X5Y1", + "portSideB3_out", + "HBM_MC_X11Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X11Y0", + "pc1_port1_out", + "NOC_NPS4_X5Y1", + "portSideB3_in", + "NOC_NPS4_X5Y1", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port4_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X11Y0", + "pc1_port1_out", + "NOC_NPS4_X5Y1", + "portSideB3_in", + "NOC_NPS4_X5Y1", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port4_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", "port0_in", "NOC_NPS_VNOC_X1Y11", "port2_out", @@ -41464,7 +41227,7 @@ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 4, + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -41632,15 +41395,36 @@ "NOC_NPS4_X5Y1", "portSideA1_in", "NOC_NPS4_X5Y1", - "portSideB2_out", + "portSideB3_out", "HBM_MC_X11Y0", - "pc0_port1_in" + "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 135 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X11Y0", @@ -41672,145 +41456,145 @@ "NOC_NPS5555_X11Y2", "port0_in", "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port3_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NIDB_X1Y0", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port4_out", "NOC_NPS4_X5Y1", - "portSideA1_in", + "portSideA2_in", "NOC_NPS4_X5Y1", "portSideB2_out", "HBM_MC_X11Y0", @@ -41832,145 +41616,145 @@ "NOC_NPS4_X5Y1", "portSideB2_in", "NOC_NPS4_X5Y1", - "portSideA1_out", - "NOC_NPS6_X5Y1", + "portSideA2_out", + "NOC_NPS6_X5Y2", "port4_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", "port3_out", - "NOC_NPS5555_X11Y2", + "NOC_NPS5555_X17Y2", "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", "NOC_NPS5555_X11Y2", "port0_out", "NOC_NPS5555_X9Y2", @@ -42000,178 +41784,165 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceStart": "HBM_MC_X11Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X7Y0", - "pc1_port1_out", - "NOC_NPS4_X3Y1", - "portSideB3_in", - "NOC_NPS4_X3Y1", + "HBM_MC_X11Y0", + "pc0_port1_out", + "NOC_NPS4_X5Y1", + "portSideB2_in", + "NOC_NPS4_X5Y1", "portSideA2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X5Y2", "port4_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_out", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_in", - "NOC_NCRB_X0Y0", + "NOC_NCRB_X2Y0", "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port3_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS5555_X17Y2", "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", "NOC_NPS5555_X7Y2", "port0_out", "NOC_NPS5555_X5Y1", @@ -42192,12 +41963,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 131 + "AchievedLatency": 135 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -42217,155 +41988,184 @@ "NOC_NPS5555_X7Y2", "port0_in", "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port3_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS7575_X4Y2", + "NOC_NPS7575_X6Y2", "port1_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X2Y20", "port2_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port0_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X2Y22", "port2_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port0_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X2Y24", "port2_out", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port1_in", - "NOC_NPS7575_X4Y4", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X2Y5", "port1_out", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port1_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X2Y7", "port0_out", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port3_in", - "NOC_NPS7575_X4Y6", + "NOC_NPS7575_X6Y6", "port1_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port0_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X2Y26", "port2_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port0_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X2Y28", "port2_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port0_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X2Y30", "port2_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port0_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X2Y32", "port2_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port0_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X2Y34", "port2_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port0_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X2Y36", "port2_out", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_in", - "NOC_NCRB_X0Y1", + "NOC_NCRB_X2Y1", "port1_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X7Y6", "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X5Y2", "port4_out", - "NOC_NPS4_X3Y1", + "NOC_NPS4_X5Y1", "portSideA2_in", - "NOC_NPS4_X3Y1", - "portSideB3_out", - "HBM_MC_X7Y0", - "pc1_port1_in" + "NOC_NPS4_X5Y1", + "portSideB2_out", + "HBM_MC_X11Y0", + "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 131 - }, + "AchievedLatency": 135 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X7Y0", @@ -42709,216 +42509,183 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceStart": "HBM_MC_X7Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X13Y0", - "pc0_port1_out", - "NOC_NPS4_X6Y1", - "portSideB2_in", - "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", + "HBM_MC_X7Y0", + "pc1_port1_out", + "NOC_NPS4_X3Y1", + "portSideB3_in", + "NOC_NPS4_X3Y1", + "portSideA2_out", + "NOC_NPS6_X3Y2", "port4_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X3Y2", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X6Y6", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X6Y6", "port1_out", - "NOC_NPS6_X4Y1", + "NOC_NPS6_X2Y2", "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X1Y2", "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X1Y2", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X5Y6", "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NCRB_X0Y0", "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", "port1_in", - "NOC_NPS7575_X5Y5", + "NOC_NPS7575_X4Y6", "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y5", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X0Y5", "port0_out", - "NOC_NPS7575_X5Y1", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", "port1_in", - "NOC_NPS7575_X5Y1", + "NOC_NPS7575_X4Y2", "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", "port1_in", - "NOC_NPS5555_X11Y2", + "NOC_NIDB_X0Y1", "port0_out", - "NOC_NPS5555_X9Y2", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", "port2_in", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y12", "port0_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS_VNOC_X0Y10", "port2_in", - "NOC_NPS5555_X7Y2", + "NOC_NPS_VNOC_X0Y10", "port0_out", - "NOC_NPS5555_X5Y1", + "NOC_NPS_VNOC_X0Y8", "port2_in", - "NOC_NPS5555_X5Y1", + "NOC_NPS_VNOC_X0Y8", "port0_out", - "NOC_NPS5555_X3Y1", + "NOC_NPS_VNOC_X0Y6", "port2_in", - "NOC_NPS5555_X3Y1", + "NOC_NPS_VNOC_X0Y6", "port0_out", - "NOC_NPS5555_X1Y1", + "NOC_NPS_VNOC_X0Y4", "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 137 + "AchievedLatency": 131 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -42938,167 +42705,176 @@ "NOC_NPS5555_X7Y2", "port0_in", "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", "port2_out", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y0", "port0_in", - "NOC_NPS5555_X9Y2", + "NOC_NPS_VNOC_X0Y0", "port2_out", - "NOC_NPS5555_X11Y2", + "NOC_NPS_VNOC_X0Y2", "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS_VNOC_X0Y2", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS_VNOC_X0Y4", "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", "port1_in", - "NOC_NPS7575_X5Y3", + "NOC_NPS7575_X0Y0", "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y1", "port0_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X0Y1", "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X0Y3", "port1_in", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X0Y3", "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", "port1_in", - "NOC_NPS7575_X5Y7", + "NOC_NPS7575_X4Y4", "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X0Y5", "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X4Y6", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X0Y28", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X1Y2", "port0_in", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X1Y2", "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X2Y2", "port0_in", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB2_out", - "HBM_MC_X13Y0", - "pc0_port1_in" + "NOC_NPS4_X3Y1", + "portSideA2_in", + "NOC_NPS4_X3Y1", + "portSideB3_out", + "HBM_MC_X7Y0", + "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 137 - }, + "AchievedLatency": 131 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X13Y0", @@ -43130,157 +42906,157 @@ "NOC_NPS5555_X11Y2", "port0_in", "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port3_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X5Y3", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NIDB_X2Y3", "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NIDB_X2Y5", "port0_in", - "NOC_NPS6_X6Y1", - "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB2_out", - "HBM_MC_X13Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA2_in", + "NOC_NPS4_X6Y1", + "portSideB2_out", + "HBM_MC_X13Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, "AchievedLatency": 137 }, { @@ -43288,6 +43064,190 @@ "PhyInstanceEnd": "NOC_NMU128_X0Y1", "VC": 3, "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X13Y0", + "pc0_port1_out", + "NOC_NPS4_X6Y1", + "portSideB2_in", + "NOC_NPS4_X6Y1", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port4_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", "Connections": [ "HBM_MC_X13Y0", "pc0_port1_out", @@ -43462,376 +43422,216 @@ "NOC_NMU128_X0Y1", "resp_in" ], - "RequiredBW": 33, - "AchievedBW": 33, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 0, + "CommType": "READ_REQ", "Connections": [ - "HBM_MC_X7Y0", - "pc0_port1_out", - "NOC_NPS4_X3Y1", - "portSideB2_in", - "NOC_NPS4_X3Y1", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port4_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", + "NOC_NPS5555_X11Y1", "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", "port2_in", - "NOC_NPS_VNOC_X0Y36", + "NOC_NPS_VNOC_X1Y3", "port0_out", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X1Y5", "port2_in", - "NOC_NPS_VNOC_X0Y34", + "NOC_NPS_VNOC_X1Y5", "port0_out", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X1Y7", "port2_in", - "NOC_NPS_VNOC_X0Y32", + "NOC_NPS_VNOC_X1Y7", "port0_out", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X1Y9", "port2_in", - "NOC_NPS_VNOC_X0Y30", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X1Y11", "port2_in", - "NOC_NPS_VNOC_X0Y28", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X1Y13", "port2_in", - "NOC_NPS_VNOC_X0Y26", + "NOC_NPS_VNOC_X1Y13", "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NIDB_X0Y7", + "NOC_NIDB_X1Y0", "port1_out", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NIDB_X0Y5", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", "port2_in", - "NOC_NPS_VNOC_X0Y24", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X1Y17", "port2_in", - "NOC_NPS_VNOC_X0Y22", + "NOC_NPS_VNOC_X1Y17", "port0_out", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X1Y19", "port2_in", - "NOC_NPS_VNOC_X0Y20", + "NOC_NPS_VNOC_X1Y19", "port0_out", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X1Y21", "port2_in", - "NOC_NPS_VNOC_X0Y18", + "NOC_NPS_VNOC_X1Y21", "port0_out", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X1Y23", "port2_in", - "NOC_NPS_VNOC_X0Y16", + "NOC_NPS_VNOC_X1Y23", "port0_out", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X1Y25", "port2_in", - "NOC_NPS_VNOC_X0Y14", + "NOC_NPS_VNOC_X1Y25", "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NIDB_X0Y3", + "NOC_NIDB_X1Y4", "port1_out", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NIDB_X0Y1", + "NOC_NIDB_X1Y6", "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X1Y27", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X1Y29", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X1Y29", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X1Y31", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X1Y31", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X1Y33", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X1Y33", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X1Y35", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X1Y35", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X1Y37", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X1Y37", "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", "port1_in", - "NOC_NPS5555_X1Y1", + "NOC_NPS5555_X7Y4", "port2_out", - "NOC_NPS5555_X3Y1", + "NOC_NPS6_X5Y1", "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X5Y1", "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X6Y1", "port0_in", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X6Y1", "port4_out", - "NOC_NPS4_X3Y1", - "portSideA2_in", - "NOC_NPS4_X3Y1", + "NOC_NPS4_X6Y1", + "portSideA1_in", + "NOC_NPS4_X6Y1", "portSideB2_out", - "HBM_MC_X7Y0", + "HBM_MC_X13Y0", "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 131 - }, + "AchievedLatency": 137 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X7Y0", @@ -44175,42 +43975,33 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceStart": "HBM_MC_X7Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "HBM_MC_X2Y0", - "pc1_port1_out", - "NOC_NPS4_X1Y1", - "portSideB1_in", - "NOC_NPS4_X1Y1", + "HBM_MC_X7Y0", + "pc0_port1_out", + "NOC_NPS4_X3Y1", + "portSideB2_in", + "NOC_NPS4_X3Y1", "portSideA2_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X3Y2", "port4_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", "NOC_NPS6_X1Y2", "port0_out", "NOC_NPS5555_X5Y6", @@ -44355,12 +44146,12 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 125 + "AchievedLatency": 131 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -44504,19 +44295,52 @@ "NOC_NPS6_X1Y2", "port0_in", "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", "port4_out", - "NOC_NPS4_X1Y1", + "NOC_NPS4_X3Y1", "portSideA2_in", - "NOC_NPS4_X1Y1", - "portSideB1_out", - "HBM_MC_X2Y0", - "pc1_port1_in" + "NOC_NPS4_X3Y1", + "portSideB2_out", + "HBM_MC_X7Y0", + "pc0_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 125 - }, + "AchievedLatency": 131 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X2Y0", @@ -44836,38 +44660,17 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { "PhyInstanceStart": "HBM_MC_X2Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ "HBM_MC_X2Y0", - "pc0_port1_out", + "pc1_port1_out", "NOC_NPS4_X1Y1", - "portSideB0_in", + "portSideB1_in", "NOC_NPS4_X1Y1", "portSideA2_out", "NOC_NPS6_X1Y2", @@ -45021,7 +44824,7 @@ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 4, + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -45169,15 +44972,36 @@ "NOC_NPS4_X1Y1", "portSideA2_in", "NOC_NPS4_X1Y1", - "portSideB0_out", + "portSideB1_out", "HBM_MC_X2Y0", - "pc0_port1_in" + "pc1_port1_in" ], "RequiredBW": 33, "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X2Y0", @@ -45497,158 +45321,137 @@ "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/M00_AXI_nsu", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 5, - "WriteBW": 5, - "ReadAchievedBW": 5, - "WriteAchievedBW": 5, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "NOC_NSU512_X0Y0", + "PhyInstanceStart": "HBM_MC_X2Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, + "VC": 2, "CommType": "READ", "Connections": [ - "NOC_NSU512_X0Y0", - "resp", - "NOC_NPS_VNOC_X0Y0", - "port3_in", - "NOC_NPS_VNOC_X0Y0", + "HBM_MC_X2Y0", + "pc0_port1_out", + "NOC_NPS4_X1Y1", + "portSideB0_in", + "NOC_NPS4_X1Y1", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port4_in", + "NOC_NPS6_X1Y2", "port0_out", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X5Y6", "port2_in", - "NOC_NPS5555_X7Y1", + "NOC_NPS5555_X5Y6", "port3_out", - "NOC_NPS5555_X7Y2", + "NOC_NCRB_X0Y0", "port1_in", - "NOC_NPS5555_X7Y2", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", "port0_out", - "NOC_NPS5555_X5Y1", + "NOC_NPS_VNOC_X0Y34", "port2_in", - "NOC_NPS5555_X5Y1", + "NOC_NPS_VNOC_X0Y34", "port0_out", - "NOC_NPS5555_X3Y1", + "NOC_NPS_VNOC_X0Y32", "port2_in", - "NOC_NPS5555_X3Y1", + "NOC_NPS_VNOC_X0Y32", "port0_out", - "NOC_NPS5555_X1Y1", + "NOC_NPS_VNOC_X0Y30", "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 5, - "AchievedBW": 5, - "RequiredLatency": 300, - "AchievedLatency": 22 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "NOC_NSU512_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", "port0_in", - "NOC_NPS5555_X7Y2", + "NOC_NIDB_X0Y7", "port1_out", - "NOC_NPS5555_X7Y1", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port3_out", - "NOC_NSU512_X0Y0", - "req" - ], - "RequiredBW": 1, - "AchievedBW": 1, - "RequiredLatency": 300, - "AchievedLatency": 22 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "NOC_NSU512_X0Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", "port0_in", - "NOC_NPS5555_X7Y2", + "NOC_NIDB_X0Y3", "port1_out", - "NOC_NPS5555_X7Y1", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port3_out", - "NOC_NSU512_X0Y0", - "req" - ], - "RequiredBW": 5, - "AchievedBW": 5, - "RequiredLatency": 300, - "AchievedLatency": 22 - }, - { - "PhyInstanceStart": "NOC_NSU512_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "NOC_NSU512_X0Y0", - "resp", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", "NOC_NPS_VNOC_X0Y0", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X0Y0", "port0_out", "NOC_NPS5555_X7Y1", @@ -45674,26 +45477,186 @@ "NOC_NMU128_X0Y1", "resp_in" ], - "RequiredBW": 1, - "AchievedBW": 1, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 22 + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port4_out", + "NOC_NPS4_X1Y1", + "portSideA2_in", + "NOC_NPS4_X1Y1", + "portSideB0_out", + "HBM_MC_X2Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", + "To": "top_i/axi_noc_cips/inst/M00_AXI_nsu/bd_6ff4_M00_AXI_nsu_0_top_INST/NOC_NSU512_INST", "ToLocked": false, - "Port": "PORT3", + "Port": "PORT0", "ReadTC": "BE", "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, + "ReadBW": 5, + "WriteBW": 5, + "ReadAchievedBW": 5, + "WriteAchievedBW": 5, "ReadLatency": 300, "WriteLatency": 300, "ReadBestPossibleLatency": 300, @@ -45701,127 +45664,171 @@ "PathLocked": true, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "NOC_NSU512_X1Y6", + "VC": 1, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X13Y0", - "pc1_port1_out", - "NOC_NPS4_X6Y1", - "portSideB3_in", - "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port4_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NPS5555_X11Y1", "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y1", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port1_out", + "NOC_NPS_VNOC_X1Y2", + "port1_in", + "NOC_NPS_VNOC_X1Y2", "port2_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X1Y4", "port0_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X1Y4", "port2_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X1Y6", "port0_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X1Y6", "port2_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X1Y8", "port0_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X1Y8", "port2_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X1Y10", "port0_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X1Y10", "port2_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X1Y12", "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", + "NOC_NPS_VNOC_X1Y12", + "port3_out", + "NOC_NSU512_X1Y6", + "req" + ], + "RequiredBW": 5, + "AchievedBW": 5, + "RequiredLatency": 300, + "AchievedLatency": 40 + }, + { + "PhyInstanceStart": "NOC_NSU512_X1Y6", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "NOC_NSU512_X1Y6", + "resp", + "NOC_NPS_VNOC_X1Y12", "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X1Y12", "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NPS_VNOC_X1Y10", + "port2_in", + "NOC_NPS_VNOC_X1Y10", + "port1_out", + "NOC_NPS_VNOC_X1Y11", "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X1Y11", "port2_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X1Y9", "port0_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X1Y9", "port2_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X1Y7", "port0_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X1Y7", "port2_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X1Y5", "port0_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X1Y5", "port2_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X1Y3", "port0_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X1Y3", "port2_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X1Y1", "port0_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X1Y1", "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", "port1_in", - "NOC_NIDB_X1Y0", + "NOC_NPS5555_X11Y2", "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 1, + "AchievedBW": 1, + "RequiredLatency": 300, + "AchievedLatency": 40 + }, + { + "PhyInstanceStart": "NOC_NSU512_X1Y6", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "NOC_NSU512_X1Y6", + "resp", + "NOC_NPS_VNOC_X1Y12", + "port3_in", + "NOC_NPS_VNOC_X1Y12", + "port1_out", "NOC_NPS_VNOC_X1Y13", - "port0_in", + "port1_in", "NOC_NPS_VNOC_X1Y13", "port2_out", "NOC_NPS_VNOC_X1Y11", @@ -45879,15 +45886,15 @@ "NOC_NMU128_X0Y1", "resp_in" ], - "RequiredBW": 132, - "AchievedBW": 132, + "RequiredBW": 5, + "AchievedBW": 5, "RequiredLatency": 300, - "AchievedLatency": 137 + "AchievedLatency": 40 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 4, + "PhyInstanceEnd": "NOC_NSU512_X1Y6", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -45927,147 +45934,60 @@ "NOC_NPS_VNOC_X1Y3", "port2_in", "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", + "NOC_NPS_VNOC_X1Y2", "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X1Y2", + "port2_out", + "NOC_NPS_VNOC_X1Y4", "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y4", + "port2_out", + "NOC_NPS_VNOC_X1Y6", "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y6", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y8", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y10", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y12", "port0_in", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y12", "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB3_out", - "HBM_MC_X13Y0", - "pc1_port1_in" + "NOC_NSU512_X1Y6", + "req" ], - "RequiredBW": 33, - "AchievedBW": 33, + "RequiredBW": 1, + "AchievedBW": 1, "RequiredLatency": 300, - "AchievedLatency": 137 - }, + "AchievedLatency": 40 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "HBM_MC_X13Y0", @@ -46099,164 +46019,348 @@ "NOC_NPS5555_X11Y2", "port0_in", "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port3_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA2_in", + "NOC_NPS4_X6Y1", + "portSideB3_out", + "HBM_MC_X13Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X13Y0", + "pc1_port1_out", + "NOC_NPS4_X6Y1", + "portSideB3_in", + "NOC_NPS4_X6Y1", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port4_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", "port2_in", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", "port0_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X2Y34", "port2_in", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X2Y34", "port0_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X2Y32", "port2_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X2Y32", "port0_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X2Y30", "port2_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X2Y30", "port0_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X2Y28", "port2_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X2Y28", "port0_out", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X2Y26", "port2_in", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X2Y26", "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", "port0_in", - "NOC_NIDB_X1Y0", + "NOC_NIDB_X2Y7", "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y5", "port1_in", - "NOC_NIDB_X1Y2", + "NOC_NIDB_X2Y5", "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", "port2_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X2Y24", "port0_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X2Y22", "port2_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X2Y22", "port0_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X2Y20", "port2_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X2Y20", "port0_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X2Y18", "port2_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X2Y18", "port0_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X2Y16", "port2_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X2Y16", "port0_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X2Y14", "port2_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X2Y14", "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NIDB_X1Y4", + "NOC_NIDB_X2Y3", "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X2Y1", "port1_in", - "NOC_NIDB_X1Y6", + "NOC_NIDB_X2Y1", "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", "port2_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X2Y12", "port0_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X2Y10", "port2_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X2Y10", "port0_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X2Y8", "port2_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X2Y8", "port0_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X2Y6", "port2_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X2Y6", "port0_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X2Y4", "port2_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X2Y4", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X2Y2", "port2_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X2Y2", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", "port3_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X17Y2", "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB3_out", - "HBM_MC_X13Y0", - "pc1_port1_in" + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" ], - "RequiredBW": 165, - "AchievedBW": 165, + "RequiredBW": 33, + "AchievedBW": 33, "RequiredLatency": 300, "AchievedLatency": 137 }, { "PhyInstanceStart": "HBM_MC_X13Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", + "VC": 2, + "CommType": "READ", "Connections": [ "HBM_MC_X13Y0", "pc1_port1_out", @@ -46431,64 +46535,15 @@ "NOC_NMU128_X0Y1", "resp_in" ], - "RequiredBW": 33, - "AchievedBW": 33, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "DDRMC_X0Y0", - "Port1_resp", - "NOC_NPS5555_X2Y1", - "port3_in", - "NOC_NPS5555_X2Y1", - "port0_out", - "NOC_NPS5555_X0Y1", - "port2_in", - "NOC_NPS5555_X0Y1", - "port3_out", - "NOC_NPS5555_X1Y1", - "port3_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 800, - "AchievedBW": 800, - "RequiredLatency": 300, - "AchievedLatency": 16 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 4, + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -46496,86 +46551,186 @@ "NOC_NPS5555_X1Y1", "port1_in", "NOC_NPS5555_X1Y1", - "port3_out", - "NOC_NPS5555_X0Y1", - "port3_in", - "NOC_NPS5555_X0Y1", "port2_out", - "NOC_NPS5555_X2Y1", + "NOC_NPS5555_X3Y1", "port0_in", - "NOC_NPS5555_X2Y1", - "port3_out", - "DDRMC_X0Y0", - "Port1_req" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 16 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port3_out", - "NOC_NPS5555_X0Y1", - "port3_in", - "NOC_NPS5555_X0Y1", + "NOC_NPS5555_X3Y1", "port2_out", - "NOC_NPS5555_X2Y1", + "NOC_NPS5555_X5Y1", "port0_in", - "NOC_NPS5555_X2Y1", - "port3_out", - "DDRMC_X0Y0", - "Port1_req" - ], - "RequiredBW": 850, - "AchievedBW": 850, - "RequiredLatency": 300, - "AchievedLatency": 16 - }, - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "DDRMC_X0Y0", - "Port1_resp", - "NOC_NPS5555_X2Y1", - "port3_in", - "NOC_NPS5555_X2Y1", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", "port0_out", - "NOC_NPS5555_X0Y1", + "NOC_NPS_VNOC_X1Y3", "port2_in", - "NOC_NPS5555_X0Y1", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NPS5555_X1Y1", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS5555_X1Y1", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA1_in", + "NOC_NPS4_X6Y1", + "portSideB3_out", + "HBM_MC_X13Y0", + "pc1_port1_in" ], - "RequiredBW": 50, - "AchievedBW": 50, + "RequiredBW": 33, + "AchievedBW": 33, "RequiredLatency": 300, - "AchievedLatency": 16 + "AchievedLatency": 137 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", "FromLocked": false, - "To": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", + "To": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", "ToLocked": false, "Port": "PORT1", "ReadTC": "BE", @@ -46591,27 +46746,71 @@ "PathLocked": true, "Nets": [ { - "PhyInstanceStart": "DDRMC_X1Y0", + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port3_out", + "NOC_NPS5555_X0Y1", + "port3_in", + "NOC_NPS5555_X0Y1", + "port2_out", + "NOC_NPS5555_X2Y1", + "port0_in", + "NOC_NPS5555_X2Y1", + "port3_out", + "DDRMC_X0Y0", + "Port1_req" + ], + "RequiredBW": 850, + "AchievedBW": 850, + "RequiredLatency": 300, + "AchievedLatency": 16 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", + "VC": 3, + "CommType": "WRITE_RESP", "Connections": [ - "DDRMC_X1Y0", + "DDRMC_X0Y0", "Port1_resp", - "NOC_NPS5555_X8Y2", + "NOC_NPS5555_X2Y1", "port3_in", - "NOC_NPS5555_X8Y2", - "port0_out", - "NOC_NPS5555_X6Y2", - "port2_in", - "NOC_NPS5555_X6Y2", + "NOC_NPS5555_X2Y1", "port0_out", - "NOC_NPS5555_X4Y1", + "NOC_NPS5555_X0Y1", "port2_in", - "NOC_NPS5555_X4Y1", - "port0_out", + "NOC_NPS5555_X0Y1", + "port3_out", + "NOC_NPS5555_X1Y1", + "port3_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 16 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "DDRMC_X0Y0", + "Port1_resp", "NOC_NPS5555_X2Y1", - "port2_in", + "port3_in", "NOC_NPS5555_X2Y1", "port0_out", "NOC_NPS5555_X0Y1", @@ -46628,12 +46827,12 @@ "RequiredBW": 800, "AchievedBW": 800, "RequiredLatency": 300, - "AchievedLatency": 22 + "AchievedLatency": 16 }, { "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "DDRMC_X1Y0", - "VC": 4, + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 0, "CommType": "READ_REQ", "Connections": [ "NOC_NMU128_X0Y1", @@ -46649,27 +46848,36 @@ "NOC_NPS5555_X2Y1", "port0_in", "NOC_NPS5555_X2Y1", - "port2_out", - "NOC_NPS5555_X4Y1", - "port0_in", - "NOC_NPS5555_X4Y1", - "port2_out", - "NOC_NPS5555_X6Y2", - "port0_in", - "NOC_NPS5555_X6Y2", - "port2_out", - "NOC_NPS5555_X8Y2", - "port0_in", - "NOC_NPS5555_X8Y2", "port3_out", - "DDRMC_X1Y0", + "DDRMC_X0Y0", "Port1_req" ], "RequiredBW": 50, "AchievedBW": 50, "RequiredLatency": 300, - "AchievedLatency": 22 - }, + "AchievedLatency": 16 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_1/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "DDRMC_X1Y0", @@ -46749,116 +46957,108 @@ "AchievedBW": 50, "RequiredLatency": 300, "AchievedLatency": 22 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S02_AXI_nmu", - "FromLocked": true, - "To": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { "PhyInstanceStart": "DDRMC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y2", - "VC": 6, + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, "CommType": "READ", "Connections": [ "DDRMC_X1Y0", - "Port0_resp", - "NOC_NPS5555_X8Y0", - "port1_in", - "NOC_NPS5555_X8Y0", + "Port1_resp", + "NOC_NPS5555_X8Y2", + "port3_in", + "NOC_NPS5555_X8Y2", "port0_out", - "NOC_NPS5555_X6Y0", + "NOC_NPS5555_X6Y2", "port2_in", - "NOC_NPS5555_X6Y0", + "NOC_NPS5555_X6Y2", "port0_out", - "NOC_NPS5555_X4Y0", + "NOC_NPS5555_X4Y1", "port2_in", - "NOC_NPS5555_X4Y0", + "NOC_NPS5555_X4Y1", "port0_out", - "NOC_NPS5555_X2Y0", + "NOC_NPS5555_X2Y1", "port2_in", - "NOC_NPS5555_X2Y0", + "NOC_NPS5555_X2Y1", "port0_out", - "NOC_NPS5555_X0Y0", - "port2_in", - "NOC_NPS5555_X0Y0", - "port3_out", "NOC_NPS5555_X0Y1", - "port1_in", + "port2_in", "NOC_NPS5555_X0Y1", "port3_out", "NOC_NPS5555_X1Y1", "port3_in", "NOC_NPS5555_X1Y1", - "port0_out", - "NOC_NMU128_X0Y2", + "port1_out", + "NOC_NMU128_X0Y1", "resp_in" ], "RequiredBW": 800, "AchievedBW": 800, "RequiredLatency": 300, - "AchievedLatency": 24 + "AchievedLatency": 22 }, { - "PhyInstanceStart": "NOC_NMU128_X0Y2", + "PhyInstanceStart": "NOC_NMU128_X0Y1", "PhyInstanceEnd": "DDRMC_X1Y0", - "VC": 4, + "VC": 0, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU128_X0Y2", + "NOC_NMU128_X0Y1", "req_out", "NOC_NPS5555_X1Y1", - "port0_in", + "port1_in", "NOC_NPS5555_X1Y1", "port3_out", "NOC_NPS5555_X0Y1", "port3_in", "NOC_NPS5555_X0Y1", - "port1_out", - "NOC_NPS5555_X0Y0", - "port3_in", - "NOC_NPS5555_X0Y0", "port2_out", - "NOC_NPS5555_X2Y0", + "NOC_NPS5555_X2Y1", "port0_in", - "NOC_NPS5555_X2Y0", + "NOC_NPS5555_X2Y1", "port2_out", - "NOC_NPS5555_X4Y0", + "NOC_NPS5555_X4Y1", "port0_in", - "NOC_NPS5555_X4Y0", + "NOC_NPS5555_X4Y1", "port2_out", - "NOC_NPS5555_X6Y0", + "NOC_NPS5555_X6Y2", "port0_in", - "NOC_NPS5555_X6Y0", + "NOC_NPS5555_X6Y2", "port2_out", - "NOC_NPS5555_X8Y0", + "NOC_NPS5555_X8Y2", "port0_in", - "NOC_NPS5555_X8Y0", - "port1_out", + "NOC_NPS5555_X8Y2", + "port3_out", "DDRMC_X1Y0", - "Port0_req" + "Port1_req" ], "RequiredBW": 50, "AchievedBW": 50, "RequiredLatency": 300, - "AchievedLatency": 24 - }, + "AchievedLatency": 22 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S02_AXI_nmu/bd_6ff4_S02_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_1/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y2", "PhyInstanceEnd": "DDRMC_X1Y0", @@ -46946,38 +47146,29 @@ "AchievedBW": 50, "RequiredLatency": 300, "AchievedLatency": 24 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S02_AXI_nmu", - "FromLocked": true, - "To": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { - "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceStart": "DDRMC_X1Y0", "PhyInstanceEnd": "NOC_NMU128_X0Y2", "VC": 6, "CommType": "READ", "Connections": [ - "DDRMC_X0Y0", + "DDRMC_X1Y0", "Port0_resp", + "NOC_NPS5555_X8Y0", + "port1_in", + "NOC_NPS5555_X8Y0", + "port0_out", + "NOC_NPS5555_X6Y0", + "port2_in", + "NOC_NPS5555_X6Y0", + "port0_out", + "NOC_NPS5555_X4Y0", + "port2_in", + "NOC_NPS5555_X4Y0", + "port0_out", "NOC_NPS5555_X2Y0", - "port3_in", + "port2_in", "NOC_NPS5555_X2Y0", "port0_out", "NOC_NPS5555_X0Y0", @@ -46998,11 +47189,11 @@ "RequiredBW": 800, "AchievedBW": 800, "RequiredLatency": 300, - "AchievedLatency": 18 + "AchievedLatency": 24 }, { "PhyInstanceStart": "NOC_NMU128_X0Y2", - "PhyInstanceEnd": "DDRMC_X0Y0", + "PhyInstanceEnd": "DDRMC_X1Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ @@ -47023,15 +47214,48 @@ "NOC_NPS5555_X2Y0", "port0_in", "NOC_NPS5555_X2Y0", - "port3_out", - "DDRMC_X0Y0", + "port2_out", + "NOC_NPS5555_X4Y0", + "port0_in", + "NOC_NPS5555_X4Y0", + "port2_out", + "NOC_NPS5555_X6Y0", + "port0_in", + "NOC_NPS5555_X6Y0", + "port2_out", + "NOC_NPS5555_X8Y0", + "port0_in", + "NOC_NPS5555_X8Y0", + "port1_out", + "DDRMC_X1Y0", "Port0_req" ], "RequiredBW": 50, "AchievedBW": 50, "RequiredLatency": 300, - "AchievedLatency": 18 - }, + "AchievedLatency": 24 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S02_AXI_nmu/bd_6ff4_S02_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y2", "PhyInstanceEnd": "DDRMC_X0Y0", @@ -47095,31 +47319,10 @@ "AchievedBW": 50, "RequiredLatency": 300, "AchievedLatency": 18 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S03_AXI_rpu", - "FromLocked": false, - "To": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + }, { "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y3", + "PhyInstanceEnd": "NOC_NMU128_X0Y2", "VC": 6, "CommType": "READ", "Connections": [ @@ -47136,12 +47339,12 @@ "NOC_NPS5555_X0Y1", "port1_in", "NOC_NPS5555_X0Y1", + "port3_out", + "NOC_NPS5555_X1Y1", + "port3_in", + "NOC_NPS5555_X1Y1", "port0_out", - "NOC_NPS5555_X1Y0", - "port0_in", - "NOC_NPS5555_X1Y0", - "port1_out", - "NOC_NMU128_X0Y3", + "NOC_NMU128_X0Y2", "resp_in" ], "RequiredBW": 800, @@ -47150,19 +47353,19 @@ "AchievedLatency": 18 }, { - "PhyInstanceStart": "NOC_NMU128_X0Y3", + "PhyInstanceStart": "NOC_NMU128_X0Y2", "PhyInstanceEnd": "DDRMC_X0Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU128_X0Y3", + "NOC_NMU128_X0Y2", "req_out", - "NOC_NPS5555_X1Y0", - "port1_in", - "NOC_NPS5555_X1Y0", - "port0_out", - "NOC_NPS5555_X0Y1", + "NOC_NPS5555_X1Y1", "port0_in", + "NOC_NPS5555_X1Y1", + "port3_out", + "NOC_NPS5555_X0Y1", + "port3_in", "NOC_NPS5555_X0Y1", "port1_out", "NOC_NPS5555_X0Y0", @@ -47180,7 +47383,28 @@ "AchievedBW": 50, "RequiredLatency": 300, "AchievedLatency": 18 - }, + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S03_AXI_rpu/bd_6ff4_S03_AXI_rpu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { "PhyInstanceStart": "NOC_NMU128_X0Y3", "PhyInstanceEnd": "DDRMC_X0Y0", @@ -47244,14 +47468,78 @@ "AchievedBW": 50, "RequiredLatency": 300, "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y3", + "VC": 6, + "CommType": "READ", + "Connections": [ + "DDRMC_X0Y0", + "Port0_resp", + "NOC_NPS5555_X2Y0", + "port3_in", + "NOC_NPS5555_X2Y0", + "port0_out", + "NOC_NPS5555_X0Y0", + "port2_in", + "NOC_NPS5555_X0Y0", + "port3_out", + "NOC_NPS5555_X0Y1", + "port1_in", + "NOC_NPS5555_X0Y1", + "port0_out", + "NOC_NPS5555_X1Y0", + "port0_in", + "NOC_NPS5555_X1Y0", + "port1_out", + "NOC_NMU128_X0Y3", + "resp_in" + ], + "RequiredBW": 800, + "AchievedBW": 800, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y3", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y3", + "req_out", + "NOC_NPS5555_X1Y0", + "port1_in", + "NOC_NPS5555_X1Y0", + "port0_out", + "NOC_NPS5555_X0Y1", + "port0_in", + "NOC_NPS5555_X0Y1", + "port1_out", + "NOC_NPS5555_X0Y0", + "port3_in", + "NOC_NPS5555_X0Y0", + "port2_out", + "NOC_NPS5555_X2Y0", + "port0_in", + "NOC_NPS5555_X2Y0", + "port3_out", + "DDRMC_X0Y0", + "Port0_req" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 18 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", "ToLocked": false, "Port": "PORT2", "ReadTC": "BE", @@ -47264,122 +47552,106 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X10Y0", - "pc1_port0_out", - "NOC_NPS4_X5Y0", - "portSideB1_in", - "NOC_NPS4_X5Y0", - "portSideA2_out", - "NOC_NPS6_X5Y2", - "port5_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port1_out", - "NOC_NPS6_X4Y2", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS6_X4Y2", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS5555_X6Y6", + "NOC_NPS_VNOC_X1Y13", "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", "port1_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", + "NOC_NPS7575_X5Y7", "port3_out", - "NOC_NPS5555_X7Y6", - "port1_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA2_in", - "NOC_NPS4_X5Y0", - "portSideB1_out", - "HBM_MC_X10Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -47416,11 +47688,11 @@ "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 29 + "AchievedLatency": 113 }, { "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ @@ -47457,178 +47729,345 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X15Y0", - "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB2_in", - "NOC_NPS4_X7Y0", - "portSideA0_out", - "NOC_NPS6_X7Y0", - "port5_in", - "NOC_NPS6_X7Y0", - "port0_out", - "NOC_NPS5555_X8Y3", - "port1_in", - "NOC_NPS5555_X8Y3", "port2_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS_VNOC_X1Y35", "port0_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS7575_X5Y7", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 37 + "AchievedLatency": 113 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 4, - "CommType": "READ_REQ", + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", + "HBM_MC_X10Y0", + "pc1_port0_out", + "NOC_NPS4_X5Y0", + "portSideB1_in", + "NOC_NPS4_X5Y0", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port5_in", + "NOC_NPS6_X5Y2", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port1_out", + "NOC_NPS6_X4Y2", + "port3_in", + "NOC_NPS6_X4Y2", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS6_X3Y2", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS6_X3Y2", "port0_out", - "NOC_NPS5555_X6Y3", + "NOC_NPS5555_X6Y6", "port2_in", - "NOC_NPS5555_X6Y3", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", "port1_out", - "NOC_NPS6_X3Y0", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", "port0_in", - "NOC_NPS6_X3Y0", - "port3_out", - "NOC_NPS6_X4Y0", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", "port0_in", - "NOC_NPS6_X4Y0", - "port3_out", - "NOC_NPS5555_X7Y3", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", "port0_in", - "NOC_NPS5555_X7Y3", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", "port1_out", - "NOC_NPS6_X5Y0", + "NOC_NIDB_X1Y6", "port0_in", - "NOC_NPS6_X5Y0", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", "port3_out", - "NOC_NPS6_X6Y0", + "NOC_NPS_VNOC_X1Y25", "port0_in", - "NOC_NPS6_X6Y0", - "port3_out", - "NOC_NPS5555_X8Y3", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", "port0_in", - "NOC_NPS5555_X8Y3", - "port1_out", - "NOC_NPS6_X7Y0", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", "port0_in", - "NOC_NPS6_X7Y0", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA0_in", - "NOC_NPS4_X7Y0", - "portSideB2_out", - "HBM_MC_X15Y0", - "pc0_port0_in" + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 37 + "AchievedLatency": 115 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 5, - "CommType": "WRITE", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 4, + "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", "NOC_NPS_VNOC_X1Y36", "port2_out", "NOC_NCRB_X1Y1", @@ -47654,102 +48093,26 @@ "NOC_NPS6_X5Y2", "port0_in", "NOC_NPS6_X5Y2", - "port3_out", - "NOC_NPS6_X6Y2", - "port0_in", - "NOC_NPS6_X6Y2", - "port3_out", - "NOC_NPS5555_X8Y6", - "port1_in", - "NOC_NPS5555_X8Y6", - "port2_out", - "NOC_NPS6_X7Y2", - "port0_in", - "NOC_NPS6_X7Y2", "port5_out", - "NOC_NPS4_X7Y0", + "NOC_NPS4_X5Y0", "portSideA2_in", - "NOC_NPS4_X7Y0", - "portSideB2_out", - "HBM_MC_X15Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X15Y0", - "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB2_in", - "NOC_NPS4_X7Y0", - "portSideA2_out", - "NOC_NPS6_X7Y2", - "port5_in", - "NOC_NPS6_X7Y2", - "port0_out", - "NOC_NPS5555_X8Y6", - "port2_in", - "NOC_NPS5555_X8Y6", - "port1_out", - "NOC_NPS6_X6Y2", - "port3_in", - "NOC_NPS6_X6Y2", - "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port1_out", - "NOC_NPS6_X4Y2", - "port3_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "NOC_NPS4_X5Y0", + "portSideB1_out", + "HBM_MC_X10Y0", + "pc1_port0_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 37 + "AchievedLatency": 115 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", "ToLocked": false, "Port": "PORT0", "ReadTC": "BE", @@ -47762,122 +48125,106 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X10Y0", - "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB0_in", - "NOC_NPS4_X5Y0", - "portSideA2_out", - "NOC_NPS6_X5Y2", - "port5_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port1_out", - "NOC_NPS6_X4Y2", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS6_X4Y2", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS5555_X6Y6", + "NOC_NPS_VNOC_X1Y13", "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", "port1_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", + "NOC_NPS7575_X5Y7", "port3_out", - "NOC_NPS5555_X7Y6", - "port1_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA2_in", - "NOC_NPS4_X5Y0", - "portSideB0_out", - "HBM_MC_X10Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -47887,73 +48234,89 @@ "NOC_NPS5555_X6Y4", "port3_in", "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port1_out", - "NOC_NPS6_X3Y0", + "port2_out", + "NOC_NPS6_X3Y1", "port0_in", - "NOC_NPS6_X3Y0", + "NOC_NPS6_X3Y1", "port3_out", - "NOC_NPS6_X4Y0", + "NOC_NPS6_X4Y1", "port0_in", - "NOC_NPS6_X4Y0", + "NOC_NPS6_X4Y1", "port3_out", - "NOC_NPS5555_X7Y3", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", "port0_in", - "NOC_NPS5555_X7Y3", - "port1_out", - "NOC_NPS6_X5Y0", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", "port0_in", - "NOC_NPS6_X5Y0", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", "port5_out", - "NOC_NPS4_X5Y0", - "portSideA0_in", - "NOC_NPS4_X5Y0", - "portSideB0_out", - "HBM_MC_X10Y0", + "NOC_NPS4_X7Y0", + "portSideA1_in", + "NOC_NPS4_X7Y0", + "portSideB2_out", + "HBM_MC_X15Y0", "pc0_port0_in" ], "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 31 + "AchievedLatency": 119 }, { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X10Y0", + "HBM_MC_X15Y0", "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB0_in", - "NOC_NPS4_X5Y0", - "portSideA0_out", - "NOC_NPS6_X5Y0", + "NOC_NPS4_X7Y0", + "portSideB2_in", + "NOC_NPS4_X7Y0", + "portSideA1_out", + "NOC_NPS6_X7Y1", "port5_in", - "NOC_NPS6_X5Y0", + "NOC_NPS6_X7Y1", "port0_out", - "NOC_NPS5555_X7Y3", - "port1_in", - "NOC_NPS5555_X7Y3", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", "port0_out", - "NOC_NPS6_X4Y0", + "NOC_NPS6_X5Y1", "port3_in", - "NOC_NPS6_X4Y0", + "NOC_NPS6_X5Y1", "port0_out", - "NOC_NPS6_X3Y0", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", "port3_in", - "NOC_NPS6_X3Y0", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", "port0_out", - "NOC_NPS5555_X6Y3", - "port1_in", - "NOC_NPS5555_X6Y3", - "port2_out", "NOC_NPS5555_X6Y4", - "port0_in", + "port2_in", "NOC_NPS5555_X6Y4", "port3_out", "NOC_NCRB_X1Y0", @@ -47963,227 +48326,113 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X5Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB2_in", - "NOC_NPS4_X2Y0", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port5_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", "port1_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y4", "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", "port1_in", - "NOC_NPS_VNOC_X1Y36", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", "port3_in", - "NOC_NPS5555_X6Y6", + "NOC_NPS7575_X5Y3", "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB2_out", - "HBM_MC_X5Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y2", "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA0_in", - "NOC_NPS4_X2Y0", - "portSideB2_out", - "HBM_MC_X5Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X5Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB2_in", - "NOC_NPS4_X2Y0", - "portSideA0_out", - "NOC_NPS6_X2Y0", - "port5_in", - "NOC_NPS6_X2Y0", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", "port3_out", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y13", "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y11", "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 119 + }, { "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 6, "CommType": "READ", "Connections": [ "HBM_MC_X15Y0", - "pc1_port0_out", + "pc0_port0_out", "NOC_NPS4_X7Y0", - "portSideB3_in", + "portSideB2_in", "NOC_NPS4_X7Y0", "portSideA0_out", "NOC_NPS6_X7Y0", @@ -48229,25 +48478,201 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 37 + "AchievedLatency": 121 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "NOC_NMU512_X1Y4", "PhyInstanceEnd": "HBM_MC_X15Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -48257,33 +48682,33 @@ "NOC_NPS5555_X6Y4", "port3_in", "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port1_out", + "NOC_NPS6_X3Y0", "port0_in", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X3Y0", "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS6_X4Y0", "port0_in", - "NOC_NPS6_X4Y1", + "NOC_NPS6_X4Y0", "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS5555_X7Y3", "port0_in", - "NOC_NPS6_X5Y1", + "NOC_NPS5555_X7Y3", + "port1_out", + "NOC_NPS6_X5Y0", + "port0_in", + "NOC_NPS6_X5Y0", "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X6Y0", "port0_in", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X6Y0", "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port0_out", "NOC_NPS5555_X8Y3", - "port2_in", + "port0_in", "NOC_NPS5555_X8Y3", "port1_out", "NOC_NPS6_X7Y0", @@ -48293,101 +48718,186 @@ "NOC_NPS4_X7Y0", "portSideA0_in", "NOC_NPS4_X7Y0", - "portSideB3_out", + "portSideB2_out", "HBM_MC_X15Y0", - "pc1_port0_in" + "pc0_port0_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 37 - }, + "AchievedLatency": 121 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X15Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X10Y0", "VC": 5, "CommType": "WRITE", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NPS6_X6Y1", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", "port3_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", "port1_in", - "NOC_NPS5555_X8Y4", + "NOC_NPS5555_X7Y4", "port2_out", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X5Y1", "port0_in", - "NOC_NPS6_X7Y1", + "NOC_NPS6_X5Y1", "port5_out", - "NOC_NPS4_X7Y0", + "NOC_NPS4_X5Y0", "portSideA1_in", - "NOC_NPS4_X7Y0", - "portSideB3_out", - "HBM_MC_X15Y0", - "pc1_port0_in" + "NOC_NPS4_X5Y0", + "portSideB0_out", + "HBM_MC_X10Y0", + "pc0_port0_in" ], "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 35 + "AchievedLatency": 113 }, { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X15Y0", - "pc1_port0_out", - "NOC_NPS4_X7Y0", - "portSideB3_in", - "NOC_NPS4_X7Y0", + "HBM_MC_X10Y0", + "pc0_port0_out", + "NOC_NPS4_X5Y0", + "portSideB0_in", + "NOC_NPS4_X5Y0", "portSideA1_out", - "NOC_NPS6_X7Y1", - "port5_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", "NOC_NPS6_X5Y1", - "port3_in", + "port5_in", "NOC_NPS6_X5Y1", "port0_out", "NOC_NPS5555_X7Y4", @@ -48413,58 +48923,133 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 35 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 113 + }, { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 6, "CommType": "READ", "Connections": [ - "HBM_MC_X5Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB3_in", - "NOC_NPS4_X2Y0", - "portSideA0_out", - "NOC_NPS6_X2Y0", + "HBM_MC_X10Y0", + "pc0_port0_out", + "NOC_NPS4_X5Y0", + "portSideB0_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", "port5_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", - "port2_out", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", "NOC_NPS5555_X6Y4", - "port0_in", + "port2_in", "NOC_NPS5555_X6Y4", "port3_out", "NOC_NCRB_X1Y0", @@ -48474,65 +49059,201 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 113 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X5Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X10Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS5555_X6Y3", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", "port2_in", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NPS6_X2Y0", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS6_X2Y0", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA0_in", - "NOC_NPS4_X2Y0", - "portSideB3_out", - "HBM_MC_X5Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -48542,66 +49263,42 @@ "NOC_NPS5555_X6Y4", "port3_in", "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", "port5_out", - "NOC_NPS4_X2Y0", + "NOC_NPS4_X5Y0", "portSideA1_in", - "NOC_NPS4_X2Y0", - "portSideB3_out", - "HBM_MC_X5Y0", - "pc1_port0_in" + "NOC_NPS4_X5Y0", + "portSideB0_out", + "HBM_MC_X10Y0", + "pc0_port0_in" ], - "RequiredBW": 264, - "AchievedBW": 264, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X5Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB3_in", - "NOC_NPS4_X2Y0", - "portSideA1_out", - "NOC_NPS6_X2Y1", - "port5_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", - "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 + "AchievedLatency": 113 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", "ToLocked": false, "Port": "PORT0", "ReadTC": "BE", @@ -48614,190 +49311,270 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X1Y0", - "pc0_port0_out", - "NOC_NPS4_X0Y0", - "portSideB2_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", "port2_in", - "NOC_NPS_VNOC_X1Y36", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS_VNOC_X1Y31", "port2_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB2_out", - "HBM_MC_X1Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", + "port0_out", "NOC_NCRB_X1Y1", - "port1_in", + "port0_in", "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS6_X1Y2", + "NOC_NPS5555_X6Y4", "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X6Y4", "port1_out", - "NOC_NPS6_X0Y2", + "NOC_NPS6_X2Y1", "port3_in", - "NOC_NPS6_X0Y2", + "NOC_NPS6_X2Y1", "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", + "NOC_NPS4_X2Y0", + "portSideA1_in", + "NOC_NPS4_X2Y0", "portSideB2_out", - "HBM_MC_X1Y0", + "HBM_MC_X5Y0", "pc0_port0_in" ], "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 31 + "AchievedLatency": 107 }, { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X1Y0", + "HBM_MC_X5Y0", "pc0_port0_out", - "NOC_NPS4_X0Y0", + "NOC_NPS4_X2Y0", "portSideB2_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", + "NOC_NPS4_X2Y0", + "portSideA1_out", + "NOC_NPS6_X2Y1", "port5_in", - "NOC_NPS6_X0Y2", + "NOC_NPS6_X2Y1", "port3_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X6Y4", "port1_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", "port2_out", - "NOC_NPS6_X1Y2", + "NOC_NPS_VNOC_X1Y35", "port0_in", - "NOC_NPS6_X1Y2", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", "port3_out", - "NOC_NPS6_X2Y2", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X5Y0", + "pc0_port0_out", + "NOC_NPS4_X2Y0", + "portSideB2_in", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port5_in", "NOC_NPS6_X2Y2", "port3_out", "NOC_NPS5555_X6Y6", @@ -48815,245 +49592,240 @@ "NOC_NPS_VNOC_X1Y37", "port1_in", "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X1Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB3_in", - "NOC_NPS4_X0Y0", - "portSideA0_out", - "NOC_NPS6_X0Y0", - "port5_in", - "NOC_NPS6_X0Y0", - "port3_out", - "NOC_NPS5555_X5Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", "port0_in", - "NOC_NPS5555_X5Y3", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", "port1_out", - "NOC_NPS6_X1Y0", + "NOC_NIDB_X1Y6", "port0_in", - "NOC_NPS6_X1Y0", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", "port3_out", - "NOC_NPS6_X2Y0", + "NOC_NPS_VNOC_X1Y25", "port0_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", "port0_in", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y23", "port2_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y21", "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 31 + "AchievedLatency": 109 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X1Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X5Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", - "port0_out", - "NOC_NPS6_X1Y0", - "port3_in", - "NOC_NPS6_X1Y0", - "port0_out", - "NOC_NPS5555_X5Y3", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", "port1_in", - "NOC_NPS5555_X5Y3", - "port0_out", - "NOC_NPS6_X0Y0", - "port3_in", - "NOC_NPS6_X0Y0", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA0_in", - "NOC_NPS4_X0Y0", - "portSideB3_out", - "HBM_MC_X1Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NIDB_X1Y1", "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", "port0_out", - "NOC_NPS6_X1Y1", + "NOC_NPS7575_X5Y2", "port3_in", - "NOC_NPS6_X1Y1", - "port0_out", - "NOC_NPS5555_X5Y4", - "port2_in", - "NOC_NPS5555_X5Y4", + "NOC_NPS7575_X5Y2", "port1_out", - "NOC_NPS6_X0Y1", - "port3_in", - "NOC_NPS6_X0Y1", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA1_in", - "NOC_NPS4_X0Y0", - "portSideB3_out", - "HBM_MC_X1Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X1Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB3_in", - "NOC_NPS4_X0Y0", - "portSideA1_out", - "NOC_NPS6_X0Y1", - "port5_in", - "NOC_NPS6_X0Y1", - "port3_out", - "NOC_NPS5555_X5Y4", - "port1_in", - "NOC_NPS5555_X5Y4", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", "port2_out", - "NOC_NPS6_X1Y1", + "NOC_NPS_VNOC_X1Y16", "port0_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", "port1_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y4", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X1Y5", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", + "portSideB2_out", + "HBM_MC_X5Y0", + "pc0_port0_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 29 + "AchievedLatency": 109 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", "ToLocked": false, - "Port": "PORT0", + "Port": "PORT2", "ReadTC": "BE", "WriteTC": "BE", "ReadBW": 132, @@ -49064,90 +49836,106 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X6Y0", - "pc0_port0_out", - "NOC_NPS4_X3Y0", - "portSideB0_in", - "NOC_NPS4_X3Y0", - "portSideA1_out", - "NOC_NPS6_X3Y1", - "port5_in", - "NOC_NPS6_X3Y1", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y11", "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NPS6_X3Y1", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA1_in", - "NOC_NPS4_X3Y0", - "portSideB0_out", - "HBM_MC_X6Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -49161,90 +49949,65 @@ "NOC_NPS6_X3Y1", "port0_in", "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", "port5_out", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X7Y0", "portSideA1_in", - "NOC_NPS4_X3Y0", - "portSideB0_out", - "HBM_MC_X6Y0", - "pc0_port0_in" + "NOC_NPS4_X7Y0", + "portSideB3_out", + "HBM_MC_X15Y0", + "pc1_port0_in" ], "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 23 + "AchievedLatency": 119 }, { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X6Y0", - "pc0_port0_out", - "NOC_NPS4_X3Y0", - "portSideB0_in", - "NOC_NPS4_X3Y0", + "HBM_MC_X15Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB3_in", + "NOC_NPS4_X7Y0", "portSideA1_out", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X7Y1", "port5_in", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X7Y1", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X8Y4", "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X12Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB0_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", + "NOC_NPS5555_X8Y4", + "port1_out", "NOC_NPS6_X6Y1", - "port5_in", + "port3_in", "NOC_NPS6_X6Y1", "port0_out", "NOC_NPS6_X5Y1", @@ -49274,137 +50037,125 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y35", "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y35", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y33", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y31", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y29", "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB0_out", - "HBM_MC_X12Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y7", "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", "port2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS_VNOC_X1Y23", "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", "port0_in", - "NOC_NPS6_X4Y2", - "port3_out", - "NOC_NPS5555_X7Y6", - "port1_in", - "NOC_NPS5555_X7Y6", + "NOC_NPS_VNOC_X1Y21", "port2_out", - "NOC_NPS6_X5Y2", + "NOC_NPS_VNOC_X1Y19", "port0_in", - "NOC_NPS6_X5Y2", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", "port3_out", - "NOC_NPS6_X6Y2", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NPS6_X6Y2", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA2_in", - "NOC_NPS4_X6Y0", - "portSideB0_out", - "HBM_MC_X12Y0", - "pc0_port0_in" + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" ], - "RequiredBW": 264, - "AchievedBW": 264, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 33 + "AchievedLatency": 119 }, { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", "Connections": [ - "HBM_MC_X12Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB0_in", - "NOC_NPS4_X6Y0", + "HBM_MC_X15Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB3_in", + "NOC_NPS4_X7Y0", "portSideA2_out", - "NOC_NPS6_X6Y2", + "NOC_NPS6_X7Y2", "port5_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", "NOC_NPS6_X6Y2", "port0_out", "NOC_NPS6_X5Y2", @@ -49438,243 +50189,262 @@ "NOC_NPS_VNOC_X1Y37", "port1_in", "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 33 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X0Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB1_in", - "NOC_NPS4_X0Y0", - "portSideA1_out", - "NOC_NPS6_X0Y1", - "port5_in", - "NOC_NPS6_X0Y1", - "port3_out", - "NOC_NPS5555_X5Y4", - "port1_in", - "NOC_NPS5555_X5Y4", "port2_out", - "NOC_NPS6_X1Y1", + "NOC_NPS_VNOC_X1Y35", "port0_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", "port1_in", - "NOC_NPS5555_X6Y4", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y25", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 29 + "AchievedLatency": 121 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X0Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X15Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", "port0_out", - "NOC_NPS6_X1Y1", + "NOC_NPS7575_X5Y2", "port3_in", - "NOC_NPS6_X1Y1", - "port0_out", - "NOC_NPS5555_X5Y4", - "port2_in", - "NOC_NPS5555_X5Y4", + "NOC_NPS7575_X5Y2", "port1_out", - "NOC_NPS6_X0Y1", - "port3_in", - "NOC_NPS6_X0Y1", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA1_in", - "NOC_NPS4_X0Y0", - "portSideB1_out", - "HBM_MC_X0Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y14", "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", - "port0_out", - "NOC_NPS6_X1Y0", - "port3_in", - "NOC_NPS6_X1Y0", - "port0_out", - "NOC_NPS5555_X5Y3", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", "port1_in", - "NOC_NPS5555_X5Y3", + "NOC_NIDB_X1Y7", "port0_out", - "NOC_NPS6_X0Y0", + "NOC_NPS7575_X5Y6", "port3_in", - "NOC_NPS6_X0Y0", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA0_in", - "NOC_NPS4_X0Y0", - "portSideB1_out", - "HBM_MC_X0Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X0Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB1_in", - "NOC_NPS4_X0Y0", - "portSideA0_out", - "NOC_NPS6_X0Y0", - "port5_in", - "NOC_NPS6_X0Y0", - "port3_out", - "NOC_NPS5555_X5Y3", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", "port0_in", - "NOC_NPS5555_X5Y3", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", "port1_out", - "NOC_NPS6_X1Y0", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", "port0_in", - "NOC_NPS6_X1Y0", + "NOC_NPS6_X3Y2", "port3_out", - "NOC_NPS6_X2Y0", + "NOC_NPS6_X4Y2", "port0_in", - "NOC_NPS6_X2Y0", + "NOC_NPS6_X4Y2", "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", + "NOC_NPS5555_X7Y6", + "port1_in", + "NOC_NPS5555_X7Y6", "port2_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS6_X5Y2", "port0_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS6_X5Y2", "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS6_X6Y2", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS6_X6Y2", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA2_in", + "NOC_NPS4_X7Y0", + "portSideB3_out", + "HBM_MC_X15Y0", + "pc1_port0_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 31 + "AchievedLatency": 121 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", "ToLocked": false, "Port": "PORT2", "ReadTC": "BE", @@ -49687,54 +50457,8921 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X6Y0", - "pc1_port0_out", - "NOC_NPS4_X3Y0", - "portSideB1_in", - "NOC_NPS4_X3Y0", - "portSideA1_out", - "NOC_NPS6_X3Y1", - "port5_in", - "NOC_NPS6_X3Y1", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y11", "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA1_in", + "NOC_NPS4_X2Y0", + "portSideB3_out", + "HBM_MC_X5Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X5Y0", + "pc1_port0_out", + "NOC_NPS4_X2Y0", + "portSideB3_in", + "NOC_NPS4_X2Y0", + "portSideA1_out", + "NOC_NPS6_X2Y1", + "port5_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X5Y0", + "pc1_port0_out", + "NOC_NPS4_X2Y0", + "portSideB3_in", + "NOC_NPS4_X2Y0", + "portSideA0_out", + "NOC_NPS6_X2Y0", + "port5_in", + "NOC_NPS6_X2Y0", + "port3_out", + "NOC_NPS5555_X6Y3", + "port0_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port0_out", + "NOC_NPS6_X2Y0", + "port3_in", + "NOC_NPS6_X2Y0", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA0_in", + "NOC_NPS4_X2Y0", + "portSideB3_out", + "HBM_MC_X5Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB2_out", + "HBM_MC_X1Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X1Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB2_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port0_out", + "NOC_NPS_VNOC_X1Y34", + "port2_in", + "NOC_NPS_VNOC_X1Y34", + "port0_out", + "NOC_NPS_VNOC_X1Y32", + "port2_in", + "NOC_NPS_VNOC_X1Y32", + "port0_out", + "NOC_NPS_VNOC_X1Y30", + "port2_in", + "NOC_NPS_VNOC_X1Y30", + "port0_out", + "NOC_NPS_VNOC_X1Y28", + "port2_in", + "NOC_NPS_VNOC_X1Y28", + "port0_out", + "NOC_NPS_VNOC_X1Y26", + "port2_in", + "NOC_NPS_VNOC_X1Y26", + "port0_out", + "NOC_NPS7575_X5Y6", + "port1_in", + "NOC_NPS7575_X5Y6", + "port3_out", + "NOC_NIDB_X1Y7", + "port0_in", + "NOC_NIDB_X1Y7", + "port1_out", + "NOC_NIDB_X1Y5", + "port1_in", + "NOC_NIDB_X1Y5", + "port0_out", + "NOC_NPS7575_X5Y4", + "port3_in", + "NOC_NPS7575_X5Y4", + "port1_out", + "NOC_NPS_VNOC_X1Y24", + "port2_in", + "NOC_NPS_VNOC_X1Y24", + "port0_out", + "NOC_NPS_VNOC_X1Y22", + "port2_in", + "NOC_NPS_VNOC_X1Y22", + "port0_out", + "NOC_NPS_VNOC_X1Y20", + "port2_in", + "NOC_NPS_VNOC_X1Y20", + "port0_out", + "NOC_NPS_VNOC_X1Y18", + "port2_in", + "NOC_NPS_VNOC_X1Y18", + "port0_out", + "NOC_NPS_VNOC_X1Y16", + "port2_in", + "NOC_NPS_VNOC_X1Y16", + "port0_out", + "NOC_NPS_VNOC_X1Y14", + "port2_in", + "NOC_NPS_VNOC_X1Y14", + "port0_out", + "NOC_NPS7575_X5Y2", + "port1_in", + "NOC_NPS7575_X5Y2", + "port3_out", + "NOC_NIDB_X1Y3", + "port0_in", + "NOC_NIDB_X1Y3", + "port1_out", + "NOC_NIDB_X1Y1", + "port1_in", + "NOC_NIDB_X1Y1", + "port0_out", + "NOC_NPS7575_X5Y0", + "port3_in", + "NOC_NPS7575_X5Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y12", + "port2_in", + "NOC_NPS_VNOC_X1Y12", + "port0_out", + "NOC_NPS_VNOC_X1Y10", + "port2_in", + "NOC_NPS_VNOC_X1Y10", + "port0_out", + "NOC_NPS_VNOC_X1Y8", + "port2_in", + "NOC_NPS_VNOC_X1Y8", + "port1_out", + "NOC_NPS_VNOC_X1Y9", + "port1_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X1Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB2_in", + "NOC_NPS4_X0Y0", + "portSideA1_out", + "NOC_NPS6_X0Y1", + "port5_in", + "NOC_NPS6_X0Y1", + "port3_out", + "NOC_NPS5555_X5Y4", + "port1_in", + "NOC_NPS5555_X5Y4", + "port2_out", + "NOC_NPS6_X1Y1", + "port0_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port0_out", + "NOC_NPS5555_X5Y4", + "port2_in", + "NOC_NPS5555_X5Y4", + "port1_out", + "NOC_NPS6_X0Y1", + "port3_in", + "NOC_NPS6_X0Y1", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA1_in", + "NOC_NPS4_X0Y0", + "portSideB2_out", + "HBM_MC_X1Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB3_out", + "HBM_MC_X1Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X1Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB3_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port0_out", + "NOC_NPS_VNOC_X1Y34", + "port2_in", + "NOC_NPS_VNOC_X1Y34", + "port0_out", + "NOC_NPS_VNOC_X1Y32", + "port2_in", + "NOC_NPS_VNOC_X1Y32", + "port0_out", + "NOC_NPS_VNOC_X1Y30", + "port2_in", + "NOC_NPS_VNOC_X1Y30", + "port0_out", + "NOC_NPS_VNOC_X1Y28", + "port2_in", + "NOC_NPS_VNOC_X1Y28", + "port0_out", + "NOC_NPS_VNOC_X1Y26", + "port2_in", + "NOC_NPS_VNOC_X1Y26", + "port0_out", + "NOC_NPS7575_X5Y6", + "port1_in", + "NOC_NPS7575_X5Y6", + "port3_out", + "NOC_NIDB_X1Y7", + "port0_in", + "NOC_NIDB_X1Y7", + "port1_out", + "NOC_NIDB_X1Y5", + "port1_in", + "NOC_NIDB_X1Y5", + "port0_out", + "NOC_NPS7575_X5Y4", + "port3_in", + "NOC_NPS7575_X5Y4", + "port1_out", + "NOC_NPS_VNOC_X1Y24", + "port2_in", + "NOC_NPS_VNOC_X1Y24", + "port0_out", + "NOC_NPS_VNOC_X1Y22", + "port2_in", + "NOC_NPS_VNOC_X1Y22", + "port0_out", + "NOC_NPS_VNOC_X1Y20", + "port2_in", + "NOC_NPS_VNOC_X1Y20", + "port0_out", + "NOC_NPS_VNOC_X1Y18", + "port2_in", + "NOC_NPS_VNOC_X1Y18", + "port0_out", + "NOC_NPS_VNOC_X1Y16", + "port2_in", + "NOC_NPS_VNOC_X1Y16", + "port0_out", + "NOC_NPS_VNOC_X1Y14", + "port2_in", + "NOC_NPS_VNOC_X1Y14", + "port0_out", + "NOC_NPS7575_X5Y2", + "port1_in", + "NOC_NPS7575_X5Y2", + "port3_out", + "NOC_NIDB_X1Y3", + "port0_in", + "NOC_NIDB_X1Y3", + "port1_out", + "NOC_NIDB_X1Y1", + "port1_in", + "NOC_NIDB_X1Y1", + "port0_out", + "NOC_NPS7575_X5Y0", + "port3_in", + "NOC_NPS7575_X5Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y12", + "port2_in", + "NOC_NPS_VNOC_X1Y12", + "port0_out", + "NOC_NPS_VNOC_X1Y10", + "port2_in", + "NOC_NPS_VNOC_X1Y10", + "port0_out", + "NOC_NPS_VNOC_X1Y8", + "port2_in", + "NOC_NPS_VNOC_X1Y8", + "port1_out", + "NOC_NPS_VNOC_X1Y9", + "port1_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X1Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB3_in", + "NOC_NPS4_X0Y0", + "portSideA1_out", + "NOC_NPS6_X0Y1", + "port5_in", + "NOC_NPS6_X0Y1", + "port3_out", + "NOC_NPS5555_X5Y4", + "port1_in", + "NOC_NPS5555_X5Y4", + "port2_out", + "NOC_NPS6_X1Y1", + "port0_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port0_out", + "NOC_NPS5555_X5Y4", + "port2_in", + "NOC_NPS5555_X5Y4", + "port1_out", + "NOC_NPS6_X0Y1", + "port3_in", + "NOC_NPS6_X0Y1", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA1_in", + "NOC_NPS4_X0Y0", + "portSideB3_out", + "HBM_MC_X1Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA1_in", + "NOC_NPS4_X3Y0", + "portSideB0_out", + "HBM_MC_X6Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X6Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB0_in", + "NOC_NPS4_X3Y0", + "portSideA1_out", + "NOC_NPS6_X3Y1", + "port5_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X6Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB0_in", + "NOC_NPS4_X3Y0", + "portSideA1_out", + "NOC_NPS6_X3Y1", + "port5_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA1_in", + "NOC_NPS4_X3Y0", + "portSideB0_out", + "HBM_MC_X6Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA1_in", + "NOC_NPS4_X6Y0", + "portSideB0_out", + "HBM_MC_X12Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X12Y0", + "pc0_port0_out", + "NOC_NPS4_X6Y0", + "portSideB0_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X12Y0", + "pc0_port0_out", + "NOC_NPS4_X6Y0", + "portSideB0_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA1_in", + "NOC_NPS4_X6Y0", + "portSideB0_out", + "HBM_MC_X12Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port0_out", + "NOC_NPS5555_X5Y4", + "port2_in", + "NOC_NPS5555_X5Y4", + "port1_out", + "NOC_NPS6_X0Y1", + "port3_in", + "NOC_NPS6_X0Y1", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA1_in", + "NOC_NPS4_X0Y0", + "portSideB1_out", + "HBM_MC_X0Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X0Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB1_in", + "NOC_NPS4_X0Y0", + "portSideA1_out", + "NOC_NPS6_X0Y1", + "port5_in", + "NOC_NPS6_X0Y1", + "port3_out", + "NOC_NPS5555_X5Y4", + "port1_in", + "NOC_NPS5555_X5Y4", + "port2_out", + "NOC_NPS6_X1Y1", + "port0_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X0Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB1_in", + "NOC_NPS4_X0Y0", + "portSideA1_out", + "NOC_NPS6_X0Y1", + "port5_in", + "NOC_NPS6_X0Y1", + "port3_out", + "NOC_NPS5555_X5Y4", + "port1_in", + "NOC_NPS5555_X5Y4", + "port2_out", + "NOC_NPS6_X1Y1", + "port0_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port0_out", + "NOC_NPS5555_X5Y4", + "port2_in", + "NOC_NPS5555_X5Y4", + "port1_out", + "NOC_NPS6_X0Y1", + "port3_in", + "NOC_NPS6_X0Y1", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA1_in", + "NOC_NPS4_X0Y0", + "portSideB1_out", + "HBM_MC_X0Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA1_in", + "NOC_NPS4_X3Y0", + "portSideB1_out", + "HBM_MC_X6Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X6Y0", + "pc1_port0_out", + "NOC_NPS4_X3Y0", + "portSideB1_in", + "NOC_NPS4_X3Y0", + "portSideA1_out", + "NOC_NPS6_X3Y1", + "port5_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X6Y0", + "pc1_port0_out", + "NOC_NPS4_X3Y0", + "portSideB1_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB1_out", + "HBM_MC_X6Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA1_in", + "NOC_NPS4_X7Y0", + "portSideB1_out", + "HBM_MC_X14Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 119 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X14Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB1_in", + "NOC_NPS4_X7Y0", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port5_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 119 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X14Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB1_in", + "NOC_NPS4_X7Y0", + "portSideA2_out", + "NOC_NPS6_X7Y2", + "port5_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port1_out", + "NOC_NPS6_X4Y2", + "port3_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 121 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port3_out", + "NOC_NPS5555_X7Y6", + "port1_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA2_in", + "NOC_NPS4_X7Y0", + "portSideB1_out", + "HBM_MC_X14Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 121 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port0_out", + "NOC_NPS5555_X7Y3", + "port2_in", + "NOC_NPS5555_X7Y3", + "port1_out", + "NOC_NPS6_X5Y0", + "port0_in", + "NOC_NPS6_X5Y0", + "port3_out", + "NOC_NPS6_X6Y0", + "port0_in", + "NOC_NPS6_X6Y0", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA0_in", + "NOC_NPS4_X6Y0", + "portSideB1_out", + "HBM_MC_X12Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 117 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X12Y0", + "pc1_port0_out", + "NOC_NPS4_X6Y0", + "portSideB1_in", + "NOC_NPS4_X6Y0", + "portSideA0_out", + "NOC_NPS6_X6Y0", + "port5_in", + "NOC_NPS6_X6Y0", + "port0_out", + "NOC_NPS6_X5Y0", + "port3_in", + "NOC_NPS6_X5Y0", + "port0_out", + "NOC_NPS5555_X7Y3", + "port1_in", + "NOC_NPS5555_X7Y3", + "port2_out", + "NOC_NPS5555_X7Y4", + "port0_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 117 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X12Y0", + "pc1_port0_out", + "NOC_NPS4_X6Y0", + "portSideB1_in", + "NOC_NPS4_X6Y0", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port5_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port1_out", + "NOC_NPS6_X4Y2", + "port3_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 117 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port3_out", + "NOC_NPS5555_X7Y6", + "port1_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA2_in", + "NOC_NPS4_X6Y0", + "portSideB1_out", + "HBM_MC_X12Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 117 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port0_out", + "NOC_NPS5555_X5Y4", + "port2_in", + "NOC_NPS5555_X5Y4", + "port1_out", + "NOC_NPS6_X0Y1", + "port3_in", + "NOC_NPS6_X0Y1", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA1_in", + "NOC_NPS4_X0Y0", + "portSideB0_out", + "HBM_MC_X0Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X0Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB0_in", + "NOC_NPS4_X0Y0", + "portSideA1_out", + "NOC_NPS6_X0Y1", + "port5_in", + "NOC_NPS6_X0Y1", + "port3_out", + "NOC_NPS5555_X5Y4", + "port1_in", + "NOC_NPS5555_X5Y4", + "port2_out", + "NOC_NPS6_X1Y1", + "port0_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X0Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB0_in", + "NOC_NPS4_X0Y0", + "portSideA1_out", + "NOC_NPS6_X0Y1", + "port5_in", + "NOC_NPS6_X0Y1", + "port3_out", + "NOC_NPS5555_X5Y4", + "port1_in", + "NOC_NPS5555_X5Y4", + "port2_out", + "NOC_NPS6_X1Y1", + "port0_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port0_out", + "NOC_NPS5555_X5Y4", + "port2_in", + "NOC_NPS5555_X5Y4", + "port1_out", + "NOC_NPS6_X0Y1", + "port3_in", + "NOC_NPS6_X0Y1", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA1_in", + "NOC_NPS4_X0Y0", + "portSideB0_out", + "HBM_MC_X0Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port1_out", + "NOC_NPS6_X3Y0", + "port0_in", + "NOC_NPS6_X3Y0", + "port3_out", + "NOC_NPS6_X4Y0", + "port0_in", + "NOC_NPS6_X4Y0", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA0_in", + "NOC_NPS4_X4Y0", + "portSideB0_out", + "HBM_MC_X8Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X8Y0", + "pc0_port0_out", + "NOC_NPS4_X4Y0", + "portSideB0_in", + "NOC_NPS4_X4Y0", + "portSideA0_out", + "NOC_NPS6_X4Y0", + "port5_in", + "NOC_NPS6_X4Y0", + "port0_out", + "NOC_NPS6_X3Y0", + "port3_in", + "NOC_NPS6_X3Y0", + "port0_out", + "NOC_NPS5555_X6Y3", + "port1_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X8Y0", + "pc0_port0_out", + "NOC_NPS4_X4Y0", + "portSideB0_in", + "NOC_NPS4_X4Y0", + "portSideA0_out", + "NOC_NPS6_X4Y0", + "port5_in", + "NOC_NPS6_X4Y0", + "port0_out", + "NOC_NPS6_X3Y0", + "port3_in", + "NOC_NPS6_X3Y0", + "port0_out", + "NOC_NPS5555_X6Y3", + "port1_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port1_out", + "NOC_NPS6_X3Y0", + "port0_in", + "NOC_NPS6_X3Y0", + "port3_out", + "NOC_NPS6_X4Y0", + "port0_in", + "NOC_NPS6_X4Y0", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA0_in", + "NOC_NPS4_X4Y0", + "portSideB0_out", + "HBM_MC_X8Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA1_in", + "NOC_NPS4_X4Y0", + "portSideB1_out", + "HBM_MC_X8Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X8Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB1_in", + "NOC_NPS4_X4Y0", + "portSideA1_out", + "NOC_NPS6_X4Y1", + "port5_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X8Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB1_in", + "NOC_NPS4_X4Y0", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port5_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA2_in", + "NOC_NPS4_X4Y0", + "portSideB1_out", + "HBM_MC_X8Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA1_in", + "NOC_NPS4_X7Y0", + "portSideB0_out", + "HBM_MC_X14Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 119 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X14Y0", + "pc0_port0_out", + "NOC_NPS4_X7Y0", + "portSideB0_in", + "NOC_NPS4_X7Y0", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port5_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 119 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X14Y0", + "pc0_port0_out", + "NOC_NPS4_X7Y0", + "portSideB0_in", + "NOC_NPS4_X7Y0", + "portSideA2_out", + "NOC_NPS6_X7Y2", + "port5_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port1_out", + "NOC_NPS6_X4Y2", + "port3_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 121 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port3_out", + "NOC_NPS5555_X7Y6", + "port1_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA2_in", + "NOC_NPS4_X7Y0", + "portSideB0_out", + "HBM_MC_X14Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 121 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA1_in", + "NOC_NPS4_X1Y0", + "portSideB2_out", + "HBM_MC_X3Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X3Y0", + "pc0_port0_out", + "NOC_NPS4_X1Y0", + "portSideB2_in", + "NOC_NPS4_X1Y0", + "portSideA1_out", + "NOC_NPS6_X1Y1", + "port5_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X3Y0", + "pc0_port0_out", + "NOC_NPS4_X1Y0", + "portSideB2_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB2_out", + "HBM_MC_X3Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA1_in", + "NOC_NPS4_X1Y0", + "portSideB3_out", + "HBM_MC_X3Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X3Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB3_in", + "NOC_NPS4_X1Y0", + "portSideA1_out", + "NOC_NPS6_X1Y1", + "port5_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X3Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB3_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB3_out", + "HBM_MC_X3Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port0_out", + "NOC_NPS6_X2Y0", + "port3_in", + "NOC_NPS6_X2Y0", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA0_in", + "NOC_NPS4_X2Y0", + "portSideB1_out", + "HBM_MC_X4Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X4Y0", + "pc1_port0_out", + "NOC_NPS4_X2Y0", + "portSideB1_in", + "NOC_NPS4_X2Y0", + "portSideA0_out", + "NOC_NPS6_X2Y0", + "port5_in", + "NOC_NPS6_X2Y0", + "port3_out", + "NOC_NPS5555_X6Y3", + "port0_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X4Y0", + "pc1_port0_out", + "NOC_NPS4_X2Y0", + "portSideB1_in", + "NOC_NPS4_X2Y0", + "portSideA1_out", + "NOC_NPS6_X2Y1", + "port5_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X6Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X4Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -49744,33 +59381,142 @@ "NOC_NPS5555_X6Y4", "port3_in", "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", "port5_out", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X2Y0", "portSideA1_in", - "NOC_NPS4_X3Y0", + "NOC_NPS4_X2Y0", "portSideB1_out", - "HBM_MC_X6Y0", + "HBM_MC_X4Y0", "pc1_port0_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 23 - }, + "AchievedLatency": 107 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X6Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X4Y0", "VC": 5, "CommType": "WRITE", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -49780,49 +59526,41 @@ "NOC_NPS5555_X6Y4", "port3_in", "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", "port1_out", - "NOC_NPS6_X3Y0", - "port0_in", - "NOC_NPS6_X3Y0", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", "port5_out", - "NOC_NPS4_X3Y0", - "portSideA0_in", - "NOC_NPS4_X3Y0", - "portSideB1_out", - "HBM_MC_X6Y0", - "pc1_port0_in" + "NOC_NPS4_X2Y0", + "portSideA1_in", + "NOC_NPS4_X2Y0", + "portSideB0_out", + "HBM_MC_X4Y0", + "pc0_port0_in" ], "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 107 }, { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X6Y0", - "pc1_port0_out", - "NOC_NPS4_X3Y0", - "portSideB1_in", - "NOC_NPS4_X3Y0", - "portSideA0_out", - "NOC_NPS6_X3Y0", + "HBM_MC_X4Y0", + "pc0_port0_out", + "NOC_NPS4_X2Y0", + "portSideB0_in", + "NOC_NPS4_X2Y0", + "portSideA1_out", + "NOC_NPS6_X2Y1", "port5_in", - "NOC_NPS6_X3Y0", - "port0_out", - "NOC_NPS5555_X6Y3", - "port1_in", - "NOC_NPS5555_X6Y3", - "port2_out", + "NOC_NPS6_X2Y1", + "port3_out", "NOC_NPS5555_X6Y4", - "port0_in", + "port1_in", "NOC_NPS5555_X6Y4", "port3_out", "NOC_NCRB_X1Y0", @@ -49832,293 +59570,368 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 107 + }, { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 6, "CommType": "READ", "Connections": [ - "HBM_MC_X14Y0", - "pc1_port0_out", - "NOC_NPS4_X7Y0", - "portSideB1_in", - "NOC_NPS4_X7Y0", - "portSideA1_out", - "NOC_NPS6_X7Y1", + "HBM_MC_X4Y0", + "pc0_port0_out", + "NOC_NPS4_X2Y0", + "portSideB0_in", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", "port5_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", "port2_in", - "NOC_NPS5555_X8Y4", + "NOC_NPS_VNOC_X1Y36", "port1_out", - "NOC_NPS6_X6Y1", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", "port3_in", - "NOC_NPS6_X6Y1", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS7575_X5Y3", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 35 + "AchievedLatency": 109 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X14Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X4Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y10", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y10", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y12", "port0_in", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NIDB_X1Y1", "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", "port1_in", - "NOC_NPS5555_X8Y4", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", "port2_out", - "NOC_NPS6_X7Y1", + "NOC_NPS_VNOC_X1Y16", "port0_in", - "NOC_NPS6_X7Y1", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA1_in", - "NOC_NPS4_X7Y0", - "portSideB1_out", - "HBM_MC_X14Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 35 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y18", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y20", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y22", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y24", "port0_in", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NIDB_X1Y5", "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", "port1_in", - "NOC_NPS5555_X8Y4", + "NOC_NIDB_X1Y7", "port0_out", - "NOC_NPS5555_X8Y3", - "port2_in", - "NOC_NPS5555_X8Y3", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", "port1_out", - "NOC_NPS6_X7Y0", + "NOC_NPS_VNOC_X1Y26", "port0_in", - "NOC_NPS6_X7Y0", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA0_in", - "NOC_NPS4_X7Y0", - "portSideB1_out", - "HBM_MC_X14Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X14Y0", - "pc1_port0_out", - "NOC_NPS4_X7Y0", - "portSideB1_in", - "NOC_NPS4_X7Y0", - "portSideA0_out", - "NOC_NPS6_X7Y0", - "port5_in", - "NOC_NPS6_X7Y0", - "port0_out", - "NOC_NPS5555_X8Y3", - "port1_in", - "NOC_NPS5555_X8Y3", + "NOC_NPS_VNOC_X1Y26", "port2_out", - "NOC_NPS5555_X8Y4", + "NOC_NPS_VNOC_X1Y28", "port0_in", - "NOC_NPS5555_X8Y4", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NPS5555_X6Y6", "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS5555_X6Y6", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NPS6_X2Y2", "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "NOC_NPS6_X2Y2", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", + "portSideB0_out", + "HBM_MC_X4Y0", + "pc0_port0_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 37 + "AchievedLatency": 109 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", "ToLocked": false, - "Port": "PORT2", + "Port": "PORT0", "ReadTC": "BE", "WriteTC": "BE", "ReadBW": 132, @@ -50129,70 +59942,106 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X12Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB1_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y11", "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -50210,186 +60059,169 @@ "NOC_NPS6_X4Y1", "port0_in", "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", "port5_out", - "NOC_NPS4_X6Y0", + "NOC_NPS4_X4Y0", "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB1_out", - "HBM_MC_X12Y0", - "pc1_port0_in" + "NOC_NPS4_X4Y0", + "portSideB2_out", + "HBM_MC_X9Y0", + "pc0_port0_in" ], - "RequiredBW": 132, - "AchievedBW": 132, + "RequiredBW": 264, + "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 31 + "AchievedLatency": 109 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 5, - "CommType": "WRITE", + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", + "HBM_MC_X9Y0", + "pc0_port0_out", + "NOC_NPS4_X4Y0", + "portSideB2_in", + "NOC_NPS4_X4Y0", + "portSideA1_out", + "NOC_NPS6_X4Y1", + "port5_in", + "NOC_NPS6_X4Y1", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", "port0_out", "NOC_NPS5555_X6Y4", - "port3_in", + "port2_in", "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y35", "port0_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y19", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y17", "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB1_out", - "HBM_MC_X12Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X12Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB1_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS7575_X5Y3", "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 109 + }, { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 6, "CommType": "READ", "Connections": [ - "HBM_MC_X0Y0", + "HBM_MC_X9Y0", "pc0_port0_out", - "NOC_NPS4_X0Y0", - "portSideB0_in", - "NOC_NPS4_X0Y0", + "NOC_NPS4_X4Y0", + "portSideB2_in", + "NOC_NPS4_X4Y0", "portSideA0_out", - "NOC_NPS6_X0Y0", + "NOC_NPS6_X4Y0", "port5_in", - "NOC_NPS6_X0Y0", - "port3_out", - "NOC_NPS5555_X5Y3", - "port0_in", - "NOC_NPS5555_X5Y3", - "port1_out", - "NOC_NPS6_X1Y0", - "port0_in", - "NOC_NPS6_X1Y0", - "port3_out", - "NOC_NPS6_X2Y0", - "port0_in", - "NOC_NPS6_X2Y0", - "port3_out", + "NOC_NPS6_X4Y0", + "port0_out", + "NOC_NPS6_X3Y0", + "port3_in", + "NOC_NPS6_X3Y0", + "port0_out", "NOC_NPS5555_X6Y3", - "port0_in", + "port1_in", "NOC_NPS5555_X6Y3", "port2_out", "NOC_NPS5555_X6Y4", @@ -50403,178 +60235,242 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 31 + "AchievedLatency": 111 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X0Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X9Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS5555_X6Y3", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", "port2_in", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", "port0_out", - "NOC_NPS6_X1Y0", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS6_X1Y0", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", "port0_out", - "NOC_NPS5555_X5Y3", + "NOC_NPS7575_X5Y7", "port1_in", - "NOC_NPS5555_X5Y3", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", "port0_out", - "NOC_NPS6_X0Y0", - "port3_in", - "NOC_NPS6_X0Y0", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA0_in", - "NOC_NPS4_X0Y0", - "portSideB0_out", - "HBM_MC_X0Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", + "port0_out", "NOC_NCRB_X1Y1", - "port1_in", + "port0_in", "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS6_X1Y2", + "NOC_NPS5555_X6Y4", "port3_in", - "NOC_NPS6_X1Y2", + "NOC_NPS5555_X6Y4", "port0_out", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X6Y3", "port2_in", - "NOC_NPS5555_X5Y6", + "NOC_NPS5555_X6Y3", "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB0_out", - "HBM_MC_X0Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X0Y0", - "pc0_port0_out", - "NOC_NPS4_X0Y0", - "portSideB0_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X3Y0", "port0_in", - "NOC_NPS6_X1Y2", + "NOC_NPS6_X3Y0", "port3_out", - "NOC_NPS6_X2Y2", + "NOC_NPS6_X4Y0", "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "NOC_NPS6_X4Y0", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA0_in", + "NOC_NPS4_X4Y0", + "portSideB2_out", + "HBM_MC_X9Y0", + "pc0_port0_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 31 + "AchievedLatency": 111 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", "ToLocked": false, "Port": "PORT0", "ReadTC": "BE", @@ -50587,106 +60483,106 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X8Y0", - "pc0_port0_out", - "NOC_NPS4_X4Y0", - "portSideB0_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS6_X3Y2", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS5555_X6Y6", + "NOC_NPS_VNOC_X1Y11", "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", "port2_in", - "NOC_NPS_VNOC_X1Y36", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", + "NOC_NPS7575_X5Y7", "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB0_out", - "HBM_MC_X8Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -50696,57 +60592,49 @@ "NOC_NPS5555_X6Y4", "port3_in", "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", "port1_out", - "NOC_NPS6_X3Y0", - "port0_in", - "NOC_NPS6_X3Y0", - "port3_out", - "NOC_NPS6_X4Y0", - "port0_in", - "NOC_NPS6_X4Y0", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", "port5_out", - "NOC_NPS4_X4Y0", - "portSideA0_in", - "NOC_NPS4_X4Y0", + "NOC_NPS4_X1Y0", + "portSideA1_in", + "NOC_NPS4_X1Y0", "portSideB0_out", - "HBM_MC_X8Y0", + "HBM_MC_X2Y0", "pc0_port0_in" ], "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 27 + "AchievedLatency": 109 }, { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X8Y0", + "HBM_MC_X2Y0", "pc0_port0_out", - "NOC_NPS4_X4Y0", + "NOC_NPS4_X1Y0", "portSideB0_in", - "NOC_NPS4_X4Y0", - "portSideA0_out", - "NOC_NPS6_X4Y0", + "NOC_NPS4_X1Y0", + "portSideA1_out", + "NOC_NPS6_X1Y1", "port5_in", - "NOC_NPS6_X4Y0", - "port0_out", - "NOC_NPS6_X3Y0", - "port3_in", - "NOC_NPS6_X3Y0", - "port0_out", - "NOC_NPS5555_X6Y3", - "port1_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", "NOC_NPS5555_X6Y4", "port3_out", "NOC_NCRB_X1Y0", @@ -50756,58 +60644,125 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 27 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 109 + }, { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 6, "CommType": "READ", "Connections": [ - "HBM_MC_X8Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB1_in", - "NOC_NPS4_X4Y0", + "HBM_MC_X2Y0", + "pc0_port0_out", + "NOC_NPS4_X1Y0", + "portSideB0_in", + "NOC_NPS4_X1Y0", "portSideA2_out", - "NOC_NPS6_X4Y2", + "NOC_NPS6_X1Y2", "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", "NOC_NPS5555_X6Y6", - "port2_in", + "port1_in", "NOC_NPS5555_X6Y6", "port3_out", "NOC_NCRB_X1Y0", @@ -50821,146 +60776,242 @@ "NOC_NPS_VNOC_X1Y37", "port1_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 27 + "AchievedLatency": 111 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X8Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X2Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NPS_VNOC_X1Y8", "port1_in", - "NOC_NPS_VNOC_X1Y36", + "NOC_NPS_VNOC_X1Y8", "port2_out", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", "port1_in", - "NOC_NCRB_X1Y1", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", "port1_out", - "NOC_NPS5555_X6Y6", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", "port3_in", - "NOC_NPS5555_X6Y6", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", "port2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS_VNOC_X1Y16", "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB1_out", - "HBM_MC_X8Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y20", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y22", "port0_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NIDB_X1Y5", "port0_in", - "NOC_NPS6_X4Y1", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA1_in", - "NOC_NPS4_X4Y0", - "portSideB1_out", - "HBM_MC_X8Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X8Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB1_in", - "NOC_NPS4_X4Y0", - "portSideA1_out", - "NOC_NPS6_X4Y1", - "port5_in", - "NOC_NPS6_X4Y1", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS6_X2Y2", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB0_out", + "HBM_MC_X2Y0", + "pc0_port0_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 111 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", "ToLocked": false, "Port": "PORT0", "ReadTC": "BE", @@ -50973,146 +61024,106 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X14Y0", - "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB0_in", - "NOC_NPS4_X7Y0", - "portSideA2_out", - "NOC_NPS6_X7Y2", - "port5_in", - "NOC_NPS6_X7Y2", - "port0_out", - "NOC_NPS5555_X8Y6", - "port2_in", - "NOC_NPS5555_X8Y6", - "port1_out", - "NOC_NPS6_X6Y2", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS6_X6Y2", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS5555_X7Y6", + "NOC_NPS_VNOC_X1Y13", "port2_in", - "NOC_NPS5555_X7Y6", - "port1_out", - "NOC_NPS6_X4Y2", - "port3_in", - "NOC_NPS6_X4Y2", + "NOC_NPS_VNOC_X1Y13", "port0_out", - "NOC_NPS6_X3Y2", + "NOC_NPS7575_X5Y1", "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", "port1_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NPS6_X4Y2", - "port3_out", - "NOC_NPS5555_X7Y6", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port3_out", - "NOC_NPS6_X6Y2", - "port0_in", - "NOC_NPS6_X6Y2", - "port3_out", - "NOC_NPS5555_X8Y6", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", "port1_in", - "NOC_NPS5555_X8Y6", - "port2_out", - "NOC_NPS6_X7Y2", - "port0_in", - "NOC_NPS6_X7Y2", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA2_in", - "NOC_NPS4_X7Y0", - "portSideB0_out", - "HBM_MC_X14Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -51134,69 +61145,37 @@ "NOC_NPS5555_X7Y4", "port1_in", "NOC_NPS5555_X7Y4", - "port0_out", - "NOC_NPS5555_X7Y3", - "port2_in", - "NOC_NPS5555_X7Y3", - "port1_out", - "NOC_NPS6_X5Y0", - "port0_in", - "NOC_NPS6_X5Y0", - "port3_out", - "NOC_NPS6_X6Y0", - "port0_in", - "NOC_NPS6_X6Y0", - "port3_out", - "NOC_NPS5555_X8Y3", - "port0_in", - "NOC_NPS5555_X8Y3", - "port1_out", - "NOC_NPS6_X7Y0", + "port2_out", + "NOC_NPS6_X5Y1", "port0_in", - "NOC_NPS6_X7Y0", + "NOC_NPS6_X5Y1", "port5_out", - "NOC_NPS4_X7Y0", - "portSideA0_in", - "NOC_NPS4_X7Y0", - "portSideB0_out", - "HBM_MC_X14Y0", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB2_out", + "HBM_MC_X11Y0", "pc0_port0_in" ], "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 37 + "AchievedLatency": 113 }, { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X14Y0", + "HBM_MC_X11Y0", "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB0_in", - "NOC_NPS4_X7Y0", - "portSideA0_out", - "NOC_NPS6_X7Y0", - "port5_in", - "NOC_NPS6_X7Y0", - "port0_out", - "NOC_NPS5555_X8Y3", - "port1_in", - "NOC_NPS5555_X8Y3", - "port2_out", - "NOC_NPS5555_X8Y4", - "port0_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", + "NOC_NPS4_X5Y0", + "portSideB2_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", "NOC_NPS6_X5Y1", - "port3_in", + "port5_in", "NOC_NPS6_X5Y1", "port0_out", "NOC_NPS5555_X7Y4", @@ -51222,62 +61201,133 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 37 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 113 + }, { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 6, "CommType": "READ", "Connections": [ - "HBM_MC_X3Y0", + "HBM_MC_X11Y0", "pc0_port0_out", - "NOC_NPS4_X1Y0", + "NOC_NPS4_X5Y0", "portSideB2_in", - "NOC_NPS4_X1Y0", - "portSideA0_out", - "NOC_NPS6_X1Y0", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", "port5_in", - "NOC_NPS6_X1Y0", - "port3_out", - "NOC_NPS6_X2Y0", - "port0_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", - "port2_out", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", "NOC_NPS5555_X6Y4", - "port0_in", + "port2_in", "NOC_NPS5555_X6Y4", "port3_out", "NOC_NCRB_X1Y0", @@ -51286,70 +61336,202 @@ "port0_out", "NOC_NPS_VNOC_X1Y37", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 27 + "AchievedLatency": 113 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X3Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X11Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS5555_X6Y3", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", "port2_in", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", "port0_out", - "NOC_NPS6_X1Y0", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS6_X1Y0", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA0_in", - "NOC_NPS4_X1Y0", - "portSideB2_out", - "HBM_MC_X3Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -51359,74 +61541,42 @@ "NOC_NPS5555_X6Y4", "port3_in", "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA1_in", - "NOC_NPS4_X1Y0", - "portSideB2_out", - "HBM_MC_X3Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X3Y0", - "pc0_port0_out", - "NOC_NPS4_X1Y0", - "portSideB2_in", - "NOC_NPS4_X1Y0", - "portSideA1_out", - "NOC_NPS6_X1Y1", - "port5_in", - "NOC_NPS6_X1Y1", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", "port3_out", - "NOC_NPS6_X2Y1", + "NOC_NPS6_X4Y1", "port0_in", - "NOC_NPS6_X2Y1", + "NOC_NPS6_X4Y1", "port3_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X7Y4", "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "NOC_NPS6_X5Y1", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB2_out", + "HBM_MC_X11Y0", + "pc0_port0_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 113 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", "ToLocked": false, "Port": "PORT2", "ReadTC": "BE", @@ -51439,98 +61589,106 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X3Y0", - "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB3_in", - "NOC_NPS4_X1Y0", - "portSideA1_out", - "NOC_NPS6_X1Y1", - "port5_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA1_in", - "NOC_NPS4_X1Y0", - "portSideB3_out", - "HBM_MC_X3Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -51540,49 +61698,49 @@ "NOC_NPS5555_X6Y4", "port3_in", "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", "port5_out", - "NOC_NPS4_X1Y0", + "NOC_NPS4_X4Y0", "portSideA1_in", - "NOC_NPS4_X1Y0", + "NOC_NPS4_X4Y0", "portSideB3_out", - "HBM_MC_X3Y0", + "HBM_MC_X9Y0", "pc1_port0_in" ], "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 109 }, { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X3Y0", + "HBM_MC_X9Y0", "pc1_port0_out", - "NOC_NPS4_X1Y0", + "NOC_NPS4_X4Y0", "portSideB3_in", - "NOC_NPS4_X1Y0", + "NOC_NPS4_X4Y0", "portSideA1_out", - "NOC_NPS6_X1Y1", + "NOC_NPS6_X4Y1", "port5_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", - "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", "NOC_NPS5555_X6Y4", - "port1_in", + "port2_in", "NOC_NPS5555_X6Y4", "port3_out", "NOC_NCRB_X1Y0", @@ -51592,162 +61750,129 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X4Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB1_in", - "NOC_NPS4_X2Y0", - "portSideA1_out", - "NOC_NPS6_X2Y1", - "port5_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", "port1_in", - "NOC_NPS5555_X6Y4", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y25", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 23 + "AchievedLatency": 109 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 4, - "CommType": "READ_REQ", + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "HBM_MC_X9Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB3_in", + "NOC_NPS4_X4Y0", + "portSideA0_out", + "NOC_NPS6_X4Y0", + "port5_in", + "NOC_NPS6_X4Y0", "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA1_in", - "NOC_NPS4_X2Y0", - "portSideB1_out", - "HBM_MC_X4Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS6_X3Y0", "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS6_X3Y0", "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA1_in", - "NOC_NPS4_X2Y0", - "portSideB1_out", - "HBM_MC_X4Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X4Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB1_in", - "NOC_NPS4_X2Y0", - "portSideA1_out", - "NOC_NPS6_X2Y1", - "port5_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X6Y3", "port1_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", "NOC_NPS5555_X6Y4", "port3_out", "NOC_NCRB_X1Y0", @@ -51757,126 +61882,201 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X4Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB0_in", - "NOC_NPS4_X2Y0", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port5_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", "port1_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", "port1_in", - "NOC_NCRB_X1Y0", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", "port1_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y0", "port1_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 111 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X4Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X9Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS5555_X6Y6", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB0_out", - "HBM_MC_X4Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -51890,72 +62090,36 @@ "NOC_NPS5555_X6Y3", "port2_in", "NOC_NPS5555_X6Y3", - "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA0_in", - "NOC_NPS4_X2Y0", - "portSideB0_out", - "HBM_MC_X4Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X4Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB0_in", - "NOC_NPS4_X2Y0", - "portSideA0_out", - "NOC_NPS6_X2Y0", - "port5_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X3Y0", "port0_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS6_X3Y0", "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS6_X4Y0", "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "NOC_NPS6_X4Y0", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA0_in", + "NOC_NPS4_X4Y0", + "portSideB3_out", + "HBM_MC_X9Y0", + "pc1_port0_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 111 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", "ToLocked": false, - "Port": "PORT0", + "Port": "PORT2", "ReadTC": "BE", "WriteTC": "BE", "ReadBW": 132, @@ -51966,106 +62130,106 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X9Y0", - "pc0_port0_out", - "NOC_NPS4_X4Y0", - "portSideB2_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS6_X3Y2", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS5555_X6Y6", + "NOC_NPS_VNOC_X1Y11", "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NPS6_X3Y2", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB2_out", - "HBM_MC_X9Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -52083,33 +62247,49 @@ "NOC_NPS6_X4Y1", "port0_in", "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", "port5_out", - "NOC_NPS4_X4Y0", + "NOC_NPS4_X5Y0", "portSideA1_in", - "NOC_NPS4_X4Y0", - "portSideB2_out", - "HBM_MC_X9Y0", - "pc0_port0_in" + "NOC_NPS4_X5Y0", + "portSideB3_out", + "HBM_MC_X11Y0", + "pc1_port0_in" ], "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 113 }, { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X9Y0", - "pc0_port0_out", - "NOC_NPS4_X4Y0", - "portSideB2_in", - "NOC_NPS4_X4Y0", + "HBM_MC_X11Y0", + "pc1_port0_out", + "NOC_NPS4_X5Y0", + "portSideB3_in", + "NOC_NPS4_X5Y0", "portSideA1_out", - "NOC_NPS6_X4Y1", + "NOC_NPS6_X5Y1", "port5_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", "NOC_NPS6_X4Y1", "port0_out", "NOC_NPS6_X3Y1", @@ -52127,58 +62307,133 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 113 + }, { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 6, "CommType": "READ", "Connections": [ - "HBM_MC_X2Y0", - "pc0_port0_out", - "NOC_NPS4_X1Y0", - "portSideB0_in", - "NOC_NPS4_X1Y0", + "HBM_MC_X11Y0", + "pc1_port0_out", + "NOC_NPS4_X5Y0", + "portSideB3_in", + "NOC_NPS4_X5Y0", "portSideA1_out", - "NOC_NPS6_X1Y1", + "NOC_NPS6_X5Y1", "port5_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", - "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", "NOC_NPS5555_X6Y4", - "port1_in", + "port2_in", "NOC_NPS5555_X6Y4", "port3_out", "NOC_NCRB_X1Y0", @@ -52188,222 +62443,201 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 113 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X2Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X11Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA1_in", - "NOC_NPS4_X1Y0", - "portSideB0_out", - "HBM_MC_X2Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", "port0_out", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y21", "port2_in", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y21", "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", "port0_out", - "NOC_NPS6_X1Y0", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS6_X1Y0", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA0_in", - "NOC_NPS4_X1Y0", - "portSideB0_out", - "HBM_MC_X2Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X2Y0", - "pc0_port0_out", - "NOC_NPS4_X1Y0", - "portSideB0_in", - "NOC_NPS4_X1Y0", - "portSideA0_out", - "NOC_NPS6_X1Y0", - "port5_in", - "NOC_NPS6_X1Y0", - "port3_out", - "NOC_NPS6_X2Y0", - "port0_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X11Y0", - "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB2_in", - "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port5_in", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y29", "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y29", "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y33", "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", "port0_out", "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -52433,101 +62667,178 @@ "NOC_NPS4_X5Y0", "portSideA1_in", "NOC_NPS4_X5Y0", - "portSideB2_out", + "portSideB3_out", "HBM_MC_X11Y0", - "pc0_port0_in" + "pc1_port0_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 29 - }, + "AchievedLatency": 113 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X11Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X7Y0", "VC": 5, "CommType": "WRITE", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y13", "port2_in", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NPS6_X3Y0", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NPS6_X3Y0", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NPS6_X4Y0", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NPS6_X4Y0", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", "port3_out", - "NOC_NPS5555_X7Y3", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", "port0_in", - "NOC_NPS5555_X7Y3", - "port1_out", - "NOC_NPS6_X5Y0", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", "port0_in", - "NOC_NPS6_X5Y0", + "NOC_NPS6_X3Y1", "port5_out", - "NOC_NPS4_X5Y0", - "portSideA0_in", - "NOC_NPS4_X5Y0", - "portSideB2_out", - "HBM_MC_X11Y0", - "pc0_port0_in" + "NOC_NPS4_X3Y0", + "portSideA1_in", + "NOC_NPS4_X3Y0", + "portSideB3_out", + "HBM_MC_X7Y0", + "pc1_port0_in" ], "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 31 + "AchievedLatency": 107 }, { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X11Y0", - "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB2_in", - "NOC_NPS4_X5Y0", - "portSideA0_out", - "NOC_NPS6_X5Y0", + "HBM_MC_X7Y0", + "pc1_port0_out", + "NOC_NPS4_X3Y0", + "portSideB3_in", + "NOC_NPS4_X3Y0", + "portSideA1_out", + "NOC_NPS6_X3Y1", "port5_in", - "NOC_NPS6_X5Y0", - "port0_out", - "NOC_NPS5555_X7Y3", - "port1_in", - "NOC_NPS5555_X7Y3", - "port0_out", - "NOC_NPS6_X4Y0", - "port3_in", - "NOC_NPS6_X4Y0", - "port0_out", - "NOC_NPS6_X3Y0", - "port3_in", - "NOC_NPS6_X3Y0", + "NOC_NPS6_X3Y1", "port0_out", - "NOC_NPS5555_X6Y3", - "port1_in", - "NOC_NPS5555_X6Y3", - "port2_out", "NOC_NPS5555_X6Y4", - "port0_in", + "port2_in", "NOC_NPS5555_X6Y4", "port3_out", "NOC_NCRB_X1Y0", @@ -52537,134 +62848,329 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 107 + }, { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 6, "CommType": "READ", "Connections": [ - "HBM_MC_X9Y0", + "HBM_MC_X7Y0", "pc1_port0_out", - "NOC_NPS4_X4Y0", + "NOC_NPS4_X3Y0", "portSideB3_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", + "NOC_NPS4_X3Y0", + "portSideA0_out", + "NOC_NPS6_X3Y0", "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", + "NOC_NPS6_X3Y0", "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", + "NOC_NPS5555_X6Y3", + "port1_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", "port3_out", "NOC_NCRB_X1Y0", - "port1_in", + "port0_in", "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", "port1_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y4", "port1_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 27 + "AchievedLatency": 109 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X9Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X7Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", + "NOC_NPS7575_X5Y7", "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB3_out", - "HBM_MC_X9Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -52682,74 +63188,26 @@ "NOC_NPS6_X3Y0", "port0_in", "NOC_NPS6_X3Y0", - "port3_out", - "NOC_NPS6_X4Y0", - "port0_in", - "NOC_NPS6_X4Y0", "port5_out", - "NOC_NPS4_X4Y0", + "NOC_NPS4_X3Y0", "portSideA0_in", - "NOC_NPS4_X4Y0", + "NOC_NPS4_X3Y0", "portSideB3_out", - "HBM_MC_X9Y0", + "HBM_MC_X7Y0", "pc1_port0_in" ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X9Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB3_in", - "NOC_NPS4_X4Y0", - "portSideA0_out", - "NOC_NPS6_X4Y0", - "port5_in", - "NOC_NPS6_X4Y0", - "port0_out", - "NOC_NPS6_X3Y0", - "port3_in", - "NOC_NPS6_X3Y0", - "port0_out", - "NOC_NPS5555_X6Y3", - "port1_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 27 + "AchievedLatency": 109 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", "ToLocked": false, "Port": "PORT2", "ReadTC": "BE", @@ -52762,114 +63220,106 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X11Y0", - "pc1_port0_out", - "NOC_NPS4_X5Y0", - "portSideB3_in", - "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port5_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y13", "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y13", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB3_out", - "HBM_MC_X11Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -52895,33 +63345,41 @@ "NOC_NPS6_X5Y1", "port0_in", "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", "port5_out", - "NOC_NPS4_X5Y0", + "NOC_NPS4_X6Y0", "portSideA1_in", - "NOC_NPS4_X5Y0", + "NOC_NPS4_X6Y0", "portSideB3_out", - "HBM_MC_X11Y0", + "HBM_MC_X13Y0", "pc1_port0_in" ], "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 29 + "AchievedLatency": 115 }, { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X11Y0", + "HBM_MC_X13Y0", "pc1_port0_out", - "NOC_NPS4_X5Y0", + "NOC_NPS4_X6Y0", "portSideB3_in", - "NOC_NPS4_X5Y0", + "NOC_NPS4_X6Y0", "portSideA1_out", - "NOC_NPS6_X5Y1", + "NOC_NPS6_X6Y1", "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", "NOC_NPS6_X5Y1", "port0_out", "NOC_NPS5555_X7Y4", @@ -52947,204 +63405,106 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X7Y0", - "pc1_port0_out", - "NOC_NPS4_X3Y0", - "portSideB3_in", - "NOC_NPS4_X3Y0", - "portSideA1_out", - "NOC_NPS6_X3Y1", - "port5_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", + "port2_out", + "NOC_NPS_VNOC_X1Y35", "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y31", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y29", "port0_in", - "NOC_NPS6_X3Y1", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA1_in", - "NOC_NPS4_X3Y0", - "portSideB3_out", - "HBM_MC_X7Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y23", "port0_in", - "NOC_NPS6_X3Y1", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA1_in", - "NOC_NPS4_X3Y0", - "portSideB3_out", - "HBM_MC_X7Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X7Y0", - "pc1_port0_out", - "NOC_NPS4_X3Y0", - "portSideB3_in", - "NOC_NPS4_X3Y0", - "portSideA1_out", - "NOC_NPS6_X3Y1", - "port5_in", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 23 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 115 + }, { "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 6, "CommType": "READ", "Connections": [ @@ -53153,21 +63513,17 @@ "NOC_NPS4_X6Y0", "portSideB3_in", "NOC_NPS4_X6Y0", - "portSideA0_out", - "NOC_NPS6_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", "port5_in", - "NOC_NPS6_X6Y0", + "NOC_NPS6_X6Y1", "port0_out", - "NOC_NPS6_X5Y0", + "NOC_NPS6_X5Y1", "port3_in", - "NOC_NPS6_X5Y0", + "NOC_NPS6_X5Y1", "port0_out", - "NOC_NPS5555_X7Y3", - "port1_in", - "NOC_NPS5555_X7Y3", - "port2_out", "NOC_NPS5555_X7Y4", - "port0_in", + "port2_in", "NOC_NPS5555_X7Y4", "port1_out", "NOC_NPS6_X4Y1", @@ -53189,81 +63545,201 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 33 + "AchievedLatency": 115 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "NOC_NMU512_X1Y4", "PhyInstanceEnd": "HBM_MC_X13Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y13", "port2_in", - "NOC_NPS5555_X6Y3", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NPS6_X3Y0", - "port0_in", - "NOC_NPS6_X3Y0", - "port3_out", - "NOC_NPS6_X4Y0", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NPS6_X4Y0", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NPS5555_X7Y3", - "port0_in", - "NOC_NPS5555_X7Y3", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPS6_X5Y0", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NPS6_X5Y0", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", "port3_out", - "NOC_NPS6_X6Y0", - "port0_in", - "NOC_NPS6_X6Y0", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA0_in", - "NOC_NPS4_X6Y0", - "portSideB3_out", - "HBM_MC_X13Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 33 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -53301,87 +63777,291 @@ "HBM_MC_X13Y0", "pc1_port0_in" ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB2_out", + "HBM_MC_X7Y0", + "pc0_port0_in" + ], "RequiredBW": 264, "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 31 + "AchievedLatency": 109 }, { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "HBM_MC_X13Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB3_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", + "HBM_MC_X7Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB2_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", "port5_in", - "NOC_NPS6_X6Y1", + "NOC_NPS6_X3Y2", "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y34", "port2_in", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y34", + "port0_out", + "NOC_NPS_VNOC_X1Y32", + "port2_in", + "NOC_NPS_VNOC_X1Y32", + "port0_out", + "NOC_NPS_VNOC_X1Y30", + "port2_in", + "NOC_NPS_VNOC_X1Y30", + "port0_out", + "NOC_NPS_VNOC_X1Y28", + "port2_in", + "NOC_NPS_VNOC_X1Y28", + "port0_out", + "NOC_NPS_VNOC_X1Y26", + "port2_in", + "NOC_NPS_VNOC_X1Y26", + "port0_out", + "NOC_NPS7575_X5Y6", + "port1_in", + "NOC_NPS7575_X5Y6", + "port3_out", + "NOC_NIDB_X1Y7", + "port0_in", + "NOC_NIDB_X1Y7", "port1_out", - "NOC_NPS6_X4Y1", + "NOC_NIDB_X1Y5", + "port1_in", + "NOC_NIDB_X1Y5", + "port0_out", + "NOC_NPS7575_X5Y4", "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS7575_X5Y4", + "port1_out", + "NOC_NPS_VNOC_X1Y24", + "port2_in", + "NOC_NPS_VNOC_X1Y24", "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y22", + "port2_in", + "NOC_NPS_VNOC_X1Y22", + "port0_out", + "NOC_NPS_VNOC_X1Y20", + "port2_in", + "NOC_NPS_VNOC_X1Y20", + "port0_out", + "NOC_NPS_VNOC_X1Y18", + "port2_in", + "NOC_NPS_VNOC_X1Y18", + "port0_out", + "NOC_NPS_VNOC_X1Y16", + "port2_in", + "NOC_NPS_VNOC_X1Y16", + "port0_out", + "NOC_NPS_VNOC_X1Y14", + "port2_in", + "NOC_NPS_VNOC_X1Y14", + "port0_out", + "NOC_NPS7575_X5Y2", + "port1_in", + "NOC_NPS7575_X5Y2", + "port3_out", + "NOC_NIDB_X1Y3", + "port0_in", + "NOC_NIDB_X1Y3", + "port1_out", + "NOC_NIDB_X1Y1", + "port1_in", + "NOC_NIDB_X1Y1", + "port0_out", + "NOC_NPS7575_X5Y0", "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS7575_X5Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y12", + "port2_in", + "NOC_NPS_VNOC_X1Y12", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y10", "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y10", "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y8", + "port2_in", + "NOC_NPS_VNOC_X1Y8", + "port1_out", + "NOC_NPS_VNOC_X1Y9", + "port1_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 109 + }, { "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 6, "CommType": "READ", "Connections": [ @@ -53410,29 +64090,205 @@ "NOC_NPS_VNOC_X1Y37", "port1_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 109 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "NOC_NMU512_X1Y4", "PhyInstanceEnd": "HBM_MC_X7Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port1_out", - "NOC_NPS_VNOC_X1Y36", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", "NOC_NPS_VNOC_X1Y36", "port2_out", "NOC_NCRB_X1Y1", @@ -53457,95 +64313,15 @@ "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port1_out", - "NOC_NPS6_X3Y0", - "port0_in", - "NOC_NPS6_X3Y0", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA0_in", - "NOC_NPS4_X3Y0", - "portSideB2_out", - "HBM_MC_X7Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X7Y0", - "pc0_port0_out", - "NOC_NPS4_X3Y0", - "portSideB2_in", - "NOC_NPS4_X3Y0", - "portSideA0_out", - "NOC_NPS6_X3Y0", - "port5_in", - "NOC_NPS6_X3Y0", - "port0_out", - "NOC_NPS5555_X6Y3", - "port1_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 109 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", "ToLocked": false, "Port": "PORT0", "ReadTC": "BE", @@ -53558,70 +64334,106 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "HBM_MC_X13Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB2_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS5555_X7Y4", + "NOC_NPS_VNOC_X1Y11", "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", "port3_in", - "NOC_NPS6_X3Y1", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -53659,68 +64471,156 @@ "HBM_MC_X13Y0", "pc0_port0_in" ], - "RequiredBW": 132, - "AchievedBW": 132, + "RequiredBW": 264, + "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 31 + "AchievedLatency": 115 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 5, - "CommType": "WRITE", + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", + "HBM_MC_X13Y0", + "pc0_port0_out", + "NOC_NPS4_X6Y0", + "portSideB2_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", "port0_out", - "NOC_NCRB_X1Y1", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y17", "port2_out", - "NOC_NPS6_X3Y1", + "NOC_NPS_VNOC_X1Y15", "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", "port1_in", - "NOC_NPS5555_X7Y4", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", "port2_out", - "NOC_NPS6_X5Y1", + "NOC_NPS_VNOC_X1Y11", "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB2_out", - "HBM_MC_X13Y0", - "pc0_port0_in" + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" ], - "RequiredBW": 264, - "AchievedBW": 264, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 31 + "AchievedLatency": 115 }, { "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", "Connections": [ "HBM_MC_X13Y0", "pc0_port0_out", @@ -53759,126 +64659,201 @@ "NOC_NPS_VNOC_X1Y37", "port0_in", "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X2Y0", - "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB1_in", - "NOC_NPS4_X1Y0", - "portSideA1_out", - "NOC_NPS6_X1Y1", - "port5_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y35", "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", "port1_in", - "NOC_NPS5555_X6Y4", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", "port3_out", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y25", "port0_in", - "NOC_NCRB_X1Y0", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 115 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X2Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X13Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", "port0_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", "port3_in", - "NOC_NPS5555_X6Y4", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS6_X1Y1", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", "port3_in", - "NOC_NPS6_X1Y1", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA1_in", - "NOC_NPS4_X1Y0", - "portSideB1_out", - "HBM_MC_X2Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port2_in", "NOC_NPS_VNOC_X1Y37", "port0_out", "NOC_NCRB_X1Y1", @@ -53888,198 +64863,134 @@ "NOC_NPS5555_X6Y4", "port3_in", "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA1_in", - "NOC_NPS4_X1Y0", - "portSideB1_out", - "HBM_MC_X2Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X2Y0", - "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB1_in", - "NOC_NPS4_X1Y0", - "portSideA1_out", - "NOC_NPS6_X1Y1", - "port5_in", - "NOC_NPS6_X1Y1", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", "port3_out", - "NOC_NPS6_X2Y1", + "NOC_NPS6_X4Y1", "port0_in", - "NOC_NPS6_X2Y1", + "NOC_NPS6_X4Y1", "port3_out", - "NOC_NPS5555_X6Y4", + "NOC_NPS5555_X7Y4", "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", "port0_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS6_X5Y1", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA1_in", + "NOC_NPS4_X6Y0", + "portSideB2_out", + "HBM_MC_X13Y0", + "pc0_port0_in" ], "RequiredBW": 132, "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 25 + "AchievedLatency": 115 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_cips/inst/M00_AXI_nsu", + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", "ToLocked": false, - "Port": "PORT0", + "Port": "PORT2", "ReadTC": "BE", "WriteTC": "BE", - "ReadBW": 5, - "WriteBW": 5, - "ReadAchievedBW": 5, - "WriteAchievedBW": 5, + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, "ReadLatency": 300, "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ { - "PhyInstanceStart": "NOC_NSU512_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "NOC_NSU512_X0Y0", - "resp", - "NOC_NPS_VNOC_X0Y0", + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port1_out", - "NOC_NPS_VNOC_X0Y25", - "port1_in", - "NOC_NPS_VNOC_X0Y25", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", "port0_out", - "NOC_NPS7575_X4Y5", + "NOC_NPS7575_X5Y1", "port3_in", - "NOC_NPS7575_X4Y5", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NIDB_X0Y4", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NIDB_X0Y4", + "NOC_NIDB_X1Y0", "port1_out", - "NOC_NIDB_X0Y6", + "NOC_NIDB_X1Y2", "port1_in", - "NOC_NIDB_X0Y6", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPS7575_X4Y7", + "NOC_NPS7575_X5Y3", "port1_in", - "NOC_NPS7575_X4Y7", - "port2_out", - "NOC_NPP_RPTR_X0Y15", - "port0_in", - "NOC_NPP_RPTR_X0Y15", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", "port0_out", - "NOC_NCRB_SSIT_X1Y6", - "port1_in", - "NOC_NCRB_SSIT_X1Y6", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPP_RPTR_X1Y13", + "NOC_NIDB_X1Y4", "port0_in", - "NOC_NPP_RPTR_X1Y13", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", "port0_out", "NOC_NPS7575_X5Y7", - "port0_in", + "port1_in", "NOC_NPS7575_X5Y7", "port3_out", "NOC_NPS_VNOC_X1Y27", @@ -54105,25 +65016,65 @@ "NOC_NPS_VNOC_X1Y37", "port2_in", "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA1_in", + "NOC_NPS4_X1Y0", + "portSideB1_out", + "HBM_MC_X2Y0", + "pc1_port0_in" ], - "RequiredBW": 5, - "AchievedBW": 5, + "RequiredBW": 264, + "AchievedBW": 264, "RequiredLatency": 300, - "AchievedLatency": 117 + "AchievedLatency": 109 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "NOC_NSU512_X0Y0", - "VC": 4, - "CommType": "READ_REQ", + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "HBM_MC_X2Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB1_in", + "NOC_NPS4_X1Y0", + "portSideA1_out", + "NOC_NPS6_X1Y1", + "port5_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port0_in", "NOC_NPS_VNOC_X1Y37", "port2_out", "NOC_NPS_VNOC_X1Y35", @@ -54185,89 +65136,77 @@ "NOC_NPS_VNOC_X1Y15", "port0_in", "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", "port1_out", - "NOC_NPS_VNOC_X1Y14", - "port1_in", - "NOC_NPS_VNOC_X1Y14", - "port0_out", - "NOC_NPS7575_X5Y2", - "port1_in", - "NOC_NPS7575_X5Y2", - "port3_out", - "NOC_NIDB_X1Y3", + "NOC_NIDB_X1Y2", "port0_in", - "NOC_NIDB_X1Y3", + "NOC_NIDB_X1Y2", "port1_out", - "NOC_NIDB_X1Y1", + "NOC_NIDB_X1Y0", "port1_in", - "NOC_NIDB_X1Y1", - "port0_out", - "NOC_NPS7575_X5Y0", - "port3_in", - "NOC_NPS7575_X5Y0", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPP_RPTR_X1Y0", + "NOC_NPS7575_X5Y1", "port1_in", - "NOC_NPP_RPTR_X1Y0", - "port1_out", - "NOC_NCRB_SSIT_X1Y0", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NCRB_SSIT_X1Y0", - "port0_out", - "NOC_NPP_RPTR_X0Y2", - "port1_in", - "NOC_NPP_RPTR_X0Y2", - "port1_out", - "NOC_NPS7575_X0Y0", - "port2_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NSU512_X0Y0", - "req" + "NOC_NMU512_X1Y4", + "resp_in" ], - "RequiredBW": 1, - "AchievedBW": 1, + "RequiredBW": 132, + "AchievedBW": 132, "RequiredLatency": 300, - "AchievedLatency": 117 + "AchievedLatency": 109 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "NOC_NSU512_X0Y0", - "VC": 5, - "CommType": "WRITE", + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", + "HBM_MC_X2Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB1_in", + "NOC_NPS4_X1Y0", + "portSideA0_out", + "NOC_NPS6_X1Y0", + "port5_in", + "NOC_NPS6_X1Y0", + "port3_out", + "NOC_NPS6_X2Y0", + "port0_in", + "NOC_NPS6_X2Y0", + "port3_out", + "NOC_NPS5555_X6Y3", + "port0_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", "NOC_NPS_VNOC_X1Y37", - "port3_in", + "port0_in", "NOC_NPS_VNOC_X1Y37", "port2_out", "NOC_NPS_VNOC_X1Y35", @@ -54329,230 +65268,331 @@ "NOC_NPS_VNOC_X1Y15", "port0_in", "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", "port1_out", - "NOC_NPS_VNOC_X1Y14", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", "port1_in", - "NOC_NPS_VNOC_X1Y14", + "NOC_NIDB_X1Y0", "port0_out", - "NOC_NPS7575_X5Y2", + "NOC_NPS7575_X5Y1", "port1_in", - "NOC_NPS7575_X5Y2", + "NOC_NPS7575_X5Y1", "port3_out", - "NOC_NIDB_X1Y3", + "NOC_NPS_VNOC_X1Y13", "port0_in", - "NOC_NIDB_X1Y3", - "port1_out", - "NOC_NIDB_X1Y1", - "port1_in", - "NOC_NIDB_X1Y1", - "port0_out", - "NOC_NPS7575_X5Y0", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS7575_X5Y0", + "NOC_NPS_VNOC_X1Y9", "port0_out", - "NOC_NPP_RPTR_X1Y0", - "port1_in", - "NOC_NPP_RPTR_X1Y0", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", "port1_out", - "NOC_NCRB_SSIT_X1Y0", + "NOC_NIDB_X1Y0", "port0_in", - "NOC_NCRB_SSIT_X1Y0", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", "port0_out", - "NOC_NPP_RPTR_X0Y2", + "NOC_NPS7575_X5Y3", "port1_in", - "NOC_NPP_RPTR_X0Y2", - "port1_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", "port2_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", "port1_out", - "NOC_NPS_VNOC_X0Y12", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", "port2_in", - "NOC_NPS_VNOC_X0Y12", + "NOC_NPS_VNOC_X1Y27", "port0_out", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X1Y29", "port2_in", - "NOC_NPS_VNOC_X0Y10", + "NOC_NPS_VNOC_X1Y29", "port0_out", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X1Y31", "port2_in", - "NOC_NPS_VNOC_X0Y8", + "NOC_NPS_VNOC_X1Y31", "port0_out", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X1Y33", "port2_in", - "NOC_NPS_VNOC_X0Y6", + "NOC_NPS_VNOC_X1Y33", "port0_out", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X1Y35", "port2_in", - "NOC_NPS_VNOC_X0Y4", + "NOC_NPS_VNOC_X1Y35", "port0_out", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X1Y37", "port2_in", - "NOC_NPS_VNOC_X0Y2", + "NOC_NPS_VNOC_X1Y37", "port0_out", - "NOC_NPS_VNOC_X0Y0", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", "port2_in", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS5555_X6Y3", + "port0_out", + "NOC_NPS6_X2Y0", + "port3_in", + "NOC_NPS6_X2Y0", + "port0_out", + "NOC_NPS6_X1Y0", + "port3_in", + "NOC_NPS6_X1Y0", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA0_in", + "NOC_NPS4_X1Y0", + "portSideB1_out", + "HBM_MC_X2Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/M00_AXI_nsu/bd_6ff4_M00_AXI_nsu_0_top_INST/NOC_NSU512_INST", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 5, + "WriteBW": 5, + "ReadAchievedBW": 5, + "WriteAchievedBW": 5, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "NOC_NSU512_X1Y6", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", "port3_out", - "NOC_NSU512_X0Y0", + "NOC_NSU512_X1Y6", "req" ], "RequiredBW": 5, "AchievedBW": 5, "RequiredLatency": 300, - "AchievedLatency": 117 + "AchievedLatency": 18 }, { - "PhyInstanceStart": "NOC_NSU512_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "NOC_NSU512_X1Y6", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "NOC_NSU512_X0Y0", + "NOC_NSU512_X1Y6", "resp", - "NOC_NPS_VNOC_X0Y0", + "NOC_NPS_VNOC_X1Y12", "port3_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", + "NOC_NPS_VNOC_X1Y12", + "port1_out", + "NOC_NPS_VNOC_X1Y13", "port1_in", - "NOC_NPS7575_X0Y0", + "NOC_NPS_VNOC_X1Y13", "port2_out", - "NOC_NPP_RPTR_X0Y2", - "port0_in", - "NOC_NPP_RPTR_X0Y2", - "port0_out", - "NOC_NCRB_SSIT_X1Y1", - "port0_in", - "NOC_NCRB_SSIT_X1Y1", - "port0_out", - "NOC_NPP_RPTR_X1Y0", + "NOC_NPS_VNOC_X1Y11", "port0_in", - "NOC_NPP_RPTR_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y0", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", "port0_in", - "NOC_NPS7575_X5Y0", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NIDB_X1Y1", - "port0_in", - "NOC_NIDB_X1Y1", - "port1_out", - "NOC_NIDB_X1Y3", - "port1_in", - "NOC_NIDB_X1Y3", - "port0_out", - "NOC_NPS7575_X5Y2", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 1, + "AchievedBW": 1, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "NOC_NSU512_X1Y6", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "NOC_NSU512_X1Y6", + "resp", + "NOC_NPS_VNOC_X1Y12", "port3_in", - "NOC_NPS7575_X5Y2", + "NOC_NPS_VNOC_X1Y12", "port1_out", - "NOC_NPS_VNOC_X1Y14", - "port0_in", - "NOC_NPS_VNOC_X1Y14", - "port2_out", - "NOC_NPS_VNOC_X1Y16", - "port0_in", - "NOC_NPS_VNOC_X1Y16", - "port2_out", - "NOC_NPS_VNOC_X1Y18", - "port0_in", - "NOC_NPS_VNOC_X1Y18", - "port2_out", - "NOC_NPS_VNOC_X1Y20", - "port0_in", - "NOC_NPS_VNOC_X1Y20", + "NOC_NPS_VNOC_X1Y13", + "port1_in", + "NOC_NPS_VNOC_X1Y13", "port2_out", - "NOC_NPS_VNOC_X1Y22", + "NOC_NPS_VNOC_X1Y11", "port0_in", - "NOC_NPS_VNOC_X1Y22", + "NOC_NPS_VNOC_X1Y11", "port2_out", - "NOC_NPS_VNOC_X1Y24", + "NOC_NPS_VNOC_X1Y9", "port0_in", - "NOC_NPS_VNOC_X1Y24", - "port2_out", - "NOC_NPS7575_X5Y4", - "port1_in", - "NOC_NPS7575_X5Y4", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NIDB_X1Y5", - "port0_in", - "NOC_NIDB_X1Y5", - "port1_out", - "NOC_NIDB_X1Y7", - "port1_in", - "NOC_NIDB_X1Y7", - "port0_out", - "NOC_NPS7575_X5Y6", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 5, + "AchievedBW": 5, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "NOC_NSU512_X1Y6", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS7575_X5Y6", + "NOC_NPS_VNOC_X1Y9", "port1_out", - "NOC_NPS_VNOC_X1Y26", - "port0_in", - "NOC_NPS_VNOC_X1Y26", - "port2_out", - "NOC_NPS_VNOC_X1Y28", - "port0_in", - "NOC_NPS_VNOC_X1Y28", - "port2_out", - "NOC_NPS_VNOC_X1Y30", - "port0_in", - "NOC_NPS_VNOC_X1Y30", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", "port2_out", - "NOC_NPS_VNOC_X1Y32", + "NOC_NPS_VNOC_X1Y10", "port0_in", - "NOC_NPS_VNOC_X1Y32", + "NOC_NPS_VNOC_X1Y10", "port2_out", - "NOC_NPS_VNOC_X1Y34", + "NOC_NPS_VNOC_X1Y12", "port0_in", - "NOC_NPS_VNOC_X1Y34", - "port1_out", - "NOC_NPS_VNOC_X1Y35", - "port1_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y12", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "NOC_NSU512_X1Y6", + "req" ], "RequiredBW": 1, "AchievedBW": 1, "RequiredLatency": 300, - "AchievedLatency": 117 + "AchievedLatency": 18 } ] }, { "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", "FromLocked": false, - "To": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", + "To": "top_i/axi_noc_mc_ddr4_1/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", "ToLocked": false, "Port": "PORT0", "ReadTC": "BE", @@ -54565,13 +65605,65 @@ "WriteLatency": 300, "ReadBestPossibleLatency": 300, "WriteBestPossibleLatency": 300, - "PathLocked": true, + "PathLocked": false, "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "DDRMC_X1Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port0_out", + "NOC_NPS5555_X10Y1", + "port2_in", + "NOC_NPS5555_X10Y1", + "port1_out", + "NOC_NPS5555_X10Y0", + "port3_in", + "NOC_NPS5555_X10Y0", + "port0_out", + "NOC_NPS5555_X8Y0", + "port2_in", + "NOC_NPS5555_X8Y0", + "port1_out", + "DDRMC_X1Y0", + "Port0_req" + ], + "RequiredBW": 850, + "AchievedBW": 850, + "RequiredLatency": 300, + "AchievedLatency": 28 + }, { "PhyInstanceStart": "DDRMC_X1Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", "Connections": [ "DDRMC_X1Y0", "Port0_resp", @@ -54610,201 +65702,77 @@ "NOC_NPS_VNOC_X1Y9", "port2_in", "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 28 + }, + { + "PhyInstanceStart": "DDRMC_X1Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "DDRMC_X1Y0", + "Port0_resp", + "NOC_NPS5555_X8Y0", "port1_in", - "NOC_NPS7575_X5Y7", + "NOC_NPS5555_X8Y0", + "port2_out", + "NOC_NPS5555_X10Y0", + "port0_in", + "NOC_NPS5555_X10Y0", "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS5555_X10Y1", + "port1_in", + "NOC_NPS5555_X10Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port0_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", "port2_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X1Y1", "port0_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X1Y3", "port2_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X1Y3", "port0_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X1Y5", "port2_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X1Y5", "port0_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X1Y7", "port2_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X1Y7", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port2_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 800, "AchievedBW": 800, "RequiredLatency": 300, - "AchievedLatency": 112 + "AchievedLatency": 28 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "NOC_NMU512_X1Y4", "PhyInstanceEnd": "DDRMC_X1Y0", "VC": 4, "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", "NOC_NPS_VNOC_X1Y9", - "port0_in", + "port3_in", "NOC_NPS_VNOC_X1Y9", "port2_out", "NOC_NPS_VNOC_X1Y7", @@ -54845,106 +65813,39 @@ "RequiredBW": 50, "AchievedBW": 50, "RequiredLatency": 300, - "AchievedLatency": 112 - }, + "AchievedLatency": 28 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "DDRMC_X1Y0", + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "DDRMC_X0Y0", "VC": 5, "CommType": "WRITE", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", "NOC_NPS_VNOC_X1Y9", - "port0_in", + "port3_in", "NOC_NPS_VNOC_X1Y9", "port2_out", "NOC_NPS_VNOC_X1Y7", @@ -54978,25 +65879,49 @@ "NOC_NPS5555_X8Y0", "port2_in", "NOC_NPS5555_X8Y0", - "port1_out", - "DDRMC_X1Y0", + "port0_out", + "NOC_NPS5555_X6Y0", + "port2_in", + "NOC_NPS5555_X6Y0", + "port0_out", + "NOC_NPS5555_X4Y0", + "port2_in", + "NOC_NPS5555_X4Y0", + "port0_out", + "NOC_NPS5555_X2Y0", + "port2_in", + "NOC_NPS5555_X2Y0", + "port3_out", + "DDRMC_X0Y0", "Port0_req" ], "RequiredBW": 850, "AchievedBW": 850, "RequiredLatency": 300, - "AchievedLatency": 112 + "AchievedLatency": 34 }, { - "PhyInstanceStart": "DDRMC_X1Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 7, "CommType": "WRITE_RESP", "Connections": [ - "DDRMC_X1Y0", + "DDRMC_X0Y0", "Port0_resp", + "NOC_NPS5555_X2Y0", + "port3_in", + "NOC_NPS5555_X2Y0", + "port2_out", + "NOC_NPS5555_X4Y0", + "port0_in", + "NOC_NPS5555_X4Y0", + "port2_out", + "NOC_NPS5555_X6Y0", + "port0_in", + "NOC_NPS5555_X6Y0", + "port2_out", "NOC_NPS5555_X8Y0", - "port1_in", + "port0_in", "NOC_NPS5555_X8Y0", "port2_out", "NOC_NPS5555_X10Y0", @@ -55006,151 +65931,42 @@ "NOC_NPS5555_X10Y1", "port1_in", "NOC_NPS5555_X10Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port0_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS5555_X11Y1", + "port0_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", "port2_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS_VNOC_X1Y1", "port0_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X1Y3", "port2_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS_VNOC_X1Y3", "port0_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X1Y5", "port2_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS_VNOC_X1Y5", "port0_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X1Y7", "port2_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS_VNOC_X1Y7", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port2_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X1Y9", "port3_out", - "NOC_NMU512_X1Y18", + "NOC_NMU512_X1Y4", "resp_in" ], "RequiredBW": 50, "AchievedBW": 50, "RequiredLatency": 300, - "AchievedLatency": 112 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ + "AchievedLatency": 34 + }, { "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", "VC": 6, "CommType": "READ", "Connections": [ @@ -55203,558 +66019,563 @@ "NOC_NPS_VNOC_X1Y9", "port2_in", "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 800, + "AchievedBW": 800, + "RequiredLatency": 300, + "AchievedLatency": 34 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", "port2_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS5555_X11Y1", "port0_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS5555_X10Y1", "port2_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS5555_X10Y1", + "port1_out", + "NOC_NPS5555_X10Y0", + "port3_in", + "NOC_NPS5555_X10Y0", "port0_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X8Y0", "port2_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X8Y0", "port0_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X6Y0", "port2_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X6Y0", "port0_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X4Y0", "port2_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X4Y0", "port0_out", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X2Y0", "port2_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X2Y0", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "DDRMC_X0Y0", + "Port0_req" ], - "RequiredBW": 800, - "AchievedBW": 800, + "RequiredBW": 50, + "AchievedBW": 50, "RequiredLatency": 300, - "AchievedLatency": 118 - }, + "AchievedLatency": 34 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S02_AXI_nmu/bd_6ff4_S02_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "axi_noc/inst/M00_AXI_nsu/bd_1091_M00_AXI_nsu_0_top_INST/NOC_NSU512_INST", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 5, + "WriteBW": 5, + "ReadAchievedBW": 5, + "WriteAchievedBW": 5, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": true, + "Nets": [ { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", + "PhyInstanceStart": "NOC_NMU128_X0Y2", + "PhyInstanceEnd": "NOC_NSU512_X2Y10", + "VC": 5, + "CommType": "WRITE", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU128_X0Y2", "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS5555_X1Y1", + "port0_in", + "NOC_NPS5555_X1Y1", "port2_out", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X3Y1", "port0_in", - "NOC_NPS_VNOC_X1Y35", + "NOC_NPS5555_X3Y1", "port2_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X5Y1", "port0_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X5Y1", "port2_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X7Y2", "port0_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X7Y2", "port2_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS5555_X9Y2", "port0_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS5555_X9Y2", "port2_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS5555_X11Y2", "port0_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS5555_X11Y2", "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", + "NOC_NPS5555_X13Y2", "port0_in", - "NOC_NIDB_X1Y6", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", "port1_in", - "NOC_NPS7575_X5Y1", + "NOC_NPS7575_X6Y0", "port3_out", - "NOC_NPS_VNOC_X1Y13", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X2Y20", + "port3_out", + "NOC_NSU512_X2Y10", + "req" + ], + "RequiredBW": 6, + "AchievedBW": 6, + "RequiredLatency": 300, + "AchievedLatency": 80 + }, + { + "PhyInstanceStart": "NOC_NSU512_X2Y10", + "PhyInstanceEnd": "NOC_NMU128_X0Y2", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "NOC_NSU512_X2Y10", + "resp", + "NOC_NPS_VNOC_X2Y20", + "port3_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port0_out", + "NOC_NMU128_X0Y2", + "resp_in" + ], + "RequiredBW": 1, + "AchievedBW": 1, + "RequiredLatency": 300, + "AchievedLatency": 80 + }, + { + "PhyInstanceStart": "NOC_NSU512_X2Y10", + "PhyInstanceEnd": "NOC_NMU128_X0Y2", + "VC": 6, + "CommType": "READ", + "Connections": [ + "NOC_NSU512_X2Y10", + "resp", + "NOC_NPS_VNOC_X2Y20", + "port3_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", "port2_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS_VNOC_X2Y0", "port0_out", - "NOC_NPS5555_X10Y1", + "NOC_NPS5555_X17Y1", "port2_in", - "NOC_NPS5555_X10Y1", - "port1_out", - "NOC_NPS5555_X10Y0", - "port3_in", - "NOC_NPS5555_X10Y0", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", "port0_out", - "NOC_NPS5555_X8Y0", + "NOC_NPS5555_X15Y2", "port2_in", - "NOC_NPS5555_X8Y0", + "NOC_NPS5555_X15Y2", "port0_out", - "NOC_NPS5555_X6Y0", + "NOC_NPS5555_X13Y2", "port2_in", - "NOC_NPS5555_X6Y0", + "NOC_NPS5555_X13Y2", "port0_out", - "NOC_NPS5555_X4Y0", + "NOC_NPS5555_X11Y2", "port2_in", - "NOC_NPS5555_X4Y0", + "NOC_NPS5555_X11Y2", "port0_out", - "NOC_NPS5555_X2Y0", + "NOC_NPS5555_X9Y2", "port2_in", - "NOC_NPS5555_X2Y0", - "port3_out", - "DDRMC_X0Y0", - "Port0_req" + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port0_out", + "NOC_NMU128_X0Y2", + "resp_in" ], - "RequiredBW": 50, - "AchievedBW": 50, + "RequiredBW": 5, + "AchievedBW": 5, "RequiredLatency": 300, - "AchievedLatency": 118 + "AchievedLatency": 80 }, { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 5, - "CommType": "WRITE", + "PhyInstanceStart": "NOC_NMU128_X0Y2", + "PhyInstanceEnd": "NOC_NSU512_X2Y10", + "VC": 4, + "CommType": "READ_REQ", "Connections": [ - "NOC_NMU512_X1Y18", + "NOC_NMU128_X0Y2", "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X1Y1", "port0_in", - "NOC_NPS_VNOC_X1Y33", + "NOC_NPS5555_X1Y1", "port2_out", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X3Y1", "port0_in", - "NOC_NPS_VNOC_X1Y31", + "NOC_NPS5555_X3Y1", "port2_out", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS5555_X5Y1", "port0_in", - "NOC_NPS_VNOC_X1Y29", + "NOC_NPS5555_X5Y1", "port2_out", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS5555_X7Y2", "port0_in", - "NOC_NPS_VNOC_X1Y27", + "NOC_NPS5555_X7Y2", "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS5555_X9Y2", "port0_in", - "NOC_NPS_VNOC_X1Y25", + "NOC_NPS5555_X9Y2", "port2_out", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS5555_X11Y2", "port0_in", - "NOC_NPS_VNOC_X1Y23", + "NOC_NPS5555_X11Y2", "port2_out", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS5555_X13Y2", "port0_in", - "NOC_NPS_VNOC_X1Y21", + "NOC_NPS5555_X13Y2", "port2_out", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS5555_X15Y2", "port0_in", - "NOC_NPS_VNOC_X1Y19", + "NOC_NPS5555_X15Y2", "port2_out", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS5555_X17Y2", "port0_in", - "NOC_NPS_VNOC_X1Y17", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", "port2_out", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X2Y0", "port0_in", - "NOC_NPS_VNOC_X1Y15", + "NOC_NPS_VNOC_X2Y0", "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X2Y2", "port0_in", - "NOC_NPS_VNOC_X1Y13", + "NOC_NPS_VNOC_X2Y2", "port2_out", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X2Y4", "port0_in", - "NOC_NPS_VNOC_X1Y11", + "NOC_NPS_VNOC_X2Y4", "port2_out", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X2Y6", "port0_in", - "NOC_NPS_VNOC_X1Y9", + "NOC_NPS_VNOC_X2Y6", "port2_out", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X2Y8", "port0_in", - "NOC_NPS_VNOC_X1Y7", + "NOC_NPS_VNOC_X2Y8", "port2_out", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X2Y10", "port0_in", - "NOC_NPS_VNOC_X1Y5", + "NOC_NPS_VNOC_X2Y10", "port2_out", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X2Y12", "port0_in", - "NOC_NPS_VNOC_X1Y3", + "NOC_NPS_VNOC_X2Y12", "port2_out", - "NOC_NPS_VNOC_X1Y1", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port0_out", - "NOC_NPS5555_X10Y1", - "port2_in", - "NOC_NPS5555_X10Y1", + "NOC_NIDB_X2Y1", "port1_out", - "NOC_NPS5555_X10Y0", - "port3_in", - "NOC_NPS5555_X10Y0", - "port0_out", - "NOC_NPS5555_X8Y0", - "port2_in", - "NOC_NPS5555_X8Y0", - "port0_out", - "NOC_NPS5555_X6Y0", - "port2_in", - "NOC_NPS5555_X6Y0", - "port0_out", - "NOC_NPS5555_X4Y0", - "port2_in", - "NOC_NPS5555_X4Y0", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", "port0_out", - "NOC_NPS5555_X2Y0", - "port2_in", - "NOC_NPS5555_X2Y0", - "port3_out", - "DDRMC_X0Y0", - "Port0_req" - ], - "RequiredBW": 850, - "AchievedBW": 850, - "RequiredLatency": 300, - "AchievedLatency": 118 - }, - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "DDRMC_X0Y0", - "Port0_resp", - "NOC_NPS5555_X2Y0", + "NOC_NPS7575_X6Y2", "port3_in", - "NOC_NPS5555_X2Y0", - "port2_out", - "NOC_NPS5555_X4Y0", - "port0_in", - "NOC_NPS5555_X4Y0", - "port2_out", - "NOC_NPS5555_X6Y0", - "port0_in", - "NOC_NPS5555_X6Y0", - "port2_out", - "NOC_NPS5555_X8Y0", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", "port0_in", - "NOC_NPS5555_X8Y0", + "NOC_NPS_VNOC_X2Y14", "port2_out", - "NOC_NPS5555_X10Y0", + "NOC_NPS_VNOC_X2Y16", "port0_in", - "NOC_NPS5555_X10Y0", - "port3_out", - "NOC_NPS5555_X10Y1", - "port1_in", - "NOC_NPS5555_X10Y1", + "NOC_NPS_VNOC_X2Y16", "port2_out", - "NOC_NPS5555_X11Y1", + "NOC_NPS_VNOC_X2Y18", "port0_in", - "NOC_NPS5555_X11Y1", + "NOC_NPS_VNOC_X2Y18", "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", + "NOC_NPS_VNOC_X2Y20", "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", + "NOC_NPS_VNOC_X2Y20", "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" + "NOC_NSU512_X2Y10", + "req" ], - "RequiredBW": 50, - "AchievedBW": 50, + "RequiredBW": 1, + "AchievedBW": 1, "RequiredLatency": 300, - "AchievedLatency": 118 + "AchievedLatency": 80 } ] } @@ -55766,8 +66587,7 @@ }, { "Name": "NOC_NMU512_X1Y18", - "TrafficLInst": "axi_noc_cips/inst/S04_AXI_nmu", - "DestId": 64 + "DestId": 0 }, { "Name": "NOC_NMU512_X2Y18", @@ -56043,7 +66863,8 @@ }, { "Name": "NOC_NSU512_X2Y10", - "DestId": 0 + "TrafficLInst": "axi_noc/inst/M00_AXI_nsu/bd_1091_M00_AXI_nsu_0_top_INST/NOC_NSU512_INST", + "DestId": 64 }, { "Name": "NOC_NSU512_X3Y10", @@ -56167,7 +66988,8 @@ }, { "Name": "NOC_NSU512_X1Y6", - "DestId": 0 + "TrafficLInst": "top_i/axi_noc_cips/inst/M00_AXI_nsu/bd_6ff4_M00_AXI_nsu_0_top_INST/NOC_NSU512_INST", + "DestId": 192 }, { "Name": "NOC_NSU512_X2Y6", @@ -56215,7 +67037,8 @@ }, { "Name": "NOC_NMU512_X1Y4", - "DestId": 0 + "TrafficLInst": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "DestId": 192 }, { "Name": "NOC_NMU512_X2Y4", @@ -56355,8 +67178,7 @@ }, { "Name": "NOC_NSU512_X0Y0", - "TrafficLInst": "axi_noc_cips/inst/M00_AXI_nsu", - "DestId": 128 + "DestId": 0 }, { "Name": "NOC_NSU512_X1Y0", @@ -56632,7 +67454,7 @@ }, { "Name": "NOC_NPS4_X0Y1", - "DestId": 960 + "DestId": 1088 }, { "Name": "NOC_NPS4_X1Y0", @@ -56640,7 +67462,7 @@ }, { "Name": "NOC_NPS4_X1Y1", - "DestId": 1536 + "DestId": 1600 }, { "Name": "NOC_NPS4_X2Y0", @@ -56648,7 +67470,7 @@ }, { "Name": "NOC_NPS4_X2Y1", - "DestId": 1792 + "DestId": 1856 }, { "Name": "NOC_NPS4_X3Y0", @@ -56656,7 +67478,7 @@ }, { "Name": "NOC_NPS4_X3Y1", - "DestId": 2368 + "DestId": 2432 }, { "Name": "NOC_NPS4_X4Y0", @@ -56664,7 +67486,7 @@ }, { "Name": "NOC_NPS4_X4Y1", - "DestId": 2880 + "DestId": 2944 }, { "Name": "NOC_NPS4_X5Y0", @@ -56672,7 +67494,7 @@ }, { "Name": "NOC_NPS4_X5Y1", - "DestId": 3392 + "DestId": 3456 }, { "Name": "NOC_NPS4_X6Y0", @@ -56680,7 +67502,7 @@ }, { "Name": "NOC_NPS4_X6Y1", - "DestId": 3904 + "DestId": 3968 }, { "Name": "NOC_NPS4_X7Y0", @@ -56688,7 +67510,7 @@ }, { "Name": "NOC_NPS4_X7Y1", - "DestId": 1408 + "DestId": 1344 }, { "Name": "NOC_NPS6_X0Y0", @@ -58024,7 +68846,7 @@ }, { "Name": "NOC_NPS_VNOC_X1Y12", - "DestId": 0 + "DestId": 192 }, { "Name": "NOC_NPS_VNOC_X2Y12", @@ -58040,7 +68862,7 @@ }, { "Name": "NOC_NPS_VNOC_X1Y11", - "DestId": 0 + "DestId": 192 }, { "Name": "NOC_NPS_VNOC_X2Y11", @@ -58056,7 +68878,7 @@ }, { "Name": "NOC_NPS_VNOC_X1Y10", - "DestId": 0 + "DestId": 192 }, { "Name": "NOC_NPS_VNOC_X2Y10", @@ -58072,7 +68894,7 @@ }, { "Name": "NOC_NPS_VNOC_X1Y9", - "DestId": 0 + "DestId": 192 }, { "Name": "NOC_NPS_VNOC_X2Y9", @@ -58232,11 +69054,11 @@ }, { "Name": "NOC_NPS5555_X0Y1", - "DestId": 192 + "DestId": 256 }, { "Name": "NOC_NPS5555_X1Y0", - "DestId": 192 + "DestId": 256 }, { "Name": "NOC_NPS5555_X1Y1", @@ -58248,7 +69070,7 @@ }, { "Name": "NOC_NPS5555_X2Y1", - "DestId": 192 + "DestId": 256 }, { "Name": "NOC_NPS5555_X3Y0", @@ -58264,7 +69086,7 @@ }, { "Name": "NOC_NPS5555_X4Y1", - "DestId": 192 + "DestId": 256 }, { "Name": "NOC_NPS5555_X5Y0", @@ -58284,7 +69106,7 @@ }, { "Name": "NOC_NPS5555_X6Y2", - "DestId": 192 + "DestId": 256 }, { "Name": "NOC_NPS5555_X7Y0", @@ -58308,7 +69130,7 @@ }, { "Name": "NOC_NPS5555_X8Y2", - "DestId": 192 + "DestId": 256 }, { "Name": "NOC_NPS5555_X9Y0", @@ -58520,13 +69342,13 @@ }, { "Name": "NOC_NMU128_X0Y0", - "TrafficLInst": "axi_noc_cips/inst/S00_AXI_nmu", - "DestId": 192 + "TrafficLInst": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "DestId": 256 }, { "Name": "NOC_NMU128_X0Y1", - "TrafficLInst": "axi_noc_cips/inst/S01_AXI_nmu", - "DestId": 256 + "TrafficLInst": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "DestId": 320 }, { "Name": "NOC_NSU128_X0Y1", @@ -58534,13 +69356,13 @@ }, { "Name": "NOC_NMU128_X0Y2", - "TrafficLInst": "axi_noc_cips/inst/S02_AXI_nmu", + "TrafficLInst": "top_i/axi_noc_cips/inst/S02_AXI_nmu/bd_6ff4_S02_AXI_nmu_0_top_INST/NOC_NMU128_INST", "DestId": 0 }, { "Name": "NOC_NMU128_X0Y3", - "TrafficLInst": "axi_noc_cips/inst/S03_AXI_rpu", - "DestId": 320 + "TrafficLInst": "top_i/axi_noc_cips/inst/S03_AXI_rpu/bd_6ff4_S03_AXI_rpu_0_top_INST/NOC_NMU128_INST", + "DestId": 384 }, { "Name": "NOC_NMU128_X0Y4", @@ -58584,49 +69406,49 @@ }, { "Name": "DDRMC_X0Y0", - "TrafficLInst": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "DestId": 384, + "TrafficLInst": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "DestId": 448, "PortIndex": 0 }, { "Name": "DDRMC_X0Y0", - "TrafficLInst": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "DestId": 192, + "TrafficLInst": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "DestId": 256, "PortIndex": 1 }, { "Name": "DDRMC_X0Y0", - "TrafficLInst": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", + "TrafficLInst": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", "DestId": 0, "PortIndex": 2 }, { "Name": "DDRMC_X0Y0", - "TrafficLInst": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", + "TrafficLInst": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", "DestId": 0, "PortIndex": 3 }, { "Name": "DDRMC_X1Y0", - "TrafficLInst": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", - "DestId": 512, + "TrafficLInst": "top_i/axi_noc_mc_ddr4_1/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "DestId": 576, "PortIndex": 0 }, { "Name": "DDRMC_X1Y0", - "TrafficLInst": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", - "DestId": 193, + "TrafficLInst": "top_i/axi_noc_mc_ddr4_1/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "DestId": 257, "PortIndex": 1 }, { "Name": "DDRMC_X1Y0", - "TrafficLInst": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", + "TrafficLInst": "top_i/axi_noc_mc_ddr4_1/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", "DestId": 0, "PortIndex": 2 }, { "Name": "DDRMC_X1Y0", - "TrafficLInst": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", + "TrafficLInst": "top_i/axi_noc_mc_ddr4_1/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", "DestId": 0, "PortIndex": 3 }, @@ -58672,386 +69494,386 @@ }, { "Name": "HBM_MC_X0Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "DestId": 640, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "DestId": 704, "PortIndex": 0 }, { "Name": "HBM_MC_X0Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "DestId": 961, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "DestId": 1089, "PortIndex": 1 }, { "Name": "HBM_MC_X0Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "DestId": 768, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "DestId": 832, "PortIndex": 2 }, { "Name": "HBM_MC_X0Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "DestId": 962, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "DestId": 1090, "PortIndex": 3 }, { "Name": "HBM_MC_X1Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "DestId": 896, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "DestId": 960, "PortIndex": 0 }, { "Name": "HBM_MC_X1Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "DestId": 960, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "DestId": 1088, "PortIndex": 1 }, { "Name": "HBM_MC_X1Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "DestId": 1088, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "DestId": 1152, "PortIndex": 2 }, { "Name": "HBM_MC_X1Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "DestId": 1152, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "DestId": 1216, "PortIndex": 3 }, { "Name": "HBM_MC_X2Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "DestId": 1216, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "DestId": 1280, "PortIndex": 0 }, { "Name": "HBM_MC_X2Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "DestId": 1537, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "DestId": 1601, "PortIndex": 1 }, { "Name": "HBM_MC_X2Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "DestId": 1344, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "DestId": 1408, "PortIndex": 2 }, { "Name": "HBM_MC_X2Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "DestId": 1538, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "DestId": 1602, "PortIndex": 3 }, { "Name": "HBM_MC_X3Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "DestId": 1472, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "DestId": 1536, "PortIndex": 0 }, { "Name": "HBM_MC_X3Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "DestId": 1536, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "DestId": 1600, "PortIndex": 1 }, { "Name": "HBM_MC_X3Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "DestId": 1600, + "TrafficLInst": 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"top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "DestId": 1472, "PortIndex": 2 }, { "Name": "HBM_MC_X14Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "DestId": 1409, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "DestId": 1345, "PortIndex": 3 }, { "Name": "HBM_MC_X15Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "DestId": 2496, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "DestId": 1984, "PortIndex": 0 }, { "Name": "HBM_MC_X15Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "DestId": 3008, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "DestId": 2560, "PortIndex": 1 }, { "Name": "HBM_MC_X15Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "DestId": 3520, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "DestId": 3072, "PortIndex": 2 }, { "Name": "HBM_MC_X15Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "DestId": 4032, + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "DestId": 3584, "PortIndex": 3 } ] diff --git a/submodules/v80-vitis-flow/resources/noc_sol_dcmac.ncr b/submodules/v80-vitis-flow/resources/noc_sol_dcmac.ncr new file mode 100644 index 00000000..b866955f --- /dev/null +++ b/submodules/v80-vitis-flow/resources/noc_sol_dcmac.ncr @@ -0,0 +1,69880 @@ +{ + "SolutionType": "OPTIMAL", + "LockAllDestIds": false, + "Paths": [ + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA2_in", + "NOC_NPS4_X5Y0", + "portSideB1_out", + "HBM_MC_X10Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X10Y0", + "pc1_port0_out", + "NOC_NPS4_X5Y0", + "portSideB1_in", + "NOC_NPS4_X5Y0", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port5_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X10Y0", + "pc1_port0_out", + "NOC_NPS4_X5Y0", + "portSideB1_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port5_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB1_out", + "HBM_MC_X10Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA1_in", + "NOC_NPS4_X7Y0", + "portSideB2_out", + "HBM_MC_X15Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X15Y0", + "pc0_port0_out", + "NOC_NPS4_X7Y0", + "portSideB2_in", + "NOC_NPS4_X7Y0", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port5_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X15Y0", + "pc0_port0_out", + "NOC_NPS4_X7Y0", + "portSideB2_in", + "NOC_NPS4_X7Y0", + "portSideA2_out", + "NOC_NPS6_X7Y2", + "port5_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA2_in", + "NOC_NPS4_X7Y0", + "portSideB2_out", + "HBM_MC_X15Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB0_out", + "HBM_MC_X10Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X10Y0", + "pc0_port0_out", + "NOC_NPS4_X5Y0", + "portSideB0_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port5_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X10Y0", + "pc0_port0_out", + "NOC_NPS4_X5Y0", + "portSideB0_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port5_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB0_out", + "HBM_MC_X10Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", + "portSideB2_out", + "HBM_MC_X5Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X5Y0", + "pc0_port0_out", + "NOC_NPS4_X2Y0", + "portSideB2_in", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port5_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X5Y0", + "pc0_port0_out", + "NOC_NPS4_X2Y0", + "portSideB2_in", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port5_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", + "portSideB2_out", + "HBM_MC_X5Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA2_in", + "NOC_NPS4_X7Y0", + "portSideB3_out", + "HBM_MC_X15Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X15Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB3_in", + "NOC_NPS4_X7Y0", + "portSideA2_out", + "NOC_NPS6_X7Y2", + "port5_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X15Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB3_in", + "NOC_NPS4_X7Y0", + "portSideA2_out", + "NOC_NPS6_X7Y2", + "port5_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA2_in", + "NOC_NPS4_X7Y0", + "portSideB3_out", + "HBM_MC_X15Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", + "portSideB3_out", + "HBM_MC_X5Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X5Y0", + "pc1_port0_out", + "NOC_NPS4_X2Y0", + "portSideB3_in", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port5_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X5Y0", + "pc1_port0_out", + "NOC_NPS4_X2Y0", + "portSideB3_in", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port5_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", + "portSideB3_out", + "HBM_MC_X5Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB2_out", + "HBM_MC_X1Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X1Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB2_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X1Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB2_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB2_out", + "HBM_MC_X1Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB3_out", + "HBM_MC_X1Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X1Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB3_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X1Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB3_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB3_out", + "HBM_MC_X1Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB0_out", + "HBM_MC_X6Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X6Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB0_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X6Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB0_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB0_out", + "HBM_MC_X6Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA2_in", + "NOC_NPS4_X6Y0", + "portSideB0_out", + "HBM_MC_X12Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X12Y0", + "pc0_port0_out", + "NOC_NPS4_X6Y0", + "portSideB0_in", + "NOC_NPS4_X6Y0", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port5_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X12Y0", + "pc0_port0_out", + "NOC_NPS4_X6Y0", + "portSideB0_in", + "NOC_NPS4_X6Y0", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port5_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA2_in", + "NOC_NPS4_X6Y0", + "portSideB0_out", + "HBM_MC_X12Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB1_out", + "HBM_MC_X0Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X0Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB1_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X0Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB1_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB1_out", + "HBM_MC_X0Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB1_out", + "HBM_MC_X6Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X6Y0", + "pc1_port0_out", + "NOC_NPS4_X3Y0", + "portSideB1_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X6Y0", + "pc1_port0_out", + "NOC_NPS4_X3Y0", + "portSideB1_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port1_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB1_out", + "HBM_MC_X6Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA2_in", + "NOC_NPS4_X7Y0", + "portSideB1_out", + "HBM_MC_X14Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X14Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB1_in", + "NOC_NPS4_X7Y0", + "portSideA2_out", + "NOC_NPS6_X7Y2", + "port5_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X14Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB1_in", + "NOC_NPS4_X7Y0", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port5_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA1_in", + "NOC_NPS4_X7Y0", + "portSideB1_out", + "HBM_MC_X14Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA2_in", + "NOC_NPS4_X6Y0", + "portSideB1_out", + "HBM_MC_X12Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X12Y0", + "pc1_port0_out", + "NOC_NPS4_X6Y0", + "portSideB1_in", + "NOC_NPS4_X6Y0", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port5_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X12Y0", + "pc1_port0_out", + "NOC_NPS4_X6Y0", + "portSideB1_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA1_in", + "NOC_NPS4_X6Y0", + "portSideB1_out", + "HBM_MC_X12Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB0_out", + "HBM_MC_X0Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X0Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB0_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X0Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB0_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB0_out", + "HBM_MC_X0Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA2_in", + "NOC_NPS4_X4Y0", + "portSideB0_out", + "HBM_MC_X8Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X8Y0", + "pc0_port0_out", + "NOC_NPS4_X4Y0", + "portSideB0_in", + "NOC_NPS4_X4Y0", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port5_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X8Y0", + "pc0_port0_out", + "NOC_NPS4_X4Y0", + "portSideB0_in", + "NOC_NPS4_X4Y0", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port5_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA2_in", + "NOC_NPS4_X4Y0", + "portSideB0_out", + "HBM_MC_X8Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA1_in", + "NOC_NPS4_X4Y0", + "portSideB1_out", + "HBM_MC_X8Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X8Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB1_in", + "NOC_NPS4_X4Y0", + "portSideA1_out", + "NOC_NPS6_X4Y1", + "port5_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X8Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB1_in", + "NOC_NPS4_X4Y0", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port5_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA2_in", + "NOC_NPS4_X4Y0", + "portSideB1_out", + "HBM_MC_X8Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + 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"NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA2_in", + "NOC_NPS4_X7Y0", + "portSideB0_out", + "HBM_MC_X14Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB2_out", + "HBM_MC_X3Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X3Y0", + "pc0_port0_out", + "NOC_NPS4_X1Y0", + "portSideB2_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X3Y0", + "pc0_port0_out", + "NOC_NPS4_X1Y0", + "portSideB2_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB2_out", + "HBM_MC_X3Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB3_out", + "HBM_MC_X3Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X3Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB3_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X3Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB3_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB3_out", + "HBM_MC_X3Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", + "portSideB1_out", + "HBM_MC_X4Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X4Y0", + "pc1_port0_out", + "NOC_NPS4_X2Y0", + "portSideB1_in", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port5_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X4Y0", + "pc1_port0_out", + "NOC_NPS4_X2Y0", + "portSideB1_in", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port5_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", + "portSideB1_out", + "HBM_MC_X4Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", + "portSideB0_out", + "HBM_MC_X4Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X4Y0", + "pc0_port0_out", + "NOC_NPS4_X2Y0", + "portSideB0_in", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port5_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X4Y0", + "pc0_port0_out", + "NOC_NPS4_X2Y0", + "portSideB0_in", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port5_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", + "portSideB0_out", + "HBM_MC_X4Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA2_in", + "NOC_NPS4_X4Y0", + "portSideB2_out", + "HBM_MC_X9Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X9Y0", + "pc0_port0_out", + "NOC_NPS4_X4Y0", + "portSideB2_in", + "NOC_NPS4_X4Y0", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port5_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X9Y0", + "pc0_port0_out", + "NOC_NPS4_X4Y0", + "portSideB2_in", + "NOC_NPS4_X4Y0", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port5_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA2_in", + "NOC_NPS4_X4Y0", + "portSideB2_out", + "HBM_MC_X9Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB0_out", + "HBM_MC_X2Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X2Y0", + "pc0_port0_out", + "NOC_NPS4_X1Y0", + "portSideB0_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X2Y0", + "pc0_port0_out", + "NOC_NPS4_X1Y0", + "portSideB0_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB0_out", + "HBM_MC_X2Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA2_in", + "NOC_NPS4_X5Y0", + "portSideB2_out", + "HBM_MC_X11Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X11Y0", + "pc0_port0_out", + "NOC_NPS4_X5Y0", + "portSideB2_in", + "NOC_NPS4_X5Y0", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port5_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X11Y0", + "pc0_port0_out", + "NOC_NPS4_X5Y0", + "portSideB2_in", + "NOC_NPS4_X5Y0", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port5_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA2_in", + "NOC_NPS4_X5Y0", + "portSideB2_out", + "HBM_MC_X11Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA2_in", + "NOC_NPS4_X4Y0", + "portSideB3_out", + "HBM_MC_X9Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X9Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB3_in", + "NOC_NPS4_X4Y0", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port5_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X9Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB3_in", + "NOC_NPS4_X4Y0", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port5_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA2_in", + "NOC_NPS4_X4Y0", + "portSideB3_out", + "HBM_MC_X9Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA2_in", + "NOC_NPS4_X5Y0", + "portSideB3_out", + "HBM_MC_X11Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X11Y0", + "pc1_port0_out", + "NOC_NPS4_X5Y0", + "portSideB3_in", + "NOC_NPS4_X5Y0", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port5_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X11Y0", + "pc1_port0_out", + "NOC_NPS4_X5Y0", + "portSideB3_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port5_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB3_out", + "HBM_MC_X11Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB3_out", + "HBM_MC_X7Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X7Y0", + "pc1_port0_out", + "NOC_NPS4_X3Y0", + "portSideB3_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X7Y0", + "pc1_port0_out", + "NOC_NPS4_X3Y0", + "portSideB3_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB3_out", + "HBM_MC_X7Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA2_in", + "NOC_NPS4_X6Y0", + "portSideB3_out", + "HBM_MC_X13Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X13Y0", + "pc1_port0_out", + "NOC_NPS4_X6Y0", + "portSideB3_in", + "NOC_NPS4_X6Y0", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port5_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X13Y0", + "pc1_port0_out", + "NOC_NPS4_X6Y0", + "portSideB3_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA1_in", + "NOC_NPS4_X6Y0", + "portSideB3_out", + "HBM_MC_X13Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB2_out", + "HBM_MC_X7Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X7Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB2_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X7Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB2_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB2_out", + "HBM_MC_X7Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port2_out", + "NOC_NPS5555_X13Y0", + "port0_in", + "NOC_NPS5555_X13Y0", + "port2_out", + "NOC_NPS5555_X15Y0", + "port0_in", + "NOC_NPS5555_X15Y0", + "port2_out", + "NOC_NPS5555_X17Y0", + "port0_in", + "NOC_NPS5555_X17Y0", + "port3_out", + "NOC_NPS5555_X17Y1", + "port1_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA2_in", + "NOC_NPS4_X6Y0", + "portSideB2_out", + "HBM_MC_X13Y0", + "pc0_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X13Y0", + "pc0_port0_out", + "NOC_NPS4_X6Y0", + "portSideB2_in", + "NOC_NPS4_X6Y0", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port5_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port1_out", + "NOC_NPS5555_X17Y0", + "port3_in", + "NOC_NPS5555_X17Y0", + "port0_out", + "NOC_NPS5555_X15Y0", + "port2_in", + "NOC_NPS5555_X15Y0", + "port0_out", + "NOC_NPS5555_X13Y0", + "port2_in", + "NOC_NPS5555_X13Y0", + "port0_out", + "NOC_NPS5555_X11Y0", + "port2_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X13Y0", + "pc0_port0_out", + "NOC_NPS4_X6Y0", + "portSideB2_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA1_in", + "NOC_NPS4_X6Y0", + "portSideB2_out", + "HBM_MC_X13Y0", + "pc0_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB1_out", + "HBM_MC_X2Y0", + "pc1_port0_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X2Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB1_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X2Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB1_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port1_out", + "NOC_NPS5555_X7Y0", + "port3_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port3_out", + "NOC_NPS5555_X7Y1", + "port1_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB1_out", + "HBM_MC_X2Y0", + "pc1_port0_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/M00_AXI_nsu/bd_6ff4_M00_AXI_nsu_0_top_INST/NOC_NSU512_INST", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 5, + "WriteBW": 5, + "ReadAchievedBW": 5, + "WriteAchievedBW": 5, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "NOC_NSU512_X1Y6", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port1_out", + "NOC_NPS_VNOC_X1Y2", + "port1_in", + "NOC_NPS_VNOC_X1Y2", + "port2_out", + "NOC_NPS_VNOC_X1Y4", + "port0_in", + "NOC_NPS_VNOC_X1Y4", + "port2_out", + "NOC_NPS_VNOC_X1Y6", + "port0_in", + "NOC_NPS_VNOC_X1Y6", + "port2_out", + "NOC_NPS_VNOC_X1Y8", + "port0_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port3_out", + "NOC_NSU512_X1Y6", + "req" + ], + "RequiredBW": 5, + "AchievedBW": 5, + "RequiredLatency": 300, + "AchievedLatency": 40 + }, + { + "PhyInstanceStart": "NOC_NSU512_X1Y6", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "NOC_NSU512_X1Y6", + "resp", + "NOC_NPS_VNOC_X1Y12", + "port3_in", + "NOC_NPS_VNOC_X1Y12", + "port1_out", + "NOC_NPS_VNOC_X1Y13", + "port1_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 1, + "AchievedBW": 1, + "RequiredLatency": 300, + "AchievedLatency": 40 + }, + { + "PhyInstanceStart": "NOC_NSU512_X1Y6", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "NOC_NSU512_X1Y6", + "resp", + "NOC_NPS_VNOC_X1Y12", + "port3_in", + "NOC_NPS_VNOC_X1Y12", + "port1_out", + "NOC_NPS_VNOC_X1Y13", + "port1_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port1_out", + "NOC_NPS5555_X11Y0", + "port3_in", + "NOC_NPS5555_X11Y0", + "port0_out", + "NOC_NPS5555_X9Y0", + "port2_in", + "NOC_NPS5555_X9Y0", + "port0_out", + "NOC_NPS5555_X7Y0", + "port2_in", + "NOC_NPS5555_X7Y0", + "port0_out", + "NOC_NPS5555_X5Y0", + "port2_in", + "NOC_NPS5555_X5Y0", + "port0_out", + "NOC_NPS5555_X3Y0", + "port2_in", + "NOC_NPS5555_X3Y0", + "port0_out", + "NOC_NPS5555_X1Y0", + "port2_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 5, + "AchievedBW": 5, + "RequiredLatency": 300, + "AchievedLatency": 40 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "NOC_NSU512_X1Y6", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port2_out", + "NOC_NPS5555_X3Y0", + "port0_in", + "NOC_NPS5555_X3Y0", + "port2_out", + "NOC_NPS5555_X5Y0", + "port0_in", + "NOC_NPS5555_X5Y0", + "port2_out", + "NOC_NPS5555_X7Y0", + "port0_in", + "NOC_NPS5555_X7Y0", + "port2_out", + "NOC_NPS5555_X9Y0", + "port0_in", + "NOC_NPS5555_X9Y0", + "port2_out", + "NOC_NPS5555_X11Y0", + "port0_in", + "NOC_NPS5555_X11Y0", + "port3_out", + "NOC_NPS5555_X11Y1", + "port1_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port1_out", + "NOC_NPS_VNOC_X1Y4", + "port1_in", + "NOC_NPS_VNOC_X1Y4", + "port2_out", + "NOC_NPS_VNOC_X1Y6", + "port0_in", + "NOC_NPS_VNOC_X1Y6", + "port2_out", + "NOC_NPS_VNOC_X1Y8", + "port0_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port3_out", + "NOC_NSU512_X1Y6", + "req" + ], + "RequiredBW": 1, + "AchievedBW": 1, + "RequiredLatency": 300, + "AchievedLatency": 40 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_1/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "DDRMC_X1Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port0_out", + "NOC_NPS5555_X0Y1", + "port0_in", + "NOC_NPS5555_X0Y1", + "port1_out", + "NOC_NPS5555_X0Y0", + "port3_in", + "NOC_NPS5555_X0Y0", + "port2_out", + "NOC_NPS5555_X2Y0", + "port0_in", + "NOC_NPS5555_X2Y0", + "port2_out", + "NOC_NPS5555_X4Y0", + "port0_in", + "NOC_NPS5555_X4Y0", + "port2_out", + "NOC_NPS5555_X6Y0", + "port0_in", + "NOC_NPS5555_X6Y0", + "port2_out", + "NOC_NPS5555_X8Y0", + "port0_in", + "NOC_NPS5555_X8Y0", + "port1_out", + "DDRMC_X1Y0", + "Port0_req" + ], + "RequiredBW": 850, + "AchievedBW": 850, + "RequiredLatency": 300, + "AchievedLatency": 24 + }, + { + "PhyInstanceStart": "DDRMC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "DDRMC_X1Y0", + "Port0_resp", + "NOC_NPS5555_X8Y0", + "port1_in", + "NOC_NPS5555_X8Y0", + "port0_out", + "NOC_NPS5555_X6Y0", + "port2_in", + "NOC_NPS5555_X6Y0", + "port0_out", + "NOC_NPS5555_X4Y0", + "port2_in", + "NOC_NPS5555_X4Y0", + "port0_out", + "NOC_NPS5555_X2Y0", + "port2_in", + "NOC_NPS5555_X2Y0", + "port0_out", + "NOC_NPS5555_X0Y0", + "port2_in", + "NOC_NPS5555_X0Y0", + "port3_out", + "NOC_NPS5555_X0Y1", + "port1_in", + "NOC_NPS5555_X0Y1", + "port0_out", + "NOC_NPS5555_X1Y0", + "port0_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 24 + }, + { + "PhyInstanceStart": "DDRMC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "DDRMC_X1Y0", + "Port0_resp", + "NOC_NPS5555_X8Y0", + "port1_in", + "NOC_NPS5555_X8Y0", + "port0_out", + "NOC_NPS5555_X6Y0", + "port2_in", + "NOC_NPS5555_X6Y0", + "port0_out", + "NOC_NPS5555_X4Y0", + "port2_in", + "NOC_NPS5555_X4Y0", + "port0_out", + "NOC_NPS5555_X2Y0", + "port2_in", + "NOC_NPS5555_X2Y0", + "port0_out", + "NOC_NPS5555_X0Y0", + "port2_in", + "NOC_NPS5555_X0Y0", + "port3_out", + "NOC_NPS5555_X0Y1", + "port1_in", + "NOC_NPS5555_X0Y1", + "port0_out", + "NOC_NPS5555_X1Y0", + "port0_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 800, + "AchievedBW": 800, + "RequiredLatency": 300, + "AchievedLatency": 24 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "DDRMC_X1Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port0_out", + "NOC_NPS5555_X0Y1", + "port0_in", + "NOC_NPS5555_X0Y1", + "port1_out", + "NOC_NPS5555_X0Y0", + "port3_in", + "NOC_NPS5555_X0Y0", + "port2_out", + "NOC_NPS5555_X2Y0", + "port0_in", + "NOC_NPS5555_X2Y0", + "port2_out", + "NOC_NPS5555_X4Y0", + "port0_in", + "NOC_NPS5555_X4Y0", + "port2_out", + "NOC_NPS5555_X6Y0", + "port0_in", + "NOC_NPS5555_X6Y0", + "port2_out", + "NOC_NPS5555_X8Y0", + "port0_in", + "NOC_NPS5555_X8Y0", + "port1_out", + "DDRMC_X1Y0", + "Port0_req" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 24 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S00_AXI_nmu/bd_6ff4_S00_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port0_out", + "NOC_NPS5555_X0Y1", + "port0_in", + "NOC_NPS5555_X0Y1", + "port1_out", + "NOC_NPS5555_X0Y0", + "port3_in", + "NOC_NPS5555_X0Y0", + "port2_out", + "NOC_NPS5555_X2Y0", + "port0_in", + "NOC_NPS5555_X2Y0", + "port3_out", + "DDRMC_X0Y0", + "Port0_req" + ], + "RequiredBW": 850, + "AchievedBW": 850, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "DDRMC_X0Y0", + "Port0_resp", + "NOC_NPS5555_X2Y0", + "port3_in", + "NOC_NPS5555_X2Y0", + "port0_out", + "NOC_NPS5555_X0Y0", + "port2_in", + "NOC_NPS5555_X0Y0", + "port3_out", + "NOC_NPS5555_X0Y1", + "port1_in", + "NOC_NPS5555_X0Y1", + "port0_out", + "NOC_NPS5555_X1Y0", + "port0_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y0", + "VC": 6, + "CommType": "READ", + "Connections": [ + "DDRMC_X0Y0", + "Port0_resp", + "NOC_NPS5555_X2Y0", + "port3_in", + "NOC_NPS5555_X2Y0", + "port0_out", + "NOC_NPS5555_X0Y0", + "port2_in", + "NOC_NPS5555_X0Y0", + "port3_out", + "NOC_NPS5555_X0Y1", + "port1_in", + "NOC_NPS5555_X0Y1", + "port0_out", + "NOC_NPS5555_X1Y0", + "port0_in", + "NOC_NPS5555_X1Y0", + "port3_out", + "NOC_NMU128_X0Y0", + "resp_in" + ], + "RequiredBW": 800, + "AchievedBW": 800, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y0", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y0", + "req_out", + "NOC_NPS5555_X1Y0", + "port3_in", + "NOC_NPS5555_X1Y0", + "port0_out", + "NOC_NPS5555_X0Y1", + "port0_in", + "NOC_NPS5555_X0Y1", + "port1_out", + "NOC_NPS5555_X0Y0", + "port3_in", + "NOC_NPS5555_X0Y0", + "port2_out", + "NOC_NPS5555_X2Y0", + "port0_in", + "NOC_NPS5555_X2Y0", + "port3_out", + "DDRMC_X0Y0", + "Port0_req" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 18 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port4_out", + "NOC_NPS4_X5Y1", + "portSideA2_in", + "NOC_NPS4_X5Y1", + "portSideB1_out", + "HBM_MC_X10Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X10Y0", + "pc1_port1_out", + "NOC_NPS4_X5Y1", + "portSideB1_in", + "NOC_NPS4_X5Y1", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port4_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X10Y0", + "pc1_port1_out", + "NOC_NPS4_X5Y1", + "portSideB1_in", + "NOC_NPS4_X5Y1", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port4_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port4_out", + "NOC_NPS4_X5Y1", + "portSideA2_in", + "NOC_NPS4_X5Y1", + "portSideB1_out", + "HBM_MC_X10Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port4_out", + "NOC_NPS4_X5Y1", + "portSideA2_in", + "NOC_NPS4_X5Y1", + "portSideB0_out", + "HBM_MC_X10Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X10Y0", + "pc0_port1_out", + "NOC_NPS4_X5Y1", + "portSideB0_in", + "NOC_NPS4_X5Y1", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port4_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X10Y0", + "pc0_port1_out", + "NOC_NPS4_X5Y1", + "portSideB0_in", + "NOC_NPS4_X5Y1", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port4_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port4_out", + "NOC_NPS4_X5Y1", + "portSideA2_in", + "NOC_NPS4_X5Y1", + "portSideB0_out", + "HBM_MC_X10Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port4_out", + "NOC_NPS4_X2Y1", + "portSideA2_in", + "NOC_NPS4_X2Y1", + "portSideB2_out", + "HBM_MC_X5Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X5Y0", + "pc0_port1_out", + "NOC_NPS4_X2Y1", + "portSideB2_in", + "NOC_NPS4_X2Y1", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port4_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X5Y0", + "pc0_port1_out", + "NOC_NPS4_X2Y1", + "portSideB2_in", + "NOC_NPS4_X2Y1", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port4_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port4_out", + "NOC_NPS4_X2Y1", + "portSideA2_in", + "NOC_NPS4_X2Y1", + "portSideB2_out", + "HBM_MC_X5Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port4_out", + "NOC_NPS4_X7Y1", + "portSideA2_in", + "NOC_NPS4_X7Y1", + "portSideB3_out", + "HBM_MC_X15Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X15Y0", + "pc1_port1_out", + "NOC_NPS4_X7Y1", + "portSideB3_in", + "NOC_NPS4_X7Y1", + "portSideA2_out", + "NOC_NPS6_X7Y2", + "port4_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X15Y0", + "pc1_port1_out", + "NOC_NPS4_X7Y1", + "portSideB3_in", + "NOC_NPS4_X7Y1", + "portSideA2_out", + "NOC_NPS6_X7Y2", + "port4_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port4_out", + "NOC_NPS4_X7Y1", + "portSideA2_in", + "NOC_NPS4_X7Y1", + "portSideB3_out", + "HBM_MC_X15Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port4_out", + "NOC_NPS4_X0Y1", + "portSideA2_in", + "NOC_NPS4_X0Y1", + "portSideB1_out", + "HBM_MC_X0Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X0Y0", + "pc1_port1_out", + "NOC_NPS4_X0Y1", + "portSideB1_in", + "NOC_NPS4_X0Y1", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port4_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X0Y0", + "pc1_port1_out", + "NOC_NPS4_X0Y1", + "portSideB1_in", + "NOC_NPS4_X0Y1", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port4_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port4_out", + "NOC_NPS4_X0Y1", + "portSideA2_in", + "NOC_NPS4_X0Y1", + "portSideB1_out", + "HBM_MC_X0Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port4_out", + "NOC_NPS4_X7Y1", + "portSideA1_in", + "NOC_NPS4_X7Y1", + "portSideB2_out", + "HBM_MC_X15Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X15Y0", + "pc0_port1_out", + "NOC_NPS4_X7Y1", + "portSideB2_in", + "NOC_NPS4_X7Y1", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port4_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X15Y0", + "pc0_port1_out", + "NOC_NPS4_X7Y1", + "portSideB2_in", + "NOC_NPS4_X7Y1", + "portSideA2_out", + "NOC_NPS6_X7Y2", + "port4_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port4_out", + "NOC_NPS4_X7Y1", + "portSideA2_in", + "NOC_NPS4_X7Y1", + "portSideB2_out", + "HBM_MC_X15Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port4_out", + "NOC_NPS4_X0Y1", + "portSideA2_in", + "NOC_NPS4_X0Y1", + "portSideB2_out", + "HBM_MC_X1Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X1Y0", + "pc0_port1_out", + "NOC_NPS4_X0Y1", + "portSideB2_in", + "NOC_NPS4_X0Y1", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port4_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X1Y0", + "pc0_port1_out", + "NOC_NPS4_X0Y1", + "portSideB2_in", + "NOC_NPS4_X0Y1", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port4_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port4_out", + "NOC_NPS4_X0Y1", + "portSideA2_in", + "NOC_NPS4_X0Y1", + "portSideB2_out", + "HBM_MC_X1Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port4_out", + "NOC_NPS4_X2Y1", + "portSideA2_in", + "NOC_NPS4_X2Y1", + "portSideB3_out", + "HBM_MC_X5Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X5Y0", + "pc1_port1_out", + "NOC_NPS4_X2Y1", + "portSideB3_in", + "NOC_NPS4_X2Y1", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port4_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X5Y0", + "pc1_port1_out", + "NOC_NPS4_X2Y1", + "portSideB3_in", + "NOC_NPS4_X2Y1", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port4_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port4_out", + "NOC_NPS4_X2Y1", + "portSideA2_in", + "NOC_NPS4_X2Y1", + "portSideB3_out", + "HBM_MC_X5Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port4_out", + "NOC_NPS4_X0Y1", + "portSideA2_in", + "NOC_NPS4_X0Y1", + "portSideB3_out", + "HBM_MC_X1Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X1Y0", + "pc1_port1_out", + "NOC_NPS4_X0Y1", + "portSideB3_in", + "NOC_NPS4_X0Y1", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port4_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X1Y0", + "pc1_port1_out", + "NOC_NPS4_X0Y1", + "portSideB3_in", + "NOC_NPS4_X0Y1", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port4_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port4_out", + "NOC_NPS4_X0Y1", + "portSideA2_in", + "NOC_NPS4_X0Y1", + "portSideB3_out", + "HBM_MC_X1Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port4_out", + "NOC_NPS4_X3Y1", + "portSideA1_in", + "NOC_NPS4_X3Y1", + "portSideB0_out", + "HBM_MC_X6Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 129 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X6Y0", + "pc0_port1_out", + "NOC_NPS4_X3Y1", + "portSideB0_in", + "NOC_NPS4_X3Y1", + "portSideA1_out", + "NOC_NPS6_X3Y1", + "port4_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 129 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X6Y0", + "pc0_port1_out", + "NOC_NPS4_X3Y1", + "portSideB0_in", + "NOC_NPS4_X3Y1", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port4_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port1_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port4_out", + "NOC_NPS4_X3Y1", + "portSideA2_in", + "NOC_NPS4_X3Y1", + "portSideB0_out", + "HBM_MC_X6Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port4_out", + "NOC_NPS4_X7Y1", + "portSideA1_in", + "NOC_NPS4_X7Y1", + "portSideB1_out", + "HBM_MC_X14Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X14Y0", + "pc1_port1_out", + "NOC_NPS4_X7Y1", + "portSideB1_in", + "NOC_NPS4_X7Y1", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port4_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X14Y0", + "pc1_port1_out", + "NOC_NPS4_X7Y1", + "portSideB1_in", + "NOC_NPS4_X7Y1", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port4_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port4_out", + "NOC_NPS4_X7Y1", + "portSideA1_in", + "NOC_NPS4_X7Y1", + "portSideB1_out", + "HBM_MC_X14Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port4_out", + "NOC_NPS4_X0Y1", + "portSideA2_in", + "NOC_NPS4_X0Y1", + "portSideB0_out", + "HBM_MC_X0Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X0Y0", + "pc0_port1_out", + "NOC_NPS4_X0Y1", + "portSideB0_in", + "NOC_NPS4_X0Y1", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port4_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X0Y0", + "pc0_port1_out", + "NOC_NPS4_X0Y1", + "portSideB0_in", + "NOC_NPS4_X0Y1", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port4_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port4_out", + "NOC_NPS4_X0Y1", + "portSideA2_in", + "NOC_NPS4_X0Y1", + "portSideB0_out", + "HBM_MC_X0Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port4_out", + "NOC_NPS4_X4Y1", + "portSideA2_in", + "NOC_NPS4_X4Y1", + "portSideB1_out", + "HBM_MC_X8Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X8Y0", + "pc1_port1_out", + "NOC_NPS4_X4Y1", + "portSideB1_in", + "NOC_NPS4_X4Y1", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port4_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X8Y0", + "pc1_port1_out", + "NOC_NPS4_X4Y1", + "portSideB1_in", + "NOC_NPS4_X4Y1", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port4_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port1_out", + "NOC_NPS_VNOC_X1Y16", + "port1_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port4_out", + "NOC_NPS4_X4Y1", + "portSideA2_in", + "NOC_NPS4_X4Y1", + "portSideB1_out", + "HBM_MC_X8Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA2_in", + "NOC_NPS4_X6Y1", + "portSideB0_out", + "HBM_MC_X12Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X12Y0", + "pc0_port1_out", + "NOC_NPS4_X6Y1", + "portSideB0_in", + "NOC_NPS4_X6Y1", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port4_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X12Y0", + "pc0_port1_out", + "NOC_NPS4_X6Y1", + "portSideB0_in", + "NOC_NPS4_X6Y1", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port4_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA1_in", + "NOC_NPS4_X6Y1", + "portSideB0_out", + "HBM_MC_X12Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port4_out", + "NOC_NPS4_X3Y1", + "portSideA1_in", + "NOC_NPS4_X3Y1", + "portSideB1_out", + "HBM_MC_X6Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 129 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X6Y0", + "pc1_port1_out", + "NOC_NPS4_X3Y1", + "portSideB1_in", + "NOC_NPS4_X3Y1", + "portSideA1_out", + "NOC_NPS6_X3Y1", + "port4_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 129 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X6Y0", + "pc1_port1_out", + "NOC_NPS4_X3Y1", + "portSideB1_in", + "NOC_NPS4_X3Y1", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port4_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port1_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port4_out", + "NOC_NPS4_X3Y1", + "portSideA2_in", + "NOC_NPS4_X3Y1", + "portSideB1_out", + "HBM_MC_X6Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA2_in", + "NOC_NPS4_X6Y1", + "portSideB1_out", + "HBM_MC_X12Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X12Y0", + "pc1_port1_out", + "NOC_NPS4_X6Y1", + "portSideB1_in", + "NOC_NPS4_X6Y1", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port4_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X12Y0", + "pc1_port1_out", + "NOC_NPS4_X6Y1", + "portSideB1_in", + "NOC_NPS4_X6Y1", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port4_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA1_in", + "NOC_NPS4_X6Y1", + "portSideB1_out", + "HBM_MC_X12Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port4_out", + "NOC_NPS4_X4Y1", + "portSideA2_in", + "NOC_NPS4_X4Y1", + "portSideB0_out", + "HBM_MC_X8Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X8Y0", + "pc0_port1_out", + "NOC_NPS4_X4Y1", + "portSideB0_in", + "NOC_NPS4_X4Y1", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port4_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X8Y0", + "pc0_port1_out", + "NOC_NPS4_X4Y1", + "portSideB0_in", + "NOC_NPS4_X4Y1", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port4_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port1_out", + "NOC_NPS_VNOC_X1Y16", + "port1_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port4_out", + "NOC_NPS4_X4Y1", + "portSideA2_in", + "NOC_NPS4_X4Y1", + "portSideB0_out", + "HBM_MC_X8Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port4_out", + "NOC_NPS4_X7Y1", + "portSideA1_in", + "NOC_NPS4_X7Y1", + "portSideB0_out", + "HBM_MC_X14Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X14Y0", + "pc0_port1_out", + "NOC_NPS4_X7Y1", + "portSideB0_in", + "NOC_NPS4_X7Y1", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port4_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X14Y0", + "pc0_port1_out", + "NOC_NPS4_X7Y1", + "portSideB0_in", + "NOC_NPS4_X7Y1", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port4_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 141 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port4_out", + "NOC_NPS4_X7Y1", + "portSideA1_in", + "NOC_NPS4_X7Y1", + "portSideB0_out", + "HBM_MC_X14Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 141 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port4_out", + "NOC_NPS4_X1Y1", + "portSideA2_in", + "NOC_NPS4_X1Y1", + "portSideB2_out", + "HBM_MC_X3Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X3Y0", + "pc0_port1_out", + "NOC_NPS4_X1Y1", + "portSideB2_in", + "NOC_NPS4_X1Y1", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port4_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X3Y0", + "pc0_port1_out", + "NOC_NPS4_X1Y1", + "portSideB2_in", + "NOC_NPS4_X1Y1", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port4_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port4_out", + "NOC_NPS4_X1Y1", + "portSideA2_in", + "NOC_NPS4_X1Y1", + "portSideB2_out", + "HBM_MC_X3Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port4_out", + "NOC_NPS4_X1Y1", + "portSideA2_in", + "NOC_NPS4_X1Y1", + "portSideB3_out", + "HBM_MC_X3Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X3Y0", + "pc1_port1_out", + "NOC_NPS4_X1Y1", + "portSideB3_in", + "NOC_NPS4_X1Y1", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port4_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X3Y0", + "pc1_port1_out", + "NOC_NPS4_X1Y1", + "portSideB3_in", + "NOC_NPS4_X1Y1", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port4_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port4_out", + "NOC_NPS4_X1Y1", + "portSideA2_in", + "NOC_NPS4_X1Y1", + "portSideB3_out", + "HBM_MC_X3Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port4_out", + "NOC_NPS4_X2Y1", + "portSideA2_in", + "NOC_NPS4_X2Y1", + "portSideB0_out", + "HBM_MC_X4Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X4Y0", + "pc0_port1_out", + "NOC_NPS4_X2Y1", + "portSideB0_in", + "NOC_NPS4_X2Y1", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port4_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X4Y0", + "pc0_port1_out", + "NOC_NPS4_X2Y1", + "portSideB0_in", + "NOC_NPS4_X2Y1", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port4_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port4_out", + "NOC_NPS4_X2Y1", + "portSideA2_in", + "NOC_NPS4_X2Y1", + "portSideB0_out", + "HBM_MC_X4Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port4_out", + "NOC_NPS4_X4Y1", + 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"port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X9Y0", + "pc0_port1_out", + "NOC_NPS4_X4Y1", + "portSideB2_in", + "NOC_NPS4_X4Y1", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port4_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port4_out", + "NOC_NPS4_X4Y1", + "portSideA2_in", + "NOC_NPS4_X4Y1", + "portSideB2_out", + "HBM_MC_X9Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port4_out", + "NOC_NPS4_X2Y1", + "portSideA2_in", + "NOC_NPS4_X2Y1", + "portSideB1_out", + "HBM_MC_X4Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X4Y0", + "pc1_port1_out", + "NOC_NPS4_X2Y1", + "portSideB1_in", + "NOC_NPS4_X2Y1", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port4_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X4Y0", + "pc1_port1_out", + "NOC_NPS4_X2Y1", + "portSideB1_in", + "NOC_NPS4_X2Y1", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port4_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 127 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port4_out", + "NOC_NPS4_X2Y1", + "portSideA2_in", + "NOC_NPS4_X2Y1", + "portSideB1_out", + "HBM_MC_X4Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 127 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port4_out", + "NOC_NPS4_X4Y1", + "portSideA1_in", + "NOC_NPS4_X4Y1", + "portSideB3_out", + "HBM_MC_X9Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X9Y0", + "pc1_port1_out", + "NOC_NPS4_X4Y1", + "portSideB3_in", + "NOC_NPS4_X4Y1", + "portSideA1_out", + "NOC_NPS6_X4Y1", + "port4_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X9Y0", + "pc1_port1_out", + "NOC_NPS4_X4Y1", + "portSideB3_in", + "NOC_NPS4_X4Y1", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port4_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 133 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port4_out", + "NOC_NPS4_X4Y1", + "portSideA2_in", + "NOC_NPS4_X4Y1", + "portSideB3_out", + "HBM_MC_X9Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 133 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port4_out", + "NOC_NPS4_X5Y1", + "portSideA2_in", + "NOC_NPS4_X5Y1", + "portSideB3_out", + "HBM_MC_X11Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X11Y0", + "pc1_port1_out", + "NOC_NPS4_X5Y1", + "portSideB3_in", + "NOC_NPS4_X5Y1", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port4_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X11Y0", + "pc1_port1_out", + "NOC_NPS4_X5Y1", + "portSideB3_in", + "NOC_NPS4_X5Y1", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port4_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port4_out", + "NOC_NPS4_X5Y1", + "portSideA1_in", + "NOC_NPS4_X5Y1", + "portSideB3_out", + "HBM_MC_X11Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port4_out", + "NOC_NPS4_X5Y1", + "portSideA2_in", + "NOC_NPS4_X5Y1", + "portSideB2_out", + "HBM_MC_X11Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X11Y0", + "pc0_port1_out", + "NOC_NPS4_X5Y1", + "portSideB2_in", + "NOC_NPS4_X5Y1", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port4_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X11Y0", + "pc0_port1_out", + "NOC_NPS4_X5Y1", + "portSideB2_in", + "NOC_NPS4_X5Y1", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port4_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 135 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port4_out", + "NOC_NPS4_X5Y1", + "portSideA2_in", + "NOC_NPS4_X5Y1", + "portSideB2_out", + "HBM_MC_X11Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 135 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port4_out", + "NOC_NPS4_X3Y1", + "portSideA2_in", + "NOC_NPS4_X3Y1", + "portSideB3_out", + "HBM_MC_X7Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X7Y0", + "pc1_port1_out", + "NOC_NPS4_X3Y1", + "portSideB3_in", + "NOC_NPS4_X3Y1", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port4_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X7Y0", + "pc1_port1_out", + "NOC_NPS4_X3Y1", + "portSideB3_in", + "NOC_NPS4_X3Y1", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port4_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port4_out", + "NOC_NPS4_X3Y1", + "portSideA2_in", + "NOC_NPS4_X3Y1", + "portSideB3_out", + "HBM_MC_X7Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + 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"port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA2_in", + "NOC_NPS4_X6Y1", + "portSideB2_out", + "HBM_MC_X13Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X13Y0", + "pc0_port1_out", + "NOC_NPS4_X6Y1", + "portSideB2_in", + "NOC_NPS4_X6Y1", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port4_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", 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"NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA1_in", + "NOC_NPS4_X6Y1", + "portSideB2_out", + "HBM_MC_X13Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port4_out", + "NOC_NPS4_X3Y1", + "portSideA2_in", + "NOC_NPS4_X3Y1", + "portSideB2_out", + "HBM_MC_X7Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X7Y0", + "pc0_port1_out", + "NOC_NPS4_X3Y1", + "portSideB2_in", + "NOC_NPS4_X3Y1", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port4_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X7Y0", + "pc0_port1_out", + "NOC_NPS4_X3Y1", + "portSideB2_in", + "NOC_NPS4_X3Y1", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port4_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 131 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port4_out", + "NOC_NPS4_X3Y1", + "portSideA2_in", + "NOC_NPS4_X3Y1", + "portSideB2_out", + "HBM_MC_X7Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 131 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port4_out", + "NOC_NPS4_X1Y1", + "portSideA2_in", + "NOC_NPS4_X1Y1", + "portSideB1_out", + "HBM_MC_X2Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X2Y0", + "pc1_port1_out", + "NOC_NPS4_X1Y1", + "portSideB1_in", + "NOC_NPS4_X1Y1", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port4_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X2Y0", + "pc1_port1_out", + "NOC_NPS4_X1Y1", + "portSideB1_in", + "NOC_NPS4_X1Y1", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port4_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port4_out", + "NOC_NPS4_X1Y1", + "portSideA2_in", + "NOC_NPS4_X1Y1", + "portSideB1_out", + "HBM_MC_X2Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port4_out", + "NOC_NPS4_X1Y1", + "portSideA2_in", + "NOC_NPS4_X1Y1", + "portSideB0_out", + "HBM_MC_X2Y0", + "pc0_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X2Y0", + "pc0_port1_out", + "NOC_NPS4_X1Y1", + "portSideB0_in", + "NOC_NPS4_X1Y1", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port4_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X2Y0", + "pc0_port1_out", + "NOC_NPS4_X1Y1", + "portSideB0_in", + "NOC_NPS4_X1Y1", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port4_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port3_out", + "NOC_NCRB_X0Y0", + "port1_in", + "NOC_NCRB_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y36", + "port2_in", + "NOC_NPS_VNOC_X0Y36", + "port0_out", + "NOC_NPS_VNOC_X0Y34", + "port2_in", + "NOC_NPS_VNOC_X0Y34", + "port0_out", + "NOC_NPS_VNOC_X0Y32", + "port2_in", + "NOC_NPS_VNOC_X0Y32", + "port0_out", + "NOC_NPS_VNOC_X0Y30", + "port2_in", + "NOC_NPS_VNOC_X0Y30", + "port0_out", + "NOC_NPS_VNOC_X0Y28", + "port2_in", + "NOC_NPS_VNOC_X0Y28", + "port0_out", + "NOC_NPS_VNOC_X0Y26", + "port2_in", + "NOC_NPS_VNOC_X0Y26", + "port0_out", + "NOC_NPS7575_X4Y6", + "port1_in", + "NOC_NPS7575_X4Y6", + "port3_out", + "NOC_NIDB_X0Y7", + "port0_in", + "NOC_NIDB_X0Y7", + "port1_out", + "NOC_NIDB_X0Y5", + "port1_in", + "NOC_NIDB_X0Y5", + "port0_out", + "NOC_NPS7575_X4Y4", + "port3_in", + "NOC_NPS7575_X4Y4", + "port1_out", + "NOC_NPS_VNOC_X0Y24", + "port2_in", + "NOC_NPS_VNOC_X0Y24", + "port0_out", + "NOC_NPS_VNOC_X0Y22", + "port2_in", + "NOC_NPS_VNOC_X0Y22", + "port0_out", + "NOC_NPS_VNOC_X0Y20", + "port2_in", + "NOC_NPS_VNOC_X0Y20", + "port0_out", + "NOC_NPS_VNOC_X0Y18", + "port2_in", + "NOC_NPS_VNOC_X0Y18", + "port0_out", + "NOC_NPS_VNOC_X0Y16", + "port2_in", + "NOC_NPS_VNOC_X0Y16", + "port0_out", + "NOC_NPS_VNOC_X0Y14", + "port2_in", + "NOC_NPS_VNOC_X0Y14", + "port0_out", + "NOC_NPS7575_X4Y2", + "port1_in", + "NOC_NPS7575_X4Y2", + "port3_out", + "NOC_NIDB_X0Y3", + "port0_in", + "NOC_NIDB_X0Y3", + "port1_out", + "NOC_NIDB_X0Y1", + "port1_in", + "NOC_NIDB_X0Y1", + "port0_out", + "NOC_NPS7575_X0Y0", + "port3_in", + "NOC_NPS7575_X0Y0", + "port1_out", + "NOC_NPS_VNOC_X0Y12", + "port2_in", + "NOC_NPS_VNOC_X0Y12", + "port0_out", + "NOC_NPS_VNOC_X0Y10", + "port2_in", + "NOC_NPS_VNOC_X0Y10", + "port0_out", + "NOC_NPS_VNOC_X0Y8", + "port2_in", + "NOC_NPS_VNOC_X0Y8", + "port0_out", + "NOC_NPS_VNOC_X0Y6", + "port2_in", + "NOC_NPS_VNOC_X0Y6", + "port0_out", + "NOC_NPS_VNOC_X0Y4", + "port2_in", + "NOC_NPS_VNOC_X0Y4", + "port0_out", + "NOC_NPS_VNOC_X0Y2", + "port2_in", + "NOC_NPS_VNOC_X0Y2", + "port0_out", + "NOC_NPS_VNOC_X0Y0", + "port2_in", + "NOC_NPS_VNOC_X0Y0", + "port0_out", + "NOC_NPS5555_X7Y1", + "port2_in", + "NOC_NPS5555_X7Y1", + "port3_out", + "NOC_NPS5555_X7Y2", + "port1_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 125 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port1_out", + "NOC_NPS5555_X7Y1", + "port3_in", + "NOC_NPS5555_X7Y1", + "port2_out", + "NOC_NPS_VNOC_X0Y0", + "port0_in", + "NOC_NPS_VNOC_X0Y0", + "port2_out", + "NOC_NPS_VNOC_X0Y2", + "port0_in", + "NOC_NPS_VNOC_X0Y2", + "port2_out", + "NOC_NPS_VNOC_X0Y4", + "port0_in", + "NOC_NPS_VNOC_X0Y4", + "port2_out", + "NOC_NPS_VNOC_X0Y6", + "port0_in", + "NOC_NPS_VNOC_X0Y6", + "port2_out", + "NOC_NPS_VNOC_X0Y8", + "port0_in", + "NOC_NPS_VNOC_X0Y8", + "port2_out", + "NOC_NPS_VNOC_X0Y10", + "port0_in", + "NOC_NPS_VNOC_X0Y10", + "port2_out", + "NOC_NPS_VNOC_X0Y12", + "port0_in", + "NOC_NPS_VNOC_X0Y12", + "port2_out", + "NOC_NPS7575_X0Y0", + "port1_in", + "NOC_NPS7575_X0Y0", + "port3_out", + "NOC_NIDB_X0Y1", + "port0_in", + "NOC_NIDB_X0Y1", + "port1_out", + "NOC_NIDB_X0Y3", + "port1_in", + "NOC_NIDB_X0Y3", + "port0_out", + "NOC_NPS7575_X4Y2", + "port3_in", + "NOC_NPS7575_X4Y2", + "port1_out", + "NOC_NPS_VNOC_X0Y14", + "port0_in", + "NOC_NPS_VNOC_X0Y14", + "port2_out", + "NOC_NPS_VNOC_X0Y16", + "port0_in", + "NOC_NPS_VNOC_X0Y16", + "port2_out", + "NOC_NPS_VNOC_X0Y18", + "port0_in", + "NOC_NPS_VNOC_X0Y18", + "port2_out", + "NOC_NPS_VNOC_X0Y20", + "port0_in", + "NOC_NPS_VNOC_X0Y20", + "port2_out", + "NOC_NPS_VNOC_X0Y22", + "port0_in", + "NOC_NPS_VNOC_X0Y22", + "port2_out", + "NOC_NPS_VNOC_X0Y24", + "port0_in", + "NOC_NPS_VNOC_X0Y24", + "port2_out", + "NOC_NPS7575_X4Y4", + "port1_in", + "NOC_NPS7575_X4Y4", + "port3_out", + "NOC_NIDB_X0Y5", + "port0_in", + "NOC_NIDB_X0Y5", + "port1_out", + "NOC_NIDB_X0Y7", + "port1_in", + "NOC_NIDB_X0Y7", + "port0_out", + "NOC_NPS7575_X4Y6", + "port3_in", + "NOC_NPS7575_X4Y6", + "port1_out", + "NOC_NPS_VNOC_X0Y26", + "port0_in", + "NOC_NPS_VNOC_X0Y26", + "port2_out", + "NOC_NPS_VNOC_X0Y28", + "port0_in", + "NOC_NPS_VNOC_X0Y28", + "port2_out", + "NOC_NPS_VNOC_X0Y30", + "port0_in", + "NOC_NPS_VNOC_X0Y30", + "port2_out", + "NOC_NPS_VNOC_X0Y32", + "port0_in", + "NOC_NPS_VNOC_X0Y32", + "port2_out", + "NOC_NPS_VNOC_X0Y34", + "port0_in", + "NOC_NPS_VNOC_X0Y34", + "port2_out", + "NOC_NPS_VNOC_X0Y36", + "port0_in", + "NOC_NPS_VNOC_X0Y36", + "port2_out", + "NOC_NCRB_X0Y1", + "port1_in", + "NOC_NCRB_X0Y1", + "port1_out", + "NOC_NPS5555_X5Y6", + "port3_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port4_out", + "NOC_NPS4_X1Y1", + "portSideA2_in", + "NOC_NPS4_X1Y1", + "portSideB0_out", + "HBM_MC_X2Y0", + "pc0_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 125 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/M00_AXI_nsu/bd_6ff4_M00_AXI_nsu_0_top_INST/NOC_NSU512_INST", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 5, + "WriteBW": 5, + "ReadAchievedBW": 5, + "WriteAchievedBW": 5, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "NOC_NSU512_X1Y6", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port1_out", + "NOC_NPS_VNOC_X1Y2", + "port1_in", + "NOC_NPS_VNOC_X1Y2", + "port2_out", + "NOC_NPS_VNOC_X1Y4", + "port0_in", + "NOC_NPS_VNOC_X1Y4", + "port2_out", + "NOC_NPS_VNOC_X1Y6", + "port0_in", + "NOC_NPS_VNOC_X1Y6", + "port2_out", + "NOC_NPS_VNOC_X1Y8", + "port0_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port3_out", + "NOC_NSU512_X1Y6", + "req" + ], + "RequiredBW": 5, + "AchievedBW": 5, + "RequiredLatency": 300, + "AchievedLatency": 40 + }, + { + "PhyInstanceStart": "NOC_NSU512_X1Y6", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "NOC_NSU512_X1Y6", + "resp", + "NOC_NPS_VNOC_X1Y12", + "port3_in", + "NOC_NPS_VNOC_X1Y12", + "port0_out", + "NOC_NPS_VNOC_X1Y10", + "port2_in", + "NOC_NPS_VNOC_X1Y10", + "port1_out", + "NOC_NPS_VNOC_X1Y11", + "port1_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 1, + "AchievedBW": 1, + "RequiredLatency": 300, + "AchievedLatency": 40 + }, + { + "PhyInstanceStart": "NOC_NSU512_X1Y6", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "NOC_NSU512_X1Y6", + "resp", + "NOC_NPS_VNOC_X1Y12", + "port3_in", + "NOC_NPS_VNOC_X1Y12", + "port1_out", + "NOC_NPS_VNOC_X1Y13", + "port1_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 5, + "AchievedBW": 5, + "RequiredLatency": 300, + "AchievedLatency": 40 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "NOC_NSU512_X1Y6", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port1_out", + "NOC_NPS_VNOC_X1Y2", + "port1_in", + "NOC_NPS_VNOC_X1Y2", + "port2_out", + "NOC_NPS_VNOC_X1Y4", + "port0_in", + "NOC_NPS_VNOC_X1Y4", + "port2_out", + "NOC_NPS_VNOC_X1Y6", + "port0_in", + "NOC_NPS_VNOC_X1Y6", + "port2_out", + "NOC_NPS_VNOC_X1Y8", + "port0_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port3_out", + "NOC_NSU512_X1Y6", + "req" + ], + "RequiredBW": 1, + "AchievedBW": 1, + "RequiredLatency": 300, + "AchievedLatency": 40 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT3", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port2_out", + "NOC_NPS_VNOC_X2Y22", + "port0_in", + "NOC_NPS_VNOC_X2Y22", + "port2_out", + "NOC_NPS_VNOC_X2Y24", + "port0_in", + "NOC_NPS_VNOC_X2Y24", + "port2_out", + "NOC_NPS7575_X6Y4", + "port1_in", + "NOC_NPS7575_X6Y4", + "port3_out", + "NOC_NIDB_X2Y5", + "port0_in", + "NOC_NIDB_X2Y5", + "port1_out", + "NOC_NIDB_X2Y7", + "port1_in", + "NOC_NIDB_X2Y7", + "port0_out", + "NOC_NPS7575_X6Y6", + "port3_in", + "NOC_NPS7575_X6Y6", + "port1_out", + "NOC_NPS_VNOC_X2Y26", + "port0_in", + "NOC_NPS_VNOC_X2Y26", + "port2_out", + "NOC_NPS_VNOC_X2Y28", + "port0_in", + "NOC_NPS_VNOC_X2Y28", + "port2_out", + "NOC_NPS_VNOC_X2Y30", + "port0_in", + "NOC_NPS_VNOC_X2Y30", + "port2_out", + "NOC_NPS_VNOC_X2Y32", + "port0_in", + "NOC_NPS_VNOC_X2Y32", + "port2_out", + "NOC_NPS_VNOC_X2Y34", + "port0_in", + "NOC_NPS_VNOC_X2Y34", + "port2_out", + "NOC_NPS_VNOC_X2Y36", + "port0_in", + "NOC_NPS_VNOC_X2Y36", + "port2_out", + "NOC_NCRB_X2Y1", + "port1_in", + "NOC_NCRB_X2Y1", + "port1_out", + "NOC_NPS5555_X7Y6", + "port3_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA2_in", + "NOC_NPS4_X6Y1", + "portSideB3_out", + "HBM_MC_X13Y0", + "pc1_port1_in" + ], + "RequiredBW": 165, + "AchievedBW": 165, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X13Y0", + "pc1_port1_out", + "NOC_NPS4_X6Y1", + "portSideB3_in", + "NOC_NPS4_X6Y1", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port4_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port3_out", + "NOC_NCRB_X2Y0", + "port1_in", + "NOC_NCRB_X2Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y36", + "port2_in", + "NOC_NPS_VNOC_X2Y36", + "port0_out", + "NOC_NPS_VNOC_X2Y34", + "port2_in", + "NOC_NPS_VNOC_X2Y34", + "port0_out", + "NOC_NPS_VNOC_X2Y32", + "port2_in", + "NOC_NPS_VNOC_X2Y32", + "port0_out", + "NOC_NPS_VNOC_X2Y30", + "port2_in", + "NOC_NPS_VNOC_X2Y30", + "port0_out", + "NOC_NPS_VNOC_X2Y28", + "port2_in", + "NOC_NPS_VNOC_X2Y28", + "port0_out", + "NOC_NPS_VNOC_X2Y26", + "port2_in", + "NOC_NPS_VNOC_X2Y26", + "port0_out", + "NOC_NPS7575_X6Y6", + "port1_in", + "NOC_NPS7575_X6Y6", + "port3_out", + "NOC_NIDB_X2Y7", + "port0_in", + "NOC_NIDB_X2Y7", + "port1_out", + "NOC_NIDB_X2Y5", + "port1_in", + "NOC_NIDB_X2Y5", + "port0_out", + "NOC_NPS7575_X6Y4", + "port3_in", + "NOC_NPS7575_X6Y4", + "port1_out", + "NOC_NPS_VNOC_X2Y24", + "port2_in", + "NOC_NPS_VNOC_X2Y24", + "port0_out", + "NOC_NPS_VNOC_X2Y22", + "port2_in", + "NOC_NPS_VNOC_X2Y22", + "port0_out", + "NOC_NPS_VNOC_X2Y20", + "port2_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "HBM_MC_X13Y0", + "pc1_port1_out", + "NOC_NPS4_X6Y1", + "portSideB3_in", + "NOC_NPS4_X6Y1", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port4_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port3_out", + "NOC_NPS5555_X11Y2", + "port1_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 137 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port1_out", + "NOC_NPS5555_X11Y1", + "port3_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port4_out", + "NOC_NPS4_X6Y1", + "portSideA1_in", + "NOC_NPS4_X6Y1", + "portSideB3_out", + "HBM_MC_X13Y0", + "pc1_port1_in" + ], + "RequiredBW": 33, + "AchievedBW": 33, + "RequiredLatency": 300, + "AchievedLatency": 137 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port3_out", + "NOC_NPS5555_X0Y1", + "port3_in", + "NOC_NPS5555_X0Y1", + "port2_out", + "NOC_NPS5555_X2Y1", + "port0_in", + "NOC_NPS5555_X2Y1", + "port3_out", + "DDRMC_X0Y0", + "Port1_req" + ], + "RequiredBW": 850, + "AchievedBW": 850, + "RequiredLatency": 300, + "AchievedLatency": 16 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "DDRMC_X0Y0", + "Port1_resp", + "NOC_NPS5555_X2Y1", + "port3_in", + "NOC_NPS5555_X2Y1", + "port0_out", + "NOC_NPS5555_X0Y1", + "port2_in", + "NOC_NPS5555_X0Y1", + "port3_out", + "NOC_NPS5555_X1Y1", + "port3_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 16 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "DDRMC_X0Y0", + "Port1_resp", + "NOC_NPS5555_X2Y1", + "port3_in", + "NOC_NPS5555_X2Y1", + "port0_out", + "NOC_NPS5555_X0Y1", + "port2_in", + "NOC_NPS5555_X0Y1", + "port3_out", + "NOC_NPS5555_X1Y1", + "port3_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 800, + "AchievedBW": 800, + "RequiredLatency": 300, + "AchievedLatency": 16 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port3_out", + "NOC_NPS5555_X0Y1", + "port3_in", + "NOC_NPS5555_X0Y1", + "port2_out", + "NOC_NPS5555_X2Y1", + "port0_in", + "NOC_NPS5555_X2Y1", + "port3_out", + "DDRMC_X0Y0", + "Port1_req" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 16 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S01_AXI_nmu/bd_6ff4_S01_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_1/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT1", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "DDRMC_X1Y0", + "VC": 1, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port3_out", + "NOC_NPS5555_X0Y1", + "port3_in", + "NOC_NPS5555_X0Y1", + "port2_out", + "NOC_NPS5555_X2Y1", + "port0_in", + "NOC_NPS5555_X2Y1", + "port2_out", + "NOC_NPS5555_X4Y1", + "port0_in", + "NOC_NPS5555_X4Y1", + "port2_out", + "NOC_NPS5555_X6Y2", + "port0_in", + "NOC_NPS5555_X6Y2", + "port2_out", + "NOC_NPS5555_X8Y2", + "port0_in", + "NOC_NPS5555_X8Y2", + "port3_out", + "DDRMC_X1Y0", + "Port1_req" + ], + "RequiredBW": 850, + "AchievedBW": 850, + "RequiredLatency": 300, + "AchievedLatency": 22 + }, + { + "PhyInstanceStart": "DDRMC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 3, + "CommType": "WRITE_RESP", + "Connections": [ + "DDRMC_X1Y0", + "Port1_resp", + "NOC_NPS5555_X8Y2", + "port3_in", + "NOC_NPS5555_X8Y2", + "port0_out", + "NOC_NPS5555_X6Y2", + "port2_in", + "NOC_NPS5555_X6Y2", + "port0_out", + "NOC_NPS5555_X4Y1", + "port2_in", + "NOC_NPS5555_X4Y1", + "port0_out", + "NOC_NPS5555_X2Y1", + "port2_in", + "NOC_NPS5555_X2Y1", + "port0_out", + "NOC_NPS5555_X0Y1", + "port2_in", + "NOC_NPS5555_X0Y1", + "port3_out", + "NOC_NPS5555_X1Y1", + "port3_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 22 + }, + { + "PhyInstanceStart": "DDRMC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y1", + "VC": 2, + "CommType": "READ", + "Connections": [ + "DDRMC_X1Y0", + "Port1_resp", + "NOC_NPS5555_X8Y2", + "port3_in", + "NOC_NPS5555_X8Y2", + "port0_out", + "NOC_NPS5555_X6Y2", + "port2_in", + "NOC_NPS5555_X6Y2", + "port0_out", + "NOC_NPS5555_X4Y1", + "port2_in", + "NOC_NPS5555_X4Y1", + "port0_out", + "NOC_NPS5555_X2Y1", + "port2_in", + "NOC_NPS5555_X2Y1", + "port0_out", + "NOC_NPS5555_X0Y1", + "port2_in", + "NOC_NPS5555_X0Y1", + "port3_out", + "NOC_NPS5555_X1Y1", + "port3_in", + "NOC_NPS5555_X1Y1", + "port1_out", + "NOC_NMU128_X0Y1", + "resp_in" + ], + "RequiredBW": 800, + "AchievedBW": 800, + "RequiredLatency": 300, + "AchievedLatency": 22 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y1", + "PhyInstanceEnd": "DDRMC_X1Y0", + "VC": 0, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y1", + "req_out", + "NOC_NPS5555_X1Y1", + "port1_in", + "NOC_NPS5555_X1Y1", + "port3_out", + "NOC_NPS5555_X0Y1", + "port3_in", + "NOC_NPS5555_X0Y1", + "port2_out", + "NOC_NPS5555_X2Y1", + "port0_in", + "NOC_NPS5555_X2Y1", + "port2_out", + "NOC_NPS5555_X4Y1", + "port0_in", + "NOC_NPS5555_X4Y1", + "port2_out", + "NOC_NPS5555_X6Y2", + "port0_in", + "NOC_NPS5555_X6Y2", + "port2_out", + "NOC_NPS5555_X8Y2", + "port0_in", + "NOC_NPS5555_X8Y2", + "port3_out", + "DDRMC_X1Y0", + "Port1_req" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 22 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S02_AXI_nmu/bd_6ff4_S02_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_1/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y2", + "PhyInstanceEnd": "DDRMC_X1Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y2", + "req_out", + "NOC_NPS5555_X1Y1", + "port0_in", + "NOC_NPS5555_X1Y1", + "port3_out", + "NOC_NPS5555_X0Y1", + "port3_in", + "NOC_NPS5555_X0Y1", + "port1_out", + "NOC_NPS5555_X0Y0", + "port3_in", + "NOC_NPS5555_X0Y0", + "port2_out", + "NOC_NPS5555_X2Y0", + "port0_in", + "NOC_NPS5555_X2Y0", + "port2_out", + "NOC_NPS5555_X4Y0", + "port0_in", + "NOC_NPS5555_X4Y0", + "port2_out", + "NOC_NPS5555_X6Y0", + "port0_in", + "NOC_NPS5555_X6Y0", + "port2_out", + "NOC_NPS5555_X8Y0", + "port0_in", + "NOC_NPS5555_X8Y0", + "port1_out", + "DDRMC_X1Y0", + "Port0_req" + ], + "RequiredBW": 850, + "AchievedBW": 850, + "RequiredLatency": 300, + "AchievedLatency": 24 + }, + { + "PhyInstanceStart": "DDRMC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y2", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "DDRMC_X1Y0", + "Port0_resp", + "NOC_NPS5555_X8Y0", + "port1_in", + "NOC_NPS5555_X8Y0", + "port0_out", + "NOC_NPS5555_X6Y0", + "port2_in", + "NOC_NPS5555_X6Y0", + "port0_out", + "NOC_NPS5555_X4Y0", + "port2_in", + "NOC_NPS5555_X4Y0", + "port0_out", + "NOC_NPS5555_X2Y0", + "port2_in", + "NOC_NPS5555_X2Y0", + "port0_out", + "NOC_NPS5555_X0Y0", + "port2_in", + "NOC_NPS5555_X0Y0", + "port3_out", + "NOC_NPS5555_X0Y1", + "port1_in", + "NOC_NPS5555_X0Y1", + "port3_out", + "NOC_NPS5555_X1Y1", + "port3_in", + "NOC_NPS5555_X1Y1", + "port0_out", + "NOC_NMU128_X0Y2", + "resp_in" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 24 + }, + { + "PhyInstanceStart": "DDRMC_X1Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y2", + "VC": 6, + "CommType": "READ", + "Connections": [ + "DDRMC_X1Y0", + "Port0_resp", + "NOC_NPS5555_X8Y0", + "port1_in", + "NOC_NPS5555_X8Y0", + "port0_out", + "NOC_NPS5555_X6Y0", + "port2_in", + "NOC_NPS5555_X6Y0", + "port0_out", + "NOC_NPS5555_X4Y0", + "port2_in", + "NOC_NPS5555_X4Y0", + "port0_out", + "NOC_NPS5555_X2Y0", + "port2_in", + "NOC_NPS5555_X2Y0", + "port0_out", + "NOC_NPS5555_X0Y0", + "port2_in", + "NOC_NPS5555_X0Y0", + "port3_out", + "NOC_NPS5555_X0Y1", + "port1_in", + "NOC_NPS5555_X0Y1", + "port3_out", + "NOC_NPS5555_X1Y1", + "port3_in", + "NOC_NPS5555_X1Y1", + "port0_out", + "NOC_NMU128_X0Y2", + "resp_in" + ], + "RequiredBW": 800, + "AchievedBW": 800, + "RequiredLatency": 300, + "AchievedLatency": 24 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y2", + "PhyInstanceEnd": "DDRMC_X1Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y2", + "req_out", + "NOC_NPS5555_X1Y1", + "port0_in", + "NOC_NPS5555_X1Y1", + "port3_out", + "NOC_NPS5555_X0Y1", + "port3_in", + "NOC_NPS5555_X0Y1", + "port1_out", + "NOC_NPS5555_X0Y0", + "port3_in", + "NOC_NPS5555_X0Y0", + "port2_out", + "NOC_NPS5555_X2Y0", + "port0_in", + "NOC_NPS5555_X2Y0", + "port2_out", + "NOC_NPS5555_X4Y0", + "port0_in", + "NOC_NPS5555_X4Y0", + "port2_out", + "NOC_NPS5555_X6Y0", + "port0_in", + "NOC_NPS5555_X6Y0", + "port2_out", + "NOC_NPS5555_X8Y0", + "port0_in", + "NOC_NPS5555_X8Y0", + "port1_out", + "DDRMC_X1Y0", + "Port0_req" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 24 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S02_AXI_nmu/bd_6ff4_S02_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y2", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y2", + "req_out", + "NOC_NPS5555_X1Y1", + "port0_in", + "NOC_NPS5555_X1Y1", + "port3_out", + "NOC_NPS5555_X0Y1", + "port3_in", + "NOC_NPS5555_X0Y1", + "port1_out", + "NOC_NPS5555_X0Y0", + "port3_in", + "NOC_NPS5555_X0Y0", + "port2_out", + "NOC_NPS5555_X2Y0", + "port0_in", + "NOC_NPS5555_X2Y0", + "port3_out", + "DDRMC_X0Y0", + "Port0_req" + ], + "RequiredBW": 850, + "AchievedBW": 850, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y2", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "DDRMC_X0Y0", + "Port0_resp", + "NOC_NPS5555_X2Y0", + "port3_in", + "NOC_NPS5555_X2Y0", + "port0_out", + "NOC_NPS5555_X0Y0", + "port2_in", + "NOC_NPS5555_X0Y0", + "port3_out", + "NOC_NPS5555_X0Y1", + "port1_in", + "NOC_NPS5555_X0Y1", + "port3_out", + "NOC_NPS5555_X1Y1", + "port3_in", + "NOC_NPS5555_X1Y1", + "port0_out", + "NOC_NMU128_X0Y2", + "resp_in" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y2", + "VC": 6, + "CommType": "READ", + "Connections": [ + "DDRMC_X0Y0", + "Port0_resp", + "NOC_NPS5555_X2Y0", + "port3_in", + "NOC_NPS5555_X2Y0", + "port0_out", + "NOC_NPS5555_X0Y0", + "port2_in", + "NOC_NPS5555_X0Y0", + "port3_out", + "NOC_NPS5555_X0Y1", + "port1_in", + "NOC_NPS5555_X0Y1", + "port3_out", + "NOC_NPS5555_X1Y1", + "port3_in", + "NOC_NPS5555_X1Y1", + "port0_out", + "NOC_NMU128_X0Y2", + "resp_in" + ], + "RequiredBW": 800, + "AchievedBW": 800, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y2", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y2", + "req_out", + "NOC_NPS5555_X1Y1", + "port0_in", + "NOC_NPS5555_X1Y1", + "port3_out", + "NOC_NPS5555_X0Y1", + "port3_in", + "NOC_NPS5555_X0Y1", + "port1_out", + "NOC_NPS5555_X0Y0", + "port3_in", + "NOC_NPS5555_X0Y0", + "port2_out", + "NOC_NPS5555_X2Y0", + "port0_in", + "NOC_NPS5555_X2Y0", + "port3_out", + "DDRMC_X0Y0", + "Port0_req" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 18 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S03_AXI_rpu/bd_6ff4_S03_AXI_rpu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y3", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y3", + "req_out", + "NOC_NPS5555_X1Y0", + "port1_in", + "NOC_NPS5555_X1Y0", + "port0_out", + "NOC_NPS5555_X0Y1", + "port0_in", + "NOC_NPS5555_X0Y1", + "port1_out", + "NOC_NPS5555_X0Y0", + "port3_in", + "NOC_NPS5555_X0Y0", + "port2_out", + "NOC_NPS5555_X2Y0", + "port0_in", + "NOC_NPS5555_X2Y0", + "port3_out", + "DDRMC_X0Y0", + "Port0_req" + ], + "RequiredBW": 850, + "AchievedBW": 850, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y3", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "DDRMC_X0Y0", + "Port0_resp", + "NOC_NPS5555_X2Y0", + "port3_in", + "NOC_NPS5555_X2Y0", + "port0_out", + "NOC_NPS5555_X0Y0", + "port2_in", + "NOC_NPS5555_X0Y0", + "port3_out", + "NOC_NPS5555_X0Y1", + "port1_in", + "NOC_NPS5555_X0Y1", + "port0_out", + "NOC_NPS5555_X1Y0", + "port0_in", + "NOC_NPS5555_X1Y0", + "port1_out", + "NOC_NMU128_X0Y3", + "resp_in" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU128_X0Y3", + "VC": 6, + "CommType": "READ", + "Connections": [ + "DDRMC_X0Y0", + "Port0_resp", + "NOC_NPS5555_X2Y0", + "port3_in", + "NOC_NPS5555_X2Y0", + "port0_out", + "NOC_NPS5555_X0Y0", + "port2_in", + "NOC_NPS5555_X0Y0", + "port3_out", + "NOC_NPS5555_X0Y1", + "port1_in", + "NOC_NPS5555_X0Y1", + "port0_out", + "NOC_NPS5555_X1Y0", + "port0_in", + "NOC_NPS5555_X1Y0", + "port1_out", + "NOC_NMU128_X0Y3", + "resp_in" + ], + "RequiredBW": 800, + "AchievedBW": 800, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y3", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y3", + "req_out", + "NOC_NPS5555_X1Y0", + "port1_in", + "NOC_NPS5555_X1Y0", + "port0_out", + "NOC_NPS5555_X0Y1", + "port0_in", + "NOC_NPS5555_X0Y1", + "port1_out", + "NOC_NPS5555_X0Y0", + "port3_in", + "NOC_NPS5555_X0Y0", + "port2_out", + "NOC_NPS5555_X2Y0", + "port0_in", + "NOC_NPS5555_X2Y0", + "port3_out", + "DDRMC_X0Y0", + "Port0_req" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 18 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB1_out", + "HBM_MC_X10Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X10Y0", + "pc1_port0_out", + "NOC_NPS4_X5Y0", + "portSideB1_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port5_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X10Y0", + "pc1_port0_out", + "NOC_NPS4_X5Y0", + "portSideB1_in", + "NOC_NPS4_X5Y0", + "portSideA2_out", + "NOC_NPS6_X5Y2", + "port5_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port1_out", + "NOC_NPS6_X4Y2", + "port3_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port3_out", + "NOC_NPS5555_X7Y6", + "port1_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA2_in", + "NOC_NPS4_X5Y0", + "portSideB1_out", + "HBM_MC_X10Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA1_in", + "NOC_NPS4_X7Y0", + "portSideB2_out", + "HBM_MC_X15Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 119 + }, + { + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X15Y0", + "pc0_port0_out", + "NOC_NPS4_X7Y0", + "portSideB2_in", + "NOC_NPS4_X7Y0", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port5_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 119 + }, + { + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X15Y0", + "pc0_port0_out", + "NOC_NPS4_X7Y0", + "portSideB2_in", + "NOC_NPS4_X7Y0", + "portSideA0_out", + "NOC_NPS6_X7Y0", + "port5_in", + "NOC_NPS6_X7Y0", + "port0_out", + "NOC_NPS5555_X8Y3", + "port1_in", + "NOC_NPS5555_X8Y3", + "port2_out", + "NOC_NPS5555_X8Y4", + "port0_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 121 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port1_out", + "NOC_NPS6_X3Y0", + "port0_in", + "NOC_NPS6_X3Y0", + "port3_out", + "NOC_NPS6_X4Y0", + "port0_in", + "NOC_NPS6_X4Y0", + "port3_out", + "NOC_NPS5555_X7Y3", + "port0_in", + "NOC_NPS5555_X7Y3", + "port1_out", + "NOC_NPS6_X5Y0", + "port0_in", + "NOC_NPS6_X5Y0", + "port3_out", + "NOC_NPS6_X6Y0", + "port0_in", + "NOC_NPS6_X6Y0", + "port3_out", + "NOC_NPS5555_X8Y3", + "port0_in", + "NOC_NPS5555_X8Y3", + "port1_out", + "NOC_NPS6_X7Y0", + "port0_in", + "NOC_NPS6_X7Y0", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA0_in", + "NOC_NPS4_X7Y0", + "portSideB2_out", + "HBM_MC_X15Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 121 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB0_out", + "HBM_MC_X10Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X10Y0", + "pc0_port0_out", + "NOC_NPS4_X5Y0", + "portSideB0_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port5_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X10Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X10Y0", + "pc0_port0_out", + "NOC_NPS4_X5Y0", + "portSideB0_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port5_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X10Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB0_out", + "HBM_MC_X10Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA1_in", + "NOC_NPS4_X2Y0", + "portSideB2_out", + "HBM_MC_X5Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X5Y0", + "pc0_port0_out", + "NOC_NPS4_X2Y0", + "portSideB2_in", + "NOC_NPS4_X2Y0", + "portSideA1_out", + "NOC_NPS6_X2Y1", + "port5_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X5Y0", + "pc0_port0_out", + "NOC_NPS4_X2Y0", + "portSideB2_in", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port5_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", + "portSideB2_out", + "HBM_MC_X5Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA1_in", + "NOC_NPS4_X7Y0", + "portSideB3_out", + "HBM_MC_X15Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 119 + }, + { + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X15Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB3_in", + "NOC_NPS4_X7Y0", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port5_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 119 + }, + { + "PhyInstanceStart": "HBM_MC_X15Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X15Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB3_in", + "NOC_NPS4_X7Y0", + "portSideA2_out", + "NOC_NPS6_X7Y2", + "port5_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port1_out", + "NOC_NPS6_X4Y2", + "port3_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 121 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X15Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port3_out", + "NOC_NPS5555_X7Y6", + "port1_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA2_in", + "NOC_NPS4_X7Y0", + "portSideB3_out", + "HBM_MC_X15Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 121 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA1_in", + "NOC_NPS4_X2Y0", + "portSideB3_out", + "HBM_MC_X5Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X5Y0", + "pc1_port0_out", + "NOC_NPS4_X2Y0", + "portSideB3_in", + "NOC_NPS4_X2Y0", + "portSideA1_out", + "NOC_NPS6_X2Y1", + "port5_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X5Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X5Y0", + "pc1_port0_out", + "NOC_NPS4_X2Y0", + "portSideB3_in", + "NOC_NPS4_X2Y0", + "portSideA0_out", + "NOC_NPS6_X2Y0", + "port5_in", + "NOC_NPS6_X2Y0", + "port3_out", + "NOC_NPS5555_X6Y3", + "port0_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X5Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port0_out", + "NOC_NPS6_X2Y0", + "port3_in", + "NOC_NPS6_X2Y0", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA0_in", + "NOC_NPS4_X2Y0", + "portSideB3_out", + "HBM_MC_X5Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB2_out", + "HBM_MC_X1Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X1Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB2_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port0_out", + "NOC_NPS_VNOC_X1Y34", + "port2_in", + "NOC_NPS_VNOC_X1Y34", + "port0_out", + "NOC_NPS_VNOC_X1Y32", + "port2_in", + "NOC_NPS_VNOC_X1Y32", + "port0_out", + "NOC_NPS_VNOC_X1Y30", + "port2_in", + "NOC_NPS_VNOC_X1Y30", + "port0_out", + "NOC_NPS_VNOC_X1Y28", + "port2_in", + "NOC_NPS_VNOC_X1Y28", + "port0_out", + "NOC_NPS_VNOC_X1Y26", + "port2_in", + "NOC_NPS_VNOC_X1Y26", + "port0_out", + "NOC_NPS7575_X5Y6", + "port1_in", + "NOC_NPS7575_X5Y6", + "port3_out", + "NOC_NIDB_X1Y7", + "port0_in", + "NOC_NIDB_X1Y7", + "port1_out", + "NOC_NIDB_X1Y5", + "port1_in", + "NOC_NIDB_X1Y5", + "port0_out", + "NOC_NPS7575_X5Y4", + "port3_in", + "NOC_NPS7575_X5Y4", + "port1_out", + "NOC_NPS_VNOC_X1Y24", + "port2_in", + "NOC_NPS_VNOC_X1Y24", + "port0_out", + "NOC_NPS_VNOC_X1Y22", + "port2_in", + "NOC_NPS_VNOC_X1Y22", + "port0_out", + "NOC_NPS_VNOC_X1Y20", + "port2_in", + "NOC_NPS_VNOC_X1Y20", + "port0_out", + "NOC_NPS_VNOC_X1Y18", + "port2_in", + "NOC_NPS_VNOC_X1Y18", + "port0_out", + "NOC_NPS_VNOC_X1Y16", + "port2_in", + "NOC_NPS_VNOC_X1Y16", + "port0_out", + "NOC_NPS_VNOC_X1Y14", + "port2_in", + "NOC_NPS_VNOC_X1Y14", + "port0_out", + "NOC_NPS7575_X5Y2", + "port1_in", + "NOC_NPS7575_X5Y2", + "port3_out", + "NOC_NIDB_X1Y3", + "port0_in", + "NOC_NIDB_X1Y3", + "port1_out", + "NOC_NIDB_X1Y1", + "port1_in", + "NOC_NIDB_X1Y1", + "port0_out", + "NOC_NPS7575_X5Y0", + "port3_in", + "NOC_NPS7575_X5Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y12", + "port2_in", + "NOC_NPS_VNOC_X1Y12", + "port0_out", + "NOC_NPS_VNOC_X1Y10", + "port2_in", + "NOC_NPS_VNOC_X1Y10", + "port0_out", + "NOC_NPS_VNOC_X1Y8", + "port2_in", + "NOC_NPS_VNOC_X1Y8", + "port1_out", + "NOC_NPS_VNOC_X1Y9", + "port1_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X1Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB2_in", + "NOC_NPS4_X0Y0", + "portSideA1_out", + "NOC_NPS6_X0Y1", + "port5_in", + "NOC_NPS6_X0Y1", + "port3_out", + "NOC_NPS5555_X5Y4", + "port1_in", + "NOC_NPS5555_X5Y4", + "port2_out", + "NOC_NPS6_X1Y1", + "port0_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port0_out", + "NOC_NPS5555_X5Y4", + "port2_in", + "NOC_NPS5555_X5Y4", + "port1_out", + "NOC_NPS6_X0Y1", + "port3_in", + "NOC_NPS6_X0Y1", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA1_in", + "NOC_NPS4_X0Y0", + "portSideB2_out", + "HBM_MC_X1Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port0_out", + "NOC_NPS5555_X5Y6", + "port2_in", + "NOC_NPS5555_X5Y6", + "port1_out", + "NOC_NPS6_X0Y2", + "port3_in", + "NOC_NPS6_X0Y2", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA2_in", + "NOC_NPS4_X0Y0", + "portSideB3_out", + "HBM_MC_X1Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X1Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB3_in", + "NOC_NPS4_X0Y0", + "portSideA2_out", + "NOC_NPS6_X0Y2", + "port5_in", + "NOC_NPS6_X0Y2", + "port3_out", + "NOC_NPS5555_X5Y6", + "port1_in", + "NOC_NPS5555_X5Y6", + "port2_out", + "NOC_NPS6_X1Y2", + "port0_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port0_out", + "NOC_NPS_VNOC_X1Y34", + "port2_in", + "NOC_NPS_VNOC_X1Y34", + "port0_out", + "NOC_NPS_VNOC_X1Y32", + "port2_in", + "NOC_NPS_VNOC_X1Y32", + "port0_out", + "NOC_NPS_VNOC_X1Y30", + "port2_in", + "NOC_NPS_VNOC_X1Y30", + "port0_out", + "NOC_NPS_VNOC_X1Y28", + "port2_in", + "NOC_NPS_VNOC_X1Y28", + "port0_out", + "NOC_NPS_VNOC_X1Y26", + "port2_in", + "NOC_NPS_VNOC_X1Y26", + "port0_out", + "NOC_NPS7575_X5Y6", + "port1_in", + "NOC_NPS7575_X5Y6", + "port3_out", + "NOC_NIDB_X1Y7", + "port0_in", + "NOC_NIDB_X1Y7", + "port1_out", + "NOC_NIDB_X1Y5", + "port1_in", + "NOC_NIDB_X1Y5", + "port0_out", + "NOC_NPS7575_X5Y4", + "port3_in", + "NOC_NPS7575_X5Y4", + "port1_out", + "NOC_NPS_VNOC_X1Y24", + "port2_in", + "NOC_NPS_VNOC_X1Y24", + "port0_out", + "NOC_NPS_VNOC_X1Y22", + "port2_in", + "NOC_NPS_VNOC_X1Y22", + "port0_out", + "NOC_NPS_VNOC_X1Y20", + "port2_in", + "NOC_NPS_VNOC_X1Y20", + "port0_out", + "NOC_NPS_VNOC_X1Y18", + "port2_in", + "NOC_NPS_VNOC_X1Y18", + "port0_out", + "NOC_NPS_VNOC_X1Y16", + "port2_in", + "NOC_NPS_VNOC_X1Y16", + "port0_out", + "NOC_NPS_VNOC_X1Y14", + "port2_in", + "NOC_NPS_VNOC_X1Y14", + "port0_out", + "NOC_NPS7575_X5Y2", + "port1_in", + "NOC_NPS7575_X5Y2", + "port3_out", + "NOC_NIDB_X1Y3", + "port0_in", + "NOC_NIDB_X1Y3", + "port1_out", + "NOC_NIDB_X1Y1", + "port1_in", + "NOC_NIDB_X1Y1", + "port0_out", + "NOC_NPS7575_X5Y0", + "port3_in", + "NOC_NPS7575_X5Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y12", + "port2_in", + "NOC_NPS_VNOC_X1Y12", + "port0_out", + "NOC_NPS_VNOC_X1Y10", + "port2_in", + "NOC_NPS_VNOC_X1Y10", + "port0_out", + "NOC_NPS_VNOC_X1Y8", + "port2_in", + "NOC_NPS_VNOC_X1Y8", + "port1_out", + "NOC_NPS_VNOC_X1Y9", + "port1_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X1Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X1Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB3_in", + "NOC_NPS4_X0Y0", + "portSideA1_out", + "NOC_NPS6_X0Y1", + "port5_in", + "NOC_NPS6_X0Y1", + "port3_out", + "NOC_NPS5555_X5Y4", + "port1_in", + "NOC_NPS5555_X5Y4", + "port2_out", + "NOC_NPS6_X1Y1", + "port0_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X1Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port0_out", + "NOC_NPS5555_X5Y4", + "port2_in", + "NOC_NPS5555_X5Y4", + "port1_out", + "NOC_NPS6_X0Y1", + "port3_in", + "NOC_NPS6_X0Y1", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA1_in", + "NOC_NPS4_X0Y0", + "portSideB3_out", + "HBM_MC_X1Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA1_in", + "NOC_NPS4_X3Y0", + "portSideB0_out", + "HBM_MC_X6Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X6Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB0_in", + "NOC_NPS4_X3Y0", + "portSideA1_out", + "NOC_NPS6_X3Y1", + "port5_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X6Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB0_in", + "NOC_NPS4_X3Y0", + "portSideA1_out", + "NOC_NPS6_X3Y1", + "port5_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA1_in", + "NOC_NPS4_X3Y0", + "portSideB0_out", + "HBM_MC_X6Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA1_in", + "NOC_NPS4_X6Y0", + "portSideB0_out", + "HBM_MC_X12Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X12Y0", + "pc0_port0_out", + "NOC_NPS4_X6Y0", + "portSideB0_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X12Y0", + "pc0_port0_out", + "NOC_NPS4_X6Y0", + "portSideB0_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA1_in", + "NOC_NPS4_X6Y0", + "portSideB0_out", + "HBM_MC_X12Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port0_out", + "NOC_NPS5555_X5Y4", + "port2_in", + "NOC_NPS5555_X5Y4", + "port1_out", + "NOC_NPS6_X0Y1", + "port3_in", + "NOC_NPS6_X0Y1", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA1_in", + "NOC_NPS4_X0Y0", + "portSideB1_out", + "HBM_MC_X0Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X0Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB1_in", + "NOC_NPS4_X0Y0", + "portSideA1_out", + "NOC_NPS6_X0Y1", + "port5_in", + "NOC_NPS6_X0Y1", + "port3_out", + "NOC_NPS5555_X5Y4", + "port1_in", + "NOC_NPS5555_X5Y4", + "port2_out", + "NOC_NPS6_X1Y1", + "port0_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X0Y0", + "pc1_port0_out", + "NOC_NPS4_X0Y0", + "portSideB1_in", + "NOC_NPS4_X0Y0", + "portSideA1_out", + "NOC_NPS6_X0Y1", + "port5_in", + "NOC_NPS6_X0Y1", + "port3_out", + "NOC_NPS5555_X5Y4", + "port1_in", + "NOC_NPS5555_X5Y4", + "port2_out", + "NOC_NPS6_X1Y1", + "port0_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port0_out", + "NOC_NPS5555_X5Y4", + "port2_in", + "NOC_NPS5555_X5Y4", + "port1_out", + "NOC_NPS6_X0Y1", + "port3_in", + "NOC_NPS6_X0Y1", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA1_in", + "NOC_NPS4_X0Y0", + "portSideB1_out", + "HBM_MC_X0Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA1_in", + "NOC_NPS4_X3Y0", + "portSideB1_out", + "HBM_MC_X6Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X6Y0", + "pc1_port0_out", + "NOC_NPS4_X3Y0", + "portSideB1_in", + "NOC_NPS4_X3Y0", + "portSideA1_out", + "NOC_NPS6_X3Y1", + "port5_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X6Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X6Y0", + "pc1_port0_out", + "NOC_NPS4_X3Y0", + "portSideB1_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X6Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB1_out", + "HBM_MC_X6Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA1_in", + "NOC_NPS4_X7Y0", + "portSideB1_out", + "HBM_MC_X14Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 119 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X14Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB1_in", + "NOC_NPS4_X7Y0", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port5_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 119 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X14Y0", + "pc1_port0_out", + "NOC_NPS4_X7Y0", + "portSideB1_in", + "NOC_NPS4_X7Y0", + "portSideA2_out", + "NOC_NPS6_X7Y2", + "port5_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port1_out", + "NOC_NPS6_X4Y2", + "port3_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 121 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port3_out", + "NOC_NPS5555_X7Y6", + "port1_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA2_in", + "NOC_NPS4_X7Y0", + "portSideB1_out", + "HBM_MC_X14Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 121 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port0_out", + "NOC_NPS5555_X7Y3", + "port2_in", + "NOC_NPS5555_X7Y3", + "port1_out", + "NOC_NPS6_X5Y0", + "port0_in", + "NOC_NPS6_X5Y0", + "port3_out", + "NOC_NPS6_X6Y0", + "port0_in", + "NOC_NPS6_X6Y0", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA0_in", + "NOC_NPS4_X6Y0", + "portSideB1_out", + "HBM_MC_X12Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 117 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X12Y0", + "pc1_port0_out", + "NOC_NPS4_X6Y0", + "portSideB1_in", + "NOC_NPS4_X6Y0", + "portSideA0_out", + "NOC_NPS6_X6Y0", + "port5_in", + "NOC_NPS6_X6Y0", + "port0_out", + "NOC_NPS6_X5Y0", + "port3_in", + "NOC_NPS6_X5Y0", + "port0_out", + "NOC_NPS5555_X7Y3", + "port1_in", + "NOC_NPS5555_X7Y3", + "port2_out", + "NOC_NPS5555_X7Y4", + "port0_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 117 + }, + { + "PhyInstanceStart": "HBM_MC_X12Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X12Y0", + "pc1_port0_out", + "NOC_NPS4_X6Y0", + "portSideB1_in", + "NOC_NPS4_X6Y0", + "portSideA2_out", + "NOC_NPS6_X6Y2", + "port5_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port1_out", + "NOC_NPS6_X4Y2", + "port3_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 117 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X12Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port3_out", + "NOC_NPS5555_X7Y6", + "port1_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA2_in", + "NOC_NPS4_X6Y0", + "portSideB1_out", + "HBM_MC_X12Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 117 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port0_out", + "NOC_NPS5555_X5Y4", + "port2_in", + "NOC_NPS5555_X5Y4", + "port1_out", + "NOC_NPS6_X0Y1", + "port3_in", + "NOC_NPS6_X0Y1", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA1_in", + "NOC_NPS4_X0Y0", + "portSideB0_out", + "HBM_MC_X0Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X0Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB0_in", + "NOC_NPS4_X0Y0", + "portSideA1_out", + "NOC_NPS6_X0Y1", + "port5_in", + "NOC_NPS6_X0Y1", + "port3_out", + "NOC_NPS5555_X5Y4", + "port1_in", + "NOC_NPS5555_X5Y4", + "port2_out", + "NOC_NPS6_X1Y1", + "port0_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X0Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X0Y0", + "pc0_port0_out", + "NOC_NPS4_X0Y0", + "portSideB0_in", + "NOC_NPS4_X0Y0", + "portSideA1_out", + "NOC_NPS6_X0Y1", + "port5_in", + "NOC_NPS6_X0Y1", + "port3_out", + "NOC_NPS5555_X5Y4", + "port1_in", + "NOC_NPS5555_X5Y4", + "port2_out", + "NOC_NPS6_X1Y1", + "port0_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port0_out", + "NOC_NPS5555_X5Y4", + "port2_in", + "NOC_NPS5555_X5Y4", + "port1_out", + "NOC_NPS6_X0Y1", + "port3_in", + "NOC_NPS6_X0Y1", + "port5_out", + "NOC_NPS4_X0Y0", + "portSideA1_in", + "NOC_NPS4_X0Y0", + "portSideB0_out", + "HBM_MC_X0Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port1_out", + "NOC_NPS6_X3Y0", + "port0_in", + "NOC_NPS6_X3Y0", + "port3_out", + "NOC_NPS6_X4Y0", + "port0_in", + "NOC_NPS6_X4Y0", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA0_in", + "NOC_NPS4_X4Y0", + "portSideB0_out", + "HBM_MC_X8Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X8Y0", + "pc0_port0_out", + "NOC_NPS4_X4Y0", + "portSideB0_in", + "NOC_NPS4_X4Y0", + "portSideA0_out", + "NOC_NPS6_X4Y0", + "port5_in", + "NOC_NPS6_X4Y0", + "port0_out", + "NOC_NPS6_X3Y0", + "port3_in", + "NOC_NPS6_X3Y0", + "port0_out", + "NOC_NPS5555_X6Y3", + "port1_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X8Y0", + "pc0_port0_out", + "NOC_NPS4_X4Y0", + "portSideB0_in", + "NOC_NPS4_X4Y0", + "portSideA0_out", + "NOC_NPS6_X4Y0", + "port5_in", + "NOC_NPS6_X4Y0", + "port0_out", + "NOC_NPS6_X3Y0", + "port3_in", + "NOC_NPS6_X3Y0", + "port0_out", + "NOC_NPS5555_X6Y3", + "port1_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port1_out", + "NOC_NPS6_X3Y0", + "port0_in", + "NOC_NPS6_X3Y0", + "port3_out", + "NOC_NPS6_X4Y0", + "port0_in", + "NOC_NPS6_X4Y0", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA0_in", + "NOC_NPS4_X4Y0", + "portSideB0_out", + "HBM_MC_X8Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA1_in", + "NOC_NPS4_X4Y0", + "portSideB1_out", + "HBM_MC_X8Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X8Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB1_in", + "NOC_NPS4_X4Y0", + "portSideA1_out", + "NOC_NPS6_X4Y1", + "port5_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X8Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X8Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB1_in", + "NOC_NPS4_X4Y0", + "portSideA2_out", + "NOC_NPS6_X4Y2", + "port5_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X8Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA2_in", + "NOC_NPS4_X4Y0", + "portSideB1_out", + "HBM_MC_X8Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port3_out", + "NOC_NPS5555_X8Y4", + "port1_in", + "NOC_NPS5555_X8Y4", + "port2_out", + "NOC_NPS6_X7Y1", + "port0_in", + "NOC_NPS6_X7Y1", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA1_in", + "NOC_NPS4_X7Y0", + "portSideB0_out", + "HBM_MC_X14Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 119 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X14Y0", + "pc0_port0_out", + "NOC_NPS4_X7Y0", + "portSideB0_in", + "NOC_NPS4_X7Y0", + "portSideA1_out", + "NOC_NPS6_X7Y1", + "port5_in", + "NOC_NPS6_X7Y1", + "port0_out", + "NOC_NPS5555_X8Y4", + "port2_in", + "NOC_NPS5555_X8Y4", + "port1_out", + "NOC_NPS6_X6Y1", + "port3_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 119 + }, + { + "PhyInstanceStart": "HBM_MC_X14Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X14Y0", + "pc0_port0_out", + "NOC_NPS4_X7Y0", + "portSideB0_in", + "NOC_NPS4_X7Y0", + "portSideA2_out", + "NOC_NPS6_X7Y2", + "port5_in", + "NOC_NPS6_X7Y2", + "port0_out", + "NOC_NPS5555_X8Y6", + "port2_in", + "NOC_NPS5555_X8Y6", + "port1_out", + "NOC_NPS6_X6Y2", + "port3_in", + "NOC_NPS6_X6Y2", + "port0_out", + "NOC_NPS6_X5Y2", + "port3_in", + "NOC_NPS6_X5Y2", + "port0_out", + "NOC_NPS5555_X7Y6", + "port2_in", + "NOC_NPS5555_X7Y6", + "port1_out", + "NOC_NPS6_X4Y2", + "port3_in", + "NOC_NPS6_X4Y2", + "port0_out", + "NOC_NPS6_X3Y2", + "port3_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 121 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X14Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port3_out", + "NOC_NPS6_X4Y2", + "port0_in", + "NOC_NPS6_X4Y2", + "port3_out", + "NOC_NPS5555_X7Y6", + "port1_in", + "NOC_NPS5555_X7Y6", + "port2_out", + "NOC_NPS6_X5Y2", + "port0_in", + "NOC_NPS6_X5Y2", + "port3_out", + "NOC_NPS6_X6Y2", + "port0_in", + "NOC_NPS6_X6Y2", + "port3_out", + "NOC_NPS5555_X8Y6", + "port1_in", + "NOC_NPS5555_X8Y6", + "port2_out", + "NOC_NPS6_X7Y2", + "port0_in", + "NOC_NPS6_X7Y2", + "port5_out", + "NOC_NPS4_X7Y0", + "portSideA2_in", + "NOC_NPS4_X7Y0", + "portSideB0_out", + "HBM_MC_X14Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 121 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA1_in", + "NOC_NPS4_X1Y0", + "portSideB2_out", + "HBM_MC_X3Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X3Y0", + "pc0_port0_out", + "NOC_NPS4_X1Y0", + "portSideB2_in", + "NOC_NPS4_X1Y0", + "portSideA1_out", + "NOC_NPS6_X1Y1", + "port5_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X3Y0", + "pc0_port0_out", + "NOC_NPS4_X1Y0", + "portSideB2_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB2_out", + "HBM_MC_X3Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA1_in", + "NOC_NPS4_X1Y0", + "portSideB3_out", + "HBM_MC_X3Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X3Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB3_in", + "NOC_NPS4_X1Y0", + "portSideA1_out", + "NOC_NPS6_X1Y1", + "port5_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X3Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X3Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB3_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X3Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB3_out", + "HBM_MC_X3Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port0_out", + "NOC_NPS6_X2Y0", + "port3_in", + "NOC_NPS6_X2Y0", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA0_in", + "NOC_NPS4_X2Y0", + "portSideB1_out", + "HBM_MC_X4Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X4Y0", + "pc1_port0_out", + "NOC_NPS4_X2Y0", + "portSideB1_in", + "NOC_NPS4_X2Y0", + "portSideA0_out", + "NOC_NPS6_X2Y0", + "port5_in", + "NOC_NPS6_X2Y0", + "port3_out", + "NOC_NPS5555_X6Y3", + "port0_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X4Y0", + "pc1_port0_out", + "NOC_NPS4_X2Y0", + "portSideB1_in", + "NOC_NPS4_X2Y0", + "portSideA1_out", + "NOC_NPS6_X2Y1", + "port5_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA1_in", + "NOC_NPS4_X2Y0", + "portSideB1_out", + "HBM_MC_X4Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA1_in", + "NOC_NPS4_X2Y0", + "portSideB0_out", + "HBM_MC_X4Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X4Y0", + "pc0_port0_out", + "NOC_NPS4_X2Y0", + "portSideB0_in", + "NOC_NPS4_X2Y0", + "portSideA1_out", + "NOC_NPS6_X2Y1", + "port5_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X4Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X4Y0", + "pc0_port0_out", + "NOC_NPS4_X2Y0", + "portSideB0_in", + "NOC_NPS4_X2Y0", + "portSideA2_out", + "NOC_NPS6_X2Y2", + "port5_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X4Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port5_out", + "NOC_NPS4_X2Y0", + "portSideA2_in", + "NOC_NPS4_X2Y0", + "portSideB0_out", + "HBM_MC_X4Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA1_in", + "NOC_NPS4_X4Y0", + "portSideB2_out", + "HBM_MC_X9Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X9Y0", + "pc0_port0_out", + "NOC_NPS4_X4Y0", + "portSideB2_in", + "NOC_NPS4_X4Y0", + "portSideA1_out", + "NOC_NPS6_X4Y1", + "port5_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X9Y0", + "pc0_port0_out", + "NOC_NPS4_X4Y0", + "portSideB2_in", + "NOC_NPS4_X4Y0", + "portSideA0_out", + "NOC_NPS6_X4Y0", + "port5_in", + "NOC_NPS6_X4Y0", + "port0_out", + "NOC_NPS6_X3Y0", + "port3_in", + "NOC_NPS6_X3Y0", + "port0_out", + "NOC_NPS5555_X6Y3", + "port1_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port1_out", + "NOC_NPS6_X3Y0", + "port0_in", + "NOC_NPS6_X3Y0", + "port3_out", + "NOC_NPS6_X4Y0", + "port0_in", + "NOC_NPS6_X4Y0", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA0_in", + "NOC_NPS4_X4Y0", + "portSideB2_out", + "HBM_MC_X9Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA1_in", + "NOC_NPS4_X1Y0", + "portSideB0_out", + "HBM_MC_X2Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X2Y0", + "pc0_port0_out", + "NOC_NPS4_X1Y0", + "portSideB0_in", + "NOC_NPS4_X1Y0", + "portSideA1_out", + "NOC_NPS6_X1Y1", + "port5_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X2Y0", + "pc0_port0_out", + "NOC_NPS4_X1Y0", + "portSideB0_in", + "NOC_NPS4_X1Y0", + "portSideA2_out", + "NOC_NPS6_X1Y2", + "port5_in", + "NOC_NPS6_X1Y2", + "port3_out", + "NOC_NPS6_X2Y2", + "port0_in", + "NOC_NPS6_X2Y2", + "port3_out", + "NOC_NPS5555_X6Y6", + "port1_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port1_out", + "NOC_NPS6_X2Y2", + "port3_in", + "NOC_NPS6_X2Y2", + "port0_out", + "NOC_NPS6_X1Y2", + "port3_in", + "NOC_NPS6_X1Y2", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA2_in", + "NOC_NPS4_X1Y0", + "portSideB0_out", + "HBM_MC_X2Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB2_out", + "HBM_MC_X11Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X11Y0", + "pc0_port0_out", + "NOC_NPS4_X5Y0", + "portSideB2_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port5_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X11Y0", + "pc0_port0_out", + "NOC_NPS4_X5Y0", + "portSideB2_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port5_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB2_out", + "HBM_MC_X11Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA1_in", + "NOC_NPS4_X4Y0", + "portSideB3_out", + "HBM_MC_X9Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X9Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB3_in", + "NOC_NPS4_X4Y0", + "portSideA1_out", + "NOC_NPS6_X4Y1", + "port5_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X9Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X9Y0", + "pc1_port0_out", + "NOC_NPS4_X4Y0", + "portSideB3_in", + "NOC_NPS4_X4Y0", + "portSideA0_out", + "NOC_NPS6_X4Y0", + "port5_in", + "NOC_NPS6_X4Y0", + "port0_out", + "NOC_NPS6_X3Y0", + "port3_in", + "NOC_NPS6_X3Y0", + "port0_out", + "NOC_NPS5555_X6Y3", + "port1_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X9Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port1_out", + "NOC_NPS6_X3Y0", + "port0_in", + "NOC_NPS6_X3Y0", + "port3_out", + "NOC_NPS6_X4Y0", + "port0_in", + "NOC_NPS6_X4Y0", + "port5_out", + "NOC_NPS4_X4Y0", + "portSideA0_in", + "NOC_NPS4_X4Y0", + "portSideB3_out", + "HBM_MC_X9Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB3_out", + "HBM_MC_X11Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X11Y0", + "pc1_port0_out", + "NOC_NPS4_X5Y0", + "portSideB3_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port5_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "HBM_MC_X11Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X11Y0", + "pc1_port0_out", + "NOC_NPS4_X5Y0", + "portSideB3_in", + "NOC_NPS4_X5Y0", + "portSideA1_out", + "NOC_NPS6_X5Y1", + "port5_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X11Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port5_out", + "NOC_NPS4_X5Y0", + "portSideA1_in", + "NOC_NPS4_X5Y0", + "portSideB3_out", + "HBM_MC_X11Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 113 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA1_in", + "NOC_NPS4_X3Y0", + "portSideB3_out", + "HBM_MC_X7Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X7Y0", + "pc1_port0_out", + "NOC_NPS4_X3Y0", + "portSideB3_in", + "NOC_NPS4_X3Y0", + "portSideA1_out", + "NOC_NPS6_X3Y1", + "port5_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 107 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X7Y0", + "pc1_port0_out", + "NOC_NPS4_X3Y0", + "portSideB3_in", + "NOC_NPS4_X3Y0", + "portSideA0_out", + "NOC_NPS6_X3Y0", + "port5_in", + "NOC_NPS6_X3Y0", + "port0_out", + "NOC_NPS5555_X6Y3", + "port1_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port1_out", + "NOC_NPS6_X3Y0", + "port0_in", + "NOC_NPS6_X3Y0", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA0_in", + "NOC_NPS4_X3Y0", + "portSideB3_out", + "HBM_MC_X7Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA1_in", + "NOC_NPS4_X6Y0", + "portSideB3_out", + "HBM_MC_X13Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X13Y0", + "pc1_port0_out", + "NOC_NPS4_X6Y0", + "portSideB3_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X13Y0", + "pc1_port0_out", + "NOC_NPS4_X6Y0", + "portSideB3_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA1_in", + "NOC_NPS4_X6Y0", + "portSideB3_out", + "HBM_MC_X13Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB2_out", + "HBM_MC_X7Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X7Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB2_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port0_out", + "NOC_NPS_VNOC_X1Y34", + "port2_in", + "NOC_NPS_VNOC_X1Y34", + "port0_out", + "NOC_NPS_VNOC_X1Y32", + "port2_in", + "NOC_NPS_VNOC_X1Y32", + "port0_out", + "NOC_NPS_VNOC_X1Y30", + "port2_in", + "NOC_NPS_VNOC_X1Y30", + "port0_out", + "NOC_NPS_VNOC_X1Y28", + "port2_in", + "NOC_NPS_VNOC_X1Y28", + "port0_out", + "NOC_NPS_VNOC_X1Y26", + "port2_in", + "NOC_NPS_VNOC_X1Y26", + "port0_out", + "NOC_NPS7575_X5Y6", + "port1_in", + "NOC_NPS7575_X5Y6", + "port3_out", + "NOC_NIDB_X1Y7", + "port0_in", + "NOC_NIDB_X1Y7", + "port1_out", + "NOC_NIDB_X1Y5", + "port1_in", + "NOC_NIDB_X1Y5", + "port0_out", + "NOC_NPS7575_X5Y4", + "port3_in", + "NOC_NPS7575_X5Y4", + "port1_out", + "NOC_NPS_VNOC_X1Y24", + "port2_in", + "NOC_NPS_VNOC_X1Y24", + "port0_out", + "NOC_NPS_VNOC_X1Y22", + "port2_in", + "NOC_NPS_VNOC_X1Y22", + "port0_out", + "NOC_NPS_VNOC_X1Y20", + "port2_in", + "NOC_NPS_VNOC_X1Y20", + "port0_out", + "NOC_NPS_VNOC_X1Y18", + "port2_in", + "NOC_NPS_VNOC_X1Y18", + "port0_out", + "NOC_NPS_VNOC_X1Y16", + "port2_in", + "NOC_NPS_VNOC_X1Y16", + "port0_out", + "NOC_NPS_VNOC_X1Y14", + "port2_in", + "NOC_NPS_VNOC_X1Y14", + "port0_out", + "NOC_NPS7575_X5Y2", + "port1_in", + "NOC_NPS7575_X5Y2", + "port3_out", + "NOC_NIDB_X1Y3", + "port0_in", + "NOC_NIDB_X1Y3", + "port1_out", + "NOC_NIDB_X1Y1", + "port1_in", + "NOC_NIDB_X1Y1", + "port0_out", + "NOC_NPS7575_X5Y0", + "port3_in", + "NOC_NPS7575_X5Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y12", + "port2_in", + "NOC_NPS_VNOC_X1Y12", + "port0_out", + "NOC_NPS_VNOC_X1Y10", + "port2_in", + "NOC_NPS_VNOC_X1Y10", + "port0_out", + "NOC_NPS_VNOC_X1Y8", + "port2_in", + "NOC_NPS_VNOC_X1Y8", + "port1_out", + "NOC_NPS_VNOC_X1Y9", + "port1_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X7Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X7Y0", + "pc0_port0_out", + "NOC_NPS4_X3Y0", + "portSideB2_in", + "NOC_NPS4_X3Y0", + "portSideA2_out", + "NOC_NPS6_X3Y2", + "port5_in", + "NOC_NPS6_X3Y2", + "port0_out", + "NOC_NPS5555_X6Y6", + "port2_in", + "NOC_NPS5555_X6Y6", + "port3_out", + "NOC_NCRB_X1Y0", + "port1_in", + "NOC_NCRB_X1Y0", + "port1_out", + "NOC_NPS_VNOC_X1Y36", + "port2_in", + "NOC_NPS_VNOC_X1Y36", + "port1_out", + "NOC_NPS_VNOC_X1Y37", + "port1_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X7Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port2_out", + "NOC_NPS7575_X5Y0", + "port1_in", + "NOC_NPS7575_X5Y0", + "port3_out", + "NOC_NIDB_X1Y1", + "port0_in", + "NOC_NIDB_X1Y1", + "port1_out", + "NOC_NIDB_X1Y3", + "port1_in", + "NOC_NIDB_X1Y3", + "port0_out", + "NOC_NPS7575_X5Y2", + "port3_in", + "NOC_NPS7575_X5Y2", + "port1_out", + "NOC_NPS_VNOC_X1Y14", + "port0_in", + "NOC_NPS_VNOC_X1Y14", + "port2_out", + "NOC_NPS_VNOC_X1Y16", + "port0_in", + "NOC_NPS_VNOC_X1Y16", + "port2_out", + "NOC_NPS_VNOC_X1Y18", + "port0_in", + "NOC_NPS_VNOC_X1Y18", + "port2_out", + "NOC_NPS_VNOC_X1Y20", + "port0_in", + "NOC_NPS_VNOC_X1Y20", + "port2_out", + "NOC_NPS_VNOC_X1Y22", + "port0_in", + "NOC_NPS_VNOC_X1Y22", + "port2_out", + "NOC_NPS_VNOC_X1Y24", + "port0_in", + "NOC_NPS_VNOC_X1Y24", + "port2_out", + "NOC_NPS7575_X5Y4", + "port1_in", + "NOC_NPS7575_X5Y4", + "port3_out", + "NOC_NIDB_X1Y5", + "port0_in", + "NOC_NIDB_X1Y5", + "port1_out", + "NOC_NIDB_X1Y7", + "port1_in", + "NOC_NIDB_X1Y7", + "port0_out", + "NOC_NPS7575_X5Y6", + "port3_in", + "NOC_NPS7575_X5Y6", + "port1_out", + "NOC_NPS_VNOC_X1Y26", + "port0_in", + "NOC_NPS_VNOC_X1Y26", + "port2_out", + "NOC_NPS_VNOC_X1Y28", + "port0_in", + "NOC_NPS_VNOC_X1Y28", + "port2_out", + "NOC_NPS_VNOC_X1Y30", + "port0_in", + "NOC_NPS_VNOC_X1Y30", + "port2_out", + "NOC_NPS_VNOC_X1Y32", + "port0_in", + "NOC_NPS_VNOC_X1Y32", + "port2_out", + "NOC_NPS_VNOC_X1Y34", + "port0_in", + "NOC_NPS_VNOC_X1Y34", + "port2_out", + "NOC_NPS_VNOC_X1Y36", + "port0_in", + "NOC_NPS_VNOC_X1Y36", + "port2_out", + "NOC_NCRB_X1Y1", + "port1_in", + "NOC_NCRB_X1Y1", + "port1_out", + "NOC_NPS5555_X6Y6", + "port3_in", + "NOC_NPS5555_X6Y6", + "port2_out", + "NOC_NPS6_X3Y2", + "port0_in", + "NOC_NPS6_X3Y2", + "port5_out", + "NOC_NPS4_X3Y0", + "portSideA2_in", + "NOC_NPS4_X3Y0", + "portSideB2_out", + "HBM_MC_X7Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA1_in", + "NOC_NPS4_X6Y0", + "portSideB2_out", + "HBM_MC_X13Y0", + "pc0_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X13Y0", + "pc0_port0_out", + "NOC_NPS4_X6Y0", + "portSideB2_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "HBM_MC_X13Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X13Y0", + "pc0_port0_out", + "NOC_NPS4_X6Y0", + "portSideB2_in", + "NOC_NPS4_X6Y0", + "portSideA1_out", + "NOC_NPS6_X6Y1", + "port5_in", + "NOC_NPS6_X6Y1", + "port0_out", + "NOC_NPS6_X5Y1", + "port3_in", + "NOC_NPS6_X5Y1", + "port0_out", + "NOC_NPS5555_X7Y4", + "port2_in", + "NOC_NPS5555_X7Y4", + "port1_out", + "NOC_NPS6_X4Y1", + "port3_in", + "NOC_NPS6_X4Y1", + "port0_out", + "NOC_NPS6_X3Y1", + "port3_in", + "NOC_NPS6_X3Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port2_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X13Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port2_out", + "NOC_NPS6_X3Y1", + "port0_in", + "NOC_NPS6_X3Y1", + "port3_out", + "NOC_NPS6_X4Y1", + "port0_in", + "NOC_NPS6_X4Y1", + "port3_out", + "NOC_NPS5555_X7Y4", + "port1_in", + "NOC_NPS5555_X7Y4", + "port2_out", + "NOC_NPS6_X5Y1", + "port0_in", + "NOC_NPS6_X5Y1", + "port3_out", + "NOC_NPS6_X6Y1", + "port0_in", + "NOC_NPS6_X6Y1", + "port5_out", + "NOC_NPS4_X6Y0", + "portSideA1_in", + "NOC_NPS4_X6Y0", + "portSideB2_out", + "HBM_MC_X13Y0", + "pc0_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 115 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2/I_hbm_mc", + "ToLocked": false, + "Port": "PORT2", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 132, + "WriteBW": 132, + "ReadAchievedBW": 132, + "WriteAchievedBW": 132, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port1_out", + "NOC_NPS6_X2Y1", + "port3_in", + "NOC_NPS6_X2Y1", + "port0_out", + "NOC_NPS6_X1Y1", + "port3_in", + "NOC_NPS6_X1Y1", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA1_in", + "NOC_NPS4_X1Y0", + "portSideB1_out", + "HBM_MC_X2Y0", + "pc1_port0_in" + ], + "RequiredBW": 264, + "AchievedBW": 264, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "HBM_MC_X2Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB1_in", + "NOC_NPS4_X1Y0", + "portSideA1_out", + "NOC_NPS6_X1Y1", + "port5_in", + "NOC_NPS6_X1Y1", + "port3_out", + "NOC_NPS6_X2Y1", + "port0_in", + "NOC_NPS6_X2Y1", + "port3_out", + "NOC_NPS5555_X6Y4", + "port1_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 109 + }, + { + "PhyInstanceStart": "HBM_MC_X2Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "HBM_MC_X2Y0", + "pc1_port0_out", + "NOC_NPS4_X1Y0", + "portSideB1_in", + "NOC_NPS4_X1Y0", + "portSideA0_out", + "NOC_NPS6_X1Y0", + "port5_in", + "NOC_NPS6_X1Y0", + "port3_out", + "NOC_NPS6_X2Y0", + "port0_in", + "NOC_NPS6_X2Y0", + "port3_out", + "NOC_NPS5555_X6Y3", + "port0_in", + "NOC_NPS5555_X6Y3", + "port2_out", + "NOC_NPS5555_X6Y4", + "port0_in", + "NOC_NPS5555_X6Y4", + "port3_out", + "NOC_NCRB_X1Y0", + "port0_in", + "NOC_NCRB_X1Y0", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port0_in", + "NOC_NPS_VNOC_X1Y37", + "port2_out", + "NOC_NPS_VNOC_X1Y35", + "port0_in", + "NOC_NPS_VNOC_X1Y35", + "port2_out", + "NOC_NPS_VNOC_X1Y33", + "port0_in", + "NOC_NPS_VNOC_X1Y33", + "port2_out", + "NOC_NPS_VNOC_X1Y31", + "port0_in", + "NOC_NPS_VNOC_X1Y31", + "port2_out", + "NOC_NPS_VNOC_X1Y29", + "port0_in", + "NOC_NPS_VNOC_X1Y29", + "port2_out", + "NOC_NPS_VNOC_X1Y27", + "port0_in", + "NOC_NPS_VNOC_X1Y27", + "port2_out", + "NOC_NPS7575_X5Y7", + "port3_in", + "NOC_NPS7575_X5Y7", + "port1_out", + "NOC_NIDB_X1Y6", + "port0_in", + "NOC_NIDB_X1Y6", + "port1_out", + "NOC_NIDB_X1Y4", + "port1_in", + "NOC_NIDB_X1Y4", + "port0_out", + "NOC_NPS7575_X5Y5", + "port1_in", + "NOC_NPS7575_X5Y5", + "port3_out", + "NOC_NPS_VNOC_X1Y25", + "port0_in", + "NOC_NPS_VNOC_X1Y25", + "port2_out", + "NOC_NPS_VNOC_X1Y23", + "port0_in", + "NOC_NPS_VNOC_X1Y23", + "port2_out", + "NOC_NPS_VNOC_X1Y21", + "port0_in", + "NOC_NPS_VNOC_X1Y21", + "port2_out", + "NOC_NPS_VNOC_X1Y19", + "port0_in", + "NOC_NPS_VNOC_X1Y19", + "port2_out", + "NOC_NPS_VNOC_X1Y17", + "port0_in", + "NOC_NPS_VNOC_X1Y17", + "port2_out", + "NOC_NPS_VNOC_X1Y15", + "port0_in", + "NOC_NPS_VNOC_X1Y15", + "port2_out", + "NOC_NPS7575_X5Y3", + "port3_in", + "NOC_NPS7575_X5Y3", + "port1_out", + "NOC_NIDB_X1Y2", + "port0_in", + "NOC_NIDB_X1Y2", + "port1_out", + "NOC_NIDB_X1Y0", + "port1_in", + "NOC_NIDB_X1Y0", + "port0_out", + "NOC_NPS7575_X5Y1", + "port1_in", + "NOC_NPS7575_X5Y1", + "port3_out", + "NOC_NPS_VNOC_X1Y13", + "port0_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "HBM_MC_X2Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port0_out", + "NOC_NPS_VNOC_X1Y11", + "port2_in", + "NOC_NPS_VNOC_X1Y11", + "port0_out", + "NOC_NPS_VNOC_X1Y13", + "port2_in", + "NOC_NPS_VNOC_X1Y13", + "port0_out", + "NOC_NPS7575_X5Y1", + "port3_in", + "NOC_NPS7575_X5Y1", + "port1_out", + "NOC_NIDB_X1Y0", + "port0_in", + "NOC_NIDB_X1Y0", + "port1_out", + "NOC_NIDB_X1Y2", + "port1_in", + "NOC_NIDB_X1Y2", + "port0_out", + "NOC_NPS7575_X5Y3", + "port1_in", + "NOC_NPS7575_X5Y3", + "port3_out", + "NOC_NPS_VNOC_X1Y15", + "port2_in", + "NOC_NPS_VNOC_X1Y15", + "port0_out", + "NOC_NPS_VNOC_X1Y17", + "port2_in", + "NOC_NPS_VNOC_X1Y17", + "port0_out", + "NOC_NPS_VNOC_X1Y19", + "port2_in", + "NOC_NPS_VNOC_X1Y19", + "port0_out", + "NOC_NPS_VNOC_X1Y21", + "port2_in", + "NOC_NPS_VNOC_X1Y21", + "port0_out", + "NOC_NPS_VNOC_X1Y23", + "port2_in", + "NOC_NPS_VNOC_X1Y23", + "port0_out", + "NOC_NPS_VNOC_X1Y25", + "port2_in", + "NOC_NPS_VNOC_X1Y25", + "port0_out", + "NOC_NPS7575_X5Y5", + "port3_in", + "NOC_NPS7575_X5Y5", + "port1_out", + "NOC_NIDB_X1Y4", + "port0_in", + "NOC_NIDB_X1Y4", + "port1_out", + "NOC_NIDB_X1Y6", + "port1_in", + "NOC_NIDB_X1Y6", + "port0_out", + "NOC_NPS7575_X5Y7", + "port1_in", + "NOC_NPS7575_X5Y7", + "port3_out", + "NOC_NPS_VNOC_X1Y27", + "port2_in", + "NOC_NPS_VNOC_X1Y27", + "port0_out", + "NOC_NPS_VNOC_X1Y29", + "port2_in", + "NOC_NPS_VNOC_X1Y29", + "port0_out", + "NOC_NPS_VNOC_X1Y31", + "port2_in", + "NOC_NPS_VNOC_X1Y31", + "port0_out", + "NOC_NPS_VNOC_X1Y33", + "port2_in", + "NOC_NPS_VNOC_X1Y33", + "port0_out", + "NOC_NPS_VNOC_X1Y35", + "port2_in", + "NOC_NPS_VNOC_X1Y35", + "port0_out", + "NOC_NPS_VNOC_X1Y37", + "port2_in", + "NOC_NPS_VNOC_X1Y37", + "port0_out", + "NOC_NCRB_X1Y1", + "port0_in", + "NOC_NCRB_X1Y1", + "port0_out", + "NOC_NPS5555_X6Y4", + "port3_in", + "NOC_NPS5555_X6Y4", + "port0_out", + "NOC_NPS5555_X6Y3", + "port2_in", + "NOC_NPS5555_X6Y3", + "port0_out", + "NOC_NPS6_X2Y0", + "port3_in", + "NOC_NPS6_X2Y0", + "port0_out", + "NOC_NPS6_X1Y0", + "port3_in", + "NOC_NPS6_X1Y0", + "port5_out", + "NOC_NPS4_X1Y0", + "portSideA0_in", + "NOC_NPS4_X1Y0", + "portSideB1_out", + "HBM_MC_X2Y0", + "pc1_port0_in" + ], + "RequiredBW": 132, + "AchievedBW": 132, + "RequiredLatency": 300, + "AchievedLatency": 111 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_cips/inst/M00_AXI_nsu/bd_6ff4_M00_AXI_nsu_0_top_INST/NOC_NSU512_INST", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 5, + "WriteBW": 5, + "ReadAchievedBW": 5, + "WriteAchievedBW": 5, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "NOC_NSU512_X1Y6", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port3_out", + "NOC_NSU512_X1Y6", + "req" + ], + "RequiredBW": 5, + "AchievedBW": 5, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "NOC_NSU512_X1Y6", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "NOC_NSU512_X1Y6", + "resp", + "NOC_NPS_VNOC_X1Y12", + "port3_in", + "NOC_NPS_VNOC_X1Y12", + "port1_out", + "NOC_NPS_VNOC_X1Y13", + "port1_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 1, + "AchievedBW": 1, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "NOC_NSU512_X1Y6", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "NOC_NSU512_X1Y6", + "resp", + "NOC_NPS_VNOC_X1Y12", + "port3_in", + "NOC_NPS_VNOC_X1Y12", + "port1_out", + "NOC_NPS_VNOC_X1Y13", + "port1_in", + "NOC_NPS_VNOC_X1Y13", + "port2_out", + "NOC_NPS_VNOC_X1Y11", + "port0_in", + "NOC_NPS_VNOC_X1Y11", + "port2_out", + "NOC_NPS_VNOC_X1Y9", + "port0_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 5, + "AchievedBW": 5, + "RequiredLatency": 300, + "AchievedLatency": 18 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "NOC_NSU512_X1Y6", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port1_out", + "NOC_NPS_VNOC_X1Y8", + "port1_in", + "NOC_NPS_VNOC_X1Y8", + "port2_out", + "NOC_NPS_VNOC_X1Y10", + "port0_in", + "NOC_NPS_VNOC_X1Y10", + "port2_out", + "NOC_NPS_VNOC_X1Y12", + "port0_in", + "NOC_NPS_VNOC_X1Y12", + "port3_out", + "NOC_NSU512_X1Y6", + "req" + ], + "RequiredBW": 1, + "AchievedBW": 1, + "RequiredLatency": 300, + "AchievedLatency": 18 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_1/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "DDRMC_X1Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port0_out", + "NOC_NPS5555_X10Y1", + "port2_in", + "NOC_NPS5555_X10Y1", + "port1_out", + "NOC_NPS5555_X10Y0", + "port3_in", + "NOC_NPS5555_X10Y0", + "port0_out", + "NOC_NPS5555_X8Y0", + "port2_in", + "NOC_NPS5555_X8Y0", + "port1_out", + "DDRMC_X1Y0", + "Port0_req" + ], + "RequiredBW": 850, + "AchievedBW": 850, + "RequiredLatency": 300, + "AchievedLatency": 28 + }, + { + "PhyInstanceStart": "DDRMC_X1Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "DDRMC_X1Y0", + "Port0_resp", + "NOC_NPS5555_X8Y0", + "port1_in", + "NOC_NPS5555_X8Y0", + "port2_out", + "NOC_NPS5555_X10Y0", + "port0_in", + "NOC_NPS5555_X10Y0", + "port3_out", + "NOC_NPS5555_X10Y1", + "port1_in", + "NOC_NPS5555_X10Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port0_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 28 + }, + { + "PhyInstanceStart": "DDRMC_X1Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "DDRMC_X1Y0", + "Port0_resp", + "NOC_NPS5555_X8Y0", + "port1_in", + "NOC_NPS5555_X8Y0", + "port2_out", + "NOC_NPS5555_X10Y0", + "port0_in", + "NOC_NPS5555_X10Y0", + "port3_out", + "NOC_NPS5555_X10Y1", + "port1_in", + "NOC_NPS5555_X10Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port0_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 800, + "AchievedBW": 800, + "RequiredLatency": 300, + "AchievedLatency": 28 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "DDRMC_X1Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port0_out", + "NOC_NPS5555_X10Y1", + "port2_in", + "NOC_NPS5555_X10Y1", + "port1_out", + "NOC_NPS5555_X10Y0", + "port3_in", + "NOC_NPS5555_X10Y0", + "port0_out", + "NOC_NPS5555_X8Y0", + "port2_in", + "NOC_NPS5555_X8Y0", + "port1_out", + "DDRMC_X1Y0", + "Port0_req" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 28 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S04_AXI_nmu/bd_6ff4_S04_AXI_nmu_0_top_INST/NOC_NMU512_INST", + "FromLocked": false, + "To": "top_i/axi_noc_mc_ddr4_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_ddrmc_main", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 800, + "WriteBW": 800, + "ReadAchievedBW": 800, + "WriteAchievedBW": 800, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port0_out", + "NOC_NPS5555_X10Y1", + "port2_in", + "NOC_NPS5555_X10Y1", + "port1_out", + "NOC_NPS5555_X10Y0", + "port3_in", + "NOC_NPS5555_X10Y0", + "port0_out", + "NOC_NPS5555_X8Y0", + "port2_in", + "NOC_NPS5555_X8Y0", + "port0_out", + "NOC_NPS5555_X6Y0", + "port2_in", + "NOC_NPS5555_X6Y0", + "port0_out", + "NOC_NPS5555_X4Y0", + "port2_in", + "NOC_NPS5555_X4Y0", + "port0_out", + "NOC_NPS5555_X2Y0", + "port2_in", + "NOC_NPS5555_X2Y0", + "port3_out", + "DDRMC_X0Y0", + "Port0_req" + ], + "RequiredBW": 850, + "AchievedBW": 850, + "RequiredLatency": 300, + "AchievedLatency": 34 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "DDRMC_X0Y0", + "Port0_resp", + "NOC_NPS5555_X2Y0", + "port3_in", + "NOC_NPS5555_X2Y0", + "port2_out", + "NOC_NPS5555_X4Y0", + "port0_in", + "NOC_NPS5555_X4Y0", + "port2_out", + "NOC_NPS5555_X6Y0", + "port0_in", + "NOC_NPS5555_X6Y0", + "port2_out", + "NOC_NPS5555_X8Y0", + "port0_in", + "NOC_NPS5555_X8Y0", + "port2_out", + "NOC_NPS5555_X10Y0", + "port0_in", + "NOC_NPS5555_X10Y0", + "port3_out", + "NOC_NPS5555_X10Y1", + "port1_in", + "NOC_NPS5555_X10Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port0_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 34 + }, + { + "PhyInstanceStart": "DDRMC_X0Y0", + "PhyInstanceEnd": "NOC_NMU512_X1Y4", + "VC": 6, + "CommType": "READ", + "Connections": [ + "DDRMC_X0Y0", + "Port0_resp", + "NOC_NPS5555_X2Y0", + "port3_in", + "NOC_NPS5555_X2Y0", + "port2_out", + "NOC_NPS5555_X4Y0", + "port0_in", + "NOC_NPS5555_X4Y0", + "port2_out", + "NOC_NPS5555_X6Y0", + "port0_in", + "NOC_NPS5555_X6Y0", + "port2_out", + "NOC_NPS5555_X8Y0", + "port0_in", + "NOC_NPS5555_X8Y0", + "port2_out", + "NOC_NPS5555_X10Y0", + "port0_in", + "NOC_NPS5555_X10Y0", + "port3_out", + "NOC_NPS5555_X10Y1", + "port1_in", + "NOC_NPS5555_X10Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port0_in", + "NOC_NPS5555_X11Y1", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port2_in", + "NOC_NPS_VNOC_X1Y1", + "port0_out", + "NOC_NPS_VNOC_X1Y3", + "port2_in", + "NOC_NPS_VNOC_X1Y3", + "port0_out", + "NOC_NPS_VNOC_X1Y5", + "port2_in", + "NOC_NPS_VNOC_X1Y5", + "port0_out", + "NOC_NPS_VNOC_X1Y7", + "port2_in", + "NOC_NPS_VNOC_X1Y7", + "port0_out", + "NOC_NPS_VNOC_X1Y9", + "port2_in", + "NOC_NPS_VNOC_X1Y9", + "port3_out", + "NOC_NMU512_X1Y4", + "resp_in" + ], + "RequiredBW": 800, + "AchievedBW": 800, + "RequiredLatency": 300, + "AchievedLatency": 34 + }, + { + "PhyInstanceStart": "NOC_NMU512_X1Y4", + "PhyInstanceEnd": "DDRMC_X0Y0", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU512_X1Y4", + "req_out", + "NOC_NPS_VNOC_X1Y9", + "port3_in", + "NOC_NPS_VNOC_X1Y9", + "port2_out", + "NOC_NPS_VNOC_X1Y7", + "port0_in", + "NOC_NPS_VNOC_X1Y7", + "port2_out", + "NOC_NPS_VNOC_X1Y5", + "port0_in", + "NOC_NPS_VNOC_X1Y5", + "port2_out", + "NOC_NPS_VNOC_X1Y3", + "port0_in", + "NOC_NPS_VNOC_X1Y3", + "port2_out", + "NOC_NPS_VNOC_X1Y1", + "port0_in", + "NOC_NPS_VNOC_X1Y1", + "port2_out", + "NOC_NPS5555_X11Y1", + "port2_in", + "NOC_NPS5555_X11Y1", + "port0_out", + "NOC_NPS5555_X10Y1", + "port2_in", + "NOC_NPS5555_X10Y1", + "port1_out", + "NOC_NPS5555_X10Y0", + "port3_in", + "NOC_NPS5555_X10Y0", + "port0_out", + "NOC_NPS5555_X8Y0", + "port2_in", + "NOC_NPS5555_X8Y0", + "port0_out", + "NOC_NPS5555_X6Y0", + "port2_in", + "NOC_NPS5555_X6Y0", + "port0_out", + "NOC_NPS5555_X4Y0", + "port2_in", + "NOC_NPS5555_X4Y0", + "port0_out", + "NOC_NPS5555_X2Y0", + "port2_in", + "NOC_NPS5555_X2Y0", + "port3_out", + "DDRMC_X0Y0", + "Port0_req" + ], + "RequiredBW": 50, + "AchievedBW": 50, + "RequiredLatency": 300, + "AchievedLatency": 34 + } + ] + }, + { + "Phase": 0, + "From": "top_i/axi_noc_cips/inst/S02_AXI_nmu/bd_6ff4_S02_AXI_nmu_0_top_INST/NOC_NMU128_INST", + "FromLocked": false, + "To": "axi_noc/inst/M00_AXI_nsu/bd_1091_M00_AXI_nsu_0_top_INST/NOC_NSU512_INST", + "ToLocked": false, + "Port": "PORT0", + "ReadTC": "BE", + "WriteTC": "BE", + "ReadBW": 5, + "WriteBW": 5, + "ReadAchievedBW": 5, + "WriteAchievedBW": 5, + "ReadLatency": 300, + "WriteLatency": 300, + "ReadBestPossibleLatency": 300, + "WriteBestPossibleLatency": 300, + "PathLocked": false, + "Nets": [ + { + "PhyInstanceStart": "NOC_NMU128_X0Y2", + "PhyInstanceEnd": "NOC_NSU512_X2Y10", + "VC": 5, + "CommType": "WRITE", + "Connections": [ + "NOC_NMU128_X0Y2", + "req_out", + "NOC_NPS5555_X1Y1", + "port0_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port3_out", + "NOC_NSU512_X2Y10", + "req" + ], + "RequiredBW": 6, + "AchievedBW": 6, + "RequiredLatency": 300, + "AchievedLatency": 80 + }, + { + "PhyInstanceStart": "NOC_NSU512_X2Y10", + "PhyInstanceEnd": "NOC_NMU128_X0Y2", + "VC": 7, + "CommType": "WRITE_RESP", + "Connections": [ + "NOC_NSU512_X2Y10", + "resp", + "NOC_NPS_VNOC_X2Y20", + "port3_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port0_out", + "NOC_NMU128_X0Y2", + "resp_in" + ], + "RequiredBW": 1, + "AchievedBW": 1, + "RequiredLatency": 300, + "AchievedLatency": 80 + }, + { + "PhyInstanceStart": "NOC_NSU512_X2Y10", + "PhyInstanceEnd": "NOC_NMU128_X0Y2", + "VC": 6, + "CommType": "READ", + "Connections": [ + "NOC_NSU512_X2Y10", + "resp", + "NOC_NPS_VNOC_X2Y20", + "port3_in", + "NOC_NPS_VNOC_X2Y20", + "port0_out", + "NOC_NPS_VNOC_X2Y18", + "port2_in", + "NOC_NPS_VNOC_X2Y18", + "port0_out", + "NOC_NPS_VNOC_X2Y16", + "port2_in", + "NOC_NPS_VNOC_X2Y16", + "port0_out", + "NOC_NPS_VNOC_X2Y14", + "port2_in", + "NOC_NPS_VNOC_X2Y14", + "port0_out", + "NOC_NPS7575_X6Y2", + "port1_in", + "NOC_NPS7575_X6Y2", + "port3_out", + "NOC_NIDB_X2Y3", + "port0_in", + "NOC_NIDB_X2Y3", + "port1_out", + "NOC_NIDB_X2Y1", + "port1_in", + "NOC_NIDB_X2Y1", + "port0_out", + "NOC_NPS7575_X6Y0", + "port3_in", + "NOC_NPS7575_X6Y0", + "port1_out", + "NOC_NPS_VNOC_X2Y12", + "port2_in", + "NOC_NPS_VNOC_X2Y12", + "port0_out", + "NOC_NPS_VNOC_X2Y10", + "port2_in", + "NOC_NPS_VNOC_X2Y10", + "port0_out", + "NOC_NPS_VNOC_X2Y8", + "port2_in", + "NOC_NPS_VNOC_X2Y8", + "port0_out", + "NOC_NPS_VNOC_X2Y6", + "port2_in", + "NOC_NPS_VNOC_X2Y6", + "port0_out", + "NOC_NPS_VNOC_X2Y4", + "port2_in", + "NOC_NPS_VNOC_X2Y4", + "port0_out", + "NOC_NPS_VNOC_X2Y2", + "port2_in", + "NOC_NPS_VNOC_X2Y2", + "port0_out", + "NOC_NPS_VNOC_X2Y0", + "port2_in", + "NOC_NPS_VNOC_X2Y0", + "port0_out", + "NOC_NPS5555_X17Y1", + "port2_in", + "NOC_NPS5555_X17Y1", + "port3_out", + "NOC_NPS5555_X17Y2", + "port1_in", + "NOC_NPS5555_X17Y2", + "port0_out", + "NOC_NPS5555_X15Y2", + "port2_in", + "NOC_NPS5555_X15Y2", + "port0_out", + "NOC_NPS5555_X13Y2", + "port2_in", + "NOC_NPS5555_X13Y2", + "port0_out", + "NOC_NPS5555_X11Y2", + "port2_in", + "NOC_NPS5555_X11Y2", + "port0_out", + "NOC_NPS5555_X9Y2", + "port2_in", + "NOC_NPS5555_X9Y2", + "port0_out", + "NOC_NPS5555_X7Y2", + "port2_in", + "NOC_NPS5555_X7Y2", + "port0_out", + "NOC_NPS5555_X5Y1", + "port2_in", + "NOC_NPS5555_X5Y1", + "port0_out", + "NOC_NPS5555_X3Y1", + "port2_in", + "NOC_NPS5555_X3Y1", + "port0_out", + "NOC_NPS5555_X1Y1", + "port2_in", + "NOC_NPS5555_X1Y1", + "port0_out", + "NOC_NMU128_X0Y2", + "resp_in" + ], + "RequiredBW": 5, + "AchievedBW": 5, + "RequiredLatency": 300, + "AchievedLatency": 80 + }, + { + "PhyInstanceStart": "NOC_NMU128_X0Y2", + "PhyInstanceEnd": "NOC_NSU512_X2Y10", + "VC": 4, + "CommType": "READ_REQ", + "Connections": [ + "NOC_NMU128_X0Y2", + "req_out", + "NOC_NPS5555_X1Y1", + "port0_in", + "NOC_NPS5555_X1Y1", + "port2_out", + "NOC_NPS5555_X3Y1", + "port0_in", + "NOC_NPS5555_X3Y1", + "port2_out", + "NOC_NPS5555_X5Y1", + "port0_in", + "NOC_NPS5555_X5Y1", + "port2_out", + "NOC_NPS5555_X7Y2", + "port0_in", + "NOC_NPS5555_X7Y2", + "port2_out", + "NOC_NPS5555_X9Y2", + "port0_in", + "NOC_NPS5555_X9Y2", + "port2_out", + "NOC_NPS5555_X11Y2", + "port0_in", + "NOC_NPS5555_X11Y2", + "port2_out", + "NOC_NPS5555_X13Y2", + "port0_in", + "NOC_NPS5555_X13Y2", + "port2_out", + "NOC_NPS5555_X15Y2", + "port0_in", + "NOC_NPS5555_X15Y2", + "port2_out", + "NOC_NPS5555_X17Y2", + "port0_in", + "NOC_NPS5555_X17Y2", + "port1_out", + "NOC_NPS5555_X17Y1", + "port3_in", + "NOC_NPS5555_X17Y1", + "port2_out", + "NOC_NPS_VNOC_X2Y0", + "port0_in", + "NOC_NPS_VNOC_X2Y0", + "port2_out", + "NOC_NPS_VNOC_X2Y2", + "port0_in", + "NOC_NPS_VNOC_X2Y2", + "port2_out", + "NOC_NPS_VNOC_X2Y4", + "port0_in", + "NOC_NPS_VNOC_X2Y4", + "port2_out", + "NOC_NPS_VNOC_X2Y6", + "port0_in", + "NOC_NPS_VNOC_X2Y6", + "port2_out", + "NOC_NPS_VNOC_X2Y8", + "port0_in", + "NOC_NPS_VNOC_X2Y8", + "port2_out", + "NOC_NPS_VNOC_X2Y10", + "port0_in", + "NOC_NPS_VNOC_X2Y10", + "port2_out", + "NOC_NPS_VNOC_X2Y12", + "port0_in", + "NOC_NPS_VNOC_X2Y12", + "port2_out", + "NOC_NPS7575_X6Y0", + "port1_in", + "NOC_NPS7575_X6Y0", + "port3_out", + "NOC_NIDB_X2Y1", + "port0_in", + "NOC_NIDB_X2Y1", + "port1_out", + "NOC_NIDB_X2Y3", + "port1_in", + "NOC_NIDB_X2Y3", + "port0_out", + "NOC_NPS7575_X6Y2", + "port3_in", + "NOC_NPS7575_X6Y2", + "port1_out", + "NOC_NPS_VNOC_X2Y14", + "port0_in", + "NOC_NPS_VNOC_X2Y14", + "port2_out", + "NOC_NPS_VNOC_X2Y16", + "port0_in", + "NOC_NPS_VNOC_X2Y16", + "port2_out", + "NOC_NPS_VNOC_X2Y18", + "port0_in", + "NOC_NPS_VNOC_X2Y18", + "port2_out", + "NOC_NPS_VNOC_X2Y20", + "port0_in", + "NOC_NPS_VNOC_X2Y20", + "port3_out", + "NOC_NSU512_X2Y10", + "req" + ], + "RequiredBW": 1, + "AchievedBW": 1, + "RequiredLatency": 300, + "AchievedLatency": 80 + } + ] + } + ], + "Components": [ + { + "Name": "NOC_NMU512_X0Y18", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X1Y18", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X2Y18", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X3Y18", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X0Y18", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X1Y18", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X2Y18", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X3Y18", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X0Y17", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X1Y17", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X2Y17", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X3Y17", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X0Y17", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X1Y17", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X2Y17", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X3Y17", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X0Y16", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X1Y16", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X2Y16", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X3Y16", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X0Y16", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X1Y16", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X2Y16", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X3Y16", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X0Y15", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X1Y15", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X2Y15", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X3Y15", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X0Y15", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X1Y15", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X2Y15", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X3Y15", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X0Y14", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X1Y14", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X2Y14", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X3Y14", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X0Y14", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X1Y14", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X2Y14", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X3Y14", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X0Y13", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X1Y13", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X2Y13", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X3Y13", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X0Y13", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X1Y13", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X2Y13", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X3Y13", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X0Y12", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X1Y12", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X2Y12", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X3Y12", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X0Y12", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X1Y12", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X2Y12", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X3Y12", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X0Y11", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X1Y11", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X2Y11", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X3Y11", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X0Y11", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X1Y11", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X2Y11", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X3Y11", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X0Y10", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X1Y10", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X2Y10", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X3Y10", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X0Y10", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X1Y10", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X2Y10", + "TrafficLInst": "axi_noc/inst/M00_AXI_nsu/bd_1091_M00_AXI_nsu_0_top_INST/NOC_NSU512_INST", + "DestId": 64 + }, + { + "Name": "NOC_NSU512_X3Y10", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X0Y9", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X1Y9", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X2Y9", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X3Y9", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X0Y9", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X1Y9", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X2Y9", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X3Y9", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X0Y8", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X1Y8", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X2Y8", + "DestId": 0 + }, + { + "Name": "NOC_NMU512_X3Y8", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X0Y8", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X1Y8", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X2Y8", + "DestId": 0 + }, + { + "Name": "NOC_NSU512_X3Y8", + "DestId": 0 + }, + { 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"top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "DestId": 2112, + "PortIndex": 0 + }, + { + "Name": "HBM_MC_X5Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "DestId": 2176, + "PortIndex": 1 + }, + { + "Name": "HBM_MC_X5Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "DestId": 2240, + "PortIndex": 2 + }, + { + "Name": "HBM_MC_X5Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5/I_hbm_mc", + "DestId": 2304, + "PortIndex": 3 + }, + { + "Name": "HBM_MC_X6Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "DestId": 2368, + "PortIndex": 0 + }, + { + "Name": "HBM_MC_X6Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "DestId": 2432, + "PortIndex": 1 + }, + { + "Name": "HBM_MC_X6Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "DestId": 2496, + "PortIndex": 2 + }, + { + "Name": "HBM_MC_X6Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6/I_hbm_mc", + "DestId": 2433, + "PortIndex": 3 + }, + { + "Name": "HBM_MC_X7Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "DestId": 2624, + "PortIndex": 0 + }, + { + "Name": "HBM_MC_X7Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "DestId": 2688, + "PortIndex": 1 + }, + { + "Name": "HBM_MC_X7Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "DestId": 2752, + "PortIndex": 2 + }, + { + "Name": "HBM_MC_X7Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7/I_hbm_mc", + "DestId": 2816, + "PortIndex": 3 + }, + { + "Name": "HBM_MC_X8Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "DestId": 2880, + "PortIndex": 0 + }, + { + "Name": "HBM_MC_X8Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "DestId": 2944, + "PortIndex": 1 + }, + { + "Name": "HBM_MC_X8Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "DestId": 3008, + "PortIndex": 2 + }, + { + "Name": "HBM_MC_X8Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0/I_hbm_mc", + "DestId": 2945, + "PortIndex": 3 + }, + { + "Name": "HBM_MC_X9Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "DestId": 3136, + "PortIndex": 0 + }, + { + "Name": "HBM_MC_X9Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "DestId": 3200, + "PortIndex": 1 + }, + { + "Name": "HBM_MC_X9Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "DestId": 3264, + "PortIndex": 2 + }, + { + "Name": "HBM_MC_X9Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1/I_hbm_mc", + "DestId": 3328, + "PortIndex": 3 + }, + { + "Name": "HBM_MC_X10Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "DestId": 3392, + "PortIndex": 0 + }, + { + "Name": "HBM_MC_X10Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "DestId": 3456, + "PortIndex": 1 + }, + { + "Name": "HBM_MC_X10Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "DestId": 3520, + "PortIndex": 2 + }, + { + "Name": "HBM_MC_X10Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2/I_hbm_mc", + "DestId": 3457, + "PortIndex": 3 + }, + { + "Name": "HBM_MC_X11Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "DestId": 3648, + "PortIndex": 0 + }, + { + "Name": "HBM_MC_X11Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "DestId": 3712, + "PortIndex": 1 + }, + { + "Name": "HBM_MC_X11Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "DestId": 3776, + "PortIndex": 2 + }, + { + "Name": "HBM_MC_X11Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3/I_hbm_mc", + "DestId": 3840, + "PortIndex": 3 + }, + { + "Name": "HBM_MC_X12Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "DestId": 3904, + "PortIndex": 0 + }, + { + "Name": "HBM_MC_X12Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "DestId": 3968, + "PortIndex": 1 + }, + { + "Name": "HBM_MC_X12Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "DestId": 4032, + "PortIndex": 2 + }, + { + "Name": "HBM_MC_X12Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4/I_hbm_mc", + "DestId": 3969, + "PortIndex": 3 + }, + { + "Name": "HBM_MC_X13Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "DestId": 128, + "PortIndex": 0 + }, + { + "Name": "HBM_MC_X13Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "DestId": 512, + "PortIndex": 1 + }, + { + "Name": "HBM_MC_X13Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "DestId": 640, + "PortIndex": 2 + }, + { + "Name": "HBM_MC_X13Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5/I_hbm_mc", + "DestId": 768, + "PortIndex": 3 + }, + { + "Name": "HBM_MC_X14Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "DestId": 896, + "PortIndex": 0 + }, + { + "Name": "HBM_MC_X14Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "DestId": 1344, + "PortIndex": 1 + }, + { + "Name": "HBM_MC_X14Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "DestId": 1472, + "PortIndex": 2 + }, + { + "Name": "HBM_MC_X14Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6/I_hbm_mc", + "DestId": 1345, + "PortIndex": 3 + }, + { + "Name": "HBM_MC_X15Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "DestId": 1984, + "PortIndex": 0 + }, + { + "Name": "HBM_MC_X15Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "DestId": 2560, + "PortIndex": 1 + }, + { + "Name": "HBM_MC_X15Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "DestId": 3072, + "PortIndex": 2 + }, + { + "Name": "HBM_MC_X15Y0", + "TrafficLInst": "top_i/axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7/I_hbm_mc", + "DestId": 3584, + "PortIndex": 3 + } + ] +} \ No newline at end of file diff --git a/submodules/v80-vitis-flow/scripts/v80++ b/submodules/v80-vitis-flow/scripts/v80++ index 3453b825..23b5a06a 100755 --- a/submodules/v80-vitis-flow/scripts/v80++ +++ b/submodules/v80-vitis-flow/scripts/v80++ @@ -143,7 +143,10 @@ pushd ${BUILD_DIR} ./v80++-linker --cfg "$CONFIG_FILE" --platform "$PLATFORM" $SEGMENTED "${TCL_INJECT_ARGS[@]}" --kernels "${KERNEL_PATHS[@]}" if [ "$PLATFORM" = "hw" ]; then cp run_pre.tcl $AVED_DIR/hw/amd_v80_gen5x8_24.1/src/run_pre.tcl - cp run_post.tcl $AVED_DIR/hw/amd_v80_gen5x8_24.1/src/run_post.tcl + cp -r ../resources/dcmac $AVED_DIR/hw/amd_v80_gen5x8_24.1/src/dcmac + cp dcmac_config.tcl $AVED_DIR/hw/amd_v80_gen5x8_24.1/src/dcmac/tcl/dcmac_config.tcl + cp ../resources/run_post.tcl $AVED_DIR/hw/amd_v80_gen5x8_24.1/src/run_post.tcl + cp ../resources/create_design.tcl $AVED_DIR/hw/amd_v80_gen5x8_24.1/src/create_design.tcl fi if [ "$PLATFORM" = "emu" ]; then cpp_files="tb.cpp " diff --git a/submodules/v80-vitis-flow/src/arg_parser/arg_parser.cpp b/submodules/v80-vitis-flow/src/arg_parser/arg_parser.cpp index 1135bfc8..e53f9a73 100644 --- a/submodules/v80-vitis-flow/src/arg_parser/arg_parser.cpp +++ b/submodules/v80-vitis-flow/src/arg_parser/arg_parser.cpp @@ -83,7 +83,50 @@ void ArgParser::parseConfig() { throw std::runtime_error("Config file not provided"); } std::string line; + bool inNetworkSection = false; while (std::getline(configFileStream, line)) { + if (line.empty() || line[0] == '#') { + continue; // Skip empty lines and comments + } + + if (line.find("[network]") == 0) { + inNetworkSection = true; + continue; + } else if (line[0] == '[') { + inNetworkSection = false; // End of network section + } + + if (inNetworkSection) { + if (line.find("eth_") == 0) { + std::size_t equalPos = line.find('='); + if (equalPos != std::string::npos) { + std::string ethIntf = line.substr(4, equalPos - 4); + int ethIntfNum = -1; + + try { + ethIntfNum = std::stoi(ethIntf); + } catch (const std::exception& e) { + utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, + "Invalid interface number: {}", ethIntf); + throw std::runtime_error("Invalid interface number"); + } + + std::string statusStr = line.substr(equalPos + 1); + bool enabled = (statusStr == "1"); + if (ethIntfNum >= 0 && ethIntfNum < 4) { + networkInterfaces[ethIntfNum] = enabled; + utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, + "Network interface {}: {}", ethIntfNum, + enabled ? "enabled" : "disabled"); + } else { + utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, + "Invalid interface number: {}", ethIntf); + throw std::runtime_error("Invalid interface number"); + } + } + } + } + if (line.find("nk=") == 0) { std::istringstream iss(line.substr(3)); std::string kernelType, count, kernelName; @@ -161,6 +204,9 @@ std::vector ArgParser::parseKernels() { std::for_each(kernelEntities.begin(), kernelEntities.end(), [&](const auto& entity) { Kernel krnl = parser.getKernel(); if (krnl.getTopModelName() == entity.second) { + if (isNetworkKernel(entity.first)) { + krnl.setNetworkKernel(); + } krnl.setName(entity.first); kernels_.emplace_back(krnl); krnl.print(); diff --git a/submodules/v80-vitis-flow/src/bd_builder/bd_builder.cpp b/submodules/v80-vitis-flow/src/bd_builder/bd_builder.cpp index 2a230b91..8c1f3f0c 100644 --- a/submodules/v80-vitis-flow/src/bd_builder/bd_builder.cpp +++ b/submodules/v80-vitis-flow/src/bd_builder/bd_builder.cpp @@ -74,6 +74,15 @@ BdBuilder::BdBuilder(std::vector kernels, std::vector connec // streamConnections.erase(sc--); systemMap.addStreamConnection(qdmaStreamConnection); } + // else if (sc->src.kernelName.find("eth_") != std::string::npos) { + // // network interface rx + // netConnections.push_back(*sc); + // streamConnections.erase(sc--); + // } else if (sc->dst.kernelName.find("eth_") != std::string::npos) { + // // network interface tx + // netConnections.push_back(*sc); + // streamConnections.erase(sc--); + // } } } @@ -94,9 +103,11 @@ void BdBuilder::buildBlockDesign() { if (platform == Platform::HARDWARE) { std::string line; + netConfigFile << configNetInterfaces(); blockDesignFile << addRunPreHeader(); blockDesignFile << setupQdmaStreaming(); - blockDesignFile << addQdmaLogic(); + // Not fully supported yet + // blockDesignFile << addQdmaLogic(); blockDesignFile << setupClkWiz(); blockDesignFile << setupSysRst(); blockDesignFile << configNumberOfAXILiteSlaves(); // done @@ -104,7 +115,12 @@ void BdBuilder::buildBlockDesign() { blockDesignFile << configureUserClock(); blockDesignFile << connectClkWiz(); - blockDesignFile << connectQdmaLogic(); + + if (std::all_of(netInterfaces.begin(), netInterfaces.end(), + [](bool enabled) { return !enabled; })) { + blockDesignFile << addBarCrossbar(); + } + // blockDesignFile << connectQdmaLogic(); // blockDesignFile << connectQdmaToRouter(); // do this for each kernel to be added @@ -161,8 +177,18 @@ void BdBuilder::buildBlockDesign() { } utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Adding xbar for axi4full interfaces: {}", countAxi4FullInterfaces); - blockDesignFile << addXbar(countAxi4FullInterfaces); - blockDesignFile << connectXbarToNoC(); + if (countAxi4FullInterfaces > 0) { + blockDesignFile << addXbar(countAxi4FullInterfaces); + blockDesignFile << connectXbarToNoC(); + } else { + blockDesignFile << addXbar(countAxi4FullInterfaces + 1); + blockDesignFile << connectXbarToNoC(); + // Adding dummy traffic generator to connect to xbar when no cores access memory + // This makes sure that the xbar is not empty + blockDesignFile << connectDummyTrafficGen(); + } + utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, + "Adding xbar for axi4full interfaces: {}", countAxi4FullInterfaces); } for (int i = 0; i < kernels.size(); i++) { Interface axi_intf; // TODO: make this work for any number of interfaces.... @@ -181,7 +207,7 @@ void BdBuilder::buildBlockDesign() { BASE_ADDRESS + i * offset); } } - blockDesignFile << "\n"; + blockDesignFile << "\n\nsave_bd_design\n"; } blockDesignFile << assignClkWizAddr() << std::endl; // blockDesignFile << assignQdmaLogicGpioAddr() << std::endl; @@ -783,7 +809,9 @@ std::string BdBuilder::connectAxis(std::string krnl_name) { uint32_t c2hIdx = 0; for (auto el = streamConnections.begin(); el != streamConnections.end(); el++) { if ((el->src.kernelName == krnl_name || el->dst.kernelName == krnl_name) && - el->src.kernelName != "cips" && el->dst.kernelName != "cips") { + el->src.kernelName != "cips" && el->dst.kernelName != "cips" && + el->src.kernelName.find("eth_") == std::string::npos && + el->dst.kernelName.find("eth_") == std::string::npos) { utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Connecting axi4stream {}.{} to {}.{}", el->src.kernelName, el->src.interfaceName, el->dst.kernelName, el->dst.interfaceName); @@ -794,7 +822,7 @@ std::string BdBuilder::connectAxis(std::string krnl_name) { el->dst.interfaceName + "]\n"; streamConnections.erase(el); return result; - } else if (el->src.kernelName == "cips") { + } else if (el->src.kernelName == "cips" && el->dst.kernelName == krnl_name) { uint32_t qid; std::string srcInterface = el->src.interfaceName; std::regex re("qdma_(\\d)"); @@ -821,7 +849,7 @@ std::string BdBuilder::connectAxis(std::string krnl_name) { } streamConnections.erase(el); return result; - } else if (el->dst.kernelName == "cips") { + } else if (el->dst.kernelName == "cips" && el->src.kernelName == krnl_name) { throw std::runtime_error("QDMA Stream C2H connections not supported yet"); // std::string result; // if(c2hIdx > 15) { @@ -840,7 +868,109 @@ std::string BdBuilder::connectAxis(std::string krnl_name) { // el->src.interfaceName + "]\n"; // } // return result; + + } else if (el->src.kernelName == "eth_0" && el->dst.kernelName == krnl_name) { + // naming fifo after the kernel + std::string fifoName = "fifo_" + el->dst.kernelName + "_" + el->dst.interfaceName; + std::string result; + result += + "create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 " + fifoName + "\n"; + result += " set_property CONFIG.IS_ACLK_ASYNC {1} [get_bd_cells " + fifoName + "]\n"; + result += + "connect_bd_intf_net -boundary_type upper [get_bd_intf_pins qsfp_0_n_1/M_AXIS_0] " + "[get_bd_intf_pins " + + fifoName + "/S_AXIS]\n"; + + result += "connect_bd_intf_net -boundary_type lower [get_bd_intf_pins " + fifoName + + "/M_AXIS] [get_bd_intf_pins base_logic/" + el->dst.kernelName + "/" + + el->dst.interfaceName + "]\n"; + result += " connect_bd_net [get_bd_pins " + fifoName + + "/s_axis_aresetn] [get_bd_pins qsfp_0_n_1/ap_rst_n]\n"; + + result += "connect_bd_net [get_bd_pins " + fifoName + + "/s_axis_aclk] [get_bd_pins qsfp_0_n_1/ap_clk]\n"; + result += "connect_bd_net [get_bd_pins " + fifoName + + "/m_axis_aclk] [get_bd_pins base_logic/clk_wiz/clk_out1]\n"; + // result += "connect_bd_intf_net [get_bd_intf_pins base_logic/" + el->dst.kernelName + + // "/" + el->dst.interfaceName + "] [get_bd_intf_pins " + fifoName + + // "/S_AXIS]\n"; + streamConnections.erase(el); + return result; + } else if (el->dst.kernelName == "eth_0" && el->src.kernelName == krnl_name) { + // naming fifo after the kernel + std::string fifoName = "fifo_" + el->src.kernelName + "_" + el->src.interfaceName; + std::string result; + result += "# Adding network connection for " + el->src.kernelName + "\n"; + result += + "create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 " + fifoName + "\n"; + result += "set_property CONFIG.IS_ACLK_ASYNC {1} [get_bd_cells " + fifoName + "]\n"; + result += "connect_bd_intf_net [get_bd_intf_pins " + fifoName + "/M_AXIS]" + + " -boundary_type upper [get_bd_intf_pins qsfp_0_n_1/S_AXIS_0]\n"; + result += "connect_bd_net [get_bd_pins " + fifoName + + "/s_axis_aresetn] [get_bd_pins qsfp_0_n_1/ap_rst_n]\n"; + result += "connect_bd_net [get_bd_pins " + fifoName + + "/s_axis_aclk] [get_bd_pins base_logic/clk_wiz/clk_out1]\n"; + result += "connect_bd_net [get_bd_pins " + fifoName + + "/m_axis_aclk] [get_bd_pins qsfp_0_n_1/ap_clk]\n"; + result += "connect_bd_intf_net [get_bd_intf_pins base_logic/" + el->src.kernelName + + "/" + el->src.interfaceName + "] [get_bd_intf_pins " + fifoName + + "/S_AXIS]\n"; + streamConnections.erase(el); + return result; + } else if (el->src.kernelName == "eth_2" && el->dst.kernelName == krnl_name) { + // naming fifo after the kernel + std::string fifoName = "fifo_" + el->dst.kernelName + "_" + el->dst.interfaceName; + std::string result; + result += + "create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 " + fifoName + "\n"; + result += "set_property CONFIG.IS_ACLK_ASYNC {1} [get_bd_cells " + fifoName + "]\n"; + result += + "connect_bd_intf_net -boundary_type upper [get_bd_intf_pins qsfp_2_n_3/M_AXIS_0] " + "[get_bd_intf_pins " + + fifoName + "/S_AXIS]\n"; + + result += "connect_bd_intf_net -boundary_type lower [get_bd_intf_pins " + fifoName + + "/M_AXIS] [get_bd_intf_pins base_logic/" + el->dst.kernelName + "/" + + el->dst.interfaceName + "]\n"; + result += "connect_bd_net [get_bd_pins " + fifoName + + "/s_axis_aresetn] [get_bd_pins qsfp_2_n_3/ap_rst_n]\n"; + + result += "connect_bd_net [get_bd_pins " + fifoName + + "/s_axis_aclk] [get_bd_pins qsfp_2_n_3/ap_clk]\n"; + result += "connect_bd_net [get_bd_pins " + fifoName + + "/m_axis_aclk] [get_bd_pins base_logic/clk_wiz/clk_out1]\n"; + // result += "connect_bd_intf_net [get_bd_intf_pins base_logic/" + el->dst.kernelName + + // "/" + el->dst.interfaceName + "] [get_bd_intf_pins " + fifoName + + // "/S_AXIS]\n"; + streamConnections.erase(el); + return result; + } else if (el->dst.kernelName == "eth_2" && el->src.kernelName == krnl_name) { + // naming fifo after the kernel + std::string fifoName = "fifo_" + el->src.kernelName + "_" + el->src.interfaceName; + std::string result; + result += "# Adding network connection for " + el->src.kernelName + "\n"; + result += + "create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 " + fifoName + "\n"; + result += "set_property CONFIG.IS_ACLK_ASYNC {1} [get_bd_cells " + fifoName + "]\n"; + result += "connect_bd_intf_net [get_bd_intf_pins " + fifoName + "/M_AXIS]" + + " -boundary_type upper [get_bd_intf_pins qsfp_2_n_3/S_AXIS_0]\n"; + result += "connect_bd_net [get_bd_pins " + fifoName + + "/s_axis_aresetn] [get_bd_pins qsfp_2_n_3/ap_rst_n]\n"; + result += "connect_bd_net [get_bd_pins " + fifoName + + "/s_axis_aclk] [get_bd_pins base_logic/clk_wiz/clk_out1]\n"; + result += "connect_bd_net [get_bd_pins " + fifoName + + "/m_axis_aclk] [get_bd_pins qsfp_2_n_3/ap_clk]\n"; + result += "connect_bd_intf_net [get_bd_intf_pins base_logic/" + el->src.kernelName + + "/" + el->src.interfaceName + "] [get_bd_intf_pins " + fifoName + + "/S_AXIS]\n"; + streamConnections.erase(el); + return result; } + // else { + // throw std::runtime_error("Invalid stream connection: " + el->src.kernelName + " -> " + // + + // el->dst.kernelName); + // } } return "\n"; // if no stream interfaces exist } @@ -952,10 +1082,26 @@ std::string BdBuilder::assignClkWizAddr() { std::string BdBuilder::setSegmented() { char resolvedPath[PATH_MAX]; - if (realpath(NOC_SOLUTION.c_str(), resolvedPath) == nullptr) { - utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, - "Failed to resolve path to {}", NOC_SOLUTION); - throw std::runtime_error("Failed to resolve path to " + std::string(NOC_SOLUTION)); + /** + * if (std::all_of(netInterfaces.begin(), netInterfaces.end(), + [](bool enabled) { return !enabled; })) { + blockDesignFile << addBarCrossbar(); + } + * + */ + if (std::all_of(netInterfaces.begin(), netInterfaces.end(), + [](bool enabled) { return !enabled; })) { + if (realpath(NOC_SOLUTION.c_str(), resolvedPath) == nullptr) { + utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, + "Failed to resolve path to {}", NOC_SOLUTION); + throw std::runtime_error("Failed to resolve path to " + std::string(NOC_SOLUTION)); + } + } else { + if (realpath(DCMAC_NOC_SOLUTION.c_str(), resolvedPath) == nullptr) { + utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, + "Failed to resolve path to {}", DCMAC_NOC_SOLUTION); + throw std::runtime_error("Failed to resolve path to " + std::string(DCMAC_NOC_SOLUTION)); + } } std::stringstream ss; ss << "set_property NOC_SOLUTION_FILE " << std::string(resolvedPath) << " [get_runs impl_1]\n"; diff --git a/submodules/v80-vitis-flow/src/main.cpp b/submodules/v80-vitis-flow/src/main.cpp index 39cf851c..92a20750 100644 --- a/submodules/v80-vitis-flow/src/main.cpp +++ b/submodules/v80-vitis-flow/src/main.cpp @@ -31,7 +31,7 @@ int main(int argc, char** argv) { auto plat = parser.getPlatform(); BdBuilder builder(parser.getKernels(), parser.getConnections(), parser.getFreqHz(), - parser.isSegmented(), plat, parser.getTclInjections()); + parser.isSegmented(), plat, parser.getNetworkInterfaces(), parser.getTclInjections()); builder.buildBlockDesign(); if (plat == Platform::EMULATOR) { diff --git a/submodules/v80-vitis-flow/src/xml_parser/kernel.cpp b/submodules/v80-vitis-flow/src/xml_parser/kernel.cpp index 1e08bbf2..48634a4c 100644 --- a/submodules/v80-vitis-flow/src/xml_parser/kernel.cpp +++ b/submodules/v80-vitis-flow/src/xml_parser/kernel.cpp @@ -93,3 +93,7 @@ void Kernel::print() { el.print(); } } + +void Kernel::setNetworkKernel() { this->networkKernel = true; } + +bool Kernel::isNetworkKernel() { return this->networkKernel; } \ No newline at end of file diff --git a/vrt/vrtd/CMakeLists.txt b/vrt/vrtd/CMakeLists.txt new file mode 100644 index 00000000..8e577aca --- /dev/null +++ b/vrt/vrtd/CMakeLists.txt @@ -0,0 +1,104 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +cmake_minimum_required(VERSION 3.16) + +project(vrtd + VERSION 0.1.0 + LANGUAGES C CXX +) + +# Optionally build examples +option(VRTD_BUILD_EXAMPLES "Build example executables" OFF) +option(BUILD_SHARED_LIBS "Build shared libraries" ON) + + +include(GNUInstallDirs) +include(CMakePackageConfigHelpers) + +find_package(slash REQUIRED) + +add_subdirectory(src) + +add_subdirectory(libvrtd) +add_subdirectory(libvrtdpp) + +#if(VRTD_BUILD_EXAMPLES) +# add_subdirectory(examples) +#endif() + +# -------- Installation: headers and library -------- +# Public headers are under include/ (layout: include/vrtd/*.h) +install( + DIRECTORY "${PROJECT_SOURCE_DIR}/include/" + DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +install( + DIRECTORY "${PROJECT_SOURCE_DIR}/libvrtd/include/" + DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +install( + TARGETS vrtd libvrtd libvrtdpp + EXPORT vrtdTargets + ARCHIVE DESTINATION "${CMAKE_INSTALL_LIBDIR}" + LIBRARY DESTINATION "${CMAKE_INSTALL_LIBDIR}" + RUNTIME DESTINATION "${CMAKE_INSTALL_BINDIR}" + INCLUDES DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +# -------- CMake package configuration -------- +# Generate the version file +write_basic_package_version_file( + "${CMAKE_CURRENT_BINARY_DIR}/vrtdConfigVersion.cmake" + VERSION ${PROJECT_VERSION} + COMPATIBILITY SameMinorVersion +) + +# Configure the main package config from template +configure_package_config_file( + "${PROJECT_SOURCE_DIR}/cmake/vrtdConfig.cmake.in" + "${CMAKE_CURRENT_BINARY_DIR}/vrtdConfig.cmake" + INSTALL_DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/vrtd" +) + +# Export targets for *install* tree +install( + EXPORT vrtdTargets + NAMESPACE vrtd:: + FILE vrtdTargets.cmake + DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/vrtd" +) + +# Install the config + version files +install( + FILES + "${CMAKE_CURRENT_BINARY_DIR}/vrtdConfig.cmake" + "${CMAKE_CURRENT_BINARY_DIR}/vrtdConfigVersion.cmake" + DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/vrtd" +) + +# Export targets for *build* tree so a project can use this directory directly +export( + EXPORT vrtdTargets + NAMESPACE vrtd:: + FILE "${CMAKE_CURRENT_BINARY_DIR}/vrtdTargets.cmake" +) diff --git a/vrt/vrtd/README.md b/vrt/vrtd/README.md new file mode 100644 index 00000000..8309211d --- /dev/null +++ b/vrt/vrtd/README.md @@ -0,0 +1,35 @@ +# vrtd + +## Coding guildelines + +**READ THIS SECTION BEFORE WRITING C CODE FOR THIS DAEMON** + +This daemon is not written using "standard/POSIX C", but instead leans +heavily on C11, libsystemd, glibc features, Linux syscall features and +GNU compiler extensions (also supported by Clang). The goal is not to +write a "portable" application, but a modern systemd daemon, using all +the tools at our disposal. + +The minimum required versions are those shipped by Ubuntu 22.04 LTS: + +* cmake 3.22.1 +* GCC 11.4.0 +* glibc 2.35 +* Linux 5.15.0 +* libsystemd 249.11 + +Lower versions might work, but have not been tested, and may stop +working in any update to vrtd. Developers contributing to vrtd are +encouraged to make use of useful extensions and capabilities as long as +they are supported by the versions mentioned above. + +The language versions is C17. C23 features should not be used unless +they are available as GNU extensions (`-std=gnu17`). + +All `.c` source files should start with `#define _GNU_SOURCE` after the +copyright message and before including any other headers. + +***IMPORTANT!*** For conciseness, consistency and clarity of code, vrtd +uses the conventions described below accross the codebase. Please +follow them for any code contributed. + diff --git a/vrt/vrtd/cmake/vrtdConfig.cmake.in b/vrt/vrtd/cmake/vrtdConfig.cmake.in new file mode 100644 index 00000000..802fc85e --- /dev/null +++ b/vrt/vrtd/cmake/vrtdConfig.cmake.in @@ -0,0 +1,27 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +@PACKAGE_INIT@ + +# If you have dependencies, call find_dependency() here. +# e.g.: find_dependency(Threads) +find_dependency(slash) + +include("${CMAKE_CURRENT_LIST_DIR}/vrtdTargets.cmake") diff --git a/vrt/vrtd/conf/vrtd.conf b/vrt/vrtd/conf/vrtd.conf new file mode 100644 index 00000000..c70e1765 --- /dev/null +++ b/vrt/vrtd/conf/vrtd.conf @@ -0,0 +1,18 @@ +include-glob = vrt.conf.d/*.conf + +[role:fullaccess] +device = any +bar-access = full +pcie-hotplug = yes + +[role:info] +query-devices = yes + +[user:root] +role = fullaccess + +[group:vrtadmin] +role = fullaccess + +[user:*] +role = info diff --git a/vrt/vrtd/include/vrtd/wire.h b/vrt/vrtd/include/vrtd/wire.h new file mode 100644 index 00000000..6291bce1 --- /dev/null +++ b/vrt/vrtd/include/vrtd/wire.h @@ -0,0 +1,230 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file wire.h + * @brief On‑wire protocol for vrtd (V80 Runtime Daemon). + * + * Transport: + * - UNIX domain sockets (AF_UNIX, SOCK_SEQPACKET). Messages are record‑oriented. + * - File descriptors may be sent out‑of‑band using SCM_RIGHTS. + * + * Framing: + * - Each message = { header, body }. + * - Total size (header + body) MUST be <= VRTD_MSG_MAX_SIZE. + * + * Sequencing: + * - Requests carry a client‑chosen @ref vrtd_req_header::seqno that is echoed + * unmodified by the server in @ref vrtd_resp_header::seqno. + * + * Versioning/Extensibility: + * - Unknown opcodes result in VRTD_RET_BAD_REQUEST. + * - New fields may be added at the *end* of messages; older peers must ignore + * trailing bytes up to @ref vrtd_resp_header::size. + * + * Security: + * - Server enforces permissions; failures surface as VRTD_RET_AUTH_ERROR. + */ + +#ifndef VRTD_WIRE_H +#define VRTD_WIRE_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Maximum total size (header + body) for any vrtd message in bytes. */ +#define VRTD_MSG_MAX_SIZE 4096 + +/** + * @brief Operations the client can request from the server. + * @note Unknown/unsupported opcodes yield VRTD_RET_BAD_REQUEST. + */ +enum vrtd_opcode { + /** Query the number of SLASH devices. */ + VRTD_REQ_GET_NUM_DEVICES, + + /** Query basic information about a device. */ + VRTD_REQ_GET_DEVICE_INFO, + + /** Query metadata about a device BAR. */ + VRTD_REQ_GET_BAR_INFO, + + /** Obtain a device BAR file descriptor via SCM_RIGHTS. */ + VRTD_REQ_GET_BAR_FD, + + /** Query QDMA capabilities of a device. */ + VRTD_REQ_QDMA_GET_INFO, + + /** Create a QDMA qpair on a device. */ + VRTD_REQ_QDMA_QPAIR_ADD, + + /** Apply an operation (start/stop/del) to a QDMA qpair. */ + VRTD_REQ_QDMA_QPAIR_OP, + + /** Obtain a read/write file descriptor for a QDMA qpair. */ + VRTD_REQ_QDMA_QPAIR_GET_FD, +}; + +/** + * @brief Return codes for vrtd operations. + * + * @warning VRTD_RET_BAD_LIB_CALL and VRTD_RET_BAD_CONN are **client‑local** + * and are never returned by the server on the wire. + */ + +enum vrtd_ret { + VRTD_RET_OK, + VRTD_RET_BAD_LIB_CALL, ///< Bad library call to libvrtd. This code will not be returned on the wire. + VRTD_RET_BAD_CONN, ///< libvrtd could not connect to vrtd. This code will not be returned on the wire. + VRTD_RET_BAD_REQUEST, ///< Malformed request. + VRTD_RET_INVALID_ARGUMENT, ///< Invalid argument. + VRTD_RET_NOEXIST, ///< Requested resource does not exist. + VRTD_RET_INTERNAL_ERROR, ///< Internal error in the vrtd daemon. Check the vrtd log. + VRTD_RET_AUTH_ERROR, ///< User does not have permission to execute request. +}; + +struct vrtd_req_header { + uint16_t size; ///< Size of the request body (not including the header). + uint16_t opcode; ///< See @ref vrtd_opcode. + uint32_t seqno; ///< Sequence number (this will simply be echoed by the server in the response header). +} __attribute__((packed)); + +struct vrtd_resp_header { + uint16_t size; ///< Size of the response body (not including the header). + uint16_t ret; ///< See @ref vrtd_ret. + uint32_t seqno; ///< Sequence number (this is simply echoed from the request header). +} __attribute__((packed)); + +/** + * @brief Placeholder body to avoid empty-struct ABI pitfalls across C/C++. + * @note Must be set to zero by clients; servers must ignore its value. + */ +struct vrtd_req_get_num_devices { + uint8_t zero; +} __attribute__((packed)); + + +struct vrtd_resp_get_num_devices { + uint32_t num_devices; ///< Number of SLASH devices known to the server. They are identified by numbers in the range [0, n). +} __attribute__((packed)); + + +struct vrtd_req_get_device_info { + uint32_t dev_number; ///< The device for which to get info. An index in the range [0, n). +} __attribute__((packed)); + +struct vrtd_resp_get_device_info { + char name[128]; ///< The name of the device. +} __attribute__((packed)); + +struct vrtd_req_get_bar_info { + uint32_t dev_number; ///< The device for which to get info. An index in the range [0, n). + uint8_t bar_number; ///< The BAR for which to get info. An index in the range [0, 6). +} __attribute__((packed)); + +struct vrtd_resp_get_bar_info { + struct slash_ioctl_bar_info bar_info; ///< The structure with BAR information. +} __attribute__((packed)); + +struct vrtd_req_get_bar_fd { + uint32_t dev_number; ///< The device for who's BAR to get a file descriptor. An index in the range [0, n). + uint8_t bar_number; ///< The BAR for which to get a file descriptor. An index in the range [0, 6). +} __attribute__((packed)); + +/** + * @brief Response to VRTD_REQ_GET_BAR_FD. + * + * The BAR file descriptor is sent out-of-band via SCM_RIGHTS in the same + * message and is present only when @ref vrtd_resp_header::ret == VRTD_RET_OK. + */ +struct vrtd_resp_get_bar_fd { + uint64_t len; ///< Size of the BAR address space; suitable for mmap. +} __attribute__((packed)); + +/** + * @brief Request QDMA capability information for a device. + * + * Complementary to @ref slash_qdma_info; this wraps the libslash QDMA + * info query and exposes it over the vrtd protocol. + */ +struct vrtd_req_qdma_get_info { + uint32_t dev_number; ///< The device for which to get QDMA info. An index in the range [0, n). +} __attribute__((packed)); + +struct vrtd_resp_qdma_get_info { + struct slash_qdma_info info; ///< QDMA capabilities for the device. +} __attribute__((packed)); + +/** + * @brief Request creation of a QDMA qpair. + * + * The @ref slash_qdma_qpair_add payload is passed through to the kernel + * and the resulting qid is returned in the response. + */ +struct vrtd_req_qdma_qpair_add { + uint32_t dev_number; ///< Device index (0-based). + struct slash_qdma_qpair_add add; ///< Qpair creation parameters. +} __attribute__((packed)); + +struct vrtd_resp_qdma_qpair_add { + struct slash_qdma_qpair_add add; ///< Echoed qpair parameters with qid filled in. +} __attribute__((packed)); + +/** + * @brief Request an operation on an existing QDMA qpair. + * + * @ref op uses the same numeric values as @ref SLASH_QDMA_QUEUE_OP_START and friends. + */ +struct vrtd_req_qdma_qpair_op { + uint32_t dev_number; ///< Device index (0-based). + uint32_t qid; ///< Qpair identifier as returned by qpair_add. + uint32_t op; ///< One of SLASH_QDMA_QUEUE_OP_{START,STOP,DEL}. +} __attribute__((packed)); + +struct vrtd_resp_qdma_qpair_op { + uint8_t zero; ///< Placeholder to avoid empty-struct ABI issues. +} __attribute__((packed)); + +/** + * @brief Request a read/write file descriptor for a QDMA qpair. + * + * The qpair FD is sent out-of-band via SCM_RIGHTS when + * @ref vrtd_resp_header::ret == VRTD_RET_OK. + */ +struct vrtd_req_qdma_qpair_get_fd { + uint32_t dev_number; ///< Device index (0-based). + uint32_t qid; ///< Qpair identifier as returned by qpair_add. + uint32_t flags; ///< Only O_CLOEXEC is currently honored. +} __attribute__((packed)); + +struct vrtd_resp_qdma_qpair_get_fd { + uint8_t zero; ///< Placeholder; all data is carried via SCM_RIGHTS. +} __attribute__((packed)); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // VRTD_WIRE_H diff --git a/vrt/vrtd/libvrtd/CMakeLists.txt b/vrt/vrtd/libvrtd/CMakeLists.txt new file mode 100644 index 00000000..734c1cbb --- /dev/null +++ b/vrt/vrtd/libvrtd/CMakeLists.txt @@ -0,0 +1,21 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +add_subdirectory(src) diff --git a/vrt/vrtd/libvrtd/include/vrtd/vrtd.h b/vrt/vrtd/libvrtd/include/vrtd/vrtd.h new file mode 100644 index 00000000..e7efeba8 --- /dev/null +++ b/vrt/vrtd/libvrtd/include/vrtd/vrtd.h @@ -0,0 +1,299 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file vrtd.h + * @brief C client API for the V80 Runtime Daemon (vrtd). + * + * This library (libvrtd) provides a client interface to the VRT daemon (vrtd), + * which multiplexes access to SLASH-managed FPGA devices + * with permission control and multi‑tenancy. + * + * Stack overview: + * slash (kernel module) <- libslash <- vrtd <- libvrtd <- libvrtdpp <- libvrt + * + * Most functions return a #vrtd_ret code. On success, functions return + * #VRTD_RET_OK and populate their output parameters. + */ + +#ifndef LIBVRTD_VRTD_H +#define LIBVRTD_VRTD_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @def VRTD_STANADRD_PATH + * @brief Default UNIX domain socket path for the vrtd daemon. + */ +#define VRTD_STANDARD_PATH "/run/vrtd.sock" + + +/** + * @brief Connect to the vrtd UNIX domain socket. + * + * Creates a SOCK_SEQPACKET connection to the vrtd daemon at @p path. + * + * @param path Absolute path to the vrtd socket (e.g. ::VRTD_STANADRD_PATH). + * Must not be NULL. + * @return On success, a non‑negative file descriptor to the socket. The caller + * owns this descriptor and must close it with @c close(). + * @return On failure, returns -1 and sets @c errno. + */ +int vrtd_connect(const char *path); + + +/** + * @brief Send a raw vrtd protocol request and receive the response. + * + * This is a low‑level escape hatch for issuing arbitrary protocol opcodes. + * Most users should prefer higher‑level helpers (e.g., vrtd_get_* functions). + * + * @param fd Connected vrtd socket file descriptor. + * @param opcode Protocol opcode to send (see @ref vrtd_req_opcode in wire.h). + * @param body Pointer to request body buffer (may be NULL if @p body_size == 0). + * @param body_size Size of request body in bytes. + * @param resp_buf Buffer to receive the response body (may be NULL if no body expected). + * @param resp_bufsz Size of @p resp_buf in bytes. + * @param out_fd Optional; if non‑NULL and the response carries a file + * descriptor (e.g., GET_BAR_FD), the received FD will be + * stored here. Otherwise ignored. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * + * @warning The request size must not exceed the protocol limit + * (e.g., @c VRTD_MSG_MAX_SIZE - sizeof(struct vrtd_req_header)). + * @note On success, @p resp_buf contains exactly the response body bytes. + * @note Only @p out_fd is optional among output parameters. + */ +enum vrtd_ret vrtd_raw_request( + int fd, + uint16_t opcode, + const void *body, uint16_t body_size, + void *resp_buf, size_t resp_bufsz, + int *out_fd +); + + +/** + * @brief Query the number of available devices. + * + * @param fd Connected vrtd socket file descriptor. + * @param num_devices_out Output pointer to receive the device count. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p num_devices_out must not be NULL. + */ +enum vrtd_ret vrtd_get_num_devices( + int fd, + uint32_t *num_devices_out +); + +/** + * @brief Get information about a device (e.g., its name). + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param name_out Output buffer for the device name. Must be at least 128 bytes. + * The string is NUL‑terminated and may be shorter than 128. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p name_out must not be NULL and must have space for 128 bytes. + */ +enum vrtd_ret vrtd_get_device_info( + int fd, + uint32_t dev, + char name_out[128] +); + +/** + * @brief Retrieve information about a device BAR (Base Address Register). + * + * Complementary to vrtd_get_bar_fd(); this returns metadata only. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param bar BAR index. + * @param bar_info_out Output pointer for BAR info (layout, permissions, etc.). + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p bar_info_out must not be NULL. + */ +enum vrtd_ret vrtd_get_bar_info( + int fd, + uint32_t dev, + uint8_t bar, + struct slash_ioctl_bar_info *bar_info_out +); + +/** + * @brief Obtain a file descriptor for a device BAR, suitable for @c mmap(). + * + * Complementary to vrtd_get_bar_info(); this returns a handle to the BAR memory. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param bar BAR index. + * @param fd_out Output pointer to receive the BAR file descriptor. + * @param len_out Output pointer to receive the BAR length in bytes. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p fd_out and @p len_out must not be NULL. + * @note The caller owns the returned FD and should close it when no longer needed + * (or use vrtd_open_bar_file()/vrtd_close_bar_file()). + */ +enum vrtd_ret vrtd_get_bar_fd( + int fd, + uint32_t dev, + uint8_t bar, + int *fd_out, + uint64_t *len_out +); + +/** + * @brief Open a BAR and map it into the process address space. + * + * Convenience helper that requests a BAR FD and performs @c mmap() into + * @p bar_file_out->map with length @p bar_file_out->len. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param bar BAR index. + * @param bar_file_out Output structure receiving the BAR FD, length and mapping. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p bar_file_out must not be NULL. + * @post On success, @p bar_file_out->fd is valid and @p bar_file_out->map is + * a writable shared mapping of size @p bar_file_out->len. + * @warning The caller must later call vrtd_close_bar_file() to unmap and close. + */ +enum vrtd_ret vrtd_open_bar_file( + int fd, + uint32_t dev, + uint8_t bar, + struct slash_bar_file *bar_file_out +); + +/** + * @brief Unmap and close resources acquired by vrtd_open_bar_file(). + * + * Safe to call with NULL and safe to call multiple times; on first successful + * call it unmaps, closes the FD, and clears @p bar_file->map. + * + * @param bar_file Pointer previously filled by vrtd_open_bar_file(). + */ +void vrtd_close_bar_file( + struct slash_bar_file *bar_file_out +); + +/** + * @brief Query QDMA capabilities for a device. + * + * Thin wrapper around the vrtd QDMA GET_INFO opcode. On success, + * fills @p info_out with the kernel's view of the QDMA device. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param info_out Output pointer for QDMA capability information. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p info_out must not be NULL. + */ +enum vrtd_ret vrtd_qdma_get_info( + int fd, + uint32_t dev, + struct slash_qdma_info *info_out +); + +/** + * @brief Create a QDMA qpair on a device. + * + * On success, @p qpair_inout is updated with the kernel‑assigned qid. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param qpair_inout In/out QDMA qpair parameters (see slash_qdma_qpair_add). + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p qpair_inout must not be NULL. + */ +enum vrtd_ret vrtd_qdma_qpair_add( + int fd, + uint32_t dev, + struct slash_qdma_qpair_add *qpair_inout +); + +/** + * @brief Start, stop, or delete a QDMA qpair. + * + * Convenience wrappers around the QDMA qpair OP opcode. + */ +enum vrtd_ret vrtd_qdma_qpair_start( + int fd, + uint32_t dev, + uint32_t qid +); + +enum vrtd_ret vrtd_qdma_qpair_stop( + int fd, + uint32_t dev, + uint32_t qid +); + +enum vrtd_ret vrtd_qdma_qpair_del( + int fd, + uint32_t dev, + uint32_t qid +); + +/** + * @brief Obtain a read/write file descriptor for a QDMA qpair. + * + * The descriptor can be used with read()/write() for C2H/H2C data transfer. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param qid Qpair identifier as returned by vrtd_qdma_qpair_add(). + * @param flags OR of O_CLOEXEC and 0 (other flags are rejected by the daemon). + * @param fd_out Output pointer to receive the qpair file descriptor. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p fd_out must not be NULL. + */ +enum vrtd_ret vrtd_qdma_qpair_get_fd( + int fd, + uint32_t dev, + uint32_t qid, + uint32_t flags, + int *fd_out +); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // LIBVRTD_VRTD_H diff --git a/vrt/vrtd/libvrtd/src/CMakeLists.txt b/vrt/vrtd/libvrtd/src/CMakeLists.txt new file mode 100644 index 00000000..fc2491ae --- /dev/null +++ b/vrt/vrtd/libvrtd/src/CMakeLists.txt @@ -0,0 +1,42 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +add_library( + libvrtd + + ${CMAKE_CURRENT_SOURCE_DIR}/requests.c +) + +target_include_directories(libvrtd + PUBLIC + $ + $ + $ + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR} +) + +# CMake prepends lib for libraries so libvrtd would be output as liblibvrtd otherwise +set_target_properties(libvrtd PROPERTIES OUTPUT_NAME vrtd) + +target_link_libraries(libvrtd + PUBLIC + slash::slash +) diff --git a/vrt/vrtd/libvrtd/src/requests.c b/vrt/vrtd/libvrtd/src/requests.c new file mode 100644 index 00000000..17fc6491 --- /dev/null +++ b/vrt/vrtd/libvrtd/src/requests.c @@ -0,0 +1,404 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "vrtd/wire.h" +#define _GNU_SOURCE + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +int vrtd_connect(const char *path) +{ + if (path == NULL) { + errno = EINVAL; + return -1; + } + + int fd = socket(AF_UNIX, SOCK_SEQPACKET | SOCK_CLOEXEC, 0); + if (fd == -1) { + return -1; + } + + struct sockaddr_un sun = {0}; + sun.sun_family = AF_UNIX; + if (strlen(path) >= sizeof(sun.sun_path)) { + errno = ENAMETOOLONG; + close(fd); + return -1; + } + strcpy(sun.sun_path, path); + + int ret = connect(fd, (struct sockaddr *) &sun, sizeof(sun)); + if (ret == -1) { + close(fd); + return -1; + } + + return fd; +} + +enum vrtd_ret vrtd_raw_request( + int fd, + uint16_t opcode, + const void *req_body, uint16_t req_size, + void *resp_body_buf, size_t resp_bufsz, + int *out_fd +) +{ + if (req_size > VRTD_MSG_MAX_SIZE - sizeof(struct vrtd_req_header)) { errno = EMSGSIZE; return -1; } + + /* ---- Send ---- */ + struct vrtd_req_header h = { + .size = req_size, + .opcode= opcode, + .seqno = 1, + }; + + struct iovec siov[2]; + siov[0].iov_base = &h; + siov[0].iov_len = sizeof(h); + siov[1].iov_base = (void*) req_body; + siov[1].iov_len = req_size; + + struct msghdr smsg = { + .msg_iov = siov, + .msg_iovlen = req_size ? 2 : 1, + }; + + ssize_t sn = sendmsg(fd, &smsg, MSG_NOSIGNAL); + if (sn == -1) { + return VRTD_RET_BAD_CONN; + } + if ((size_t) sn != sizeof(h) + req_size) { + return VRTD_RET_BAD_CONN; + } + + /* ---- Receive ---- */ + struct vrtd_resp_header rh = {0}; + + struct iovec riov[2]; + riov[0].iov_base = &rh; + riov[0].iov_len = sizeof(rh); + riov[1].iov_base = resp_body_buf; + riov[1].iov_len = resp_bufsz; + + char cbuf[CMSG_SPACE(sizeof(int))]; + struct msghdr rmsg = { + .msg_iov = riov, + .msg_iovlen = resp_bufsz ? 2 : 1, + .msg_control = out_fd ? cbuf : NULL, + .msg_controllen = out_fd ? sizeof(cbuf) : 0, + }; + + if (out_fd) { + *out_fd = -1; + } + + ssize_t rn = recvmsg(fd, &rmsg, MSG_CMSG_CLOEXEC); + if (rn == -1) { + return VRTD_RET_BAD_CONN; + } + + if (rmsg.msg_flags & MSG_TRUNC) { + return VRTD_RET_BAD_LIB_CALL; + } + if (rmsg.msg_flags & MSG_CTRUNC) { + return VRTD_RET_BAD_LIB_CALL; + } + + if ((size_t)rn < sizeof(rh)) { + return VRTD_RET_BAD_CONN; + } + + size_t expect = sizeof(rh) + rh.size; + if ((size_t) rn != expect) { + return VRTD_RET_BAD_CONN; + } + + /* Extract FD if any */ + for (struct cmsghdr *c = CMSG_FIRSTHDR(&rmsg); c != NULL; c = CMSG_NXTHDR(&rmsg, c)) { + if (c->cmsg_level == SOL_SOCKET && c->cmsg_type == SCM_RIGHTS && c->cmsg_len >= CMSG_LEN(sizeof(int))) { + assert(out_fd != NULL); + memcpy(out_fd, CMSG_DATA(c), sizeof(int)); + break; + } + } + + return 0; +} + +enum vrtd_ret vrtd_get_num_devices(int fd, uint32_t *out) +{ + if (out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_resp_get_num_devices resp = {0}; + int ret = vrtd_raw_request(fd, VRTD_REQ_GET_NUM_DEVICES, + NULL, 0, + &resp, sizeof(resp), + NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + *out = resp.num_devices; + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_get_device_info(int fd, uint32_t dev, char name_out[128]) +{ + if (name_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_get_device_info req = { + .dev_number = dev, + }; + struct vrtd_resp_get_device_info resp = {0}; + int ret = vrtd_raw_request(fd, VRTD_REQ_GET_DEVICE_INFO, + &req, sizeof(req), + &resp, sizeof(resp), + NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + strcpy(name_out, resp.name); + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_get_bar_info(int fd, uint32_t dev, uint8_t bar, struct slash_ioctl_bar_info *bar_info_out) +{ + if (bar_info_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_get_bar_info req = { + .dev_number = dev, + .bar_number = bar, + }; + struct vrtd_resp_get_bar_info resp = {0}; + int ret = vrtd_raw_request(fd, VRTD_REQ_GET_BAR_INFO, + &req, sizeof(req), + &resp, sizeof(resp), + NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + memcpy(bar_info_out, &resp.bar_info, sizeof(struct slash_ioctl_bar_info)); + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_get_bar_fd(int fd, uint32_t dev, uint8_t bar, int *fd_out, uint64_t *len_out) +{ + if (fd_out == NULL || len_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_get_bar_fd req = { + .dev_number = dev, + .bar_number = bar, + }; + struct vrtd_resp_get_bar_fd resp = {0}; + int ret = vrtd_raw_request(fd, VRTD_REQ_GET_BAR_FD, + &req, sizeof(req), + &resp, sizeof(resp), + fd_out); + if (ret != VRTD_RET_OK) { + return ret; + } + + *len_out = resp.len; + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_qdma_get_info(int fd, uint32_t dev, struct slash_qdma_info *info_out) +{ + if (info_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_qdma_get_info req = { + .dev_number = dev, + }; + struct vrtd_resp_qdma_get_info resp = {0}; + + int ret = vrtd_raw_request(fd, VRTD_REQ_QDMA_GET_INFO, + &req, sizeof(req), + &resp, sizeof(resp), + NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + memcpy(info_out, &resp.info, sizeof(struct slash_qdma_info)); + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_qdma_qpair_add(int fd, uint32_t dev, struct slash_qdma_qpair_add *qpair_inout) +{ + if (qpair_inout == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_qdma_qpair_add req = { + .dev_number = dev, + .add = *qpair_inout, + }; + struct vrtd_resp_qdma_qpair_add resp = {0}; + + int ret = vrtd_raw_request(fd, VRTD_REQ_QDMA_QPAIR_ADD, + &req, sizeof(req), + &resp, sizeof(resp), + NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + *qpair_inout = resp.add; + + return VRTD_RET_OK; +} + +static enum vrtd_ret vrtd_qdma_qpair_op(int fd, uint32_t dev, uint32_t qid, uint32_t op) +{ + struct vrtd_req_qdma_qpair_op req = { + .dev_number = dev, + .qid = qid, + .op = op, + }; + struct vrtd_resp_qdma_qpair_op resp = {0}; + + int ret = vrtd_raw_request(fd, VRTD_REQ_QDMA_QPAIR_OP, + &req, sizeof(req), + &resp, sizeof(resp), + NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_qdma_qpair_start(int fd, uint32_t dev, uint32_t qid) +{ + return vrtd_qdma_qpair_op(fd, dev, qid, SLASH_QDMA_QUEUE_OP_START); +} + +enum vrtd_ret vrtd_qdma_qpair_stop(int fd, uint32_t dev, uint32_t qid) +{ + return vrtd_qdma_qpair_op(fd, dev, qid, SLASH_QDMA_QUEUE_OP_STOP); +} + +enum vrtd_ret vrtd_qdma_qpair_del(int fd, uint32_t dev, uint32_t qid) +{ + return vrtd_qdma_qpair_op(fd, dev, qid, SLASH_QDMA_QUEUE_OP_DEL); +} + +enum vrtd_ret vrtd_qdma_qpair_get_fd( + int fd, + uint32_t dev, + uint32_t qid, + uint32_t flags, + int *fd_out +) +{ + if (fd_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_qdma_qpair_get_fd req = { + .dev_number = dev, + .qid = qid, + .flags = flags, + }; + struct vrtd_resp_qdma_qpair_get_fd resp = {0}; + + int ret = vrtd_raw_request(fd, VRTD_REQ_QDMA_QPAIR_GET_FD, + &req, sizeof(req), + &resp, sizeof(resp), + fd_out); + if (ret != VRTD_RET_OK) { + return ret; + } + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_open_bar_file( + int fd, + uint32_t dev, + uint8_t bar, + struct slash_bar_file *bar_file_out +) { + if (bar_file_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + int bar_fd = -1; + size_t len = 0; + enum vrtd_ret ret = vrtd_get_bar_fd(fd, dev,bar, &bar_file_out->fd, &bar_file_out->len); + if (ret != VRTD_RET_OK) { + return ret; + } + + bar_file_out->map = mmap(NULL, bar_file_out->len, PROT_READ | PROT_WRITE, MAP_SHARED, bar_file_out->fd, 0); + if (bar_file_out->map == MAP_FAILED) { + bar_file_out->map = NULL; + close(fd); + return VRTD_RET_INTERNAL_ERROR; + } + + return VRTD_RET_OK; +} + +void vrtd_close_bar_file(struct slash_bar_file *bar_file) +{ + if (bar_file == NULL) { + return; + } + + if (bar_file->map != NULL) { + munmap(bar_file->map, bar_file->len); + close(bar_file->fd); + + bar_file->map = NULL; + } +} diff --git a/vrt/vrtd/libvrtdpp/CMakeLists.txt b/vrt/vrtd/libvrtdpp/CMakeLists.txt new file mode 100644 index 00000000..734c1cbb --- /dev/null +++ b/vrt/vrtd/libvrtdpp/CMakeLists.txt @@ -0,0 +1,21 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +add_subdirectory(src) diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/bar.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/bar.hpp new file mode 100644 index 00000000..0a75845b --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/bar.hpp @@ -0,0 +1,117 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_BAR_HPP +#define VRTD_BAR_HPP + +#include +#include +#include +#include + +#include + +namespace vrtd { + +/** + * @brief Value-type metadata handle for a device BAR (Base Address Register). + * + * Provides discovery information and a convenience method to open/map the BAR. + * + * @par Semantics + * - @c isUsable(): this BAR is currently accessible/mappable to the caller. + * - @c isInUse(): this BAR is leased by another tenant (currently always false). + * - @c getStartAddress(), @c getLength(): physical address and size in **bytes**. + * + * @par Lifetime + * A @c Bar becomes invalid if its originating @c Session is closed or moved. + * Any subsequent member call will throw. + * + * @par Thread safety + * Methods are thread-safe and may be called concurrently; they synchronize + * on the originating @c Session. + */ +class Bar { +public: + ~Bar() = default; + + Bar(const Bar&) = default; + Bar& operator=(const Bar&) = default; + Bar(Bar&&) noexcept = default; + Bar& operator=(Bar&&) noexcept = default; + + /** + * @brief Zero-based device index that owns this BAR. + */ + uint32_t getDeviceNum() const noexcept; + + /** + * @brief Zero-based BAR index on the device. + */ + uint8_t getNum() const noexcept; + + /** + * @brief Whether this BAR is currently usable (mappable) by the caller. + */ + bool isUsable() const noexcept; + + /** + * @brief Whether this BAR is currently in use by another tenant. + * + * @note In the current implementation this always returns false. + */ + bool isInUse() const noexcept; + + /** + * @brief Physical start address of the BAR. + */ + uint64_t getStartAddress() const noexcept; + + /** + * @brief Length/size of the BAR (bytes). + */ + uint64_t getLength() const noexcept; + + /** + * @brief Open and @c mmap() this BAR, returning an owning @c BarFile. + * + * @return @c BarFile that RAII-owns the FD and mapping; its destructor + * unmaps and closes automatically. + * @throws vrtd::Error on failure. + */ + BarFile openBarFile() const; +private: + // Only allow the Session class to generate this class + friend class Session; + Bar(uint32_t deviceNum, uint8_t num, bool usable, bool inUse, uint64_t startAddress, uint64_t length, std::function fOpenBarFile) noexcept; + + uint32_t deviceNum; + uint8_t num; + bool usable; + bool inUse; + uint64_t startAddress; + uint64_t length; + + std::function fOpenBarFile; +}; + +} // namespace vrtd + +#endif // VRTD_BAR_HPP \ No newline at end of file diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/bar_file.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/bar_file.hpp new file mode 100644 index 00000000..1e4e25b1 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/bar_file.hpp @@ -0,0 +1,199 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_BAR_FILE_HPP +#define VRTD_BAR_FILE_HPP + +#include + +#include + +#include + +namespace vrtd { + +/** + * @brief Owning RAII handle for a mapped BAR region. + * + * Encapsulates a @c slash_bar_file containing the BAR mapping (@c map) and + * length (@c len). Provides typed access via @c getPtr() which brackets + * memory access with the appropriate @c slash_bar_file_start_* / + * @c slash_bar_file_end_* calls. Direct raw access is available via + * @c getRawPtr(), but requires manual bracketing. + * + * @warning Not thread-safe. At most one memory operation (read or write) + * may be active at a time per @c BarFile instance. Concurrent + * calls to @c getPtr() / @c getRawPtr() on the same object are + * not allowed. + * + * @note Move-only; copying is disabled. The moved-from object is closed. + */ +class BarFile { +public: +/** + * @brief Destructor. + * + * Releases the mapping and FD if still open. + * + * @warning If a memory operation is still in progress (i.e., a live + * @c BarFilePtr returned by @c getPtr() has not been destroyed), + * the destructor may throw (e.g., to signal improper usage). + * Users must ensure all @c BarFilePtr instances are destroyed + * before destroying or closing the @c BarFile. + */ + ~BarFile(); + + BarFile(const BarFile&) = delete; + BarFile& operator=(const BarFile&) = delete; + + /** + * @brief Move constructor; transfers ownership and closes the source. + */ + BarFile(BarFile&&) noexcept; + + /** + * @brief Move assignment; closes current, then takes ownership. + */ + BarFile& operator=(BarFile&&) noexcept; + + /** + * @brief Size of the mapped BAR in bytes. + */ + size_t getLen() const noexcept; + + /** + * @brief Get a raw volatile pointer into the mapping. + * + * @param address Byte offset from the start of the mapping (default 0). + * @return @c volatile void* pointing at @p address inside the mapping. + * + * @warning Using the raw pointer requires the caller to manually bracket + * accesses with @c slash_bar_file_start_read() / @c _end_read() or + * @c slash_bar_file_start_write() / @c _end_write() as appropriate. + * Prefer @c getPtr() for RAII-safe access. + * + * @throws std::runtime_error if the file is closed or @p address is out of range. + */ + volatile void *getRawPtr(size_t address = 0) const noexcept; + + /** + * @brief Close the mapping and underlying FD. + * + * After a successful close, @c isClosed() returns true and further + * operations will throw. + * + * @warning Not idempotent/noexcept by design: if a memory operation is + * still in progress (i.e., a @c BarFilePtr is alive), this + * function may throw to signal misuse. + */ + void close(); + + /** + * @brief Whether the BAR has been closed. + */ + bool isClosed() const noexcept; + +private: + friend class Session; + explicit BarFile(slash_bar_file barFile) noexcept; + + slash_bar_file barFile; + + // Internal single-operation guards (non-thread-safe). + bool reading{}; + bool writing{}; + bool closed{}; + +public: + /** + * @brief Direction of an access session. + */ + enum class Direction { + Read, + Write, + }; + + /** + * @brief Acquire a typed RAII pointer into the BAR mapping. + * + * Starts a read or write session (depending on @p direction) and returns + * a move-only @c BarFilePtr that will automatically end the session on + * destruction. Only one operation (read or write) may be active at a time. + * + * @tparam T Element type. Must be an object type; recommended to be + * trivially copyable/standard-layout. Accesses are through + * @c volatile pointers to model device memory semantics. + * @param direction Whether this is a read or write operation. + * @param address Byte offset into the mapping where @c T is addressed. + * + * @return @c BarFilePtr owning the access session. + * + * @throws std::runtime_error if: + * - the file is closed, + * - @p address is out of range, + * - another read/write operation is already in progress, + * - @p direction is invalid. + * + * @warning The caller is responsible for alignment correctness. + */ + template + BarFilePtr getPtr(Direction direction, size_t address = 0) { + if (closed) { + throw std::runtime_error("Memory operation on closed bar file"); + } + + if (address >= barFile.len) { + throw std::runtime_error("Bad address"); + } + + if (reading || writing) { + throw std::runtime_error("Memory operation already in progress"); + } + + volatile uint8_t *p = static_cast(barFile.map); + volatile T *paddr = static_cast(&p[address]); + + std::function callback{}; + + if (direction == Direction::Read) { + slash_bar_file_start_read(&barFile); + reading = true; + callback = [&]{ + slash_bar_file_end_read(&barFile); + reading = false; + }; + } else if (direction == Direction::Write) { + slash_bar_file_start_write(&barFile); + writing = true; + callback = [&]{ + slash_bar_file_end_write(&barFile); + writing = false; + }; + } else { + throw std::runtime_error("Bad direction"); + } + + return BarFilePtr(paddr, callback); + } +}; + +} // namespace vrtd + +#endif // VRTD_BAR_FILE_HPP diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/bar_file_ptr.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/bar_file_ptr.hpp new file mode 100644 index 00000000..298292ca --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/bar_file_ptr.hpp @@ -0,0 +1,137 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_BAR_FILE_PTR_HPP +#define VRTD_BAR_FILE_PTR_HPP + +#include +#include +#include +#include + +namespace vrtd { + +/** + * @brief Move-only RAII pointer for BAR memory access sessions. + * + * A @c BarFilePtr behaves like a @c volatile T* while it is alive and + * runs a stored callback when destroyed exactly once (used to end the + * read/write session started by @c BarFile::getPtr()). + * + * @tparam T Object type for element access (must satisfy @c std::is_object_v). + * + * @warning Not thread-safe. Intended to be short-lived and used on a + * single thread that owns the corresponding @c BarFile operation. + */ +template +class BarFilePtr { + static_assert(std::is_object_v, "T must be an object type"); +public: + using element_type = T; + using pointer = volatile T*; + using callback_t = std::function; + + /** + * @brief Construct from a raw volatile pointer and optional destructor callback. + * + * @param p Raw volatile pointer within the BAR mapping. + * @param cb Callback to run on destruction (e.g., to end a read/write session). + */ + explicit BarFilePtr(pointer p = nullptr, callback_t cb = {}) noexcept + : p_(p), cb_(std::move(cb)) {} + + // move-only (ensures callback runs at most once) + BarFilePtr(BarFilePtr&& other) noexcept + : p_(other.p_), cb_(std::move(other.cb_)) { + other.p_ = nullptr; + other.cb_ = nullptr; + } + BarFilePtr& operator=(BarFilePtr&& other) noexcept { + if (this != &other) { + run_callback(); + p_ = other.p_; + cb_ = std::move(other.cb_); + other.p_ = nullptr; + other.cb_ = nullptr; + } + return *this; + } + + BarFilePtr(const BarFilePtr&) = delete; + BarFilePtr& operator=(const BarFilePtr&) = delete; + + /** + * @brief Destructor; runs the callback at most once if present. + */ + ~BarFilePtr() { run_callback(); } + + // ---- implicit conversions (only these two) ---- + /** + * @brief Implicit conversion to volatile T*. + */ + operator pointer() const noexcept { return p_; } + /** + * @brief Implicit conversion to volatile void*. + */ + operator volatile void*() const noexcept { return p_; } + + // ---- pointer-like interface ---- + pointer get() const noexcept { return p_; } + volatile T& operator*() const noexcept { return *p_; } + pointer operator->() const noexcept { return p_; } + + // index (useful for arrays / pointer arithmetic) + volatile T& operator[](std::size_t i) const noexcept { return p_[i]; } + + /** + * @brief returns true if non-null. + */ + explicit operator bool() const noexcept { return p_ != nullptr; } + + // comparisons + friend bool operator==(const BarFilePtr& a, const BarFilePtr& b) noexcept { return a.p_ == b.p_; } + friend bool operator!=(const BarFilePtr& a, const BarFilePtr& b) noexcept { return !(a == b); } + friend bool operator==(const BarFilePtr& a, std::nullptr_t) noexcept { return a.p_ == nullptr; } + friend bool operator==(std::nullptr_t, const BarFilePtr& a) noexcept { return a.p_ == nullptr; } + friend bool operator!=(const BarFilePtr& a, std::nullptr_t) noexcept { return a.p_ != nullptr; } + friend bool operator!=(std::nullptr_t, const BarFilePtr& a) noexcept { return a.p_ != nullptr; } + + // optional: compare directly with a raw volatile T* + friend bool operator==(const BarFilePtr& a, pointer p) noexcept { return a.p_ == p; } + friend bool operator==(pointer p, const BarFilePtr& a) noexcept { return a.p_ == p; } + friend bool operator!=(const BarFilePtr& a, pointer p) noexcept { return a.p_ != p; } + friend bool operator!=(pointer p, const BarFilePtr& a) noexcept { return a.p_ != p; } + +private: + void run_callback() noexcept { + if (cb_) { + auto cb = std::move(cb_); + cb_ = nullptr; // ensure single fire + cb(); + } + } + + pointer p_ = nullptr; + callback_t cb_ = nullptr; +}; + +} // namsepace vrtd + +#endif // VRTD_BAR_FILE_PTR_HPP diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/device.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/device.hpp new file mode 100644 index 00000000..5854e4f2 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/device.hpp @@ -0,0 +1,94 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_DEVICE_HPP +#define VRTD_DEVICE_HPP + +#include +#include +#include +#include +#include + +#include + +namespace vrtd { + +/** + * @brief Value-type handle describing a vrtd device. + * + * A @c Device carries its device number and name and routes operations back + * through its originating @c Session. + * + * @par Lifetime + * A @c Device becomes invalid if its originating @c Session is closed or moved. + * Any subsequent member call will throw. + * + * @par Thread safety + * Methods are thread-safe and may be called concurrently; they synchronize + * on the originating @c Session. + */ +class Device { +public: + ~Device() = default; + + Device(const Device&) = default; + Device& operator=(const Device&) = default; + Device(Device&&) noexcept = default; + Device& operator=(Device&&) noexcept = default; + + /** + * @brief Zero-based device index as seen by vrtd. + */ + uint32_t getNum() const noexcept; + + /** + * @brief Human-readable device name. + * + * Stable for the lifetime of the @c Device object. + */ + const std::string& getName() const noexcept; + + /** + * @brief Access a device BAR by index. + * + * @param num BAR index. + * @return Metadata handle for the requested BAR. + * @throws vrtd::Error on error (e.g., invalid index or unusable session). + * + * @par Notes + * The returned @c Bar becomes invalid if the originating @c Session is + * later closed or moved. + */ + Bar getBar(uint8_t num) const; +private: + // Only allow the Session class to generate this class + friend class Session; + Device(uint32_t num, std::string_view name, std::function fGetBar); + + uint32_t num; + std::string name; + + std::function fGetBar; +}; + +} + +#endif // VRTD_DEVICE_HPP diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/error.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/error.hpp new file mode 100644 index 00000000..1c44f94a --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/error.hpp @@ -0,0 +1,75 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_ERROR_H +#define VRTD_ERROR_H + +#include + +#include + +namespace vrtd { + +/** + * @brief Exception type for libvrtd/libvrtd++ operations. + * + * Wraps a #vrtd_ret code and exposes a human-readable, static message via + * @c what(). Use @c getErrorCode() to branch on a specific error. + * + * @note Transport/socket issues in the C++ layer are mapped to + * #VRTD_RET_BAD_CONN. + * @note The message returned by @c what() is a static string mapped from the + * code (e.g., "Authentication error") and does not allocate. + */ +class Error : public std::exception { +private: + vrtd_ret errorCode; + +public: + /** + * @brief Construct an Error with the given code. + * @param errorCode A value from #vrtd_ret. + */ + explicit Error(vrtd_ret errorCode) noexcept; + + ~Error() = default; + + Error(const Error&) = default; + Error& operator=(const Error&) = default; + Error(Error&&) noexcept = default; + Error& operator=(Error&&) noexcept = default; + + /** + * @brief Retrieve the underlying error code. + */ + vrtd_ret getErrorCode() const noexcept; + + /** + * @brief Human-readable description corresponding to @c errorCode. + * + * @return Pointer to a static, null-terminated string. The storage is + * valid for the lifetime of the program. + */ + const char *what() const noexcept override; +}; + +} + +#endif //VRTD_ERROR_H diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/qdma_qpair.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/qdma_qpair.hpp new file mode 100644 index 00000000..530af905 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/qdma_qpair.hpp @@ -0,0 +1,124 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_QDMA_QPAIR_HPP +#define VRTD_QDMA_QPAIR_HPP + +#include +#include +#include + +namespace vrtd { + +/** + * @brief RAII wrapper for a QDMA queue pair (qpair). + * + * A @c QdmaQpair owns a qpair created through a @c Session. It provides + * convenience methods to start/stop the qpair and to obtain a read/write + * file descriptor. On destruction, it requests deletion of the qpair. + * + * @warning A @c QdmaQpair becomes invalid if its originating @c Session + * is closed or moved; methods will throw in that case. The + * destructor never throws and will silently ignore errors when + * attempting to delete the qpair. + */ +class QdmaQpair { +public: + ~QdmaQpair(); + + QdmaQpair(const QdmaQpair&) = delete; + QdmaQpair& operator=(const QdmaQpair&) = delete; + + QdmaQpair(QdmaQpair&& other) noexcept; + QdmaQpair& operator=(QdmaQpair&& other) noexcept; + + /** + * @brief Device index owning this qpair. + */ + uint32_t getDeviceNum() const noexcept { return devNum; } + + /** + * @brief Qpair identifier as assigned by the kernel. + */ + uint32_t getQid() const noexcept { return qid; } + + /** + * @brief Start the qpair. + * + * @throws vrtd::Error on error. + */ + void start(); + + /** + * @brief Stop the qpair. + * + * @throws vrtd::Error on error. + */ + void stop(); + + /** + * @brief Obtain a read/write file descriptor for this qpair. + * + * @param flags OR of O_CLOEXEC and 0 (other flags may be rejected). + * @return New file descriptor owned by the caller. + * @throws vrtd::Error on error. + */ + int fd(uint32_t flags = O_CLOEXEC); + + /** + * @brief Obtain a std::fstream bound to this qpair. + * + * @param flags OR of O_CLOEXEC and 0 (other flags may be rejected). + * @param mode Standard iostream open mode (defaults to in|out|binary). + * @return A @c std::fstream owning a new file descriptor for this qpair. + * + * @throws vrtd::Error or std::runtime_error on error. + * + * @note Implementation is Linux-specific and relies on @c /proc/self/fd. + */ + std::fstream fstream( + uint32_t flags = O_CLOEXEC, + std::ios_base::openmode mode = + std::ios_base::in | std::ios_base::out | std::ios_base::binary + ); + +private: + friend class Session; + + QdmaQpair(uint32_t devNum, + uint32_t qid, + std::function fStart, + std::function fStop, + std::function fDelete, + std::function fOpenFd) noexcept; + + uint32_t devNum{}; + uint32_t qid{}; + bool owned{true}; + + std::function fStart; + std::function fStop; + std::function fDelete; + std::function fOpenFd; +}; + +} // namespace vrtd + +#endif // VRTD_QDMA_QPAIR_HPP diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/session.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/session.hpp new file mode 100644 index 00000000..6ec856c4 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/session.hpp @@ -0,0 +1,199 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_SESSION_HPP +#define VRTD_SESSION_HPP + +#include +#include +#include +#include +#include +#include + +#include +#include + +namespace vrtd { + + +/** + * @brief Owning session/connection to the V Runtime Daemon (vrtd). + * + * A @c Session wraps a connected libvrtd socket and provides typed, exception-based + * access to devices and BARs. All public member functions are thread-safe; calls + * synchronize on an internal @c std::mutex. + * + * @par Exceptions + * Most member functions throw #vrtd::Error on failure. The destructor never throws. + * + * @par Lifetime and moves + * - The session is non-copyable and movable. + * - Moving a session leaves the moved-from object in the closed state + * (i.e., @c isClosed()==true and @c operator bool() == false). + * - **Important:** Any @c Device or @c Bar previously obtained from a session becomes + * invalid once that session is closed or moved; subsequent operations on those + * objects will throw. + */ +class Session { +public: + /** + * @brief Construct and connect to the vrtd socket. + * + * @param socket_path Filesystem path to the vrtd UNIX socket. + * Defaults to the standard path. + * @throws vrtd::Error if the connection cannot be established. + */ + explicit Session(const char *socket_path = VRTD_STANDARD_PATH); + + /** + * @brief Destructor; closes the session if still open. + */ + ~Session() noexcept; + + Session(const Session&) = delete; + Session& operator=(const Session&) = delete; + + /** + * @brief Move-construct a session. + * + * The moved-from session becomes closed. + * + * @param other The session to move from. + */ + Session(Session&& other) noexcept; + + /** + * @brief Move-assign a session. + * + * Closes any existing connection, then takes ownership from @p other. + * The moved-from session becomes closed. + * + * @param other The session to move from. + */ + Session& operator=(Session&& other) noexcept; + + /** + * @brief Number of devices visible via vrtd. + * @return Device count. + * @throws vrtd::Error on error. + * + * @par Thread safety + * Safe for concurrent calls across threads. + */ + uint32_t getNumDevices() const; + + /** + * @brief Retrieve a device handle by index. + * + * @param i Zero-based device index; must be less than @c getNumDevices(). + * @return A lightweight @c Device value referring back to this session. + * @throws vrtd::Error if @p i is out of range or if the session is not usable. + * + * @par Notes + * The returned @c Device becomes invalid if this session is later closed or moved. + */ + Device getDevice(size_t i) const; + + /** + * @brief Query QDMA capabilities for a device. + * + * @param device Device for which to query QDMA info. + * @return A copy of the QDMA capability struct as reported by the daemon. + * @throws vrtd::Error on error. + */ + struct slash_qdma_info getQdmaInfo(const Device& device) const; + + /** + * @brief Create a QDMA qpair on a device. + * + * Returns an owning @c QdmaQpair that will automatically delete + * the qpair on destruction. + * + * @param device Device on which to create the qpair. + * @param cfg Qpair configuration parameters. The returned qpair + * exposes @c getQid(). + * @return An owning @c QdmaQpair. + * @throws vrtd::Error on error. + */ + QdmaQpair createQdmaQpair( + const Device& device, + const struct slash_qdma_qpair_add& cfg + ) const; + + /** + * @brief Start, stop or delete an existing QDMA qpair. + * + * Convenience wrappers around the vrtd QDMA queue-op requests. + * + * @throws vrtd::Error on error. + */ + void startQdmaQpair(const Device& device, uint32_t qid) const; + void stopQdmaQpair (const Device& device, uint32_t qid) const; + void deleteQdmaQpair(const Device& device, uint32_t qid) const; + + /** + * @brief Obtain a read/write file descriptor for a QDMA qpair. + * + * @param device Device owning the qpair. + * @param qid Qpair identifier as returned by @c createQdmaQpair(). + * @param flags OR of O_CLOEXEC and 0 (other flags may be rejected). + * @return A new file descriptor referring to the qpair, owned by the caller. + * @throws vrtd::Error on error. + */ + int openQdmaQpairFd(const Device& device, uint32_t qid, uint32_t flags = 0) const; + + /** + * @brief Explicitly close the session. + * + * Idempotent. After closing, @c isClosed()==true and further operations + * on this session or on previously obtained @c Device/@c Bar objects will throw. + */ + void close() noexcept; + + /** + * @brief Whether the session is closed. + */ + bool isClosed() const noexcept; + + /** + * @brief Truthiness conversion. + * + * @return @c true if the session is open (not closed). + */ + explicit operator bool() const noexcept; +private: + int fd; + mutable std::unique_ptr m; + + /** + * @internal Obtains a BAR for @p device. Called via @c Device::getBar(). + */ + Bar getBar(const Device& device, uint8_t bar_number) const; + + /** + * @internal Opens and mmaps a BAR file. Called via @c Bar::openBarFile(). + */ + BarFile openBarFile(const Bar &bar) const; +}; + +} + +#endif // VRTD_SESSION_HPP diff --git a/vrt/vrtd/libvrtdpp/src/CMakeLists.txt b/vrt/vrtd/libvrtdpp/src/CMakeLists.txt new file mode 100644 index 00000000..ad38cbae --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/CMakeLists.txt @@ -0,0 +1,51 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +add_library( + libvrtdpp + + ${CMAKE_CURRENT_SOURCE_DIR}/bar_file.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/bar.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/qdma_qpair.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/device.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/error.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/session.cpp +) + +target_include_directories(libvrtdpp + PUBLIC + $ + $ + $ + $ + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR} +) + +# CMake prepends lib for libraries so libvrtdpp would be output as liblibvrtdpp otherwise +set_target_properties(libvrtdpp PROPERTIES OUTPUT_NAME vrtdpp) + +set_target_properties(libvrtdpp PROPERTIES + CXX_STANDARD 20 + CXX_STANDARD_REQUIRED YES + CXX_EXTENSIONS YES +) + +target_link_libraries(libvrtdpp PUBLIC libvrtd) diff --git a/vrt/vrtd/libvrtdpp/src/bar.cpp b/vrt/vrtd/libvrtdpp/src/bar.cpp new file mode 100644 index 00000000..29583566 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/bar.cpp @@ -0,0 +1,63 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +namespace vrtd { + +Bar::Bar(uint32_t deviceNum, uint8_t num, bool usable, bool inUse, uint64_t startAddress, uint64_t length, std::function fOpenBarFile) noexcept { + this->deviceNum = deviceNum; + this->num = num; + this->usable = usable; + this->inUse = inUse; + this->startAddress = startAddress; + this->length = length; + this->fOpenBarFile = fOpenBarFile; +} + +uint32_t Bar::getDeviceNum() const noexcept { + return deviceNum; +} + +uint8_t Bar::getNum() const noexcept { + return num; +} + +bool Bar::isUsable() const noexcept { + return usable; +} + +bool Bar::isInUse() const noexcept { + return inUse; +} + +uint64_t Bar::getStartAddress() const noexcept { + return startAddress; +} + +uint64_t Bar::getLength() const noexcept { + return length; +} + +BarFile Bar::openBarFile() const { + return fOpenBarFile(*this); +} + +} diff --git a/vrt/vrtd/libvrtdpp/src/bar_file.cpp b/vrt/vrtd/libvrtdpp/src/bar_file.cpp new file mode 100644 index 00000000..bd95d743 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/bar_file.cpp @@ -0,0 +1,96 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include +#include +#include + +#include + +namespace vrtd { + +BarFile::BarFile(slash_bar_file barFile) noexcept { + this->barFile = barFile; +} + +BarFile::~BarFile() { + close(); +} + +BarFile::BarFile(BarFile&& other) noexcept { + barFile = std::exchange(other.barFile, {}); + reading = std::exchange(other.reading, false); + writing = std::exchange(other.writing, false); + closed = std::exchange(other.closed, true); +} + +BarFile& BarFile::operator=(BarFile&& other) noexcept { + close(); + + barFile = std::exchange(other.barFile, {}); + reading = std::exchange(other.reading, false); + writing = std::exchange(other.writing, false); + closed = std::exchange(other.closed, true); + + return *this; +} + +void BarFile::close() { + if (closed) { + return; + } + + if (reading || writing) { + throw std::runtime_error("Bar file closed while in memory operation"); + } + + munmap(barFile.map, barFile.len); + ::close(barFile.fd); +} + +bool BarFile::isClosed() const noexcept { + return closed; +} + +size_t BarFile::getLen() const noexcept { + if (closed) { + return 0; + } + + return barFile.len; +} + +volatile void *BarFile::getRawPtr(size_t address) const noexcept { + if (closed) { + return nullptr; + } + + if (address >= barFile.len) { + return nullptr; + } + + volatile uint8_t *p = static_cast(barFile.map); + + return &p[address]; +} + +} diff --git a/vrt/vrtd/libvrtdpp/src/device.cpp b/vrt/vrtd/libvrtdpp/src/device.cpp new file mode 100644 index 00000000..9eb8c791 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/device.cpp @@ -0,0 +1,43 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +namespace vrtd { + +Device::Device(uint32_t num, std::string_view name, std::function fGetBar) { + this->num = num; + this->name = name; + this->fGetBar = fGetBar; +} + +uint32_t Device::getNum() const noexcept { + return num; +} + +const std::string& Device::getName() const noexcept { + return name; +} + +Bar Device::getBar(uint8_t num) const { + return fGetBar(*this, num); +} + +} diff --git a/vrt/vrtd/libvrtdpp/src/error.cpp b/vrt/vrtd/libvrtdpp/src/error.cpp new file mode 100644 index 00000000..42ae734b --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/error.cpp @@ -0,0 +1,61 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +namespace vrtd { + +Error::Error(vrtd_ret errorCode) noexcept { + this->errorCode = errorCode; +} + +vrtd_ret Error::getErrorCode() const noexcept { + return errorCode; +} + +const char *Error::what() const noexcept { + switch (errorCode) { + case VRTD_RET_BAD_LIB_CALL: + return "Bad library call"; + + case VRTD_RET_BAD_CONN: + return "Bad connection to daemon"; + + case VRTD_RET_BAD_REQUEST: + return "Bad request"; + + case VRTD_RET_INVALID_ARGUMENT: + return "Invalid argument"; + + case VRTD_RET_NOEXIST: + return "Requested resouce doesn't exist"; + + case VRTD_RET_INTERNAL_ERROR: + return "Internal error in vrtd daemon"; + + case VRTD_RET_AUTH_ERROR: + return "Missing permission"; + + default: + return "Unknown error"; + } +} + +} diff --git a/vrt/vrtd/libvrtdpp/src/qdma_qpair.cpp b/vrt/vrtd/libvrtdpp/src/qdma_qpair.cpp new file mode 100644 index 00000000..9c7e28d8 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/qdma_qpair.cpp @@ -0,0 +1,155 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include +#include +#include +#include + +namespace vrtd { + +QdmaQpair::QdmaQpair(uint32_t devNum, + uint32_t qid, + std::function fStart, + std::function fStop, + std::function fDelete, + std::function fOpenFd) noexcept + : devNum(devNum) + , qid(qid) + , owned(true) + , fStart(std::move(fStart)) + , fStop(std::move(fStop)) + , fDelete(std::move(fDelete)) + , fOpenFd(std::move(fOpenFd)) +{ +} + +QdmaQpair::~QdmaQpair() +{ + if (!owned) { + return; + } + + if (!fDelete || qid == 0) { + return; + } + + try { + fDelete(*this); + } catch (...) { + // Destructors must not throw; ignore errors on best-effort delete. + } +} + +QdmaQpair::QdmaQpair(QdmaQpair&& other) noexcept + : devNum(other.devNum) + , qid(other.qid) + , owned(other.owned) + , fStart(std::move(other.fStart)) + , fStop(std::move(other.fStop)) + , fDelete(std::move(other.fDelete)) + , fOpenFd(std::move(other.fOpenFd)) +{ + other.owned = false; + other.qid = 0; +} + +QdmaQpair& QdmaQpair::operator=(QdmaQpair&& other) noexcept +{ + if (this == &other) { + return *this; + } + + // Drop current ownership (best-effort delete in destructor semantics) + if (owned && fDelete && qid != 0) { + try { + fDelete(*this); + } catch (...) { + // ignore + } + } + + devNum = other.devNum; + qid = other.qid; + owned = other.owned; + fStart = std::move(other.fStart); + fStop = std::move(other.fStop); + fDelete= std::move(other.fDelete); + fOpenFd= std::move(other.fOpenFd); + + other.owned = false; + other.qid = 0; + + return *this; +} + +void QdmaQpair::start() +{ + if (!fStart) { + throw std::runtime_error("QDMA qpair start not available"); + } + + fStart(*this); +} + +void QdmaQpair::stop() +{ + if (!fStop) { + throw std::runtime_error("QDMA qpair stop not available"); + } + + fStop(*this); +} + +int QdmaQpair::fd(uint32_t flags) +{ + if (!fOpenFd) { + throw std::runtime_error("QDMA qpair fd() not available"); + } + + return fOpenFd(*this, flags); +} + +std::fstream QdmaQpair::fstream(uint32_t flags, std::ios_base::openmode mode) +{ + int qfd = fd(flags); + + try { + std::string path = "/proc/self/fd/" + std::to_string(qfd); + + std::fstream stream; + stream.open(path, mode); + + ::close(qfd); + + if (!stream.is_open()) { + throw std::runtime_error("Failed to open fstream for QDMA qpair"); + } + + return stream; + } catch (...) { + ::close(qfd); + throw; + } +} + +} // namespace vrtd diff --git a/vrt/vrtd/libvrtdpp/src/session.cpp b/vrt/vrtd/libvrtdpp/src/session.cpp new file mode 100644 index 00000000..3fa6074e --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/session.cpp @@ -0,0 +1,251 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#include "vrtd/wire.h" +#endif + +#include +#include + +#include +#include +#include +#include +#include + +namespace vrtd { + +Session::Session(const char *socketPath) +: m(std::make_unique()) { + fd = vrtd_connect(socketPath); + + if (fd == -1) { + throw std::runtime_error(std::string("Failed to open socket ") + strerrordesc_np(errno)); + } +} + +Session::~Session() noexcept +{ + close(); +} + +Session::Session(Session&& other) noexcept +{ + if (!other.isClosed()) { + std::lock_guard lk(*other.m); + + fd = std::exchange(other.fd, -1); + m = std::exchange(other.m, nullptr); + } else { + fd = -1; + m = nullptr; + } +} + +Session& Session::operator=(Session&& other) noexcept +{ + close(); + + if (!other.isClosed()) { + std::lock_guard lk(*other.m); + + fd = std::exchange(other.fd, -1); + m = std::exchange(other.m, nullptr); + } + + return *this; +} + +uint32_t Session::getNumDevices() const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + uint32_t numDevices; + + auto ret = vrtd_get_num_devices(fd, &numDevices); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return numDevices; +} + +Device Session::getDevice(size_t i) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + char name[128]; + + auto ret = vrtd_get_device_info(fd, i, name); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return Device(i, {name, strlen(name)}, [&](const Device& device, uint8_t num) { return getBar(device, num); } ); +} + +Bar Session::getBar(const Device& device, uint8_t num) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + slash_ioctl_bar_info barInfo; + + auto ret = vrtd_get_bar_info(fd, device.getNum(), num, &barInfo); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return Bar(device.getNum(), num, barInfo.usable, barInfo.in_use, barInfo.start_address, barInfo.length, [&](const Bar&bar) { return openBarFile(bar); } ); +} + +BarFile Session::openBarFile(const Bar& bar) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + slash_bar_file barFile; + + auto ret = vrtd_open_bar_file(fd, bar.getDeviceNum(), bar.getNum(), &barFile); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return BarFile(barFile); +} + +slash_qdma_info Session::getQdmaInfo(const Device& device) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + slash_qdma_info info; + auto ret = vrtd_qdma_get_info(fd, device.getNum(), &info); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return info; +} + +QdmaQpair Session::createQdmaQpair( + const Device& device, + const slash_qdma_qpair_add& cfg +) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + slash_qdma_qpair_add tmp = cfg; + auto ret = vrtd_qdma_qpair_add(fd, device.getNum(), &tmp); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return QdmaQpair( + device.getNum(), + tmp.qid, + [this, device](const QdmaQpair& qp) { startQdmaQpair(device, qp.getQid()); }, + [this, device](const QdmaQpair& qp) { stopQdmaQpair(device, qp.getQid()); }, + [this, device](const QdmaQpair& qp) { deleteQdmaQpair(device, qp.getQid()); }, + [this, device](const QdmaQpair& qp, uint32_t flags) { return openQdmaQpairFd(device, qp.getQid(), flags); } + ); +} + +void Session::startQdmaQpair(const Device& device, uint32_t qid) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + auto ret = vrtd_qdma_qpair_start(fd, device.getNum(), qid); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } +} + +void Session::stopQdmaQpair(const Device& device, uint32_t qid) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + auto ret = vrtd_qdma_qpair_stop(fd, device.getNum(), qid); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } +} + +void Session::deleteQdmaQpair(const Device& device, uint32_t qid) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + auto ret = vrtd_qdma_qpair_del(fd, device.getNum(), qid); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } +} + +int Session::openQdmaQpairFd(const Device& device, uint32_t qid, uint32_t flags) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + int qfd = -1; + auto ret = vrtd_qdma_qpair_get_fd(fd, device.getNum(), qid, flags, &qfd); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return qfd; +} + +void Session::close() noexcept { + if (isClosed()) { + return; + } + + ::close(fd); + fd = -1; + m = nullptr; +} + +bool Session::isClosed() const noexcept { + if (fd == -1 || !m) { + return true; + } else { + return false; + } +} + +} diff --git a/vrt/vrtd/src/CMakeLists.txt b/vrt/vrtd/src/CMakeLists.txt new file mode 100644 index 00000000..b86e013d --- /dev/null +++ b/vrt/vrtd/src/CMakeLists.txt @@ -0,0 +1,51 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +# Library sources (list explicitly; avoid GLOB for reproducible builds) +add_executable(vrtd + ${CMAKE_CURRENT_SOURCE_DIR}/accept.c + ${CMAKE_CURRENT_SOURCE_DIR}/auth.c + ${CMAKE_CURRENT_SOURCE_DIR}/config.c + ${CMAKE_CURRENT_SOURCE_DIR}/device.c + ${CMAKE_CURRENT_SOURCE_DIR}/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/serve.c + ${CMAKE_CURRENT_SOURCE_DIR}/signals.c +) + + +# C standard / properties +set_target_properties(vrtd PROPERTIES + C_STANDARD 11 + C_STANDARD_REQUIRED YES + C_EXTENSIONS YES + VERSION ${PROJECT_VERSION} + SOVERSION ${PROJECT_VERSION_MAJOR} +) + +# Public include dir (for consumers) and private include dir (for .c / private headers) +target_include_directories(vrtd + PUBLIC + $ + $ + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR} +) + +target_link_libraries(vrtd PRIVATE slash::slash systemd inih) diff --git a/vrt/vrtd/src/accept.c b/vrt/vrtd/src/accept.c new file mode 100644 index 00000000..44257b3d --- /dev/null +++ b/vrt/vrtd/src/accept.c @@ -0,0 +1,212 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#define _GNU_SOURCE + +#include "accept.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "utils.h" +#include "serve.h" +#include "state.h" + +static int create_client_event(sd_event_source *listener_event_source, int cfd, struct vrtd *state, struct client **clientp); +static int populate_uid_gid(int cfd, struct client *client); + +int on_event_new_connection(sd_event_source *s, int fd, uint32_t revents, void *userdata) +{ + struct vrtd *state = userdata; + + assert(state != NULL); + + if (!(revents & EPOLLIN)) { + return 0; + } + + for (;;) { + struct sockaddr_un peer; + socklen_t peerlen = sizeof(peer); + int cfd = accept4(fd, (struct sockaddr*)&peer, &peerlen, SOCK_NONBLOCK | SOCK_CLOEXEC); + if (cfd == -1) { + if (errno == EINTR) { + continue; + } + if (errno == EAGAIN || errno == EWOULDBLOCK) { + break; /* all pending connections accepted */ + } + (void) sd_journal_print(LOG_ERR, "accept4() failed: %m"); + return -1; + } + + _cleanup_(cleanup_clientp) + struct client *client; + int ret = create_client_event(s, cfd, state, &client); + if (ret == -1) { + close(cfd); + continue; + } + + assert(client != NULL); + + ret = client_ptr_array_push_move(&state->clients, &client); + if (ret == -1) { + (void) sd_journal_print(LOG_ERR, "Failed to allocate memory when adding new client"); + continue; + } + } + + return 0; +} + + +static int create_client_event(sd_event_source *listener_event_source, int cfd, struct vrtd *state, struct client **clientp) +{ + *clientp = calloc(1, sizeof **clientp); + PROPAGATE_ERROR_NULL_STDC_LOG(clientp, LOG_ERR, "Out of memory allocating client data"); + + _cleanup_(cleanup_clientp) + struct client *client = *clientp; + + _cleanup_(cleanup_free) + char *description = NULL; + + // If something fails, we should disable + unref. + _cleanup_(sd_event_source_disable_unrefp) + sd_event_source *source = NULL; + + sd_event *ev = sd_event_source_get_event(listener_event_source); + PROPAGATE_ERROR_NULL_LOG(ev, LOG_ERR, "Failed to get event for source"); + + int ret = sd_event_add_io(ev, &source, cfd, EPOLLIN | EPOLLRDHUP, on_client_io, client); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to add client as event source"); + + { + struct ucred cred; + socklen_t clen = sizeof(cred); + if (getsockopt(cfd, SOL_SOCKET, SO_PEERCRED, &cred, &clen) == 0) { + ret = asprintf(&description, "client fd=%d pid=%d uid=%d gid=%d", + cfd, (int)cred.pid, (int)cred.uid, (int)cred.gid); + } else { + ret = asprintf(&description, "client fd=%d", cfd); + } + } + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Failed to allocate description for client"); + + ret = populate_uid_gid(cfd, client); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Failed to obtain user/group information for lcient"); + + ret = sd_event_source_set_description(source, description); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Could not set description for client fd"); + + client->fd = cfd; + client->state = state; + client->event_source = source; + + // Nothing went wrong. Do not unref. + source = NULL; + + // Nothing went wrong. Do not remove client. + client = NULL; + + return 0; +} + +static +int populate_uid_gid(int cfd, struct client *client) +{ + if (!client || cfd < 0) { + sd_journal_print(LOG_ERR, "populate_uid_gid: invalid arguments"); + return -1; + } + + // --- Identify peer (SO_PEERCRED) --- + struct ucred cred = {0}; + socklen_t len = sizeof(cred); + int rc = getsockopt(cfd, SOL_SOCKET, SO_PEERCRED, &cred, &len); + PROPAGATE_ERROR_STDC_LOG(rc, LOG_ERR, "SO_PEERCRED failed"); + + uid_t new_uid = cred.uid; + + // --- Lookup passwd entry for username (for getgrouplist) --- + long buflen = sysconf(_SC_GETPW_R_SIZE_MAX); + if (buflen <= 0 || buflen > (1 << 20)) buflen = 16384; + + _cleanup_(cleanup_free) char *pwbuf = malloc((size_t)buflen); + PROPAGATE_ERROR_NULL_STDC_LOG(pwbuf, LOG_ERR, "malloc pwbuf"); + + struct passwd pwent, *pw = NULL; + int pr = getpwuid_r(new_uid, &pwent, pwbuf, (size_t)buflen, &pw); + if (pr != 0 || !pw) { + sd_journal_print(LOG_ERR, "getpwuid_r(%u) failed: %s", + (unsigned)new_uid, + pr ? strerrordesc_np(pr) : "not found"); + return -1; + } + + // --- Probe exact group count, then allocate exactly that many --- + int ngroups = 0; + (void)getgrouplist(pw->pw_name, cred.gid, NULL, &ngroups); // expected to return -1 + if (ngroups <= 0) { + sd_journal_print(LOG_ERR, "getgrouplist probe returned non-positive size for user %s", pw->pw_name); + return -1; + } + + _cleanup_(cleanup_free) gid_t *groups = malloc((size_t)ngroups * sizeof(gid_t)); + PROPAGATE_ERROR_NULL_STDC_LOG(groups, LOG_ERR, "malloc groups[%d]", ngroups); + + int gl = getgrouplist(pw->pw_name, cred.gid, groups, &ngroups); + if (gl < 0 || ngroups <= 0) { + sd_journal_print(LOG_ERR, "getgrouplist fetch failed for user %s", pw->pw_name); + return -1; + } + + // --- Commit atomically: reset gids, set uid, then push all groups --- + // Leave client untouched until now; from here on, rollbacks are manual. + gid_t_array_free(&client->gids); + client->uid = new_uid; + + for (int i = 0; i < ngroups; ++i) { + int r = gid_t_array_push(&client->gids, groups[i]); + if (r == -1) { + sd_journal_print(LOG_ERR, "gid_t_array_push failed at index %d", i); + // Roll back to consistent "unset" state + gid_t_array_free(&client->gids); + client->uid = (uid_t)-1; + return -1; + } + } + + return 0; +} + + diff --git a/vrt/vrtd/src/accept.h b/vrt/vrtd/src/accept.h new file mode 100644 index 00000000..48a907ee --- /dev/null +++ b/vrt/vrtd/src/accept.h @@ -0,0 +1,30 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_ACCEPT_H +#define VRTD_ACCEPT_H + +#include + +#include + +int on_event_new_connection(sd_event_source *s, int fd, uint32_t revents, void *userdata); + +#endif // VRTD_ACCEPT_H diff --git a/vrt/vrtd/src/array.h b/vrt/vrtd/src/array.h new file mode 100644 index 00000000..83dace0c --- /dev/null +++ b/vrt/vrtd/src/array.h @@ -0,0 +1,220 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_ARRAY_H +#define VRTD_ARRAY_H + +#include +#include +#include + +#include + +#include "utils.h" + +// DECLARE_ARRAY declares a dynamic array of type T. +// +// Access is done directly via a.d[i] and a.len. The 0-value is the 0-len array. +// +#define DECLARE_ARRAY_IMPL(T_ARRAY, T) \ + struct T_ARRAY { \ + T *d; \ + size_t len; \ + size_t cap; \ + }; \ + \ + static inline \ + struct T_ARRAY T_ARRAY##_init(void) { \ + return (struct T_ARRAY) { \ + .d = NULL, \ + .len = 0, \ + .cap = 0, \ + }; \ + } \ + \ + static inline NODISCARD \ + int T_ARRAY##_resize(struct T_ARRAY *arr, size_t len) \ + { \ + size_t cap = likely(len > 0) ? bit_ceil(len) : 0; \ + T *d; \ + \ + /* Don't constantly reallocate for add-remove 1024-1025 elements */ \ + /* This may reallocate unnecessarily (once) for tightened arrays but this is fine */ \ + /* Tighthening should only be done for arrays that will keep their size for a long time */ \ + /* Otherwise we'd have to complicate this hot comparison */ \ + if (cap == arr->cap || cap == (arr->cap >> 1)) { \ + arr->len = len; \ + return 0; \ + } \ + \ + d = (T *) reallocarray(arr->d, cap, sizeof(T)); \ + if (unlikely(d == NULL && cap != 0)) { \ + return -1; \ + } \ + \ + arr->d = d; \ + arr->len = len; \ + arr->cap = cap; \ + \ + return 0; \ + } \ + \ + static inline NODISCARD \ + int T_ARRAY##_push(struct T_ARRAY *arr, T v) { \ + if (unlikely(T_ARRAY##_resize(arr, arr->len + 1) == -1)) { \ + return -1; \ + } \ + arr->d[arr->len - 1] = v; \ + return 0; \ + } \ + \ + static inline int T_ARRAY##_pop(struct T_ARRAY *arr, T *out) { \ + if (arr->len == 0) { \ + return -1; \ + } \ + \ + if (out != NULL) { \ + *out = arr->d[arr->len - 1]; \ + } \ + \ + return T_ARRAY##_resize(arr, arr->len - 1); \ + } \ + \ + static inline void T_ARRAY##_pop_safe(struct T_ARRAY *arr, T *out) { \ + if (arr->len == 0) { \ + return; \ + } \ + \ + if (out != NULL) { \ + *out = arr->d[arr->len - 1]; \ + } \ + \ + arr->len--; \ + } \ + \ + static inline \ + void T_ARRAY##_zero(struct T_ARRAY *arr) \ + { \ + memset(arr->d, 0, arr->cap * sizeof(T)); \ + } \ + \ + static inline \ + int T_ARRAY##_shrink_to_fit(struct T_ARRAY *arr) \ + { \ + T *d; \ + \ + d = (T *) reallocarray(arr->d, arr->len, sizeof(T)); \ + if (unlikely(d == NULL && arr->len != 0)) { \ + return -1; \ + } \ + \ + arr->d = d; \ + arr->cap = arr->len; \ + \ + return 0; \ + } \ + \ + static inline \ + void T_ARRAY##_rm_by_value_impl(struct T_ARRAY *arr, T value) \ + { \ + size_t j = 0; \ + for (size_t i = 0; i < arr->len; i++) { \ + if (arr->d[i] == value) { \ + continue; \ + } \ + \ + arr->d[j++] = arr->d[i]; \ + } \ + \ + arr->len = j; \ + } \ + \ + static inline \ + void T_ARRAY##_free_impl(struct T_ARRAY *arr) \ + { \ + free(arr->d); \ + \ + arr->d = NULL; \ + arr->len = 0; \ + arr->cap = 0; \ + } + +#define DECLARE_ARRAY(T_ARRAY, T) \ + DECLARE_ARRAY_IMPL(T_ARRAY, T) \ + \ + static inline \ + void T_ARRAY##_free(struct T_ARRAY *arr) \ + { \ + T_ARRAY##_free_impl(arr); \ + } \ +\ + static inline \ + void T_ARRAY##_freep(struct T_ARRAY **arr) \ + { \ + T_ARRAY##_free(*arr); \ + *arr = NULL; \ + } \ + \ + static inline \ + void T_ARRAY##_rm_by_value(struct T_ARRAY *arr, T value) \ + { \ + T_ARRAY##_rm_by_value_impl(arr, value); \ + } + +#define DECLARE_OWNING_PTR_ARRAY(T_ARRAY, T, CLEANUP) \ + DECLARE_ARRAY_IMPL(T_ARRAY, T) \ + \ + static inline \ + int T_ARRAY##_push_move(struct T_ARRAY *arr, T *ptr) \ + { \ + int ret = T_ARRAY##_push(arr, *ptr); \ + if (unlikely(ret == -1)) { \ + return -1; \ + } \ + \ + *ptr = NULL; \ + \ + return 0; \ + } \ + \ + static inline \ + void T_ARRAY##_free(struct T_ARRAY *arr) \ + { \ + for (size_t i = 0; i < arr->len; ++i) { \ + CLEANUP(arr->d[i]); \ + } \ + \ + T_ARRAY##_free_impl(arr); \ + } \ + \ + static inline \ + void T_ARRAY##_rm_by_value(struct T_ARRAY *arr, T value) \ + { \ + T_ARRAY##_rm_by_value_impl(arr, value); \ + \ + CLEANUP(value); \ + } + +DECLARE_ARRAY(int_array, int) +DECLARE_ARRAY(uint_array, unsigned int) +DECLARE_ARRAY(gid_t_array, gid_t) +DECLARE_OWNING_PTR_ARRAY(str_array, char *, free) + +#endif // VRTD_ARRAY_H diff --git a/vrt/vrtd/src/auth.c b/vrt/vrtd/src/auth.c new file mode 100644 index 00000000..642085b8 --- /dev/null +++ b/vrt/vrtd/src/auth.c @@ -0,0 +1,285 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#define _GNU_SOURCE + +#include "auth.h" +#include "config.h" +#include "state.h" +#include "utils.h" + +#include +#include +#include + +int ensure_role(struct client *client); + +int auth_request_get_device_info( + struct client *client, + const struct vrtd_req_get_device_info *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (client->role->query) { + return 1; + } else { + return 0; + } +} + +int auth_request_get_num_devices( + struct client *client, + const struct vrtd_req_get_num_devices *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (client->role->query) { + return 1; + } else { + return 0; + } +} + +int auth_request_get_bar_info( + struct client *client, + const struct vrtd_req_get_bar_info *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (client->role->query) { + return 1; + } else { + return 0; + } +} + +int auth_request_get_bar_fd( + struct client *client, + const struct vrtd_req_get_bar_fd *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (!client->role->query) { + return 0; + } + + if (!client->role->allow_any_device) { + return 0; + } + + if (!client->role->bar_policy.any) { + return 0; + } + + return 1; +} + +int auth_request_qdma_get_info( + struct client *client, + const struct vrtd_req_qdma_get_info *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (client->role->query) { + return 1; + } else { + return 0; + } +} + +int auth_request_qdma_qpair_add( + struct client *client, + const struct vrtd_req_qdma_qpair_add *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (!client->role->query) { + return 0; + } + + if (!client->role->allow_any_device) { + return 0; + } + + if (!client->role->bar_policy.any) { + /* TODO: introduce a dedicated QDMA policy instead of reusing bar_policy. */ + return 0; + } + + return 1; +} + +int auth_request_qdma_qpair_op( + struct client *client, + const struct vrtd_req_qdma_qpair_op *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (!client->role->query) { + return 0; + } + + if (!client->role->allow_any_device) { + return 0; + } + + if (!client->role->bar_policy.any) { + /* TODO: introduce a dedicated QDMA policy instead of reusing bar_policy. */ + return 0; + } + + return 1; +} + +int auth_request_qdma_qpair_get_fd( + struct client *client, + const struct vrtd_req_qdma_qpair_get_fd *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (!client->role->query) { + return 0; + } + + if (!client->role->allow_any_device) { + return 0; + } + + if (!client->role->bar_policy.any) { + /* TODO: introduce a dedicated QDMA policy instead of reusing bar_policy. */ + return 0; + } + + return 1; +} + +int ensure_role(struct client *client) +{ + assert(client != NULL); + + if (client->role != NULL) { + return 0; + } + + _cleanup_(cleanup_free) + char *role_name = NULL; + + int ret = asprintf(&role_name, "Internal role for user: %u", (unsigned int) client->uid); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Allocation error when intenral role for user"); + + _cleanup_(cleanup_rolep) + struct role *role = NULL; + + ret = role_merge_new(&role, "TODO: Change this string"); + PROPAGATE_ERROR(ret); + + assert(client->state != NULL); + assert(client->state->config != NULL); + + const struct config *config = client->state->config; + + ret = role_merge_add_array(role, &config->default_user->roles); + PROPAGATE_ERROR(ret); + + for (size_t i = 0; i < config->users.len; i++) { + const struct user_config *user_config = config->users.d[i]; + assert(user_config != NULL); + + if (user_config->uid == client->uid) { + ret = role_merge_add_array(role, &user_config->roles); + PROPAGATE_ERROR(ret); + } + } + + for (size_t i = 0; i < config->groups.len; i++) { + const struct group_config *group_config = config->groups.d[i]; + assert(group_config != NULL); + + for (size_t j = 0; j < client->gids.len; j++) { + gid_t gid = client->gids.d[j]; + + if (group_config->gid == gid) { + ret = role_merge_add_array(role, &group_config->roles); + PROPAGATE_ERROR(ret); + } + } + } + + client->role = role; + role = NULL; + + return 0; +} diff --git a/vrt/vrtd/src/auth.h b/vrt/vrtd/src/auth.h new file mode 100644 index 00000000..77ca6b86 --- /dev/null +++ b/vrt/vrtd/src/auth.h @@ -0,0 +1,66 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_AUTH_H +#define VRTD_AUTH_H + +#include "serve.h" + +int auth_request_get_device_info( + struct client *client, + const struct vrtd_req_get_device_info *req_body +); + +int auth_request_get_num_devices( + struct client *client, + const struct vrtd_req_get_num_devices *req_body +); + +int auth_request_get_bar_info( + struct client *client, + const struct vrtd_req_get_bar_info *req_body +); + +int auth_request_get_bar_fd( + struct client *client, + const struct vrtd_req_get_bar_fd *req_body +); + +int auth_request_qdma_get_info( + struct client *client, + const struct vrtd_req_qdma_get_info *req_body +); + +int auth_request_qdma_qpair_add( + struct client *client, + const struct vrtd_req_qdma_qpair_add *req_body +); + +int auth_request_qdma_qpair_op( + struct client *client, + const struct vrtd_req_qdma_qpair_op *req_body +); + +int auth_request_qdma_qpair_get_fd( + struct client *client, + const struct vrtd_req_qdma_qpair_get_fd *req_body +); + +#endif // VRTD_AUTH_H diff --git a/vrt/vrtd/src/config.c b/vrt/vrtd/src/config.c new file mode 100644 index 00000000..28fd7c5a --- /dev/null +++ b/vrt/vrtd/src/config.c @@ -0,0 +1,647 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#define _GNU_SOURCE + +#define VRTD_DEFAULT_CONFIG_PATH "/etc/vrt/vrtd.conf" + +#include "array.h" +#include "config.h" +#include "utils.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +// This is on Ubuntu +static_assert(INI_HANDLER_LINENO == 0, "vrtd does not support INI_HANDLER_LINENO = 1"); + +static const char DEFAULT_USER_NAME[] = "*"; + +struct config_parse_state { + struct config *config; + + struct str_array visited_files; +}; + +static int parse_file_glob(struct config_parse_state *state, const char *pattern); +static int parse_file(struct config_parse_state *state, const char *path); +static int parse_file_unique(struct config_parse_state *state, const char *path); +static int parse_config_callback(void *user, const char *section, const char *name, const char *value); +static int role_find_and_add_value(struct config *config, const char *objname, const char *name, const char *value); +static int role_add_value(struct role *role, const char *name, const char *value); +static int user_find_and_add_value(struct config *config, const char *objname, const char *name, const char *value); +static int user_add_value(struct user_config *user, const char *name, const char *value); +static int group_find_and_add_value(struct config *config, const char *objname, const char *name, const char *value); +static int group_add_value(struct group_config *group, const char *name, const char *value); +static int set_user_uid(uid_t *uid, const char *name); +static int set_group_gid(gid_t *gid, const char *name); +static int assign_users_roles(struct config *config); +static int assign_user_roles(struct config *config, struct user_config *user); +static int assign_groups_roles(struct config *config); +static int assign_group_roles(struct config *config, struct group_config *group); + +// Cleanups + +void cleanup_role(struct role *role) +{ + if (role == NULL) { + return; + } + + free(role->name); + role->name = NULL; + + uint_array_free(&role->allowed_devices); + + free(role); +} + +void cleanup_user_config(struct user_config *user) +{ + if (user == NULL) { + return; + } + + free(user->name); + user->name = NULL; + + str_array_free(&user->role_names); + role_ref_array_free(&user->roles); + + free(user); +} + +void cleanup_group_config(struct group_config *group) +{ + if (group == NULL) { + return; + } + + free(group->name); + group->name = NULL; + + str_array_free(&group->role_names); + role_ref_array_free(&group->roles); + + free(group); +} + +void cleanup_config(struct config *config) +{ + if (config == NULL) { + return; + } + + role_ptr_array_free(&config->roles); + + cleanup_user_config(config->default_user); + + user_config_ptr_array_free(&config->users); + group_config_ptr_array_free(&config->groups); + + free(config); +} + +static inline +void cleanup_parse_state_stack(struct config_parse_state *state) +{ + state->config = NULL; + + str_array_free(&state->visited_files); +} + +// Role merge + +int role_merge_new(struct role **rolep, const char *name) +{ + assert(rolep != NULL); + + _cleanup_(cleanup_rolep) + struct role *role = calloc(1, sizeof *role); + PROPAGATE_ERROR_NULL_STDC_LOG(role, LOG_ERR, "Error allocating new role"); + + _cleanup_(cleanup_free) + char *s = strdup(name); + PROPAGATE_ERROR_NULL_STDC_LOG(s, LOG_ERR, "Error allocating new role"); + + role->name = s; + s = NULL; + + *rolep = role; + role = NULL; + + return 0; +} + +int role_merge_add_role(struct role *dst, const struct role *src) +{ + if (dst == NULL || src == NULL) { + assert(false); + return -1; + } + + /* Highest privilege wins => OR the booleans. */ + dst->pcie_hotplug = dst->pcie_hotplug || src->pcie_hotplug; + dst->query = dst->query || src->query; + dst->allow_any_device= dst->allow_any_device|| src->allow_any_device; + dst->bar_policy.any = dst->bar_policy.any || src->bar_policy.any; + + /* TODO: Intentionally skip allowed_devices merging for now. */ + return 0; +} + +int role_merge_add_array(struct role *dst, const struct role_ref_array *roles) +{ + if (dst == NULL || roles == NULL) { + assert(false); + return -1; + } + + for (size_t i = 0; i < roles->len; ++i) { + const struct role *r = roles->d[i]; + assert(r != NULL); + + int ret = role_merge_add_role(dst, r); + PROPAGATE_ERROR(ret); + } + + return 0; +} + + + +int config_load(struct config **configp) +{ + _cleanup_(cleanup_parse_state_stack) + struct config_parse_state state = {0}; + + // Cleanup on error + _cleanup_(cleanup_configp) + struct config *config = calloc(1, sizeof(**configp)); + + config->default_user = calloc(1, sizeof(*config->default_user)); + PROPAGATE_ERROR_NULL_LOG(config->default_user, LOG_ERR, "Memory error assigning default user"); + + config->default_user->name = strdup(DEFAULT_USER_NAME); + PROPAGATE_ERROR_NULL_LOG(config->default_user->name, LOG_ERR, "Memory error assigning default user name"); + + state.config = config; + + const char *path = getenv("VRTD_CONFIG"); + if (path == NULL || path[0] == '\0') { + path = VRTD_DEFAULT_CONFIG_PATH; + } + + int ret = parse_file(&state, path); + + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to parse config file"); + + ret = assign_users_roles(config); + PROPAGATE_ERROR(ret); + + ret = assign_groups_roles(config); + PROPAGATE_ERROR(ret); + + // No error, do not cleanup + *configp = config; + config = NULL; + + return 0; +} + +static int parse_file_glob(struct config_parse_state *state, const char *pattern) +{ + _cleanup_(globfree) + glob_t glob_state; + memset(&glob_state, 0, sizeof(glob_state)); + + int ret = glob(pattern, GLOB_ERR, NULL, &glob_state); + if (ret == GLOB_NOMATCH) { + return 0; + } else if (ret != 0) { + (void) sd_journal_print( + LOG_ERR, + "Error matching pattern %s: %s", + pattern, + glob_err_to_string(ret) + ); + + return -1; + } + + for (size_t i = 0; i < glob_state.gl_pathc; i++) { + ret = parse_file(state, glob_state.gl_pathv[i]); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Found by pattern %s", pattern); + } + + return 0; +} + +static int parse_file(struct config_parse_state *state, const char *path) +{ + _cleanup_(cleanup_free) + char *full_path = realpath(path, NULL); + PROPAGATE_ERROR_NULL_STDC_LOG(full_path, LOG_ERR, "Error obtaining the cannonical path for %s", path); + + for (size_t i = 0; i < state->visited_files.len; i++) { + if (strcmp(full_path, state->visited_files.d[i]) == 0) { + /* We have already parsed this file -- exit as OK */ + return 0; + } + } + + char *full_path_ref = full_path; + + int ret = str_array_push_move(&state->visited_files, &full_path); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Error processing %s", full_path); + + ret = parse_file_unique(state, full_path_ref); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Error parsing file %s", full_path_ref); + + return 0; +} + +static int parse_file_unique(struct config_parse_state *state, const char *path) +{ + int ret = ini_parse(path, parse_config_callback, state); + if (ret != 0) { + if (ret > 0) { + (void) sd_journal_print(LOG_ERR, "Parse error at %s:%d", path, ret); + return -1; + } else if (ret == -1) { + (void) sd_journal_print(LOG_ERR, "Could not open file %s", path); + return -1; + } else if (ret == -2) { + (void) sd_journal_print(LOG_ERR, "Out of memory reading file %s", path); + return -1; + } else { + (void) sd_journal_print(LOG_WARNING, "Unknown error reading file %s", path); + return 0; + } + } + + return 0; +} + +// This callback uses 0 for error and 1 for success, as per inih spec +static int parse_config_callback(void *user, const char *section, const char *name, const char *value) +{ + #define MATCH(s, n) (strcmp(section, s) == 0 && strcmp(name, n) == 0) + #define MATCH_OBJECT(c, n) \ + ({ const char *colon__ = strchr(section, ':'); \ + colon__ && (size_t)(colon__ - section) == strlen(c) && \ + memcmp(section, (c), strlen(c)) == 0 && \ + (n = colon__ + 1, n[0] != '\0'); \ + }) + + int ret; + const char *objname; + struct config_parse_state *state = user; + + if (MATCH("", "include")) { + ret = parse_file(state, value); + if (ret == -1) { + return 0; + } + } else if (MATCH("", "include-glob")) { + ret = parse_file_glob(state, value); + if (ret == -1) { + return 0; + } + } else if (MATCH("", "enable-mock-device")) { + state->config->mock_device = string_to_bool(value); + } else if (MATCH_OBJECT("role", objname)) { + ret = role_find_and_add_value(state->config, objname, name, value); + if (ret == -1) { + return 0; + } + } else if (MATCH_OBJECT("user", objname)) { + ret = user_find_and_add_value(state->config, objname, name, value); + if (ret == -1) { + return 0; + } + } else if (MATCH_OBJECT("group", objname)) { + ret = group_find_and_add_value(state->config, objname, name, value); + if (ret == -1) { + return 0; + } + } else { + (void) sd_journal_print(LOG_WARNING, "Unknown section/key: [%s] %s", section, name); + return 1; + } + + return 1; + + #undef MATCH + #undef MATCH_OBJECT +} + +static int role_find_and_add_value(struct config *config, const char *objname, const char *name, const char *value) +{ + for (size_t i = 0; i < config->roles.len; ++i) { + if (strcmp(config->roles.d[i]->name, objname) == 0) { + return role_add_value(config->roles.d[i], name, value); + } + } + + _cleanup_(cleanup_rolep) + struct role *role = calloc(1, sizeof *role); + PROPAGATE_ERROR_NULL_STDC_LOG(role, LOG_ERR, "Could not allocate role"); + + role->name = strdup(objname); + PROPAGATE_ERROR_NULL_STDC_LOG(role->name, LOG_ERR, "Could not allocate role name"); + + int ret = role_add_value(role, name, value); + PROPAGATE_ERROR(ret); + + ret = role_ptr_array_push_move(&config->roles, &role); + PROPAGATE_ERROR(ret); + + return 0; +} + +static int role_add_value(struct role *role, const char *name, const char *value) +{ + if (strcmp(name, "pcie-hotplug") == 0) { + if (strcmp(value, "yes") == 0) { + role->pcie_hotplug = true; + return 0; + } else if (strcmp(value, "no") == 0) { + role->pcie_hotplug = false; + return 0; + } else { + return -1; + } + } else if (strcmp(name, "bar-access") == 0) { + if (strcmp(value, "full") == 0) { + role->bar_policy.any = true; + return 0; + } else { + return -1; + } + } else if (strcmp(name, "device") == 0) { + if (strcmp(value, "any") == 0) { + role->allow_any_device = true; + return 0; + } else { + return -1; + } + } else if (strcmp(name, "query-devices") == 0) { + if (strcmp(value, "yes") == 0) { + role->query = true; + return 0; + } else if (strcmp(value, "no") == 0) { + role->query = false; + return 0; + } else { + return -1; + } + } else { + return -1; + } +} + +static int user_find_and_add_value(struct config *config, const char *objname, const char *name, const char *value) +{ + if (strcmp(objname, "*") == 0) { + return user_add_value(config->default_user, name, value); + } + + for (size_t i = 0; i < config->users.len; ++i) { + if (strcmp(config->users.d[i]->name, objname) == 0) { + return user_add_value(config->users.d[i], name, value); + } + } + + _cleanup_(cleanup_user_configp) + struct user_config *user = calloc(1, sizeof *user); + PROPAGATE_ERROR_NULL_STDC_LOG(user, LOG_ERR, "Could not allocate user"); + + user->name = strdup(objname); + PROPAGATE_ERROR_NULL_STDC_LOG(user->name, LOG_ERR, "Could not allocate user name"); + + int ret = set_user_uid(&user->uid, objname); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Could not find uid for user %s", objname); + + ret = user_add_value(user, name, value); + PROPAGATE_ERROR(ret); + + ret = user_config_ptr_array_push_move(&config->users, &user); + PROPAGATE_ERROR(ret); + + return 0; +} + +static int user_add_value(struct user_config *user, const char *name, const char *value) +{ + if (strcmp(name, "role") == 0) { + _cleanup_(cleanup_free) + char *role = strdup(value); + PROPAGATE_ERROR_NULL_STDC_LOG(role, LOG_ERR, "Could not allocate role name"); + + int ret = str_array_push_move(&user->role_names, &role); + PROPAGATE_ERROR(ret); + + return 0; + } else { + return -1; + } +} + +static int group_find_and_add_value(struct config *config, const char *objname, const char *name, const char *value) +{ + for (size_t i = 0; i < config->groups.len; ++i) { + if (strcmp(config->groups.d[i]->name, objname) == 0) { + return group_add_value(config->groups.d[i], name, value); + } + } + + _cleanup_(cleanup_group_configp) + struct group_config *group = calloc(1, sizeof *group); + PROPAGATE_ERROR_NULL_STDC_LOG(group, LOG_ERR, "Could not allocate group"); + + group->name = strdup(objname); + PROPAGATE_ERROR_NULL_STDC_LOG(group->name, LOG_ERR, "Could not allocate group name"); + + int ret = set_group_gid(&group->gid, objname); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Could not find gid for group %s", objname); + + ret = group_add_value(group, name, value); + PROPAGATE_ERROR(ret); + + ret = group_config_ptr_array_push_move(&config->groups, &group); + PROPAGATE_ERROR(ret); + + return 0; +} + +static int group_add_value(struct group_config *group, const char *name, const char *value) +{ + if (strcmp(name, "role") == 0) { + _cleanup_(cleanup_free) + char *role = strdup(value); + PROPAGATE_ERROR_NULL_STDC_LOG(role, LOG_ERR, "Could not allocate role name"); + + int ret = str_array_push_move(&group->role_names, &role); + PROPAGATE_ERROR(ret); + + return 0; + } else { + return -1; + } +} + +static int set_user_uid(uid_t *uid, const char *name) +{ + size_t bufsz = BUFSIZ; + int ret; + struct passwd pwd; + struct passwd *result; + + do { + char *buf = malloc(bufsz); + PROPAGATE_ERROR_NULL_STDC_LOG(buf, LOG_ERR, "Failed malloc in get_user_uid"); + +retry: + ret = getpwnam_r(name, &pwd, buf, bufsz, &result); + if (ret == EINTR) { + goto retry; + } + + free(buf); + + bufsz *= 2; + } while (ret == ERANGE); + + PROPAGATE_ERROR_NULL_STDC_LOG(result, LOG_ERR, "User %s not found", name); + + *uid = result->pw_uid; + return 0; +} + +static int set_group_gid(gid_t *gid, const char *name) +{ + size_t bufsz = BUFSIZ; + int ret; + struct group pwd; + struct group *result; + + do { + char *buf = malloc(bufsz); + PROPAGATE_ERROR_NULL_STDC_LOG(buf, LOG_ERR, "Failed malloc in set_group_gid"); + +retry: + ret = getgrnam_r(name, &pwd, buf, bufsz, &result); + if (ret == EINTR) { + goto retry; + } + + free(buf); + + bufsz *= 2; + } while (ret == ERANGE); + + PROPAGATE_ERROR_NULL_STDC_LOG(result, LOG_ERR, "Group %s not found", name); + + *gid = result->gr_gid; + return 0; +} + +static int assign_users_roles(struct config *config) +{ + int ret = assign_user_roles(config, config->default_user); + PROPAGATE_ERROR(ret); + + for (size_t i = 0; i < config->users.len; i++) { + ret = assign_user_roles(config, config->users.d[i]); + PROPAGATE_ERROR(ret); + } + + return 0; +} + +static int assign_user_roles(struct config *config, struct user_config *user) +{ + for (size_t j = 0; j < user->role_names.len; j++) { + bool found_role_name = false; + + for (size_t k = 0; k < config->roles.len; k++) { + if (strcmp(user->role_names.d[j], config->roles.d[k]->name) == 0) { + int ret = role_ref_array_push(&user->roles, config->roles.d[k]); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed allocation in assign_user_roles"); + + found_role_name = true; + break; + } + } + + if (!found_role_name) { + (void) sd_journal_print(LOG_WARNING, "Failed to find user role %s for user %s", user->role_names.d[j], user->name); + } + } + + return 0; +} + +static int assign_groups_roles(struct config *config) +{ + for (size_t i = 0; i < config->groups.len; i++) { + int ret = assign_group_roles(config, config->groups.d[i]); + PROPAGATE_ERROR(ret); + } + + return 0; +} + +static int assign_group_roles(struct config *config, struct group_config *group) +{ + for (size_t j = 0; j < group->role_names.len; j++) { + bool found_role_name = false; + + for (size_t k = 0; k < config->roles.len; k++) { + if (strcmp(group->role_names.d[j], config->roles.d[k]->name) == 0) { + int ret = role_ref_array_push(&group->roles, config->roles.d[k]); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed allocation in assign_group_roles"); + + found_role_name = true; + break; + } + } + + if (!found_role_name) { + (void) sd_journal_print(LOG_WARNING, "Failed to find group role %s for group %s", group->role_names.d[j], group->name); + } + } + + return 0; +} diff --git a/vrt/vrtd/src/config.h b/vrt/vrtd/src/config.h new file mode 100644 index 00000000..861c5af1 --- /dev/null +++ b/vrt/vrtd/src/config.h @@ -0,0 +1,136 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_CONFIG_H +#define VRTD_CONFIG_H + +#include +#include + +#include "array.h" + +struct bar_policy { + bool any; +}; + +struct role { + char *name; /* owning */ + struct uint_array allowed_devices; + + struct bar_policy bar_policy; + + bool query; + bool allow_any_device; + bool pcie_hotplug; +}; + +void cleanup_role(struct role *role); +static inline +void cleanup_rolep(struct role **rolep) +{ + if (rolep == NULL) { + return; + } + + cleanup_role(*rolep); + + *rolep = NULL; +} + +DECLARE_ARRAY(role_ref_array, struct role *) +DECLARE_OWNING_PTR_ARRAY(role_ptr_array, struct role *, cleanup_role) + +struct user_config { + char *name; /* owning */ + uid_t uid; + + struct str_array role_names; /* Used for lazy loading roles */ + struct role_ref_array roles; +}; + +void cleanup_user_config(struct user_config *user); +static inline +void cleanup_user_configp(struct user_config **userp) +{ + if (userp == NULL) { + return; + } + + cleanup_user_config(*userp); + + *userp = NULL; +} + +DECLARE_OWNING_PTR_ARRAY(user_config_ptr_array, struct user_config *, cleanup_user_config) + +struct group_config { + char *name; /* owning */ + gid_t gid; + + struct str_array role_names; /* Used for lazy loading roles */ + struct role_ref_array roles; +}; + +void cleanup_group_config(struct group_config *group); +static inline +void cleanup_group_configp(struct group_config **groupp) +{ + if (groupp == NULL) { + return; + } + + cleanup_group_config(*groupp); + + *groupp = NULL; +} + +DECLARE_OWNING_PTR_ARRAY(group_config_ptr_array, struct group_config *, cleanup_group_config) + +struct config { + struct role_ptr_array roles; + + struct user_config *default_user; + + struct user_config_ptr_array users; + struct group_config_ptr_array groups; + + bool mock_device; +}; + +void cleanup_config(struct config *config); +static inline +void cleanup_configp(struct config **configp) +{ + if (configp == NULL) { + return; + } + + cleanup_config(*configp); + + *configp = NULL; +} + +int config_load(struct config **config); + +int role_merge_new(struct role **rolep, const char *name); +int role_merge_add_role(struct role *dst, const struct role *src); +int role_merge_add_array(struct role *dst, const struct role_ref_array *roles); + +#endif // VRTD_CONFIG_H diff --git a/vrt/vrtd/src/device.c b/vrt/vrtd/src/device.c new file mode 100644 index 00000000..67c8d43e --- /dev/null +++ b/vrt/vrtd/src/device.c @@ -0,0 +1,210 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#define _GNU_SOURCE + +#include "device.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int devices_open(struct device_ptr_array *devices, size_t pathc, char ** paths); +static int device_open(struct device *d, const char *path); +void cleanup_device(struct device *d); + +int devices_discover_and_open(struct device_ptr_array *devices) +{ + _cleanup_(globfree) + glob_t g = {0}; + + int ret = glob("/dev/slash_ctl*", GLOB_ERR, NULL, &g); + if (ret != 0) { + (void) sd_journal_print( + LOG_ERR, + "Error matching pattern /dev/slash_ctl*: %s", + glob_err_to_string(ret) + ); + + return -1; + } + + return devices_open(devices, g.gl_pathc, g.gl_pathv); +} + +static int devices_open(struct device_ptr_array *devices, size_t pathc, char ** paths) +{ + for (size_t i = 0; i < pathc; ++i) { + const char *path = paths[i]; + + _cleanup_(cleanup_devicep) + struct device *d = calloc(1, sizeof *d); + PROPAGATE_ERROR_NULL_STDC_LOG(d, LOG_ERR, "Failed to allocate memory for device data"); + + int ret = device_open(d, path); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to open device %s", path); + + ret = device_ptr_array_push_move(devices, &d); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to allocate memory for device data"); + } + + return 0; +} + +static int device_open(struct device *d, const char *path) +{ + d->path = strdup(path); + PROPAGATE_ERROR_NULL_STDC_LOG(d->path, LOG_ERR, "Failed to allocate memory for device data"); + + d->ctl = slash_ctldev_open(path); + if (d->ctl == NULL) { + (void) sd_journal_print( + LOG_ERR, + "Error opening device %s: %m", + path + ); + free(d->path); + return -1; + } + + assert(d->ctl != NULL); + + /* Best-effort QDMA ctl path: + * Map /dev/slash_ctlN -> /dev/slash_qdma_ctlN by string replacement. + * This assumes matching indices and a single device. + * + * TODO: replace this with a robust mapping via sysfs/PCI BDF when + * multiple devices or different naming schemes are supported. + */ + { + const char *prefix = "/dev/slash_ctl"; + _cleanup_(cleanup_free) + char *qdma_path = NULL; + + if (strncmp(path, prefix, strlen(prefix)) == 0) { + const char *suffix = path + strlen(prefix); + int n = asprintf(&qdma_path, "/dev/slash_qdma_ctl%s", suffix); + if (n < 0) { + qdma_path = NULL; + } + } + + if (qdma_path != NULL) { + d->qdma = slash_qdma_open(qdma_path); + if (d->qdma == NULL) { + (void) sd_journal_print( + LOG_WARNING, + "Error opening QDMA device %s (for %s): %m", + qdma_path, d->path + ); + } + } + } + + for (size_t i = 0; i < SIZEOF_ARRAY(d->bar_info); i++) { + d->bar_info[i] = slash_bar_info_read(d->ctl, i); + if (d->bar_info[i] == NULL) { + (void) sd_journal_print( + LOG_ERR, + "Error opening bar_info %zu on device %s: %m", + i, d->path + ); + continue; + } + + assert(d->bar_info[i] != NULL); + + if (d->bar_info[i]->usable) { + d->bar_files[i] = slash_bar_file_open(d->ctl, i, O_CLOEXEC); + if (d->bar_files[i] == NULL) { + (void) sd_journal_print( + LOG_ERR, + "Error opening bar_file %zu on device %s: %m", + i, d->path + ); + } + } + } + + return 0; +} + +void cleanup_device(struct device *d) +{ + if (d == NULL) { + return; + } + + if (d->qdma != NULL) { + if (slash_qdma_close(d->qdma) != 0) { + (void) sd_journal_print( + LOG_WARNING, + "Error closing qdma device for %s: %m (ignored)", + d->path ? d->path : "(unknown)" + ); + } + d->qdma = NULL; + } + + /* Close any opened BAR files */ + for (size_t i = 0; i < SIZEOF_ARRAY(d->bar_files); i++) { + if (d->bar_files[i] != NULL) { + if (slash_bar_file_close(d->bar_files[i]) != 0) { + (void) sd_journal_print( + LOG_WARNING, + "Error closing bar_file %zu for %s: %m (ignored)", + i, d->path ? d->path : "(unknown)" + ); + } + d->bar_files[i] = NULL; + } + } + + /* Free bar info data */ + for (size_t i = 0; i < SIZEOF_ARRAY(d->bar_info); i++) { + if (d->bar_info[i] != NULL) { + slash_bar_info_free(d->bar_info[i]); + d->bar_info[i] = NULL; + } + } + + /* Close control device last */ + if (d->ctl != NULL) { + if (slash_ctldev_close(d->ctl) != 0) { + (void) sd_journal_print( + LOG_WARNING, + "Error closing ctldevice %s: %m (ignored)", + d->path ? d->path : "(unknown)" + ); + } + d->ctl = NULL; + } + + free(d->path); + d->path = NULL; + + free(d); +} diff --git a/vrt/vrtd/src/device.h b/vrt/vrtd/src/device.h new file mode 100644 index 00000000..7195b3cf --- /dev/null +++ b/vrt/vrtd/src/device.h @@ -0,0 +1,52 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_CTLDEV_H +#define VRTD_CTLDEV_H + +#include + +#include +#include + +#include "array.h" + +struct device { + char *path; /* owning */ + struct slash_ctldev *ctl; + struct slash_qdma *qdma; + struct slash_ioctl_bar_info *bar_info[6]; + struct slash_bar_file *bar_files[6]; +}; + +void cleanup_device(struct device *d); +static inline +void cleanup_devicep(struct device **d) +{ + cleanup_device(*d); + + *d = NULL; +} + +DECLARE_OWNING_PTR_ARRAY(device_ptr_array, struct device *, cleanup_device); + +int devices_discover_and_open(struct device_ptr_array *devices); + +#endif // VRTD_CTLDEV_H diff --git a/vrt/vrtd/src/main.c b/vrt/vrtd/src/main.c new file mode 100644 index 00000000..00440113 --- /dev/null +++ b/vrt/vrtd/src/main.c @@ -0,0 +1,263 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#define _GNU_SOURCE + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "config.h" +#include "array.h" +#include "utils.h" +#include "state.h" +#include "accept.h" +#include "device.h" +#include "signals.h" + +static void check_journal_and_abort_if_needed(void); +static int configure_watchdog(sd_event *ev); +static int configure_signals(sd_event *ev, struct vrtd *state); +static int configure_sockets(sd_event *ev, struct vrtd *state); +static int block_signals(const int *signals, size_t n); + +int main(void) +{ + struct vrtd state = {0}; + + check_journal_and_abort_if_needed(); + + int ret = config_load(&state.config); + if (ret == -1) { + (void) sd_journal_print(LOG_CRIT, "Failed to load config"); + exit(EXIT_FAILURE); + } + + ret = devices_discover_and_open(&state.devices); + if (ret == -1) { + (void) sd_journal_print(LOG_CRIT, "Failed to load devices"); + exit(EXIT_FAILURE); + } + + _cleanup_(sd_event_unrefp) + sd_event *ev = NULL; + ret = sd_event_default(&ev); + if (ret < 0) { + (void) sd_journal_print(LOG_CRIT, "Failed to allocate event loop: %s", strerrordesc_np(-ret)); + exit(EXIT_FAILURE); + } + + ret = configure_watchdog(ev); + if (ret == -1) { + (void) sd_journal_print(LOG_CRIT, "Failed to configure watchdog"); + exit(EXIT_FAILURE); + } + + ret = configure_signals(ev, &state); + if (ret == -1) { + (void) sd_journal_print(LOG_CRIT, "Failed to configure signals"); + exit(EXIT_FAILURE); + } + + ret = configure_sockets(ev, &state); + if (ret == -1) { + (void) sd_journal_print(LOG_CRIT, "Failed to configure sockets"); + exit(EXIT_FAILURE); + } + + ret = sd_notify(0, "READY=1"); + if (ret < 0) { + (void) sd_journal_print(LOG_CRIT, "Failed to notify ready: %s", strerrordesc_np(-ret)); + exit(EXIT_FAILURE); + } else if (ret == 0) { + (void) sd_journal_print(LOG_INFO, "No notification socket"); + } + + ret = sd_event_loop(ev); + if (ret < 0) { + (void) sd_journal_print(LOG_CRIT, "Critical error: %s", strerrordesc_np(-ret)); + exit(EXIT_FAILURE); + } + + (void) sd_notify(0, "STOPPING=1"); + + return ret; +} + + +/** + * In vrtd we do all our logging through the systemd-journal. + * This is very convenient as it allows inspecting with journalctl -u + * in the usual way, saves us from having to manage our own files in + * /var/log (with rotation, compression etc.) and is nice QoL all around. + * + * The problem is that logging can fail, which raises the question about + * how we are to handle that failure. + * + * It is important to note that if the systemd-journal is not active, + * the logging functions will succeed, and silently do nothing. This is + * a systemd design choice. For now, we simply accept this behaviour. + * + * The logging functions can fail if: + * + * 1) We call them with invalid parameters (EINVAL). + * 2) We send a message that's too big. + * 3) We run out of memory (ENOMEM). + * 4) Some other process limit is reached. + * 5) An I/O error occurs. + * 6) The internal sendmsg syscall is interrupted by a signal (EINTR). + * + * Aborting the program if logging fails is not a good idea. We are left + * with two choices: + * + * a) generally ignore logging errors + * b) generally check logging errors + * + * Our current approach is to generally ignore logging errors, checking + * only once (in the function below) at the very beginning of the program, + * mostly to catch errors of type (5), and failing if we cannot log anything + * at all. Because this happens before we notify READY=1, the service will + * never appear started and systemctl start will fail, making it obvious to + * the sysadmin that something is wrong. + * + * If we decide to check (which would massively increase complexity and may + * slightly affect performance), we should assert against (1); assert against (2) + * when there is no user-provided parameters (and fall back to a message without them + * if there are); ignore (3); fall back to some other (stderr?) logging if (4) or (5) + * and quietly retry (6). + * + * The reason to ignore (3) is because logging code is not a structurally sane + * place to recover from ENOMEM. If we're limited, we'll hit ENOMEM again later + * and we can do a better job at recovering then. + */ +static void check_journal_and_abort_if_needed() +{ + int ret = sd_journal_print(LOG_INFO, "Starting vrtd..."); + if (ret < 0) { + (void) fprintf(stderr, "Failed to access systemd journal\n"); + exit(EXIT_FAILURE); + } +} + +static int configure_signals(sd_event *ev, struct vrtd *state) +{ + struct sigaction sa_ignore = { .sa_handler = SIG_IGN }; + int ret = sigemptyset(&sa_ignore.sa_mask); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Error manipulating signal set"); + + ret = sigaction(SIGPIPE, &sa_ignore, NULL); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Failed to ignore SIGPIPE"); + + int signals[] = {SIGINT, SIGTERM, SIGQUIT, SIGHUP}; + + ret = block_signals(signals, SIZEOF_ARRAY(signals)); + PROPAGATE_ERROR(ret); + + for (size_t i = 0; i < SIZEOF_ARRAY(signals); i++) { + ret = sd_event_add_signal(ev, NULL, signals[i], on_event_signal, state); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to add event source: %s", sigabbrev_np(signals[i])); + } + + return 0; +} + +static int block_signals(const int *signals, size_t n) +{ + sigset_t set; + sigemptyset(&set); + for (size_t i = 0; i < n; i++) { + sigaddset(&set, signals[i]); + } + + int ret = sigprocmask(SIG_BLOCK, &set, NULL); + PROPAGATE_ERROR_STDC_LOG(ret,LOG_CRIT, "Failed to mask signals"); + + return 0; +} + +static int configure_sockets(sd_event *ev, struct vrtd *state) +{ + _cleanup_(cleanup_argv) + char **names = NULL; + + int ret = sd_listen_fds_with_names(1, &names); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Could not list listen fds"); + if (ret == 0) { + (void) sd_journal_print(LOG_ERR, "No socket provided"); + return -1; + } + + for (int i = 0; i < ret; i++) { + int fd = SD_LISTEN_FDS_START + i; + + ret = sd_is_socket(fd, AF_UNIX, SOCK_SEQPACKET, 1); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to get state of socket %s", names[i]); + if (ret == 0) { + (void) sd_journal_print(LOG_ERR, "Bad socket type %s", names[i]); + return -1; + } + + _cleanup_(sd_event_source_unrefp) + sd_event_source *source = NULL; + ret = sd_event_add_io(ev, &source, fd, EPOLLIN, on_event_new_connection, state); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set up listening for socket %s", names[i]); + + _cleanup_(cleanup_free) + char *description = NULL; + + ret = asprintf(&description, "Unix socket %s", names[i]); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Could not allocate description for socket %s", names[i]); + + ret = sd_event_source_set_description(source, description); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Could not set description for socket %s", names[i]); + + ret = sd_event_source_set_io_fd_own(source, 1); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set up fd ownership for socket %s", names[i]); + + ret = sd_event_source_set_floating(source, 1); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set up floating source for socket %s", names[i]); + + ret = sd_event_source_set_exit_on_failure(source, 1); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set up exit on failure for socket %s", names[i]); + + (void) sd_journal_print(LOG_INFO, "Listening on unix socket %s", names[i]); + } + + return 0; +} + +static int configure_watchdog(sd_event *ev) +{ + int ret = sd_event_set_watchdog(ev, 1); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to enable watchdog"); + + return 0; +} diff --git a/vrt/vrtd/src/serve.c b/vrt/vrtd/src/serve.c new file mode 100644 index 00000000..b8c167b8 --- /dev/null +++ b/vrt/vrtd/src/serve.c @@ -0,0 +1,742 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#define _GNU_SOURCE + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "array.h" +#include "auth.h" +#include "serve.h" +#include "utils.h" +#include "state.h" +#include "vrtd/wire.h" + +static int client_update_wanted_epoll_events(struct client *client, sd_event_source *s); +static int client_handle_in(struct client *client); +static int client_handle_out(struct client *client); +static int client_handle_request(struct client *client); +static uint16_t client_handle_request_get_device_info( + struct client *client, + const struct vrtd_req_get_device_info *req_body, + uint16_t req_size, + struct vrtd_resp_get_device_info *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_get_num_devices( + struct client *client, + const struct vrtd_req_get_num_devices *req_body, + uint16_t req_size, + struct vrtd_resp_get_num_devices *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_get_bar_info( + struct client *client, + const struct vrtd_req_get_bar_info *req_body, + uint16_t req_size, + struct vrtd_resp_get_bar_info *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_get_bar_fd( + struct client *client, + const struct vrtd_req_get_bar_fd *req_body, + uint16_t req_size, + struct vrtd_resp_get_bar_fd *resp_body, + uint16_t *resp_size, + int *out_fd, + bool *have_out_fd +); +static uint16_t client_handle_request_qdma_get_info( + struct client *client, + const struct vrtd_req_qdma_get_info *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_get_info *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_qdma_qpair_add( + struct client *client, + const struct vrtd_req_qdma_qpair_add *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_qpair_add *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_qdma_qpair_op( + struct client *client, + const struct vrtd_req_qdma_qpair_op *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_qpair_op *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_qdma_qpair_get_fd( + struct client *client, + const struct vrtd_req_qdma_qpair_get_fd *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_qpair_get_fd *resp_body, + uint16_t *resp_size, + int *out_fd, + bool *have_out_fd +); + +void cleanup_client(struct client *client) +{ + if (client == NULL) { + return; + } + + gid_t_array_free(&client->gids); + + if (client->fd >= 0) { + (void) close(client->fd); + client->fd = -1; + } + + (void) sd_event_source_disable_unrefp(&client->event_source); + + free(client); +} + +int on_client_io(sd_event_source *s, int fd, uint32_t revents, void *user) +{ + struct client *client = user; + (void) s; + + assert(client->fd == fd); + + int ret; + + if (revents & (EPOLLERR | EPOLLHUP | EPOLLRDHUP)) { + client_ptr_array_rm_by_value(&client->state->clients, client); + return 0; + } + + if (!client->have_request && (revents & EPOLLIN)) { + ret = client_handle_in(client); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to handle client input"); + } + + if (client->have_request && !client->have_response) { + ret = client_handle_request(client); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to handle client request"); + } + + if ((client->have_response && (revents & EPOLLOUT)) || + client->have_new_response) { + client->have_new_response = false; + + ret = client_handle_out(client); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to handle client output"); + } + + ret = client_update_wanted_epoll_events(client, s); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to update epoll events"); + + + + return 0; +} + +static int client_update_wanted_epoll_events(struct client *client, sd_event_source *s) +{ + uint32_t events = + EPOLLRDHUP | + (!client->have_request ? EPOLLIN : 0) | + (client->have_response ? EPOLLOUT : 0) + ; + + if (events == client->wanted_epoll_events) { + return 0; + } + client->wanted_epoll_events = events; + + int ret = sd_event_source_set_io_events(s, events); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set io source io events"); + + return 0; +} + +static int client_handle_in(struct client *client) +{ + assert(!client->have_request); + + struct iovec iovec[1] = { + { .iov_base = client->inb, .iov_len = VRTD_MSG_MAX_SIZE }, + }; + + struct msghdr msg = { + .msg_name = NULL, + .msg_namelen = 0, + .msg_iov = iovec, + .msg_iovlen = SIZEOF_ARRAY(iovec), + .msg_control = NULL, + .msg_controllen = 0, + .msg_flags = 0, + }; + + ssize_t n; +retry: + n = recvmsg(client->fd, &msg, MSG_DONTWAIT); + if (n == -1) { + switch (errno) { + case EINTR: + goto retry; + case EAGAIN: +#if EAGAIN != EWOULDBLOCK + case EWOULDBLOCK: +#endif + return 0; + default: + return -1; + } + } + + if (msg.msg_flags & (MSG_TRUNC | MSG_CTRUNC)) { + // TODO: handle error from client + return -1; + } + + struct vrtd_req_header *header = (struct vrtd_req_header *) client->inb; + if (n < sizeof(struct vrtd_req_header) || header->size + sizeof(struct vrtd_req_header) != n || header->size > VRTD_MSG_MAX_SIZE - sizeof *header) { + // TODO: handle error from client + return -1; + } + + client->have_request = true; + + return 0; +} + +static int client_handle_out(struct client *client) +{ + assert(client->have_response); + + size_t size = sizeof(struct vrtd_resp_header) + ((struct vrtd_resp_header *) client->outb)->size; + + struct iovec iovec[1] = { + { .iov_base = client->outb, .iov_len = size }, + }; + + struct msghdr msg = { + .msg_name = NULL, + .msg_namelen = 0, + .msg_iov = iovec, + .msg_iovlen = SIZEOF_ARRAY(iovec), + .msg_control = NULL, + .msg_controllen = 0, + .msg_flags = 0, + }; + + char cbuf[CMSG_SPACE(sizeof(int))]; + + if (client->have_out_fd) { + memset(cbuf, 0, sizeof cbuf); + + msg.msg_control = cbuf; + msg.msg_controllen = sizeof cbuf; + + struct cmsghdr *cmsg = CMSG_FIRSTHDR(&msg); + cmsg->cmsg_level = SOL_SOCKET; + cmsg->cmsg_type = SCM_RIGHTS; + cmsg->cmsg_len = CMSG_LEN(sizeof(int)); + + memcpy(CMSG_DATA(cmsg), &client->out_fd, sizeof(int)); + } + + ssize_t n; +retry: + n = sendmsg(client->fd, &msg, MSG_DONTWAIT | MSG_NOSIGNAL); + if (n == -1) { + switch (errno) { + case EINTR: + goto retry; + case EAGAIN: +#if EAGAIN != EWOULDBLOCK + case EWOULDBLOCK: +#endif + return 0; + default: + return -1; + } + } + + if (n != size) { + (void) sd_journal_print(LOG_ERR, "Message truncated"); + return -1; + } + + client->have_response = false; + client->have_out_fd = false; + + return 0; +} + +static int client_handle_request(struct client *client) +{ + assert(client->have_request); + assert(!client->have_response); + + struct vrtd_req_header *req_header = CLIENT_IN_HEADER(*client); + struct vrtd_resp_header *resp_header = CLIENT_OUT_HEADER(*client); + + resp_header->seqno = req_header->seqno; + + // Separate variable for allignment reasons + uint16_t size; + + switch (req_header->opcode) { + case VRTD_REQ_GET_NUM_DEVICES: + resp_header->ret = + client_handle_request_get_num_devices( + client, + CLIENT_IN_BODY(*client, vrtd_req_get_num_devices), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_get_num_devices), + &size + ); + break; + case VRTD_REQ_GET_DEVICE_INFO: + resp_header->ret = + client_handle_request_get_device_info( + client, + CLIENT_IN_BODY(*client, vrtd_req_get_device_info), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_get_device_info), + &size + ); + break; + case VRTD_REQ_GET_BAR_INFO: + resp_header->ret = + client_handle_request_get_bar_info( + client, + CLIENT_IN_BODY(*client, vrtd_req_get_bar_info), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_get_bar_info), + &size + ); + break; + case VRTD_REQ_GET_BAR_FD: + resp_header->ret = + client_handle_request_get_bar_fd( + client, + CLIENT_IN_BODY(*client, vrtd_req_get_bar_fd), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_get_bar_fd), + &size, + &client->out_fd, + &client->have_out_fd + ); + break; + case VRTD_REQ_QDMA_GET_INFO: + resp_header->ret = + client_handle_request_qdma_get_info( + client, + CLIENT_IN_BODY(*client, vrtd_req_qdma_get_info), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_qdma_get_info), + &size + ); + break; + case VRTD_REQ_QDMA_QPAIR_ADD: + resp_header->ret = + client_handle_request_qdma_qpair_add( + client, + CLIENT_IN_BODY(*client, vrtd_req_qdma_qpair_add), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_qdma_qpair_add), + &size + ); + break; + case VRTD_REQ_QDMA_QPAIR_OP: + resp_header->ret = + client_handle_request_qdma_qpair_op( + client, + CLIENT_IN_BODY(*client, vrtd_req_qdma_qpair_op), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_qdma_qpair_op), + &size + ); + break; + case VRTD_REQ_QDMA_QPAIR_GET_FD: + resp_header->ret = + client_handle_request_qdma_qpair_get_fd( + client, + CLIENT_IN_BODY(*client, vrtd_req_qdma_qpair_get_fd), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_qdma_qpair_get_fd), + &size, + &client->out_fd, + &client->have_out_fd + ); + break; + + default: + resp_header->ret = VRTD_RET_BAD_REQUEST; + resp_header->size = 0; + + break; + } + + resp_header->size = size; + + client->have_request = false; + client->have_response = true; + client->have_new_response = true; + + return 0; +} + +static uint16_t client_handle_request_get_num_devices( + struct client *client, + const struct vrtd_req_get_num_devices *req_body, + uint16_t req_size, + struct vrtd_resp_get_num_devices *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_get_num_devices(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + return VRTD_RET_BAD_REQUEST; + } + + resp_body->num_devices = client->state->devices.len; + + *resp_size = sizeof(*resp_body); + return VRTD_RET_OK; +} + +static uint16_t client_handle_request_qdma_get_info( + struct client *client, + const struct vrtd_req_qdma_get_info *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_get_info *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_qdma_get_info(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL || d->qdma == NULL) { + return VRTD_RET_NOEXIST; + } + + if (slash_qdma_info_read(d->qdma, &resp_body->info) != 0) { + return VRTD_RET_INTERNAL_ERROR; + } + + *resp_size = sizeof(*resp_body); + return VRTD_RET_OK; +} + +static uint16_t client_handle_request_qdma_qpair_add( + struct client *client, + const struct vrtd_req_qdma_qpair_add *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_qpair_add *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_qdma_qpair_add(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL || d->qdma == NULL) { + return VRTD_RET_NOEXIST; + } + + resp_body->add = req_body->add; + + if (slash_qdma_qpair_add(d->qdma, &resp_body->add) != 0) { + return VRTD_RET_INTERNAL_ERROR; + } + + *resp_size = sizeof(*resp_body); + return VRTD_RET_OK; +} + +static uint16_t client_handle_request_qdma_qpair_op( + struct client *client, + const struct vrtd_req_qdma_qpair_op *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_qpair_op *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_qdma_qpair_op(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL || d->qdma == NULL) { + return VRTD_RET_NOEXIST; + } + + switch (req_body->op) { + case SLASH_QDMA_QUEUE_OP_START: + ret = slash_qdma_qpair_start(d->qdma, req_body->qid); + break; + case SLASH_QDMA_QUEUE_OP_STOP: + ret = slash_qdma_qpair_stop(d->qdma, req_body->qid); + break; + case SLASH_QDMA_QUEUE_OP_DEL: + ret = slash_qdma_qpair_del(d->qdma, req_body->qid); + break; + default: + return VRTD_RET_INVALID_ARGUMENT; + } + + if (ret != 0) { + return VRTD_RET_INTERNAL_ERROR; + } + + resp_body->zero = 0; + *resp_size = sizeof(*resp_body); + return VRTD_RET_OK; +} + +static uint16_t client_handle_request_qdma_qpair_get_fd( + struct client *client, + const struct vrtd_req_qdma_qpair_get_fd *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_qpair_get_fd *resp_body, + uint16_t *resp_size, + int *out_fd, + bool *have_out_fd +) +{ + int ret = auth_request_qdma_qpair_get_fd(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + *have_out_fd = false; + + if (req_size < sizeof(*req_body)) { + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL || d->qdma == NULL) { + return VRTD_RET_NOEXIST; + } + + int fd = slash_qdma_qpair_get_fd(d->qdma, req_body->qid, (int)req_body->flags); + if (fd < 0) { + return VRTD_RET_INTERNAL_ERROR; + } + + *out_fd = fd; + *have_out_fd = true; + + resp_body->zero = 0; + *resp_size = sizeof(*resp_body); + return VRTD_RET_OK; +} + +static uint16_t client_handle_request_get_device_info( + struct client *client, + const struct vrtd_req_get_device_info *req_body, + uint16_t req_size, + struct vrtd_resp_get_device_info *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_get_device_info(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + return VRTD_RET_NOEXIST; + } + + _cleanup_(cleanup_free) + char *path = strdup(client->state->devices.d[req_body->dev_number]->path); + if (unlikely(path == NULL)) { + return VRTD_RET_INTERNAL_ERROR; + } + + snprintf(resp_body->name, sizeof resp_body->name, "%s", basename(path)); + + *resp_size = sizeof(*resp_body); + return VRTD_RET_OK; +} + +static uint16_t client_handle_request_get_bar_info( + struct client *client, + const struct vrtd_req_get_bar_info *req_body, + uint16_t req_size, + struct vrtd_resp_get_bar_info *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_get_bar_info(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + return VRTD_RET_NOEXIST; + } + + if (req_body->bar_number >= 6) { + return VRTD_RET_BAD_REQUEST; + } + + // TODO: Free this + struct slash_ioctl_bar_info *bar_info = client->state->devices.d[req_body->dev_number]->bar_info[req_body->bar_number]; + if (bar_info == NULL) { + return VRTD_RET_NOEXIST; + } + + resp_body->bar_info = *bar_info; + + *resp_size = sizeof(*resp_body); + return VRTD_RET_OK; +} + +static uint16_t client_handle_request_get_bar_fd( + struct client *client, + const struct vrtd_req_get_bar_fd *req_body, + uint16_t req_size, + struct vrtd_resp_get_bar_fd *resp_body, + uint16_t *resp_size, + int *out_fd, + bool *have_out_fd +) +{ + int ret = auth_request_get_bar_fd(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + *have_out_fd = false; + + if (req_size < sizeof(*req_body)) { + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + return VRTD_RET_NOEXIST; + } + + if (req_body->bar_number >= 6) { + return VRTD_RET_BAD_REQUEST; + } + + struct slash_bar_file *bar_file = client->state->devices.d[req_body->dev_number]->bar_files[req_body->bar_number]; + if (bar_file == NULL) { + return VRTD_RET_NOEXIST; + } + + resp_body->len = bar_file->len; + *out_fd = bar_file->fd; + *have_out_fd = true; + + *resp_size = sizeof(*resp_body); + return VRTD_RET_OK; +} diff --git a/vrt/vrtd/src/serve.h b/vrt/vrtd/src/serve.h new file mode 100644 index 00000000..3eab99bd --- /dev/null +++ b/vrt/vrtd/src/serve.h @@ -0,0 +1,79 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_SERVE_H +#define VRTD_SERVE_H + +#include +#include + +#include +#include + +#include "array.h" + +struct client { + uint8_t inb[VRTD_MSG_MAX_SIZE]; + uint8_t outb[VRTD_MSG_MAX_SIZE]; + + int fd; + + int out_fd; + bool have_out_fd; + + bool have_request; + bool have_response; + bool have_new_response; + + uint32_t wanted_epoll_events; + + uid_t uid; + struct gid_t_array gids; + + struct vrtd *state; + struct role *role; + + sd_event_source *event_source; +}; + +#define CLIENT_IN_HEADER(C) ((struct vrtd_req_header *) (C).inb) +#define CLIENT_OUT_HEADER(C) ((struct vrtd_resp_header *) (C).outb) + +#define CLIENT_IN_BODY(C, T) ((struct T *) ((C).inb + sizeof(struct vrtd_req_header))) +#define CLIENT_OUT_BODY(C, T) ((struct T *) ((C).outb + sizeof(struct vrtd_resp_header))) + +void cleanup_client(struct client *client); +static inline +void cleanup_clientp(struct client **clientp) +{ + if (clientp == NULL) { + return; + } + + cleanup_client(*clientp); + + *clientp = NULL; +} + +DECLARE_OWNING_PTR_ARRAY(client_ptr_array, struct client *, cleanup_client) + +int on_client_io(sd_event_source *s, int fd, uint32_t revents, void *user); + +#endif // VRTD_SERVE_H diff --git a/vrt/vrtd/src/signals.c b/vrt/vrtd/src/signals.c new file mode 100644 index 00000000..2c1bb49d --- /dev/null +++ b/vrt/vrtd/src/signals.c @@ -0,0 +1,85 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#define _GNU_SOURCE + +#include "signals.h" + +#include +#include +#include +#include + +#include "state.h" +#include "config.h" +#include "utils.h" + +int reload_config(struct vrtd *state); + +int on_event_signal(sd_event_source *s, const struct signalfd_siginfo *si, void *userdata) +{ + int sig = si->ssi_signo; + + struct vrtd *state = userdata; + assert(state != NULL); + + // Log or act based on the signal + switch (sig) { + case SIGINT: + case SIGTERM: { + // Stop the event loop gracefully + sd_event *event = sd_event_source_get_event(s); + if (event) { + sd_event_exit(event, 0); + } + break; + } + + case SIGHUP: { + reload_config(state); + break; + } + + default: { + (void) sd_journal_print(LOG_WARNING, "Unhandled signal: %s (%d)\n", sigabbrev_np(sig), sig); + + break; + } + } + + return 0; +} + +int reload_config(struct vrtd *state) +{ + for (size_t i = 0; i < state->clients.len; i++) { + struct client *client = state->clients.d[i]; + assert(client != NULL); + + cleanup_rolep(&client->role); + } + + cleanup_configp(&state->config); + + int ret = config_load(&state->config); + PROPAGATE_ERROR(ret); + + return 0; +} diff --git a/vrt/vrtd/src/signals.h b/vrt/vrtd/src/signals.h new file mode 100644 index 00000000..b4aceaba --- /dev/null +++ b/vrt/vrtd/src/signals.h @@ -0,0 +1,28 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_SIGNALS_H +#define VRTD_SIGNALS_H + +#include + +int on_event_signal(sd_event_source *s, const struct signalfd_siginfo *si, void *userdata); + +#endif // VRTD_SIGNALS_H diff --git a/vrt/vrtd/src/state.h b/vrt/vrtd/src/state.h new file mode 100644 index 00000000..1228ff71 --- /dev/null +++ b/vrt/vrtd/src/state.h @@ -0,0 +1,36 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_STATE_H +#define VRTD_STATE_H + +#include "device.h" +#include "config.h" +#include "serve.h" + +struct vrtd { + struct config *config; + + struct client_ptr_array clients; + + struct device_ptr_array devices; +}; + +#endif // VRTD_STATE_H diff --git a/vrt/vrtd/src/utils.h b/vrt/vrtd/src/utils.h new file mode 100644 index 00000000..9e595ffd --- /dev/null +++ b/vrt/vrtd/src/utils.h @@ -0,0 +1,228 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_UTILS_H +#define VRTD_UTILS_H + +#include +#include +#include +#include +#include + +#include +#include + +#if defined(__has_include) +# if __has_include() +# include +# define HAVE_STDBIT 1 +# endif +#endif + +#define NODISCARD __attribute__((warn_unused_result)) + +/* ---- type-specific helpers ---- */ +#if HAVE_STDBIT +static inline uint32_t bit_ceil_u32(uint32_t n) { + return stdc_bit_ceil((unsigned int)(x)); +} +static inline uint64_t bit_ceil_u64(uint64_t n) { + return stdc_bit_ceil((unsigned long long)(x)); +} +#else +static inline uint32_t bit_ceil_u32(uint32_t n) { + if (n == 0) return 1u; + if (n > 0x80000000u) return 0u; // not representable + return 1u << (32 - __builtin_clz(n - 1)); // GCC/Clang +} +static inline uint64_t bit_ceil_u64(uint64_t n) { + if (n == 0) return 1ull; + if (n > 0x8000000000000000ull) return 0ull; // not representable + return 1ull << (64 - __builtin_clzll(n - 1)); +} +#endif + +/* ---- generic front-end ---- */ +#define bit_ceil(n) _Generic((n), \ + uint32_t: bit_ceil_u32, \ + uint64_t: bit_ceil_u64 \ +)(n) + +#define max(a,b) \ + ({ __auto_type _a = (a); \ + __auto_type _b = (b); \ + _a > _b ? _a : _b; }) + +#define min(a,b) \ + ({ __auto_type _a = (a); \ + __auto_type _b = (b); \ + _a > _b ? _a : _b; }) + +#define SIZEOF_ARRAY(X) (sizeof(X) / sizeof(X[0])) + +#define NOP() ((void) 0) + +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202311L + #define NODISCARD [[nodiscard]] +#elif defined(__GNUC__) || defined(__clang__) + #define NODISCARD __attribute__((warn_unused_result)) +#else + #define NODISCARD +#endif + +#ifndef unlikey +#define unlikely(x) __builtin_expect(!!(x), 0) +#endif + +#ifndef likely +#define likely(x) __builtin_expect(!!(x), 1) +#endif + +// #define ASSERT_TYPE(var, type) \ +// static_assert( \ +// __builtin_types_compatible_p(__typeof__(var), type), \ +// "Type assertion failed: variable is not of type " #type \ +// ) + +#define _PROPAGATE_ERROR_INTERNAL_NOLOG(RET, CMP, JUMP) \ + ({ \ + __auto_type _ret = RET; \ + if (CMP) { \ + JUMP; \ + } \ + }) + +#define _PROPAGATE_ERROR_INTERNAL_LOG(RET, CMP, JUMP, LOGLEVEL, FMT, ...) \ + ({ \ + __auto_type _ret = RET; \ + if (CMP) { \ + sd_journal_print(LOGLEVEL, FMT, ##__VA_ARGS__); \ + JUMP; \ + } \ + }) + +#define PROPAGATE_ERROR(RET) \ + _PROPAGATE_ERROR_INTERNAL_NOLOG(RET, (_ret == -1), return -1) +#define PROPAGATE_ERROR_NULL(RET) \ + _PROPAGATE_ERROR_INTERNAL_NOLOG(RET, (_ret == NULL), return -1) +#define PROPAGATE_ERROR_SD(RET) \ + _PROPAGATE_ERROR_INTERNAL_NOLOG(RET, (_ret < 0), return -1) + +#define PROPAGATE_ERROR_LOG(RET, LOGLEVEL, FMT, ...) \ + _PROPAGATE_ERROR_INTERNAL_LOG(RET, (_ret == -1), return -1, LOGLEVEL, FMT, ##__VA_ARGS__) +#define PROPAGATE_ERROR_NULL_LOG(RET, LOGLEVEL, FMT, ...) \ + _PROPAGATE_ERROR_INTERNAL_LOG(RET, (_ret == NULL), return -1, LOGLEVEL, FMT, ##__VA_ARGS__) +#define PROPAGATE_ERROR_STDC_LOG(RET, LOGLEVEL, FMT, ...) \ + _PROPAGATE_ERROR_INTERNAL_LOG(RET, (_ret == -1), return -1, LOGLEVEL, FMT ": %m", ##__VA_ARGS__) +#define PROPAGATE_ERROR_NULL_STDC_LOG(RET, LOGLEVEL, FMT, ...) \ + _PROPAGATE_ERROR_INTERNAL_LOG(RET, (_ret == NULL), return -1, LOGLEVEL, FMT ": %m", ##__VA_ARGS__) +#define PROPAGATE_ERROR_SD_LOG(RET, LOGLEVEL, FMT, ...) \ + _PROPAGATE_ERROR_INTERNAL_LOG(RET, (_ret < 0), return -1, LOGLEVEL, FMT ": %s", ##__VA_ARGS__, strerrordesc_np(-_ret)) + + +#define _cleanup_(f) __attribute__((cleanup(f))) + +static inline const char *glob_err_to_string(int err) +{ + switch (err) { + case 0: + return "OK"; + case GLOB_NOSPACE: + return "out of memory"; + case GLOB_ABORTED: + return "read error"; + case GLOB_NOMATCH: + return "no matches found"; + default: + return "unknown glob(3) error"; + } +} + +static inline +void cleanup_free(void *p) { + void **ptr = (void**)p; + free(*ptr); + + *ptr = NULL; +} + +static inline +void cleanup_argv(char ***p) { + char **ptr = *p; + char **ptrel = ptr; + + if (!ptr) { + return; + } + + while (*ptrel) { + free(*ptrel); + ptrel++; + } + + free(ptr); + + *p = NULL; +} + +static inline +bool string_to_bool(const char *s) +{ + if (unlikely(!s)) { + return false; + } + + // Trim leading/trailing ASCII whitespace (locale-agnostic) + while (isspace(*s)) { + s++; + } + size_t n = strlen(s); + while (n && isspace(s[n-1])) { + n--; + } + + if (unlikely(n == 0)) { + return false; + } + + // Fast-path single-char cases + if (n == 1) { + char c = s[0]; + if (c == '1' || c == 'y' || c == 'Y') { + return true; + } + return false; + } + + // "yes" + if (n == 3 && strncasecmp(s, "yes", 3) == 0) { + return true; + } + + // "true" + if (n == 4 && strncasecmp(s, "true", 4) == 0) { + return true; + } + + return false; +} + +#endif // VRTD_UTILS_H diff --git a/vrt/vrtd/style.md b/vrt/vrtd/style.md new file mode 100644 index 00000000..400afbaf --- /dev/null +++ b/vrt/vrtd/style.md @@ -0,0 +1,77 @@ +# Coding style + +## Errors + +There is no generally idiomatic way to do error handing in C. Each +project uses it's own convention. + +Here is the convention for vrtd internal functions: functions that +can fail should return a sentinal value indicating faliure. This +sentinal value is `-1` for the `int` type. + +If a function would be naturally `void`, but can fail, make it return +an `int` and return either `-1` (failure) or `0` success. + +Do not try to +"optimize" by using integers of smaller sizes. As this value is +generally returned as a constant, checked immediatly after the return +and then never used again, it is safe to assume it will only ever live +in a register. + +Do **NOT** return other negative values as failures, as the error +handling macros described bellow only use a comparison such as `== -1` +to check for error conditions. + +If a function would naturally return something else, but it can fail, prefer to return +an integer, and pass the "return value" via a pointer instead, as bellow: + +```C +double div(double x, double y) +{ + return x / y; +} + +int div_safe(double x, double y, double *result) +{ + if (y == 0.0) { + return -1; + } + + if (result == NULL) { + // Usually not an error if the caller doesn't want the result. + // Otherwise we would do assert(result != NULL) + + return 0; + } + + *result = x / y; + + return 0; +} +``` + +You should also do this in the case where `-1` is valid value for an `int` +result. + +### Macros for internal error handling + +We provide a set of macros to make error handling more ergonomic. The basic +macros are the `PROPAGATE_ERROR` and `GOTO_ON_ERROR`, and the practically more +common `PROPAGATE_ERROR` and `GOTO_ON_ERROR_LOG`. + +#### `PROPAGATE_ERROR` + +`PROPAGATE_ERROR` returns `-1` if and only if the provided argument is + +```C +int foo(void) +{ + int ret = bar(); + PROPAGATE_ERROR(bar); + + zee(); + + return 0; +} +``` + diff --git a/vrt/vrtd/systemd/vrtd.service b/vrt/vrtd/systemd/vrtd.service new file mode 100644 index 00000000..52a6b043 --- /dev/null +++ b/vrt/vrtd/systemd/vrtd.service @@ -0,0 +1,42 @@ +[Unit] +Description=vrtd daemon + +[Service] +Type=notify +ExecStart=/usr/lib/vrt/vrtd +User=vrtd +Group=vrtd + +WatchdogSec=60s + +DevicePolicy=auto +PrivateDevices=false + +# Create a writable runtime dir for any transient files if you want it: +RuntimeDirectory=vrtd +RuntimeDirectoryMode=0755 + +AmbientCapabilities=CAP_SYS_RAWIO +CapabilityBoundingSet=CAP_SYS_RAWIO + +# Hardening +NoNewPrivileges=true +ProtectSystem=full +ProtectHome=true +PrivateTmp=true +ProtectKernelTunables=true +ProtectKernelModules=true +ProtectControlGroups=true +LockPersonality=true +MemoryDenyWriteExecute=true +RestrictRealtime=true +RestrictSUIDSGID=true +SystemCallArchitectures=native +RestrictAddressFamilies=AF_UNIX +ReadWritePaths=/run/vrtd + +Restart=on-failure +RestartSec=2s + +[Install] +WantedBy=multi-user.target diff --git a/vrt/vrtd/systemd/vrtd.socket b/vrt/vrtd/systemd/vrtd.socket new file mode 100644 index 00000000..c0a9433f --- /dev/null +++ b/vrt/vrtd/systemd/vrtd.socket @@ -0,0 +1,13 @@ +[Unit] +Description=vrtd UNIX SEQPACKET socket + +[Socket] +ListenSequentialPacket=/run/vrtd.sock +FileDescriptorName=api +SocketMode=0660 +SocketGroup=vrt +RemoveOnStop=yes +DirectoryMode=0755 + +[Install] +WantedBy=sockets.target diff --git a/vrt/vrtd/udev/99-vrtd.rules b/vrt/vrtd/udev/99-vrtd.rules new file mode 100644 index 00000000..dd24b003 --- /dev/null +++ b/vrt/vrtd/udev/99-vrtd.rules @@ -0,0 +1,2 @@ +KERNEL=="slash", MODE="0600", OWNER="vrtd", GROUP="vrtd" +KERNEL=="slash_ctl*", MODE="0600", OWNER="vrtd", GROUP="vrtd" \ No newline at end of file diff --git a/vrt/vrtd/vrtd-flow.rst b/vrt/vrtd/vrtd-flow.rst new file mode 100644 index 00000000..9fb43c4f --- /dev/null +++ b/vrt/vrtd/vrtd-flow.rst @@ -0,0 +1,343 @@ +V80 Runtime Daemon – Client Flow +================================ + +Overview +-------- + +``vrtd`` (the *V80 Runtime Daemon*) multiplexes access to SLASH-managed FPGA +devices and enforces permission rules for multi-tenancy. Applications talk to +``vrtd`` over a Unix domain socket via: + +- **C API**: *libvrtd* (````) +- **C++ wrapper**: *libvrtd++* (``vrtd::Session``, ``vrtd::Device``, ``vrtd::Bar``, + ``vrtd::BarFile``) + +Pipeline +~~~~~~~~ + +.. code-block:: + + +-----------+ +----------+ +-----------+ +---------+ +--------+ + | libvrt | <-- | libvrtd++| <-- | libvrtd | <-- | vrtd | <-- |libslash| + +-----------+ +----------+ +-----------+ +---------+ +--------+ + AF_UNIX / SOCK_SEQPACKET + sendmsg/recvmsg (+SCM_RIGHTS) + +Roles +~~~~~ + +- **SLASH kernel module / libslash**: low-level device control. +- **vrtd**: daemon that arbitrates access and permissions (multi-tenant). +- **libvrtd (C)**: wire protocol client; exposes typed requests/responses. +- **libvrtd++ (C++)**: safer RAII/exception wrapper on top of libvrtd. + +Quick Start (C++) +----------------- + +Minimal program that opens a session, grabs device 0, opens BAR 0, and reads an +``uint32_t`` via RAII: + +.. code-block:: cpp + + #include + #include + #include + #include + #include + #include + + int main() { + try { + // Prefer the corrected macro name VRTD_STANDARD_PATH if available. + vrtd::Session s; // defaults to the standard socket path + + auto n = s.getNumDevices(); + if (n == 0) { + std::cout << "No devices\n"; + return 0; + } + + vrtd::Device d = s.getDevice(0); + vrtd::Bar b = d.getBar(0); + + vrtd::BarFile bf = b.openBarFile(); + + // Start a READ session at offset 0 and access as uint32_t + auto p = bf.getPtr(vrtd::BarFile::Direction::Read, /*address=*/0); + std::uint32_t value = *p; // read via volatile + (void)value; + + bf.close(); // explicit close (will also run in destructor if no op active) + } catch (const vrtd::Error& e) { + std::cerr << "vrtd error: " << e.what() << "\n"; + return 1; + } catch (const std::exception& e) { + std::cerr << "std error: " << e.what() << "\n"; + return 1; + } + return 0; + } + +Quick Start (C) +--------------- + +Same operation using the C API and explicit bracketing for memory access: + +.. code-block:: c + + #include + #include + #include + #include + #include + + int main() { + int fd = vrtd_connect(VRTD_STANDARD_PATH); // use corrected macro + if (fd < 0) { perror("vrtd_connect"); return 1; } + + uint32_t num = 0; + if (vrtd_get_num_devices(fd, &num) != VRTD_RET_OK || num == 0) { + fprintf(stderr, "no devices or error\n"); close(fd); return 1; + } + + // Open BAR 0 of device 0 and map it + struct slash_bar_file bf = {0}; + enum vrtd_ret r = vrtd_open_bar_file(fd, /*dev=*/0, /*bar=*/0, &bf); + if (r != VRTD_RET_OK) { + fprintf(stderr, "open bar failed: %d\n", (int)r); close(fd); return 1; + } + + // READ session for a 32-bit value at offset 0 + slash_bar_file_start_read(&bf); + volatile uint32_t *p = (volatile uint32_t*)((volatile uint8_t*)bf.map + 0); + uint32_t value = *p; + slash_bar_file_end_read(&bf); + (void)value; + + vrtd_close_bar_file(&bf); // unmap + close + close(fd); + return 0; + } + +End-to-End Flow (C and C++) +--------------------------- + +This section walks the common path from connection to BAR memory access, showing the **C** and **C++** entry points side-by-side, plus ownership, error, and threading notes at each step. (No full examples—only the exact calls you’ll use.) + +1) Connect +~~~~~~~~~~ + +- **C** + - Call: ``int fd = vrtd_connect(VRTD_STANDARD_PATH);`` + - On success: ``fd >= 0`` (caller **owns** and must ``close(fd)``). + - On failure: returns ``-1`` and sets ``errno``. +- **C++** + - Call: ``vrtd::Session s;`` or ``vrtd::Session s{"/run/vrtd.sock"};`` + - On failure: **throws** ``vrtd::Error(VRTD_RET_BAD_CONN)``. + - Ownership: RAII; destructor calls ``close()``. ``s.close()`` is explicit. + - State/introspection: ``s.isClosed()``, ``static_cast(s)``. + - Thread-safety: **Thread-safe** (internal mutex). + +2) Discover Devices +~~~~~~~~~~~~~~~~~~~ + +- **C** + - Count: ``vrtd_get_num_devices(fd, &count)`` → ``VRTD_RET_OK`` on success. + - Name: ``vrtd_get_device_info(fd, dev_index, name_buf)`` where + ``char name_buf[128];`` (NUL-terminated; buffer **must be** 128 bytes). +- **C++** + - Count: ``uint32_t n = s.getNumDevices();`` → may **throw** ``vrtd::Error``. + - Select: ``vrtd::Device d = s.getDevice(i);`` (0-based; throws + ``vrtd::Error(VRTD_RET_NOEXIST)`` if out of range). + - Accessors: ``d.getNum()``, ``d.getName()``. + - Lifetime note: Any ``Device`` becomes **invalid** if its originating + ``Session`` is closed or moved; later calls **throw**. + +3) BAR Metadata +~~~~~~~~~~~~~~~ + +- **C** + - Call: ``vrtd_get_bar_info(fd, dev, bar, &info)`` where + ``struct slash_ioctl_bar_info info;`` + - Returns: Usability, in-use flag, physical start address, length (bytes). +- **C++** + - Call: ``vrtd::Bar b = d.getBar(bar_index);`` → may **throw** ``vrtd::Error``. + - Query: ``b.isUsable()``, ``b.isInUse()`` (currently always ``false``), + ``b.getStartAddress()``, ``b.getLength()`` (both **bytes**, physical). + - Lifetime note: ``Bar`` is **invalidated** if its session is closed/moved. + +4) Obtain BAR FD (for mmap) +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **C** + - Call: ``vrtd_get_bar_fd(fd, dev, bar, &bar_fd, &len)`` + - Behavior: Receives ``bar_fd`` via ``SCM_RIGHTS``; caller **owns** and must ``close(bar_fd)`` when done (or use Step 5 helper). +- **C++** + - Not typically called directly; the wrapper performs this internally in + ``Bar::openBarFile()``. + +5) Map the BAR +~~~~~~~~~~~~~~ + +- **C** + - Call: ``vrtd_open_bar_file(fd, dev, bar, &bf)`` where + ``struct slash_bar_file bf;`` + - On success: ``bf.fd`` valid, ``bf.map`` is mapped, ``bf.len`` is size. + - Unmap/close: ``vrtd_close_bar_file(&bf);`` (safe to call multiple times; no-op if already unmapped). +- **C++** + - Call: ``vrtd::BarFile bf = b.openBarFile();`` → may **throw** ``vrtd::Error``. + - Ownership: RAII; ``BarFile`` owns FD + mapping. + - Close: ``bf.close();`` / destructor. **May throw** if an operation is still in progress (see Step 6). + - State: ``bf.isClosed()``, ``bf.getLen()``. + +6) Access BAR Memory +~~~~~~~~~~~~~~~~~~~~ + +- **C** + - **Read**: ``slash_bar_file_start_read(&bf);`` … access via + ``volatile`` pointer into ``bf.map`` … ``slash_bar_file_end_read(&bf);`` + - **Write**: ``slash_bar_file_start_write(&bf);`` … access … ``slash_bar_file_end_write(&bf);`` + - Notes: + - Use ``(volatile uint8_t*)bf.map + offset`` to compute addresses. + - Ensure alignment and bounds (``offset + sizeof(T) <= bf.len``). + - Access semantics use ``volatile``. +- **C++** + - Preferred: ``auto p = bf.getPtr(vrtd::BarFile::Direction::Read /*or Write*/, offset);`` + - Returns a **move-only** ``vrtd::BarFilePtr`` that brackets the operation and + ends it automatically on destruction. + - Misuse throws ``std::runtime_error`` (closed, bad address, or another op in progress). + - Only one operation (read **or** write) may be active at a time per ``BarFile``. + - ``T`` should be trivially copyable/standard-layout; access is via **``volatile``**. + - Raw pointer (advanced): ``bf.getRawPtr(offset)`` → ``volatile void*`` + - **Caller must** manually call the appropriate ``slash_bar_file_start_*`` / + ``_end_*`` functions; recommended only when RAII bracketing cannot be used. + +Error Model & Mapping +--------------------- + +- **C** functions return ``vrtd_ret`` (check for ``VRTD_RET_OK`` before using outputs). +- **C++** methods **throw** ``vrtd::Error``; transport/socket failures map to + ``VRTD_RET_BAD_CONN``. ``vrtd::Error::what()`` returns a static, human-readable string. +- Local misuse in ``BarFile``/``BarFilePtr`` (e.g., overlapping ops, bad address) throws ``std::runtime_error``. + +Thread Safety Summary +~~~~~~~~~~~~~~~~~~~~~ + +- **Session / Device / Bar (C++)**: Public methods are **thread-safe** (internal mutex). + Objects remain **logically** tied to the lifetime of their originating ``Session``. +- **BarFile / BarFilePtr (C++)**: **Not thread-safe**. At most one active read/write + operation per ``BarFile``. ``close()`` / destructor may **throw** if an operation is active. + +Lifetime & Moves (C++) +~~~~~~~~~~~~~~~~~~~~~~ + +- Moving or closing a ``Session`` invalidates previously obtained ``Device`` and ``Bar`` objects (their methods will throw thereafter). +- ``BarFile`` is move-only. Ensure all ``BarFilePtr``s have been destroyed **before** + calling ``bf.close()`` or letting the destructor run, otherwise an exception may be thrown. + + +Wire Protocol (High-Level) +-------------------------- + +- Transport: **AF_UNIX** + ``SOCK_SEQPACKET``. +- Messages: request/response headers (size, opcode, seqno) + body. +- FD passing: responses may carry a file descriptor using ``SCM_RIGHTS`` + (e.g., for BAR file access). +- Size limits: request body must respect protocol bounds + (e.g. ``VRTD_MSG_MAX_SIZE`` minus headers). +- Generic escape hatch: ``vrtd_raw_request`` sends arbitrary opcodes; most + users should prefer typed helpers. + +C API at a Glance +----------------- + +- ``vrtd_connect(path)`` → returns ``fd`` (close with ``close()``). +- ``vrtd_get_num_devices(fd, &out)`` → device count. +- ``vrtd_get_device_info(fd, dev, name[128])`` → device name (NUL-terminated). +- ``vrtd_get_bar_info(fd, dev, bar, &info)`` → BAR metadata. +- ``vrtd_get_bar_fd(fd, dev, bar, &fd_out, &len)`` → BAR FD + length. +- ``vrtd_open_bar_file(fd, dev, bar, &slash_bar_file)`` → maps BAR. +- ``vrtd_close_bar_file(&slash_bar_file)`` → unmaps/closes BAR. +- ``vrtd_raw_request(fd, opcode, ...)`` → low-level request/response. + +C++ Wrapper Flow +---------------- + +- ``vrtd::Session``: owns the connection; **thread-safe** (internal mutex). + - ``getNumDevices()``, ``getDevice(i)``, ``close()``, ``operator bool``. +- ``vrtd::Device``: value-type view of a device (number + name). + - **Invalidated** if its originating session is closed or moved. + - ``getBar(bar_index)`` → ``vrtd::Bar``. +- ``vrtd::Bar``: value-type BAR metadata and opener. + - **Invalidated** if the originating session is closed or moved. + - ``openBarFile()`` → ``vrtd::BarFile`` (owns FD + mapping). +- ``vrtd::BarFile``: **not thread-safe**; single in-flight op. + - ``getPtr(Direction, offset)`` → move-only pointer that brackets + read/write operations and ends them on destruction. + - ``getRawPtr(offset)`` → volatile pointer (caller must bracket manually). + - ``close()`` / destructor may **throw** if an op is still active. + +Error Model +----------- + +- All typed C functions return ``vrtd_ret``. Success is ``VRTD_RET_OK``. +- The C++ API throws ``vrtd::Error``; ``what()`` returns a static + human-readable string mapped from the code (no allocation). + +Common codes: + +- ``VRTD_RET_OK`` — success. +- ``VRTD_RET_BAD_LIB_CALL`` — bad library usage (e.g., null out-pointer). +- ``VRTD_RET_BAD_CONN`` — broken/absent transport (socket errors, etc.). +- ``VRTD_RET_BAD_REQUEST`` — malformed request. +- ``VRTD_RET_INVALID_ARGUMENT`` — invalid argument. +- ``VRTD_RET_NOEXIST`` — resource does not exist (e.g., out-of-range index). +- ``VRTD_RET_INTERNAL_ERROR`` — daemon-side failure; check vrtd logs. +- ``VRTD_RET_AUTH_ERROR`` — permission error. + +Thread Safety +------------- + +- **Session / Device / Bar (C++)**: public methods are **thread-safe**; they + synchronize on the owning session’s mutex. However, *object validity* is tied + to the session—closing or moving a session invalidates previously obtained + ``Device``/``Bar`` values. +- **BarFile / BarFilePtr (C++)**: **not thread-safe**. Only one read or write + operation may be active at a time on a single ``BarFile``. Re-entrant calls + (e.g., two ``getPtr()``s) throw. + +Lifetime & Moves (C++) +---------------------- + +- Moving a ``Session`` closes the moved-from object. Any ``Device``/``Bar`` from + that session become invalid; subsequent calls on them will throw. +- ``BarFile`` is move-only. Its destructor (or ``close()``) releases resources. + If a read/write operation is active (a ``BarFilePtr`` still alive), + destruction/close may throw to signal misuse. + +Addressing & Access Semantics +----------------------------- + +- BAR addresses returned by metadata are **physical**. ``getStartAddress()`` and + ``getLength()`` are in **bytes**. +- ``BarFile::getPtr()`` checks only ``address < len``—the caller must ensure + alignment and that ``address + sizeof(T) <= len``. +- Accesses are through **``volatile``** pointers to model device memory. + +Notes & Compatibility +--------------------- + +- The intended default socket macro name is ``VRTD_STANDARD_PATH``. If you see a + misspelled macro in older headers, prefer passing an explicit path or define + ``VRTD_STANDARD_PATH`` accordingly. +- Use typed helpers where possible; ``vrtd_raw_request`` is for advanced usage. + +Troubleshooting +--------------- + +- **Out-of-range device index** → ``VRTD_RET_NOEXIST`` (C) or ``vrtd::Error`` (C++). +- **Session closed/moved, then using Device/Bar** → throws (invalid lifetime). +- **Two concurrent ``getPtr()`` calls on the same BarFile** → throws re-entrancy error. +- **Transport errors** (socket down, daemon not running) → map to + ``VRTD_RET_BAD_CONN`` / ``vrtd::Error`` with "connection" message. +