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Hi! I'm trying to use this lib for some co-simulation works but I have some questions about its feasibility for my use case.
We have user logic based on XDMA and QDMA, but Xilinx's IP Core is encrypted and can't be simulated with verilator. However, I see that this lib has software interfaces for XDMA and QDMA, so I'm wondering if we can connect our user logic to these software interfaces for simulation purposes? I'm not sure if this is feasible or if there are any potential issues to be aware of. Thank you very much!