Maintain a reverse mapping of SigBits to module cells/wires to avoid rescanning the whole module for every ABC run.

Looping over all module cells and wires to call `mark_port()` in every ABC run doesn't scale when there are
thousands of ABC runs over very large designs. Instead, keep around a mapping from canonical
SigBits to the cells and wires associated with each SigBit. Then instead of scanning all cells and wires,
we can consider just the relevant cells and wires. Of course we also have to maintain this mapping
as the module is updated between ABC runs, which is a bit annoying. However the speedups are quite
large for big designs.

Author: rocallahan