Merge pull request #5336 from rocallahan/remove-log-cstr

Remove `.c_str()` calls from `log()`/`log_error()`

Author: jix

backends/aiger/aiger.cc

@@ -1040,7 +1040,7 @@ struct AigerBackend : public Backend {
 			std::ofstream mapf;
 			mapf.open(map_filename.c_str(), std::ofstream::trunc);
 			if (mapf.fail())
-				log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
+				log_error("Can't open file `%s' for writing: %s\n", map_filename, strerror(errno));
 			writer.write_map(mapf, verbose_map, no_startoffset);
 		}
 
@@ -1051,7 +1051,7 @@ struct AigerBackend : public Backend {
 			PrettyJson json;
 
 			if (!json.write_to_file(yw_map_filename))
-				log_error("Can't open file `%s' for writing: %s\n", yw_map_filename.c_str(), strerror(errno));
+				log_error("Can't open file `%s' for writing: %s\n", yw_map_filename, strerror(errno));
 			writer.write_ywmap(json);
 		}
 	}

backends/aiger/xaiger.cc

@@ -788,7 +788,7 @@ struct XAigerBackend : public Backend {
 			std::ofstream mapf;
 			mapf.open(map_filename.c_str(), std::ofstream::trunc);
 			if (mapf.fail())
-				log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
+				log_error("Can't open file `%s' for writing: %s\n", map_filename, strerror(errno));
 			writer.write_map(mapf);
 		}
 	}

backends/blif/blif.cc

@@ -674,7 +674,7 @@ struct BlifBackend : public Backend {
 		}
 
 		if (!top_module_name.empty())
-			log_error("Can't find top module `%s'!\n", top_module_name.c_str());
+			log_error("Can't find top module `%s'!\n", top_module_name);
 
 		for (auto module : mod_list)
 			BlifDumper::dump(*f, module, design, config);

backends/btor/btor.cc

@@ -246,7 +246,7 @@ struct BtorWorker
 			string cell_list;
 			for (auto c : cell_recursion_guard)
 				cell_list += stringf("\n    %s", log_id(c));
-			log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str());
+			log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list);
 		}
 
 		cell_recursion_guard.insert(cell);
@@ -1489,7 +1489,7 @@ struct BtorWorker
 			std::ofstream f;
 			f.open(info_filename.c_str(), std::ofstream::trunc);
 			if (f.fail())
-				log_error("Can't open file `%s' for writing: %s\n", info_filename.c_str(), strerror(errno));
+				log_error("Can't open file `%s' for writing: %s\n", info_filename, strerror(errno));
 			for (auto &it : info_lines)
 				f << it;
 			f.close();

backends/edif/edif.cc

@@ -519,7 +519,7 @@ struct EdifBackend : public Backend {
 						continue;
 					} else {
 						for (auto &ref : it.second)
-							log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.first.c_str());
+							log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.first);
 						log_abort();
 					}
 				}

backends/firrtl/firrtl.cc

@@ -347,7 +347,7 @@ void emit_elaborated_extmodules(RTLIL::Design *design, std::ostream &f)
 				auto modInstance = design->module(cell->type);
 				// Ensure that we actually have a module instance
 				if (modInstance == nullptr) {
-					log_error("Unknown cell type %s\n", cell->type.c_str());
+					log_error("Unknown cell type %s\n", cell->type);
 					return;
 				}
 
@@ -505,14 +505,14 @@ struct FirrtlWorker
 						sinkExpr = firstName;
 						break;
 					default:
-						log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal(it->second), dir);
+						log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type, log_signal(it->second), dir);
 						break;
 				}
 				// Check for subfield assignment.
 				std::string bitsString = "bits(";
 				if (sinkExpr.compare(0, bitsString.length(), bitsString) == 0) {
 					if (sinkSig == nullptr)
-						log_error("Unknown subfield %s.%s\n", cell_type.c_str(), sinkExpr.c_str());
+						log_error("Unknown subfield %s.%s\n", cell_type, sinkExpr);
 					// Don't generate the assignment here.
 					// Add the source and sink to the "reverse_wire_map" and we'll output the assignment
 					//  as part of the coalesced subfield assignments for this wire.

backends/functional/cxx.cc

@@ -268,7 +268,7 @@ struct FunctionalCxxBackend : public Backend
 		extra_args(f, filename, args, argidx, design);
 
 		for (auto module : design->selected_modules()) {
-            log("Dumping module `%s'.\n", module->name.c_str());
+            log("Dumping module `%s'.\n", module->name);
 			printCxx(*f, filename, module);
 		}
 	}

backends/functional/smtlib.cc

@@ -285,7 +285,7 @@ struct FunctionalSmtBackend : public Backend {
 		extra_args(f, filename, args, argidx, design);
 
 		for (auto module : design->selected_modules()) {
-			log("Processing module `%s`.\n", module->name.c_str());
+			log("Processing module `%s`.\n", module->name);
 			SmtModule smt(module);
 			smt.write(*f);
 		}

backends/functional/smtlib_rosette.cc

@@ -307,7 +307,7 @@ struct FunctionalSmtrBackend : public Backend {
 		}
 
 		for (auto module : design->selected_modules()) {
-			log("Processing module `%s`.\n", module->name.c_str());
+			log("Processing module `%s`.\n", module->name);
 			SmtrModule smtr(module);
 			smtr.write(*f);
 		}

backends/functional/test_generic.cc

@@ -143,7 +143,7 @@ struct FunctionalTestGeneric : public Pass
 */
 
 		for (auto module : design->selected_modules()) {
-            log("Dumping module `%s'.\n", module->name.c_str());
+            log("Dumping module `%s'.\n", module->name);
 			auto fir = Functional::IR::from_module(module);
 			for(auto node : fir)
 				std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n";