@@ -47,9 +47,9 @@ be found in :file:`frontends/verilog/verilog_lexer.l` in the Yosys source tree.
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The lexer does little more than identifying all keywords and literals recognised
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by the Yosys Verilog frontend.
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- The lexer keeps track of the current location in the Verilog source code using
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- some global variables. These variables are used by the constructor of AST nodes
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- to annotate each node with the source code location it originated from .
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+ The lexer keeps track of the current location in the Verilog source code with
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+ a `` VerilogLexer::out_loc `` and uses it to construct parser-defined
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+ symbol objects .
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Finally the lexer identifies and handles special comments such as "``// synopsys
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translate_off ``" and "``// synopsys full_case ``". (It is recommended to use
@@ -178,21 +178,22 @@ properties:
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- | Source code location
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| Each ``AST::AstNode`` is automatically annotated with the current source
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- code location by the ``AST::AstNode`` constructor. It is stored in the
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- ``std::string filename`` and ``int linenum`` member variables.
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+ code location by the ``AST::AstNode`` constructor. The ``location`` type
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+ is a manual reimplementation of the bison-provided location type. This
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+ type is defined at ``frontends/verilog/verilog_location.h``.
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- The ``AST::AstNode `` constructor can be called with up to two child nodes that
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- are automatically added to the list of child nodes for the new object. This
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+ The ``AST::AstNode `` constructor can be called with up to 4 child nodes. This
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simplifies the creation of AST nodes for simple expressions a bit. For example
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the bison code for parsing multiplications:
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.. code :: none
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- :number-lines:
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+ :number-lines:
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- basic_expr '*' attr basic_expr {
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- $$ = new AstNode(AST_MUL, $1, $4);
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- append_attr($$, $3);
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- } |
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+ basic_expr TOK_ASTER attr basic_expr {
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+ $$ = std::make_unique<AstNode>(AST_MUL, std::move($1), std::move($4));
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+ SET_AST_NODE_LOC($$.get(), @1, @4);
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+ append_attr($$.get(), $3);
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+ } |
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The generated AST data structure is then passed directly to the AST frontend
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that performs the actual conversion to RTLIL.
@@ -204,7 +205,7 @@ tree respectively.
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Transforming AST to RTLIL
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-------------------------
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- The AST Frontend converts a set of modules in AST representation to modules in
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+ The AST frontend converts a set of modules in AST representation to modules in
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RTLIL representation and adds them to the current design. This is done in two
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steps: simplification and RTLIL generation.
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