diff --git a/docs/solutions/reference-designs/eval-ad9081/index.rst b/docs/solutions/reference-designs/eval-ad9081/index.rst index 7ea9aa281..1675b4760 100644 --- a/docs/solutions/reference-designs/eval-ad9081/index.rst +++ b/docs/solutions/reference-designs/eval-ad9081/index.rst @@ -94,8 +94,11 @@ Table of contents #. :ref:`ad9081 quickstart`: #. Using the :ref:`Arria 10 SX SoC ` - #. Using the :ref:`VCK190 & VPK180/Versal ` - #. Using the :ref:`ZCU102/Zynq UltraScale MP SoC ` + #. Using the :ref:`VCK190 & VPK180/Versal ` + #. Using the :ref:`VCU118/ Virtex UltraScale+ ` + #. Using the :ref:`ZC706/ Zynq-7000 SoC ` + #. Using the :ref:`ZCU102/Zynq UltraScale+ MP SoC ` + #. Configure an SD Card with :external+adi-kuiper-gen:doc:`Kuiper ` diff --git a/docs/solutions/reference-designs/eval-ad9081/prerequisites.rst b/docs/solutions/reference-designs/eval-ad9081/prerequisites.rst index fdd8c5c07..8b215648c 100644 --- a/docs/solutions/reference-designs/eval-ad9081/prerequisites.rst +++ b/docs/solutions/reference-designs/eval-ad9081/prerequisites.rst @@ -32,9 +32,9 @@ Hardware prerequisites - LAN cable (Ethernet) - Host PC (Windows or Linux) -#. Internet connection (without proxies makes things much easier) to update the - scripts/binaries on the SD card that came with the ADI FMC Card (firewalls - are OK, proxies make things a pain). +#. Internet connection (without proxies makes things much easier) to update + the scripts/binaries on the SD card that came with the ADI FMC Card + (firewalls are OK, proxies make things a pain). #. RF Test equipment #. An SD card with at least 16GB of memory (in case you're using Linux). You should have received one when purchasing the evaluation board. @@ -45,9 +45,10 @@ Software prerequisites Normally, for basic functionalities regarding visualizing the data received from the FPGA, we use the following: -#. :external+scopy:doc:`Scopy ` v2.0 or later (must contain the IIO plugin) +#. :external+scopy:doc:`Scopy ` v2.0 or later (must contain the IIO + plugin) .. note:: - :adi:`ADI <>` does not offer FPGA carrier platforms for sale or loan; getting - one yourself is the normal part of development or evaluation. + :adi:`ADI <>` does not offer FPGA carrier platforms for sale or loan; + getting one yourself is the normal part of development or evaluation. diff --git a/docs/solutions/reference-designs/eval-ad9081/quickstart/a10soc.rst b/docs/solutions/reference-designs/eval-ad9081/quickstart/a10soc.rst index 1e2e253f0..324aaabaf 100644 --- a/docs/solutions/reference-designs/eval-ad9081/quickstart/a10soc.rst +++ b/docs/solutions/reference-designs/eval-ad9081/quickstart/a10soc.rst @@ -3,15 +3,17 @@ Arria 10 SoC Quick start =============================================================================== -.. image:: ../../images/ad9081_a10soc_setup.jpg - :width: 800 - This guide provides quick instructions on how to setup the :adi:`EVAL-AD9081` on: - :intel:`Arria 10 SoC ` (Rev. C or later) on FMCA +.. image:: ../../images/a10soc.jpg + :width: 900 + +.. esd-warning:: + .. warning:: :adi:`EVAL-AD9082` is not supported on @@ -55,8 +57,8 @@ Instructions on how to manually build the boot files from source can be found here: - :dokuwiki:`Building the Intel SoC-FPGA kernel and devicetrees from source ` -- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build details at - :external+hdl:ref:`build_hdl`. +- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build + details at :external+hdl:ref:`build_hdl`. Required software ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -115,16 +117,17 @@ These resistors can be found on the backside of the A10SoC, underneath the FMCA connector (J29). The following picture shows the required configuration to be compatible with the :adi:`EVAL-AD9081`. +.. image:: ../../images/a10soc_fmc_rework.jpg + :width: 400 + Testing ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Creating the setup ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. image:: ../../images/a10soc.jpg - :width: 900 - -.. esd-warning:: +.. image:: ../../images/ad9081_a10soc_setup.jpg + :width: 800 In the following example, we will make a physical loopback between the ADC and the DAC channels on the evaluation board, using SMA cables. @@ -132,9 +135,10 @@ and the DAC channels on the evaluation board, using SMA cables. Follow the steps in this order, to avoid damaging the components: #. Connect the SMA cables ADC0-DAC0, ADC1-DAC1, ADC2-DAC2, ADC3-DAC3 -#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the - FPGA carrier **HPC1** FMCA (J29) socket -#. Both the HPS (J26) and FPGA (J27) memory module must be installed on the A10SoC +#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the A10SOC + **HPC1** FMCA (J29) socket +#. Both the HPS (J26) and FPGA (J27) memory module must be installed on the + A10SoC #. Insert microSD card into the card socket on the FPGA #. Configure the FPGA for SD card boot mode. That is the :intel:`default position ` @@ -147,9 +151,6 @@ Follow the steps in this order, to avoid damaging the components: #. Observe Kernel and serial console output messages on your terminal (use the first ttyUSB or COM port registered) -.. image:: ../../images/a10soc_fmc_rework.jpg - :width: 400 - Boot messages ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -677,6 +678,13 @@ To reboot the system, run: be taken not to corrupt the file system -- please shut down things, don't just turn off the power switch. Depending on your monitor, the standard power off could be hiding. You can do this from the terminal as well with - :code:`sudo shutdown -h now` or the above-mentioned command for powering off. + :code:`sudo shutdown -h now` or the above-mentioned command for powering + off. .. include:: ../../common/using-iio-osc.rst + +.. + About the IIO devices + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + TBD diff --git a/docs/solutions/reference-designs/eval-ad9081/quickstart/index.rst b/docs/solutions/reference-designs/eval-ad9081/quickstart/index.rst index f8ba33d04..fd8606cac 100644 --- a/docs/solutions/reference-designs/eval-ad9081/quickstart/index.rst +++ b/docs/solutions/reference-designs/eval-ad9081/quickstart/index.rst @@ -5,14 +5,16 @@ Quick start guides The Quick start guides provide simple step by step instructions on how to do an initial system setup for the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` -boards on various FPGA development boards. In these guides, we will discuss how -to program the bitstream, run a no-OS program or boot a Linux distribution. +boards on various FPGA development boards. In these guides, we will discuss +how to program the bitstream, run a no-OS program or boot a Linux distribution. .. toctree:: On A10SoC - On VCK190 - On ZCU102 + On VCK190 + On ZC706 + On VCU118 + On ZCU102 .. _ad9081 carriers: diff --git a/docs/solutions/reference-designs/eval-ad9081/quickstart/versal.rst b/docs/solutions/reference-designs/eval-ad9081/quickstart/vck190.rst similarity index 95% rename from docs/solutions/reference-designs/eval-ad9081/quickstart/versal.rst rename to docs/solutions/reference-designs/eval-ad9081/quickstart/vck190.rst index 43c086830..60dee13b9 100644 --- a/docs/solutions/reference-designs/eval-ad9081/quickstart/versal.rst +++ b/docs/solutions/reference-designs/eval-ad9081/quickstart/vck190.rst @@ -1,16 +1,18 @@ -.. _ad9081 quickstart versal: +.. _ad9081 quickstart vck190: VCK190 Quick start =============================================================================== -.. image:: ../../images/ad9081_vck190_setup.jpg - :width: 800 - This guide provides some quick instructions on how to setup the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` on: - :xilinx:`VCK190` FMCP1 (J51) port +.. image:: ../../images/vck190.jpg + :width: 900 + +.. esd-warning:: + Using Linux as software ------------------------------------------------------------------------------- @@ -37,8 +39,8 @@ here: - :ref:`linux-kernel zynqmp` (the only difference compared to the ZynqMP is that instead of running ``make adi_zynqmp_defconfig``, you must run ``make adi_versal_defconfig``) -- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build details at - :external+hdl:ref:`build_hdl`. +- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build + details at :external+hdl:ref:`build_hdl`. Required Software ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -64,72 +66,69 @@ Required Hardware Testing ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -.. image:: ../../images/vck190.jpg - :width: 900 - Creating the setup ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. esd-warning:: +.. image:: ../../images/ad9081_vck190_setup.jpg + :width: 800 Follow the steps in this order, to avoid damaging the components: -- Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the - FPGA carrier FMC+ FMCP1 socket -- Connect USB UART J207 (Type-C USB) to your host PC -- Insert SD card with ADI Kuiper image into socket J302 -- Insert System Controller SD card into socket J206 -- Configure ACAP for SD boot (mode SW1[4:1] switch in the position - **OFF,OFF,OFF,ON** as seen in the below picture) -.. image:: ../../images/vck190_sw1.jpg - :width: 200 +#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the + VCK190 FMCP1 socket +#. Connect USB UART J207 (Type-C USB) to your host PC +#. Insert SD card with ADI Kuiper image into socket J302 +#. Insert System Controller micro SD card into socket J206 +#. Configure ACAP for SD boot (mode SW1[4:1] switch in the position + **OFF,OFF,OFF,ON** as seen in the below picture) + + .. image:: ../../images/vck190_sw1.jpg + :width: 200 -- Configure System Controller for SD card boot (mode SW11[4:1] switch in the +#. Configure System Controller for SD card boot (mode SW11[4:1] switch in the position **OFF,OFF,OFF,ON** as seen in the below picture). -.. image:: ../../images/vck190_sw11.jpg - :width: 200 + .. image:: ../../images/vck190_sw11.jpg + :width: 200 -- Connect an Ethernet cable to J307 and also to SYSCTL Ethernet port to access - Board Evaluation & Management Tool (BEAM); -- Turn on the power switch on the FPGA board; -- Observe kernel and serial console messages on your terminal, both the ACAP - UART interface and the System controller. (use the first ttyUSB or COM port - registered for the ACAP UART interface, and try the other 2 to find the one - for System Controller); -- On the System Controller console, a BEAM Tool Web Address should be assigned. - Go to this web address to set VADJ_FMC to 1.5V; -- To change VADJ_FMC On BEAM, click 'Test The Board'>'Board Settings'>'FMC'. - Then on 'Set VADJ_FMC', select 1.5V and click 'Set'. +#. Connect an Ethernet cable to J307 and also to SYSCTL Ethernet port to access + Board Evaluation & Management Tool (BEAM); +#. Turn on the power switch on the FPGA board; +#. Observe kernel and serial console messages on your terminal, both the ACAP + UART interface and the System controller. (use the first ttyUSB or COM port + registered for the ACAP UART interface, and try the other 2 to find the one + for System Controller); +#. On the System Controller console, a BEAM Tool Web Address should be assigned. + Go to this web address to set VADJ_FMC to 1.5V; -.. image:: beam-home.jpg - :width: 1000 + .. image:: beam-home.jpg + :width: 1000 -.. image:: beam-board-settings.jpg - :width: 1000 + .. image:: beam-board-settings.jpg + :width: 1000 -.. image:: beam-set-vadj.jpg - :width: 1000 + .. image:: beam-set-vadj.jpg + :width: 1000 -- On the ACAP UART interface console, reboot the system. After reboot, - ad9081 devices should be present. +#. On the ACAP UART interface console, reboot the system. After reboot, + AD9081 devices should be present. -.. note:: + .. note:: - Versal-based carriers (:xilinx:`VCK190`) might not boot with released image. + Versal-based carriers (:xilinx:`VCK190`) might not boot with released image. - The problem appears because some revisions of :xilinx:`VCK190` or - :xilinx:`VPK180` may have the date/time set randomly or in 64bit format. - To make them boot, it is enough to overwrite the date, following next steps: + The problem appears because some revisions of :xilinx:`VCK190` or + :xilinx:`VPK180` may have the date/time set randomly or in 64bit format. + To make them boot, it is enough to overwrite the date, following next steps: - - when booting the board, hit any key to go into u-boot menu - - type ``mw F12A0000 6613DE3D`` (this value is hexa of the date from Unix - Converter webpage) - - continue booting + - when booting the board, hit any key to go into u-boot menu + - type ``mw F12A0000 6613DE3D`` (this value is hexa of the date from Unix + Converter webpage) + - continue booting ACAP SD card boot files -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The files that need to be present on the SD card BOOT partition are: @@ -143,13 +142,13 @@ Copy the BOOT.BIN, boot.scr and system.dtb from the ADI Kuiper image. Then, copy the Image from the ``versal-common`` folder. Setting up UART -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ When setting up the UART make sure you connect to the ACAP UART interface and not the System controller. Boot messages -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Login Information required for the System Controller: @@ -868,13 +867,13 @@ To reboot the system, run: be taken not to corrupt the file system -- please shut down things, don't just turn off the power switch. Depending on your monitor, the standard power off could be hiding. You can do this from the terminal as well with - :code:`sudo shutdown -h now` or the above-mentioned command for powering off. + :code:`sudo shutdown -h now` or the above-mentioned command for powering + off. .. include:: ../../common/using-iio-osc.rst -About the IIO devices -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - .. - This section is with ^^^ because the last section from using-iio-osc.rst which - is included previously, has the last section as ^^^. + About the IIO devices + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + TBD diff --git a/docs/solutions/reference-designs/eval-ad9081/quickstart/vcu118.rst b/docs/solutions/reference-designs/eval-ad9081/quickstart/vcu118.rst new file mode 100644 index 000000000..fca12fbcb --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad9081/quickstart/vcu118.rst @@ -0,0 +1,279 @@ +.. _ad9081 quickstart vcu118: + +VCU118 Quick start +=============================================================================== + +This guide provides quick instructions on how to setup the +:adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` on: + +- :xilinx:`VCU118` FMC+ + +.. image:: ../../images/vcu118.png + :width: 900 + +.. esd-warning:: + +Using Linux as software +------------------------------------------------------------------------------- + +Necessary files +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following files are needed for the system to boot: + +- HDL boot image: ``BOOT.BIN`` +- Linux Kernel image: ``Image`` +- Linux device tree: ``system.dtb`` + +They can either be taken from the SD card -- already generated by us, or you +can build them manually. + +In the following sections, we explain **how to take them from the SD card**. + +Instructions on how to manually build the boot files from source can be found +here: + +- :ref:`linux-kernel microblaze` +- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build + details at :external+hdl:ref:`build_hdl`. + +Required Software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- SD Card 16GB imaged with :external+adi-kuiper-gen:doc:`Kuiper ` + (check out that guide on how to do it, then come back to this section) +- A UART terminal (Putty/Tera Term/Minicom, etc.) with baud rate 115200 (8N1) + +Required Hardware +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx :xilinx:`VCU118` Rev 1.0 or later FPGA board and its power supply +- :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC evaluation board +- SD card with at least 16GB of memory +- 2 x Micro-USB cable +- LAN cable (Ethernet) +- Signal generator +- 4x SMA cables +- (Optional) USB keyboard & mouse and a HDMI compatible monitor +- (Optional) 4 way splitter + +More details as to why you need these, can be found at +:ref:`ad9081 prerequisites`. + +Testing +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Creating the setup +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ../../images/ad9081_vcu118_setup.png + :width: 800 + +In the following example, we will make a physical loopback between the ADC +and the DAC channels on the evaluation board, using SMA cables. + +Follow the steps in this order, to avoid damaging the components: + +#. Connect the SMA cables ADC0-DAC0, ADC1-DAC1, ADC2-DAC2, ADC3-DAC3 +#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the VCU118 + **FMC+** socket +#. Insert SD card into the SD card socket on the FPGA +#. Configure :xilinx:`VCU118` for SD card boot mode (mode SW6[3:1] switch in + the position **1: Down, 2: Down, 3: Up, 4: Up** ) +#. Plug-in an Ethernet cable from your router/switch to the Ethernet port on + the FPGA board +#. Connect USB UART (Micro-USB) to your host PC +#. (Optional) Connect a monitor to the FPGA by HDMI, and a mouse and a keyboard +#. Connect the power supply for the FPGA +#. Turn on the power switch on the FPGA board +#. Observe Kernel and serial console output messages on your terminal (use + the first ttyUSB or COM port registered) + +Boot messages +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following is what is printed in the serial console, after you have +connected to the proper ttyUSB or COM port: + +.. collapsible:: Complete boot log + + :: + + U-Boot 2018.01-21442-gf06dec3cab (Nov 10 2023 - 16:08:56 +0200) Xilinx ZynqMP VCU118 revA, Build: jenkins-development-build_uboot-6 + + I2C: ready + DRAM: 4 GiB + + +Useful commands for the serial terminal +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The below commands are to be run in the serial terminal connected to the FPGA. + +To find out the IP of the FPGA board, run the following command and take the +IP specified at "eth0 inet": + +.. shell:: + + $ifconfig + +To see the IIO devices detected, run: + +.. shell:: + + $iio_info | grep iio:device + iio:device0: hmc7044 + iio:device1: axi-ad9081-tx-hpc (buffer capable) + iio:device2: axi-ad9081-rx-hpc (buffer capable) + +To see the EEPROM specifications, run: + +.. shell:: + + $fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom + +To use the :dokuwiki:`JESD204 status utility `, +run: + +.. shell:: + + $jesd_status + +All links should be in DATA without errors: + +.. shell:: + + $jesd_status -s + (DEVICES) Found 2 JESD204 Link Layer peripherals + + (0): axi-jesd204-rx/44a90000.axi-jesd204-rx [*] + (1): axi-jesd204-tx/44b90000.axi-jesd204-tx + + (STATUS) + Link is enabled + Link Status DATA + Measured Link Clock (MHz) 249.998 + Reported Link Clock (MHz) 250.000 + Measured Device Clock (MHz) 250.000 + Reported Device Clock (MHz) 250.000 + Desired Device Clock (MHz) 250.000 + Lane rate (MHz) 10000.000 + Lane rate / 40 (MHz) 250.000 + LMFC rate (MHz) 7.812 + SYSREF captured Yes + SYSREF alignment error No + SYNC~ + + (LANE STATUS) + Lane# 0 1 2 3 + Errors 0 0 0 0 + Latency (Multiframes/Octets) 1/22 1/20 1/25 1/21 + CGS State DATA DATA DATA DATA + Initial Frame Sync Yes Yes Yes Yes + Initial Lane Alignment Sequence Yes Yes Yes Yes + +To power off the system, run the following command, and wait for the final +message to be printed, then power off the FPGA board from the switch as well. + +.. shell:: + + $poweroff + +To reboot the system, run: + +.. shell:: + + $reboot + +.. important:: + + Even thought this is Linux, this is a persistent file systems. Care should + be taken not to corrupt the file system -- please shut down things, don't + just turn off the power switch. Depending on your monitor, the standard + power off could be hiding. You can do this from the terminal as well with + :code:`sudo shutdown -h now` or the above-mentioned command for powering + off. + +.. include:: ../../common/using-iio-osc.rst + +.. + About the IIO devices + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + TBD + +Using no-OS as software +------------------------------------------------------------------------------- + +Necessary files +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following files are needed for the system to boot: + +- HDL boot file: ``system_top.xsa`` +- no-OS project: :git-no-os:`projects/ad9081` + +Instructions on how to build the boot files from source can be found here: + +- :external+no-OS:doc:`projects/adc/ad9081`. More no-OS build + details at :external+no-OS:doc:`build_guide`. +- :external+hdl:ref:`ad9081_fmca_ebz`. More HDL build details at + :external+hdl:ref:`build_hdl`. + +Required Software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx Vivado and Vitis (downloading Vitis from + `here `_ + will include Vivado as well) +- An UART terminal (Putty/Tera Term/Minicom, etc.), Baud rate 115200 (8N1) + +Required Hardware +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx :xilinx:`VCU118` Rev 1.0 or later FPGA board and its power supply +- :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC evaluation board +- 2x Micro-USB cables, one for UART and one for JTAG +- (Optional) USB keyboard & mouse and a HDMI-compatible monitor + +More details as to why you need these, can be found at +:ref:`ad9081 prerequisites`. + +Testing +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Creating the setup +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ../../images/ad9081_vcu118_setup.png + :width: 800 + +Follow the steps in this order, to avoid damaging the components: + +#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the VCU118 + **FMC+** socket +#. Configure :xilinx:`VCU118` for SD card boot mode (mode SW6[3:1] switch in + the position **1: Down, 2: Down, 3: Up, 4: Up** ) +#. Connect USB UART (Micro-USB) to your host PC +#. Connect USB JTAG (Micro-USB) to your host PC +#. (Optional) Connect a monitor to the FPGA by HDMI, and a mouse and a keyboard +#. Turn on the power switch on the FPGA board +#. Observe console output messages on your terminal (use the first ttyUSB or + COM port registered) + +Console output +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following is what is printed in the serial console, after you have +connected to the proper ttyUSB or COM port: + +.. collapsible:: Complete boot log + + :: + + Xilinx Microblaze First Stage Boot Loader + +.. + TBD + +.. include:: ../../common/using-iio-osc.rst diff --git a/docs/solutions/reference-designs/eval-ad9081/quickstart/zc706.rst b/docs/solutions/reference-designs/eval-ad9081/quickstart/zc706.rst new file mode 100644 index 000000000..144acda4b --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad9081/quickstart/zc706.rst @@ -0,0 +1,783 @@ +.. _ad9081 quickstart zc706: + +ZC706 Quick start +=============================================================================== + +This guide provides quick instructions on how to setup the +:adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` on: + +- :xilinx:`ZC706` FMC HPC + +.. image:: ../../images/zc706.png + :width: 900 + +.. esd-warning:: + +Using Linux as software +------------------------------------------------------------------------------- + +Necessary files +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following files are needed for the system to boot: + +- HDL boot image: ``BOOT.BIN`` +- Linux Kernel image: ``uImage`` +- Linux device tree: ``devicetree.dtb`` + +They can either be taken from the SD card -- already generated by us, or you +can build them manually. + +In the following sections, we explain **how to take them from the SD card**. + +Instructions on how to manually build the boot files from source can be found +here: + +- :ref:`linux-kernel zynq` +- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build + details at :external+hdl:ref:`build_hdl`. + +Required Software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- SD Card 16GB imaged with :external+adi-kuiper-gen:doc:`Kuiper ` + (check out that guide on how to do it, then come back to this section) +- A UART terminal (Putty/Tera Term/Minicom, etc.) with baud rate 115200 (8N1) + +Required Hardware +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx :xilinx:`ZC706`` Rev 1.2 or higher FPGA board and its power supply +- :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC evaluation board +- SD card with at least 16GB of memory +- Mini-USB cable (UART) +- LAN cable (Ethernet) +- 4x SMA cables +- (Optional) USB keyboard & mouse and a HDMI compatible monitor + +More details as to why you need these, can be found at +:ref:`ad9081 prerequisites`. + +Testing +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Creating the setup +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ../../images/ad9081-fmca-ebz-zc706.png + :width: 800 + +In the following example, we will make a physical loopback between the ADC +and the DAC channels on the evaluation board, using SMA cables. + +Follow the steps in this order, to avoid damaging the components: + +#. Connect the SMA cables ADC0-DAC0, ADC1-DAC1, ADC2-DAC2, ADC3-DAC3 +#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the ZC706 + **HPC** FMC socket +#. Insert SD card into the SD card socket on the FPGA +#. Configure :xilinx:`ZC706`` for SD card boot mode (Set the jumpers: + The main one is: SW11 - Big Blue Switch in the middle, which controls the + Boot Mode, it needs to be set: **1: Down, 2: Down, 3: Up, 4: Up, 5: Down**) +#. Plug-in an Ethernet cable from your router/switch to the Ethernet port on + the FPGA board +#. Connect USB UART (Mini-USB) to your host PC +#. (Optional) Connect a monitor to the FPGA by HDMI, and a mouse and a keyboard +#. Connect the power supply for the FPGA +#. Turn on the power switch on the FPGA board +#. Observe Kernel and serial console output messages on your terminal (use + the first ttyUSB or COM port registered) + +Boot messages +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following is what is printed in the serial console, after you have +connected to the proper ttyUSB or COM port: + +.. collapsible:: Complete boot log + + :: + + U-Boot 2014.07-dirty (Nov 20 2014 - 17:07:55) + + Board: Xilinx Zynq + I2C: ready + DRAM: ECC disabled 1 GiB + MMC: zynq_sdhci: 0 + SF: Detected S25FL128S_64K with page size 512 Bytes, erase size 128 KiB, total 32 MiB + In: serial + Out: serial + Err: serial + Net: Gem.e000b000 + Hit any key to stop autoboot: 0 + Device: zynq_sdhci + Manufacturer ID: 3 + OEM: 5344 + Name: SC32G + Tran Speed: 50000000 + Rd Block Len: 512 + SD version 3.0 + High Capacity: Yes + Capacity: 29.7 GiB + Bus Width: 4-bit + reading uEnv.txt + 407 bytes read in 27 ms (14.6 KiB/s) + Loaded environment from uEnv.txt + Importing environment from SD ... + Running uenvcmd ... + Copying Linux from SD to RAM... + reading uImage + 6506856 bytes read in 580 ms (10.7 MiB/s) + reading devicetree.dtb + 23071 bytes read in 39 ms (577.1 KiB/s) + reading uramdisk.image.gz + ** Unable to read file uramdisk.image.gz ** + ## Booting kernel from Legacy Image at 03000000 ... + Image Name: Linux-5.4.0-93252-ga4800dc5737b + Image Type: ARM Linux Kernel Image (uncompressed) + Data Size: 6506792 Bytes = 6.2 MiB + Load Address: 00008000 + Entry Point: 00008000 + Verifying Checksum ... OK + ## Flattened Device Tree blob at 02a00000 + Booting using the fdt blob at 0x2a00000 + Loading Kernel Image ... OK + Loading Device Tree to 1fff7000, end 1ffffa1e ... OK + + Starting kernel ... + + Booting Linux on physical CPU 0x0 + Linux version 5.4.0-93252-ga4800dc5737b (michael@mhenneri-D06) (gcc version 8.2.0 (GCC)) #2881 SMP PREEMPT Fri Mar 19 16:22:37 CET 2021 + CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d + CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache + OF: fdt: Machine model: Xilinx Zynq ZC706 + OF: fdt: earlycon: stdout-path /amba@0/uart@E0001000 not found + Memory policy: Data cache writealloc + cma: Reserved 128 MiB at 0x38000000 + percpu: Embedded 15 pages/cpu s29516 r8192 d23732 u61440 + Built 1 zonelists, mobility grouping on. Total pages: 260608 + Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype=ext4 rootwait clk_ignore_unused cpuidle.off=1 + Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear) + Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear) + mem auto-init: stack:off, heap alloc:off, heap free:off + Memory: 888452K/1048576K available (9216K kernel code, 743K rwdata, 7044K rodata, 1024K init, 162K bss, 29052K reserved, 131072K cma-reserved, 131072K highmem) + rcu: Preemptible hierarchical RCU implementation. + rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. + Tasks RCU enabled. + rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. + rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 + NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16 + efuse mapped to (ptrval) + slcr mapped to (ptrval) + L2C: platform modifies aux control register: 0x72360000 -> 0x72760000 + L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000 + L2C-310 erratum 769419 enabled + L2C-310 enabling early BRESP for Cortex-A9 + L2C-310 full line of zeros enabled for Cortex-A9 + L2C-310 ID prefetch enabled, offset 1 lines + L2C-310 dynamic clock gating enabled, standby mode enabled + L2C-310 cache controller enabled, 8 ways, 512 kB + L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001 + random: get_random_bytes called from start_kernel+0x2cc/0x454 with crng_init=0 + zynq_clock_init: clkc starts at (ptrval) + Zynq clock init + sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns + clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns + Switching to timer-based delay loop, resolution 3ns + clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns + timer #0 at (ptrval), irq=17 + Console: colour dummy device 80x30 + Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333) + pid_max: default: 32768 minimum: 301 + Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear) + Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear) + CPU: Testing write buffer coherency: ok + CPU0: Spectre v2: using BPIALL workaround + CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 + Setting up static identity map for 0x100000 - 0x100060 + rcu: Hierarchical SRCU implementation. + smp: Bringing up secondary CPUs ... + CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 + CPU1: Spectre v2: using BPIALL workaround + smp: Brought up 1 node, 2 CPUs + SMP: Total of 2 processors activated (1333.33 BogoMIPS). + CPU: All CPU(s) started in SVC mode. + devtmpfs: initialized + VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 + clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns + futex hash table entries: 512 (order: 3, 32768 bytes, linear) + pinctrl core: initialized pinctrl subsystem + NET: Registered protocol family 16 + DMA: preallocated 256 KiB pool for atomic coherent allocations + hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. + hw-breakpoint: maximum watchpoint size is 4 bytes. + zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval) + e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 25, base_baud = 3125000) is a xuartps + printk: console [ttyPS0] enabled + SCSI subsystem initialized + usbcore: registered new interface driver usbfs + usbcore: registered new interface driver hub + usbcore: registered new device driver usb + mc: Linux media interface: v0.10 + videodev: Linux video capture interface: v2.00 + jesd204: created con: id=0, topo=0, link=0, /amba/spi@e0007000/hmc7044@0 <-> /fpga-axi@0/axi-adxcvr-tx@44b60000 + jesd204: created con: id=1, topo=0, link=2, /amba/spi@e0007000/hmc7044@0 <-> /fpga-axi@0/axi-adxcvr-rx@44a60000 + jesd204: created con: id=2, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@44b60000 <-> /fpga-axi@0/axi-jesd204-tx@44b90000 + jesd204: created con: id=3, topo=0, link=2, /fpga-axi@0/axi-adxcvr-rx@44a60000 <-> /fpga-axi@0/axi-jesd204-rx@44a90000 + jesd204: created con: id=4, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@44b90000 <-> /fpga-axi@0/axi-ad9081-tx-hpc@44b10000 + jesd204: created con: id=5, topo=0, link=2, /fpga-axi@0/axi-jesd204-rx@44a90000 <-> /fpga-axi@0/axi-ad9081-rx-hpc@44a10000 + jesd204: created con: id=6, topo=0, link=2, /fpga-axi@0/axi-ad9081-rx-hpc@44a10000 <-> /amba/spi@e0006000/ad9081@0 + jesd204: created con: id=7, topo=0, link=0, /fpga-axi@0/axi-ad9081-tx-hpc@44b10000 <-> /amba/spi@e0006000/ad9081@0 + jesd204: /amba/spi@e0006000/ad9081@0: JESD204[2] transition uninitialized -> initialized + jesd204: /amba/spi@e0006000/ad9081@0: JESD204[0] transition uninitialized -> initialized + jesd204: found 8 devices and 1 topologies + FPGA manager framework + Advanced Linux Sound Architecture Driver Initialized. + clocksource: Switched to clocksource arm_global_timer + thermal_sys: Registered thermal governor 'step_wise' + NET: Registered protocol family 2 + tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear) + TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear) + TCP bind hash table entries: 8192 (order: 4, 65536 bytes, linear) + TCP: Hash tables configured (established 8192 bind 8192) + UDP hash table entries: 512 (order: 2, 16384 bytes, linear) + UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear) + NET: Registered protocol family 1 + hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing. + hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available + workingset: timestamp_bits=30 max_order=18 bucket_order=0 + bounce: pool size: 64 pages + io scheduler mq-deadline registered + io scheduler kyber registered + zynq-pinctrl 700.pinctrl: zynq pinctrl initialized + dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330 + dma-pl330 f8003000.dmac: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16 + brd: module loaded + loop: module loaded + Registered mathworks_ip class + spi-nor spi2.0: found s25fl128s1, expected n25q128a11 + random: fast init done + spi-nor spi2.0: s25fl128s1 (32768 Kbytes) + 5 fixed-partitions partitions found on MTD device spi2.0 + Creating 5 MTD partitions on "spi2.0": + 0x000000000000-0x000000500000 : "boot" + 0x000000500000-0x000000520000 : "bootenv" + 0x000000520000-0x000000540000 : "config" + 0x000000540000-0x000000fc0000 : "image" + 0x000000fc0000-0x000002000000 : "spare" + MACsec IEEE 802.1AE + libphy: Fixed MDIO Bus: probed + tun: Universal TUN/TAP device driver, 1.6 + libphy: MACB_mii_bus: probed + Marvell 88E1116R e000b000.ethernet-ffffffff:07: attached PHY driver [Marvell 88E1116R] (mii_bus:phy_addr=e000b000.ethernet-ffffffff:07, irq=POLL) + macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 29 (00:0a:35:00:01:22) + usbcore: registered new interface driver asix + usbcore: registered new interface driver ax88179_178a + usbcore: registered new interface driver cdc_ether + usbcore: registered new interface driver net1080 + usbcore: registered new interface driver cdc_subset + usbcore: registered new interface driver zaurus + usbcore: registered new interface driver cdc_ncm + ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver + usbcore: registered new interface driver uas + usbcore: registered new interface driver usb-storage + usbcore: registered new interface driver usbserial_generic + usbserial: USB Serial support registered for generic + usbcore: registered new interface driver ftdi_sio + usbserial: USB Serial support registered for FTDI USB Serial Device + usbcore: registered new interface driver upd78f0730 + usbserial: USB Serial support registered for upd78f0730 + chipidea-usb2 e0002000.usb: e0002000.usb supply vbus not found, using dummy regulator + ULPI transceiver vendor/product ID 0x0424/0x0007 + Found SMSC USB3320 ULPI transceiver. + ULPI integrity check: passed. + ci_hdrc ci_hdrc.0: EHCI Host Controller + ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1 + ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00 + usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.04 + usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 + usb usb1: Product: EHCI Host Controller + usb usb1: Manufacturer: Linux 5.4.0-93252-ga4800dc5737b ehci_hcd + usb usb1: SerialNumber: ci_hdrc.0 + hub 1-0:1.0: USB hub found + hub 1-0:1.0: 1 port detected + i2c /dev entries driver + si570 1-005d: registered, current frequency 156250000 Hz + i2c i2c-0: Added multiplexed i2c bus 1 + adv7511 2-0039: 2-0039 supply avdd not found, using dummy regulator + adv7511 2-0039: 2-0039 supply dvdd not found, using dummy regulator + adv7511 2-0039: 2-0039 supply pvdd not found, using dummy regulator + adv7511 2-0039: 2-0039 supply bgvdd not found, using dummy regulator + adv7511 2-0039: 2-0039 supply dvdd-3v not found, using dummy regulator + i2c i2c-0: Added multiplexed i2c bus 2 + at24 3-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write + i2c i2c-0: Added multiplexed i2c bus 3 + pca953x 4-0021: 4-0021 supply vcc not found, using dummy regulator + i2c i2c-0: Added multiplexed i2c bus 4 + rtc-pcf8563 5-0051: registered as rtc0 + i2c i2c-0: Added multiplexed i2c bus 5 + at24 6-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write + i2c i2c-0: Added multiplexed i2c bus 6 + i2c i2c-0: Added multiplexed i2c bus 7 + i2c i2c-0: Added multiplexed i2c bus 8 + pca954x 0-0074: registered 8 multiplexed busses for I2C switch pca9548 + usbcore: registered new interface driver uvcvideo + USB Video Class driver (1.1.1) + gspca_main: v2.14.0 registered + cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s + Xilinx Zynq CpuIdle Driver started + failed to register cpuidle driver + sdhci: Secure Digital Host Controller Interface driver + sdhci: Copyright(c) Pierre Ossman + sdhci-pltfm: SDHCI platform and OF driver helper + mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA + ledtrig-cpu: registered to indicate activity on CPUs + hidraw: raw HID events driver (C) Jiri Kosina + usbcore: registered new interface driver usbhid + usbhid: USB HID core driver + mmc0: new high speed SDHC card at address aaaa + mmcblk0: mmc0:aaaa SC32G 29.7 GiB + jesd204: /amba/spi@e0007000/hmc7044@0,jesd204:1,parent=spi1.0: Using as SYSREF provider + mmcblk0: p1 p2 p3 + axi_adxcvr 44a60000.axi-adxcvr-rx: adxcvr_enforce_settings: Using QPLL without access, assuming desired Lane rate will be configured by a different instance + axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using QPLL on GTX2 at 0x44A60000. Number of lanes: 4. + axi_adxcvr 44b60000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using QPLL on GTX2 at 0x44B60000. Number of lanes: 4. + axi-jesd204-rx 44a90000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44A90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm. + axi-jesd204-tx 44b90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44B90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm. + axi_sysid 45000000.axi-sysid-0: AXI System ID core version (1.01.a) found + axi_sysid 45000000.axi-sysid-0: [ad9081_fmca_ebz] on [zc706] git branch git <1099badaf4f3621f9db1723a17d0dcd3dc74e26b> clean [2021-03-08 14:35:28] UTC + fpga_manager fpga0: Xilinx Zynq FPGA Manager registered + usbcore: registered new interface driver snd-usb-audio + NET: Registered protocol family 10 + Segment Routing with IPv6 + sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver + NET: Registered protocol family 17 + NET: Registered protocol family 36 + Registering SWP/SWPB emulation handler + [drm] Cannot find any crtc or sizes + [drm] Initialized axi_hdmi_drm 1.0.0 20120930 for 70e00000.axi_hdmi on minor 0 + ad9081 spi0.0: AD9081 Rev. 3 Grade 10 (API 1.1.0) probed + cf_axi_dds 44b10000.axi-ad9081-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44B10000 mapped to 0x(ptrval), probed DDS AD9081 + asoc-simple-card adv7511_hdmi_snd: spdif-hifi <-> 75c00000.axi-spdif-tx mapping ok + cf_axi_adc 44a10000.axi-ad9081-rx-hpc: ADI AIM (10.01.b) at 0x44A10000 mapped to 0x(ptrval), probed ADC AD9081 as MASTER + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition initialized -> probed + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition initialized -> probed + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition probed -> idle + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition probed -> idle + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition idle -> device_init + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition idle -> device_init + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition device_init -> link_init + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition device_init -> link_init + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition link_init -> link_supported + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition link_init -> link_supported + hmc7044 spi1.0: hmc7044_jesd204_link_pre_setup: Link2 forcing continuous SYSREF mode + hmc7044 spi1.0: hmc7044_jesd204_link_pre_setup: Link0 forcing continuous SYSREF mode + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition link_supported -> link_pre_setup + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition link_supported -> link_pre_setup + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition link_pre_setup -> clk_sync_stage1 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition link_pre_setup -> clk_sync_stage1 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2 + [drm] Cannot find any crtc or sizes + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3 + [drm] Cannot find any crtc or sizes + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition clk_sync_stage3 -> link_setup + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition clk_sync_stage3 -> link_setup + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition link_setup -> opt_setup_stage1 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition link_setup -> opt_setup_stage1 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition opt_setup_stage1 -> opt_setup_stage2 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition opt_setup_stage2 -> opt_setup_stage3 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition opt_setup_stage3 -> opt_setup_stage4 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition opt_setup_stage4 -> opt_setup_stage5 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5 + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition opt_setup_stage5 -> clocks_enable + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition opt_setup_stage5 -> clocks_enable + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition clocks_enable -> link_enable + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition clocks_enable -> link_enable + ad9081 spi0.0: JESD RX (JTX) Link2 in DATA, SYNC deasserted, PLL locked, PHASE established, MODE valid + ad9081 spi0.0: JESD TX (JRX) Link0 0xF lanes in DATA + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition link_enable -> link_running + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition link_enable -> link_running + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition link_running -> opt_post_running_stage + jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition link_running -> opt_post_running_stage + input: gpio_keys as /devices/soc0/gpio_keys/input/input0 + rtc-pcf8563 5-0051: setting system clock to 2021-03-19T15:24:20 UTC (1616167460) + clk: Not disabling unused clocks + ALSA device list: + #0: HDMI monitor + EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null) + VFS: Mounted root (ext4 filesystem) on device 179:2. + devtmpfs: mounted + Freeing unused kernel memory: 1024K + Run /sbin/init as init process + systemd[1]: Failed to lookup module alias 'autofs4': Function not implemented + systemd[1]: systemd 241 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN2 +IDN -PCRE2) + systemd[1]: Detected architecture arm. + + Welcome to Kuiper GNU/Linux 10 (buster)! + + systemd[1]: Set hostname to . + systemd[1]: File /lib/systemd/system/systemd-journald.service:12 configures an IP firewall (IPAddressDeny=any), but the local system does not support BPF/cgroup based firewalling. + systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.) + systemd[1]: /etc/systemd/system/tof-server.service:1: Assignment outside of section. Ignoring. + systemd[1]: /etc/systemd/system/tof-server.service:2: Assignment outside of section. Ignoring. + random: systemd: uninitialized urandom read (16 bytes read) + random: systemd: uninitialized urandom read (16 bytes read) + systemd[1]: Reached target Swap. + [ OK ] Reached target Swap. + random: systemd: uninitialized urandom read (16 bytes read) + systemd[1]: Started Forward Password Requests to Wall Directory Watch. + [ OK ] Started Forward Password R�…uests to Wall Directory Watch. + systemd[1]: Listening on Journal Socket (/dev/log). + [ OK ] Listening on Journal Socket (/dev/log). + [ OK ] Listening on Journal Socket. + Starting Set the console keyboard layout... + Starting Load Kernel Modules... + [ OK ] Created slice User and Session Slice. + [ OK ] Listening on Syslog Socket. + Mounting RPC Pipe File System... + [ OK ] Listening on udev Control Socket. + [ OK ] Created slice system-getty.slice. + [ OK ] Listening on fsck to fsckd communication Socket. + [ OK ] Created slice system-serial\x2dgetty.slice. + [ OK ] Created slice system-systemd\x2dfsck.slice. + Starting Restore / save the current clock... + [ OK ] Listening on udev Kernel Socket. + Starting udev Coldplug all Devices... + Starting Journal Service... + [ OK ] Listening on initctl Compatibility Named Pipe. + [ OK ] Reached target Slices. + Mounting Kernel Debug File System... + [FAILED] Failed to start Load Kernel Modules. + See 'systemctl status systemd-modules-load.service' for details. + [ OK ] Started Set the console keyboard layout. + [ OK ] Started Journal Service. + [FAILED] Failed to mount RPC Pipe File System. + See 'systemctl status run-rpc_pipefs.mount' for details. + [DEPEND] Dependency failed for RPC �…curity service for NFS server. + [DEPEND] Dependency failed for RPC �…ice for NFS client and server. + [ OK ] Started Restore / save the current clock. + [ OK ] Mounted Kernel Debug File System. + Starting Remount Root and Kernel File Systems... + [ OK ] Reached target NFS client services. + [ OK ] Reached target Remote File Systems (Pre). + [ OK ] Reached target Remote File Systems. + Mounting Kernel Configuration File System..random: crng init done + random: 7 urandom warning(s) missed due to ratelimiting + . + Starting Apply Kernel Variables... + [ OK ] Mounted Kernel Configuration File System. + [ OK ] Started udev Coldplug all Devices. + [ OK ] Started Apply Kernel Variables. + Starting Helper to synchronize boot up for ifupdown... + [ OK ] Started Helper to synchronize boot up for ifupdown. + [ OK ] Started Remount Root and Kernel File Systems. + Starting Create System Users... + Starting Flush Journal to Persistent Storage... + Starting Load/Save Random Seed... + [ OK ] Started Create System Users. + [ OK ] Started Load/Save Random Seed. + Starting Create Static Device Nodes in /dev... + [ OK ] Started Flush Journal to Persistent Storage. + [ OK ] Started Create Static Device Nodes in /dev. + Starting udev Kernel Device Manager... + [ OK ] Reached target Local File Systems (Pre). + [ OK ] Started udev Kernel Device Manager. + Starting Show Plymouth Boot Screen... + [ OK ] Started Show Plymouth Boot Screen. + [ OK ] Reached target Local Encrypted Volumes. + [ OK ] Started Forward Password R�…s to Plymouth Directory Watch. + Starting Load Kernel Modules... + [ OK ] Found device /dev/ttyPS0. + [FAILED] Failed to start Load Kernel Modules. + See 'systemctl status systemd-modules-load.service' for details. + [ OK ] Found device /dev/disk/by-partuuid/18f1f9d5-01. + Starting File System Check�…isk/by-partuuid/18f1f9d5-01... + [ OK ] Started File System Check Daemon to report status. + [ OK ] Started File System Check �…/disk/by-partuuid/18f1f9d5-01. + Mounting /boot... + [ OK ] Mounted /boot. + [ OK ] Reached target Local File Systems. + Starting Raise network interfaces... + Starting Tell Plymouth To Write Out Runtime Data... + Starting Set console font and keymap... + Starting Create Volatile Files and Directories... + Starting Preprocess NFS configuration... + [ OK ] Started Tell Plymouth To Write Out Runtime Data. + [ OK ] Started Preprocess NFS configuration. + [ OK ] Started Set console font and keymap. + [ OK ] Started Create Volatile Files and Directories. + Starting Update UTMP about System Boot/Shutdown... + Starting Network Time Synchronization... + [ OK ] Started Update UTMP about System Boot/Shutdown. + Starting Load Kernel Modules... + Starting Tell Plymouth To Write Out Runtime Data... + [ OK ] Started Network Time Synchronization. + [ OK ] Started Raise network interfaces. + [ OK ] Started Tell Plymouth To Write Out Runtime Data. + [FAILED] Failed to start Load Kernel Modules. + See 'systemctl status systemd-modules-load.service' for details. + [ OK ] Reached target System Time Synchronized. + [ OK ] Reached target System Initialization. + [ OK ] Listening on D-Bus System Message Bus Socket. + [ OK ] Started Daily rotation of log files. + [ OK ] Started Daily apt download activities. + [ OK ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket. + [ OK ] Listening on triggerhappy.socket. + [ OK ] Listening on GPS (Global P�…ioning System) Daemon Sockets. + [ OK ] Listening on CUPS Scheduler. + [ OK ] Reached target Sockets. + [ OK ] Started Daily Cleanup of Temporary Directories. + [ OK ] Started Daily man-db regeneration. + [ OK ] Started Daily apt upgrade and clean activities. + [ OK ] Reached target Timers. + [ OK ] Started CUPS Scheduler. + [ OK ] Reached target Paths. + [ OK ] Reached target Basic System. + [ OK ] Started D-Bus System Message Bus. + [ OK ] Started tof-server.service. + Starting Avahi mDNS/DNS-SD Stack... + Starting rng-tools.service... + Starting dhcpcd on all interfaces... + Starting WPA supplicant... + Starting Login Service... + [ OK ] Started Regular background program processing daemon. + [ OK ] Started CUPS Scheduler. + [ OK ] Started Manage Sound Card State (restore and store). + Starting LSB: Switch to on�…nless shift key is pressed)... + Starting System Logging Service... + Starting Check for Raspberry Pi EEPROM updates... + Starting Disk Manager... + Starting Save/Restore Sound Card State... + Starting dphys-swapfile - �…unt, and delete a swap file... + Starting triggerhappy global hotkey daemon... + Starting Modem Manager... + [ OK ] Started System Logging Service. + [ OK ] Started triggerhappy global hotkey daemon. + [FAILED] Failed to start rng-tools.service. + See 'systemctl status rng-tools.service' for details. + [ OK ] Started dhcpcd on all interfaces. + [ OK ] Started Check for Raspberry Pi EEPROM updates. + [ OK ] Started Save/Restore Sound Card State. + [ OK ] Reached target Sound Card. + [ OK ] Started Login Service. + [ OK ] Started Avahi mDNS/DNS-SD Stack. + [ OK ] Started WPA supplicant. + Starting Authorization Manager... + [ OK ] Reached target Network. + Starting OpenBSD Secure Shell server... + Starting Permit User Sessions... + Starting HTTP based time synchronization tool... + Starting /etc/rc.local Compatibility... + [ OK ] Started IIO Daemon. + [ OK ] Started Make remote CUPS printers available locally. + [ OK ] Started LSB: Switch to ond�…(unless shift key is pressed). + [ OK ] Started HTTP based time synchronization tool. + [ OK ] Started Permit User Sessions. + [ OK ] Started /etc/rc.local Compatibility. + [ OK ] Started dphys-swapfile - s�…mount, and delete a swap file. + Starting Light Display Manager... + Starting Hold until boot process finishes up... + [ OK ] Started Authorization Manager. + [ OK ] Started OpenBSD Secure Shell server. + [ OK ] Started Modem Manager. + + Raspbian GNU/Linux 10 analog ttyPS0 + + analog login: root (automatic login) + + Last login: Fri Mar 19 15:23:10 GMT 2021 on ttyPS0 + Linux analog 5.4.0-93252-ga4800dc5737b #2881 SMP PREEMPT Fri Mar 19 16:22:37 CET 2021 armv7l + + The programs included with the Debian GNU/Linux system are free software; + the exact distribution terms for each program are described in the + individual files in /usr/share/doc/*/copyright. + + Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent + permitted by applicable law. + root@analog:~# + +Useful commands for the serial terminal +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The below commands are to be run in the serial terminal connected to the FPGA. + +**Login Information** + +user: analog +password: analog + +To find out the IP of the FPGA board, run the following command and take the +IP specified at "eth0 inet": + +.. shell:: + + $ifconfig + +To see the IIO devices detected, run: + +.. shell:: + + $iio_info | grep iio:device + iio:device0: xadc + iio:device1: hmc7044 + iio:device2: axi-ad9081-tx-hpc (buffer capable) + iio:device3: axi-ad9081-rx-hpc (buffer capable) + +To see the EEPROM specifications, run: + +.. shell:: + + $fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom + +To use the :dokuwiki:`JESD204 status utility `, +run: + +.. shell:: + + $jesd_status + +All links should be in DATA without errors: + +.. shell:: + + $jesd_status -s + (DEVICES) Found 2 JESD204 Link Layer peripherals + + (0): axi-jesd204-rx/44a90000.axi-jesd204-rx [*] + (1): axi-jesd204-tx/44b90000.axi-jesd204-tx + + (STATUS) + Link is enabled + Link Status + Measured Link Clock 250.003 + Reported Link Clock 250.000 + Lane rate + Lane rate / 40 + LMFC rate + SYSREF captured + SYSREF alignment error + SYNC~ + + (LANE STATUS) + Lane# 0 1 2 3 + Errors 1 0 0 1 + Latency (Multiframes/Octets) 1/33 1/34 1/32 1/32 + CGS State DATA DATA DATA DATA + Initial Frame Sync Yes Yes Yes Yes + Initial Lane Alignment Sequence Yes Yes Yes Yes + + F1axi-jesd204-rx/44a90000.axi-jesd204-rxF2axi-jesd204-tx/44b90000.axi-jesd204-txF9Quit + +Additionally, if running ``stty rows 30`` before running ``jesd_status``, you +can expand the visible area of it and see more than 4 lanes. + +To power off the system, run the following command, and wait for the final +message to be printed, then power off the FPGA board from the switch as well. + +.. shell:: + + $poweroff + +To reboot the system, run: + +.. shell:: + + $reboot + +.. important:: + + Even thought this is Linux, this is a persistent file systems. Care should + be taken not to corrupt the file system -- please shut down things, don't + just turn off the power switch. Depending on your monitor, the standard + power off could be hiding. You can do this from the terminal as well with + :code:`sudo shutdown -h now` or the above-mentioned command for powering + off. + +.. include:: ../../common/using-iio-osc.rst + +.. + About the IIO devices + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + TBD + +Using no-OS as software +------------------------------------------------------------------------------- + +Necessary files +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following files are needed for the system to boot: + +- HDL boot file: ``system_top.xsa`` +- no-OS project: :git-no-os:`projects/ad9081` + +Instructions on how to build the boot files from source can be found here: + +- :external+no-OS:doc:`projects/adc/ad9081`. More no-OS build + details at :external+no-OS:doc:`build_guide`. +- :external+hdl:ref:`ad9081_fmca_ebz`. More HDL build details at + :external+hdl:ref:`build_hdl`. + +Required Software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx Vivado and Vitis (downloading Vitis from + `here `_ + will include Vivado as well) +- An UART terminal (Putty/Tera Term/Minicom, etc.), Baud rate 115200 (8N1) + +Required Hardware +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx :xilinx:`ZC706` Rev 1.2 or higher FPGA board and its power supply +- :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC evaluation board +- 2x Micro-USB cables, one for UART and one for JTAG +- (Optional) USB keyboard & mouse and a HDMI-compatible monitor + +More details as to why you need these, can be found at +:ref:`ad9081 prerequisites`. + +Testing +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Creating the setup +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ../../images/ad9081-fmca-ebz-zc706.png + :width: 800 + +Follow the steps in this order, to avoid damaging the components: + +#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the ZC706 + **HPC** FMC socket +#. Configure :xilinx:`ZC706`` for SD card boot mode (Set the jumpers: + The main one is: SW11 - Big Blue Switch in the middle, which controls the + Boot Mode, it needs to be set: **1: Up, 2: Up, 3: Up, 4: Up, 5: Down**. +#. Connect USB UART (Mini-USB) to your host PC +#. Connect USB JTAG (Mini-USB) to your host PC +#. Turn on the power switch on the FPGA board +#. Observe console output messages on your terminal (use the first ttyUSB or + COM port registered) + +Console output +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following is what is printed in the serial console, after you have +connected to the proper ttyUSB or COM port: + +.. collapsible:: Complete boot log + + :: + + Xilinx Zynq First Stage Boot Loader + +.. + TBD + +.. include:: ../../common/using-iio-osc.rst diff --git a/docs/solutions/reference-designs/eval-ad9081/quickstart/zynqmp.rst b/docs/solutions/reference-designs/eval-ad9081/quickstart/zcu102.rst similarity index 99% rename from docs/solutions/reference-designs/eval-ad9081/quickstart/zynqmp.rst rename to docs/solutions/reference-designs/eval-ad9081/quickstart/zcu102.rst index 155d99874..98c5cdfc6 100644 --- a/docs/solutions/reference-designs/eval-ad9081/quickstart/zynqmp.rst +++ b/docs/solutions/reference-designs/eval-ad9081/quickstart/zcu102.rst @@ -1,16 +1,18 @@ -.. _ad9081 quickstart zynqmp: +.. _ad9081 quickstart zcu102: ZCU102 Quick start =============================================================================== -.. image:: ../../images/ad9081_zcu102_setup.png - :width: 800 - This guide provides quick instructions on how to setup the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` on: - :xilinx:`ZCU102` FMC HPC0 +.. image:: ../../images/zcu102.jpg + :width: 900 + +.. esd-warning:: + Using Linux as software ------------------------------------------------------------------------------- @@ -32,8 +34,8 @@ Instructions on how to manually build the boot files from source can be found here: - :ref:`linux-kernel zynqmp` -- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build details at - :external+hdl:ref:`build_hdl`. +- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build + details at :external+hdl:ref:`build_hdl`. Required Software ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -62,11 +64,8 @@ Testing Creating the setup ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. image:: ../../images/zcu102.jpg - :width: 900 - -.. esd-warning:: - +.. image:: ../../images/ad9081_zcu102_setup.png + :width: 800 In the following example, we will make a physical loopback between the ADC and the DAC channels on the evaluation board, using SMA cables. @@ -74,11 +73,15 @@ and the DAC channels on the evaluation board, using SMA cables. Follow the steps in this order, to avoid damaging the components: #. Connect the SMA cables ADC0-DAC0, ADC1-DAC1, ADC2-DAC2, ADC3-DAC3 -#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the - FPGA carrier **HPC1** FMC1 socket +#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the ZCU102 + **HPC1** FMC1 socket #. Insert SD card into the SD card socket on the FPGA #. Configure :xilinx:`ZCU102` for SD card boot mode (mode SW6[4:1] switch in the position **OFF,OFF,OFF,ON** as seen in the below picture) + + .. image:: ../../images/zcu102_1p0_bootmode.jpg + :width: 400 + #. Plug-in an Ethernet cable from your router/switch to the Ethernet port on the FPGA board #. Connect USB UART J83 (Micro USB) to your host PC @@ -88,9 +91,6 @@ Follow the steps in this order, to avoid damaging the components: #. Observe Kernel and serial console output messages on your terminal (use the first ttyUSB or COM port registered) -.. image:: ../../images/zcu102_1p0_bootmode.jpg - :width: 400 - Boot messages ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1012,14 +1012,16 @@ To reboot the system, run: be taken not to corrupt the file system -- please shut down things, don't just turn off the power switch. Depending on your monitor, the standard power off could be hiding. You can do this from the terminal as well with - :code:`sudo shutdown -h now` or the above-mentioned command for powering off. + :code:`sudo shutdown -h now` or the above-mentioned command for powering + off. .. include:: ../../common/using-iio-osc.rst About the IIO devices ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Main receivers RX1, RX2, RX3, and RX4 are handled by the axi-ad9081-rx-hpc IIO device. +Main receivers RX1, RX2, RX3, and RX4 are handled by the axi-ad9081-rx-hpc IIO +device. Channels: @@ -1074,19 +1076,17 @@ Testing Creating the setup ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. image:: ../../images/zcu102.jpg - :width: 900 - -.. esd-warning:: +.. image:: ../../images/ad9081_zcu102_setup.png + :width: 800 Follow the steps in this order, to avoid damaging the components: -#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the - FPGA carrier **HPC1** FMC1 socket +#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the ZCU102 + **HPC1** FMC1 socket #. Configure :xilinx:`ZCU102` for JTAG boot mode (mode SW6[4:1] switch in the position **ON,ON,ON,ON**) #. Connect USB UART J83 (Micro USB) to your host PC -#. Connecy USB JTAG (Micro USB) to your host PC +#. Connect USB JTAG (Micro USB) to your host PC #. (Optional) Connect a monitor to the FPGA by HDMI, and a mouse and a keyboard #. Turn on the power switch on the FPGA board #. Observe console output messages on your terminal (use the first ttyUSB or @@ -1103,3 +1103,8 @@ connected to the proper ttyUSB or COM port: :: Xilinx Zynq MP First Stage Boot Loader + +.. + TBD + +.. include:: ../../common/using-iio-osc.rst diff --git a/docs/solutions/reference-designs/images/ad9081-fmca-ebz-zc706.png b/docs/solutions/reference-designs/images/ad9081-fmca-ebz-zc706.png new file mode 100644 index 000000000..871f7a55e --- /dev/null +++ b/docs/solutions/reference-designs/images/ad9081-fmca-ebz-zc706.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:a3d5f688eeb3e64cf11d02aa12ebd9daa8afecd4bb2693949cee26a608b8b323 +size 353988 diff --git a/docs/solutions/reference-designs/images/ad9081_vcu118_setup.png b/docs/solutions/reference-designs/images/ad9081_vcu118_setup.png new file mode 100644 index 000000000..363385beb --- /dev/null +++ b/docs/solutions/reference-designs/images/ad9081_vcu118_setup.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4e17f854b6025cc3aa315979c48fb303fa278eb1273ff208835b67e4c6f60ec7 +size 338059 diff --git a/docs/solutions/reference-designs/images/vcu118.png b/docs/solutions/reference-designs/images/vcu118.png new file mode 100644 index 000000000..d3e280a70 --- /dev/null +++ b/docs/solutions/reference-designs/images/vcu118.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f1fa6c7c06b2065d2c837e876c1096360cb72d0b49bc1c29c576b9277242972e +size 461345 diff --git a/docs/solutions/reference-designs/images/zc706.png b/docs/solutions/reference-designs/images/zc706.png new file mode 100644 index 000000000..519dff1f0 --- /dev/null +++ b/docs/solutions/reference-designs/images/zc706.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:de5d78dc194d506299a62d62a10f4a9a66852c9a3b937e004535abacceb87224 +size 303508