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index 000000000..0d3cb09b3
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+oid sha256:9ca7154cf8ccca98d8c5a856db59196ed77ccbe24d33274172e299f4504382c3
+size 282089
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new file mode 100644
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diff --git a/docs/learning/demo_hp_analog_meets_ai/demo_block_diagram.svg b/docs/learning/demo_hp_analog_meets_ai/demo_block_diagram.svg
new file mode 100644
index 000000000..7e3eb0b87
--- /dev/null
+++ b/docs/learning/demo_hp_analog_meets_ai/demo_block_diagram.svg
@@ -0,0 +1,532 @@
+
+
+
+
diff --git a/docs/learning/demo_hp_analog_meets_ai/demo_description.svg b/docs/learning/demo_hp_analog_meets_ai/demo_description.svg
new file mode 100644
index 000000000..c963dc36c
--- /dev/null
+++ b/docs/learning/demo_hp_analog_meets_ai/demo_description.svg
@@ -0,0 +1 @@
+
\ No newline at end of file
diff --git a/docs/learning/demo_hp_analog_meets_ai/index.rst b/docs/learning/demo_hp_analog_meets_ai/index.rst
new file mode 100644
index 000000000..6096e643c
--- /dev/null
+++ b/docs/learning/demo_hp_analog_meets_ai/index.rst
@@ -0,0 +1,198 @@
+DEMO High-Performance Analog Meets AI
+===============================================================================
+
+Extracting data from high-performance, high-data-rate analog signal chains for
+AI model training and real-time inference presents significant challenges due to
+the complexity of interfaces, processing, and integration requirements. Analog
+Devices addresses these challenges by providing a comprehensive, open-source
+data extraction and integration software stack, which ensures seamless
+connectivity between advanced signal chains and high-performance compute
+platforms.
+
+Resources
+-------------------------------------------------------------------------------
+
+- HDL branch: :git-hdl:`adrv9009_qsfp_10G `
+- Linux branch: :git-linux:`adr9009zu11eg_100MHZ_qsfp `
+- Corundum branch: `corundum `__
+- PyADI-IIO branch: :git-pyadi-iio:`jupiter_modulation `
+
+Block diagram
+-------------------------------------------------------------------------------
+
+.. figure:: demo_block_diagram.svg
+ :align: center
+ :width: 900
+
+Demo description
+-------------------------------------------------------------------------------
+
+This demo illustrates an AI-based multi-channel RF modulation scheme recognition
+workflow for signal intelligence applications. Four AD-JUPITER-EBZ systems are
+used to generate RF signals with different modulation schemes across a total of
+eight channels. The signals are then digitized by two ADRV9009-ZU11EG SoMs,
+which stream the raw IQ data to a host PC via 10Gb Ethernet links. The AI model,
+derived from a MathWorks reference design, is deployed on the NVIDIA GPU hosted
+in the PC. The NVIDIA Holoscan AI infrastructure manages the efficient transfer
+of data from the network interfaces into GPU memory, where the AI model is
+executed. By combining ADI’s high-performance data extraction infrastructure
+with MathWorks development tools and NVIDIA deployment frameworks, the system
+enables efficient AI application development and real-time execution for
+advanced signal intelligence tasks.
+
+.. figure:: demo_description.svg
+ :align: center
+ :width: 600
+
+System Capabilities
+-------------------------------------------------------------------------------
+
+The system demonstrates an advanced, end-to-end data extraction and AI-based
+signal processing workflow designed for high-performance signal intelligence
+applications. It combines Analog Devices’ high-speed RF hardware and data
+infrastructure with third-party AI frameworks to deliver real-time modulation
+recognition and efficient AI model development.
+
+Key capabilities include:
+
+#. High-Performance Data Extraction
+
+ * Supports real-time acquisition of high-bandwidth RF data from multi-channel
+ signal chains.
+ * Seamlessly bridges physical interfaces, FPGA-based logic, and low-level
+ software drivers to enable reliable data transfer from ADI RF front ends to
+ edge processors.
+ * Flexible connectivity options, including Ethernet, PCIe, USB, and UART,
+ allow integration with a wide range of compute platforms.
+
+#. Real-Time AI Modulation Recognition
+
+ * Demonstrates multi-channel RF modulation scheme classification using AI
+ models deployed on NVIDIA GPUs.
+ * The NVIDIA Holoscan AI infrastructure ensures efficient data movement
+ between network interfaces and GPU memory, supporting low-latency
+ inference.
+
+#. Multi-Channel & Multi-Device Synchronization
+
+ * Incorporates multiple AD-JUPITER-EBZ boards and ADRV9009-ZU11EG SoMs to
+ generate and digitize RF signals across eight channels.
+ * Provides accurate clock distribution and synchronization through
+ AD-SYNCHRONA14-EBZ, ensuring deterministic latency and coherent signal
+ processing across multiple systems.
+
+#. Seamless Data Integration Stack
+
+ * Enables flexible partitioning of data flow between edge and host compute
+ devices, improving scalability and system optimization.
+ * Utilizes an open-source ADI software stack that simplifies the setup of
+ data collection pipelines for AI model training and real-time inference.
+
+#. Integration with Industry-Standard AI Frameworks
+
+ * Compatible with MathWorks reference designs for AI model generation,
+ MATLAB-based workflows, NVIDIA Holoscan, and ROS2.
+ * Bridges data science workflows with embedded environments to enable
+ real-world dataset generation, model optimization, and deployment.
+
+#. End-to-End AI Development Ecosystem
+
+ * ADI’s AI Fusion tools within CodeFusion Studio™ enable model optimization,
+ deployment, and real-time performance analysis.
+ * Supports rapid development cycles by providing actionable insights and
+ performance metrics for system tuning.
+
+Required Hardware
+-------------------------------------------------------------------------------
+
+The following hardware components are required to set up and run the
+multi-channel RF modulation recognition demo:
+
+.. list-table::
+ :widths: 15 30 5 15
+ :header-rows: 1
+
+ * - Component
+ - Role
+ - Quantity
+ - Notes
+ * - :dokuwiki:`Jupiter SDR `
+ - Versatile 2 x RxTx software-defined-radio platform based on ADRV9002 and
+ Xilinx Zynq UltraScale+ MPSoC. Generates RF signals with configurable
+ modulation schemes.
+ - 4
+ - Used to generate 8-channel RF input for AI recognition.
+ * - :dokuwiki:`ADRV9009-ZU11EG RF-SOM
+ `
+ - RF System-on-Module with dual ADRV9009 wideband transceivers. Performs
+ high-speed digitization and streaming of IQ data to the host.
+ - 2
+ - Provides synchronized multi-channel data acquisition.
+ * - :dokuwiki:`AD-SYNCHRONA14-EBZ
+ `
+ - Clock synchronization and distribution board based on AD9545 and HMC7044.
+ Ensures accurate multi-channel phase alignment.
+ - 1
+ - Synchronizes all RF signal paths and data capture timing.
+ * - NVIDIA IGX Orin platform
+ - High-performance computing system with NVIDIA GPU acceleration. Runs
+ Holoscan AI infrastructure and the AI modulation recognition model.
+ - 1
+ - Requires 10Gb Ethernet connectivity.
+ * - SMA Cables
+ - RF connection between the SDR transmit and receive channels.
+ - 8
+ - High-quality coaxial cables recommended for minimal signal loss.
+ * - 100G QSFP28 Active Optical Cable
+ - Provides high-speed data connection between the RF-SOM and the host
+ compute platform.
+ - 1
+ - Supports low-latency, high-bandwidth Ethernet link.
+ * - Network switch with at least 4 PoE ports
+ - Provides Ethernet connectivity and power delivery to connected devices.
+ - 1
+ - Use a managed switch compatible with 10GbE interfaces.
+
+SD Card Configuration
+-------------------------------------------------------------------------------
+
+- For the Jupiter SDR platform, the boot files are generated using the Using
+ Kuiper Image:
+
+ :external+adi-kuiper-gen:ref:`Writing the Image to an SD Card
+ `
+
+- For the ADRV9009-ZU11EG, begin by checking out the HDL branch, then navigate
+ to the **adrv2crr_fmc** directory.
+
+Run the following command to enable Corundum support and build the design:
+**make CORUNDUM=1** Once the build process is complete, generate the necessary
+boot files: boot.bin, device tree, and uImage by following the steps:
+
+- BOOT.BIN: :external+hdl:ref:`Build the boot image BOOT.BIN `
+- Devicetree: :dokuwiki:`Building the Zynq Linux kernel and devicetrees from
+ source `
+
+Capture in Data Using Scopy2.0
+-------------------------------------------------------------------------------
+
+Captured RF Signal in Time Domain
+
+.. figure:: capture_time.jpg
+ :align: center
+ :width: 900
+
+Captured RF Signal in Frequency Domain
+
+.. figure:: capture_frequency.jpg
+ :align: center
+ :width: 900
+
+AI Modulation Detection Applications
+-------------------------------------------------------------------------------
+
+.. toctree::
+ :caption: The following applications are available:
+ :maxdepth: 1
+
+ software/index
diff --git a/docs/learning/demo_hp_analog_meets_ai/software/index.rst b/docs/learning/demo_hp_analog_meets_ai/software/index.rst
new file mode 100644
index 000000000..dd4cd5ab6
--- /dev/null
+++ b/docs/learning/demo_hp_analog_meets_ai/software/index.rst
@@ -0,0 +1,241 @@
+Software Configuration and Setup
+=================================
+
+This section provides guidance on configuring and running the software
+components of the High-Performance Analog Meets AI demonstration.
+
+Overview
+--------
+
+The demonstration consists of two main software components:
+
+1. **Holoscan Modulation Classification Application** - A real-time AI-powered
+ modulation classification system built with NVIDIA Holoscan SDK
+2. **Data Visualization Dashboard** - A Python-based Dash application for
+ monitoring and analyzing classification results
+
+Holoscan Modulation Classification Application
+----------------------------------------------
+
+Description
+~~~~~~~~~~~
+
+This application performs real-time modulation classification on incoming data
+using MATLAB-generated CUDA code. It processes signals from ADRV9009 devices and
+classifies them into one of eight modulation schemes:
+
+- BPSK (Binary Phase Shift Keying)
+- QPSK (Quadrature Phase Shift Keying)
+- 8PSK (8-Phase Shift Keying)
+- 16QAM (16-Quadrature Amplitude Modulation)
+- 64QAM (64-Quadrature Amplitude Modulation)
+- PAM4 (4-Pulse Amplitude Modulation)
+- GFSK (Gaussian Frequency Shift Keying)
+- CPFSK (Continuous Phase Frequency Shift Keying)
+
+Key Components
+~~~~~~~~~~~~~~
+
+**Holohub application**: The Holohub application and IIO operators
+ - Example applications:
+ https://github.com/nvidia-holoscan/holohub/tree/main/applications/iio
+ - Generic operators:
+ https://github.com/nvidia-holoscan/holohub/tree/main/operators/iio_controller
+
+There are 5 operators (each with its own Python binding) that can read/write IIO
+attributes, read/write IIO buffers and configure the initial setup for a
+device/system. This demonstration uses the buffer read operator in order to read
+from the 2 ADRV9009 devices. After that, the matlab module (that needs to be
+compiled beforehand) will call the classification function that returns the
+modulation and confidence level. This will be printed to the output file from
+where the python dash app will read and display the information.
+
+Configuration
+~~~~~~~~~~~~~
+
+1. **Network Configuration**
+
+ Update IP addresses in main.cpp for your ADRV9009 devices:
+
+ .. code-block:: cpp
+
+ // Configure IIO buffer read for Talise device at IP 10.43.1.10 auto
+ iio_rx_1 = make_operator("iio_rx_1",
+ Arg("ctx") =
+ std::string("ip:10.43.1.10"), Arg("dev")
+ = std::string("axi-adrv9009-rx-hpc"), //
+ ... other parameters
+
+2. **Output Configuration**
+
+ Modify the YAML file to set output file paths:
+
+ .. code-block:: yaml
+
+ matlab:
+ out_file: "modulation_results.txt"
+
+3. **Channel Configuration**
+
+ The application is configured for 8 channels (4 I/Q pairs):
+
+ .. code-block:: cpp
+
+ std::vector channel_names = {
+ "voltage0_i", "voltage0_q", "voltage1_i", "voltage1_q", "voltage2_i",
+ "voltage2_q", "voltage3_i", "voltage3_q"
+ };
+
+Building and Running
+~~~~~~~~~~~~~~~~~~~~
+
+1. **Build the Application**
+
+ .. shell::
+
+ ~/holohub $build iio
+
+2. **Run the Application**
+
+ .. shell::
+
+ ~/holohub $run iio
+
+The application will:
+
+- Connect to the specified ADRV9009 devices
+- Continuously read data samples (8192 samples per buffer, but it is
+ configurable from the code)
+- Process data through the MATLAB classification model
+- Output results to ``modulation_results.txt`` and ``modulation_results1.txt``
+
+Data Visualization Dashboard
+----------------------------
+
+Location
+~~~~~~~~
+
+The visualization script is located at:
+:git-pyadi-iio:`raw+afpop:jupiter_modulation/examples/plot_identification_data.py`
+
+Description
+~~~~~~~~~~~
+
+This Python application provides a web-based dashboard for monitoring and
+analyzing the modulation classification results in real-time. It features:
+
+- Real-time confusion matrices
+- Constellation diagrams
+- Time-domain waveform plots
+- Classification accuracy metrics
+- Interactive modulation selection
+
+Key Features
+~~~~~~~~~~~~
+
+**Real-time Monitoring**
+ - Reads results from Holoscan output files every 3 seconds
+ - Updates visualizations dynamically
+ - Tracks classification performance over time
+
+**Modulation Control**
+ - Manual modulation selection or automatic random switching
+ - Real-time transmission to connected SDR devices
+ - Supports all 8 modulation schemes
+
+**Signal Visualization**
+ - Constellation diagrams showing I/Q relationships
+ - Time-domain waveforms (I and Q components)
+ - Interactive plots with hover information
+
+Prerequisites
+~~~~~~~~~~~~~
+
+Install required Python packages:
+
+.. shell::
+
+ $pip3 install dash plotly pandas scipy scikit-learn numpy pyadi-iio
+
+Hardware Requirements
+~~~~~~~~~~~~~~~~~~~~~
+
+The dashboard expects the following hardware setup:
+
+- **4 ADRV9002 devices** for signal transmission (IPs: 192.168.0.15-18)
+- **2 ADRV9009ZU11eg devices** for signal reception (configured in Holoscan app)
+- **Modulated data files** in ``modulated_data/`` directory
+
+Configuration
+~~~~~~~~~~~~~
+
+1. **File Paths**
+
+ Update file paths to match your Holoscan output location:
+
+ .. code-block:: python
+
+ file_path =
+ '/home/analog/git/holohub/build/matlab_classify_modulator/modulation_results.txt'
+ file_path1 =
+ '/home/analog/git/holohub/build/matlab_classify_modulator/modulation_results1.txt'
+
+2. **SDR Configuration**
+
+ Configure SDR devices with appropriate IP addresses and stream profiles:
+
+ .. code-block:: python
+
+ sdr = adi.adrv9002(uri="ip:192.168.0.15")
+ sdr.write_stream_profile("lte_40_lvds_api_68_14_10.stream",
+ "lte_40_lvds_api_68_14_10.json")
+
+3. **Modulated Data**
+
+ Ensure modulated data files are available in the ``modulated_data/``
+ directory:
+
+ - mod_BPSK.mat
+ - mod_QPSK.mat
+ - mod_8PSK.mat
+ - mod_16QAM.mat
+ - mod_64QAM.mat
+ - mod_PAM4.mat
+ - mod_GFSK.mat
+ - mod_CPFSK.mat
+
+Running the Dashboard
+~~~~~~~~~~~~~~~~~~~~~
+
+1. **Start the Holoscan Application**
+
+ Ensure the Holoscan modulation classification application is running and
+ generating output files.
+
+2. **Launch the Dashboard**
+
+ .. shell::
+
+ $python3 plot_identification_data.py
+
+3. **Access the Web Interface**
+
+ Open a web browser and navigate to ``http://localhost:8050``
+
+Usage Workflow
+~~~~~~~~~~~~~~
+
+1. **Select Modulation**: Use the dropdown to choose a specific modulation or
+ select "Random" for automatic switching
+2. **Monitor Classification**: Observe real-time classification results for both
+ ADRV9009 devices
+3. **Analyze Performance**: Review confusion matrices and accuracy metrics
+4. **Examine Signals**: Study constellation diagrams and time-domain waveforms
+
+Support and Resources
+---------------------
+
+For additional support and documentation:
+
+- **Holoscan SDK Documentation**: https://docs.nvidia.com/holoscan/
+- **PyADI-IIO Documentation**: :external+pyadi-iio:doc:`index`
diff --git a/docs/learning/index.rst b/docs/learning/index.rst
index 41cef5d36..f5726634a 100644
--- a/docs/learning/index.rst
+++ b/docs/learning/index.rst
@@ -4,6 +4,8 @@ Learning! Tutorials, Workshops, Etc
.. toctree::
:maxdepth: 4
+ demo_hp_analog_meets_ai/index
+
Mixed Signal Basics
-------------------------------------------------------------------------------
@@ -63,7 +65,6 @@ Workshops
workshop_a_precision_converter_fpga_integration_journey/index
-
Academic Workshops
-------------------------------------------------------------------------------
diff --git a/docs/learning/workshop_what_sw_for_sdr/index.rst b/docs/learning/workshop_what_sw_for_sdr/index.rst
index c83d46434..7d9218c3c 100644
--- a/docs/learning/workshop_what_sw_for_sdr/index.rst
+++ b/docs/learning/workshop_what_sw_for_sdr/index.rst
@@ -12,8 +12,8 @@ FTC2024 Jupiter Workshop
- Jupiter SD Card image is available `here `__
- Documentation is available `here `__ (PPT, lab instructions and exercises)
-
-Introduction
-------------
-Future home of this workshop:
-WIP
+FTC2025 Pluto Workshop
+-----------------------------------------------------------------------------
+- Title: Software hands-on training kit: Getting started with SDR using ADALM-PLUTO
+- RPi5 SD Card image with Kuiper v2.0 available `here `__
+- Documentation is available `here `__ (PPT, lab instructions and exercises)
diff --git a/docs/products/adsp/index.rst b/docs/products/adsp/index.rst
index 1aae11a2b..0920b0e18 100644
--- a/docs/products/adsp/index.rst
+++ b/docs/products/adsp/index.rst
@@ -66,6 +66,8 @@ and coordinated with the community during weekly public office hours at 17:00 CE
on Thursdays using a
`Jitsi meeting `__.
+To set up new ADSP evaluation boards see :ref:`Getting Started `.
+
Upstream forks
--------------
@@ -112,3 +114,5 @@ ADI repositories
:git-adsp-ldr:`v1.0.2 `
- :git-lnxdsp-repo-manifest:`+`
- :git-br2-external:`+`
+ - v2025.05:
+ :git-br2-external:`Release 0.1.0 `
diff --git a/docs/products/adsp/setup.rst b/docs/products/adsp/setup.rst
index 1777ec601..81b264c9b 100644
--- a/docs/products/adsp/setup.rst
+++ b/docs/products/adsp/setup.rst
@@ -8,6 +8,12 @@ do not support booting directly from SD cards. Therefore the evaluation boards
need to be bootstrapped over JTAG using a :adi:`ADI ICE-1000 or ICE-2000 JTAG
debugger `.
+Download a binary release
+-------------------------
+
+Navigate to the :git-br2-external:`br2-external releases page ` and
+download the appropriate `images-*.tar.xz` release archive.
+
Setup a JTAG connection
-----------------------
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diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/Zoom_hot_input3.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/Zoom_hot_input3.png
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diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/index.rst b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/index.rst
new file mode 100644
index 000000000..9e1e8942b
--- /dev/null
+++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/index.rst
@@ -0,0 +1,164 @@
+.. _ethernet-apl-considerations:
+
+Ethernet-APL Considerations
+===========================
+
+Surge Protection
+----------------
+
+Ethernet-APL specifications requires the use of 25A surge protection
+devices to avoid damage due to fast transients. To fulfill this
+requiremnts a 25A TVS diode is needed. Due to the parasitic
+capacitance of this component (D3), it is important to implement a
+low capacitance diodes bridge (D26 to D29) to minimize the TVS diode
+capacitance to gurantee proper Ethernet communication.
+
+In addition, due to the voltage generated by the TVS diode, it is
+important to protect the ADIN1110 Tx pins. To achieve this
+requirement, a second pair of TVS diodes (D15 and D16) has been
+included in these pins.
+
+Power-up Requirements
+---------------------
+
+To guarantee that the connection of a new device into the field
+switch won't impact other devices connected to the same field
+switch, there are mandatory power-up requirements:
+
+- Maximum current step must be <50mA
+- Maximum di/dt of 10mA/ms
+- Maximum charge of 20μJ
+- No more than 6 current events during the first second
+
+After the first second the maximum di/dt is limited to 10mA/ms.
+
+More details can be found in APL Port Profile Specification or the
+IEC TS 63444 standard.
+
+.. figure:: Power-up.png
+ :width: 450 px
+ :align: left
+ :alt: Illustrative Current Step Characteristics During Power-up
+
+ Illustrative Current Step Characteristics During Power-up
+
+The main way is to make sure there is sequencing implemented on the
+power circuit of the APL field device; the power parts should never
+start-up at the same time such that it will cause huge spike that
+violates the APL specifications or even cause malfunction if it is
+not design as intended.
+
+In addition, a proper power sequence is necessary for the
+microcontroller MAX32690, this is for the sequence specific for the
+following voltage lines of the microcontroller's main supply pins:
+3V3 (VDDIOH/VDD3A), 1V8 (VDDIO/VDDA) and 1V1 (VCORE). It is
+recommended that at least every voltage signal rise has a sequence in
+which have a time distances apart, either to the time difference
+between amplitude, or more specifically, the time difference between
+the minimum or threshold/reset voltages of the three main supply
+pins of MAX32690: VRST(VDDIOH_MIN) = 1.71V, VRST(VDDIO_MIN) = 1.71V
+and VCORE(MIN) = 1.05V.
+
+.. figure:: MCU_sequence.png
+ :width: 450 px
+ :align: left
+ :alt: Power Up and Power Down Requirements of MAX32690
+
+ Power Up and Power Down Requirements of MAX32690
+
+In power-up capture of the LINE_P current along with the voltages of
+REG_3V5, SUP_3V3 and ISO_3V3 one main observation is that the spikes
+are generated during the beginning of conduction of every voltage
+regulator (e.g., LDO and Buck Converter). If there is no power
+sequencing, all of these parts might start-up at the same time,
+failing the charge requirement on the spike from the large peak
+current it might generate, and may cause other failures on the
+reference design.
+
+.. figure:: Hot_input1.png
+
+ Hot Input LINE_P Current Capture w/ REG_3V5, SUP_3V3, ISO_3V3
+ Voltages
+
+There is another power-up capture, in which the line current is
+captured along with the LINE_P voltage and the LOAD_P voltage shown
+in below figure. During hot plugging scenario, the LINE_P voltage rise
+is extremely fast which generate the main inrush, and this is to be
+expected. The inrush does not necessarily have to pass the 20uC
+charge maximum, but it is still measured to see and prove that even
+at very high peak, the charge is small granted that it happened too
+fast. The critical events of current however, are the spikes that
+happened after the inrush along with the di/dt.
+
+Looking at Figure cc, the start-up or di/dt slope or slew rate is
+only at 1.5003 mA/ms which is slow enough and it didn't violate the
+SPUR di/dt maximum of 10mA/ms. None of the spikes happening after
+the inrush has a charge value violating the 20μC maximum. In
+addition to the charge and di/dt, the amplitude of all the "events"
+which are the spikes and steps of the line current should not exceed
+the maximum amplitude feasible, which is dictated on its power
+specification, which for Power Class A, the maximum value should
+never exceed 55.56mA. The reference design has passed the APL port
+profile current step characteristics requirement for start-up during
+hot-plug scenario.
+
+.. figure:: Hot_input2.png
+
+ Hot Input LINE_P Current Capture w/ REG_3V5, LINE_P, LOAD_P Voltages
+
+Zooming in the beginning of the power-up sequence the following are
+measured: The inrush only has a 2.4μC of charge despite the high peak
+current of 126mA because of its very fast time, take note that the
+inrush doesn't require to pass the 20μC. The more critical spike is
+the one happening after the inrush which has a charge of around
+13μC to 17μC with a peak of 36.4mA but has a wider time on the
+spike. To optimize the 2nd Spike, it is recommended to have a very
+small shunt capacitance in the load side of LT8440 or the LOAD_P
+node, the lower the capacitance, the lower the spike peak will be
+and the shorter the charging time, thus reducing the spike's
+effective charge.
+
+.. figure:: Zoom_hot_input.png
+ :width: 450 px
+ :align: left
+ :alt: Zoomed Hot Input LINE_P Current Capture
+
+ Zoomed Hot Input LINE_P Current Capture
+
+For the same power sequence during power-up, the LINE_P current is
+capture along with the primary three supply voltages of the signal
+chain: 3V3, 1V8 and 1V1. The time distance between 3V3 and 1V8 is
+186.03ms, between 3V3 and 1V1 is 189.23ms, and zooming in further,
+the time distance between 1V8 and 1V1 is 3.2ms. The sequence is in
+correct order for start-up, which is 3V3 first, 1V8 second and 1V1
+third or last.
+
+.. figure:: Hot-Input3.png
+ :width: 450 px
+ :align: left
+ :alt: Hot Input Power-up Sequence of 3V3, 1V8 and 1V1
+
+ Hot Input Power-up Sequence of 3V3, 1V8 and 1V1
+
+.. figure:: Zoom_hot_input3.png
+ :width: 450 px
+ :align: left
+ :alt: Zoomed Power-up Sequence for 1V8 and 1V1
+
+ Zoomed Power-up Sequence for 1V8 and 1V1
+
+The capture for the power shut down sequence of LINE_P current and
+the main three supply voltages for the microcontroller, following
+the threshold or the minimum reset voltages of each supply: The
+time between 3V3 (min = 1.71V) and 1V8 (min = 1.71V) is 0.4ms,
+between 3V3 (min = 1.71V) and 1V1 (min = 1.05V) is 0.56ms and
+between 1V8 (min = 1.71V) and 1V1 (min = 1.05V) is 0.16ms. It is
+also following the correct sequence for shutdown being 1V1 first,
+1V8 second and 3V3 third or last.
+
+.. figure:: shutdown.png
+ :width: 450 px
+ :align: left
+ :alt: Shut-down Sequence for 3V3, 1V8 and 1V1
+
+ Shut-down Sequence for 3V3, 1V8 and 1V1
\ No newline at end of file
diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/shutdown.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/shutdown.png
new file mode 100644
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--- /dev/null
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diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/zoom_hot_input.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/zoom_hot_input.png
new file mode 100644
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diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Connection.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Connection.png
new file mode 100644
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diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Current_performance.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Current_performance.png
new file mode 100644
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diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Efficiency.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Efficiency.png
new file mode 100644
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diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LOAD_P.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LOAD_P.png
new file mode 100644
index 000000000..091ed6b26
--- /dev/null
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diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LT8440-connection.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LT8440-connection.png
new file mode 100644
index 000000000..16f9da3db
--- /dev/null
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diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LT8440-simplify.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LT8440-simplify.png
new file mode 100644
index 000000000..9245a6679
--- /dev/null
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@@ -0,0 +1,3 @@
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diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Line_thresolds.csv b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Line_thresolds.csv
new file mode 100644
index 000000000..f6136ecd5
--- /dev/null
+++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Line_thresolds.csv
@@ -0,0 +1,4 @@
+Condition |VLINEA - VLINEB|,Minimum (V),Typical (V),Maximum(V)
+Levels 1 to 2,10.14,10.5,10.82
+Levels 10 to 11,14.57,15,15.43
+Levels 15 to 16,17.02,17.5,17.95
diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Power_estimation.csv b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Power_estimation.csv
new file mode 100644
index 000000000..d126eafcd
--- /dev/null
+++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Power_estimation.csv
@@ -0,0 +1,16 @@
+Section,Device analised,Rail,Voltage(V),Current(mA),Power(mW),Comments
+"10Base-T1L Circuit ADIN1110",,DVDD_1V1,1.1,12,13.2,1.1V can be taken from internal LDO of ADIN1110
+,,VDDIO,1.8,18,32.4,
+,,AVDD_H,1.8,28,50.4,
+,,AVDD_L,1.8,28,50.4,
+Digital Circuit,MAX32690,VCORE,1.1,9.18,10.098,7.65uA/MHz @ 120MHz (maximum)
+,,VDD_3A,3.3,0.339,1.1187,VDD3A connected with VDDIOH
+,,VDD_IOH,3.3,8,26.4,I_OL and I_OH max current
+,,VDD_A,1.8,0.399,0.7182,VDDA connected with VDDIO
+,,VDD_IO,1.8,4,7.2,I_OL and I_OH max current
+Analog-to-Digital Converter/ Temperature Sensor Circuit,ADFS7124-4,AVDD (isolated side),3.3,2.2,7.26,being supplied via isolate power
+,,IOVDD (isolated side),3.3,1.08,3.564,being supplied via isolate power
+Digital Isolator,ADuM1441,VDD1,3.3,0.9,"2,97",
+,,VDD2 (isolated side),3.3,0.9,2.97, being supplied via isolate power
+Supervisory Circuit,MAX42500,VDD,"3,3",0.15,0.495,being supplied via separate line using LDO (Functional Safety)
+,MAX6613,VCC,3.3,0.013,0.0429,being supplied via separate line using LDO (Functional Safety)
\ No newline at end of file
diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Power_performance.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Power_performance.png
new file mode 100644
index 000000000..a8f5d7496
--- /dev/null
+++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Power_performance.png
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:1a0fdc53bdb18e12e1b406a0586e3d2b103139d2bf5b7427a06c40a3f5fe1b84
+size 60496
diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Regulation.csv b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Regulation.csv
new file mode 100644
index 000000000..dfefce56e
--- /dev/null
+++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Regulation.csv
@@ -0,0 +1,8 @@
+Condition |VLINEA - VLINEB|,Minimum (mA),Typica (mA),Maximum(mA)
+|VLINEA-VLINEB| = 9V,37.7,40.5,43.3
+Level 1 ,37.7,40.5,43.3
+Level 2,36.9,39.7,42.4
+Level 10,26.3,28.7,31.3
+Level 11,25.3,27.7,30.3
+Level 15,21.7,24.2,26.7
+Level 16,20.9,23.4,25.9
\ No newline at end of file
diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/index.rst b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/index.rst
new file mode 100644
index 000000000..3095813ca
--- /dev/null
+++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/index.rst
@@ -0,0 +1,363 @@
+.. _instrinsic_safety_design:
+
+Intrinsic Safety Design
+========================
+
+Ethernet-APL Field Platform Power Description
+"""""""""""""""""""""""""""""""""""""""""""""
+
+Introduction
+------------
+
+The :adi:`AD-ETHERNETAPLDEVICE-SL` follows specification based on
+Ethernet-APL Port Profile Power consumption. As a complete system,
+with the power conditioner involve as main part of the entire power
+tree (along with switching converters and LDO regulators), the
+following signal names are identified:
+
+.. csv-table:: Description for Significant Signals in the Board
+ :file: power_specifications.csv
+ :header-rows: 1
+ :widths: auto
+
+As shown in Table 2 - Electrical Characteristics of Power Classes, the
+:adi:`AD-ETHERNETAPLDEVICE-SL` has a required Power Class A
+specification. For the complete table, read the document's Table 6
+of `Ethernet-APL Port Profile specification
+`_.
+
+.. csv-table:: Electrical Characteristics of Power Classes
+ (Excerpt only/incomplete table)
+ :file: power_class.csv
+
+Circuit Analysis
+----------------
+The main goal for the power circuit of the reference design is to
+make sure that even if the power produced from the source port is as
+minimal as 540mW, or if the power received of the load port (field
+device or the :adi:`AD-ETHERNETAPLDEVICE-SL` itself) is as minimal as
+only 500mW for Power Class A, the board should still operate normally
+on those circumstances. Which means the reference design board should
+consume low power as possible that it doesn't violate the boundaries
+of line current and voltage range indicated in the specifications.
+
+This is why the :adi:`LT8440` Power conditioner is important and acts
+as main anchor part of the design, because it pulls at minimum 20mA
+to drive the protection diodes of the APL line to conduct power and
+provide data communication, and also enters shunt regulation mode to
+pull enough power for the device to function, while also limiting the
+current and power at 650mW maximum worst case to prevent overheating
+to comply with intrinsic safety. Ideally its best to select power
+parts of the best efficiency so it will only pull much lesser current
+on the LINE_P and LOAD_P during normal operation. However, if cost
+and small form-factor is the primary concern (in this case on this
+reference design with DIN-B form factor), we can slightly compromise
+the efficiency but making sure first that it won't violate the line
+current ceiling it can pull to the :adi:`LT8440`.
+
+.. figure:: Connection.png
+ :alt: Source to Load Simplified 2-WISE/APL Port Connection
+
+ Source to Load Simplified 2-WISE/APL Port Connection
+
+LT8440 Operation
+~~~~~~~~~~~~~~~~
+
+The LT8440 can operate on two different constant current regulation:
+Shunt Regulation Mode and Current Limit Mode, depending on the
+voltage sensed by the LINEA and LINEB pins of LT8440, and the current
+that will flow to the LOAD_P thru the system of
+AD-EthernetAPLDevice-SL, it will dictate the regulation amplitude of
+the line current and which mode it will regulate. For the complete
+specification of LT8440 for Table 4, Table 5 and Table 6, see the
+Electrical Characteristics on LT8440 datasheet.
+
+The line current will also depend on both the shunt current
+(I_SHUNT) and LOAD_P current (I_LOADP) as the line current (I_LINEP)
+is the summation of I_LOADP and I_SHUNT shown in Equation 1.
+
+.. math::
+
+ I_LINEP = I_LOADP+I_SHUNT (1)
+
+.. figure:: LT8440-simplify.png
+ :alt: Simplified Partial Circuit of LT8440
+
+ Simplified Partial Circuit of LT8440
+
+.. csv-table:: Line Voltage Threshold for sensed voltage between LINEA
+ and LINEB (Excerpt only - incomplete table)
+ :file: Line_thresolds.csv
+
+During Shunt Regulation Mode, the shunt pin of the LT8440 is
+conducting in which it satisfies Equation 1.
+
+The shunt pin will conduct if the current I_LOADP is not conducting
+(0mA) or I_LOADP is only minimal or lesser than the typical Shunt
+Regulation Mode current indicated in table 5 so the shunt pin detects
+the lack of I_LOADP, then the shunt pin pulls more current so that
+I_LINEP will regulate the current within the boundaries indicated on
+Table 5.
+
+Shunt current will only be equal to the line current if LOAD_P is
+operating at No-Load (0mA). If there is a minimal I_LOADP current,
+the Shunt current self-adjust to be what is indicated on Equation 2,
+which is simply a linear algebra manipulation of Equation 1.
+
+.. math::
+
+ I_SHUNT = I_LINEP - I_LOADP (2)
+
+For example: for LINE_P voltage of 10.5V, and I_LOADP = 10mA, the
+Shunt pin will pull the current I_SHUNT = 30mA approximately, so that
+it will satisfy the I_LINEP = 40.5mA (for Level 1) or I_LINEP =
+39.7mA (for Level 2).
+
+.. csv-table:: Regulating Line Current during Shunt Regulation Mode
+ (Excerpt only - incomplete table)
+ :file: Regulation.csv
+
+The LINEA and LINEB pins sensed the voltage on the input line and
+dictate the current regulation, the position in which the LINEA/B
+connected will have a different measured or sensed voltage while
+still complies to the specifications indicated on Table 3 and Table
+4, which is provided completely on the LT8440 datasheet.
+
+The LINEA/B should be connected after the polarity protection diodes
+indicated in Figure 3, so that the effective capacitances and
+inductances that will generate discharges of the system is being
+isolated by the diodes, and it will not be counted to the effective
+capacitance nad inductance of the input line or the load port, this
+is based on Table 1 of IEC60079-47, the allowable internal line
+capacitance is only 5nF, and allowable line inductance is 10uH. This
+will however result for the sensed voltage to be lower at normal
+operation because of the forward voltages of diodes reducing the
+sensed voltage.
+
+At lower sensed voltage, the current regulation of the LT8440 will
+have a higher offset current, but it is still in line with the
+electrical specification of LT8440, and the power limiter will still
+work as intended.
+
+Figure 3 is the designed configuration for AD-EthernetAPLDevice-SL
+to pass the Intrinsic safety design certification.
+
+.. figure:: LT8440-connection.png
+ :alt: Required Frontend Design with Large Effective Capacitance &
+ Inductance on the Load Side
+
+ Required Frontend Design with Large Effective Capacitance &
+ Inductance on the Load Side
+
+Power Tree Design
+~~~~~~~~~~~~~~~~~
+
+Initial step is to design the power parts after the LT8440 with the
+theoretical assumption of the power at maximum load condition that
+guarantees to operate the critical signal chain parts of
+AD-EthernetAPLDevice-SL, which are going to pull power from the
+LT8440's LOAD_P node. The performance of the design for current and
+power on LOAD_P shall not exceed the specifications or shall not trip
+the limits of LT8440 itself and the APL Specifications.
+
+Tabulating the estimated power budget of AD-EthernetAPLDevice-SL at
+maximum load based on the datasheets of the significant parts of the
+signal chain, we can calculate the theoretical power consumption at
+worst case and select appropriate power parts for the power tree
+using the LTPOWERPLANNER for the Power Tree calculation.
+
+.. csv-table:: Power Budget at Estimated Full Load
+ :file: Power_estimation.csv
+
+In the power tree provided in Figure 8 based on estimated power
+budget at full load.
+
+The reference design incorporates a for the different needed rails,
+mainly the triple output of 3.3V (3V3), 1.8V (1V8) and 1.1V (1V1)
+lines to power-up the common parts, a separate 3.3V line (SUP_3V3)
+dedicated to supplying power for the supervisory circuit, and an
+isolated 3.3V (ISO_3V3) for supplying the data isolator and A/D
+Converter temperature sensor interface.
+
+.. figure:: Power_planner.png
+ :alt: AD-EthernetAPLDevice-SL Power Tree
+
+ AD-EthernetAPLDevice-SL Power Tree
+
+The LT8606 acts as the pre-regulator of the power tree, it has a
+wide range of input voltage, capable of up to 42V maximum operation,
+small, efficient, and requires low component, this is suitable to the
+wide voltage range of 9V to 15V (or 17.5V maximum) on the LINE_P that
+will translate to a slightly reduced wide voltage on the LOAD_P node,
+take note that the voltage rating of the selected buck converter is
+considered with the 2/3 derating. The 350mA max current can provide
+more leeway (from 2/3 de-rating) and still is suitable for this 500mW
+system. The UVLO prevents the converter from operating if the LOAD_P
+voltage from the ethernet cable is too low, thus preventing some
+faulty operating conditions. Zener diodes are added to clamp the
+output rail and guarantee it will not exceed the VZ = 4.7V under any
+conditions, important as overvoltage protection for intrinsic safety,
+because it relaxes the requirements for picking parts when the
+voltage and power are much lower after the LT8440 and the Zener
+diodes.
+
+For simulation using LTSPICE for example (or estimation via
+datasheet), the LT8606 buck has an estimated efficiency of 90.3% and
+in the LTPOWERPLANNER power tree, the calculated maximum pulled
+current is 42.8mA in the input of LT8606, which is also the LOAD_P
+node. Among the parts for the main voltages 3V3, 1V8 and 1V1, the
+1V8 is the one that needs the most current as most of the signal
+chain parts, which are ADIN1110 and MAX32690, needed the supply
+voltage of 1.8V. To sustain a better efficiency so it won't pull too
+much current from the output of LT8606, we need another buck
+converter. The selected part for 1V8 output is MAX17626, it is
+small, high efficiency capable and requires low component count so
+it's easy to implement. By simulation using for example the EE-SIM
+Oasis software (or estimation via datasheet), the estimated
+efficiency given by the input and output voltages is 83.2% in which
+is indicated in the power tree of LTPOWERPLANNER.
+
+The 3V3 and 1V1 pulls very low current, so LDO regulators are better
+and cheaper with negligible effect on power loss. In this case we
+picked the ADP151 series of LDOs with fixed values for 1.1V and 3.3V
+because of small form factor, reduced cost and lower component
+count.
+
+The MAX253 push-pull converter is the selected isolated power part
+because of minimal design requirement or low component count. Based
+on the datasheet using 1:1.3 transformer, the estimated efficiency is
+84%. This is negligible for estimated drawn current of 4.5mA at the
+output with calculated output voltage of 4V to 4.3V. The push-pull
+won't regulate properly at light load or lower current, so a post
+regulator LDO is included to provide the fixed 3.3V isolated voltage
+for the A/D converter and digital isolator. The AVDD of ADFS7124-4
+can be sensitive or in risk of noise, so an optional RLC low pass
+filter is included. Zener Diodes are also included in the MAX253
+output to prevent overvoltage by clamping it to VZ = 4.7V during
+potential overvoltage fault and for general intrinsic safety.
+
+For functional safety specifically on the supply for the supervisory
+circuit like the MAX42500, the voltage line that is supplying should
+not be the voltage it monitors. A separate 3.3V line is powering the
+supervisor using ADP151-3.3V LDO which is labeled SUP_3V3, therefore
+the MAX42500 will still work properly even if there is an OV/UV
+event occurring to 3V3, 1V1, and 1V8.
+
+For the external SPI of AD-EthernetAPLDevice-SL, we included a
+dedicated supply pin of external 3.3V, although it is not counted in
+the overall power calculation because the SPI's load specification
+is not defined. However, the extra power that is available or unused
+will be dedicated to the external SPI, with the main LDO selected is
+ADP123. The LDO's dedicated VOUT feedback is usable for application
+were we need to modify the output voltage it will regulate. This is
+specific for intrinsic safety case where a limiting resistor is
+added, but the output should still maintain in 3.3V.
+
+Based on the calculation of the LTPOWERPLANNER, the maximum power or
+full load is approximately 300mW which is the estimated power pulled
+on the LOAD_P, and the I_LOADP only pulls an estimated maximum
+current of 42.85mA, which didn't exceed the limit of 55.56mA of APL.
+
+Note: The actual power on the board can be much lesser than the
+calculated power because the parts like the MAX32690 and ADIN1110
+won't require to fully utilized that much power to function. The
+actual or measured power and current are discussed on the Power
+Consumption section.
+
+Power Consumption
+~~~~~~~~~~~~~~~~~
+
+Characterizing the performance of the LT8440 Power Conditioner and
+the entire Power Tree, the following curves are captured at ambient
+temperature of 25 degrees Celsius (typical).
+
+.. figure:: LOAD_P.png
+ :alt: LOAD_P (Load Side) and Shunt Parameters
+
+ LOAD_P (Load Side) and Shunt Parameters
+
+The load side power and current are pulling approximately 288mW and
+21.38mA respectively at 15V line voltage, these are the highest
+parameters that the load side or LOAD_P node will consume during
+normal operation.
+
+For 9V line, the load side power and current are pulling
+approximately 260.9mW and 19.706mA respectively at normal operation.
+
+The reference design is operating on LT8440's shunt regulation mode,
+where the shunt pin is pulling current. The shunt power and current
+are pulling approximately 122.03mW and 9.03mA respectively at 15V
+line voltage, while its approximately 19.71mW and 2.79mA
+respectively at 9V line voltage. The highest shunt power occurred
+at 12.7V line voltage which is approximately 139.46mW.
+
+The shunt and load side power are small enough to not violate the APL
+limit when adding the two parameters.
+
+.. figure:: Efficiency.png
+ :alt: Efficiency and Current of Power Tree
+
+ Efficiency and Current of Power Tree
+
+The power tree was designed with the intention of prioritizing the
+small form factor and cost of parts, so there is a trade-off in the
+power efficiency for these power parts that are connected after the
+load side of LT8440.
+
+As shown in Figure 6, the efficiency in range of 33.04% up to
+36.65% which is not high and is a significant trade-off despite the
+very low power consumption, as long as it does not exceed the APL
+Limit power consumption of 500mW. Which on another point of focus,
+the efficiency can be trade-off, but the power pulled, or to be more
+specific, the current being pulled should be low enough that it
+would not exceed the current ceiling of the APL limit as shown also
+in Figure 6. So, when sacrificing the efficiency, it will pull more
+current and power, but those two parameters must not exceed what is
+indicated on the APL requirements like the 55.56mA maximum current at
+9V, and the 500mW limit for the entire line voltage range.
+
+.. figure:: Power_performance.png
+ :alt: LINE_P Power Performance at Normal Operation, Shorted and
+ Opened Load
+
+ LINE_P Power Performance at Normal Operation, Shorted and
+ Opened Load
+
+Speaking of the line voltage range of APL, the actual entire power
+consumption range of the whole reference design is measured, the
+power curves are shown in Figure 7. During normal operation, which
+is for the boundaries of APL profile specs in the line voltage range
+of 9V to 15V, the maximum power occurred at LINE_P for line voltage
+of 12.7V is 484mW, which if compared to the open or disconnected
+load side of LT8440 at shunt mode, the power is the same 484mW at
+12.8V line voltage instead.
+
+For Intrinsic safety scenario at line voltage range of 9V to 17.5V as
+dictated by IEC60079-47 standard, the maximum APL line power is
+625.62mW during the scenario that the load side is intentional
+faulted/shorted, it did not exceed the maximum die power rating of
+650mW, and is within below the 5.32W specification of IEC60079-47,
+therefore the LT8440 is doing its function as a power conditioner at
+normal operation and as a power limiter during fault scenario.
+
+.. figure:: Current_performance.png
+ :alt: LINE_P Current Performance at Normal Operation, Shorted and
+ Opened Load
+
+ LINE_P Current Performance at Normal Operation, Shorted and
+ Opened Load
+
+The triangular nature of the power curve of LINE_P is a result of the
+staircase like nature of the I_LINEP or APL line current. This is
+from the inherent design or construction of the LT8440 silicon in
+which it has hysteresis in its sensing of voltage during current
+regulation, so the shifting of current regulated has hysteresis
+transition first whenever the sensed voltage changes or varies.
+
+For the line currents, none of it exceeds to the limits of APL
+during normal operation, and also shorted operation of IEC60079-47
+as shown in Figure 8.
+
+For questions and more information, please visit the `EngineerZone
+`_ community or contact your local ADI
+representative.
diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_class.csv b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_class.csv
new file mode 100644
index 000000000..2a1de46bd
--- /dev/null
+++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_class.csv
@@ -0,0 +1,8 @@
+Specs,Class A,Class C,Class 3
+UPS(max) (VDC) ,15,15,50
+UPS(min) (VDC) ,9.6,11.61,46
+IPS(min) (mA) ,55.56,95,1250
+PPS(min) (W) ,0.54,1.1,57.5
+UPL(min) (VDC) ,9,1,36
+PPL(min) (W) ,0.5,1,36
+IPL(min) (mA) ,20,20,40
\ No newline at end of file
diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_planner.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_planner.png
new file mode 100644
index 000000000..d21e1cc0a
--- /dev/null
+++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_planner.png
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:376c8f6269e7c791e75a6591722ab9c63d5cdfc454dd50c5a2085c3c73209ab0
+size 5611138
diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_specifications.csv b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_specifications.csv
new file mode 100644
index 000000000..6db82ceb2
--- /dev/null
+++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_specifications.csv
@@ -0,0 +1,14 @@
+Node Name,Value,Description
+1V1,1.1V,"1.1V output of AD151-1.1 LDO, supplying the MAX32690's VCORE"
+1V8,1.8V,"1.8V output of MAX17626 buck converter, for VDDIO of 1.8V in the entire signal chain"
+3V3,3.3V,"Output voltage of ADP151-3.3 LDO, powering up VDD with 3.3V requirement"
+3V5,3.5V to 3.6V,"Output voltage of LT8606 buck converter, approximately within 3.5V, can have a bit more margin if increase to 3.6V"
+I_LINEP,20mA to 55.56mA,"Current at the Ethernet-APL Line, the main input current, or the line current, or the main DC current consumption"
+I_LOADP,0mA to 55mA,"Current at Load side of LT8440, also known as input current of LT8606 Buck Converter"
+I_SHUNT,0mA to 43.3mA,Current flowing to the Shunt Pin of LT8440
+ISO_3V3,3.3V,Isolated output of 3.3V produced by combination of MAX253 push-pull and ADP151-3.3 LDO. w/ respect to secondary/isolated ground
+ISO_GND,Ground (0V),isolated ground
+LINE_P,9V to 15V (typical),"Input APL Line (the differential connection of LINE_P and LINE_N is the ""LOAD PORT"" of APL field device)"
+LOAD_N,Ground (0V),main local ground (named LOAD_E on secondary board of AD-EthernetAPLDevice-SL)
+LOAD_P,approx. 8V to 14V (typical),"Voltage at Load Side of LT8440, also the input of LT8606 Buck converter"
+SUP_3V3,3.3V,"Separate 3.3V output for supplying supervisory circuits like MAX42500 and MAX6613, using ADP151-3.3 LDO "
\ No newline at end of file
diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/index.rst b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/index.rst
index 4bd49616a..031bb4722 100644
--- a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/index.rst
+++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/index.rst
@@ -59,14 +59,14 @@ Hardware Design Files
~~~~~~~~~~~~~~~~~~~~~
- :download:`Schematic Power and Comms board <02-083152-01-b.pdf>`
-- :download:`Schematic Digital IS board <02-083153-01-c.pdf>`
+- :download:`Schematic Digital IS board <02-083153-01-d.pdf>`
- :download:`Schematic Digital NON-IS board <02-084576-01-b.pdf>`
-- :download:`Layout Power and Comms board <08-083152-01-b-1.pdf>`
-- :download:`Layout Digital IS board <08-083153-01-c.pdf>`
+- :download:`Layout Power and Comms board <08-083152-01-b.pdf>`
+- :download:`Layout Digital IS board <08-083153-01-d.pdf>`
- :download:`Layout Digital NON-IS board <08-084576-01-b.pdf>`
-- :download:`Bill of Materials Power and Comms board <05-083152-01-b.csv.zip>`
-- :download:`Bill of Materials Digital IS board <05-083153-01-c.csv.zip>`
-- :download:`Bill of Materials Digital NON-IS board <05-084576-01-b.csv.zip>`
+- :download:`Bill of Materials Power and Comms board <05-083152-01-b.zip>`
+- :download:`Bill of Materials Digital IS board <05-083153-01-d.zip>`
+- :download:`Bill of Materials Digital NON-IS board <05-084576-01-b.zip>`
Package Contents
----------------
@@ -195,11 +195,8 @@ The software stack includes:
- Secure boot and authentication via MAXQ1065
- Zephyr RTOS support
-..
- Enable this after adding content
-
- Complementary Documentation
- ---------------------------
+Complementary Documentation
+---------------------------
.. toctree::
:titlesonly:
diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/sw_block_diagram.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/sw_block_diagram.png
index f7bacfa1d..01ef8b996 100644
--- a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/sw_block_diagram.png
+++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/sw_block_diagram.png
@@ -1,3 +1,3 @@
version https://git-lfs.github.com/spec/v1
-oid sha256:869c2524a94f2a4cb83a83edbcc8850540da50a335079c325e72b124dfcb1375
-size 119657
+oid sha256:67022734e6fdc51c776b0947b1c865e8dd5d1ebc427ab411d564be30ac9581d0
+size 103423
diff --git a/docs/solutions/reference-designs/eval-ad9081/index.rst b/docs/solutions/reference-designs/eval-ad9081/index.rst
index 7ea9aa281..1675b4760 100644
--- a/docs/solutions/reference-designs/eval-ad9081/index.rst
+++ b/docs/solutions/reference-designs/eval-ad9081/index.rst
@@ -94,8 +94,11 @@ Table of contents
#. :ref:`ad9081 quickstart`:
#. Using the :ref:`Arria 10 SX SoC `
- #. Using the :ref:`VCK190 & VPK180/Versal `
- #. Using the :ref:`ZCU102/Zynq UltraScale MP SoC `
+ #. Using the :ref:`VCK190 & VPK180/Versal `
+ #. Using the :ref:`VCU118/ Virtex UltraScale+ `
+ #. Using the :ref:`ZC706/ Zynq-7000 SoC `
+ #. Using the :ref:`ZCU102/Zynq UltraScale+ MP SoC `
+
#. Configure an SD Card with :external+adi-kuiper-gen:doc:`Kuiper `
diff --git a/docs/solutions/reference-designs/eval-ad9081/prerequisites.rst b/docs/solutions/reference-designs/eval-ad9081/prerequisites.rst
index fdd8c5c07..8b215648c 100644
--- a/docs/solutions/reference-designs/eval-ad9081/prerequisites.rst
+++ b/docs/solutions/reference-designs/eval-ad9081/prerequisites.rst
@@ -32,9 +32,9 @@ Hardware prerequisites
- LAN cable (Ethernet)
- Host PC (Windows or Linux)
-#. Internet connection (without proxies makes things much easier) to update the
- scripts/binaries on the SD card that came with the ADI FMC Card (firewalls
- are OK, proxies make things a pain).
+#. Internet connection (without proxies makes things much easier) to update
+ the scripts/binaries on the SD card that came with the ADI FMC Card
+ (firewalls are OK, proxies make things a pain).
#. RF Test equipment
#. An SD card with at least 16GB of memory (in case you're using Linux). You
should have received one when purchasing the evaluation board.
@@ -45,9 +45,10 @@ Software prerequisites
Normally, for basic functionalities regarding visualizing the data received
from the FPGA, we use the following:
-#. :external+scopy:doc:`Scopy ` v2.0 or later (must contain the IIO plugin)
+#. :external+scopy:doc:`Scopy ` v2.0 or later (must contain the IIO
+ plugin)
.. note::
- :adi:`ADI <>` does not offer FPGA carrier platforms for sale or loan; getting
- one yourself is the normal part of development or evaluation.
+ :adi:`ADI <>` does not offer FPGA carrier platforms for sale or loan;
+ getting one yourself is the normal part of development or evaluation.
diff --git a/docs/solutions/reference-designs/eval-ad9081/quickstart/a10soc.rst b/docs/solutions/reference-designs/eval-ad9081/quickstart/a10soc.rst
index 1e2e253f0..324aaabaf 100644
--- a/docs/solutions/reference-designs/eval-ad9081/quickstart/a10soc.rst
+++ b/docs/solutions/reference-designs/eval-ad9081/quickstart/a10soc.rst
@@ -3,15 +3,17 @@
Arria 10 SoC Quick start
===============================================================================
-.. image:: ../../images/ad9081_a10soc_setup.jpg
- :width: 800
-
This guide provides quick instructions on how to setup the
:adi:`EVAL-AD9081` on:
- :intel:`Arria 10 SoC `
(Rev. C or later) on FMCA
+.. image:: ../../images/a10soc.jpg
+ :width: 900
+
+.. esd-warning::
+
.. warning::
:adi:`EVAL-AD9082` is not supported on
@@ -55,8 +57,8 @@ Instructions on how to manually build the boot files from source can be found
here:
- :dokuwiki:`Building the Intel SoC-FPGA kernel and devicetrees from source `
-- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build details at
- :external+hdl:ref:`build_hdl`.
+- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build
+ details at :external+hdl:ref:`build_hdl`.
Required software
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -115,16 +117,17 @@ These resistors can be found on the backside of the A10SoC, underneath the
FMCA connector (J29). The following picture shows the required configuration
to be compatible with the :adi:`EVAL-AD9081`.
+.. image:: ../../images/a10soc_fmc_rework.jpg
+ :width: 400
+
Testing
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Creating the setup
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. image:: ../../images/a10soc.jpg
- :width: 900
-
-.. esd-warning::
+.. image:: ../../images/ad9081_a10soc_setup.jpg
+ :width: 800
In the following example, we will make a physical loopback between the ADC
and the DAC channels on the evaluation board, using SMA cables.
@@ -132,9 +135,10 @@ and the DAC channels on the evaluation board, using SMA cables.
Follow the steps in this order, to avoid damaging the components:
#. Connect the SMA cables ADC0-DAC0, ADC1-DAC1, ADC2-DAC2, ADC3-DAC3
-#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the
- FPGA carrier **HPC1** FMCA (J29) socket
-#. Both the HPS (J26) and FPGA (J27) memory module must be installed on the A10SoC
+#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the A10SOC
+ **HPC1** FMCA (J29) socket
+#. Both the HPS (J26) and FPGA (J27) memory module must be installed on the
+ A10SoC
#. Insert microSD card into the card socket on the FPGA
#. Configure the FPGA for SD card boot mode. That is the
:intel:`default position `
@@ -147,9 +151,6 @@ Follow the steps in this order, to avoid damaging the components:
#. Observe Kernel and serial console output messages on your terminal (use
the first ttyUSB or COM port registered)
-.. image:: ../../images/a10soc_fmc_rework.jpg
- :width: 400
-
Boot messages
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -677,6 +678,13 @@ To reboot the system, run:
be taken not to corrupt the file system -- please shut down things, don't
just turn off the power switch. Depending on your monitor, the standard
power off could be hiding. You can do this from the terminal as well with
- :code:`sudo shutdown -h now` or the above-mentioned command for powering off.
+ :code:`sudo shutdown -h now` or the above-mentioned command for powering
+ off.
.. include:: ../../common/using-iio-osc.rst
+
+..
+ About the IIO devices
+ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+ TBD
diff --git a/docs/solutions/reference-designs/eval-ad9081/quickstart/index.rst b/docs/solutions/reference-designs/eval-ad9081/quickstart/index.rst
index f8ba33d04..fd8606cac 100644
--- a/docs/solutions/reference-designs/eval-ad9081/quickstart/index.rst
+++ b/docs/solutions/reference-designs/eval-ad9081/quickstart/index.rst
@@ -5,14 +5,16 @@ Quick start guides
The Quick start guides provide simple step by step instructions on how to do
an initial system setup for the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082`
-boards on various FPGA development boards. In these guides, we will discuss how
-to program the bitstream, run a no-OS program or boot a Linux distribution.
+boards on various FPGA development boards. In these guides, we will discuss
+how to program the bitstream, run a no-OS program or boot a Linux distribution.
.. toctree::
On A10SoC
- On VCK190
- On ZCU102
+ On VCK190
+ On ZC706
+ On VCU118
+ On ZCU102
.. _ad9081 carriers:
diff --git a/docs/solutions/reference-designs/eval-ad9081/quickstart/versal.rst b/docs/solutions/reference-designs/eval-ad9081/quickstart/vck190.rst
similarity index 95%
rename from docs/solutions/reference-designs/eval-ad9081/quickstart/versal.rst
rename to docs/solutions/reference-designs/eval-ad9081/quickstart/vck190.rst
index 43c086830..60dee13b9 100644
--- a/docs/solutions/reference-designs/eval-ad9081/quickstart/versal.rst
+++ b/docs/solutions/reference-designs/eval-ad9081/quickstart/vck190.rst
@@ -1,16 +1,18 @@
-.. _ad9081 quickstart versal:
+.. _ad9081 quickstart vck190:
VCK190 Quick start
===============================================================================
-.. image:: ../../images/ad9081_vck190_setup.jpg
- :width: 800
-
This guide provides some quick instructions on how to setup the
:adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` on:
- :xilinx:`VCK190` FMCP1 (J51) port
+.. image:: ../../images/vck190.jpg
+ :width: 900
+
+.. esd-warning::
+
Using Linux as software
-------------------------------------------------------------------------------
@@ -37,8 +39,8 @@ here:
- :ref:`linux-kernel zynqmp` (the only difference compared to the ZynqMP is
that instead of running ``make adi_zynqmp_defconfig``,
you must run ``make adi_versal_defconfig``)
-- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build details at
- :external+hdl:ref:`build_hdl`.
+- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build
+ details at :external+hdl:ref:`build_hdl`.
Required Software
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -64,72 +66,69 @@ Required Hardware
Testing
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. image:: ../../images/vck190.jpg
- :width: 900
-
Creating the setup
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. esd-warning::
+.. image:: ../../images/ad9081_vck190_setup.jpg
+ :width: 800
Follow the steps in this order, to avoid damaging the components:
-- Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the
- FPGA carrier FMC+ FMCP1 socket
-- Connect USB UART J207 (Type-C USB) to your host PC
-- Insert SD card with ADI Kuiper image into socket J302
-- Insert System Controller SD card into socket J206
-- Configure ACAP for SD boot (mode SW1[4:1] switch in the position
- **OFF,OFF,OFF,ON** as seen in the below picture)
-.. image:: ../../images/vck190_sw1.jpg
- :width: 200
+#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the
+ VCK190 FMCP1 socket
+#. Connect USB UART J207 (Type-C USB) to your host PC
+#. Insert SD card with ADI Kuiper image into socket J302
+#. Insert System Controller micro SD card into socket J206
+#. Configure ACAP for SD boot (mode SW1[4:1] switch in the position
+ **OFF,OFF,OFF,ON** as seen in the below picture)
+
+ .. image:: ../../images/vck190_sw1.jpg
+ :width: 200
-- Configure System Controller for SD card boot (mode SW11[4:1] switch in the
+#. Configure System Controller for SD card boot (mode SW11[4:1] switch in the
position **OFF,OFF,OFF,ON** as seen in the below picture).
-.. image:: ../../images/vck190_sw11.jpg
- :width: 200
+ .. image:: ../../images/vck190_sw11.jpg
+ :width: 200
-- Connect an Ethernet cable to J307 and also to SYSCTL Ethernet port to access
- Board Evaluation & Management Tool (BEAM);
-- Turn on the power switch on the FPGA board;
-- Observe kernel and serial console messages on your terminal, both the ACAP
- UART interface and the System controller. (use the first ttyUSB or COM port
- registered for the ACAP UART interface, and try the other 2 to find the one
- for System Controller);
-- On the System Controller console, a BEAM Tool Web Address should be assigned.
- Go to this web address to set VADJ_FMC to 1.5V;
-- To change VADJ_FMC On BEAM, click 'Test The Board'>'Board Settings'>'FMC'.
- Then on 'Set VADJ_FMC', select 1.5V and click 'Set'.
+#. Connect an Ethernet cable to J307 and also to SYSCTL Ethernet port to access
+ Board Evaluation & Management Tool (BEAM);
+#. Turn on the power switch on the FPGA board;
+#. Observe kernel and serial console messages on your terminal, both the ACAP
+ UART interface and the System controller. (use the first ttyUSB or COM port
+ registered for the ACAP UART interface, and try the other 2 to find the one
+ for System Controller);
+#. On the System Controller console, a BEAM Tool Web Address should be assigned.
+ Go to this web address to set VADJ_FMC to 1.5V;
-.. image:: beam-home.jpg
- :width: 1000
+ .. image:: beam-home.jpg
+ :width: 1000
-.. image:: beam-board-settings.jpg
- :width: 1000
+ .. image:: beam-board-settings.jpg
+ :width: 1000
-.. image:: beam-set-vadj.jpg
- :width: 1000
+ .. image:: beam-set-vadj.jpg
+ :width: 1000
-- On the ACAP UART interface console, reboot the system. After reboot,
- ad9081 devices should be present.
+#. On the ACAP UART interface console, reboot the system. After reboot,
+ AD9081 devices should be present.
-.. note::
+ .. note::
- Versal-based carriers (:xilinx:`VCK190`) might not boot with released image.
+ Versal-based carriers (:xilinx:`VCK190`) might not boot with released image.
- The problem appears because some revisions of :xilinx:`VCK190` or
- :xilinx:`VPK180` may have the date/time set randomly or in 64bit format.
- To make them boot, it is enough to overwrite the date, following next steps:
+ The problem appears because some revisions of :xilinx:`VCK190` or
+ :xilinx:`VPK180` may have the date/time set randomly or in 64bit format.
+ To make them boot, it is enough to overwrite the date, following next steps:
- - when booting the board, hit any key to go into u-boot menu
- - type ``mw F12A0000 6613DE3D`` (this value is hexa of the date from Unix
- Converter webpage)
- - continue booting
+ - when booting the board, hit any key to go into u-boot menu
+ - type ``mw F12A0000 6613DE3D`` (this value is hexa of the date from Unix
+ Converter webpage)
+ - continue booting
ACAP SD card boot files
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The files that need to be present on the SD card BOOT partition are:
@@ -143,13 +142,13 @@ Copy the BOOT.BIN, boot.scr and system.dtb from the
ADI Kuiper image. Then, copy the Image from the ``versal-common`` folder.
Setting up UART
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
When setting up the UART make sure you connect to the ACAP UART interface and
not the System controller.
Boot messages
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Login Information required for the System Controller:
@@ -868,13 +867,13 @@ To reboot the system, run:
be taken not to corrupt the file system -- please shut down things, don't
just turn off the power switch. Depending on your monitor, the standard
power off could be hiding. You can do this from the terminal as well with
- :code:`sudo shutdown -h now` or the above-mentioned command for powering off.
+ :code:`sudo shutdown -h now` or the above-mentioned command for powering
+ off.
.. include:: ../../common/using-iio-osc.rst
-About the IIO devices
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
..
- This section is with ^^^ because the last section from using-iio-osc.rst which
- is included previously, has the last section as ^^^.
+ About the IIO devices
+ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+ TBD
diff --git a/docs/solutions/reference-designs/eval-ad9081/quickstart/vcu118.rst b/docs/solutions/reference-designs/eval-ad9081/quickstart/vcu118.rst
new file mode 100644
index 000000000..fca12fbcb
--- /dev/null
+++ b/docs/solutions/reference-designs/eval-ad9081/quickstart/vcu118.rst
@@ -0,0 +1,279 @@
+.. _ad9081 quickstart vcu118:
+
+VCU118 Quick start
+===============================================================================
+
+This guide provides quick instructions on how to setup the
+:adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` on:
+
+- :xilinx:`VCU118` FMC+
+
+.. image:: ../../images/vcu118.png
+ :width: 900
+
+.. esd-warning::
+
+Using Linux as software
+-------------------------------------------------------------------------------
+
+Necessary files
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The following files are needed for the system to boot:
+
+- HDL boot image: ``BOOT.BIN``
+- Linux Kernel image: ``Image``
+- Linux device tree: ``system.dtb``
+
+They can either be taken from the SD card -- already generated by us, or you
+can build them manually.
+
+In the following sections, we explain **how to take them from the SD card**.
+
+Instructions on how to manually build the boot files from source can be found
+here:
+
+- :ref:`linux-kernel microblaze`
+- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build
+ details at :external+hdl:ref:`build_hdl`.
+
+Required Software
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- SD Card 16GB imaged with :external+adi-kuiper-gen:doc:`Kuiper `
+ (check out that guide on how to do it, then come back to this section)
+- A UART terminal (Putty/Tera Term/Minicom, etc.) with baud rate 115200 (8N1)
+
+Required Hardware
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- AMD Xilinx :xilinx:`VCU118` Rev 1.0 or later FPGA board and its power supply
+- :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC evaluation board
+- SD card with at least 16GB of memory
+- 2 x Micro-USB cable
+- LAN cable (Ethernet)
+- Signal generator
+- 4x SMA cables
+- (Optional) USB keyboard & mouse and a HDMI compatible monitor
+- (Optional) 4 way splitter
+
+More details as to why you need these, can be found at
+:ref:`ad9081 prerequisites`.
+
+Testing
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Creating the setup
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. image:: ../../images/ad9081_vcu118_setup.png
+ :width: 800
+
+In the following example, we will make a physical loopback between the ADC
+and the DAC channels on the evaluation board, using SMA cables.
+
+Follow the steps in this order, to avoid damaging the components:
+
+#. Connect the SMA cables ADC0-DAC0, ADC1-DAC1, ADC2-DAC2, ADC3-DAC3
+#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the VCU118
+ **FMC+** socket
+#. Insert SD card into the SD card socket on the FPGA
+#. Configure :xilinx:`VCU118` for SD card boot mode (mode SW6[3:1] switch in
+ the position **1: Down, 2: Down, 3: Up, 4: Up** )
+#. Plug-in an Ethernet cable from your router/switch to the Ethernet port on
+ the FPGA board
+#. Connect USB UART (Micro-USB) to your host PC
+#. (Optional) Connect a monitor to the FPGA by HDMI, and a mouse and a keyboard
+#. Connect the power supply for the FPGA
+#. Turn on the power switch on the FPGA board
+#. Observe Kernel and serial console output messages on your terminal (use
+ the first ttyUSB or COM port registered)
+
+Boot messages
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following is what is printed in the serial console, after you have
+connected to the proper ttyUSB or COM port:
+
+.. collapsible:: Complete boot log
+
+ ::
+
+ U-Boot 2018.01-21442-gf06dec3cab (Nov 10 2023 - 16:08:56 +0200) Xilinx ZynqMP VCU118 revA, Build: jenkins-development-build_uboot-6
+
+ I2C: ready
+ DRAM: 4 GiB
+
+
+Useful commands for the serial terminal
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The below commands are to be run in the serial terminal connected to the FPGA.
+
+To find out the IP of the FPGA board, run the following command and take the
+IP specified at "eth0 inet":
+
+.. shell::
+
+ $ifconfig
+
+To see the IIO devices detected, run:
+
+.. shell::
+
+ $iio_info | grep iio:device
+ iio:device0: hmc7044
+ iio:device1: axi-ad9081-tx-hpc (buffer capable)
+ iio:device2: axi-ad9081-rx-hpc (buffer capable)
+
+To see the EEPROM specifications, run:
+
+.. shell::
+
+ $fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
+
+To use the :dokuwiki:`JESD204 status utility `,
+run:
+
+.. shell::
+
+ $jesd_status
+
+All links should be in DATA without errors:
+
+.. shell::
+
+ $jesd_status -s
+ (DEVICES) Found 2 JESD204 Link Layer peripherals
+
+ (0): axi-jesd204-rx/44a90000.axi-jesd204-rx [*]
+ (1): axi-jesd204-tx/44b90000.axi-jesd204-tx
+
+ (STATUS)
+ Link is enabled
+ Link Status DATA
+ Measured Link Clock (MHz) 249.998
+ Reported Link Clock (MHz) 250.000
+ Measured Device Clock (MHz) 250.000
+ Reported Device Clock (MHz) 250.000
+ Desired Device Clock (MHz) 250.000
+ Lane rate (MHz) 10000.000
+ Lane rate / 40 (MHz) 250.000
+ LMFC rate (MHz) 7.812
+ SYSREF captured Yes
+ SYSREF alignment error No
+ SYNC~
+
+ (LANE STATUS)
+ Lane# 0 1 2 3
+ Errors 0 0 0 0
+ Latency (Multiframes/Octets) 1/22 1/20 1/25 1/21
+ CGS State DATA DATA DATA DATA
+ Initial Frame Sync Yes Yes Yes Yes
+ Initial Lane Alignment Sequence Yes Yes Yes Yes
+
+To power off the system, run the following command, and wait for the final
+message to be printed, then power off the FPGA board from the switch as well.
+
+.. shell::
+
+ $poweroff
+
+To reboot the system, run:
+
+.. shell::
+
+ $reboot
+
+.. important::
+
+ Even thought this is Linux, this is a persistent file systems. Care should
+ be taken not to corrupt the file system -- please shut down things, don't
+ just turn off the power switch. Depending on your monitor, the standard
+ power off could be hiding. You can do this from the terminal as well with
+ :code:`sudo shutdown -h now` or the above-mentioned command for powering
+ off.
+
+.. include:: ../../common/using-iio-osc.rst
+
+..
+ About the IIO devices
+ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+ TBD
+
+Using no-OS as software
+-------------------------------------------------------------------------------
+
+Necessary files
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The following files are needed for the system to boot:
+
+- HDL boot file: ``system_top.xsa``
+- no-OS project: :git-no-os:`projects/ad9081`
+
+Instructions on how to build the boot files from source can be found here:
+
+- :external+no-OS:doc:`projects/adc/ad9081`. More no-OS build
+ details at :external+no-OS:doc:`build_guide`.
+- :external+hdl:ref:`ad9081_fmca_ebz`. More HDL build details at
+ :external+hdl:ref:`build_hdl`.
+
+Required Software
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- AMD Xilinx Vivado and Vitis (downloading Vitis from
+ `here `_
+ will include Vivado as well)
+- An UART terminal (Putty/Tera Term/Minicom, etc.), Baud rate 115200 (8N1)
+
+Required Hardware
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- AMD Xilinx :xilinx:`VCU118` Rev 1.0 or later FPGA board and its power supply
+- :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC evaluation board
+- 2x Micro-USB cables, one for UART and one for JTAG
+- (Optional) USB keyboard & mouse and a HDMI-compatible monitor
+
+More details as to why you need these, can be found at
+:ref:`ad9081 prerequisites`.
+
+Testing
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Creating the setup
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. image:: ../../images/ad9081_vcu118_setup.png
+ :width: 800
+
+Follow the steps in this order, to avoid damaging the components:
+
+#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the VCU118
+ **FMC+** socket
+#. Configure :xilinx:`VCU118` for SD card boot mode (mode SW6[3:1] switch in
+ the position **1: Down, 2: Down, 3: Up, 4: Up** )
+#. Connect USB UART (Micro-USB) to your host PC
+#. Connect USB JTAG (Micro-USB) to your host PC
+#. (Optional) Connect a monitor to the FPGA by HDMI, and a mouse and a keyboard
+#. Turn on the power switch on the FPGA board
+#. Observe console output messages on your terminal (use the first ttyUSB or
+ COM port registered)
+
+Console output
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following is what is printed in the serial console, after you have
+connected to the proper ttyUSB or COM port:
+
+.. collapsible:: Complete boot log
+
+ ::
+
+ Xilinx Microblaze First Stage Boot Loader
+
+..
+ TBD
+
+.. include:: ../../common/using-iio-osc.rst
diff --git a/docs/solutions/reference-designs/eval-ad9081/quickstart/zc706.rst b/docs/solutions/reference-designs/eval-ad9081/quickstart/zc706.rst
new file mode 100644
index 000000000..144acda4b
--- /dev/null
+++ b/docs/solutions/reference-designs/eval-ad9081/quickstart/zc706.rst
@@ -0,0 +1,783 @@
+.. _ad9081 quickstart zc706:
+
+ZC706 Quick start
+===============================================================================
+
+This guide provides quick instructions on how to setup the
+:adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` on:
+
+- :xilinx:`ZC706` FMC HPC
+
+.. image:: ../../images/zc706.png
+ :width: 900
+
+.. esd-warning::
+
+Using Linux as software
+-------------------------------------------------------------------------------
+
+Necessary files
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The following files are needed for the system to boot:
+
+- HDL boot image: ``BOOT.BIN``
+- Linux Kernel image: ``uImage``
+- Linux device tree: ``devicetree.dtb``
+
+They can either be taken from the SD card -- already generated by us, or you
+can build them manually.
+
+In the following sections, we explain **how to take them from the SD card**.
+
+Instructions on how to manually build the boot files from source can be found
+here:
+
+- :ref:`linux-kernel zynq`
+- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build
+ details at :external+hdl:ref:`build_hdl`.
+
+Required Software
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- SD Card 16GB imaged with :external+adi-kuiper-gen:doc:`Kuiper `
+ (check out that guide on how to do it, then come back to this section)
+- A UART terminal (Putty/Tera Term/Minicom, etc.) with baud rate 115200 (8N1)
+
+Required Hardware
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- AMD Xilinx :xilinx:`ZC706`` Rev 1.2 or higher FPGA board and its power supply
+- :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC evaluation board
+- SD card with at least 16GB of memory
+- Mini-USB cable (UART)
+- LAN cable (Ethernet)
+- 4x SMA cables
+- (Optional) USB keyboard & mouse and a HDMI compatible monitor
+
+More details as to why you need these, can be found at
+:ref:`ad9081 prerequisites`.
+
+Testing
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Creating the setup
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. image:: ../../images/ad9081-fmca-ebz-zc706.png
+ :width: 800
+
+In the following example, we will make a physical loopback between the ADC
+and the DAC channels on the evaluation board, using SMA cables.
+
+Follow the steps in this order, to avoid damaging the components:
+
+#. Connect the SMA cables ADC0-DAC0, ADC1-DAC1, ADC2-DAC2, ADC3-DAC3
+#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the ZC706
+ **HPC** FMC socket
+#. Insert SD card into the SD card socket on the FPGA
+#. Configure :xilinx:`ZC706`` for SD card boot mode (Set the jumpers:
+ The main one is: SW11 - Big Blue Switch in the middle, which controls the
+ Boot Mode, it needs to be set: **1: Down, 2: Down, 3: Up, 4: Up, 5: Down**)
+#. Plug-in an Ethernet cable from your router/switch to the Ethernet port on
+ the FPGA board
+#. Connect USB UART (Mini-USB) to your host PC
+#. (Optional) Connect a monitor to the FPGA by HDMI, and a mouse and a keyboard
+#. Connect the power supply for the FPGA
+#. Turn on the power switch on the FPGA board
+#. Observe Kernel and serial console output messages on your terminal (use
+ the first ttyUSB or COM port registered)
+
+Boot messages
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following is what is printed in the serial console, after you have
+connected to the proper ttyUSB or COM port:
+
+.. collapsible:: Complete boot log
+
+ ::
+
+ U-Boot 2014.07-dirty (Nov 20 2014 - 17:07:55)
+
+ Board: Xilinx Zynq
+ I2C: ready
+ DRAM: ECC disabled 1 GiB
+ MMC: zynq_sdhci: 0
+ SF: Detected S25FL128S_64K with page size 512 Bytes, erase size 128 KiB, total 32 MiB
+ In: serial
+ Out: serial
+ Err: serial
+ Net: Gem.e000b000
+ Hit any key to stop autoboot: 0
+ Device: zynq_sdhci
+ Manufacturer ID: 3
+ OEM: 5344
+ Name: SC32G
+ Tran Speed: 50000000
+ Rd Block Len: 512
+ SD version 3.0
+ High Capacity: Yes
+ Capacity: 29.7 GiB
+ Bus Width: 4-bit
+ reading uEnv.txt
+ 407 bytes read in 27 ms (14.6 KiB/s)
+ Loaded environment from uEnv.txt
+ Importing environment from SD ...
+ Running uenvcmd ...
+ Copying Linux from SD to RAM...
+ reading uImage
+ 6506856 bytes read in 580 ms (10.7 MiB/s)
+ reading devicetree.dtb
+ 23071 bytes read in 39 ms (577.1 KiB/s)
+ reading uramdisk.image.gz
+ ** Unable to read file uramdisk.image.gz **
+ ## Booting kernel from Legacy Image at 03000000 ...
+ Image Name: Linux-5.4.0-93252-ga4800dc5737b
+ Image Type: ARM Linux Kernel Image (uncompressed)
+ Data Size: 6506792 Bytes = 6.2 MiB
+ Load Address: 00008000
+ Entry Point: 00008000
+ Verifying Checksum ... OK
+ ## Flattened Device Tree blob at 02a00000
+ Booting using the fdt blob at 0x2a00000
+ Loading Kernel Image ... OK
+ Loading Device Tree to 1fff7000, end 1ffffa1e ... OK
+
+ Starting kernel ...
+
+ Booting Linux on physical CPU 0x0
+ Linux version 5.4.0-93252-ga4800dc5737b (michael@mhenneri-D06) (gcc version 8.2.0 (GCC)) #2881 SMP PREEMPT Fri Mar 19 16:22:37 CET 2021
+ CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
+ CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
+ OF: fdt: Machine model: Xilinx Zynq ZC706
+ OF: fdt: earlycon: stdout-path /amba@0/uart@E0001000 not found
+ Memory policy: Data cache writealloc
+ cma: Reserved 128 MiB at 0x38000000
+ percpu: Embedded 15 pages/cpu s29516 r8192 d23732 u61440
+ Built 1 zonelists, mobility grouping on. Total pages: 260608
+ Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype=ext4 rootwait clk_ignore_unused cpuidle.off=1
+ Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear)
+ Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
+ mem auto-init: stack:off, heap alloc:off, heap free:off
+ Memory: 888452K/1048576K available (9216K kernel code, 743K rwdata, 7044K rodata, 1024K init, 162K bss, 29052K reserved, 131072K cma-reserved, 131072K highmem)
+ rcu: Preemptible hierarchical RCU implementation.
+ rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
+ Tasks RCU enabled.
+ rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
+ rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
+ NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
+ efuse mapped to (ptrval)
+ slcr mapped to (ptrval)
+ L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
+ L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
+ L2C-310 erratum 769419 enabled
+ L2C-310 enabling early BRESP for Cortex-A9
+ L2C-310 full line of zeros enabled for Cortex-A9
+ L2C-310 ID prefetch enabled, offset 1 lines
+ L2C-310 dynamic clock gating enabled, standby mode enabled
+ L2C-310 cache controller enabled, 8 ways, 512 kB
+ L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
+ random: get_random_bytes called from start_kernel+0x2cc/0x454 with crng_init=0
+ zynq_clock_init: clkc starts at (ptrval)
+ Zynq clock init
+ sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
+ clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
+ Switching to timer-based delay loop, resolution 3ns
+ clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
+ timer #0 at (ptrval), irq=17
+ Console: colour dummy device 80x30
+ Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
+ pid_max: default: 32768 minimum: 301
+ Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
+ Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
+ CPU: Testing write buffer coherency: ok
+ CPU0: Spectre v2: using BPIALL workaround
+ CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
+ Setting up static identity map for 0x100000 - 0x100060
+ rcu: Hierarchical SRCU implementation.
+ smp: Bringing up secondary CPUs ...
+ CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
+ CPU1: Spectre v2: using BPIALL workaround
+ smp: Brought up 1 node, 2 CPUs
+ SMP: Total of 2 processors activated (1333.33 BogoMIPS).
+ CPU: All CPU(s) started in SVC mode.
+ devtmpfs: initialized
+ VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
+ clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
+ futex hash table entries: 512 (order: 3, 32768 bytes, linear)
+ pinctrl core: initialized pinctrl subsystem
+ NET: Registered protocol family 16
+ DMA: preallocated 256 KiB pool for atomic coherent allocations
+ hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
+ hw-breakpoint: maximum watchpoint size is 4 bytes.
+ zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
+ e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 25, base_baud = 3125000) is a xuartps
+ printk: console [ttyPS0] enabled
+ SCSI subsystem initialized
+ usbcore: registered new interface driver usbfs
+ usbcore: registered new interface driver hub
+ usbcore: registered new device driver usb
+ mc: Linux media interface: v0.10
+ videodev: Linux video capture interface: v2.00
+ jesd204: created con: id=0, topo=0, link=0, /amba/spi@e0007000/hmc7044@0 <-> /fpga-axi@0/axi-adxcvr-tx@44b60000
+ jesd204: created con: id=1, topo=0, link=2, /amba/spi@e0007000/hmc7044@0 <-> /fpga-axi@0/axi-adxcvr-rx@44a60000
+ jesd204: created con: id=2, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@44b60000 <-> /fpga-axi@0/axi-jesd204-tx@44b90000
+ jesd204: created con: id=3, topo=0, link=2, /fpga-axi@0/axi-adxcvr-rx@44a60000 <-> /fpga-axi@0/axi-jesd204-rx@44a90000
+ jesd204: created con: id=4, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@44b90000 <-> /fpga-axi@0/axi-ad9081-tx-hpc@44b10000
+ jesd204: created con: id=5, topo=0, link=2, /fpga-axi@0/axi-jesd204-rx@44a90000 <-> /fpga-axi@0/axi-ad9081-rx-hpc@44a10000
+ jesd204: created con: id=6, topo=0, link=2, /fpga-axi@0/axi-ad9081-rx-hpc@44a10000 <-> /amba/spi@e0006000/ad9081@0
+ jesd204: created con: id=7, topo=0, link=0, /fpga-axi@0/axi-ad9081-tx-hpc@44b10000 <-> /amba/spi@e0006000/ad9081@0
+ jesd204: /amba/spi@e0006000/ad9081@0: JESD204[2] transition uninitialized -> initialized
+ jesd204: /amba/spi@e0006000/ad9081@0: JESD204[0] transition uninitialized -> initialized
+ jesd204: found 8 devices and 1 topologies
+ FPGA manager framework
+ Advanced Linux Sound Architecture Driver Initialized.
+ clocksource: Switched to clocksource arm_global_timer
+ thermal_sys: Registered thermal governor 'step_wise'
+ NET: Registered protocol family 2
+ tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
+ TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear)
+ TCP bind hash table entries: 8192 (order: 4, 65536 bytes, linear)
+ TCP: Hash tables configured (established 8192 bind 8192)
+ UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
+ UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
+ NET: Registered protocol family 1
+ hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
+ hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
+ workingset: timestamp_bits=30 max_order=18 bucket_order=0
+ bounce: pool size: 64 pages
+ io scheduler mq-deadline registered
+ io scheduler kyber registered
+ zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
+ dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
+ dma-pl330 f8003000.dmac: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
+ brd: module loaded
+ loop: module loaded
+ Registered mathworks_ip class
+ spi-nor spi2.0: found s25fl128s1, expected n25q128a11
+ random: fast init done
+ spi-nor spi2.0: s25fl128s1 (32768 Kbytes)
+ 5 fixed-partitions partitions found on MTD device spi2.0
+ Creating 5 MTD partitions on "spi2.0":
+ 0x000000000000-0x000000500000 : "boot"
+ 0x000000500000-0x000000520000 : "bootenv"
+ 0x000000520000-0x000000540000 : "config"
+ 0x000000540000-0x000000fc0000 : "image"
+ 0x000000fc0000-0x000002000000 : "spare"
+ MACsec IEEE 802.1AE
+ libphy: Fixed MDIO Bus: probed
+ tun: Universal TUN/TAP device driver, 1.6
+ libphy: MACB_mii_bus: probed
+ Marvell 88E1116R e000b000.ethernet-ffffffff:07: attached PHY driver [Marvell 88E1116R] (mii_bus:phy_addr=e000b000.ethernet-ffffffff:07, irq=POLL)
+ macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 29 (00:0a:35:00:01:22)
+ usbcore: registered new interface driver asix
+ usbcore: registered new interface driver ax88179_178a
+ usbcore: registered new interface driver cdc_ether
+ usbcore: registered new interface driver net1080
+ usbcore: registered new interface driver cdc_subset
+ usbcore: registered new interface driver zaurus
+ usbcore: registered new interface driver cdc_ncm
+ ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
+ usbcore: registered new interface driver uas
+ usbcore: registered new interface driver usb-storage
+ usbcore: registered new interface driver usbserial_generic
+ usbserial: USB Serial support registered for generic
+ usbcore: registered new interface driver ftdi_sio
+ usbserial: USB Serial support registered for FTDI USB Serial Device
+ usbcore: registered new interface driver upd78f0730
+ usbserial: USB Serial support registered for upd78f0730
+ chipidea-usb2 e0002000.usb: e0002000.usb supply vbus not found, using dummy regulator
+ ULPI transceiver vendor/product ID 0x0424/0x0007
+ Found SMSC USB3320 ULPI transceiver.
+ ULPI integrity check: passed.
+ ci_hdrc ci_hdrc.0: EHCI Host Controller
+ ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
+ ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
+ usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.04
+ usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
+ usb usb1: Product: EHCI Host Controller
+ usb usb1: Manufacturer: Linux 5.4.0-93252-ga4800dc5737b ehci_hcd
+ usb usb1: SerialNumber: ci_hdrc.0
+ hub 1-0:1.0: USB hub found
+ hub 1-0:1.0: 1 port detected
+ i2c /dev entries driver
+ si570 1-005d: registered, current frequency 156250000 Hz
+ i2c i2c-0: Added multiplexed i2c bus 1
+ adv7511 2-0039: 2-0039 supply avdd not found, using dummy regulator
+ adv7511 2-0039: 2-0039 supply dvdd not found, using dummy regulator
+ adv7511 2-0039: 2-0039 supply pvdd not found, using dummy regulator
+ adv7511 2-0039: 2-0039 supply bgvdd not found, using dummy regulator
+ adv7511 2-0039: 2-0039 supply dvdd-3v not found, using dummy regulator
+ i2c i2c-0: Added multiplexed i2c bus 2
+ at24 3-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write
+ i2c i2c-0: Added multiplexed i2c bus 3
+ pca953x 4-0021: 4-0021 supply vcc not found, using dummy regulator
+ i2c i2c-0: Added multiplexed i2c bus 4
+ rtc-pcf8563 5-0051: registered as rtc0
+ i2c i2c-0: Added multiplexed i2c bus 5
+ at24 6-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
+ i2c i2c-0: Added multiplexed i2c bus 6
+ i2c i2c-0: Added multiplexed i2c bus 7
+ i2c i2c-0: Added multiplexed i2c bus 8
+ pca954x 0-0074: registered 8 multiplexed busses for I2C switch pca9548
+ usbcore: registered new interface driver uvcvideo
+ USB Video Class driver (1.1.1)
+ gspca_main: v2.14.0 registered
+ cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
+ Xilinx Zynq CpuIdle Driver started
+ failed to register cpuidle driver
+ sdhci: Secure Digital Host Controller Interface driver
+ sdhci: Copyright(c) Pierre Ossman
+ sdhci-pltfm: SDHCI platform and OF driver helper
+ mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
+ ledtrig-cpu: registered to indicate activity on CPUs
+ hidraw: raw HID events driver (C) Jiri Kosina
+ usbcore: registered new interface driver usbhid
+ usbhid: USB HID core driver
+ mmc0: new high speed SDHC card at address aaaa
+ mmcblk0: mmc0:aaaa SC32G 29.7 GiB
+ jesd204: /amba/spi@e0007000/hmc7044@0,jesd204:1,parent=spi1.0: Using as SYSREF provider
+ mmcblk0: p1 p2 p3
+ axi_adxcvr 44a60000.axi-adxcvr-rx: adxcvr_enforce_settings: Using QPLL without access, assuming desired Lane rate will be configured by a different instance
+ axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using QPLL on GTX2 at 0x44A60000. Number of lanes: 4.
+ axi_adxcvr 44b60000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using QPLL on GTX2 at 0x44B60000. Number of lanes: 4.
+ axi-jesd204-rx 44a90000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44A90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm.
+ axi-jesd204-tx 44b90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44B90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm.
+ axi_sysid 45000000.axi-sysid-0: AXI System ID core version (1.01.a) found
+ axi_sysid 45000000.axi-sysid-0: [ad9081_fmca_ebz] on [zc706] git branch git <1099badaf4f3621f9db1723a17d0dcd3dc74e26b> clean [2021-03-08 14:35:28] UTC
+ fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
+ usbcore: registered new interface driver snd-usb-audio
+ NET: Registered protocol family 10
+ Segment Routing with IPv6
+ sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+ NET: Registered protocol family 17
+ NET: Registered protocol family 36
+ Registering SWP/SWPB emulation handler
+ [drm] Cannot find any crtc or sizes
+ [drm] Initialized axi_hdmi_drm 1.0.0 20120930 for 70e00000.axi_hdmi on minor 0
+ ad9081 spi0.0: AD9081 Rev. 3 Grade 10 (API 1.1.0) probed
+ cf_axi_dds 44b10000.axi-ad9081-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44B10000 mapped to 0x(ptrval), probed DDS AD9081
+ asoc-simple-card adv7511_hdmi_snd: spdif-hifi <-> 75c00000.axi-spdif-tx mapping ok
+ cf_axi_adc 44a10000.axi-ad9081-rx-hpc: ADI AIM (10.01.b) at 0x44A10000 mapped to 0x(ptrval), probed ADC AD9081 as MASTER
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition initialized -> probed
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition initialized -> probed
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition probed -> idle
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition probed -> idle
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition idle -> device_init
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition idle -> device_init
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition device_init -> link_init
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition device_init -> link_init
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition link_init -> link_supported
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition link_init -> link_supported
+ hmc7044 spi1.0: hmc7044_jesd204_link_pre_setup: Link2 forcing continuous SYSREF mode
+ hmc7044 spi1.0: hmc7044_jesd204_link_pre_setup: Link0 forcing continuous SYSREF mode
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition link_supported -> link_pre_setup
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition link_supported -> link_pre_setup
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition link_pre_setup -> clk_sync_stage1
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition link_pre_setup -> clk_sync_stage1
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
+ [drm] Cannot find any crtc or sizes
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
+ [drm] Cannot find any crtc or sizes
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition clk_sync_stage3 -> link_setup
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition clk_sync_stage3 -> link_setup
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition link_setup -> opt_setup_stage1
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition link_setup -> opt_setup_stage1
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition opt_setup_stage1 -> opt_setup_stage2
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition opt_setup_stage2 -> opt_setup_stage3
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition opt_setup_stage3 -> opt_setup_stage4
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition opt_setup_stage4 -> opt_setup_stage5
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition opt_setup_stage5 -> clocks_enable
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition opt_setup_stage5 -> clocks_enable
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition clocks_enable -> link_enable
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition clocks_enable -> link_enable
+ ad9081 spi0.0: JESD RX (JTX) Link2 in DATA, SYNC deasserted, PLL locked, PHASE established, MODE valid
+ ad9081 spi0.0: JESD TX (JRX) Link0 0xF lanes in DATA
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition link_enable -> link_running
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition link_enable -> link_running
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[2] transition link_running -> opt_post_running_stage
+ jesd204: /amba/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0] transition link_running -> opt_post_running_stage
+ input: gpio_keys as /devices/soc0/gpio_keys/input/input0
+ rtc-pcf8563 5-0051: setting system clock to 2021-03-19T15:24:20 UTC (1616167460)
+ clk: Not disabling unused clocks
+ ALSA device list:
+ #0: HDMI monitor
+ EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
+ VFS: Mounted root (ext4 filesystem) on device 179:2.
+ devtmpfs: mounted
+ Freeing unused kernel memory: 1024K
+ Run /sbin/init as init process
+ systemd[1]: Failed to lookup module alias 'autofs4': Function not implemented
+ systemd[1]: systemd 241 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN2 +IDN -PCRE2)
+ systemd[1]: Detected architecture arm.
+
+ Welcome to Kuiper GNU/Linux 10 (buster)!
+
+ systemd[1]: Set hostname to .
+ systemd[1]: File /lib/systemd/system/systemd-journald.service:12 configures an IP firewall (IPAddressDeny=any), but the local system does not support BPF/cgroup based firewalling.
+ systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.)
+ systemd[1]: /etc/systemd/system/tof-server.service:1: Assignment outside of section. Ignoring.
+ systemd[1]: /etc/systemd/system/tof-server.service:2: Assignment outside of section. Ignoring.
+ random: systemd: uninitialized urandom read (16 bytes read)
+ random: systemd: uninitialized urandom read (16 bytes read)
+ systemd[1]: Reached target Swap.
+ [ OK ] Reached target Swap.
+ random: systemd: uninitialized urandom read (16 bytes read)
+ systemd[1]: Started Forward Password Requests to Wall Directory Watch.
+ [ OK ] Started Forward Password R�…uests to Wall Directory Watch.
+ systemd[1]: Listening on Journal Socket (/dev/log).
+ [ OK ] Listening on Journal Socket (/dev/log).
+ [ OK ] Listening on Journal Socket.
+ Starting Set the console keyboard layout...
+ Starting Load Kernel Modules...
+ [ OK ] Created slice User and Session Slice.
+ [ OK ] Listening on Syslog Socket.
+ Mounting RPC Pipe File System...
+ [ OK ] Listening on udev Control Socket.
+ [ OK ] Created slice system-getty.slice.
+ [ OK ] Listening on fsck to fsckd communication Socket.
+ [ OK ] Created slice system-serial\x2dgetty.slice.
+ [ OK ] Created slice system-systemd\x2dfsck.slice.
+ Starting Restore / save the current clock...
+ [ OK ] Listening on udev Kernel Socket.
+ Starting udev Coldplug all Devices...
+ Starting Journal Service...
+ [ OK ] Listening on initctl Compatibility Named Pipe.
+ [ OK ] Reached target Slices.
+ Mounting Kernel Debug File System...
+ [FAILED] Failed to start Load Kernel Modules.
+ See 'systemctl status systemd-modules-load.service' for details.
+ [ OK ] Started Set the console keyboard layout.
+ [ OK ] Started Journal Service.
+ [FAILED] Failed to mount RPC Pipe File System.
+ See 'systemctl status run-rpc_pipefs.mount' for details.
+ [DEPEND] Dependency failed for RPC �…curity service for NFS server.
+ [DEPEND] Dependency failed for RPC �…ice for NFS client and server.
+ [ OK ] Started Restore / save the current clock.
+ [ OK ] Mounted Kernel Debug File System.
+ Starting Remount Root and Kernel File Systems...
+ [ OK ] Reached target NFS client services.
+ [ OK ] Reached target Remote File Systems (Pre).
+ [ OK ] Reached target Remote File Systems.
+ Mounting Kernel Configuration File System..random: crng init done
+ random: 7 urandom warning(s) missed due to ratelimiting
+ .
+ Starting Apply Kernel Variables...
+ [ OK ] Mounted Kernel Configuration File System.
+ [ OK ] Started udev Coldplug all Devices.
+ [ OK ] Started Apply Kernel Variables.
+ Starting Helper to synchronize boot up for ifupdown...
+ [ OK ] Started Helper to synchronize boot up for ifupdown.
+ [ OK ] Started Remount Root and Kernel File Systems.
+ Starting Create System Users...
+ Starting Flush Journal to Persistent Storage...
+ Starting Load/Save Random Seed...
+ [ OK ] Started Create System Users.
+ [ OK ] Started Load/Save Random Seed.
+ Starting Create Static Device Nodes in /dev...
+ [ OK ] Started Flush Journal to Persistent Storage.
+ [ OK ] Started Create Static Device Nodes in /dev.
+ Starting udev Kernel Device Manager...
+ [ OK ] Reached target Local File Systems (Pre).
+ [ OK ] Started udev Kernel Device Manager.
+ Starting Show Plymouth Boot Screen...
+ [ OK ] Started Show Plymouth Boot Screen.
+ [ OK ] Reached target Local Encrypted Volumes.
+ [ OK ] Started Forward Password R�…s to Plymouth Directory Watch.
+ Starting Load Kernel Modules...
+ [ OK ] Found device /dev/ttyPS0.
+ [FAILED] Failed to start Load Kernel Modules.
+ See 'systemctl status systemd-modules-load.service' for details.
+ [ OK ] Found device /dev/disk/by-partuuid/18f1f9d5-01.
+ Starting File System Check�…isk/by-partuuid/18f1f9d5-01...
+ [ OK ] Started File System Check Daemon to report status.
+ [ OK ] Started File System Check �…/disk/by-partuuid/18f1f9d5-01.
+ Mounting /boot...
+ [ OK ] Mounted /boot.
+ [ OK ] Reached target Local File Systems.
+ Starting Raise network interfaces...
+ Starting Tell Plymouth To Write Out Runtime Data...
+ Starting Set console font and keymap...
+ Starting Create Volatile Files and Directories...
+ Starting Preprocess NFS configuration...
+ [ OK ] Started Tell Plymouth To Write Out Runtime Data.
+ [ OK ] Started Preprocess NFS configuration.
+ [ OK ] Started Set console font and keymap.
+ [ OK ] Started Create Volatile Files and Directories.
+ Starting Update UTMP about System Boot/Shutdown...
+ Starting Network Time Synchronization...
+ [ OK ] Started Update UTMP about System Boot/Shutdown.
+ Starting Load Kernel Modules...
+ Starting Tell Plymouth To Write Out Runtime Data...
+ [ OK ] Started Network Time Synchronization.
+ [ OK ] Started Raise network interfaces.
+ [ OK ] Started Tell Plymouth To Write Out Runtime Data.
+ [FAILED] Failed to start Load Kernel Modules.
+ See 'systemctl status systemd-modules-load.service' for details.
+ [ OK ] Reached target System Time Synchronized.
+ [ OK ] Reached target System Initialization.
+ [ OK ] Listening on D-Bus System Message Bus Socket.
+ [ OK ] Started Daily rotation of log files.
+ [ OK ] Started Daily apt download activities.
+ [ OK ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
+ [ OK ] Listening on triggerhappy.socket.
+ [ OK ] Listening on GPS (Global P�…ioning System) Daemon Sockets.
+ [ OK ] Listening on CUPS Scheduler.
+ [ OK ] Reached target Sockets.
+ [ OK ] Started Daily Cleanup of Temporary Directories.
+ [ OK ] Started Daily man-db regeneration.
+ [ OK ] Started Daily apt upgrade and clean activities.
+ [ OK ] Reached target Timers.
+ [ OK ] Started CUPS Scheduler.
+ [ OK ] Reached target Paths.
+ [ OK ] Reached target Basic System.
+ [ OK ] Started D-Bus System Message Bus.
+ [ OK ] Started tof-server.service.
+ Starting Avahi mDNS/DNS-SD Stack...
+ Starting rng-tools.service...
+ Starting dhcpcd on all interfaces...
+ Starting WPA supplicant...
+ Starting Login Service...
+ [ OK ] Started Regular background program processing daemon.
+ [ OK ] Started CUPS Scheduler.
+ [ OK ] Started Manage Sound Card State (restore and store).
+ Starting LSB: Switch to on�…nless shift key is pressed)...
+ Starting System Logging Service...
+ Starting Check for Raspberry Pi EEPROM updates...
+ Starting Disk Manager...
+ Starting Save/Restore Sound Card State...
+ Starting dphys-swapfile - �…unt, and delete a swap file...
+ Starting triggerhappy global hotkey daemon...
+ Starting Modem Manager...
+ [ OK ] Started System Logging Service.
+ [ OK ] Started triggerhappy global hotkey daemon.
+ [FAILED] Failed to start rng-tools.service.
+ See 'systemctl status rng-tools.service' for details.
+ [ OK ] Started dhcpcd on all interfaces.
+ [ OK ] Started Check for Raspberry Pi EEPROM updates.
+ [ OK ] Started Save/Restore Sound Card State.
+ [ OK ] Reached target Sound Card.
+ [ OK ] Started Login Service.
+ [ OK ] Started Avahi mDNS/DNS-SD Stack.
+ [ OK ] Started WPA supplicant.
+ Starting Authorization Manager...
+ [ OK ] Reached target Network.
+ Starting OpenBSD Secure Shell server...
+ Starting Permit User Sessions...
+ Starting HTTP based time synchronization tool...
+ Starting /etc/rc.local Compatibility...
+ [ OK ] Started IIO Daemon.
+ [ OK ] Started Make remote CUPS printers available locally.
+ [ OK ] Started LSB: Switch to ond�…(unless shift key is pressed).
+ [ OK ] Started HTTP based time synchronization tool.
+ [ OK ] Started Permit User Sessions.
+ [ OK ] Started /etc/rc.local Compatibility.
+ [ OK ] Started dphys-swapfile - s�…mount, and delete a swap file.
+ Starting Light Display Manager...
+ Starting Hold until boot process finishes up...
+ [ OK ] Started Authorization Manager.
+ [ OK ] Started OpenBSD Secure Shell server.
+ [ OK ] Started Modem Manager.
+
+ Raspbian GNU/Linux 10 analog ttyPS0
+
+ analog login: root (automatic login)
+
+ Last login: Fri Mar 19 15:23:10 GMT 2021 on ttyPS0
+ Linux analog 5.4.0-93252-ga4800dc5737b #2881 SMP PREEMPT Fri Mar 19 16:22:37 CET 2021 armv7l
+
+ The programs included with the Debian GNU/Linux system are free software;
+ the exact distribution terms for each program are described in the
+ individual files in /usr/share/doc/*/copyright.
+
+ Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
+ permitted by applicable law.
+ root@analog:~#
+
+Useful commands for the serial terminal
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The below commands are to be run in the serial terminal connected to the FPGA.
+
+**Login Information**
+
+user: analog
+password: analog
+
+To find out the IP of the FPGA board, run the following command and take the
+IP specified at "eth0 inet":
+
+.. shell::
+
+ $ifconfig
+
+To see the IIO devices detected, run:
+
+.. shell::
+
+ $iio_info | grep iio:device
+ iio:device0: xadc
+ iio:device1: hmc7044
+ iio:device2: axi-ad9081-tx-hpc (buffer capable)
+ iio:device3: axi-ad9081-rx-hpc (buffer capable)
+
+To see the EEPROM specifications, run:
+
+.. shell::
+
+ $fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
+
+To use the :dokuwiki:`JESD204 status utility `,
+run:
+
+.. shell::
+
+ $jesd_status
+
+All links should be in DATA without errors:
+
+.. shell::
+
+ $jesd_status -s
+ (DEVICES) Found 2 JESD204 Link Layer peripherals
+
+ (0): axi-jesd204-rx/44a90000.axi-jesd204-rx [*]
+ (1): axi-jesd204-tx/44b90000.axi-jesd204-tx
+
+ (STATUS)
+ Link is enabled
+ Link Status
+ Measured Link Clock 250.003
+ Reported Link Clock 250.000
+ Lane rate
+ Lane rate / 40
+ LMFC rate
+ SYSREF captured
+ SYSREF alignment error
+ SYNC~
+
+ (LANE STATUS)
+ Lane# 0 1 2 3
+ Errors 1 0 0 1
+ Latency (Multiframes/Octets) 1/33 1/34 1/32 1/32
+ CGS State DATA DATA DATA DATA
+ Initial Frame Sync Yes Yes Yes Yes
+ Initial Lane Alignment Sequence Yes Yes Yes Yes
+
+ F1axi-jesd204-rx/44a90000.axi-jesd204-rxF2axi-jesd204-tx/44b90000.axi-jesd204-txF9Quit
+
+Additionally, if running ``stty rows 30`` before running ``jesd_status``, you
+can expand the visible area of it and see more than 4 lanes.
+
+To power off the system, run the following command, and wait for the final
+message to be printed, then power off the FPGA board from the switch as well.
+
+.. shell::
+
+ $poweroff
+
+To reboot the system, run:
+
+.. shell::
+
+ $reboot
+
+.. important::
+
+ Even thought this is Linux, this is a persistent file systems. Care should
+ be taken not to corrupt the file system -- please shut down things, don't
+ just turn off the power switch. Depending on your monitor, the standard
+ power off could be hiding. You can do this from the terminal as well with
+ :code:`sudo shutdown -h now` or the above-mentioned command for powering
+ off.
+
+.. include:: ../../common/using-iio-osc.rst
+
+..
+ About the IIO devices
+ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+ TBD
+
+Using no-OS as software
+-------------------------------------------------------------------------------
+
+Necessary files
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The following files are needed for the system to boot:
+
+- HDL boot file: ``system_top.xsa``
+- no-OS project: :git-no-os:`projects/ad9081`
+
+Instructions on how to build the boot files from source can be found here:
+
+- :external+no-OS:doc:`projects/adc/ad9081`. More no-OS build
+ details at :external+no-OS:doc:`build_guide`.
+- :external+hdl:ref:`ad9081_fmca_ebz`. More HDL build details at
+ :external+hdl:ref:`build_hdl`.
+
+Required Software
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- AMD Xilinx Vivado and Vitis (downloading Vitis from
+ `here `_
+ will include Vivado as well)
+- An UART terminal (Putty/Tera Term/Minicom, etc.), Baud rate 115200 (8N1)
+
+Required Hardware
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- AMD Xilinx :xilinx:`ZC706` Rev 1.2 or higher FPGA board and its power supply
+- :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC evaluation board
+- 2x Micro-USB cables, one for UART and one for JTAG
+- (Optional) USB keyboard & mouse and a HDMI-compatible monitor
+
+More details as to why you need these, can be found at
+:ref:`ad9081 prerequisites`.
+
+Testing
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Creating the setup
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. image:: ../../images/ad9081-fmca-ebz-zc706.png
+ :width: 800
+
+Follow the steps in this order, to avoid damaging the components:
+
+#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the ZC706
+ **HPC** FMC socket
+#. Configure :xilinx:`ZC706`` for SD card boot mode (Set the jumpers:
+ The main one is: SW11 - Big Blue Switch in the middle, which controls the
+ Boot Mode, it needs to be set: **1: Up, 2: Up, 3: Up, 4: Up, 5: Down**.
+#. Connect USB UART (Mini-USB) to your host PC
+#. Connect USB JTAG (Mini-USB) to your host PC
+#. Turn on the power switch on the FPGA board
+#. Observe console output messages on your terminal (use the first ttyUSB or
+ COM port registered)
+
+Console output
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following is what is printed in the serial console, after you have
+connected to the proper ttyUSB or COM port:
+
+.. collapsible:: Complete boot log
+
+ ::
+
+ Xilinx Zynq First Stage Boot Loader
+
+..
+ TBD
+
+.. include:: ../../common/using-iio-osc.rst
diff --git a/docs/solutions/reference-designs/eval-ad9081/quickstart/zynqmp.rst b/docs/solutions/reference-designs/eval-ad9081/quickstart/zcu102.rst
similarity index 99%
rename from docs/solutions/reference-designs/eval-ad9081/quickstart/zynqmp.rst
rename to docs/solutions/reference-designs/eval-ad9081/quickstart/zcu102.rst
index 155d99874..98c5cdfc6 100644
--- a/docs/solutions/reference-designs/eval-ad9081/quickstart/zynqmp.rst
+++ b/docs/solutions/reference-designs/eval-ad9081/quickstart/zcu102.rst
@@ -1,16 +1,18 @@
-.. _ad9081 quickstart zynqmp:
+.. _ad9081 quickstart zcu102:
ZCU102 Quick start
===============================================================================
-.. image:: ../../images/ad9081_zcu102_setup.png
- :width: 800
-
This guide provides quick instructions on how to setup the
:adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` on:
- :xilinx:`ZCU102` FMC HPC0
+.. image:: ../../images/zcu102.jpg
+ :width: 900
+
+.. esd-warning::
+
Using Linux as software
-------------------------------------------------------------------------------
@@ -32,8 +34,8 @@ Instructions on how to manually build the boot files from source can be found
here:
- :ref:`linux-kernel zynqmp`
-- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build details at
- :external+hdl:ref:`build_hdl`.
+- :external+hdl:ref:`ad9081_fmca_ebz` build documentation. More HDL build
+ details at :external+hdl:ref:`build_hdl`.
Required Software
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -62,11 +64,8 @@ Testing
Creating the setup
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. image:: ../../images/zcu102.jpg
- :width: 900
-
-.. esd-warning::
-
+.. image:: ../../images/ad9081_zcu102_setup.png
+ :width: 800
In the following example, we will make a physical loopback between the ADC
and the DAC channels on the evaluation board, using SMA cables.
@@ -74,11 +73,15 @@ and the DAC channels on the evaluation board, using SMA cables.
Follow the steps in this order, to avoid damaging the components:
#. Connect the SMA cables ADC0-DAC0, ADC1-DAC1, ADC2-DAC2, ADC3-DAC3
-#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the
- FPGA carrier **HPC1** FMC1 socket
+#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the ZCU102
+ **HPC1** FMC1 socket
#. Insert SD card into the SD card socket on the FPGA
#. Configure :xilinx:`ZCU102` for SD card boot mode (mode SW6[4:1] switch in
the position **OFF,OFF,OFF,ON** as seen in the below picture)
+
+ .. image:: ../../images/zcu102_1p0_bootmode.jpg
+ :width: 400
+
#. Plug-in an Ethernet cable from your router/switch to the Ethernet port on
the FPGA board
#. Connect USB UART J83 (Micro USB) to your host PC
@@ -88,9 +91,6 @@ Follow the steps in this order, to avoid damaging the components:
#. Observe Kernel and serial console output messages on your terminal (use
the first ttyUSB or COM port registered)
-.. image:: ../../images/zcu102_1p0_bootmode.jpg
- :width: 400
-
Boot messages
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -1012,14 +1012,16 @@ To reboot the system, run:
be taken not to corrupt the file system -- please shut down things, don't
just turn off the power switch. Depending on your monitor, the standard
power off could be hiding. You can do this from the terminal as well with
- :code:`sudo shutdown -h now` or the above-mentioned command for powering off.
+ :code:`sudo shutdown -h now` or the above-mentioned command for powering
+ off.
.. include:: ../../common/using-iio-osc.rst
About the IIO devices
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-Main receivers RX1, RX2, RX3, and RX4 are handled by the axi-ad9081-rx-hpc IIO device.
+Main receivers RX1, RX2, RX3, and RX4 are handled by the axi-ad9081-rx-hpc IIO
+device.
Channels:
@@ -1074,19 +1076,17 @@ Testing
Creating the setup
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. image:: ../../images/zcu102.jpg
- :width: 900
-
-.. esd-warning::
+.. image:: ../../images/ad9081_zcu102_setup.png
+ :width: 800
Follow the steps in this order, to avoid damaging the components:
-#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the
- FPGA carrier **HPC1** FMC1 socket
+#. Connect the :adi:`EVAL-AD9081` / :adi:`EVAL-AD9082` FMC board to the ZCU102
+ **HPC1** FMC1 socket
#. Configure :xilinx:`ZCU102` for JTAG boot mode (mode SW6[4:1] switch in
the position **ON,ON,ON,ON**)
#. Connect USB UART J83 (Micro USB) to your host PC
-#. Connecy USB JTAG (Micro USB) to your host PC
+#. Connect USB JTAG (Micro USB) to your host PC
#. (Optional) Connect a monitor to the FPGA by HDMI, and a mouse and a keyboard
#. Turn on the power switch on the FPGA board
#. Observe console output messages on your terminal (use the first ttyUSB or
@@ -1103,3 +1103,8 @@ connected to the proper ttyUSB or COM port:
::
Xilinx Zynq MP First Stage Boot Loader
+
+..
+ TBD
+
+.. include:: ../../common/using-iio-osc.rst
diff --git a/docs/solutions/reference-designs/images/ad9081-fmca-ebz-zc706.png b/docs/solutions/reference-designs/images/ad9081-fmca-ebz-zc706.png
new file mode 100644
index 000000000..871f7a55e
--- /dev/null
+++ b/docs/solutions/reference-designs/images/ad9081-fmca-ebz-zc706.png
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:a3d5f688eeb3e64cf11d02aa12ebd9daa8afecd4bb2693949cee26a608b8b323
+size 353988
diff --git a/docs/solutions/reference-designs/images/ad9081_vcu118_setup.png b/docs/solutions/reference-designs/images/ad9081_vcu118_setup.png
new file mode 100644
index 000000000..363385beb
--- /dev/null
+++ b/docs/solutions/reference-designs/images/ad9081_vcu118_setup.png
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:4e17f854b6025cc3aa315979c48fb303fa278eb1273ff208835b67e4c6f60ec7
+size 338059
diff --git a/docs/solutions/reference-designs/images/vcu118.png b/docs/solutions/reference-designs/images/vcu118.png
new file mode 100644
index 000000000..d3e280a70
--- /dev/null
+++ b/docs/solutions/reference-designs/images/vcu118.png
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:f1fa6c7c06b2065d2c837e876c1096360cb72d0b49bc1c29c576b9277242972e
+size 461345
diff --git a/docs/solutions/reference-designs/images/zc706.png b/docs/solutions/reference-designs/images/zc706.png
new file mode 100644
index 000000000..519dff1f0
--- /dev/null
+++ b/docs/solutions/reference-designs/images/zc706.png
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:de5d78dc194d506299a62d62a10f4a9a66852c9a3b937e004535abacceb87224
+size 303508