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podgoripodgori
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axi_dmac: Default to 64 bit addressing
This commit increases the maximum address width of the DMA AXI interfaces to 64 to enable accessing the upper DDR memory regions of the 64 bit address spaces. Signed-off-by: Ionut Podgoreanu <[email protected]>
1 parent 083d801 commit 5533991

12 files changed

+25
-25
lines changed

‎docs/regmap/adi_regmap_dmac.txt

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@@ -9,7 +9,7 @@ ENDTITLE
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REG
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0x000
1111
VERSION
12-
Version of the peripheral. Follows semantic versioning. Current version 4.05.64.
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Version of the peripheral. Follows semantic versioning. Current version 4.05.65.
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ENDREG
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FIELD
@@ -25,7 +25,7 @@ RO
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ENDFIELD
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FIELD
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[7:0] 0x00000064
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[7:0] 0x00000065
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VERSION_PATCH
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RO
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ENDFIELD

‎library/axi_dmac/address_generator.v

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@@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
3-
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -39,7 +39,7 @@ module address_generator #(
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parameter ID_WIDTH = 3,
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parameter DMA_DATA_WIDTH = 64,
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parameter DMA_ADDR_WIDTH = 32,
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parameter DMA_ADDR_WIDTH = 64,
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parameter BEATS_PER_BURST_WIDTH = 4,
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parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8),
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parameter LENGTH_WIDTH = 8,

‎library/axi_dmac/axi_dmac.v

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@@ -1,6 +1,6 @@
11
// ***************************************************************************
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// ***************************************************************************
3-
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -60,7 +60,7 @@ module axi_dmac #(
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parameter DMA_AXI_PROTOCOL_SG = 0,
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parameter DMA_TYPE_DEST = 0,
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parameter DMA_TYPE_SRC = 2,
63-
parameter DMA_AXI_ADDR_WIDTH = 32,
63+
parameter DMA_AXI_ADDR_WIDTH = 64,
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parameter MAX_BYTES_PER_BURST = 128,
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parameter FIFO_SIZE = 8, // In bursts
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parameter AXI_ID_WIDTH_SRC = 1,

‎library/axi_dmac/axi_dmac_framelock.v

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@@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
3-
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -34,7 +34,7 @@
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// ***************************************************************************
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module axi_dmac_framelock #(
37-
parameter DMA_AXI_ADDR_WIDTH = 32,
37+
parameter DMA_AXI_ADDR_WIDTH = 64,
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parameter BYTES_PER_BEAT_WIDTH_DEST = 3,
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parameter BYTES_PER_BEAT_WIDTH_SRC = 3,
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parameter FRAMELOCK_MODE = 0, // 0 - MM writer ; 1 - MM reader

‎library/axi_dmac/axi_dmac_regmap.v

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@@ -1,6 +1,6 @@
11
// ***************************************************************************
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// ***************************************************************************
3-
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -44,7 +44,7 @@ module axi_dmac_regmap #(
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parameter BYTES_PER_BURST_WIDTH = 7,
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parameter DMA_TYPE_DEST = 0,
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parameter DMA_TYPE_SRC = 2,
47-
parameter DMA_AXI_ADDR_WIDTH = 32,
47+
parameter DMA_AXI_ADDR_WIDTH = 64,
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parameter DMA_LENGTH_WIDTH = 24,
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parameter DMA_LENGTH_ALIGN = 3,
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parameter DMA_CYCLIC = 0,
@@ -147,7 +147,7 @@ module axi_dmac_regmap #(
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input [31:0] dbg_ids1
148148
);
149149

150-
localparam PCORE_VERSION = 'h00040564;
150+
localparam PCORE_VERSION = 'h00040565;
151151
localparam HAS_ADDR_HIGH = DMA_AXI_ADDR_WIDTH > 32;
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localparam ADDR_LOW_MSB = HAS_ADDR_HIGH ? 31 : DMA_AXI_ADDR_WIDTH-1;
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‎library/axi_dmac/axi_dmac_regmap_request.v

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@@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
3-
// Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2018-2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -41,7 +41,7 @@ module axi_dmac_regmap_request #(
4141
parameter BYTES_PER_BEAT_WIDTH_SRC = 1,
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parameter BYTES_PER_BEAT_WIDTH_SG = 1,
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parameter BYTES_PER_BURST_WIDTH = 7,
44-
parameter DMA_AXI_ADDR_WIDTH = 32,
44+
parameter DMA_AXI_ADDR_WIDTH = 64,
4545
parameter DMA_LENGTH_WIDTH = 24,
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parameter DMA_LENGTH_ALIGN = 3,
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parameter DMA_CYCLIC = 0,

‎library/axi_dmac/axi_dmac_transfer.v

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@@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
3-
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -46,7 +46,7 @@ module axi_dmac_transfer #(
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parameter BYTES_PER_BEAT_WIDTH_SG = $clog2(DMA_DATA_WIDTH_SG/8),
4747
parameter DMA_TYPE_DEST = 0,
4848
parameter DMA_TYPE_SRC = 2,
49-
parameter DMA_AXI_ADDR_WIDTH = 32,
49+
parameter DMA_AXI_ADDR_WIDTH = 64,
5050
parameter DMA_2D_TRANSFER = 0,
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parameter DMA_2D_TLAST_MODE = 0,
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parameter DMA_SG_TRANSFER = 0,

‎library/axi_dmac/dest_axi_mm.v

Lines changed: 2 additions & 2 deletions
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@@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
3-
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -39,7 +39,7 @@ module dest_axi_mm #(
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4040
parameter ID_WIDTH = 3,
4141
parameter DMA_DATA_WIDTH = 64,
42-
parameter DMA_ADDR_WIDTH = 32,
42+
parameter DMA_ADDR_WIDTH = 64,
4343
parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8),
4444
parameter BEATS_PER_BURST_WIDTH = 4,
4545
parameter MAX_BYTES_PER_BURST = 128,

‎library/axi_dmac/dmac_2d_transfer.v

Lines changed: 2 additions & 2 deletions
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@@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
3-
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
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//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -38,7 +38,7 @@
3838
module dmac_2d_transfer #(
3939

4040
parameter DMA_2D_TLAST_MODE = 0, // 0 - End of Frame; 1 - End of Line
41-
parameter DMA_AXI_ADDR_WIDTH = 32,
41+
parameter DMA_AXI_ADDR_WIDTH = 64,
4242
parameter DMA_LENGTH_WIDTH = 24,
4343
parameter BYTES_PER_BURST_WIDTH = 7,
4444
parameter BYTES_PER_BEAT_WIDTH_SRC = 3,

‎library/axi_dmac/dmac_sg.v

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@@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
3-
// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -36,7 +36,7 @@
3636
`timescale 1ns/100ps
3737

3838
module dmac_sg #(
39-
parameter DMA_AXI_ADDR_WIDTH = 32,
39+
parameter DMA_AXI_ADDR_WIDTH = 64,
4040
parameter DMA_DATA_WIDTH = 64,
4141
parameter DMA_LENGTH_WIDTH = 24,
4242
parameter AXI_LENGTH_WIDTH = 8,

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