Skip to content

Commit 6d09b9a

Browse files
IuliaCMoldovanIuliaCMoldovan
committed
projects/cn0577 & library/axi_ltc2387: Add make parameters
- projects/cn0577: Added make parameters ADC_RES (the ADC input resolution) and TWOLANES (two-lane mode or one-lane mode). Also fixed the sysid parameters logging - library/axi_ltc2387/axi_ltc2387_if.v: Changed the parameter name RESOLUTION to ADC_RES, as it was redundant Signed-off-by: Iulia Moldovan <[email protected]>
1 parent 91c52c7 commit 6d09b9a

File tree

6 files changed

+51
-46
lines changed

6 files changed

+51
-46
lines changed

‎library/axi_ltc2387/axi_ltc2387.v‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -52,7 +52,7 @@ module axi_ltc2387 #(
5252
parameter OUT_RES = 32, // 32-bit for ADC_RES=18 or 16-bit for ADC_RES=16
5353
parameter TWOLANES = 1
5454
) (
55-
input delay_clk,
55+
input delay_clk,
5656

5757
// adc interface
5858

@@ -159,7 +159,7 @@ module axi_ltc2387 #(
159159
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
160160
.IO_DELAY_GROUP (IO_DELAY_GROUP),
161161
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
162-
.RESOLUTION (ADC_RES),
162+
.ADC_RES (ADC_RES),
163163
.IODELAY_CTRL (IODELAY_CTRL),
164164
.TWOLANES (TWOLANES)
165165
) i_if (

‎library/axi_ltc2387/axi_ltc2387_if.v‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -44,7 +44,7 @@ module axi_ltc2387_if #(
4444
parameter IODELAY_CTRL = 1,
4545
parameter DELAY_REFCLK_FREQUENCY = 200,
4646
parameter TWOLANES = 1, // 0 for one-lane, 1 for two lanes
47-
parameter RESOLUTION = 18 // 16 or 18 bits
47+
parameter ADC_RES = 18 // 16 or 18 bits
4848
) (
4949

5050
// delay interface
@@ -68,12 +68,12 @@ module axi_ltc2387_if #(
6868
input db_p,
6969
input db_n,
7070

71-
output reg adc_valid,
72-
output reg [RESOLUTION-1:0] adc_data
71+
output reg adc_valid,
72+
output reg [ADC_RES-1:0] adc_data
7373
);
7474

75-
localparam ONE_L_WIDTH = (RESOLUTION == 18) ? 9 : 8;
76-
localparam TWO_L_WIDTH = (RESOLUTION == 18) ? 5 : 4;
75+
localparam ONE_L_WIDTH = (ADC_RES == 18) ? 9 : 8;
76+
localparam TWO_L_WIDTH = (ADC_RES == 18) ? 5 : 4;
7777
localparam WIDTH = (TWOLANES == 0) ? ONE_L_WIDTH : TWO_L_WIDTH;
7878

7979
// internal wires
@@ -100,7 +100,7 @@ module axi_ltc2387_if #(
100100
adc_valid <= 1'b0;
101101
clk_gate_d <= {clk_gate_d[1:0], clk_gate};
102102
if (clk_gate_d[1] == 1'b1 && clk_gate_d[0] == 1'b0) begin
103-
if (RESOLUTION == 18) begin
103+
if (ADC_RES == 18) begin
104104
adc_data <= adc_data_int;
105105
adc_valid <= 1'b1;
106106
end else begin
@@ -139,7 +139,7 @@ module axi_ltc2387_if #(
139139
assign adc_data_int[1] = da_p_int_s;
140140
assign adc_data_int[0] = da_n_int_s;
141141
end else begin
142-
if (RESOLUTION == 18) begin
142+
if (ADC_RES == 18) begin
143143
assign adc_data_int[17] = adc_data_da_p[3];
144144
assign adc_data_int[16] = adc_data_db_p[3];
145145
assign adc_data_int[15] = adc_data_da_n[3];

‎library/axi_ltc2387/axi_ltc2387_ip.tcl‎

Lines changed: 2 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -38,8 +38,7 @@ ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 $cc
3838
ipx::infer_bus_interface dco_p xilinx.com:signal:clock_rtl:1.0 $cc
3939
ipx::infer_bus_interface dco_n xilinx.com:signal:clock_rtl:1.0 $cc
4040

41-
ipgui::add_static_text -name {Warning} -component $cc -parent $page0 -text {In one-lane mode, only 18-bit resolution is supported!
42-
Output data width (OUT_RES) depends on ADC_RES!}
41+
ipgui::add_static_text -name {Warning} -component $cc -parent $page0 -text {In one-lane mode, only 18-bit resolution is supported!}
4342

4443
ipx::add_user_parameter ADC_RES $cc
4544
set_property value_resolve_type user [ipx::get_user_parameters ADC_RES -of_objects $cc]
@@ -58,24 +57,6 @@ set_property -dict [list \
5857
"value_validation_list" "18 16" \
5958
] [ipx::get_user_parameters ADC_RES -of_objects $cc]
6059

61-
# OUT_RES depends on the value of ADC_RES, and is set in the project
62-
ipx::add_user_parameter OUT_RES $cc
63-
set_property value_resolve_type user [ipx::get_user_parameters OUT_RES -of_objects $cc]
64-
ipgui::add_param -name "OUT_RES" -component $cc -parent $page0
65-
set_property -dict [list \
66-
"display_name" "OUT_RES" \
67-
"layout" "horizontal" \
68-
"tooltip" "Output data width" \
69-
"widget" "radioGroup" \
70-
] [ipgui::get_guiparamspec -name "OUT_RES" -component $cc]
71-
72-
set_property -dict [list \
73-
"value" "32" \
74-
"value_format" "long" \
75-
"value_validation_type" "list" \
76-
"value_validation_list" "32 16" \
77-
] [ipx::get_user_parameters OUT_RES -of_objects $cc]
78-
7960
ipx::add_user_parameter TWOLANES $cc
8061
set_property value_resolve_type user [ipx::get_user_parameters TWOLANES -of_objects $cc]
8162
ipgui::add_param -name "TWOLANES" -component $cc -parent $page0

‎projects/cn0577/common/cn0577_bd.tcl‎

Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,21 @@
11
###############################################################################
2-
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
# ltc2387
6+
# env params
7+
8+
set ADC_RES $ad_project_params(ADC_RES); # ADC resolution; default 18 bits
9+
if {$ADC_RES == 16} {
10+
set OUT_RES 16
11+
} else {
12+
# if ADC_RES == 18
13+
set OUT_RES 32
14+
}
15+
set TWOLANES $ad_project_params(TWOLANES); # two-lane mode (1) or one-lane mode (0); default two-lane
16+
17+
# ltc2387 i/o
18+
719
create_bd_port -dir I ref_clk
820
create_bd_port -dir O sampling_clk
921
create_bd_port -dir I dco_p
@@ -18,9 +30,9 @@ create_bd_port -dir O clk_gate
1830
# adc peripheral
1931

2032
ad_ip_instance axi_ltc2387 axi_ltc2387
21-
ad_ip_parameter axi_ltc2387 CONFIG.ADC_RES 18
22-
ad_ip_parameter axi_ltc2387 CONFIG.OUT_RES 32
23-
ad_ip_parameter axi_ltc2387 CONFIG.TWOLANES $two_lanes
33+
ad_ip_parameter axi_ltc2387 CONFIG.ADC_RES $ADC_RES
34+
ad_ip_parameter axi_ltc2387 CONFIG.OUT_RES $OUT_RES
35+
ad_ip_parameter axi_ltc2387 CONFIG.TWOLANES $TWOLANES
2436
ad_ip_parameter axi_ltc2387 CONFIG.ADC_INIT_DELAY 27
2537

2638
# axi pwm gen
@@ -43,7 +55,7 @@ ad_ip_parameter axi_ltc2387_dma CONFIG.SYNC_TRANSFER_START 0
4355
ad_ip_parameter axi_ltc2387_dma CONFIG.AXI_SLICE_SRC 0
4456
ad_ip_parameter axi_ltc2387_dma CONFIG.AXI_SLICE_DEST 0
4557
ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_2D_TRANSFER 0
46-
ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_SRC 32
58+
ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_SRC $OUT_RES
4759
ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_DEST 64
4860

4961
# connections

‎projects/cn0577/zed/system_bd.tcl‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,8 @@
11
###############################################################################
2-
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
# specify number of channels - the design supports one lane/two lanes
7-
set two_lanes 1
8-
96
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
107
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
118
source ../common/cn0577_bd.tcl
@@ -15,6 +12,7 @@ ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
1512
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
1613
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
1714

18-
set sys_cstring "TWO_LANES=$two_lanes"
15+
set sys_cstring "TWOLANES=$ad_project_params(TWOLANES) \
16+
ADC_RES=$ad_project_params(ADC_RES)"
1917

2018
sysid_gen_sys_init_file $sys_cstring

‎projects/cn0577/zed/system_project.tcl‎

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,28 @@
11
###############################################################################
2-
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
# load script
6+
# load scripts
77
source ../../../scripts/adi_env.tcl
88
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
99
source $ad_hdl_dir/projects/scripts/adi_board.tcl
1010

11-
adi_project cn0577_zed
11+
# TWOLANES: parameter describing the number of lanes
12+
# - 1: in two-lane mode (default)
13+
# - 0: in one-lane mode
14+
#
15+
# ADC_RES: parameter describing the ADC input resolution
16+
# - 18: 18 bits (default)
17+
# - 16: 16 bits
18+
#
19+
# in one-lane mode (TWOLANES=0), only the 18-bit resolution is supported! (ADC_RES=16)
20+
21+
adi_project cn0577_zed 0 [list \
22+
TWOLANES [get_env_param TWOLANES 1 ] \
23+
ADC_RES [get_env_param ADC_RES 18 ] \
24+
]
25+
1226
adi_project_files cn0577_zed [list \
1327
"system_top.v" \
1428
"system_constr.xdc" \

0 commit comments

Comments
 (0)