From 15e9ec7b1eae12ae6132782f2416b170c7a19867 Mon Sep 17 00:00:00 2001 From: Laez Barbosa Date: Thu, 21 Aug 2025 10:34:44 -0300 Subject: [PATCH 1/2] library/spi_engine, library/util_sigma_delta_spi: remove spi active Remove the active signal from the SPI Engine, which was used in util_sigma_delta_spi as a necessary condition to generating triggers. This signal was the last vestige that made the use of the SPI Engine SYNC instruction necessary. Now this instruction is completely optional. Signed-off-by: Laez Barbosa --- .../spi_engine/spi_engine_execution.rst | 5 ----- docs/library/util_sigma_delta_spi/index.rst | 3 +-- .../spi_engine_execution.v | 13 ----------- .../spi_engine_execution_hw.tcl | 2 -- .../util_sigma_delta_spi.v | 22 +++++++++---------- .../util_sigma_delta_spi_hw.tcl | 1 - .../common/ad411x_ad717x_asdz_qsys.tcl | 1 - projects/cn0363/common/cn0363_bd.tcl | 1 - 8 files changed, 11 insertions(+), 37 deletions(-) diff --git a/docs/library/spi_engine/spi_engine_execution.rst b/docs/library/spi_engine/spi_engine_execution.rst index b8dcc524bf9..919dd7400fc 100644 --- a/docs/library/spi_engine/spi_engine_execution.rst +++ b/docs/library/spi_engine/spi_engine_execution.rst @@ -52,9 +52,6 @@ Signal and Interface Pins - All other signals are synchronous to this clock. * - resetn - Resets the internal state machine of the core. - * - active - - Indicates whether the peripheral is currently active and processing - commands. * - ctrl - :ref:`spi_engine control-interface` subordinate. SPI Engine Control stream that contains commands and data for the @@ -72,8 +69,6 @@ SPI Engine command stream into low-level SPI bus access. Communication with a command stream generator happens via the ``ctrl`` interface and the low-level SPI access is handled on the ``spi`` interface. -The ``active`` signal is asserted as long as the peripheral is busy executing -incoming commands. Internally the SPI Engine execution module consists of an instruction encoder that translates the incoming commands into an internal control signal, a diff --git a/docs/library/util_sigma_delta_spi/index.rst b/docs/library/util_sigma_delta_spi/index.rst index f798f385f9e..9b61c7fddff 100644 --- a/docs/library/util_sigma_delta_spi/index.rst +++ b/docs/library/util_sigma_delta_spi/index.rst @@ -58,8 +58,7 @@ the ADC, or it can be connected to a HDL block, like the transaction to read the converted signal. The data ready condition is only detected if the chip-select signal (which is -connected to the converter) is asserted and the ``spi_active`` signal is -de-asserted and both signals have been in that state for **at least** +connected to the converter) is asserted has been in that state for **at least** ``IDLE_TIMEOUT`` clock cycles. The timeout is used to avoid spurious signal detection and the ``IDLE_TIMEOUT`` diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution.v b/library/spi_engine/spi_engine_execution/spi_engine_execution.v index f64c1155f55..ea69d7008bb 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution.v +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution.v @@ -49,8 +49,6 @@ module spi_engine_execution #( input clk, input resetn, - output reg active, - output cmd_ready, input cmd_valid, input [15:0] cmd, @@ -227,17 +225,6 @@ module spi_engine_execution #( cmd_d1 <= cmd; end - always @(posedge clk) begin - if (resetn == 1'b0) begin - active <= 1'b0; - end else begin - if (exec_cmd == 1'b1) - active <= 1'b1; - else if (sync_ready == 1'b1 && sync_valid == 1'b1) - active <= 1'b0; - end - end - // Load the interface configurations from the 'Configuration Write' // instruction always @(posedge clk) begin diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl b/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl index 85385a42a0c..4a3c307ce91 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl @@ -34,8 +34,6 @@ proc p_elaboration {} { ad_interface clock clk input 1 ad_interface reset resetn input 1 if_clk - ad_interface signal active output 1 - # command interface add_interface cmd axi4stream end diff --git a/library/util_sigma_delta_spi/util_sigma_delta_spi.v b/library/util_sigma_delta_spi/util_sigma_delta_spi.v index 9a0b077a76a..9ec5a5d8836 100644 --- a/library/util_sigma_delta_spi/util_sigma_delta_spi.v +++ b/library/util_sigma_delta_spi/util_sigma_delta_spi.v @@ -44,8 +44,6 @@ module util_sigma_delta_spi #( input clk, input resetn, - input spi_active, - input s_sclk, input s_sdo, input s_sdo_t, @@ -62,15 +60,15 @@ module util_sigma_delta_spi #( ); /* - * For converters from the ADI SigmaDelta family the data ready interrupt signal - * uses the same physical wire as the the DOUT signal for the SPI bus. This - * module extracts the data ready signal from the SPI bus and makes sure to - * suppress false positives. The data ready signal is indicated by the converter - * by pulling DOUT low. This will only happen if the CS pin for the converter is - * low and no SPI transfer is active. There is a small delay between the end of - * the SPI transfer and the point where the converter starts to indicate the - * data ready signal. IDLE_TIMEOUT allows to specify the amount of clock cycles - * the bus needs to be idle before the data ready signal is detected. + * For converters from the ADI SigmaDelta family the data ready interrupt + * signal uses the same physical wire as the the DOUT signal for the SPI bus. + * This module extracts the data ready signal from the SPI bus and makes sure + * to suppress false positives. The data ready signal is indicated by the + * converter by pulling DOUT low. This will only happen if the CS pin for the + * converter is low. There is a small delay between the end of the SPI transfer + * and the point where the converter starts to indicate the data ready signal. + * IDLE_TIMEOUT allows to specify the amount of clock cycles the bus needs to + * be idle before the data ready signal is detected. */ assign m_sclk = s_sclk; @@ -86,7 +84,7 @@ module util_sigma_delta_spi #( if (resetn == 1'b0) begin counter <= IDLE_TIMEOUT; end else begin - if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin + if (s_cs[CS_PIN] == 1'b0) begin if (counter != 'h00) counter <= counter - 1'b1; end else begin diff --git a/library/util_sigma_delta_spi/util_sigma_delta_spi_hw.tcl b/library/util_sigma_delta_spi/util_sigma_delta_spi_hw.tcl index 38d44d5c401..1f6b8a405e6 100644 --- a/library/util_sigma_delta_spi/util_sigma_delta_spi_hw.tcl +++ b/library/util_sigma_delta_spi/util_sigma_delta_spi_hw.tcl @@ -30,7 +30,6 @@ proc p_elaboration {} { ad_interface clock clk input 1 ad_interface reset resetn input 1 if_clk - ad_interface signal spi_active input 1 active ad_interface signal data_ready output 1 if_pwm ad_interface clock s_sclk input 1 sclk diff --git a/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl b/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl index db6df8bfb4a..6f1c5d6e761 100644 --- a/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl +++ b/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl @@ -78,7 +78,6 @@ add_connection spi_engine_execution_0.if_sdi util_sigma_delta_spi.if_s_sdi add_connection spi_engine_execution_0.if_sdo util_sigma_delta_spi.if_s_sdo add_connection spi_engine_execution_0.if_sdo_t util_sigma_delta_spi.if_s_sdo_t add_connection spi_engine_offload_0.if_trigger util_sigma_delta_spi.if_data_ready -add_connection spi_engine_execution_0.if_active util_sigma_delta_spi.if_spi_active # add_connection axi_spi_engine_0. diff --git a/projects/cn0363/common/cn0363_bd.tcl b/projects/cn0363/common/cn0363_bd.tcl index 9b703ce5f4b..0955c77ae58 100644 --- a/projects/cn0363/common/cn0363_bd.tcl +++ b/projects/cn0363/common/cn0363_bd.tcl @@ -70,7 +70,6 @@ ad_connect util_sigma_delta_spi/resetn $hier_spi_engine/resetn ad_connect $hier_spi_engine/m_spi util_sigma_delta_spi/s_spi ad_connect util_sigma_delta_spi/data_ready $hier_spi_engine/trigger -ad_connect $hier_spi_engine/${hier_spi_engine}_execution/active util_sigma_delta_spi/spi_active ad_connect util_sigma_delta_spi/m_spi spi ad_ip_instance c_counter_binary phase_gen From c19d4401bb73010bfdbcb0d24b0162699bc5ff2e Mon Sep 17 00:00:00 2001 From: Laez Barbosa Date: Tue, 9 Sep 2025 09:31:12 -0300 Subject: [PATCH 2/2] Update version reg Signed-off-by: Laez Barbosa --- docs/regmap/adi_regmap_spi_engine.txt | 6 +++--- library/spi_engine/axi_spi_engine/axi_spi_engine.v | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/regmap/adi_regmap_spi_engine.txt b/docs/regmap/adi_regmap_spi_engine.txt index 5cd86d6f9ef..846522dbe53 100644 --- a/docs/regmap/adi_regmap_spi_engine.txt +++ b/docs/regmap/adi_regmap_spi_engine.txt @@ -13,19 +13,19 @@ Version of the peripheral. Follows semantic versioning. Current version 1.04.02. ENDREG FIELD -[31:16] 0x00000001 +[31:16] 0x0001 VERSION_MAJOR RO ENDFIELD FIELD -[15:8] 0x00000005 +[15:8] 0x05 VERSION_MINOR RO ENDFIELD FIELD -[7:0] 0x00000001 +[7:0] 0x03 VERSION_PATCH RO ENDFIELD diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v index 378b982007a..628595b0c88 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v @@ -133,7 +133,7 @@ module axi_spi_engine #( input [7:0] offload_sync_data ); - localparam PCORE_VERSION = 'h010501; + localparam PCORE_VERSION = 'h010503; localparam S_AXI = 0; localparam UP_FIFO = 1;