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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
| 2 | +/* |
| 3 | + * Analog Devices ADAQ23878 |
| 4 | + * |
| 5 | + * hdl_project: <adaq2387x/zed> |
| 6 | + * for all config modes, please check the README of the HDL project |
| 7 | + * board_revision: <A> |
| 8 | + * |
| 9 | + * Copyright (C) 2022 - 2025 Analog Devices Inc. |
| 10 | + */ |
| 11 | +/dts-v1/; |
| 12 | + |
| 13 | +#include "zynq-zed.dtsi" |
| 14 | +#include "zynq-zed-adv7511.dtsi" |
| 15 | +#include <dt-bindings/gpio/gpio.h> |
| 16 | +#include <dt-bindings/pwm/pwm.h> |
| 17 | + |
| 18 | +/ { |
| 19 | + vref: regulator-vref { |
| 20 | + compatible = "regulator-fixed"; |
| 21 | + regulator-name = "fixed-supply"; |
| 22 | + regulator-min-microvolt = <4096000>; |
| 23 | + regulator-max-microvolt = <4096000>; |
| 24 | + regulator-always-on; |
| 25 | + }; |
| 26 | + |
| 27 | + clocks { |
| 28 | + ext_clk: clock@0 { |
| 29 | + #clock-cells = <0>; |
| 30 | + compatible = "fixed-clock"; |
| 31 | + clock-frequency = <100000000>; |
| 32 | + }; |
| 33 | + }; |
| 34 | + gpio-control@0 { |
| 35 | + compatible = "adi,one-bit-adc-dac"; |
| 36 | + #address-cells = <1>; |
| 37 | + #size-cells = <0>; |
| 38 | + out-gpios = <&gpio0 86 GPIO_ACTIVE_HIGH>, |
| 39 | + <&gpio0 87 GPIO_ACTIVE_HIGH>; |
| 40 | + channel@0 { |
| 41 | + reg = <0>; |
| 42 | + label = "adaq23878_testpat"; |
| 43 | + }; |
| 44 | + channel@1 { |
| 45 | + reg = <1>; |
| 46 | + label = "adaq23878_pd"; |
| 47 | + }; |
| 48 | + }; |
| 49 | +}; |
| 50 | + |
| 51 | +&fpga_axi { |
| 52 | + rx_dma: dma-controller@44a30000 { |
| 53 | + compatible = "adi,axi-dmac-1.00.a"; |
| 54 | + reg = <0x44a30000 0x1000>; |
| 55 | + #dma-cells = <1>; |
| 56 | + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
| 57 | + clocks = <&clkc 15>; |
| 58 | + |
| 59 | + adi,channels { |
| 60 | + #size-cells = <0>; |
| 61 | + #address-cells = <1>; |
| 62 | + |
| 63 | + dma-channel@0 { |
| 64 | + reg = <0>; |
| 65 | + adi,source-bus-width = <32>; |
| 66 | + adi,source-bus-type = <2>; |
| 67 | + adi,destination-bus-width = <64>; |
| 68 | + adi,destination-bus-type = <0>; |
| 69 | + }; |
| 70 | + }; |
| 71 | + }; |
| 72 | + |
| 73 | + axi_pwm_gen: pwm@44a60000 { |
| 74 | + compatible = "adi,axi-pwmgen-2.00.a"; |
| 75 | + reg = <0x44a60000 0x1000>; |
| 76 | + label = "adaq23878_if"; |
| 77 | + #pwm-cells = <2>; |
| 78 | + clocks = <&clkc 15>, <&ext_clk>; |
| 79 | + clock-names = "axi", "ext"; |
| 80 | + }; |
| 81 | + |
| 82 | + adaq23878@0{ |
| 83 | + compatible = "adaq23878"; |
| 84 | + clocks = <&ext_clk>; |
| 85 | + dmas = <&rx_dma 0>; |
| 86 | + dma-names = "rx"; |
| 87 | + pwms = <&axi_pwm_gen 0 0 |
| 88 | + &axi_pwm_gen 1 0>; |
| 89 | + pwm-names = "cnv", "clk_en"; |
| 90 | + vref-supply = <&vref>; |
| 91 | + |
| 92 | + // uncomment the below command to use in one lane mode |
| 93 | + // adi,use-one-lane; |
| 94 | + }; |
| 95 | +}; |
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