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Merge branch 'refs/heads/main' into feat/flux_lines_plot
2 parents 69c4690 + 3b22d74 commit 781dd94

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+81
-40
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7 files changed

+81
-40
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doc/changelog.d/6599.added.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
Added offset to page port creation during connect_to_component.

doc/changelog.d/6600.fixed.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
Circuit config fixes

src/ansys/aedt/core/generic/configurations.py

Lines changed: 43 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -21,11 +21,11 @@
2121
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
2222
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
2323
# SOFTWARE.
24-
2524
from collections import defaultdict
2625
import copy
2726
from datetime import datetime
2827
import json
28+
import math
2929
import os
3030
from pathlib import Path
3131
import tempfile
@@ -2216,7 +2216,7 @@ def export_config(self, config_file=None, overwrite=False):
22162216
getattr(self, key)(dict_out) # Call private export method to update dict_out.
22172217

22182218
pin_mapping = defaultdict(list)
2219-
data_refdes = {}
2219+
data_instance = {}
22202220
data_models = {}
22212221
pin_nets = {}
22222222
skip_list = [
@@ -2242,21 +2242,22 @@ def export_config(self, config_file=None, overwrite=False):
22422242
"IBIS_Model_Text",
22432243
"aminetlist_example_model_rx",
22442244
"CoSimulator",
2245+
"source_name",
22452246
]
22462247
for comp in list(self._app.modeler.schematic.components.values()):
2248+
if not comp.component_info:
2249+
continue
2250+
else:
2251+
component = comp.component_info["Component"]
22472252
properties = {}
22482253
num_terminals = None
2249-
refdes = comp.refdes
2254+
instance = comp.parameters["InstanceName"]
22502255
position = comp.location
22512256
angle = comp.angle
22522257
mirror = comp.mirror
22532258
parameters = comp.parameters
2254-
if not comp.component_info:
2255-
continue
2256-
else:
2257-
component = comp.component_info["Component"]
22582259
path = comp.component_path
2259-
port_names = None
2260+
port_names = []
22602261
if not path:
22612262
component_type = "Nexxim Component"
22622263
path = ""
@@ -2283,9 +2284,9 @@ def export_config(self, config_file=None, overwrite=False):
22832284
elif path[-4:] == ".sss":
22842285
component_type = "nexxim state space"
22852286
num_terminals = comp.model_data.props["numberofports"]
2286-
port_names = comp.model_data.props["PortNames"]
22872287

22882288
for pin in comp.pins:
2289+
port_names.append(pin.name)
22892290
if pin.net == "0":
22902291
net = "gnd"
22912292
else:
@@ -2294,15 +2295,15 @@ def export_config(self, config_file=None, overwrite=False):
22942295
pin_nets.update(temp_dict)
22952296

22962297
temp_dict2 = {
2297-
refdes: {
2298+
instance: {
22982299
"component": component,
22992300
"properties": properties,
23002301
"position": position,
23012302
"angle": angle,
23022303
"mirror": mirror,
23032304
}
23042305
}
2305-
data_refdes.update(temp_dict2)
2306+
data_instance.update(temp_dict2)
23062307
if "$PROJECTDIR" in path:
23072308
path = path.replace("$PROJECTDIR", self._app.project_path)
23082309
elif "<Project>" in path:
@@ -2322,10 +2323,10 @@ def export_config(self, config_file=None, overwrite=False):
23222323
for key, values in pin_mapping.items():
23232324
temp_dict3 = {}
23242325
for value in values:
2325-
if value._circuit_comp.refdes in temp_dict3:
2326-
temp_dict3[value._circuit_comp.refdes].append(value.name)
2326+
if value._circuit_comp.parameters["InstanceName"] in temp_dict3:
2327+
temp_dict3[value._circuit_comp.parameters["InstanceName"]].append(value.name)
23272328
else:
2328-
temp_dict3.update({value._circuit_comp.refdes: [value.name]})
2329+
temp_dict3.update({value._circuit_comp.parameters["InstanceName"]: [value.name]})
23292330
pin_mapping[key] = temp_dict3
23302331

23312332
port_dict = {}
@@ -2339,7 +2340,7 @@ def export_config(self, config_file=None, overwrite=False):
23392340
del pin_mapping[key]
23402341

23412342
dict_out.update(
2342-
{"models": data_models, "refdes": data_refdes, "pin_mapping": pin_mapping, "ports": port_dict}
2343+
{"models": data_models, "instance": data_instance, "pin_mapping": pin_mapping, "ports": port_dict}
23432344
) # Call private export method to update dict_out.
23442345

23452346
# update the json if it exists already
@@ -2385,7 +2386,10 @@ def import_config(self, config_file, *args):
23852386
self.results._reset_results()
23862387

23872388
data = read_configuration_file(config_file)
2388-
2389+
try:
2390+
offset = data["general"]["port_offset"]
2391+
except KeyError:
2392+
offset = 0
23892393
if self.options.import_variables:
23902394
try:
23912395
for k, v in data["general"]["variables"].items():
@@ -2402,7 +2406,7 @@ def import_config(self, config_file, *args):
24022406
else:
24032407
self.results.import_postprocessing_variables = True
24042408

2405-
for i, j in data["refdes"].items():
2409+
for i, j in data["instance"].items():
24062410
for key, value in data["models"].items():
24072411
if key == j["component"]:
24082412
component_type = value["component_type"]
@@ -2441,6 +2445,8 @@ def import_config(self, config_file, *args):
24412445
new_comp = self._app.modeler.schematic.create_touchstone_component(
24422446
value["file_path"], location=j["position"], angle=j["angle"]
24432447
)
2448+
for pin in new_comp.pins:
2449+
pin.name = value["port_names"][pin.pin_number - 1]
24442450
elif component_type == "spice":
24452451
new_comp = self._app.modeler.schematic.create_component_from_spicemodel(
24462452
input_file=value["file_path"], location=j["position"]
@@ -2455,6 +2461,8 @@ def import_config(self, config_file, *args):
24552461
)
24562462
if not new_comp: # pragma: no cover
24572463
continue
2464+
else:
2465+
new_comp.parameters["InstanceName"] = i
24582466
# reorder pin positions for spice or nexxim state space components or touchstone components
24592467
if (
24602468
value.get("pin_locations", {})
@@ -2474,7 +2482,7 @@ def import_config(self, config_file, *args):
24742482
pins = []
24752483
for key, value in j.items():
24762484
for comp in comp_list:
2477-
if comp.refdes == key:
2485+
if comp.parameters["InstanceName"] == key:
24782486
for pin in comp.pins:
24792487
if pin.name in value:
24802488
pins.append(pin)
@@ -2483,15 +2491,29 @@ def import_config(self, config_file, *args):
24832491
location = [x - y for x, y in zip(gnd_pin.location, [0, 0.00254])]
24842492
self._app.modeler.schematic.create_gnd(location, page=i)
24852493
elif len(pins) > 1:
2486-
pins[0].connect_to_component(pins[1:], page_name=i)
2494+
pins[0].connect_to_component(pins[1:], page_name=i, offset=offset)
24872495

24882496
for i, j in data["ports"].items():
2497+
created = False
24892498
for key, value in j.items():
24902499
for comp in comp_list:
2491-
if comp.refdes == key:
2500+
if comp.parameters["InstanceName"] == key:
24922501
for pin in comp.pins:
24932502
if pin.name in value:
2494-
self._app.modeler.schematic.create_interface_port(name=i, location=pin.location)
2503+
location = [
2504+
pin.location[0] - offset * math.cos(pin.total_angle * math.pi / 180),
2505+
pin.location[1] - offset * math.sin(pin.total_angle * math.pi / 180),
2506+
]
2507+
2508+
if not created:
2509+
self._app.modeler.schematic.create_interface_port(name=i, location=location)
2510+
created = True
2511+
else:
2512+
self._app.modeler.schematic.create_page_port(
2513+
name=i, location=location, angle=pin.total_angle
2514+
)
2515+
if offset != 0:
2516+
self._app.modeler.schematic.create_wire([location, pin.location])
24952517

24962518
if self.options.import_setups and data.get("setups", None):
24972519
self.results.import_setup = True

src/ansys/aedt/core/modeler/circuits/object_3d_circuit.py

Lines changed: 33 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@
3131
from ansys.aedt.core.generic.general_methods import pyaedt_function_handler
3232
from ansys.aedt.core.generic.numbers_utils import decompose_variable_value
3333
from ansys.aedt.core.generic.settings import settings
34+
from ansys.aedt.core.modeler.geometry_operators import GeometryOperators
3435
from ansys.aedt.core.modeler.geometry_operators import GeometryOperators as go
3536

3637

@@ -48,6 +49,11 @@ def units(self):
4849
"""Length units."""
4950
return self._circuit_comp.units
5051

52+
@property
53+
def total_angle(self):
54+
"""Return the pin orientation in the schematic."""
55+
return int(self.angle + self._circuit_comp.angle)
56+
5157
@property
5258
def location(self):
5359
"""Pin Position in [x,y] format.
@@ -152,7 +158,14 @@ def _get_deltas(self, point, move_x=True, move_y=True, positive=True, units=1):
152158

153159
@pyaedt_function_handler(component_pin="assignment")
154160
def connect_to_component(
155-
self, assignment, page_name=None, use_wire=False, wire_name="", clearance_units=1, page_port_angle=None
161+
self,
162+
assignment,
163+
page_name=None,
164+
use_wire=False,
165+
wire_name="",
166+
clearance_units=1,
167+
page_port_angle=None,
168+
offset=0,
156169
):
157170
"""Connect schematic components.
158171
@@ -174,6 +187,8 @@ def connect_to_component(
174187
page_port_angle : int, optional
175188
Page port angle on the source pin. The default is ``None``, in which case
176189
the angle is automatically computed.
190+
offset : float, optional
191+
Page port offset in the direction of the pin. The default is ``0``.
177192
178193
Returns
179194
-------
@@ -274,11 +289,7 @@ def connect_to_component(
274289
if page_name is None:
275290
page_name = f"{self._circuit_comp.composed_name.replace('CompInst@', '').replace(';', '_')}_{self.name}"
276291

277-
if (
278-
len(assignment) == 1
279-
and (abs(self.location[1] - assignment[0].location[1]) + abs(self.location[0] - assignment[0].location[0]))
280-
< 0.01524
281-
):
292+
if len(assignment) == 1 and GeometryOperators.points_distance(self.location, assignment[0].location) < 0.01524:
282293
self._circuit_comp._circuit_components.create_wire([self.location, assignment[0].location], name=page_name)
283294
return True
284295
if "Port" in self._circuit_comp.composed_name:
@@ -296,19 +307,25 @@ def connect_to_component(
296307
self._component._circuit_components.logger.debug(
297308
"Cannot parse page name from circuit component name"
298309
)
299-
if self.location[0] > self._circuit_comp.location[0]:
300-
angle = 180
301-
else:
302-
angle = 0
303-
ret1 = self._circuit_comp._circuit_components.create_page_port(page_name, self.location, angle=angle)
310+
angle = page_port_angle if page_port_angle else self.total_angle
311+
location = [
312+
self.location[0] - offset * math.cos(self.total_angle * math.pi / 180),
313+
self.location[1] - offset * math.sin(self.total_angle * math.pi / 180),
314+
]
315+
ret1 = self._circuit_comp._circuit_components.create_page_port(page_name, location, angle=angle)
316+
if offset != 0:
317+
self._circuit_comp._circuit_components.create_wire([self.location, location])
304318
for cmp in assignment:
305-
if cmp.location[0] > cmp._circuit_comp.location[0]:
306-
angle = 180
307-
else:
308-
angle = 0
319+
location = [
320+
cmp.location[0] - offset * math.cos(cmp.total_angle * math.pi / 180),
321+
cmp.location[1] - offset * math.sin(cmp.total_angle * math.pi / 180),
322+
]
323+
309324
ret2 = self._circuit_comp._circuit_components.create_page_port(
310-
page_name, location=cmp.location, angle=angle
325+
page_name, location=location, angle=cmp.total_angle
311326
)
327+
if offset != 0:
328+
self._circuit_comp._circuit_components.create_wire([cmp.location, location])
312329
if ret1 and ret2:
313330
return True, ret1, ret2
314331
else:

src/ansys/aedt/core/modeler/circuits/primitives_circuit.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -529,7 +529,7 @@ def create_model_from_touchstone(self, input_file, model_name=None, show_bitmap=
529529
bmp_file_name = Path(image_subcircuit_path).name
530530

531531
if not port_names:
532-
port_names = ["Port" + str(i + 1) for i in range(num_terminal)]
532+
port_names = [str(i + 1) for i in range(num_terminal)]
533533
arg = [
534534
"NAME:" + model_name,
535535
"Name:=",

tests/system/extensions/example_models/T45/circuit_config.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@
5757
"file_path": ""
5858
}
5959
},
60-
"refdes": {
60+
"instance": {
6161
"L1": {
6262
"component": "IND_",
6363
"properties": {

tests/system/general/test_21_Circuit.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -823,7 +823,7 @@ def test_44_auto_wire(self, aedtapp):
823823
l2 = aedtapp.modeler.schematic.create_inductor(value=1e-9, location=[1400, 4000], angle=0)
824824
aedtapp.modeler.schematic.create_resistor(value=50, location=[3100, 3200])
825825

826-
assert p1.pins[0].connect_to_component(r1.pins[1], use_wire=True)
826+
assert p1.pins[0].connect_to_component(r1.pins[1], use_wire=True, offset=0.0512)
827827
assert l1.pins[0].connect_to_component(l2.pins[0], use_wire=True)
828828
assert l3.pins[0].connect_to_component(l2.pins[1], use_wire=True, clearance_units=2)
829829
assert l4.pins[1].connect_to_component(l3.pins[0], use_wire=True, clearance_units=2)

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