Skip to content

Commit a7e383b

Browse files
litghostlitghost
authored
Merge pull request chipsalliance#3 from litghost/dos2unix_fix
Convert to unix line endings.
2 parents 6a9e3cb + d89cf3e commit a7e383b

File tree

2 files changed

+293
-293
lines changed

2 files changed

+293
-293
lines changed

‎interchange/LogicalNetlist.capnp

Lines changed: 140 additions & 140 deletions
Original file line numberDiff line numberDiff line change
@@ -1,140 +1,140 @@
1-
# Copyright 2020-2021 Xilinx, Inc. and Google, Inc.
2-
#
3-
# Licensed under the Apache License, Version 2.0 (the "License");
4-
# you may not use this file except in compliance with the License.
5-
# You may obtain a copy of the License at
6-
#
7-
# http://www.apache.org/licenses/LICENSE-2.0
8-
#
9-
# Unless required by applicable law or agreed to in writing, software
10-
# distributed under the License is distributed on an "AS IS" BASIS,
11-
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12-
# See the License for the specific language governing permissions and
13-
# limitations under the License.
14-
15-
@0xcb2ccd67aa912967;
16-
using Java = import "/capnp/java.capnp";
17-
using Ref = import "References.capnp";
18-
$Java.package("com.xilinx.rapidwright.interchange");
19-
$Java.outerClassname("LogicalNetlist");
20-
21-
struct HashSet {
22-
type @0 : Ref.ImplementationType = enumerator;
23-
hide @1 : Bool = true;
24-
}
25-
annotation hashSet(*) :HashSet;
26-
27-
struct StringRef {
28-
type @0 :Ref.ReferenceType = rootValue;
29-
field @1 :Text = "strList";
30-
}
31-
annotation stringRef(*) :StringRef;
32-
using StringIdx = UInt32;
33-
34-
struct PortRef {
35-
type @0 :Ref.ReferenceType = parent;
36-
field @1 :Text = "portList";
37-
depth @2 :Int32 = 1;
38-
}
39-
annotation portRef(*) :PortRef;
40-
using PortIdx = UInt32;
41-
42-
struct CellRef {
43-
type @0 :Ref.ReferenceType = parent;
44-
field @1 :Text = "cellDecls";
45-
depth @2 :Int32 = 1;
46-
}
47-
annotation cellRef(*) :CellRef;
48-
using CellIdx = UInt32;
49-
50-
struct InstRef {
51-
type @0 :Ref.ReferenceType = parent;
52-
field @1 :Text = "instList";
53-
depth @2 :Int32 = 1;
54-
}
55-
annotation instRef(*) :InstRef;
56-
using InstIdx = UInt32;
57-
58-
struct Netlist {
59-
60-
name @0 : Text;
61-
propMap @1 : PropertyMap;
62-
strList @2 : List(Text) $hashSet();
63-
portList @3 : List(Port);
64-
cellDecls @4 : List(CellDeclaration);
65-
topInst @5 : CellInstance;
66-
instList @6 : List(CellInstance);
67-
cellList @7 : List(Cell);
68-
69-
struct CellDeclaration {
70-
name @0 : StringIdx $stringRef();
71-
propMap @1 : PropertyMap;
72-
view @2 : StringIdx $stringRef();
73-
lib @3 : StringIdx $stringRef();
74-
ports @4 : List(PortIdx) $portRef();
75-
}
76-
77-
struct CellInstance {
78-
name @0 : StringIdx $stringRef();
79-
propMap @1 : PropertyMap;
80-
view @2 : StringIdx $stringRef();
81-
cell @3 : CellIdx $cellRef();
82-
}
83-
84-
struct Cell {
85-
index @0 : CellIdx $cellRef();
86-
insts @1 : List(InstIdx) $instRef();
87-
nets @2 : List(Net);
88-
}
89-
90-
struct Net {
91-
name @0 : StringIdx $stringRef();
92-
propMap @1 : PropertyMap;
93-
portInsts @2 : List(PortInstance);
94-
}
95-
96-
struct Port {
97-
name @0 : StringIdx $stringRef();
98-
dir @1 : Direction;
99-
propMap @2 : PropertyMap;
100-
union {
101-
bit @3 : Void;
102-
bus @4 : Bus;
103-
}
104-
}
105-
106-
enum Direction {
107-
input @0;
108-
output @1;
109-
inout @2;
110-
}
111-
112-
struct Bus {
113-
busStart @0 : UInt32;
114-
busEnd @1 : UInt32;
115-
}
116-
117-
struct PortInstance {
118-
port @0 : PortIdx $portRef(depth = 3);
119-
busIdx : union {
120-
singleBit @1 : Void; # Single bit
121-
idx @2 : UInt32; # Index within bussed port
122-
}
123-
union {
124-
extPort @3 : Void;
125-
inst @4 : InstIdx $instRef(depth = 3);
126-
}
127-
}
128-
129-
struct PropertyMap {
130-
entries @0 : List(Entry);
131-
struct Entry {
132-
key @0 : StringIdx $stringRef();
133-
union {
134-
textValue @1 : StringIdx $stringRef();
135-
intValue @2 : Int32;
136-
boolValue @3 : Bool;
137-
}
138-
}
139-
}
140-
}
1+
# Copyright 2020-2021 Xilinx, Inc. and Google, Inc.
2+
#
3+
# Licensed under the Apache License, Version 2.0 (the "License");
4+
# you may not use this file except in compliance with the License.
5+
# You may obtain a copy of the License at
6+
#
7+
# http://www.apache.org/licenses/LICENSE-2.0
8+
#
9+
# Unless required by applicable law or agreed to in writing, software
10+
# distributed under the License is distributed on an "AS IS" BASIS,
11+
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12+
# See the License for the specific language governing permissions and
13+
# limitations under the License.
14+
15+
@0xcb2ccd67aa912967;
16+
using Java = import "/capnp/java.capnp";
17+
using Ref = import "References.capnp";
18+
$Java.package("com.xilinx.rapidwright.interchange");
19+
$Java.outerClassname("LogicalNetlist");
20+
21+
struct HashSet {
22+
type @0 : Ref.ImplementationType = enumerator;
23+
hide @1 : Bool = true;
24+
}
25+
annotation hashSet(*) :HashSet;
26+
27+
struct StringRef {
28+
type @0 :Ref.ReferenceType = rootValue;
29+
field @1 :Text = "strList";
30+
}
31+
annotation stringRef(*) :StringRef;
32+
using StringIdx = UInt32;
33+
34+
struct PortRef {
35+
type @0 :Ref.ReferenceType = parent;
36+
field @1 :Text = "portList";
37+
depth @2 :Int32 = 1;
38+
}
39+
annotation portRef(*) :PortRef;
40+
using PortIdx = UInt32;
41+
42+
struct CellRef {
43+
type @0 :Ref.ReferenceType = parent;
44+
field @1 :Text = "cellDecls";
45+
depth @2 :Int32 = 1;
46+
}
47+
annotation cellRef(*) :CellRef;
48+
using CellIdx = UInt32;
49+
50+
struct InstRef {
51+
type @0 :Ref.ReferenceType = parent;
52+
field @1 :Text = "instList";
53+
depth @2 :Int32 = 1;
54+
}
55+
annotation instRef(*) :InstRef;
56+
using InstIdx = UInt32;
57+
58+
struct Netlist {
59+
60+
name @0 : Text;
61+
propMap @1 : PropertyMap;
62+
strList @2 : List(Text) $hashSet();
63+
portList @3 : List(Port);
64+
cellDecls @4 : List(CellDeclaration);
65+
topInst @5 : CellInstance;
66+
instList @6 : List(CellInstance);
67+
cellList @7 : List(Cell);
68+
69+
struct CellDeclaration {
70+
name @0 : StringIdx $stringRef();
71+
propMap @1 : PropertyMap;
72+
view @2 : StringIdx $stringRef();
73+
lib @3 : StringIdx $stringRef();
74+
ports @4 : List(PortIdx) $portRef();
75+
}
76+
77+
struct CellInstance {
78+
name @0 : StringIdx $stringRef();
79+
propMap @1 : PropertyMap;
80+
view @2 : StringIdx $stringRef();
81+
cell @3 : CellIdx $cellRef();
82+
}
83+
84+
struct Cell {
85+
index @0 : CellIdx $cellRef();
86+
insts @1 : List(InstIdx) $instRef();
87+
nets @2 : List(Net);
88+
}
89+
90+
struct Net {
91+
name @0 : StringIdx $stringRef();
92+
propMap @1 : PropertyMap;
93+
portInsts @2 : List(PortInstance);
94+
}
95+
96+
struct Port {
97+
name @0 : StringIdx $stringRef();
98+
dir @1 : Direction;
99+
propMap @2 : PropertyMap;
100+
union {
101+
bit @3 : Void;
102+
bus @4 : Bus;
103+
}
104+
}
105+
106+
enum Direction {
107+
input @0;
108+
output @1;
109+
inout @2;
110+
}
111+
112+
struct Bus {
113+
busStart @0 : UInt32;
114+
busEnd @1 : UInt32;
115+
}
116+
117+
struct PortInstance {
118+
port @0 : PortIdx $portRef(depth = 3);
119+
busIdx : union {
120+
singleBit @1 : Void; # Single bit
121+
idx @2 : UInt32; # Index within bussed port
122+
}
123+
union {
124+
extPort @3 : Void;
125+
inst @4 : InstIdx $instRef(depth = 3);
126+
}
127+
}
128+
129+
struct PropertyMap {
130+
entries @0 : List(Entry);
131+
struct Entry {
132+
key @0 : StringIdx $stringRef();
133+
union {
134+
textValue @1 : StringIdx $stringRef();
135+
intValue @2 : Int32;
136+
boolValue @3 : Bool;
137+
}
138+
}
139+
}
140+
}

0 commit comments

Comments
 (0)