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SPI: Implemented MISO, MOSI, SCK and SS pins handling using avr_bitbang functions.
1 parent 5669a06 commit dfc7fbe

20 files changed

+427
-38
lines changed

simavr/cores/sim_mega128.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -391,7 +391,7 @@ const struct mcu_t {
391391
.vector = TIMER3_CAPT_vect,
392392
},
393393
},
394-
AVR_SPI_DECLARE(0, 0),
394+
AVR_SPI_DECLARE(0, 0, 'B', 1, 3, 2, 0),
395395
.twi = {
396396

397397
.r_twcr = TWCR,

simavr/cores/sim_mega1280.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -616,7 +616,7 @@ const struct mcu_t {
616616
},
617617

618618
},
619-
AVR_SPI_DECLARE(PRR0, PRSPI),
619+
AVR_SPI_DECLARE(PRR0, PRSPI, 'B', 1, 3, 2, 0),
620620
.twi = {
621621

622622
.r_twcr = TWCR,

simavr/cores/sim_mega1281.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -431,7 +431,7 @@ const struct mcu_t {
431431
.vector = TIMER3_CAPT_vect,
432432
},
433433
},
434-
AVR_SPI_DECLARE(PRR0, PRSPI),
434+
AVR_SPI_DECLARE(PRR0, PRSPI, 'B', 1, 3, 2, 0),
435435
.twi = {
436436

437437
.r_twcr = TWCR,

simavr/cores/sim_mega128rfr2.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -469,7 +469,7 @@ const struct mcu_t {
469469
.vector = TIMER3_CAPT_vect,
470470
},
471471
},
472-
AVR_SPI_DECLARE(PRR0, PRSPI),
472+
AVR_SPI_DECLARE(PRR0, PRSPI, 'B', 1, 3, 2, 0),
473473
.twi = {
474474

475475
.r_twcr = TWCR,

simavr/cores/sim_mega169.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -319,7 +319,7 @@ const struct mcu_t {
319319
},
320320
},
321321
},
322-
AVR_SPI_DECLARE(PRR, PRSPI),
322+
AVR_SPI_DECLARE(PRR, PRSPI, 'B', 1, 3, 2, 0),
323323
};
324324

325325
static avr_t * make()

simavr/cores/sim_mega2560.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -618,7 +618,7 @@ const struct mcu_t {
618618
},
619619

620620
},
621-
AVR_SPI_DECLARE(PRR0, PRSPI),
621+
AVR_SPI_DECLARE(PRR0, PRSPI, 'B', 1, 3, 2, 0),
622622
.twi = {
623623

624624
.r_twcr = TWCR,

simavr/cores/sim_megax.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -301,7 +301,7 @@ const struct mcu_t SIM_CORENAME = {
301301
},
302302
},
303303
},
304-
AVR_SPI_DECLARE(0, 0),
304+
AVR_SPI_DECLARE(0, 0, 'B', 7, 6, 5, 4),
305305
.twi = {
306306

307307
.r_twcr = TWCR,

simavr/cores/sim_megax4.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -432,9 +432,9 @@ const struct mcu_t SIM_CORENAME = {
432432
},
433433
#endif
434434
#ifdef MSTR0 /* xx4a and xx4pa series */
435-
AVR_SPIX_DECLARE(0, PRR0, PRSPI),
435+
AVR_SPIX_DECLARE(0, PRR0, PRSPI, 'B', 7, 6, 5, 4),
436436
#else
437-
AVR_SPI_DECLARE(PRR0, PRSPI),
437+
AVR_SPI_DECLARE(PRR0, PRSPI, 'B', 7, 6, 5, 4),
438438
#endif
439439
.twi = {
440440
.disabled = AVR_IO_REGBIT(PRR0,PRTWI),

simavr/cores/sim_megax8.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -345,7 +345,7 @@ const struct mcu_t SIM_CORENAME = {
345345
}
346346
}
347347
},
348-
AVR_SPI_DECLARE(PRR, PRSPI),
348+
AVR_SPI_DECLARE(PRR, PRSPI, 'B', 5, 4, 3, 2),
349349
.twi = {
350350
.disabled = AVR_IO_REGBIT(PRR,PRTWI),
351351

simavr/cores/sim_megaxm1.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -311,7 +311,7 @@ const struct mcu_t SIM_CORENAME = {
311311
},
312312
},
313313
},
314-
AVR_SPI_DECLARE(PRR, PRSPI),
314+
AVR_SPI_DECLARE(PRR, PRSPI, 'C', 7, 0, 1, 1),
315315
};
316316
#endif /* SIM_CORENAME */
317317

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