Merge branch 'develop'

Author: caleb531

cachesimulator/simulator.py

@@ -11,6 +11,8 @@
 REF_COL_NAMES = ('WordAddr', 'BinAddr', 'Tag', 'Index', 'Offset', 'Hit/Miss')
 # The minimum number of bits required per group in a prettified binary string
 MIN_BITS_PER_GROUP = 3
+# The default column width of the displayed results table
+DEFAULT_TABLE_WIDTH = 80
 
 
 # Retrieves the binary address of a certain length for a base-10 word address
@@ -305,7 +307,8 @@ def run_simulation(num_blocks_per_set, num_words_per_block, cache_size,
 
     # The character-width of all displayed tables
     # Attempt to fit table to terminal width, otherwise use default of 80
-    table_width = shutil.get_terminal_size((80, 20)).columns
+    table_width = max((shutil.get_terminal_size(
+        (DEFAULT_TABLE_WIDTH, 20)).columns, DEFAULT_TABLE_WIDTH))
 
     print()
     display_addr_refs(refs, ref_statuses, table_width)

setup.py

@@ -16,7 +16,7 @@ def get_long_description():
 
 setup(
     name='cache-simulator',
-    version='1.0.1r1',
+    version='1.0.2',
     description='A processor cache simulator for the MIPS ISA',
     long_description=get_long_description(),
     url='https://github.com/caleb531/cache-simulator',