Merge pull request #114 from antmicro/acom/run-cron-ci

Run cron CI

Author: acomodi

.github/workflows/ci.yml

@@ -8,7 +8,11 @@
 
 name: FPGA interchange CI tests
 
-on: [push, pull_request]
+on:
+  push:
+  pull_request:
+  schedule:
+    - cron: '0 0 * * *'
 
 jobs:
   Check-Repository:

.github/workflows/update_conda_lock.yml

@@ -0,0 +1,54 @@
+# Copyright (C) 2022 F4PGA Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:ISC
+
+name: update_conda_lock
+
+on:
+  push:
+  pull_request:
+  schedule:
+    - cron: '0 3 * * *'
+  workflow_dispatch:
+
+jobs:
+  update-locks:
+    runs-on: ubuntu-18.04
+    strategy:
+      fail-fast: false
+    steps:
+    - name: Checkout Repository
+      uses: actions/checkout@v3
+      with:
+        fetch-depth: 0
+        submodules:  'recursive'
+        ssh-key: ${{ secrets.SSH_DEPLOY_KEY }}
+
+    - name: Update Conda Lock
+      uses: SymbiFlow/actions/update_conda_lock@c6142a4ec7859653352757eb8f7c4630f63f96e3
+      with:
+        conda_lock_file:  'conda_lock.yml'
+        environment_file: 'environment.yml'
+
+    - name: Check diff
+      id: check-diff
+      run: |
+        if [[ $(git status --porcelain --ignore-submodules)  ]]; then echo "::set-output name=changes::true"; else echo "::set-output name=changes::false"; fi
+
+    - name: Issue Pull Request
+      if: ${{ github.ref == 'refs/heads/main' && steps.check-diff.outputs.changes == 'true' }}
+      uses: peter-evans/create-pull-request@v4
+      with:
+        token: ${{ secrets.GITHUB_TOKEN }}
+        author: GitHub <[email protected]>
+        commit-message: "[BOT] Conda Lock Update"
+        title: "[BOT] Conda Lock Update"
+        body: Pull Request created by the conda lock update workflow.
+        branch: bot-conda-lock-update
+        labels: bot-conda-lock-update,merge-if-green
+        delete-branch: true
+        signoff: true

Makefile

@@ -8,7 +8,7 @@
 
 TOP_DIR := $(realpath $(dir $(lastword $(MAKEFILE_LIST))))
 REQUIREMENTS_FILE := requirements.txt
-ENVIRONMENT_FILE := environment.yml
+ENVIRONMENT_FILE := conda_lock.yml
 
 # Paths
 RAPIDWRIGHT_PATH ?= $(TOP_DIR)/third_party/RapidWright

README.md

@@ -13,7 +13,7 @@ make env
 Enter the environment by running:
 
 ```
-make enter
+source env/conda/bin/activate fpga-interchange
 ```
 
 To update the RapidWright data run:

conda_lock.yml

@@ -0,0 +1,27 @@
+# Copyright (C) 2022 F4PGA Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:ISC
+
+name: fpga-interchange
+channels:
+    - defaults
+    - litex-hub
+dependencies:
+    - litex-hub::capnproto-java=0.1.5_0012_g44a8c1e=20201104_165332
+    - litex-hub::gcc-riscv64-elf-newlib=9.2.0=20201119_154229
+    - litex-hub::iverilog=0_8_5850_g540555fc=20210730_085634
+    - litex-hub::nextpnr-fpga_interchange
+    - litex-hub::prjoxide=v0.0_398_g711770c=20210730_085634
+    - litex-hub::prjxray-db
+    - litex-hub::prjxray-tools
+    - litex-hub::vtr-optimized
+    - litex-hub::yosys
+    - swig
+    - packaging=21.3
+    - pip=21.1.3
+    - pip:
+        - -r requirements.txt

environment.yml

@@ -14,13 +14,14 @@ dependencies:
     - litex-hub::capnproto-java=0.1.5_0012_g44a8c1e=20201104_165332
     - litex-hub::gcc-riscv64-elf-newlib=9.2.0=20201119_154229
     - litex-hub::iverilog=0_8_5850_g540555fc=20210730_085634
-    - litex-hub::nextpnr-fpga_interchange=0.2_33_g81e97086=20220302_164843_py37
+    - litex-hub::nextpnr-fpga_interchange
     - litex-hub::prjoxide=v0.0_398_g711770c=20210730_085634
-    - litex-hub::prjxray-db=0.0_257_g0a0adde=20220202_022309
-    - litex-hub::prjxray-tools=0.1_2942_g5349556b=20220202_022309
-    - litex-hub::vtr-optimized=8.0.0_5170_g81b5aa2a8=20220202_022309
-    - litex-hub::yosys=0.13_39_g958c3a46a=20220202_022309_py37
+    - litex-hub::prjxray-db
+    - litex-hub::prjxray-tools
+    - litex-hub::vtr-optimized
+    - litex-hub::yosys
     - swig
-    - pip
+    - packaging=21.3
+    - pip=21.1.3
     - pip:
         - -r requirements.txt

requirements.txt

@@ -1,11 +1,12 @@
-psutil
-ninja
-git+https://github.com/litghost/rapidyaml.git@fixup_python_packaging#egg=rapidyaml
 fasm
-git+https://github.com/SymbiFlow/prjxray.git
-git+https://github.com/SymbiFlow/symbiflow-xc-fasm.git
-git+https://github.com/capnproto/pycapnp.git
-git+https://github.com/SymbiFlow/symbiflow-xc-fasm2bels.git
+ninja
+psutil
+pycapnp==v1.1.0
+rapidyaml==0.2.2
+
+git+https://github.com/f4pga/prjxray.git
+git+https://github.com/chipsalliance/f4pga-xc-fasm.git
+git+https://github.com/SymbiFlow/f4pga-xc-fasm2bels.git
 -e third_party/python-fpga-interchange
 
 # Litex