Add LUT output pins to chipdb.

Signed-off-by: Keith Rothman <[email protected]>

Author: litghost

fpga_interchange/chip_info.py

@@ -251,6 +251,7 @@ def __init__(self):
         self.pins = []
         self.low_bit = 0
         self.high_bit = 0
+        self.out_pin = ''
 
     def field_label(self, label_prefix, field):
         prefix = '{}.{}.{}'.format(label_prefix, self.name, field)
@@ -267,6 +268,7 @@ def append_bba(self, bba, label_prefix):
         bba.u32(len(self.pins))
         bba.u32(self.low_bit)
         bba.u32(self.high_bit)
+        bba.str_id(self.out_pin)
 
 
 class LutElement():
@@ -721,7 +723,7 @@ def __init__(self):
         self.generator = ''
 
         # Note: Increment by 1 this whenever schema changes.
-        self.version = 5
+        self.version = 6
         self.width = 0
         self.height = 0
 

fpga_interchange/populate_chip_info.py

@@ -172,6 +172,8 @@ def emit(self, lut_elements):
                 for pin in bel.inputPins:
                     lut_bel.pins.append(pin)
 
+                lut_bel.out_pin = bel.outputPin
+
                 lut_bel.low_bit = bel.lowBit
                 lut_bel.high_bit = bel.highBit
 
@@ -297,7 +299,8 @@ def __init__(self, device, tile_type_index, tile_type, cell_bel_mapper,
                             if port.type == PortType.PORT_OUT:
                                 # Only record wires driven by BEL pin outputs.
                                 # BEL pin inputs do not consume the wire.
-                                pseudo_cell_wires.add(port.wire)
+                                if port.wire != -1:
+                                    pseudo_cell_wires.add(port.wire)
 
             # Make sure every BEL pin from the database matches at least 1
             # instance (possibly more!).