Xilinx Floating: Indent primitives differently

This makes the next commit easier to analyse in diff viewers.

Author: DigitalBrains1

clash-cores/src/Clash/Cores/Xilinx/Floating/Annotations.hs

@@ -37,61 +37,62 @@ vhdlBinaryPrim
   -> Name
   -> String
   -> Primitive
-vhdlBinaryPrim primName tclTFName funcName = InlineYamlPrimitive [VHDL] [__i|
-  BlackBox:
-    name: #{primName}
-    type: |-
-      #{primName}
-        :: ( KnownDomain dom           --     ARG[0]
-           , KnownNat d                --     ARG[1]
-           , HasCallStack              --     ARG[2]
-           )
-        => Config                      --     ARG[3]
-        -> Clock dom                   --     ARG[4]
-        -> Enable dom                  --     ARG[5]
-        -> DSignal dom n Float         -- x , ARG[6]
-        -> DSignal dom n Float         -- y , ARG[7]
-        -> DSignal dom (n + d) Float
-    kind: Declaration
-    template: |-
-      -- #{funcName} begin
-      ~DEVNULL[~LIT[3]]~GENSYM[#{funcName}][0] : block
-        COMPONENT ~INCLUDENAME[0]
-          PORT (
-            aclk : IN STD_LOGIC;
-      ~IF~ISACTIVEENABLE[5]~THEN      aclken : IN STD_LOGIC;
-      ~ELSE~FI      s_axis_a_tvalid : IN STD_LOGIC;
-            s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-            s_axis_b_tvalid : IN STD_LOGIC;
-            s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-            m_axis_result_tvalid : OUT STD_LOGIC;
-            m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
-          );
-        END COMPONENT;
-      ~IF~ISACTIVEENABLE[5]~THEN  signal ~GENSYM[clken_std][2]: std_logic;
-      begin
-        ~SYM[2] <= '1' when (~ARG[5]) else '0';
-      ~ELSEbegin
-      ~FI  ~GENSYM[#{funcName}][1] : ~INCLUDENAME[0]
-          PORT MAP (
-            aclk => ~ARG[4],
-      ~IF~ISACTIVEENABLE[5]~THEN      aclken => ~SYM[2],
-      ~ELSE~FI      s_axis_a_tvalid => '1',
-            s_axis_a_tdata => ~ARG[6],
-            s_axis_b_tvalid => '1',
-            s_axis_b_tdata => ~ARG[7],
-            m_axis_result_tvalid => open,
-            m_axis_result_tdata => ~RESULT
-          );
+vhdlBinaryPrim primName tclTFName funcName =
+  InlineYamlPrimitive [VHDL] [__i|
+    BlackBox:
+      name: #{primName}
+      type: |-
+        #{primName}
+          :: ( KnownDomain dom           --     ARG[0]
+             , KnownNat d                --     ARG[1]
+             , HasCallStack              --     ARG[2]
+             )
+          => Config                      --     ARG[3]
+          -> Clock dom                   --     ARG[4]
+          -> Enable dom                  --     ARG[5]
+          -> DSignal dom n Float         -- x , ARG[6]
+          -> DSignal dom n Float         -- y , ARG[7]
+          -> DSignal dom (n + d) Float
+      kind: Declaration
+      template: |-
+        -- #{funcName} begin
+        ~DEVNULL[~LIT[3]]~GENSYM[#{funcName}][0] : block
+          COMPONENT ~INCLUDENAME[0]
+            PORT (
+              aclk : IN STD_LOGIC;
+        ~IF~ISACTIVEENABLE[5]~THEN      aclken : IN STD_LOGIC;
+        ~ELSE~FI      s_axis_a_tvalid : IN STD_LOGIC;
+              s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+              s_axis_b_tvalid : IN STD_LOGIC;
+              s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+              m_axis_result_tvalid : OUT STD_LOGIC;
+              m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+            );
+          END COMPONENT;
+        ~IF~ISACTIVEENABLE[5]~THEN  signal ~GENSYM[clken_std][2]: std_logic;
+        begin
+          ~SYM[2] <= '1' when (~ARG[5]) else '0';
+        ~ELSEbegin
+        ~FI  ~GENSYM[#{funcName}][1] : ~INCLUDENAME[0]
+            PORT MAP (
+              aclk => ~ARG[4],
+        ~IF~ISACTIVEENABLE[5]~THEN      aclken => ~SYM[2],
+        ~ELSE~FI      s_axis_a_tvalid => '1',
+              s_axis_a_tdata => ~ARG[6],
+              s_axis_b_tvalid => '1',
+              s_axis_b_tdata => ~ARG[7],
+              m_axis_result_tvalid => open,
+              m_axis_result_tdata => ~RESULT
+            );
 
-      end block;
-      -- #{funcName} end
-    includes:
-      - extension: clash.tcl
-        name: floating_point
-        format: Haskell
-        templateFunction: #{tclTFName}
-  |]
+        end block;
+        -- #{funcName} end
+      includes:
+        - extension: clash.tcl
+          name: floating_point
+          format: Haskell
+          templateFunction: #{tclTFName}
+    |]
 
 -- | The InlinePrimitive annotation for a binary function in Verilog.
 
@@ -362,50 +363,51 @@ vhdlComparePrim
   -> Name
   -> String
   -> Primitive
-vhdlComparePrim primName tclTFName funcName = InlineYamlPrimitive [VHDL] [__i|
-  BlackBox:
-    name: #{primName}
-    kind: Declaration
-    template: |-
-      -- #{funcName} begin
-      ~GENSYM[#{funcName}][#{blockSym}] : block
-        COMPONENT ~INCLUDENAME[0]
-          PORT (
-            aclk : IN STD_LOGIC;
-      ~IF~ISACTIVEENABLE[#{enable}]~THEN      aclken : IN STD_LOGIC;
-      ~ELSE~FI      s_axis_a_tvalid : IN STD_LOGIC;
-            s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-            s_axis_b_tvalid : IN STD_LOGIC;
-            s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-            m_axis_result_tvalid : OUT STD_LOGIC;
-            m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-          );
-        END COMPONENT;
-      ~IF~ISACTIVEENABLE[#{enable}]~THEN  signal ~GENSYM[clken_std][#{clkEnStdSym}]: std_logic;~ELSE~FI
-        signal ~GENSYM[ip_result][#{ipResultSym}] : std_logic_vector(7 downto 0);
-      begin
-        ~IF~ISACTIVEENABLE[#{enable}]~THEN~SYM[#{clkEnStdSym}] <= '1' when (~ARG[#{enable}]) else '0';~ELSE~FI
-        ~RESULT <= ~SYM[#{ipResultSym}](3 downto 0);
-        ~GENSYM[#{funcName}][#{compSym}] : ~INCLUDENAME[0]
-          PORT MAP (
-            aclk => ~ARG[#{clock}],
-      ~IF~ISACTIVEENABLE[#{enable}]~THEN      aclken => ~SYM[#{clkEnStdSym}],
-      ~ELSE~FI      s_axis_a_tvalid => '1',
-            s_axis_a_tdata => ~ARG[#{x}],
-            s_axis_b_tvalid => '1',
-            s_axis_b_tdata => ~ARG[#{y}],
-            m_axis_result_tvalid => open,
-            m_axis_result_tdata => ~SYM[#{ipResultSym}]
-          );
+vhdlComparePrim primName tclTFName funcName =
+  InlineYamlPrimitive [VHDL] [__i|
+    BlackBox:
+      name: #{primName}
+      kind: Declaration
+      template: |-
+        -- #{funcName} begin
+        ~GENSYM[#{funcName}][#{blockSym}] : block
+          COMPONENT ~INCLUDENAME[0]
+            PORT (
+              aclk : IN STD_LOGIC;
+        ~IF~ISACTIVEENABLE[#{enable}]~THEN      aclken : IN STD_LOGIC;
+        ~ELSE~FI      s_axis_a_tvalid : IN STD_LOGIC;
+              s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+              s_axis_b_tvalid : IN STD_LOGIC;
+              s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+              m_axis_result_tvalid : OUT STD_LOGIC;
+              m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+            );
+          END COMPONENT;
+        ~IF~ISACTIVEENABLE[#{enable}]~THEN  signal ~GENSYM[clken_std][#{clkEnStdSym}]: std_logic;~ELSE~FI
+          signal ~GENSYM[ip_result][#{ipResultSym}] : std_logic_vector(7 downto 0);
+        begin
+          ~IF~ISACTIVEENABLE[#{enable}]~THEN~SYM[#{clkEnStdSym}] <= '1' when (~ARG[#{enable}]) else '0';~ELSE~FI
+          ~RESULT <= ~SYM[#{ipResultSym}](3 downto 0);
+          ~GENSYM[#{funcName}][#{compSym}] : ~INCLUDENAME[0]
+            PORT MAP (
+              aclk => ~ARG[#{clock}],
+        ~IF~ISACTIVEENABLE[#{enable}]~THEN      aclken => ~SYM[#{clkEnStdSym}],
+        ~ELSE~FI      s_axis_a_tvalid => '1',
+              s_axis_a_tdata => ~ARG[#{x}],
+              s_axis_b_tvalid => '1',
+              s_axis_b_tdata => ~ARG[#{y}],
+              m_axis_result_tvalid => open,
+              m_axis_result_tdata => ~SYM[#{ipResultSym}]
+            );
 
-      end block;
-      -- #{funcName} end
-    includes:
-      - extension: clash.tcl
-        name: floating_point
-        format: Haskell
-        templateFunction: #{tclTFName}
-  |]
+        end block;
+        -- #{funcName} end
+      includes:
+        - extension: clash.tcl
+          name: floating_point
+          format: Haskell
+          templateFunction: #{tclTFName}
+    |]
  where
   clock, enable, x, y :: Int
   (  _knownDomain :: Int
@@ -433,27 +435,27 @@ veriComparePrim
   -> Primitive
 veriComparePrim primName tclTFName funcName =
   InlineYamlPrimitive [Verilog, SystemVerilog] [__i|
-  BlackBox:
-    name: #{primName}
-    kind: Declaration
-    template: |-
-      // #{funcName} begin
-      ~INCLUDENAME[0] ~GENSYM[#{funcName}][#{compSym}] (
-        .aclk(~ARG[#{clock}]),
-      ~IF~ISACTIVEENABLE[#{enable}]~THEN  .aclken(~ARG[#{enable}]),
-      ~ELSE~FI  .s_axis_a_tvalid(1'b1),
-        .s_axis_a_tdata(~ARG[#{x}]),
-        .s_axis_b_tvalid(1'b1),
-        .s_axis_b_tdata(~ARG[#{y}]),
-        .m_axis_result_tvalid(),
-        .m_axis_result_tdata(~RESULT)
-      );
-      // #{funcName} end
-    includes:
-      - extension: clash.tcl
-        name: floating_point
-        format: Haskell
-        templateFunction: #{tclTFName}
+    BlackBox:
+      name: #{primName}
+      kind: Declaration
+      template: |-
+        // #{funcName} begin
+        ~INCLUDENAME[0] ~GENSYM[#{funcName}][#{compSym}] (
+          .aclk(~ARG[#{clock}]),
+        ~IF~ISACTIVEENABLE[#{enable}]~THEN  .aclken(~ARG[#{enable}]),
+        ~ELSE~FI  .s_axis_a_tvalid(1'b1),
+          .s_axis_a_tdata(~ARG[#{x}]),
+          .s_axis_b_tvalid(1'b1),
+          .s_axis_b_tdata(~ARG[#{y}]),
+          .m_axis_result_tvalid(),
+          .m_axis_result_tdata(~RESULT)
+        );
+        // #{funcName} end
+      includes:
+        - extension: clash.tcl
+          name: floating_point
+          format: Haskell
+          templateFunction: #{tclTFName}
     |]
  where
   clock, enable, x, y :: Int