KNOWNBUG test for SVA 'and' of two properties

Author: kroening

regression/verilog/SVA/property_and1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+property_and1.sv
+--bdd
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This is rejected with a typechecking error.

regression/verilog/SVA/property_and1.sv

@@ -0,0 +1,9 @@
+module main;
+
+  property P1;
+    1
+  endproperty
+
+  assert property (P1 and P1);
+
+endmodule