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Buechi: identify special cases where reachability is sufficient
This adds treatment for the special case where all nonaccepting states of the Buechi automaton have an unconditional self-loop. In this case, when these nonaccepting states is reached, the trace cannot be extended to an accepting trace, and will hence be rejected. Hence, in this case, the Buechi acceptance condition is unnecessary, and a simple reachability property is sufficient.
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6 files changed

+21
-12
lines changed

6 files changed

+21
-12
lines changed

regression/ebmc-spot/sva-buechi/sequence5.desc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
CORE
22
../../verilog/SVA/sequence5.sv
33
--buechi
4-
^\[main\.p0\] 1: PROVED up to bound \d+$
4+
^\[main\.p0\] 1: PROVED \(1-induction\)$
55
^\[main\.p1\] 0: REFUTED$
66
^\[main\.p2\] 1'bx: REFUTED$
77
^\[main\.p3\] 1'bz: REFUTED$

regression/ebmc-spot/sva-buechi/sva_and1.desc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
CORE
22
../../verilog/SVA/sva_and1.sv
33
--buechi
4-
^\[main\.p0\] always \(1 and 1\): PROVED up to bound \d+$
4+
^\[main\.p0\] always \(1 and 1\): PROVED \(1-induction\)$
55
^\[main\.p1\] always \(1 and 0\): REFUTED$
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^\[main\.p2\] always \(1 and 32'b0000000000000000000000000000000x\): REFUTED$
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^EXIT=10$

regression/ebmc-spot/sva-buechi/sva_iff1.desc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
CORE
22
../../verilog/SVA/sva_iff1.sv
33
--buechi
4-
^\[main\.p0\] always \(1 iff 1\): PROVED up to bound \d+$
4+
^\[main\.p0\] always \(1 iff 1\): PROVED \(1-induction\)$
55
^\[main\.p1\] always \(1 iff 0\): REFUTED$
66
^\[main\.p2\] always \(1 iff 32'b0000000000000000000000000000000x\): REFUTED$
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^EXIT=10$

regression/ebmc-spot/sva-buechi/sva_implies1.desc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
CORE
22
../../verilog/SVA/sva_implies1.sv
33
--buechi
4-
^\[main\.p0\] always \(1 implies 1\): PROVED up to bound \d+$
4+
^\[main\.p0\] always \(1 implies 1\): PROVED \(1-induction\)$
55
^\[main\.p1\] always \(1 implies 0\): REFUTED$
66
^\[main\.p2\] always \(1 implies 32'b0000000000000000000000000000000x\): REFUTED$
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^EXIT=10$

regression/ebmc-spot/sva-buechi/sva_not1.desc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
CORE
22
../../verilog/SVA/sva_not1.sv
33
--buechi
4-
^\[main\.p0] always not 0: PROVED up to bound \d+$
4+
^\[main\.p0] always not 0: PROVED \(1-induction\)$
55
^\[main\.p1] always not 1: REFUTED$
66
^EXIT=10$
77
^SIGNAL=0$

src/ebmc/instrument_buechi.cpp

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -64,15 +64,24 @@ void instrument_buechi(
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transition_system.trans_expr.trans() =
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and_exprt{transition_system.trans_expr.trans(), buechi.trans};
6666

67-
// Replace the normalized property expression.
68-
// Note that we have negated the property,
69-
// so this is the negation of the Buechi acceptance condition.
70-
property.normalized_expr =
71-
F_exprt{G_exprt{not_exprt{buechi.liveness_signal}}};
67+
// Replace the normalized property expression
68+
// by the Buechi acceptance condition.
69+
exprt::operandst property_conjuncts;
70+
71+
if(!buechi.liveness_signal.is_false())
72+
{
73+
// Note that we have negated the property,
74+
// so this is the negation of the Buechi acceptance condition.
75+
property_conjuncts.push_back(
76+
F_exprt{G_exprt{not_exprt{buechi.liveness_signal}}});
77+
}
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7379
if(!buechi.error_signal.is_true())
74-
property.normalized_expr = and_exprt{
75-
property.normalized_expr, G_exprt{not_exprt{buechi.error_signal}}};
80+
{
81+
property_conjuncts.push_back(G_exprt{not_exprt{buechi.error_signal}});
82+
}
83+
84+
property.normalized_expr = conjunction(property_conjuncts);
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7786
message.debug() << "New property: " << format(property.normalized_expr)
7887
<< messaget::eom;

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