Verilog: module port declarations with default value

This fixes the grammar to allow ANSI module port declarations that have a
default value.

This adds support for module ports (ANSI and non-ANSI) that have a default
value to the type checker.

Author: kroening

regression/verilog/modules/port_with_value2.desc

@@ -0,0 +1,9 @@
+CORE
+port_with_value2.sv
+
+^file .* line 2: output ports must not have a default value$
+^EXIT=2$
+^SIGNAL=0$
+--
+^warning: ignoring
+--

regression/verilog/modules/port_with_value2.sv

@@ -0,0 +1,4 @@
+// output ports must not have a default value
+module M(output [31:0] o = 4567);
+
+endmodule

regression/verilog/modules/port_with_value3.desc

@@ -0,0 +1,9 @@
+CORE
+port_with_value3.sv
+
+^file .* line 2: expected constant expression, but got `M\.a'$
+^EXIT=2$
+^SIGNAL=0$
+--
+^warning: ignoring
+--

regression/verilog/modules/port_with_value3.sv

@@ -0,0 +1,4 @@
+// default values for inputs must be constants
+module M(input a, input b = a);
+
+endmodule

src/verilog/parser.y

@@ -899,14 +899,15 @@ ansi_port_declaration_brace:
 
           // append to last one -- required to make 
           // the grammar LR1
-	| ansi_port_declaration_brace ',' port_identifier
+	| ansi_port_declaration_brace ',' port_identifier ansi_port_initializer_opt
 		{ $$=$1;
 		  exprt decl(ID_decl);
 		  decl.add_to_operands(std::move(stack_expr($3)));
 		  // grab the type and class from previous!
 		  const irept &prev=stack_expr($$).get_sub().back();
                   decl.set(ID_type, prev.find(ID_type));
                   decl.set(ID_class, prev.find(ID_class));
+                  decl.set(ID_value, stack_expr($4));
 		  stack_expr($$).move_to_sub(decl);
 		}
 	;
@@ -935,6 +936,7 @@ ansi_port_declaration:
                   // and the unpacked_array_type goes onto the declarator.
                   stack_expr($$).type() = std::move(stack_expr($1).type());
                   addswap($2, ID_type, $3);
+                  stack_expr($2).set(ID_value, stack_expr($4));
                   mto($$, $2); /* declarator */ }
 	| variable_port_header port_identifier unpacked_dimension_brace ansi_port_initializer_opt
 		{ init($$, ID_decl);
@@ -946,6 +948,7 @@ ansi_port_declaration:
                   // and the unpacked_array_type goes onto the declarator.
                   stack_expr($$).type() = std::move(stack_expr($1).type());
                   addswap($2, ID_type, $3);
+                  stack_expr($2).set(ID_value, stack_expr($4));
                   mto($$, $2); /* declarator */ }
 	;
 

src/verilog/verilog_elaborate.cpp

@@ -62,6 +62,21 @@ void verilog_typecheckt::collect_port_symbols(const verilog_declt &decl)
     new_symbol.base_name = base_name;
     new_symbol.pretty_name = strip_verilog_prefix(new_symbol.name);
 
+    // When using ANSI style, input ports may have an
+    // elaboration-time constant default value
+    auto &default_value = declarator.value();
+    if(default_value.is_not_nil())
+    {
+      if(new_symbol.is_output)
+        throw errort{}.with_location(default_value.source_location())
+          << "output ports must not have a default value";
+
+      auto value = default_value;
+      convert_expr(value);
+      auto elaborated_value = elaborate_constant_expression_check(value);
+      new_symbol.value = elaborated_value;
+    }
+
     add_symbol(std::move(new_symbol));
   }
 }