SystemVerilog: nested modules

This adds SystemVerilog nested modules.

Author: kroening

regression/verilog/modules/nested1.desc

@@ -0,0 +1,6 @@
+CORE
+nested1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--

regression/verilog/modules/nested1.sv

@@ -0,0 +1,11 @@
+module main;
+
+  module my_module;
+    wire [7:0] value = 123;
+  endmodule
+
+  my_module m();
+
+  assert final (m.value == 123);
+
+endmodule

src/verilog/parser.y

@@ -870,8 +870,9 @@ module_or_generate_item_declaration:
 non_port_module_item:
 	  attribute_instance_brace generate_region { $$=$2; }
         | module_or_generate_item
-        | attribute_instance_brace specparam_declaration {$$=$2; }
 	| attribute_instance_brace specify_block { $$=$2;}
+        | attribute_instance_brace specparam_declaration {$$=$2; }
+        | module_declaration
         ;
 
 /*