Verilog: test for assignment to indexed part select

This adds a test for an assignment to an indexed part select with constant
indices.

Author: kroening

regression/verilog/part-select/indexed-part-select5.desc

@@ -0,0 +1,8 @@
+CORE
+indexed-part-select5.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--

regression/verilog/part-select/indexed-part-select5.sv

@@ -0,0 +1,14 @@
+module main(input my_input);
+
+  bit [7:0] some_wire;
+
+  always @my_input begin
+    some_wire[0 +: 2] = 'b01;
+    some_wire[2 +: 2] = 'b01;
+    some_wire[4 +: 2] = 'b01;
+    some_wire[6 +: 2] = 'b01;
+  end
+
+  p0: assert final (some_wire == 'b01_01_01_01);
+
+endmodule