We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
2 parents cca88cd + 0c34ed7 commit ada2100Copy full SHA for ada2100
regression/verilog/part-select/indexed-part-select4.desc
@@ -0,0 +1,9 @@
1
+KNOWNBUG
2
+indexed-part-select4.sv
3
+--bound 0
4
+^EXIT=0$
5
+^SIGNAL=0$
6
+--
7
+^warning: ignoring
8
9
+Synthesis-time constant folding for the index does not work.
regression/verilog/part-select/indexed-part-select4.sv
@@ -0,0 +1,14 @@
+module main(input my_input);
+
+ bit [7:0] some_wire;
+ always @my_input begin
+ integer i;
+ for(i=0; i<4; i++)
+ // part select with index known at synthesis time
+ some_wire[i * 2 +: 2] = 'b01;
10
+ end
11
12
+ p0: assert final (some_wire == 'b01_01_01_01);
13
14
+endmodule
0 commit comments