SystemVerilog .*

SystemVerilog 1800-2005 has introduced the .* operator, used for

a) implicit port connections, and

b) patterns.

This adds support to the scanner, parser, and type checker.

Author: kroening

CHANGELOG

@@ -5,6 +5,7 @@
 * Verilog: $onehot and $onehot0 are now elaboration-time constant
 * SystemVerilog: fix for #-# and #=# for empty matches
 * SystemVerilog: fix for |-> and |=> for empty matches
+* SystemVerilog: support 1800-2005 .*
 * LTL/SVA to Buechi with --buechi
 * SMV: abs, bool, count, max, min, toint, word1
 * BMC: new encoding for F, avoiding spurious traces

src/verilog/parser.y

@@ -405,6 +405,7 @@ int yyverilogerror(const char *error)
 %token TOK_LSQPLUS              "[+"
 %token TOK_LSQEQUAL             "[="
 %token TOK_LSQMINUSGREATER      "[->"
+%token TOK_DOTASTERIC           ".*"
 
 /* System Verilog Keywords */
 %token TOK_ACCEPT_ON        "accept_on"

src/verilog/scanner.l

@@ -273,6 +273,8 @@ void verilog_scanner_init()
 "[+"            { SYSTEM_VERILOG_OPERATOR(TOK_LSQPLUS, "[+"); }
 "[="            { SYSTEM_VERILOG_OPERATOR(TOK_LSQEQUAL, "[="); }
 "[->"           { SYSTEM_VERILOG_OPERATOR(TOK_LSQMINUSGREATER, "[->"); }
+                /* port connections, patterns */
+".*"            { SYSTEM_VERILOG_OPERATOR(TOK_DOTASTERIC, ".*"); }
 
                 /* Verilog 1364-1995 keywords */