From 86b9c0078559eb676c362a3284b70717139f4549 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Sat, 20 Jul 2024 09:19:57 -0700
Subject: [PATCH] SystemVerilog: KNOWNBUG test for nested modules

This adds a test for SystemVerilog nested modules.
---
 regression/verilog/modules/nested1.desc |  6 ++++++
 regression/verilog/modules/nested1.sv   | 11 +++++++++++
 2 files changed, 17 insertions(+)
 create mode 100644 regression/verilog/modules/nested1.desc
 create mode 100644 regression/verilog/modules/nested1.sv

diff --git a/regression/verilog/modules/nested1.desc b/regression/verilog/modules/nested1.desc
new file mode 100644
index 000000000..84f142e5b
--- /dev/null
+++ b/regression/verilog/modules/nested1.desc
@@ -0,0 +1,6 @@
+KNOWNBUG
+nested1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
diff --git a/regression/verilog/modules/nested1.sv b/regression/verilog/modules/nested1.sv
new file mode 100644
index 000000000..ffba7ab4b
--- /dev/null
+++ b/regression/verilog/modules/nested1.sv
@@ -0,0 +1,11 @@
+module main;
+
+  module my_module;
+    wire [7:0] value = 123;
+  endmodule
+
+  my_module m();
+
+  assert final (m.value == 123);
+
+endmodule