From e0b31a66c0fa9dc2dbeba09f3cbc8c763c42ed8d Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Mon, 26 Aug 2024 17:39:06 -0700
Subject: [PATCH] Verilog: non_port_module_item grammar rule

This changes the non_port_module_item grammar rule to match IEEE 1800-2017
Sec 23.2.4.
---
 src/verilog/parser.y | 17 ++++-------------
 1 file changed, 4 insertions(+), 13 deletions(-)

diff --git a/src/verilog/parser.y b/src/verilog/parser.y
index 1dd472595..1994cf3bc 100644
--- a/src/verilog/parser.y
+++ b/src/verilog/parser.y
@@ -905,24 +905,15 @@ module_or_generate_item_declaration:
 	;
 
 non_port_module_item:
-	  attribute_instance_brace generate_region
-		{ add_attributes($2, $1); $$=$2; }
+	  generate_region
         | module_or_generate_item
         | attribute_instance_brace specparam_declaration
 		{ add_attributes($2, $1); $$=$2; }
-	| attribute_instance_brace specify_block
-		{ add_attributes($2, $1); $$=$2; }
+        | program_declaration
+        | module_declaration
+        | interface_declaration
         ;
 
-/*
-	  module_or_generate_item
-	| attribute_instance_brace parameter_declaration
-	//	{ add_attributes($2, $1); $$=$2; }
-	// | attribute_instance_brace local_parameter_declaration
-	//	{ add_attributes($2, $1); $$=$2; }
-	;
-*/
-
 // System Verilog standard 1800-2017
 // A.1.5 Configuration source text