From b76612a27a1aa1c6f8392ab79c3a8bc61e112592 Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Mon, 26 Aug 2024 13:12:17 -0700 Subject: [PATCH] Verilog: parse tree now is a list of generic compilation unit items SystemVerilog allows a broad range of items to appear at the compilation unit level. This changes the parse tree to be a list of generic compilation unit items. --- src/verilog/parser.y | 2 +- src/verilog/verilog_expr.h | 3 +- src/verilog/verilog_language.cpp | 2 +- src/verilog/verilog_parse_tree.cpp | 59 ++++++++++++------------------ src/verilog/verilog_parse_tree.h | 45 +++++------------------ src/verilog/verilog_typecheck.cpp | 5 +-- 6 files changed, 38 insertions(+), 78 deletions(-) diff --git a/src/verilog/parser.y b/src/verilog/parser.y index 1994cf3bc..778ae5530 100644 --- a/src/verilog/parser.y +++ b/src/verilog/parser.y @@ -616,7 +616,7 @@ description: | package_declaration | attribute_instance_brace package_item { add_attributes($2, $1); - PARSER.parse_tree.create_package_item(stack_expr($2)); } + PARSER.parse_tree.add_item(stack_expr($2)); } | attribute_instance_brace bind_directive | config_declaration ; diff --git a/src/verilog/verilog_expr.h b/src/verilog/verilog_expr.h index 3e1928154..d7cdd25b7 100644 --- a/src/verilog/verilog_expr.h +++ b/src/verilog/verilog_expr.h @@ -1893,9 +1893,8 @@ to_verilog_assume_statement(verilog_statementt &statement) class verilog_module_sourcet : public irept { public: - verilog_module_sourcet() = default; - explicit verilog_module_sourcet(irep_idt _base_name) + : irept(ID_verilog_module) { base_name(_base_name); } diff --git a/src/verilog/verilog_language.cpp b/src/verilog/verilog_language.cpp index 5c7d345c6..bca21c6fc 100644 --- a/src/verilog/verilog_language.cpp +++ b/src/verilog/verilog_language.cpp @@ -136,7 +136,7 @@ void verilog_languaget::dependencies( { // dependencies on other Verilog modules - const auto &module = (it->second)->verilog_module; + const auto &module = *it->second; for(auto &identifier : module.submodules()) module_set.insert(id2string(identifier)); diff --git a/src/verilog/verilog_parse_tree.cpp b/src/verilog/verilog_parse_tree.cpp index 1cac5be98..62174e19e 100644 --- a/src/verilog/verilog_parse_tree.cpp +++ b/src/verilog/verilog_parse_tree.cpp @@ -29,8 +29,6 @@ void verilog_parse_treet::create_module( exprt &ports, exprt &module_items) { - items.push_back(itemt(itemt::MODULE)); - if(ports.get_sub().size()==1 && ports.get_sub().front().is_nil()) ports.clear(); @@ -43,10 +41,10 @@ void verilog_parse_treet::create_module( ((const exprt &)module_keyword).source_location(); new_module.add(ID_module_items) = std::move(module_items); - items.back().verilog_module = std::move(new_module); + auto &new_item = add_item(std::move(new_module)); // add to module map - module_map[name.id()] = --items.end(); + module_map[name.id()] = &to_verilog_module_source(new_item); } /*******************************************************************\ @@ -64,12 +62,12 @@ Function: verilog_parse_treet::modules_provided void verilog_parse_treet::modules_provided( std::set &module_set) const { - for(itemst::const_iterator it=items.begin(); - it!=items.end(); - it++) - if(it->is_module()) - module_set.insert( - id2string(verilog_module_symbol(it->verilog_module.base_name()))); + for(auto &item : items) + { + if(item.id() == ID_verilog_module) + module_set.insert(id2string( + verilog_module_symbol(to_verilog_module_source(item).base_name()))); + } } /*******************************************************************\ @@ -88,11 +86,14 @@ void verilog_parse_treet::build_module_map() { module_map.clear(); - for(itemst::iterator it=items.begin(); - it!=items.end(); - it++) - if(it->is_module()) - module_map[it->verilog_module.base_name()] = it; + for(const auto &item : items) + { + if(item.id() == ID_verilog_module) + { + auto &verilog_module = to_verilog_module_source(item); + module_map[verilog_module.base_name()] = &verilog_module; + } + } } /*******************************************************************\ @@ -109,15 +110,13 @@ Function: verilog_parse_treet::show void verilog_parse_treet::show(std::ostream &out) const { - for(itemst::const_iterator it=items.begin(); - it!=items.end(); - it++) - it->show(out); + for(const auto &item : items) + show(item, out); } /*******************************************************************\ -Function: verilog_parse_treet::itemt::show +Function: verilog_parse_treet::show Inputs: @@ -127,20 +126,10 @@ Function: verilog_parse_treet::itemt::show \*******************************************************************/ -void verilog_parse_treet::itemt::show(std::ostream &out) const +void verilog_parse_treet::show(const itemt &item, std::ostream &out) const { - switch(type) - { - case itemt::MODULE: - verilog_module.show(out); - break; - - case itemt::PACKAGE_ITEM: - out << "Package item:\n"; - out << verilog_package_item.pretty() << '\n'; - break; - - default: - PRECONDITION(false); - } + if(item.id() == ID_verilog_module) + to_verilog_module_source(item).show(out); + else + out << item.pretty() << '\n'; } diff --git a/src/verilog/verilog_parse_tree.h b/src/verilog/verilog_parse_tree.h index e27ce1a6b..40cc2685d 100644 --- a/src/verilog/verilog_parse_tree.h +++ b/src/verilog/verilog_parse_tree.h @@ -27,37 +27,10 @@ class verilog_parse_treet verilog_standardt standard; - struct itemt - { - public: - typedef enum - { - MODULE, - PACKAGE_ITEM - } item_typet; - item_typet type; - - explicit itemt(item_typet __type) : type(__type) - { - } - - verilog_module_sourcet verilog_module; - - exprt verilog_package_item; - - bool is_module() const - { - return type==MODULE; - } - - bool is_package_item() const - { - return type == PACKAGE_ITEM; - } - - void show(std::ostream &out) const; - }; - + using itemt = irept; + + void show(const itemt &, std::ostream &) const; + typedef std::list itemst; itemst items; @@ -83,10 +56,10 @@ class verilog_parse_treet exprt &ports, exprt &statements); - void create_package_item(exprt package_item) + itemt &add_item(itemt item) { - items.push_back(itemt(itemt::PACKAGE_ITEM)); - items.back().verilog_package_item = std::move(package_item); + items.push_back(std::move(item)); + return items.back(); } void swap(verilog_parse_treet &parse_tree) @@ -100,7 +73,9 @@ class verilog_parse_treet void modules_provided( std::set &module_set) const; - typedef std::unordered_map module_mapt; + typedef std:: + unordered_map + module_mapt; module_mapt module_map; void build_module_map(); diff --git a/src/verilog/verilog_typecheck.cpp b/src/verilog/verilog_typecheck.cpp index ae284a140..bbf5d2594 100644 --- a/src/verilog/verilog_typecheck.cpp +++ b/src/verilog/verilog_typecheck.cpp @@ -1847,10 +1847,7 @@ bool verilog_typecheck( } return verilog_typecheck( - symbol_table, - it->second->verilog_module, - parse_tree.standard, - message_handler); + symbol_table, *it->second, parse_tree.standard, message_handler); } /*******************************************************************\