From 2c01a3aba5b68995ca516bfc8165174265fc4d25 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Fri, 30 Aug 2024 16:35:32 -0700
Subject: [PATCH] move signed1 test

This moves the signed1 test into the expressions subdirectory.
---
 .../test.desc => expressions/signed1.desc}        |  4 ++--
 regression/verilog/expressions/signed1.sv         | 15 +++++++++++++++
 regression/verilog/signed1/main.v                 | 15 ---------------
 3 files changed, 17 insertions(+), 17 deletions(-)
 rename regression/verilog/{signed1/test.desc => expressions/signed1.desc} (57%)
 create mode 100644 regression/verilog/expressions/signed1.sv
 delete mode 100644 regression/verilog/signed1/main.v

diff --git a/regression/verilog/signed1/test.desc b/regression/verilog/expressions/signed1.desc
similarity index 57%
rename from regression/verilog/signed1/test.desc
rename to regression/verilog/expressions/signed1.desc
index 6a3d0fa20..2c2b91706 100644
--- a/regression/verilog/signed1/test.desc
+++ b/regression/verilog/expressions/signed1.desc
@@ -1,6 +1,6 @@
 CORE
-main.v
---module main --bound 1
+signed1.sv
+--module main --bound 0
 ^EXIT=0$
 ^SIGNAL=0$
 --
diff --git a/regression/verilog/expressions/signed1.sv b/regression/verilog/expressions/signed1.sv
new file mode 100644
index 000000000..9ea0e2422
--- /dev/null
+++ b/regression/verilog/expressions/signed1.sv
@@ -0,0 +1,15 @@
+module main;
+
+  wire signed [31:0] wire1 = -1;
+  wire [31:0] wire2 = -1;
+  
+  p1: assert final (wire1==wire2);
+  p2: assert final ((wire1 >>> 1)==-1);
+  p3: assert final ((wire2 >>> 1)!=-1);
+  p4: assert final ((wire1[31:0] >>> 1)!=-1); // part-selects are unsigned
+  p5: assert final (($unsigned(wire1) >>> 1)!=-1);
+  p6: assert final (($signed(wire2) >>> 1)==-1);
+  p7: assert final ((-'d1 >>> 1)!=-1); // based numbers are unsigned
+  p8: assert final ((-1 >>> 1)==-1);
+
+endmodule
diff --git a/regression/verilog/signed1/main.v b/regression/verilog/signed1/main.v
deleted file mode 100644
index 38131af31..000000000
--- a/regression/verilog/signed1/main.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module main;
-
-  wire signed [31:0] wire1 = -1;
-  wire [31:0] wire2 = -1;
-  
-  always assert p1: wire1==wire2;
-  always assert p2: (wire1 >>> 1)==-1;
-  always assert p3: (wire2 >>> 1)!=-1;
-  always assert p4: (wire1[31:0] >>> 1)!=-1; // part-selects are unsigned
-  always assert p5: ($unsigned(wire1) >>> 1)!=-1;
-  always assert p6: ($signed(wire2) >>> 1)==-1;
-  always assert p7: (-'d1 >>> 1)!=-1; // based numbers are unsigned
-  always assert p8: (-1 >>> 1)==-1;
-
-endmodule