From c7c1fae2299ff19a23213f592199a18ab3982cc6 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Fri, 30 Aug 2024 16:40:34 -0700
Subject: [PATCH] Verilog: KNOWNBUG test for signed base 2 literal

The signed base 2 literal should be sign-extended.
---
 regression/verilog/expressions/signed2.desc | 9 +++++++++
 regression/verilog/expressions/signed2.sv   | 7 +++++++
 2 files changed, 16 insertions(+)
 create mode 100644 regression/verilog/expressions/signed2.desc
 create mode 100644 regression/verilog/expressions/signed2.sv

diff --git a/regression/verilog/expressions/signed2.desc b/regression/verilog/expressions/signed2.desc
new file mode 100644
index 000000000..3904ebe12
--- /dev/null
+++ b/regression/verilog/expressions/signed2.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+signed2.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The signed base 2 literal should be sign-extended.
diff --git a/regression/verilog/expressions/signed2.sv b/regression/verilog/expressions/signed2.sv
new file mode 100644
index 000000000..3183e9393
--- /dev/null
+++ b/regression/verilog/expressions/signed2.sv
@@ -0,0 +1,7 @@
+module main;
+
+  p0: assert final ('sb1 == -1);
+  p1: assert final ('sb11 == -1);
+  p2: assert final (4'sb111 == 7);
+
+endmodule