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| 1 | + |
| 2 | +/*- |
| 3 | + * SPDX-License-Identifier: BSD-2-Clause |
| 4 | + * |
| 5 | + * Copyright (c) 2021 Jesper Schmitz Mouridsen <[email protected]> |
| 6 | + * Copyright (c) 2019 Jonathan A. Kollasch <[email protected]> |
| 7 | +
|
| 8 | + * Redistribution and use in source and binary forms, with or without |
| 9 | + * modification, are permitted provided that the following conditions |
| 10 | + * are met: |
| 11 | + * 1. Redistributions of source code must retain the above copyright |
| 12 | + * notice, this list of conditions and the following disclaimer. |
| 13 | + * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | + * notice, this list of conditions and the following disclaimer in the |
| 15 | + * documentation and/or other materials provided with the distribution. |
| 16 | + * |
| 17 | + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 18 | + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 21 | + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 22 | + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 23 | + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 24 | + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 25 | + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 26 | + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | + * SUCH DAMAGE. |
| 28 | + * |
| 29 | + * $FreeBSD$ |
| 30 | + */ |
| 31 | + |
| 32 | + |
| 33 | +#ifndef __ANXEDP_H__ |
| 34 | +#define __ANXEDP_H__ |
| 35 | +#include <drm/drmP.h> |
| 36 | +#include <drm/drm_crtc.h> |
| 37 | +#undef CONFIG_DRM_DP_CEC |
| 38 | +#include <drm/drm_crtc_helper.h> |
| 39 | +#include <drm/drm_dp_helper.h> |
| 40 | +#include <drm/drm_edid.h> |
| 41 | +#include <drm/drm_dp_helper.h> |
| 42 | +#include <drm/drm_probe_helper.h> |
| 43 | +#include <drm/drm_bridge.h> |
| 44 | +#include <drm/drm_panel.h> |
| 45 | +#include <drm/drm_connector.h> |
| 46 | +#include <drm/drm_edid.h> |
| 47 | +#include <linux/bitops.h> |
| 48 | +#include "dev/drm/rockchip/rk_edp.h" |
| 49 | +#define __BITS(hi,lo) ((~((~0)<<((hi)+1)))&((~0)<<(lo))) |
| 50 | +#define __BIT BIT |
| 51 | +#define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) |
| 52 | +#define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask)) |
| 53 | +#define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) |
| 54 | +#define ANXDP_AUDIO 0 |
| 55 | +#define ANXDP_DP_TX_VERSION 0x010 |
| 56 | +#define ANXDP_TX_SW_RESET 0x014 |
| 57 | +#define RESET_DP_TX __BIT(0) |
| 58 | +#define ANXDP_FUNC_EN_1 0x018 |
| 59 | +#define MASTER_VID_FUNC_EN_N __BIT(7) |
| 60 | +#define RK_VID_CAP_FUNC_EN_N __BIT(6) |
| 61 | +#define SLAVE_VID_FUNC_EN_N __BIT(5) |
| 62 | +#define RK_VID_FIFO_FUNC_EN_N __BIT(5) |
| 63 | +#define AUD_FIFO_FUNC_EN_N __BIT(4) |
| 64 | +#define AUD_FUNC_EN_N __BIT(3) |
| 65 | +#define HDCP_FUNC_EN_N __BIT(2) |
| 66 | +#define CRC_FUNC_EN_N __BIT(1) |
| 67 | +#define SW_FUNC_EN_N __BIT(0) |
| 68 | +#define ANXDP_FUNC_EN_2 0x01c |
| 69 | +#define SSC_FUNC_EN_N __BIT(7) |
| 70 | +#define AUX_FUNC_EN_N __BIT(2) |
| 71 | +#define SERDES_FIFO_FUNC_EN_N __BIT(1) |
| 72 | +#define LS_CLK_DOMAIN_FUNC_EN_N __BIT(0) |
| 73 | +#define ANXDP_VIDEO_CTL_1 0x020 |
| 74 | +#define VIDEO_EN __BIT(7) |
| 75 | +#define VIDEO_MUTE __BIT(6) |
| 76 | +#define ANXDP_VIDEO_CTL_2 0x024 |
| 77 | +#define ANXDP_VIDEO_CTL_3 0x028 |
| 78 | +#define ANXDP_VIDEO_CTL_4 0x02c |
| 79 | +#define ANXDP_VIDEO_CTL_8 0x03c |
| 80 | +#define ANXDP_VIDEO_CTL_10 0x044 |
| 81 | +#define F_SEL __BIT(4) |
| 82 | +#define SLAVE_I_SCAN_CFG __BIT(2) |
| 83 | +#define SLAVE_VSYNC_P_CFG __BIT(1) |
| 84 | +#define SLAVE_HSYNC_P_CFG __BIT(0) |
| 85 | +#define ANXDP_PLL_REG_1 0x0fc |
| 86 | +#define REF_CLK_24M __BIT(0) |
| 87 | +#define RKANXDP_PD 0x12c |
| 88 | +#define DP_INC_BG __BIT(7) |
| 89 | +#define DP_EXP_PD __BIT(6) |
| 90 | +#define DP_PHY_PD __BIT(5) |
| 91 | +#define RK_AUX_PD __BIT(5) |
| 92 | +#define AUX_PD __BIT(4) |
| 93 | +#define RK_PLL_PD __BIT(4) |
| 94 | +#define CHx_PD(x) __BIT(x) /* 0<=x<=3 */ |
| 95 | +#define DP_ALL_PD __BITS(7,0) |
| 96 | +#define ANXDP_LANE_MAP 0x35c |
| 97 | +#define ANXDP_ANALOG_CTL_1 0x370 |
| 98 | +#define TX_TERMINAL_CTRL_50_OHM __BIT(4) |
| 99 | +#define ANXDP_ANALOG_CTL_2 0x374 |
| 100 | +#define SEL_24M __BIT(3) |
| 101 | +#define TX_DVDD_BIT_1_0625V 0x4 |
| 102 | +#define ANXDP_ANALOG_CTL_3 0x378 |
| 103 | +#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) |
| 104 | +#define VCO_BIT_600_MICRO (0x5 << 0) |
| 105 | +#define ANXDP_PLL_FILTER_CTL_1 0x37c |
| 106 | +#define PD_RING_OSC __BIT(6) |
| 107 | +#define AUX_TERMINAL_CTRL_50_OHM (2 << 4) |
| 108 | +#define TX_CUR1_2X __BIT(2) |
| 109 | +#define TX_CUR_16_MA 3 |
| 110 | +#define ANXDP_TX_AMP_TUNING_CTL 0x380 |
| 111 | +#define ANXDP_AUX_HW_RETRY_CTL 0x390 |
| 112 | +#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) __SHIFTIN((x), __BITS(10,8)) |
| 113 | +#define AUX_HW_RETRY_INTERVAL_600_US __SHIFTIN(0, __BITS(4,3)) |
| 114 | +#define AUX_HW_RETRY_INTERVAL_800_US __SHIFTIN(1, __BITS(4,3)) |
| 115 | +#define AUX_HW_RETRY_INTERVAL_1000_US __SHIFTIN(2, __BITS(4,3)) |
| 116 | +#define AUX_HW_RETRY_INTERVAL_1800_US __SHIFTIN(3, __BITS(4,3)) |
| 117 | +#define AUX_HW_RETRY_COUNT_SEL(x) __SHIFTIN((x), __BITS(2,0)) |
| 118 | +#define ANXDP_COMMON_INT_STA_1 0x3c4 |
| 119 | +#define PLL_LOCK_CHG __BIT(6) |
| 120 | +#define ANXDP_COMMON_INT_STA_2 0x3c8 |
| 121 | +#define ANXDP_COMMON_INT_STA_3 0x3cc |
| 122 | +#define ANXDP_COMMON_INT_STA_4 0x3d0 |
| 123 | +#define ANXDP_DP_INT_STA 0x3dc |
| 124 | +#define INT_HPD __BIT(6) |
| 125 | +#define HW_TRAINING_FINISH __BIT(5) |
| 126 | +#define RPLY_RECEIV __BIT(1) |
| 127 | +#define AUX_ERR __BIT(0) |
| 128 | +#define ANXDP_SYS_CTL_1 0x600 |
| 129 | +#define DET_STA __BIT(2) |
| 130 | +#define FORCE_DET __BIT(1) |
| 131 | +#define DET_CTRL __BIT(0) |
| 132 | +#define ANXDP_SYS_CTL_2 0x604 |
| 133 | +#define ANXDP_SYS_CTL_3 0x608 |
| 134 | +#define HPD_STATUS __BIT(6) |
| 135 | +#define F_HPD __BIT(5) |
| 136 | +#define HPD_CTRL __BIT(4) |
| 137 | +#define HDCP_RDY __BIT(3) |
| 138 | +#define STRM_VALID __BIT(2) |
| 139 | +#define F_VALID __BIT(1) |
| 140 | +#define VALID_CTRL __BIT(0) |
| 141 | +#define ANXDP_SYS_CTL_4 0x60c |
| 142 | +#define ANXDP_PKT_SEND_CTL 0x640 |
| 143 | +#define ANXDP_HDCP_CTL 0x648 |
| 144 | +#define ANXDP_LINK_BW_SET 0x680 |
| 145 | +#define ANXDP_LANE_COUNT_SET 0x684 |
| 146 | +#define ANXDP_TRAINING_PTN_SET 0x688 |
| 147 | +#define SCRAMBLING_DISABLE __BIT(5) |
| 148 | +#define SW_TRAINING_PATTERN_SET_PTN2 __SHIFTIN(2, __BITS(1,0)) |
| 149 | +#define SW_TRAINING_PATTERN_SET_PTN1 __SHIFTIN(1, __BITS(1,0)) |
| 150 | +#define ANXDP_LNx_LINK_TRAINING_CTL(x) (0x68c + 4 * (x)) /* 0 <= x <= 3 */ |
| 151 | +#define MAX_PRE_REACH __BIT(5) |
| 152 | +#define PRE_EMPHASIS_SET(x) __SHIFTIN((x), __BITS(4,3)) |
| 153 | +#define MAX_DRIVE_REACH __BIT(2) |
| 154 | +#define DRIVE_CURRENT_SET(x) __SHIFTIN((x), __BITS(1,0)) |
| 155 | +#define ANXDP_DEBUG_CTL 0x6c0 |
| 156 | +#define PLL_LOCK __BIT(4) |
| 157 | +#define F_PLL_LOCK __BIT(3) |
| 158 | +#define PLL_LOCK_CTRL __BIT(2) |
| 159 | +#define PN_INV __BIT(0) |
| 160 | +#define ANXDP_LINK_DEBUG_CTL 0x6e0 |
| 161 | +#define ANXDP_PLL_CTL 0x71c |
| 162 | +#define ANXDP_PHY_PD 0x720 |
| 163 | +#define ANXDP_PHY_TEST 0x724 |
| 164 | +#define MACRO_RST __BIT(5) |
| 165 | +#define ANXDP_M_AUD_GEN_FILTER_TH 0x778 |
| 166 | +#define ANXDP_AUX_CH_STA 0x780 |
| 167 | +#define AUX_BUSY __BIT(4) |
| 168 | +#define AUX_STATUS(x) __SHIFTOUT((x), __BITS(3,0)) |
| 169 | +#define ANXDP_AUX_ERR_NUM 0x784 |
| 170 | +#define ANXDP_AUX_CH_DEFER_CTL 0x788 |
| 171 | +#define DEFER_CTRL_EN __BIT(7) |
| 172 | +#define DEFER_COUNT(x) __SHIFTIN((x), __BITS(6,0)) |
| 173 | +#define ANXDP_AUX_RX_COMM 0x78c |
| 174 | +#define AUX_RX_COMM_I2C_DEFER __BIT(3) |
| 175 | +#define AUX_RX_COMM_AUX_DEFER __BIT(1) |
| 176 | +#define ANXDP_BUFFER_DATA_CTL 0x790 |
| 177 | +#define BUF_CLR __BIT(7) |
| 178 | +#define BUF_DATA_COUNT(x) __SHIFTIN((x), __BITS(4,0)) |
| 179 | +#define ANXDP_AUX_CH_CTL_1 0x794 |
| 180 | +#define AUX_LENGTH(x) __SHIFTIN((x) - 1, __BITS(7,4)) |
| 181 | +#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) |
| 182 | + |
| 183 | +#define AUX_TX_COMM(x) __SHIFTOUT(x, __BITS(3,0)) |
| 184 | +#define AUX_TX_COMM_DP __BIT(3) |
| 185 | +#define AUX_TX_COMM_MOT __BIT(2) |
| 186 | +#define AUX_TX_COMM_READ __BIT(0) |
| 187 | +#define ANXDP_AUX_ADDR_7_0 0x798 |
| 188 | +#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) |
| 189 | +#define ANXDP_AUX_ADDR_15_8 0x79c |
| 190 | +#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) |
| 191 | +#define ANXDP_AUX_ADDR_19_16 0x7a0 |
| 192 | +#define AUX_ADDR_19_16(x) (((x) >> 16) & 0xf) |
| 193 | +#define ANXDP_AUX_CH_CTL_2 0x7a4 |
| 194 | +#define ADDR_ONLY __BIT(1) |
| 195 | +#define AUX_EN __BIT(0) |
| 196 | +#define ANXDP_BUF_DATA(x) (0x7c0 + 4 * (x)) |
| 197 | +#define ANXDP_SOC_GENERAL_CTL 0x800 |
| 198 | +#define AUDIO_MODE_SPDIF_MODE __BIT(8) |
| 199 | +#define VIDEO_MODE_SLAVE_MODE __BIT(1) |
| 200 | +#define ANXDP_CRC_CON 0x890 |
| 201 | +#define ANXDP_PLL_REG_2 0x9e4 |
| 202 | +#define ANXDP_PLL_REG_3 0x9e8 |
| 203 | +#define ANXDP_PLL_REG_4 0x9ec |
| 204 | +#define ANXDP_PLL_REG_5 0xa00 |
| 205 | + |
| 206 | + |
| 207 | + |
| 208 | +struct rk_edp_softc; |
| 209 | + |
| 210 | +struct anxdp_softc { |
| 211 | + struct mtx mtx; |
| 212 | + device_t iicbus; |
| 213 | + struct device* sc_dev; |
| 214 | + |
| 215 | + struct resource *res[2]; |
| 216 | + u_int sc_flags; |
| 217 | +#define ANXDP_FLAG_ROCKCHIP __BIT(0) |
| 218 | +struct drm_connector sc_connector; |
| 219 | + struct drm_encoder sc_encoder; |
| 220 | +struct drm_dp_aux sc_dpaux; |
| 221 | +struct drm_panel * sc_panel; |
| 222 | +uint8_t sc_dpcd[DP_RECEIVER_CAP_SIZE]; |
| 223 | + struct drm_bridge sc_bridge; |
| 224 | + struct drm_display_mode sc_curmode; |
| 225 | +}; |
| 226 | +struct rk_edp_softc { |
| 227 | + struct anxdp_softc sc_base; |
| 228 | + device_t dev; |
| 229 | + struct syscon *grf; |
| 230 | + clk_t pclk; |
| 231 | + clk_t dpclk; |
| 232 | + clk_t grfclk; |
| 233 | + |
| 234 | + |
| 235 | +}; |
| 236 | +#define ANXDP_LOCK(sc) mtx_lock(&(sc)->mtx) |
| 237 | +#define ANXDP_UNLOCK(sc) mtx_unlock(&(sc)->mtx) |
| 238 | +#define ANXDP_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) |
| 239 | +#define ANXDP_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) |
| 240 | + |
| 241 | +#define to_edp_connector(x) container_of(x, struct anxdp_connector, base) |
| 242 | +int anxdp_attach(struct anxdp_softc *sc); |
| 243 | +int anxdp_bind(struct anxdp_softc *sc,struct drm_encoder *encoder); |
| 244 | +void anxdp_init_aux(struct anxdp_softc * sc); |
| 245 | +void anxdp_add_bridge(struct anxdp_softc *sc,struct drm_encoder *encoder); |
| 246 | + |
| 247 | +DECLARE_CLASS(anxdp_driver); |
| 248 | +#endif /* ANXEDP_H */ |
| 249 | + |
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