diff --git a/bench/f32-conv-hwc2chw.cc b/bench/f32-conv-hwc2chw.cc index 4e3f93b063e..62474b75c46 100644 --- a/bench/f32-conv-hwc2chw.cc +++ b/bench/f32-conv-hwc2chw.cc @@ -161,21 +161,21 @@ static void f32_conv_hwc2chw_3x3s2p1c3x2v__rvv_1x1(benchmark::State& state, const char* net) { f32_conv_hwc2chw(state, xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_1x1, xnn_init_f32_minmax_scalar_params, - 2 * xnn_init_hardware_config()->vlenb / sizeof(float) /* output channel tile */); + 2 * xnn_get_hardware_config()->vlenb / sizeof(float) /* output channel tile */); } static void f32_conv_hwc2chw_3x3s2p1c3x2v__rvv_2x1(benchmark::State& state, const char* net) { f32_conv_hwc2chw(state, xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x1, xnn_init_f32_minmax_scalar_params, - 2 * xnn_init_hardware_config()->vlenb / sizeof(float) /* output channel tile */); + 2 * xnn_get_hardware_config()->vlenb / sizeof(float) /* output channel tile */); } static void f32_conv_hwc2chw_3x3s2p1c3x2v__rvv_2x2(benchmark::State& state, const char* net) { f32_conv_hwc2chw(state, xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x2, xnn_init_f32_minmax_scalar_params, - 2 * xnn_init_hardware_config()->vlenb / sizeof(float) /* output channel tile */); + 2 * xnn_get_hardware_config()->vlenb / sizeof(float) /* output channel tile */); } BENCHMARK_DCONV(f32_conv_hwc2chw_3x3s2p1c3x2v__rvv_1x1); diff --git a/bench/f32-gemm-minmax.cc b/bench/f32-gemm-minmax.cc index b48dfd5b7d0..c95f3b51d58 100644 --- a/bench/f32-gemm-minmax.cc +++ b/bench/f32-gemm-minmax.cc @@ -315,7 +315,7 @@ xnn_f32_gemm_minmax_ukernel_1x4v__rvv, xnn_init_f32_minmax_scalar_params, xnn_pack_f32_gemm_goi_w, - /*mr=*/1, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(float), /*kr=*/1, /*sr=*/1, + /*mr=*/1, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(float), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -326,7 +326,7 @@ xnn_f32_gemm_minmax_ukernel_7x4v__rvv, xnn_init_f32_minmax_scalar_params, xnn_pack_f32_gemm_goi_w, - /*mr=*/7, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(float), /*kr=*/1, /*sr=*/1, + /*mr=*/7, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(float), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } diff --git a/bench/qd8-f32-qc4w-gemm.cc b/bench/qd8-f32-qc4w-gemm.cc index 0a4be42debd..4a6cc51e727 100644 --- a/bench/qd8-f32-qc4w-gemm.cc +++ b/bench/qd8-f32-qc4w-gemm.cc @@ -26,7 +26,7 @@ xnn_qd8_f32_qc4w_gemm_minmax_ukernel_1x4v__rvv, xnn_init_f32_qc4w_minmax_scalar_params, xnn_pack_qs8_qc4w_gemm_goi_w, - /*mr=*/1, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/1, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -37,7 +37,7 @@ xnn_qd8_f32_qc4w_gemm_minmax_ukernel_2x4v__rvv, xnn_init_f32_qc4w_minmax_scalar_params, xnn_pack_qs8_qc4w_gemm_goi_w, - /*mr=*/2, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/2, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -48,7 +48,7 @@ xnn_qd8_f32_qc4w_gemm_minmax_ukernel_3x4v__rvv, xnn_init_f32_qc4w_minmax_scalar_params, xnn_pack_qs8_qc4w_gemm_goi_w, - /*mr=*/3, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/3, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -59,7 +59,7 @@ xnn_qd8_f32_qc4w_gemm_minmax_ukernel_4x4v__rvv, xnn_init_f32_qc4w_minmax_scalar_params, xnn_pack_qs8_qc4w_gemm_goi_w, - /*mr=*/4, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/4, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -70,7 +70,7 @@ xnn_qd8_f32_qc4w_gemm_minmax_ukernel_5x4v__rvv, xnn_init_f32_qc4w_minmax_scalar_params, xnn_pack_qs8_qc4w_gemm_goi_w, - /*mr=*/5, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/5, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -81,7 +81,7 @@ xnn_qd8_f32_qc4w_gemm_minmax_ukernel_6x4v__rvv, xnn_init_f32_qc4w_minmax_scalar_params, xnn_pack_qs8_qc4w_gemm_goi_w, - /*mr=*/6, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/6, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -92,7 +92,7 @@ xnn_qd8_f32_qc4w_gemm_minmax_ukernel_7x4v__rvv, xnn_init_f32_qc4w_minmax_scalar_params, xnn_pack_qs8_qc4w_gemm_goi_w, - /*mr=*/7, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/7, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -103,7 +103,7 @@ xnn_qd8_f32_qc4w_gemm_minmax_ukernel_8x4v__rvv, xnn_init_f32_qc4w_minmax_scalar_params, xnn_pack_qs8_qc4w_gemm_goi_w, - /*mr=*/8, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/8, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } diff --git a/bench/qd8-f32-qc8w-gemm.cc b/bench/qd8-f32-qc8w-gemm.cc index 198f14167a6..d9e0a634e64 100644 --- a/bench/qd8-f32-qc8w-gemm.cc +++ b/bench/qd8-f32-qc8w-gemm.cc @@ -26,7 +26,7 @@ xnn_qd8_f32_qc8w_gemm_minmax_ukernel_1x4v__rvv, xnn_init_f32_minmax_scalar_params, xnn_pack_qs8_gemm_goi_w, - /*mr=*/1, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/1, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -37,7 +37,7 @@ xnn_qd8_f32_qc8w_gemm_minmax_ukernel_2x4v__rvv, xnn_init_f32_minmax_scalar_params, xnn_pack_qs8_gemm_goi_w, - /*mr=*/2, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/2, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -48,7 +48,7 @@ xnn_qd8_f32_qc8w_gemm_minmax_ukernel_3x4v__rvv, xnn_init_f32_minmax_scalar_params, xnn_pack_qs8_gemm_goi_w, - /*mr=*/3, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/3, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -59,7 +59,7 @@ xnn_qd8_f32_qc8w_gemm_minmax_ukernel_4x4v__rvv, xnn_init_f32_minmax_scalar_params, xnn_pack_qs8_gemm_goi_w, - /*mr=*/4, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/4, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -70,7 +70,7 @@ xnn_qd8_f32_qc8w_gemm_minmax_ukernel_5x4v__rvv, xnn_init_f32_minmax_scalar_params, xnn_pack_qs8_gemm_goi_w, - /*mr=*/5, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/5, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -81,7 +81,7 @@ xnn_qd8_f32_qc8w_gemm_minmax_ukernel_6x4v__rvv, xnn_init_f32_minmax_scalar_params, xnn_pack_qs8_gemm_goi_w, - /*mr=*/6, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/6, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -92,7 +92,7 @@ xnn_qd8_f32_qc8w_gemm_minmax_ukernel_7x4v__rvv, xnn_init_f32_minmax_scalar_params, xnn_pack_qs8_gemm_goi_w, - /*mr=*/7, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/7, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -103,7 +103,7 @@ xnn_qd8_f32_qc8w_gemm_minmax_ukernel_8x4v__rvv, xnn_init_f32_minmax_scalar_params, xnn_pack_qs8_gemm_goi_w, - /*mr=*/8, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/8, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } diff --git a/bench/qs8-qc8w-gemm-fp32.cc b/bench/qs8-qc8w-gemm-fp32.cc index a3a28ba5e0d..28c73b93493 100644 --- a/bench/qs8-qc8w-gemm-fp32.cc +++ b/bench/qs8-qc8w-gemm-fp32.cc @@ -469,7 +469,7 @@ xnn_qs8_qc8w_gemm_minmax_fp32_ukernel_1x4v__rvv, xnn_init_qs8_qc8w_conv_minmax_fp32_scalar_params, xnn_pack_qs8_gemm_goi_w, - /*mr=*/1, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/1, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -480,7 +480,7 @@ xnn_qs8_qc8w_gemm_minmax_fp32_ukernel_4x4v__rvv, xnn_init_qs8_qc8w_conv_minmax_fp32_scalar_params, xnn_pack_qs8_gemm_goi_w, - /*mr=*/4, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/4, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } @@ -491,7 +491,7 @@ xnn_qs8_qc8w_gemm_minmax_fp32_ukernel_7x4v__rvv, xnn_init_qs8_qc8w_conv_minmax_fp32_scalar_params, xnn_pack_qs8_gemm_goi_w, - /*mr=*/7, /*nr=*/4 * xnn_init_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, + /*mr=*/7, /*nr=*/4 * xnn_get_hardware_config()->vlenb / sizeof(int32_t), /*kr=*/1, /*sr=*/1, /*arch_flags=*/xnn_arch_riscv_vector); } diff --git a/bench/utils.cc b/bench/utils.cc index c0d5e79e5af..853b876f803 100644 --- a/bench/utils.cc +++ b/bench/utils.cc @@ -259,7 +259,7 @@ size_t GetMaxCacheSize() { } bool CheckArchFlags(benchmark::State& state, uint64_t arch_flags) { - const xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == nullptr) { state.SkipWithError("no hardware config"); return false; diff --git a/src/configs/argmaxpool-config.c b/src/configs/argmaxpool-config.c index cfe6cd00181..94397fa82b9 100644 --- a/src/configs/argmaxpool-config.c +++ b/src/configs/argmaxpool-config.c @@ -19,7 +19,7 @@ XNN_INIT_ONCE_GUARD(f32_argmaxpool); static void init_f32_argmaxpool_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_argmaxpool_config = (struct xnn_argmaxpool_config) { @@ -60,8 +60,8 @@ static void init_f32_argmaxpool_config(void) { #endif } -const struct xnn_argmaxpool_config* xnn_init_f32_argmaxpool_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_argmaxpool_config* xnn_get_f32_argmaxpool_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/avgpool-config.c b/src/configs/avgpool-config.c index 6c94a78100c..5f2288db741 100644 --- a/src/configs/avgpool-config.c +++ b/src/configs/avgpool-config.c @@ -21,7 +21,7 @@ XNN_INIT_ONCE_GUARD(f32_avgpool); static void init_f16_avgpool_config(void) { #if (XNN_ARCH_ARM || XNN_ARCH_ARM64) && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_avgpool_config.ukernel = (xnn_avgpool_ukernel_fn) xnn_f16_avgpool_minmax_ukernel_9p__neonfp16arith_u8; @@ -30,7 +30,7 @@ static void init_f16_avgpool_config(void) { f16_avgpool_config.channel_tile = 8; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_f16c)) { f16_avgpool_config.ukernel = (xnn_avgpool_ukernel_fn) xnn_f16_avgpool_minmax_ukernel_9p__f16c_u8; @@ -43,7 +43,7 @@ static void init_f16_avgpool_config(void) { static void init_f32_avgpool_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_avgpool_config.ukernel = (xnn_avgpool_ukernel_fn) xnn_f32_avgpool_minmax_ukernel_9p__neon_u4; @@ -62,7 +62,7 @@ static void init_f32_avgpool_config(void) { f32_avgpool_config.primary_tile = 9; f32_avgpool_config.channel_tile = 4; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -101,8 +101,8 @@ static void init_f32_avgpool_config(void) { #endif } -const struct xnn_avgpool_config* xnn_init_f16_avgpool_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_avgpool_config* xnn_get_f16_avgpool_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -110,8 +110,8 @@ const struct xnn_avgpool_config* xnn_init_f16_avgpool_config() { return &f16_avgpool_config; } -const struct xnn_avgpool_config* xnn_init_f32_avgpool_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_avgpool_config* xnn_get_f32_avgpool_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/binary-elementwise-config.c b/src/configs/binary-elementwise-config.c index 0f8faa7a1b3..c6af76f940b 100644 --- a/src/configs/binary-elementwise-config.c +++ b/src/configs/binary-elementwise-config.c @@ -66,7 +66,7 @@ XNN_INIT_ONCE_GUARD(qu8_vprelu); static void init_f16_vadd_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vadd_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vadd_ukernel__neonfp16arith_u16; @@ -75,7 +75,7 @@ static void init_f16_vadd_config(void) { f16_vadd_config.element_tile = 16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vadd_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vadd_ukernel__neonfp16arith_u16; @@ -84,7 +84,7 @@ static void init_f16_vadd_config(void) { f16_vadd_config.element_tile = 16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512FP16 if ((hardware_config->arch_flags & xnn_arch_x86_avx512fp16)) { @@ -105,7 +105,7 @@ static void init_f16_vadd_config(void) { static void init_f16_vdiv_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vdiv_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vdiv_ukernel__fp16arith_u2; @@ -114,7 +114,7 @@ static void init_f16_vdiv_config(void) { f16_vdiv_config.element_tile = 2; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vdiv_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vdiv_ukernel__aarch64_neonfp16arith_u8; @@ -123,7 +123,7 @@ static void init_f16_vdiv_config(void) { f16_vdiv_config.element_tile = 8; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512FP16 if ((hardware_config->arch_flags & xnn_arch_x86_avx512fp16)) { @@ -144,7 +144,7 @@ static void init_f16_vdiv_config(void) { static void init_f16_vmax_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vmax_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vmax_ukernel__neonfp16arith_u16; @@ -153,7 +153,7 @@ static void init_f16_vmax_config(void) { f16_vmax_config.element_tile = 16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vmax_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vmax_ukernel__neonfp16arith_u16; @@ -162,7 +162,7 @@ static void init_f16_vmax_config(void) { f16_vmax_config.element_tile = 16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512FP16 if ((hardware_config->arch_flags & xnn_arch_x86_avx512fp16)) { @@ -183,7 +183,7 @@ static void init_f16_vmax_config(void) { static void init_f16_vmin_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vmin_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vmin_ukernel__neonfp16arith_u16; @@ -192,7 +192,7 @@ static void init_f16_vmin_config(void) { f16_vmin_config.element_tile = 16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vmin_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vmin_ukernel__neonfp16arith_u16; @@ -201,7 +201,7 @@ static void init_f16_vmin_config(void) { f16_vmin_config.element_tile = 16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512FP16 if ((hardware_config->arch_flags & xnn_arch_x86_avx512fp16)) { @@ -222,7 +222,7 @@ static void init_f16_vmin_config(void) { static void init_f16_vmul_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vmul_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vmul_ukernel__neonfp16arith_u16; @@ -231,7 +231,7 @@ static void init_f16_vmul_config(void) { f16_vmul_config.element_tile = 16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vmul_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vmul_ukernel__neonfp16arith_u16; @@ -240,7 +240,7 @@ static void init_f16_vmul_config(void) { f16_vmul_config.element_tile = 16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512FP16 if ((hardware_config->arch_flags & xnn_arch_x86_avx512fp16)) { @@ -261,7 +261,7 @@ static void init_f16_vmul_config(void) { static void init_f16_vprelu_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vprelu_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vprelu_ukernel__neonfp16arith_u16; @@ -270,7 +270,7 @@ static void init_f16_vprelu_config(void) { f16_vprelu_config.element_tile = 16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vprelu_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vprelu_ukernel__neonfp16arith_u16; @@ -279,7 +279,7 @@ static void init_f16_vprelu_config(void) { f16_vprelu_config.element_tile = 16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512FP16 if ((hardware_config->arch_flags & xnn_arch_x86_avx512fp16)) { @@ -300,7 +300,7 @@ static void init_f16_vprelu_config(void) { static void init_f16_vsub_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vsub_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vsub_ukernel__neonfp16arith_u16; @@ -309,7 +309,7 @@ static void init_f16_vsub_config(void) { f16_vsub_config.element_tile = 16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vsub_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vsub_ukernel__neonfp16arith_u16; @@ -318,7 +318,7 @@ static void init_f16_vsub_config(void) { f16_vsub_config.element_tile = 16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512FP16 if ((hardware_config->arch_flags & xnn_arch_x86_avx512fp16)) { @@ -339,7 +339,7 @@ static void init_f16_vsub_config(void) { static void init_f16_vsqrdiff_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vsqrdiff_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vsqrdiff_ukernel__neonfp16arith_u16; @@ -348,7 +348,7 @@ static void init_f16_vsqrdiff_config(void) { f16_vsqrdiff_config.element_tile = 16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vsqrdiff_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f16_vsqrdiff_ukernel__neonfp16arith_u16; @@ -357,7 +357,7 @@ static void init_f16_vsqrdiff_config(void) { f16_vsqrdiff_config.element_tile = 16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512FP16 if ((hardware_config->arch_flags & xnn_arch_x86_avx512fp16)) { @@ -378,7 +378,7 @@ static void init_f16_vsqrdiff_config(void) { static void init_f32_vadd_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ f32_vadd_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vadd_ukernel__neon_u8; @@ -397,7 +397,7 @@ static void init_f32_vadd_config(void) { f32_vadd_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vaddc_ukernel__neon_u8; f32_vadd_config.element_tile = 8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -424,7 +424,7 @@ static void init_f32_vadd_config(void) { f32_vadd_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vaddc_ukernel__wasmsimd_u16; f32_vadd_config.element_tile = 16; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_vadd_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vadd_ukernel__rvv_u8v; f32_vadd_config.opc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vaddc_ukernel__rvv_u8v; f32_vadd_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vaddc_ukernel__rvv_u8v; @@ -444,7 +444,7 @@ static void init_f32_vadd_config(void) { static void init_f32_vcopysign_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ f32_vcopysign_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vcopysign_ukernel__neon_u8; @@ -463,7 +463,7 @@ static void init_f32_vcopysign_config(void) { f32_vcopysign_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vrcopysignc_ukernel__neon_u8; f32_vcopysign_config.element_tile = 8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -506,7 +506,7 @@ static void init_f32_vcopysign_config(void) { static void init_f32_vdiv_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ f32_vdiv_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vdiv_ukernel__scalar_u2; @@ -525,7 +525,7 @@ static void init_f32_vdiv_config(void) { f32_vdiv_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vrdivc_ukernel__aarch64_neon_u8; f32_vdiv_config.element_tile = 8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -552,7 +552,7 @@ static void init_f32_vdiv_config(void) { f32_vdiv_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vrdivc_ukernel__wasmsimd_u16; f32_vdiv_config.element_tile = 16; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_vdiv_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vdiv_ukernel__rvv_u8v; f32_vdiv_config.opc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vdivc_ukernel__rvv_u8v; f32_vdiv_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vrdivc_ukernel__rvv_u8v; @@ -567,7 +567,7 @@ static void init_f32_vdiv_config(void) { static void init_f32_vmax_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ f32_vmax_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmax_ukernel__neon_u8; @@ -586,7 +586,7 @@ static void init_f32_vmax_config(void) { f32_vmax_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmaxc_ukernel__neon_u8; f32_vmax_config.element_tile = 8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -608,7 +608,7 @@ static void init_f32_vmax_config(void) { f32_vmax_config.element_tile = 8; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->is_x86) { f32_vmax_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmax_ukernel__wasmsimd_x86_u16; @@ -622,7 +622,7 @@ static void init_f32_vmax_config(void) { f32_vmax_config.element_tile = 16; } #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_vmax_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmax_ukernel__rvv_u8v; f32_vmax_config.opc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmaxc_ukernel__rvv_u8v; f32_vmax_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmaxc_ukernel__rvv_u8v; @@ -642,7 +642,7 @@ static void init_f32_vmax_config(void) { static void init_f32_vmin_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ f32_vmin_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmin_ukernel__neon_u8; @@ -661,7 +661,7 @@ static void init_f32_vmin_config(void) { f32_vmin_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vminc_ukernel__neon_u8; f32_vmin_config.element_tile = 8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -683,7 +683,7 @@ static void init_f32_vmin_config(void) { f32_vmin_config.element_tile = 8; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->is_x86) { f32_vmin_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmin_ukernel__wasmsimd_x86_u16; @@ -697,7 +697,7 @@ static void init_f32_vmin_config(void) { f32_vmin_config.element_tile = 16; } #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_vmin_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmin_ukernel__rvv_u8v; f32_vmin_config.opc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vminc_ukernel__rvv_u8v; f32_vmin_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vminc_ukernel__rvv_u8v; @@ -717,7 +717,7 @@ static void init_f32_vmin_config(void) { static void init_f32_vmul_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ f32_vmul_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmul_ukernel__neon_u8; @@ -736,7 +736,7 @@ static void init_f32_vmul_config(void) { f32_vmul_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmulc_ukernel__neon_u8; f32_vmul_config.element_tile = 8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -763,7 +763,7 @@ static void init_f32_vmul_config(void) { f32_vmul_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmulc_ukernel__wasmsimd_u16; f32_vmul_config.element_tile = 16; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_vmul_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmul_ukernel__rvv_u8v; f32_vmul_config.opc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmulc_ukernel__rvv_u8v; f32_vmul_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vmulc_ukernel__rvv_u8v; @@ -783,7 +783,7 @@ static void init_f32_vmul_config(void) { static void init_f32_vprelu_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ f32_vprelu_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vprelu_ukernel__neon_u8; @@ -802,7 +802,7 @@ static void init_f32_vprelu_config(void) { f32_vprelu_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vrpreluc_ukernel__neon_u8; f32_vprelu_config.element_tile = 8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -838,7 +838,7 @@ static void init_f32_vprelu_config(void) { static void init_f32_vsub_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ f32_vsub_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vsub_ukernel__neon_u8; @@ -857,7 +857,7 @@ static void init_f32_vsub_config(void) { f32_vsub_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vrsubc_ukernel__neon_u8; f32_vsub_config.element_tile = 8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -884,7 +884,7 @@ static void init_f32_vsub_config(void) { f32_vsub_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vrsubc_ukernel__wasmsimd_u16; f32_vsub_config.element_tile = 16; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_vsub_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vsub_ukernel__rvv_u8v; f32_vsub_config.opc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vsubc_ukernel__rvv_u8v; f32_vsub_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vrsubc_ukernel__rvv_u8v; @@ -904,7 +904,7 @@ static void init_f32_vsub_config(void) { static void init_f32_vsqrdiff_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ f32_vsqrdiff_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vsqrdiff_ukernel__neon_u8; @@ -923,7 +923,7 @@ static void init_f32_vsqrdiff_config(void) { f32_vsqrdiff_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vsqrdiffc_ukernel__neon_u8; f32_vsqrdiff_config.element_tile = 8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -950,7 +950,7 @@ static void init_f32_vsqrdiff_config(void) { f32_vsqrdiff_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vsqrdiffc_ukernel__wasmsimd_u16; f32_vsqrdiff_config.element_tile = 16; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_vsqrdiff_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vsqrdiff_ukernel__rvv_u8v; f32_vsqrdiff_config.opc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vsqrdiffc_ukernel__rvv_u8v; f32_vsqrdiff_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vsqrdiffc_ukernel__rvv_u8v; @@ -970,7 +970,7 @@ static void init_f32_vsqrdiff_config(void) { static void init_qs8_vadd_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ qs8_vadd_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_qs8_vadd_minmax_ukernel__neon_ld64_u16; @@ -992,7 +992,7 @@ static void init_qs8_vadd_config(void) { qs8_vadd_config.init = (xnn_init_binary_params_fn) xnn_init_qs8_add_minmax_scalar_params; qs8_vadd_config.element_tile = 32; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -1035,7 +1035,7 @@ static void init_qs8_vadd_config(void) { qs8_vadd_config.init = (xnn_init_binary_params_fn) xnn_init_qs8_add_minmax_scalar_params; qs8_vadd_config.element_tile = 32; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qs8_vadd_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_qs8_vadd_minmax_ukernel__rvv_u2v; qs8_vadd_config.opc_ukernel = (xnn_vbinary_ukernel_fn) xnn_qs8_vaddc_minmax_ukernel__rvv_u2v; qs8_vadd_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_qs8_vaddc_minmax_ukernel__rvv_u2v; @@ -1058,7 +1058,7 @@ static void init_qs8_vadd_config(void) { static void init_qs8_vmul_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ qs8_vmul_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_qs8_vmul_minmax_rndnu_ukernel__neon_ld64_u16; @@ -1080,7 +1080,7 @@ static void init_qs8_vmul_config(void) { qs8_vmul_config.init = (xnn_init_binary_params_fn) xnn_init_qs8_mul_minmax_rndnu_neon_params; qs8_vmul_config.element_tile = 16; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx)) { qs8_vmul_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_qs8_vmul_minmax_fp32_ukernel__avx_mul16_ld64_u16; @@ -1108,7 +1108,7 @@ static void init_qs8_vmul_config(void) { qs8_vmul_config.init = (xnn_init_binary_params_fn) xnn_init_qs8_mul_minmax_scalar_params; qs8_vmul_config.element_tile = 8; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qs8_vmul_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_qs8_vmul_minmax_fp32_ukernel__rvv_u2v; qs8_vmul_config.opc_ukernel = (xnn_vbinary_ukernel_fn) xnn_qs8_vmulc_minmax_fp32_ukernel__rvv_u2v; qs8_vmul_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_qs8_vmulc_minmax_fp32_ukernel__rvv_u2v; @@ -1125,7 +1125,7 @@ static void init_qs8_vmul_config(void) { static void init_qs8_vprelu_config(void) { #if XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { qs8_vprelu_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_qs8_vprelu_ukernel__avx2_u16; @@ -1151,7 +1151,7 @@ static void init_qs8_vprelu_config(void) { static void init_qu8_vadd_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ qu8_vadd_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_qu8_vadd_minmax_ukernel__neon_ld64_u16; @@ -1173,7 +1173,7 @@ static void init_qu8_vadd_config(void) { qu8_vadd_config.init = (xnn_init_binary_params_fn) xnn_init_qu8_add_minmax_scalar_params; qu8_vadd_config.element_tile = 8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -1216,7 +1216,7 @@ static void init_qu8_vadd_config(void) { qu8_vadd_config.init = (xnn_init_binary_params_fn) xnn_init_qu8_add_minmax_scalar_params; qu8_vadd_config.element_tile = 32; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qu8_vadd_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_qu8_vadd_minmax_ukernel__rvv_u2v; qu8_vadd_config.opc_ukernel = (xnn_vbinary_ukernel_fn) xnn_qu8_vaddc_minmax_ukernel__rvv_u2v; qu8_vadd_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_qu8_vaddc_minmax_ukernel__rvv_u2v; @@ -1233,7 +1233,7 @@ static void init_qu8_vadd_config(void) { static void init_qu8_vmul_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)){ qu8_vmul_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_qu8_vmul_minmax_rndnu_ukernel__neon_ld64_u16; @@ -1255,7 +1255,7 @@ static void init_qu8_vmul_config(void) { qu8_vmul_config.init = (xnn_init_binary_params_fn) xnn_init_qu8_mul_minmax_rndnu_neon_params; qu8_vmul_config.element_tile = 16; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx)) { qu8_vmul_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_qu8_vmul_minmax_fp32_ukernel__avx_mul16_ld64_u16; @@ -1283,7 +1283,7 @@ static void init_qu8_vmul_config(void) { qu8_vmul_config.init = (xnn_init_binary_params_fn) xnn_init_qu8_mul_minmax_scalar_params; qu8_vmul_config.element_tile = 8; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qu8_vmul_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_qu8_vmul_minmax_fp32_ukernel__rvv_u2v; qu8_vmul_config.opc_ukernel = (xnn_vbinary_ukernel_fn) xnn_qu8_vmulc_minmax_fp32_ukernel__rvv_u2v; qu8_vmul_config.ropc_ukernel = (xnn_vbinary_ukernel_fn) xnn_qu8_vmulc_minmax_fp32_ukernel__rvv_u2v; @@ -1300,7 +1300,7 @@ static void init_qu8_vmul_config(void) { static void init_qu8_vprelu_config(void) { #if XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { qu8_vprelu_config.op_ukernel = (xnn_vbinary_ukernel_fn) xnn_qu8_vprelu_ukernel__avx2_u16; @@ -1324,8 +1324,8 @@ static void init_qu8_vprelu_config(void) { #endif } -const struct xnn_binary_elementwise_config* xnn_init_f16_vadd_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f16_vadd_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -1333,8 +1333,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f16_vadd_config() { return &f16_vadd_config; } -const struct xnn_binary_elementwise_config* xnn_init_f16_vdiv_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f16_vdiv_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -1342,8 +1342,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f16_vdiv_config() { return &f16_vdiv_config; } -const struct xnn_binary_elementwise_config* xnn_init_f16_vmax_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f16_vmax_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -1351,8 +1351,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f16_vmax_config() { return &f16_vmax_config; } -const struct xnn_binary_elementwise_config* xnn_init_f16_vmin_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f16_vmin_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -1360,8 +1360,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f16_vmin_config() { return &f16_vmin_config; } -const struct xnn_binary_elementwise_config* xnn_init_f16_vmul_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f16_vmul_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -1369,8 +1369,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f16_vmul_config() { return &f16_vmul_config; } -const struct xnn_binary_elementwise_config* xnn_init_f16_vprelu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f16_vprelu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -1378,8 +1378,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f16_vprelu_config() { return &f16_vprelu_config; } -const struct xnn_binary_elementwise_config* xnn_init_f16_vsub_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f16_vsub_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -1387,8 +1387,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f16_vsub_config() { return &f16_vsub_config; } -const struct xnn_binary_elementwise_config* xnn_init_f16_vsqrdiff_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f16_vsqrdiff_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -1396,8 +1396,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f16_vsqrdiff_config() { return &f16_vsqrdiff_config; } -const struct xnn_binary_elementwise_config* xnn_init_f32_vadd_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f32_vadd_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1405,8 +1405,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f32_vadd_config() { return &f32_vadd_config; } -const struct xnn_binary_elementwise_config* xnn_init_f32_vcopysign_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f32_vcopysign_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1414,8 +1414,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f32_vcopysign_config() { return &f32_vcopysign_config; } -const struct xnn_binary_elementwise_config* xnn_init_f32_vdiv_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f32_vdiv_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1423,8 +1423,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f32_vdiv_config() { return &f32_vdiv_config; } -const struct xnn_binary_elementwise_config* xnn_init_f32_vmax_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f32_vmax_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1432,8 +1432,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f32_vmax_config() { return &f32_vmax_config; } -const struct xnn_binary_elementwise_config* xnn_init_f32_vmin_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f32_vmin_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1441,8 +1441,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f32_vmin_config() { return &f32_vmin_config; } -const struct xnn_binary_elementwise_config* xnn_init_f32_vmul_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f32_vmul_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1450,8 +1450,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f32_vmul_config() { return &f32_vmul_config; } -const struct xnn_binary_elementwise_config* xnn_init_f32_vprelu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f32_vprelu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1459,8 +1459,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f32_vprelu_config() { return &f32_vprelu_config; } -const struct xnn_binary_elementwise_config* xnn_init_f32_vsub_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f32_vsub_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1468,8 +1468,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f32_vsub_config() { return &f32_vsub_config; } -const struct xnn_binary_elementwise_config* xnn_init_f32_vsqrdiff_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_f32_vsqrdiff_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1477,8 +1477,8 @@ const struct xnn_binary_elementwise_config* xnn_init_f32_vsqrdiff_config() { return &f32_vsqrdiff_config; } -const struct xnn_binary_elementwise_config* xnn_init_qs8_vadd_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_qs8_vadd_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1486,8 +1486,8 @@ const struct xnn_binary_elementwise_config* xnn_init_qs8_vadd_config() { return &qs8_vadd_config; } -const struct xnn_binary_elementwise_config* xnn_init_qs8_vmul_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_qs8_vmul_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1495,8 +1495,8 @@ const struct xnn_binary_elementwise_config* xnn_init_qs8_vmul_config() { return &qs8_vmul_config; } -const struct xnn_binary_elementwise_config* xnn_init_qs8_vprelu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_qs8_vprelu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1504,8 +1504,8 @@ const struct xnn_binary_elementwise_config* xnn_init_qs8_vprelu_config() { return &qs8_vprelu_config; } -const struct xnn_binary_elementwise_config* xnn_init_qu8_vadd_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_qu8_vadd_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1513,8 +1513,8 @@ const struct xnn_binary_elementwise_config* xnn_init_qu8_vadd_config() { return &qu8_vadd_config; } -const struct xnn_binary_elementwise_config* xnn_init_qu8_vmul_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_qu8_vmul_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -1522,8 +1522,8 @@ const struct xnn_binary_elementwise_config* xnn_init_qu8_vmul_config() { return &qu8_vmul_config; } -const struct xnn_binary_elementwise_config* xnn_init_qu8_vprelu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_binary_elementwise_config* xnn_get_qu8_vprelu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/cmul-config.c b/src/configs/cmul-config.c index a9b68e5846b..f3896685930 100644 --- a/src/configs/cmul-config.c +++ b/src/configs/cmul-config.c @@ -32,7 +32,7 @@ XNN_INIT_ONCE_GUARD(f32_cmul); static void init_f32_cmul_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_cmul_config.ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vcmul_ukernel__neon_u8; @@ -42,7 +42,7 @@ static void init_f32_cmul_config(void) { #elif XNN_ARCH_ARM64 f32_cmul_config.ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vcmul_ukernel__neon_u8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -57,16 +57,16 @@ static void init_f32_cmul_config(void) { #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD f32_cmul_config.ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vcmul_ukernel__wasmsimd_u8; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_cmul_config.ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vcmul_ukernel__rvv_u2v; #else f32_cmul_config.ukernel = (xnn_vbinary_ukernel_fn) xnn_f32_vcmul_ukernel__scalar_u4; #endif } -const struct xnn_cmul_config* xnn_init_f16_cmul_config() { +const struct xnn_cmul_config* xnn_get_f16_cmul_config() { #if (XNN_ARCH_ARM || XNN_ARCH_ARM64) && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -77,8 +77,8 @@ const struct xnn_cmul_config* xnn_init_f16_cmul_config() { #endif } -const struct xnn_cmul_config* xnn_init_f32_cmul_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_cmul_config* xnn_get_f32_cmul_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/conv-hwc2chw-config.c b/src/configs/conv-hwc2chw-config.c index c9ad58e77ba..f621409362e 100644 --- a/src/configs/conv-hwc2chw-config.c +++ b/src/configs/conv-hwc2chw-config.c @@ -21,7 +21,7 @@ XNN_INIT_ONCE_GUARD(f32_conv_hwc2chw_3x3c3s2); static void init_f16_conv_hwc2chw_3x3c3s2_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_conv_hwc2chw_3x3c3s2_config.ukernel_with_symm_padding = @@ -31,7 +31,7 @@ static void init_f16_conv_hwc2chw_3x3c3s2_config(void) { f16_conv_hwc2chw_3x3c3s2_config.output_height_tile = 2; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_conv_hwc2chw_3x3c3s2_config.ukernel_with_symm_padding = @@ -45,7 +45,7 @@ static void init_f16_conv_hwc2chw_3x3c3s2_config(void) { static void init_f32_conv_hwc2chw_3x3c3s2_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_conv_hwc2chw_3x3c3s2_config.ukernel_with_symm_padding = @@ -79,7 +79,7 @@ static void init_f32_conv_hwc2chw_3x3c3s2_config(void) { f32_conv_hwc2chw_3x3c3s2_config.output_channel_tile = 4; f32_conv_hwc2chw_3x3c3s2_config.output_height_tile = 2; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_conv_hwc2chw_3x3c3s2_config.ukernel_with_symm_padding = (xnn_conv_hwc2chw_ukernel_fn) xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x2; f32_conv_hwc2chw_3x3c3s2_config.init.f32 = xnn_init_f32_minmax_scalar_params; @@ -94,8 +94,8 @@ static void init_f32_conv_hwc2chw_3x3c3s2_config(void) { #endif } -const struct xnn_conv_hwc2chw_config* xnn_init_f16_conv_hwc2chw_3x3c3s2_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_conv_hwc2chw_config* xnn_get_f16_conv_hwc2chw_3x3c3s2_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_chw_compatible_config(hardware_config)) { return NULL; } @@ -103,8 +103,8 @@ const struct xnn_conv_hwc2chw_config* xnn_init_f16_conv_hwc2chw_3x3c3s2_config() return &f16_conv_hwc2chw_3x3c3s2_config; } -const struct xnn_conv_hwc2chw_config* xnn_init_f32_conv_hwc2chw_3x3c3s2_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_conv_hwc2chw_config* xnn_get_f32_conv_hwc2chw_3x3c3s2_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_chw_compatible_config(hardware_config)) { return NULL; } diff --git a/src/configs/dwconv-config.c b/src/configs/dwconv-config.c index 42b6d0d0d50..36f5bab531c 100644 --- a/src/configs/dwconv-config.c +++ b/src/configs/dwconv-config.c @@ -31,7 +31,7 @@ XNN_INIT_ONCE_GUARD(qu8_dwconv); static void init_f16_dwconv_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_dwconv_config[0].minmax = (xnn_dwconv_ukernel_fn) xnn_f16_dwconv_minmax_ukernel_3p16c__neonfp16arith; @@ -55,7 +55,7 @@ static void init_f16_dwconv_config(void) { f16_dwconv_config[3].primary_tile = 25; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_dwconv_config[0].minmax = (xnn_dwconv_ukernel_fn) xnn_f16_dwconv_minmax_ukernel_3p16c__neonfp16arith; @@ -79,7 +79,7 @@ static void init_f16_dwconv_config(void) { f16_dwconv_config[3].primary_tile = 25; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { f16_dwconv_config[0].minmax = (xnn_dwconv_ukernel_fn) xnn_f16_dwconv_minmax_ukernel_3p16c__fma3; @@ -107,7 +107,7 @@ static void init_f16_dwconv_config(void) { static void init_f32_dwconv_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_dwconv_config[0].minmax = (xnn_dwconv_ukernel_fn) xnn_f32_dwconv_minmax_ukernel_3p8c__neon; @@ -202,7 +202,7 @@ static void init_f32_dwconv_config(void) { f32_dwconv_config[3].channel_tile = 8; f32_dwconv_config[3].primary_tile = 25; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -308,7 +308,7 @@ static void init_f32_dwconv_config(void) { f32_dwconv_config[2].channel_tile = 8; f32_dwconv_config[2].primary_tile = 9; #else - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->is_x86) { f32_dwconv_config[0].minmax = (xnn_dwconv_ukernel_fn) xnn_f32_dwconv_minmax_ukernel_3p8c__wasmsimd_x86; @@ -365,7 +365,7 @@ static void init_f32_dwconv_config(void) { #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR size_t lmul = 8; const int element_size = 4; // size of float - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_dwconv_config[0].minmax = (xnn_dwconv_ukernel_fn) xnn_f32_dwconv_minmax_ukernel_3p8vc__rvv; f32_dwconv_config[0].linear = (xnn_dwconv_ukernel_fn) xnn_f32_dwconv_ukernel_3p8vc__rvv; @@ -439,7 +439,7 @@ static void init_f32_dwconv_config(void) { static void init_qs8_qc8w_dwconv_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { if ((hardware_config->arch_flags & xnn_arch_arm_neon_v8)) { @@ -497,7 +497,7 @@ static void init_qs8_qc8w_dwconv_config(void) { qs8_qc8w_dwconv_config[2].channel_tile = 16; qs8_qc8w_dwconv_config[2].primary_tile = 25; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -570,7 +570,7 @@ static void init_qs8_qc8w_dwconv_config(void) { qs8_qc8w_dwconv_config[2].channel_tile = 16; qs8_qc8w_dwconv_config[2].primary_tile = 25; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qs8_qc8w_dwconv_config[0].minmax = (xnn_dwconv_ukernel_fn) xnn_qs8_qc8w_dwconv_minmax_fp32_ukernel_3p8vc__rvv; qs8_qc8w_dwconv_config[0].init.qs8_qc8w = xnn_init_qs8_qc8w_conv_minmax_fp32_scalar_params; qs8_qc8w_dwconv_config[0].channel_tile = 8 * hardware_config->vlenb / sizeof(int32_t); @@ -601,7 +601,7 @@ static void init_qs8_qc8w_dwconv_config(void) { static void init_qs8_dwconv_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { qs8_dwconv_config[0].minmax = (xnn_dwconv_ukernel_fn) xnn_qs8_dwconv_minmax_rndnu_ukernel_9p16c__neon_mla8_ld64; @@ -632,7 +632,7 @@ static void init_qs8_dwconv_config(void) { qs8_dwconv_config[1].channel_tile = 16; qs8_dwconv_config[1].primary_tile = 25; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -685,7 +685,7 @@ static void init_qs8_dwconv_config(void) { qs8_dwconv_config[1].channel_tile = 16; qs8_dwconv_config[1].primary_tile = 25; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qs8_dwconv_config[0].minmax = (xnn_dwconv_ukernel_fn) xnn_qs8_dwconv_minmax_fp32_ukernel_9p8vc__rvv; qs8_dwconv_config[0].init.qs8_qc8w = xnn_init_qs8_qc8w_conv_minmax_fp32_scalar_params; qs8_dwconv_config[0].channel_tile = 8 * hardware_config->vlenb / sizeof(int32_t); @@ -708,7 +708,7 @@ static void init_qs8_dwconv_config(void) { static void init_qu8_dwconv_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { qu8_dwconv_config[0].minmax = (xnn_dwconv_ukernel_fn) xnn_qu8_dwconv_minmax_rndnu_ukernel_9p16c__neon_mul8; @@ -739,7 +739,7 @@ static void init_qu8_dwconv_config(void) { qu8_dwconv_config[1].channel_tile = 8; qu8_dwconv_config[1].primary_tile = 25; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -792,7 +792,7 @@ static void init_qu8_dwconv_config(void) { qu8_dwconv_config[1].channel_tile = 8; qu8_dwconv_config[1].primary_tile = 25; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qs8_dwconv_config[0].minmax = (xnn_dwconv_ukernel_fn) xnn_qu8_dwconv_minmax_fp32_ukernel_9p8vc__rvv; qs8_dwconv_config[0].init.qu8 = xnn_init_qu8_conv_minmax_fp32_scalar_params; qs8_dwconv_config[0].channel_tile = 8 * hardware_config->vlenb / sizeof(int32_t); @@ -813,8 +813,8 @@ static void init_qu8_dwconv_config(void) { #endif } -const struct xnn_dwconv_config* xnn_init_f16_dwconv_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_dwconv_config* xnn_get_f16_dwconv_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -822,8 +822,8 @@ const struct xnn_dwconv_config* xnn_init_f16_dwconv_config() { return f16_dwconv_config; } -const struct xnn_dwconv_config* xnn_init_f32_dwconv_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_dwconv_config* xnn_get_f32_dwconv_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -831,8 +831,8 @@ const struct xnn_dwconv_config* xnn_init_f32_dwconv_config() { return f32_dwconv_config; } -const struct xnn_dwconv_config* xnn_init_qs8_qc8w_dwconv_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_dwconv_config* xnn_get_qs8_qc8w_dwconv_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -840,8 +840,8 @@ const struct xnn_dwconv_config* xnn_init_qs8_qc8w_dwconv_config() { return qs8_qc8w_dwconv_config; } -const struct xnn_dwconv_config* xnn_init_qs8_dwconv_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_dwconv_config* xnn_get_qs8_dwconv_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -849,8 +849,8 @@ const struct xnn_dwconv_config* xnn_init_qs8_dwconv_config() { return qs8_dwconv_config; } -const struct xnn_dwconv_config* xnn_init_qu8_dwconv_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_dwconv_config* xnn_get_qu8_dwconv_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/dwconv2d-chw-config.c b/src/configs/dwconv2d-chw-config.c index dc6ffca7776..0116d6e3810 100644 --- a/src/configs/dwconv2d-chw-config.c +++ b/src/configs/dwconv2d-chw-config.c @@ -21,7 +21,7 @@ XNN_INIT_ONCE_GUARD(f32_dwconv2d_chw); static void init_f16_dwconv2d_chw_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_dwconv2d_chw_config.dwconv2d_chw_3x3.ukernel = (xnn_dwconv2d_chw_ukernel_fn) xnn_f16_dwconv2d_chw_ukernel_3x3p1__neonfp16arith_2x8; @@ -41,7 +41,7 @@ static void init_f16_dwconv2d_chw_config(void) { f16_dwconv2d_chw_config.dwconv2d_chw_5x5s2.output_width_tile = 8; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_dwconv2d_chw_config.dwconv2d_chw_3x3.ukernel = (xnn_dwconv2d_chw_ukernel_fn) xnn_f16_dwconv2d_chw_ukernel_3x3p1__neonfp16arith_2x8; @@ -65,7 +65,7 @@ static void init_f16_dwconv2d_chw_config(void) { static void init_f32_dwconv2d_chw_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_dwconv2d_chw_config.dwconv2d_chw_3x3.ukernel = (xnn_dwconv2d_chw_ukernel_fn) xnn_f32_dwconv2d_chw_ukernel_3x3p1__neon_2x4; @@ -117,7 +117,7 @@ static void init_f32_dwconv2d_chw_config(void) { f32_dwconv2d_chw_config.dwconv2d_chw_5x5s2.init.f32 = xnn_init_f32_minmax_scalar_params; f32_dwconv2d_chw_config.dwconv2d_chw_5x5s2.output_width_tile = 4; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_ssse3)) { f32_dwconv2d_chw_config.dwconv2d_chw_3x3.ukernel = (xnn_dwconv2d_chw_ukernel_fn) xnn_f32_dwconv2d_chw_ukernel_3x3p1__ssse3_2x4_acc2; @@ -141,7 +141,7 @@ static void init_f32_dwconv2d_chw_config(void) { f32_dwconv2d_chw_config.dwconv2d_chw_5x5s2.init.f32 = xnn_init_f32_minmax_scalar_params; f32_dwconv2d_chw_config.dwconv2d_chw_5x5s2.output_width_tile = 4; #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->is_x86) { f32_dwconv2d_chw_config.dwconv2d_chw_3x3.ukernel = (xnn_dwconv2d_chw_ukernel_fn) xnn_f32_dwconv2d_chw_ukernel_3x3p1__wasmsimd_x86_loadsplat_2x4; @@ -177,7 +177,7 @@ static void init_f32_dwconv2d_chw_config(void) { f32_dwconv2d_chw_config.dwconv2d_chw_5x5s2.output_width_tile = 4; } #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_dwconv2d_chw_config.dwconv2d_chw_3x3.ukernel = (xnn_dwconv2d_chw_ukernel_fn) xnn_f32_dwconv2d_chw_ukernel_3x3p1__rvv_7x1v; f32_dwconv2d_chw_config.dwconv2d_chw_3x3.init.f32 = xnn_init_f32_minmax_scalar_params; f32_dwconv2d_chw_config.dwconv2d_chw_3x3.output_width_tile = 1 * hardware_config->vlenb / sizeof(float); @@ -212,8 +212,8 @@ static void init_f32_dwconv2d_chw_config(void) { #endif } -const struct xnn_dwconv2d_chw_config* xnn_init_f16_dwconv2d_chw_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_dwconv2d_chw_config* xnn_get_f16_dwconv2d_chw_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_chw_compatible_config(hardware_config)) { return NULL; } @@ -221,8 +221,8 @@ const struct xnn_dwconv2d_chw_config* xnn_init_f16_dwconv2d_chw_config() { return &f16_dwconv2d_chw_config; } -const struct xnn_dwconv2d_chw_config* xnn_init_f32_dwconv2d_chw_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_dwconv2d_chw_config* xnn_get_f32_dwconv2d_chw_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_chw_compatible_config(hardware_config)) { return NULL; } diff --git a/src/configs/gemm-config.c b/src/configs/gemm-config.c index de54287664e..99b4b984980 100644 --- a/src/configs/gemm-config.c +++ b/src/configs/gemm-config.c @@ -93,7 +93,7 @@ XNN_INIT_ONCE_GUARD(qu8_gemm); static void init_f16_gemm_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { @@ -108,7 +108,7 @@ static void init_f16_gemm_config(void) { f16_gemm_config.nr = 8; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { @@ -232,7 +232,7 @@ static void init_f16_gemm_config(void) { #endif // XNN_ENABLE_ASSEMBLY } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { @@ -268,7 +268,7 @@ static void init_f16_gemm_config(void) { static void init_pf16_gemm_config(void) { #if XNN_ARCH_ARM64 && XNN_ENABLE_KLEIDIAI const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); assert(hardware_config != NULL); if (XNN_ENABLE_ARM_SME2 && (hardware_config->arch_flags & xnn_arch_arm_sme2)) { #if XNN_ENABLE_ARM_SME2 @@ -291,7 +291,7 @@ static void init_pf16_gemm_config(void) { static void init_bf16_f32_gemm_config(void) { #if XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if (XNN_ENABLE_AVX512BF16 && (hardware_config->arch_flags & xnn_arch_x86_avx512bf16)) { @@ -312,7 +312,7 @@ static void init_bf16_f32_gemm_config(void) { static void init_pf32_gemm_config(void) { #if XNN_ARCH_ARM64 && XNN_ENABLE_KLEIDIAI - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if (XNN_ENABLE_ARM_SME2 && (hardware_config->arch_flags & xnn_arch_arm_sme2)) { @@ -339,7 +339,7 @@ static void init_pf32_gemm_config(void) { static void init_pqs8_qc8w_gemm_config(void) { #if XNN_ARCH_ARM64 && XNN_ENABLE_KLEIDIAI const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); assert(hardware_config != NULL); (void)hardware_config; // May be unused. if (XNN_ENABLE_ARM_SME2 && (hardware_config->arch_flags & xnn_arch_arm_sme2)) { @@ -375,7 +375,7 @@ static void init_pqs8_qc8w_gemm_config(void) { static void init_f32_gemm_config_impl(struct xnn_gemm_config* f32_gemm_config, bool consistent_arithmetic) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -704,7 +704,7 @@ static void init_f32_gemm_config_impl(struct xnn_gemm_config* f32_gemm_config, b #endif // XNN_ENABLE_ASSEMBLY #endif // XNN_ENABLE_ASSEMBLY && !XNN_PLATFORM_IOS && !XNN_PLATFORM_MAC #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512F && XNN_ARCH_X86_64 && !XNN_PLATFORM_WINDOWS @@ -772,7 +772,7 @@ static void init_f32_gemm_config_impl(struct xnn_gemm_config* f32_gemm_config, b f32_gemm_config->nr = 8; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if (hardware_config->is_x86) { @@ -834,7 +834,7 @@ static void init_f32_gemm_config_impl(struct xnn_gemm_config* f32_gemm_config, b #endif } #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_riscv_vector)) { @@ -878,7 +878,7 @@ static void init_f32_gemm_config() { static void init_f32_igemm_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -1207,7 +1207,7 @@ static void init_f32_igemm_config(void) { #endif // XNN_ENABLE_ASSEMBLY #endif // XNN_ENABLE_ASSEMBLY && !XNN_PLATFORM_IOS && !XNN_PLATFORM_MAC #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512F @@ -1262,7 +1262,7 @@ static void init_f32_igemm_config(void) { f32_igemm_config.nr = 8; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if (hardware_config->is_x86) { @@ -1324,7 +1324,7 @@ static void init_f32_igemm_config(void) { #endif } #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_riscv_vector)) { @@ -1363,7 +1363,7 @@ static void init_f32_igemm_config(void) { static void init_f32_gemm_nr2_config_impl(struct xnn_gemm_config* f32_gemm_nr2_config, bool consistent_arithmetic) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -1414,7 +1414,7 @@ static void init_f32_gemm_nr2_config_impl(struct xnn_gemm_config* f32_gemm_nr2_c #endif // XNN_ENABLE_ASSEMBLY #endif // XNN_ENABLE_ASSEMBLY && !XNN_PLATFORM_IOS && !XNN_PLATFORM_MAC #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512F && XNN_ARCH_X86_64 && !XNN_PLATFORM_WINDOWS @@ -1492,7 +1492,7 @@ static void init_f32_gemm_nr2_config_impl(struct xnn_gemm_config* f32_gemm_nr2_c f32_gemm_nr2_config->log2_kr = 2; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if (hardware_config->is_x86) { @@ -1565,7 +1565,7 @@ static void init_f32_gemm_nr2_config() { static void init_f32_qc4w_gemm_config(void) { f32_qc4w_gemm_config.planes = 1; #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -1592,7 +1592,7 @@ static void init_f32_qc4w_gemm_config(void) { f32_qc4w_gemm_config.mr = 6; f32_qc4w_gemm_config.nr = 8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512SKX @@ -1647,7 +1647,7 @@ static void init_f32_qc4w_gemm_config(void) { static void init_f32_qc8w_gemm_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -1744,7 +1744,7 @@ static void init_f32_qc8w_gemm_config(void) { #endif // XNN_ENABLE_ASSEMBLY #endif // XNN_ENABLE_ASSEMBLY && !XNN_PLATFORM_IOS && !XNN_PLATFORM_MAC #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512SKX @@ -1792,7 +1792,7 @@ static void init_f32_qc8w_gemm_config(void) { f32_qc8w_gemm_config.nr = 8; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if (hardware_config->is_x86) { @@ -1866,7 +1866,7 @@ static void init_qdu8_f16_qc4w_gemm_config(void) { qdu8_f16_qc4w_gemm_config.pack_gemm_gio = (xnn_packw_gemm_gio_ukernel_fn) xnn_pack_qs8_qc4w_gemm_gio_w; qdu8_f16_qc4w_gemm_config.pack_gemm_goi = (xnn_packw_gemm_goi_ukernel_fn) xnn_pack_qs8_qc4w_gemm_goi_w; #if XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX256VNNI @@ -1938,7 +1938,7 @@ static void init_qd8_f16_qc4w_gemm_config(void) { qd8_f16_qc4w_gemm_config.pack_gemm_gio = (xnn_packw_gemm_gio_ukernel_fn) xnn_pack_qs8_qc4w_gemm_gio_w; qd8_f16_qc4w_gemm_config.pack_gemm_goi = (xnn_packw_gemm_goi_ukernel_fn) xnn_pack_qs8_qc4w_gemm_goi_w; #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -1962,7 +1962,7 @@ static void init_qd8_f16_qc4w_gemm_config(void) { } } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if (XNN_ENABLE_ARM_I8MM && (hardware_config->arch_flags & xnn_arch_arm_neon_i8mm)) { @@ -2003,7 +2003,7 @@ static void init_qd8_f16_qb4w_gemm_config(void) { qd8_f16_qb4w_gemm_config.pack_weights_and_biases = xnn_pack_qb4_weights_and_biases; #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -2027,7 +2027,7 @@ static void init_qd8_f16_qb4w_gemm_config(void) { } } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if (XNN_ENABLE_ARM_I8MM && (hardware_config->arch_flags & xnn_arch_arm_neon_i8mm)) { @@ -2059,7 +2059,7 @@ static void init_qd8_f16_qb4w_gemm_config(void) { qd8_f16_qb4w_gemm_config.planes = 2; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { @@ -2083,7 +2083,7 @@ static void init_qd8_f32_qc4w_gemm_config(void) { qd8_f32_qc4w_gemm_config.pack_gemm_gio = (xnn_packw_gemm_gio_ukernel_fn) xnn_pack_qs8_qc4w_gemm_gio_w; // Ignored qd8_f32_qc4w_gemm_config.pack_gemm_goi = (xnn_packw_gemm_goi_ukernel_fn) xnn_pack_qs8_qc4w_gemm_goi_w; // Ignored #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -2114,7 +2114,7 @@ static void init_qd8_f32_qc4w_gemm_config(void) { qd8_f32_qc4w_gemm_config.planes = 2; } #elif XNN_ARCH_ARM64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if (XNN_ENABLE_ARM_I8MM && (hardware_config->arch_flags & xnn_arch_arm_neon_i8mm)) { @@ -2147,7 +2147,7 @@ static void init_qd8_f32_qc4w_gemm_config(void) { } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 #if XNN_ENABLE_AVX512AMX - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_x86_avx512amx)) { @@ -2179,7 +2179,7 @@ static void init_qd8_f32_qc4w_gemm_config(void) { qd8_f32_qc4w_gemm_config.log2_kr = 3; qd8_f32_qc4w_gemm_config.planes = 2; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qd8_f32_qc4w_gemm_config.minmax.dqgemm[XNN_MR_TO_INDEX(1)] = xnn_init_hmp_dqgemm_ukernel((xnn_dqgemm_ukernel_fn) xnn_qd8_f32_qc4w_gemm_minmax_ukernel_1x4v__rvv); qd8_f32_qc4w_gemm_config.minmax.dqgemm[XNN_MR_TO_INDEX(4)] = xnn_init_hmp_dqgemm_ukernel((xnn_dqgemm_ukernel_fn) xnn_qd8_f32_qc4w_gemm_minmax_ukernel_4x4v__rvv); qd8_f32_qc4w_gemm_config.init.f32_qc4w = xnn_init_f32_qc4w_minmax_scalar_params; @@ -2201,7 +2201,7 @@ static void init_qd8_f32_qc4w_gemm_config(void) { static void init_qp8_f32_qc4w_gemm_config(void) { #if XNN_ARCH_ARM64 && XNN_ENABLE_KLEIDIAI const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); assert(hardware_config != NULL); if (XNN_ENABLE_ARM_SME2 && (hardware_config->arch_flags & xnn_arch_arm_sme2)) { #if XNN_ENABLE_ARM_SME2 @@ -2258,7 +2258,7 @@ static void init_qp8_f32_qc4w_gemm_config(void) { static void init_qp8_f32_qc8w_gemm_config(void) { #if XNN_ARCH_ARM64 && XNN_ENABLE_KLEIDIAI const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); assert(hardware_config != NULL); if (XNN_ENABLE_ARM_I8MM && (hardware_config->arch_flags & xnn_arch_arm_neon_i8mm)) { #if XNN_ENABLE_ARM_I8MM @@ -2292,7 +2292,7 @@ static void init_qp8_f32_qc8w_gemm_config(void) { static void init_qp8_f32_qb4w_gemm_config(void) { #if XNN_ARCH_ARM64 && XNN_ENABLE_KLEIDIAI const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); assert(hardware_config != NULL); if (XNN_ENABLE_ARM_I8MM && (hardware_config->arch_flags & xnn_arch_arm_neon_i8mm)) { #if XNN_ENABLE_ARM_I8MM @@ -2330,7 +2330,7 @@ static void init_qdu8_f32_qb4w_gemm_config(void) { qdu8_f32_qb4w_gemm_config.packed_stride_weights_and_biases = xnn_packed_stride_qb4_weights_and_biases; qdu8_f32_qb4w_gemm_config.pack_weights_and_biases = xnn_pack_qb4_weights_and_biases; #if XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512VNNIGFNI @@ -2371,7 +2371,7 @@ static void init_qd8_f32_qb4w_gemm_config(void) { qd8_f32_qb4w_gemm_config.pack_weights_and_biases = xnn_pack_qb4_weights_and_biases; #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -2402,7 +2402,7 @@ static void init_qd8_f32_qb4w_gemm_config(void) { qd8_f32_qb4w_gemm_config.planes = 2; } #elif XNN_ARCH_ARM64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if (XNN_ENABLE_ARM_I8MM && (hardware_config->arch_flags & xnn_arch_arm_neon_i8mm)) { @@ -2434,7 +2434,7 @@ static void init_qd8_f32_qb4w_gemm_config(void) { qd8_f32_qb4w_gemm_config.planes = 2; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { @@ -2492,7 +2492,7 @@ static void init_qd8_f16_qc8w_gemm_config(void) { qd8_f16_qc8w_gemm_config.pack_gemm_gio = (xnn_packw_gemm_gio_ukernel_fn) xnn_pack_qs8_gemm_gio_w; qd8_f16_qc8w_gemm_config.pack_gemm_goi = (xnn_packw_gemm_goi_ukernel_fn) xnn_pack_qs8_gemm_goi_w; #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -2577,7 +2577,7 @@ static void init_qd8_f16_qc8w_gemm_config(void) { #endif // XNN_ENABLE_ASSEMBLY } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_PLATFORM_IOS || XNN_PLATFORM_MAC || XNN_PLATFORM_WINDOWS @@ -2737,7 +2737,7 @@ static void init_qd8_f16_qc8w_gemm_config(void) { #endif // XNN_ENABLE_ASSEMBLY #endif // XNN_PLATFORM_IOS || XNN_PLATFORM_MAC || XNN_PLATFORM_WINDOWS #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512AMX @@ -2793,7 +2793,7 @@ static void init_qdu8_f16_qc8w_gemm_config(void) { qdu8_f16_qc8w_gemm_config.pack_gemm_gio = (xnn_packw_gemm_gio_ukernel_fn) xnn_pack_qs8_gemm_gio_w; qdu8_f16_qc8w_gemm_config.pack_gemm_goi = (xnn_packw_gemm_goi_ukernel_fn) xnn_pack_qs8_gemm_goi_w; #if XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX256VNNI @@ -2847,7 +2847,7 @@ static void init_qd8_f16_qc8w_igemm_config(void) { qd8_f16_qc8w_igemm_config.pack_gemm_gio = (xnn_packw_gemm_gio_ukernel_fn) xnn_pack_qs8_gemm_gio_w; qd8_f16_qc8w_igemm_config.pack_gemm_goi = (xnn_packw_gemm_goi_ukernel_fn) xnn_pack_qs8_gemm_goi_w; #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -2920,7 +2920,7 @@ static void init_qd8_f16_qc8w_igemm_config(void) { #endif // XNN_ENABLE_ASSEMBLY } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_PLATFORM_IOS || XNN_PLATFORM_MAC || XNN_PLATFORM_WINDOWS @@ -3080,7 +3080,7 @@ static void init_qd8_f16_qc8w_igemm_config(void) { #endif // XNN_ENABLE_ASSEMBLY #endif // XNN_PLATFORM_IOS || XNN_PLATFORM_MAC || XNN_PLATFORM_WINDOWS #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512AMX @@ -3136,7 +3136,7 @@ static void init_qdu8_f32_qc8w_gemm_config(void) { qdu8_f32_qc8w_gemm_config.pack_gemm_gio = (xnn_packw_gemm_gio_ukernel_fn) xnn_pack_qs8_gemm_gio_w; qdu8_f32_qc8w_gemm_config.pack_gemm_goi = (xnn_packw_gemm_goi_ukernel_fn) xnn_pack_qs8_gemm_goi_w; #if XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512VNNI && XNN_ARCH_X86_64 && !XNN_PLATFORM_WINDOWS @@ -3207,7 +3207,7 @@ static void init_qdu8_f32_qc8w_igemm_config(void) { qdu8_f32_qc8w_igemm_config.pack_gemm_gio = (xnn_packw_gemm_gio_ukernel_fn) xnn_pack_qs8_gemm_gio_w; qdu8_f32_qc8w_igemm_config.pack_gemm_goi = (xnn_packw_gemm_goi_ukernel_fn) xnn_pack_qs8_gemm_goi_w; #if XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512VNNI @@ -3260,7 +3260,7 @@ static void init_qdu8_f32_qc4w_gemm_config(void) { qdu8_f32_qc4w_gemm_config.pack_gemm_gio = (xnn_packw_gemm_gio_ukernel_fn) xnn_pack_qs8_qc4w_gemm_gio_w; // Ignored qdu8_f32_qc4w_gemm_config.pack_gemm_goi = (xnn_packw_gemm_goi_ukernel_fn) xnn_pack_qs8_qc4w_gemm_goi_w; // Ignored #if XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512VNNIGFNI && XNN_ENABLE_AVX256VNNI @@ -3375,7 +3375,7 @@ static void init_qd8_f32_qc8w_gemm_config(void) { qd8_f32_qc8w_gemm_config.pack_gemm_gio = (xnn_packw_gemm_gio_ukernel_fn) xnn_pack_qs8_gemm_gio_w; qd8_f32_qc8w_gemm_config.pack_gemm_goi = (xnn_packw_gemm_goi_ukernel_fn) xnn_pack_qs8_gemm_goi_w; #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -3493,7 +3493,7 @@ static void init_qd8_f32_qc8w_gemm_config(void) { qd8_f32_qc8w_gemm_config.init.f32 = xnn_init_f32_minmax_scalar_params; } #elif XNN_ARCH_ARM64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_PLATFORM_IOS || XNN_PLATFORM_MAC || XNN_PLATFORM_WINDOWS @@ -3682,7 +3682,7 @@ static void init_qd8_f32_qc8w_gemm_config(void) { #endif // XNN_ENABLE_ASSEMBLY #endif // XNN_PLATFORM_IOS || XNN_PLATFORM_MAC || XNN_PLATFORM_WINDOWS #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512AMX @@ -3763,7 +3763,7 @@ static void init_qd8_f32_qc8w_gemm_config(void) { qd8_f32_qc8w_gemm_config.log2_kr = 3; } #elif XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_wasm_sdot)) { @@ -3817,7 +3817,7 @@ static void init_qd8_f32_qc8w_gemm_config(void) { qd8_f32_qc8w_gemm_config.log2_kr = 1; qd8_f32_qc8w_gemm_config.log2_sr = 2; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qd8_f32_qc8w_gemm_config.minmax.dqgemm[XNN_MR_TO_INDEX(1)] = xnn_init_hmp_dqgemm_ukernel((xnn_dqgemm_ukernel_fn) xnn_qd8_f32_qc8w_gemm_minmax_ukernel_1x4v__rvv); qd8_f32_qc8w_gemm_config.minmax.dqgemm[XNN_MR_TO_INDEX(4)] = xnn_init_hmp_dqgemm_ukernel((xnn_dqgemm_ukernel_fn) xnn_qd8_f32_qc8w_gemm_minmax_ukernel_4x4v__rvv); qd8_f32_qc8w_gemm_config.minmax.dqigemm[XNN_MR_TO_INDEX(1)] = xnn_init_hmp_dqigemm_ukernel((xnn_dqigemm_ukernel_fn) xnn_qd8_f32_qc8w_igemm_minmax_ukernel_1x4v__rvv); @@ -3840,7 +3840,7 @@ static void init_qd8_f32_qc8w_gemm_config(void) { static void init_qs8_qc4w_gemm_config(void) { #if XNN_ARCH_ARM64 && !XNN_PLATFORM_WINDOWS - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if (XNN_ENABLE_ARM_DOTPROD && (hardware_config->arch_flags & xnn_arch_arm_neon_dot)) { @@ -3876,7 +3876,7 @@ static void init_qs8_qc8w_gemm_config(void) { qs8_qc8w_gemm_config.pack_gemm_gio = (xnn_packw_gemm_gio_ukernel_fn) xnn_pack_qs8_gemm_gio_w; qs8_qc8w_gemm_config.pack_gemm_goi = (xnn_packw_gemm_goi_ukernel_fn) xnn_pack_qs8_gemm_goi_w; #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -4128,7 +4128,7 @@ static void init_qs8_qc8w_gemm_config(void) { qs8_qc8w_gemm_config.log2_kr = 2; } #elif XNN_ARCH_ARM64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_PLATFORM_IOS || XNN_PLATFORM_MAC || XNN_PLATFORM_WINDOWS @@ -4403,7 +4403,7 @@ static void init_qs8_qc8w_gemm_config(void) { #endif // XNN_ENABLE_ASSEMBLY #endif // XNN_PLATFORM_IOS || XNN_PLATFORM_MAC || XNN_PLATFORM_WINDOWS #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512AMX @@ -4571,7 +4571,7 @@ static void init_qs8_qc8w_gemm_config(void) { } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD #if XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_wasm_sdot)) { @@ -4707,7 +4707,7 @@ static void init_qs8_qc8w_gemm_config(void) { #endif #endif #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qs8_qc8w_gemm_config.minmax.gemm[XNN_MR_TO_INDEX(1)] = xnn_init_hmp_gemm_ukernel((xnn_gemm_ukernel_fn) xnn_qs8_qc8w_gemm_minmax_fp32_ukernel_1x4v__rvv); qs8_qc8w_gemm_config.minmax.gemm[XNN_MR_TO_INDEX(4)] = xnn_init_hmp_gemm_ukernel((xnn_gemm_ukernel_fn) xnn_qs8_qc8w_gemm_minmax_fp32_ukernel_4x4v__rvv); qs8_qc8w_gemm_config.minmax.igemm[XNN_MR_TO_INDEX(1)] = xnn_init_hmp_igemm_ukernel((xnn_igemm_ukernel_fn) xnn_qs8_qc8w_igemm_minmax_fp32_ukernel_1x4v__rvv); @@ -4757,7 +4757,7 @@ static void init_qu8_gemm_config(void) { qu8_gemm_config.pack_gemm_gio = (xnn_packw_gemm_gio_ukernel_fn) xnn_pack_qu8_gemm_gio_w; qu8_gemm_config.pack_gemm_goi = (xnn_packw_gemm_goi_ukernel_fn) xnn_pack_qu8_gemm_goi_w; #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -4967,7 +4967,7 @@ static void init_qu8_gemm_config(void) { qu8_gemm_config.nr = 16; #endif // XNN_ENABLE_ASSEMBLY #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512SKX @@ -5041,8 +5041,8 @@ static void init_qu8_gemm_config(void) { assert(qu8_gemm_config.mr <= XNN_MAX_MR); } -const struct xnn_gemm_config* xnn_init_f16_gemm_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_gemm_config* xnn_get_f16_gemm_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -5050,8 +5050,8 @@ const struct xnn_gemm_config* xnn_init_f16_gemm_config() { return &f16_gemm_config; } -const struct xnn_gemm_config* xnn_init_pf16_gemm_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_gemm_config* xnn_get_pf16_gemm_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -5059,8 +5059,8 @@ const struct xnn_gemm_config* xnn_init_pf16_gemm_config() { return pf16_gemm_config.mr ? &pf16_gemm_config : NULL; } -const struct xnn_gemm_config* xnn_init_bf16_f32_gemm_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_gemm_config* xnn_get_bf16_f32_gemm_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_bf16_compatible_config(hardware_config)) { return NULL; } @@ -5068,24 +5068,24 @@ const struct xnn_gemm_config* xnn_init_bf16_f32_gemm_config() { return &bf16_f32_gemm_config; } -const struct xnn_gemm_config* xnn_init_pf32_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_pf32_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(pf32_gemm); return pf32_gemm_config.mr ? &pf32_gemm_config : NULL; } -const struct xnn_gemm_config* xnn_init_pqs8_qc8w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_pqs8_qc8w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(pqs8_qc8w_gemm); return pqs8_qc8w_gemm_config.mr ? &pqs8_qc8w_gemm_config : NULL; } -const struct xnn_gemm_config* xnn_init_f32_gemm_config(uint32_t flags) { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_f32_gemm_config(uint32_t flags) { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(f32_gemm); @@ -5096,16 +5096,16 @@ const struct xnn_gemm_config* xnn_init_f32_gemm_config(uint32_t flags) { } } -const struct xnn_gemm_config* xnn_init_f32_igemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_f32_igemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(f32_igemm); return &f32_igemm_config; } -const struct xnn_gemm_config* xnn_init_f32_gemm_nr2_config(uint32_t flags) { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_f32_gemm_nr2_config(uint32_t flags) { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(f32_gemm_nr2); @@ -5116,24 +5116,24 @@ const struct xnn_gemm_config* xnn_init_f32_gemm_nr2_config(uint32_t flags) { } } -const struct xnn_gemm_config* xnn_init_f32_qc4w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_f32_qc4w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(f32_qc4w_gemm); return &f32_qc4w_gemm_config; } -const struct xnn_gemm_config* xnn_init_f32_qc8w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_f32_qc8w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(f32_qc8w_gemm); return &f32_qc8w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qd8_f16_qc8w_gemm_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_gemm_config* xnn_get_qd8_f16_qc8w_gemm_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -5141,8 +5141,8 @@ const struct xnn_gemm_config* xnn_init_qd8_f16_qc8w_gemm_config() { return &qd8_f16_qc8w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qd8_f16_qc8w_igemm_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_gemm_config* xnn_get_qd8_f16_qc8w_igemm_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -5150,8 +5150,8 @@ const struct xnn_gemm_config* xnn_init_qd8_f16_qc8w_igemm_config() { return &qd8_f16_qc8w_igemm_config; } -const struct xnn_gemm_config* xnn_init_qd8_f16_qc4w_gemm_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_gemm_config* xnn_get_qd8_f16_qc4w_gemm_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -5164,8 +5164,8 @@ const struct xnn_gemm_config* xnn_init_qd8_f16_qc4w_gemm_config() { return &qd8_f16_qc4w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qdu8_f16_qc4w_gemm_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_gemm_config* xnn_get_qdu8_f16_qc4w_gemm_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -5173,8 +5173,8 @@ const struct xnn_gemm_config* xnn_init_qdu8_f16_qc4w_gemm_config() { return &qdu8_f16_qc4w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qd8_f16_qb4w_gemm_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_gemm_config* xnn_get_qd8_f16_qb4w_gemm_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -5182,72 +5182,72 @@ const struct xnn_gemm_config* xnn_init_qd8_f16_qb4w_gemm_config() { return &qd8_f16_qb4w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qd8_f32_qc4w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qd8_f32_qc4w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qd8_f32_qc4w_gemm); return &qd8_f32_qc4w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qdu8_f32_qc4w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qdu8_f32_qc4w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qdu8_f32_qc4w_gemm); return &qdu8_f32_qc4w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qd8_f32_qb4w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qd8_f32_qb4w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qd8_f32_qb4w_gemm); return &qd8_f32_qb4w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qdu8_f32_qb4w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qdu8_f32_qb4w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qdu8_f32_qb4w_gemm); return &qdu8_f32_qb4w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qdu8_f16_qc8w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qdu8_f16_qc8w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qdu8_f16_qc8w_gemm); return &qdu8_f16_qc8w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qdu8_f32_qc8w_igemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qdu8_f32_qc8w_igemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qdu8_f32_qc8w_igemm); return &qdu8_f32_qc8w_igemm_config; } -const struct xnn_gemm_config* xnn_init_qdu8_f32_qc8w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qdu8_f32_qc8w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qdu8_f32_qc8w_gemm); return &qdu8_f32_qc8w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qd8_f32_qc8w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qd8_f32_qc8w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qd8_f32_qc8w_gemm); return &qd8_f32_qc8w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qp8_f32_qc4w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qp8_f32_qc4w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qp8_f32_qc4w_gemm); @@ -5258,8 +5258,8 @@ const struct xnn_gemm_config* xnn_init_qp8_f32_qc4w_gemm_config() { return NULL; } -const struct xnn_gemm_config* xnn_init_qp8_f32_qc8w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qp8_f32_qc8w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qp8_f32_qc8w_gemm); @@ -5270,9 +5270,9 @@ const struct xnn_gemm_config* xnn_init_qp8_f32_qc8w_gemm_config() { return NULL; } -const struct xnn_gemm_config* xnn_init_qp8_f32_qb4w_gemm_config() { +const struct xnn_gemm_config* xnn_get_qp8_f32_qb4w_gemm_config() { const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -5284,24 +5284,24 @@ XNN_INIT_ONCE(qp8_f32_qb4w_gemm); return NULL; } -const struct xnn_gemm_config* xnn_init_qs8_qc4w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qs8_qc4w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qs8_qc4w_gemm); return &qs8_qc4w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qs8_qc8w_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qs8_qc8w_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qs8_qc8w_gemm); return &qs8_qc8w_gemm_config; } -const struct xnn_gemm_config* xnn_init_qu8_gemm_config() { - if (xnn_init_hardware_config() == NULL) { +const struct xnn_gemm_config* xnn_get_qu8_gemm_config() { + if (xnn_get_hardware_config() == NULL) { return NULL; } XNN_INIT_ONCE(qu8_gemm); diff --git a/src/configs/hardware-config.c b/src/configs/hardware-config.c index b4e942aa695..6ad6094565c 100644 --- a/src/configs/hardware-config.c +++ b/src/configs/hardware-config.c @@ -348,7 +348,7 @@ static void init_hardware_config(void) { #endif // XNN_ENABLE_CPUINFO } -const struct xnn_hardware_config* xnn_init_hardware_config() { +const struct xnn_hardware_config* xnn_get_hardware_config() { #if !XNN_PLATFORM_WEB && !XNN_ARCH_RISCV && !XNN_ARCH_PPC64 && XNN_ENABLE_CPUINFO if (!cpuinfo_initialize()) { xnn_log_error("failed to initialize cpuinfo"); diff --git a/src/configs/ibilinear-chw-config.c b/src/configs/ibilinear-chw-config.c index 5634b03fbd5..e82ffc170b4 100644 --- a/src/configs/ibilinear-chw-config.c +++ b/src/configs/ibilinear-chw-config.c @@ -21,14 +21,14 @@ XNN_INIT_ONCE_GUARD(f32_ibilinear_chw); static void init_f16_ibilinear_chw_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_ibilinear_chw_config.ukernel = (xnn_ibilinear_chw_ukernel_fn) xnn_f16_ibilinear_chw_ukernel__neonfp16arith_p8; f16_ibilinear_chw_config.channel_tile = 1; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_ibilinear_chw_config.ukernel = (xnn_ibilinear_chw_ukernel_fn) xnn_f16_ibilinear_chw_ukernel__neonfp16arith_p8; @@ -43,7 +43,7 @@ static void init_f16_ibilinear_chw_config(void) { static void init_f32_ibilinear_chw_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_ibilinear_chw_config.ukernel = (xnn_ibilinear_chw_ukernel_fn) xnn_f32_ibilinear_chw_ukernel__neon_p8; @@ -71,8 +71,8 @@ static void init_f32_ibilinear_chw_config(void) { (xnn_indirection_init_resize_bilinear2d_chw_fn) xnn_indirection_init_resize_bilinear2d_chw_f32; } -const struct xnn_ibilinear_chw_config* xnn_init_f16_ibilinear_chw_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_ibilinear_chw_config* xnn_get_f16_ibilinear_chw_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_chw_compatible_config(hardware_config)) { return NULL; } @@ -80,8 +80,8 @@ const struct xnn_ibilinear_chw_config* xnn_init_f16_ibilinear_chw_config() { return &f16_ibilinear_chw_config; } -const struct xnn_ibilinear_chw_config* xnn_init_f32_ibilinear_chw_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_ibilinear_chw_config* xnn_get_f32_ibilinear_chw_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_chw_compatible_config(hardware_config)) { return NULL; } diff --git a/src/configs/ibilinear-config.c b/src/configs/ibilinear-config.c index 7445a913b56..e40895ca75f 100644 --- a/src/configs/ibilinear-config.c +++ b/src/configs/ibilinear-config.c @@ -25,21 +25,21 @@ XNN_INIT_ONCE_GUARD(u8_ibilinear); static void init_f16_ibilinear_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_ibilinear_config.ukernel = (xnn_ibilinear_ukernel_fn) xnn_f16_ibilinear_ukernel__neonfp16arith_c8; f16_ibilinear_config.pixel_tile = 1; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_ibilinear_config.ukernel = (xnn_ibilinear_ukernel_fn) xnn_f16_ibilinear_ukernel__neonfp16arith_c8; f16_ibilinear_config.pixel_tile = 1; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { f16_ibilinear_config.ukernel = (xnn_ibilinear_ukernel_fn) xnn_f16_ibilinear_ukernel__fma3_c8; @@ -54,7 +54,7 @@ static void init_f16_ibilinear_config(void) { static void init_f32_ibilinear_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_ibilinear_config.ukernel = (xnn_ibilinear_ukernel_fn) xnn_f32_ibilinear_ukernel__neon_c8; @@ -87,7 +87,7 @@ static void init_f32_ibilinear_config(void) { static void init_s8_ibilinear_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { s8_ibilinear_config.ukernel = (xnn_ibilinear_ukernel_fn) xnn_s8_ibilinear_ukernel__neon_c8; @@ -100,7 +100,7 @@ static void init_s8_ibilinear_config(void) { s8_ibilinear_config.ukernel = (xnn_ibilinear_ukernel_fn) xnn_s8_ibilinear_ukernel__neon_c16; s8_ibilinear_config.pixel_tile = 1; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_sse4_1)) { s8_ibilinear_config.ukernel = (xnn_ibilinear_ukernel_fn) xnn_s8_ibilinear_ukernel__sse41_c16; @@ -124,7 +124,7 @@ static void init_s8_ibilinear_config(void) { static void init_u8_ibilinear_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { u8_ibilinear_config.ukernel = (xnn_ibilinear_ukernel_fn) xnn_u8_ibilinear_ukernel__neon_c8; @@ -137,7 +137,7 @@ static void init_u8_ibilinear_config(void) { u8_ibilinear_config.ukernel = (xnn_ibilinear_ukernel_fn) xnn_u8_ibilinear_ukernel__neon_c16; u8_ibilinear_config.pixel_tile = 1; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_sse4_1)) { u8_ibilinear_config.ukernel = (xnn_ibilinear_ukernel_fn) xnn_u8_ibilinear_ukernel__sse41_c16; @@ -159,8 +159,8 @@ static void init_u8_ibilinear_config(void) { (xnn_indirection_init_resize_bilinear2d_hwc_fn) xnn_indirection_init_resize_bilinear2d_hwc_q11; } -const struct xnn_ibilinear_config* xnn_init_f16_ibilinear_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_ibilinear_config* xnn_get_f16_ibilinear_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -168,8 +168,8 @@ const struct xnn_ibilinear_config* xnn_init_f16_ibilinear_config() { return &f16_ibilinear_config; } -const struct xnn_ibilinear_config* xnn_init_f32_ibilinear_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_ibilinear_config* xnn_get_f32_ibilinear_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -177,8 +177,8 @@ const struct xnn_ibilinear_config* xnn_init_f32_ibilinear_config() { return &f32_ibilinear_config; } -const struct xnn_ibilinear_config* xnn_init_s8_ibilinear_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_ibilinear_config* xnn_get_s8_ibilinear_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -186,8 +186,8 @@ const struct xnn_ibilinear_config* xnn_init_s8_ibilinear_config() { return &s8_ibilinear_config; } -const struct xnn_ibilinear_config* xnn_init_u8_ibilinear_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_ibilinear_config* xnn_get_u8_ibilinear_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/lut32norm-config.c b/src/configs/lut32norm-config.c index d0d655f714f..db88f4c84f1 100644 --- a/src/configs/lut32norm-config.c +++ b/src/configs/lut32norm-config.c @@ -20,8 +20,8 @@ static void init_u8_lut32norm_config(void) { u8_lut32norm_config.lut32norm = xnn_u8_lut32norm_ukernel__scalar; } -const struct xnn_lut32norm_config* xnn_init_u8_lut32norm_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_lut32norm_config* xnn_get_u8_lut32norm_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/maxpool-config.c b/src/configs/maxpool-config.c index f6a5a3bcab8..d382e9e70c2 100644 --- a/src/configs/maxpool-config.c +++ b/src/configs/maxpool-config.c @@ -25,21 +25,21 @@ XNN_INIT_ONCE_GUARD(u8_maxpool); static void init_f16_maxpool_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_maxpool_config.ukernel = (xnn_maxpool_ukernel_fn) xnn_f16_maxpool_minmax_ukernel_9p__neonfp16arith_u8; f16_maxpool_config.init.f16 = xnn_init_f16_minmax_scalar_params; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_maxpool_config.ukernel = (xnn_maxpool_ukernel_fn) xnn_f16_maxpool_minmax_ukernel_9p__neonfp16arith_u8; f16_maxpool_config.init.f16 = xnn_init_f16_minmax_scalar_params; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { f16_maxpool_config.ukernel = (xnn_maxpool_ukernel_fn) xnn_f16_maxpool_minmax_ukernel_9p__avx2_u16; @@ -53,7 +53,7 @@ static void init_f16_maxpool_config(void) { static void init_f32_maxpool_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_maxpool_config.ukernel = (xnn_maxpool_ukernel_fn) xnn_f32_maxpool_minmax_ukernel_9p__neon_u4; @@ -82,7 +82,7 @@ static void init_f32_maxpool_config(void) { static void init_s8_maxpool_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { s8_maxpool_config.ukernel = (xnn_maxpool_ukernel_fn) xnn_s8_maxpool_minmax_ukernel_9p__neon_u16; @@ -95,7 +95,7 @@ static void init_s8_maxpool_config(void) { s8_maxpool_config.ukernel = (xnn_maxpool_ukernel_fn) xnn_s8_maxpool_minmax_ukernel_9p__neon_u16; s8_maxpool_config.init.s8 = xnn_init_s8_minmax_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_sse4_1)) { s8_maxpool_config.ukernel = (xnn_maxpool_ukernel_fn) xnn_s8_maxpool_minmax_ukernel_9p__sse41_u16; @@ -115,7 +115,7 @@ static void init_s8_maxpool_config(void) { static void init_u8_maxpool_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { u8_maxpool_config.ukernel = (xnn_maxpool_ukernel_fn) xnn_u8_maxpool_minmax_ukernel_9p__neon_u16; @@ -139,8 +139,8 @@ static void init_u8_maxpool_config(void) { #endif } -const struct xnn_maxpool_config* xnn_init_f16_maxpool_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_maxpool_config* xnn_get_f16_maxpool_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -148,8 +148,8 @@ const struct xnn_maxpool_config* xnn_init_f16_maxpool_config() { return &f16_maxpool_config; } -const struct xnn_maxpool_config* xnn_init_f32_maxpool_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_maxpool_config* xnn_get_f32_maxpool_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -157,8 +157,8 @@ const struct xnn_maxpool_config* xnn_init_f32_maxpool_config() { return &f32_maxpool_config; } -const struct xnn_maxpool_config* xnn_init_s8_maxpool_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_maxpool_config* xnn_get_s8_maxpool_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -166,8 +166,8 @@ const struct xnn_maxpool_config* xnn_init_s8_maxpool_config() { return &s8_maxpool_config; } -const struct xnn_maxpool_config* xnn_init_u8_maxpool_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_maxpool_config* xnn_get_u8_maxpool_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/pack-lh-config.c b/src/configs/pack-lh-config.c index 40a78d61dcb..fadbb351ac7 100644 --- a/src/configs/pack-lh-config.c +++ b/src/configs/pack-lh-config.c @@ -41,9 +41,9 @@ static void init_f16_qdint8_pack_lh_config(void) { f16_qdint8_pack_lh_config.log2_packed_element_size = 0; } -const struct xnn_pack_lh_config* xnn_init_f16_qdint8_pack_lh_config() { +const struct xnn_pack_lh_config* xnn_get_f16_qdint8_pack_lh_config() { const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -59,9 +59,9 @@ static void init_f16_qduint8_pack_lh_config(void) { f16_qduint8_pack_lh_config.log2_packed_element_size = 0; } -const struct xnn_pack_lh_config* xnn_init_f16_qduint8_pack_lh_config() { +const struct xnn_pack_lh_config* xnn_get_f16_qduint8_pack_lh_config() { const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -77,9 +77,9 @@ static void init_f32_qdint8_pack_lh_config(void) { f32_qdint8_pack_lh_config.log2_packed_element_size = 0; } -const struct xnn_pack_lh_config* xnn_init_f32_qdint8_pack_lh_config() { +const struct xnn_pack_lh_config* xnn_get_f32_qdint8_pack_lh_config() { const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -95,9 +95,9 @@ static void init_f32_qduint8_pack_lh_config(void) { f32_qduint8_pack_lh_config.log2_packed_element_size = 0; } -const struct xnn_pack_lh_config* xnn_init_f32_qduint8_pack_lh_config() { +const struct xnn_pack_lh_config* xnn_get_f32_qduint8_pack_lh_config() { const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -117,9 +117,9 @@ static void init_qp8_pack_lh_config(void) { qp8_pack_lh_config.log2_packed_element_size = 0; } -const struct xnn_pack_lh_config* xnn_init_qp8_pack_lh_config() { +const struct xnn_pack_lh_config* xnn_get_qp8_pack_lh_config() { const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -130,7 +130,7 @@ const struct xnn_pack_lh_config* xnn_init_qp8_pack_lh_config() { static void init_x32_pack_lh_config(void) { #if XNN_ARCH_ARM64 && XNN_ENABLE_KLEIDIAI #if XNN_ENABLE_ARM_SME2 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_sme2)) { x32_pack_lh_config.ukernel = (xnn_pack_lh_ukernel_fn) xnn_x32_pack_lh_ukernel__neonsme2; @@ -144,8 +144,8 @@ static void init_x32_pack_lh_config(void) { x32_pack_lh_config.gemv_noop = true; } -const struct xnn_pack_lh_config* xnn_init_x32_pack_lh_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_pack_lh_config* xnn_get_x32_pack_lh_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -156,7 +156,7 @@ const struct xnn_pack_lh_config* xnn_init_x32_pack_lh_config() { static void init_x16_pack_lh_config(void) { #if XNN_ARCH_ARM64 && XNN_ENABLE_KLEIDIAI #if XNN_ENABLE_ARM_SME2 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_sme2)) { x16_pack_lh_config.ukernel = (xnn_pack_lh_ukernel_fn) xnn_x16_pack_lh_ukernel__neonsme2; @@ -170,8 +170,8 @@ static void init_x16_pack_lh_config(void) { x16_pack_lh_config.gemv_noop = true; } -const struct xnn_pack_lh_config* xnn_init_x16_pack_lh_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_pack_lh_config* xnn_get_x16_pack_lh_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -182,7 +182,7 @@ const struct xnn_pack_lh_config* xnn_init_x16_pack_lh_config() { static void init_x8_pack_lh_config(void) { #if XNN_ARCH_ARM64 && XNN_ENABLE_KLEIDIAI #if XNN_ENABLE_ARM_SME2 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_sme2)) { x8_pack_lh_config.ukernel = (xnn_pack_lh_ukernel_fn) xnn_x8_pack_lh_ukernel__neonsme2; @@ -196,8 +196,8 @@ static void init_x8_pack_lh_config(void) { x8_pack_lh_config.gemv_noop = true; } -const struct xnn_pack_lh_config* xnn_init_x8_pack_lh_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_pack_lh_config* xnn_get_x8_pack_lh_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/raddstoreexpminusmax-config.c b/src/configs/raddstoreexpminusmax-config.c index a77f7644c8b..7498f5e09d2 100644 --- a/src/configs/raddstoreexpminusmax-config.c +++ b/src/configs/raddstoreexpminusmax-config.c @@ -21,19 +21,19 @@ XNN_INIT_ONCE_GUARD(f32_raddstoreexpminusmax); static void init_f16_raddstoreexpminusmax_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_raddstoreexpminusmax_config.ukernel = (xnn_raddstoreexpminusmax_ukernel_fn) xnn_f16_raddstoreexpminusmax_ukernel__neonfp16arith_rr2_p2_u32; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_raddstoreexpminusmax_config.ukernel = (xnn_raddstoreexpminusmax_ukernel_fn) xnn_f16_raddstoreexpminusmax_ukernel__neonfp16arith_rr2_p2_u32; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { f16_raddstoreexpminusmax_config.ukernel = (xnn_raddstoreexpminusmax_ukernel_fn) xnn_f16_raddstoreexpminusmax_ukernel__avx2_rr1_p2_u32; @@ -43,7 +43,7 @@ static void init_f16_raddstoreexpminusmax_config(void) { static void init_f32_raddstoreexpminusmax_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_raddstoreexpminusmax_config.ukernel = @@ -56,7 +56,7 @@ static void init_f32_raddstoreexpminusmax_config(void) { f32_raddstoreexpminusmax_config.ukernel = (xnn_raddstoreexpminusmax_ukernel_fn) xnn_f32_raddstoreexpminusmax_ukernel__neonfma_rr1_lut64_p2_u16_acc2; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -100,8 +100,8 @@ static bool is_f16_compatible_config(const struct xnn_hardware_config* hardware_ #endif } -const struct xnn_raddstoreexpminusmax_config* xnn_init_f16_raddstoreexpminusmax_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_raddstoreexpminusmax_config* xnn_get_f16_raddstoreexpminusmax_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !is_f16_compatible_config(hardware_config)) { return NULL; } @@ -109,8 +109,8 @@ const struct xnn_raddstoreexpminusmax_config* xnn_init_f16_raddstoreexpminusmax_ return &f16_raddstoreexpminusmax_config; } -const struct xnn_raddstoreexpminusmax_config* xnn_init_f32_raddstoreexpminusmax_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_raddstoreexpminusmax_config* xnn_get_f32_raddstoreexpminusmax_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/reduce-config.c b/src/configs/reduce-config.c index eebbd923894..18f2d734665 100644 --- a/src/configs/reduce-config.c +++ b/src/configs/reduce-config.c @@ -76,7 +76,7 @@ static uint32_t pack_float32(float value) { static void init_s8_rmax_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { s8_rmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_s8_rmax_ukernel__neon_u32_acc2; @@ -89,7 +89,7 @@ static void init_s8_rmax_config(void) { s8_rmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_s8_rmax_ukernel__neon_u32_acc2; s8_rmax_config.rd_ukernel = (xnn_reduce_discontiguous_ukernel_fn) xnn_s8_rdmax_ukernel_2p2x__neon_c32; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_sse4_1)) { s8_rmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_s8_rmax_ukernel__sse41_u32_acc2; @@ -114,7 +114,7 @@ static void init_s8_rmax_config(void) { static void init_s8_rminmax_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { s8_rminmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_s8_rminmax_ukernel__neon_u32_acc2; @@ -124,7 +124,7 @@ static void init_s8_rminmax_config(void) { #elif XNN_ARCH_ARM64 s8_rminmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_s8_rminmax_ukernel__neon_u32_acc2; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_sse4_1)) { s8_rminmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_s8_rminmax_ukernel__sse41_u32_acc2; @@ -142,7 +142,7 @@ static void init_s8_rminmax_config(void) { static void init_s8_rmin_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { s8_rmin_config.ukernel = (xnn_reduce_ukernel_fn) xnn_s8_rmin_ukernel__neon_u32_acc2; @@ -155,7 +155,7 @@ static void init_s8_rmin_config(void) { s8_rmin_config.ukernel = (xnn_reduce_ukernel_fn) xnn_s8_rmin_ukernel__neon_u32_acc2; s8_rmin_config.rd_ukernel = (xnn_reduce_discontiguous_ukernel_fn) xnn_s8_rdmin_ukernel_2p2x__neon_c32; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_sse4_1)) { s8_rmin_config.ukernel = (xnn_reduce_ukernel_fn) xnn_s8_rmin_ukernel__sse41_u32_acc2; @@ -180,7 +180,7 @@ static void init_s8_rmin_config(void) { static void init_u8_rmax_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { u8_rmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_u8_rmax_ukernel__neon_u32_acc2; @@ -211,7 +211,7 @@ static void init_u8_rmax_config(void) { static void init_u8_rminmax_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { u8_rminmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_u8_rminmax_ukernel__neon_u32_acc2; @@ -233,7 +233,7 @@ static void init_u8_rminmax_config(void) { static void init_u8_rmin_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { u8_rmin_config.ukernel = (xnn_reduce_ukernel_fn) xnn_u8_rmin_ukernel__neon_u32_acc2; @@ -264,7 +264,7 @@ static void init_u8_rmin_config(void) { static void init_qs8_rsum_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -282,7 +282,7 @@ static void init_qs8_rsum_config(void) { qs8_rsum_config.rd_ukernel = (xnn_reduce_discontiguous_ukernel_fn) xnn_qs8_rdsum_ukernel_7p7x__scalar_c4; } #elif XNN_ARCH_ARM64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (XNN_ENABLE_ARM_DOTPROD && (hardware_config->arch_flags & xnn_arch_arm_neon_dot)) { @@ -294,7 +294,7 @@ static void init_qs8_rsum_config(void) { } qs8_rsum_config.rd_ukernel = (xnn_reduce_discontiguous_ukernel_fn) xnn_qs8_rdsum_ukernel_7p7x__neon_c32; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512VNNI @@ -355,7 +355,7 @@ static void init_qs8_rsum_config(void) { static void init_qu8_rsum_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -369,7 +369,7 @@ static void init_qu8_rsum_config(void) { qu8_rsum_config.ukernel = (xnn_reduce_ukernel_fn) xnn_qu8_rsum_ukernel__neon_u32_acc2; qu8_rsum_config.rd_ukernel = (xnn_reduce_discontiguous_ukernel_fn) xnn_qu8_rdsum_ukernel_7p7x__neon_u16; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { @@ -400,14 +400,14 @@ static void init_qu8_rsum_config(void) { static void init_f16_f32acc_rsum_config(void) { #if (XNN_ARCH_ARM || XNN_ARCH_ARM64) && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_f32acc_rsum_config.ukernel = (xnn_reduce_ukernel_fn) xnn_f16_f32acc_rsum_ukernel__neonfp16arith_u32_acc4; f16_f32acc_rsum_config.rd_ukernel = (xnn_reduce_discontiguous_ukernel_fn) xnn_f16_f32acc_rdsum_ukernel_7p7x__neonfp16arith_c16; } #elif (XNN_ARCH_X86 || XNN_ARCH_X86_64) - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -437,7 +437,7 @@ static void init_f16_f32acc_rsum_config(void) { static void init_f16_rmax_config(void) { #if (XNN_ARCH_ARM || XNN_ARCH_ARM64) && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_f16_rmax_ukernel__neonfp16arith_u32_acc4; @@ -447,7 +447,7 @@ static void init_f16_rmax_config(void) { f16_rmax_config.rd_ukernel = (xnn_reduce_discontiguous_ukernel_fn) xnn_f16_rdmax_ukernel_2p2x__scalar_c2; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); (void) hardware_config; // May be unused. #if XNN_ENABLE_AVX512FP16 @@ -477,7 +477,7 @@ static void init_f16_rmax_config(void) { static void init_f16_rminmax_config(void) { #if (XNN_ARCH_ARM || XNN_ARCH_ARM64) && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rminmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_f16_rminmax_ukernel__neonfp16arith_u32_acc4; @@ -486,7 +486,7 @@ static void init_f16_rminmax_config(void) { } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 #if XNN_ENABLE_AVX512FP16 || XNN_ENABLE_AVX512SKX - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #endif #if XNN_ENABLE_AVX512FP16 @@ -509,7 +509,7 @@ static void init_f16_rminmax_config(void) { static void init_f16_rmin_config(void) { #if (XNN_ARCH_ARM || XNN_ARCH_ARM64) && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rmin_config.ukernel = (xnn_reduce_ukernel_fn) xnn_f16_rmin_ukernel__neonfp16arith_u32_acc4; @@ -520,7 +520,7 @@ static void init_f16_rmin_config(void) { } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 #if XNN_ENABLE_AVX512FP16 || XNN_ENABLE_AVX512SKX - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #endif #if XNN_ENABLE_AVX512FP16 @@ -547,7 +547,7 @@ static void init_f16_rmin_config(void) { static void init_f32_rmax_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_rmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_f32_rmax_ukernel__neon_u16_acc4; @@ -560,7 +560,7 @@ static void init_f32_rmax_config(void) { f32_rmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_f32_rmax_ukernel__neon_u16_acc4; f32_rmax_config.rd_ukernel = (xnn_reduce_discontiguous_ukernel_fn) xnn_f32_rdmax_ukernel_2p2x__neon_c32; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -601,7 +601,7 @@ static void init_f32_rmax_config(void) { static void init_f32_rminmax_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_rminmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_f32_rminmax_ukernel__neon_u16_acc4; @@ -611,7 +611,7 @@ static void init_f32_rminmax_config(void) { #elif XNN_ARCH_ARM64 f32_rminmax_config.ukernel = (xnn_reduce_ukernel_fn) xnn_f32_rminmax_ukernel__neon_u16_acc4; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -636,7 +636,7 @@ static void init_f32_rminmax_config(void) { static void init_f32_rmin_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_rmin_config.ukernel = (xnn_reduce_ukernel_fn) xnn_f32_rmin_ukernel__neon_u16_acc4; @@ -649,7 +649,7 @@ static void init_f32_rmin_config(void) { f32_rmin_config.ukernel = (xnn_reduce_ukernel_fn) xnn_f32_rmin_ukernel__neon_u16_acc4; f32_rmin_config.rd_ukernel = (xnn_reduce_discontiguous_ukernel_fn) xnn_f32_rdmin_ukernel_2p2x__neon_c32; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -690,7 +690,7 @@ static void init_f32_rmin_config(void) { static void init_f32_rsum_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_rsum_config.ukernel = (xnn_reduce_ukernel_fn) xnn_f32_rsum_ukernel__neon_u16_acc4; @@ -703,7 +703,7 @@ static void init_f32_rsum_config(void) { f32_rsum_config.ukernel = (xnn_reduce_ukernel_fn) xnn_f32_rsum_ukernel__neon_u16_acc4; f32_rsum_config.rd_ukernel = (xnn_reduce_discontiguous_ukernel_fn) xnn_f32_rdsum_ukernel_7p7x__neon_c16; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -749,8 +749,8 @@ static void init_f32_rsum_config(void) { f32_rsum_config.update = xnn_update_f32_reduce_scalar_params; } -const struct xnn_reduce_config* xnn_init_f16_f32acc_rsum_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_f16_f32acc_rsum_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -758,8 +758,8 @@ const struct xnn_reduce_config* xnn_init_f16_f32acc_rsum_config() { return &f16_f32acc_rsum_config; } -const struct xnn_reduce_config* xnn_init_f16_rmax_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_f16_rmax_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -767,8 +767,8 @@ const struct xnn_reduce_config* xnn_init_f16_rmax_config() { return &f16_rmax_config; } -const struct xnn_reduce_config* xnn_init_f16_rminmax_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_f16_rminmax_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -776,8 +776,8 @@ const struct xnn_reduce_config* xnn_init_f16_rminmax_config() { return &f16_rminmax_config; } -const struct xnn_reduce_config* xnn_init_f16_rmin_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_f16_rmin_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -785,8 +785,8 @@ const struct xnn_reduce_config* xnn_init_f16_rmin_config() { return &f16_rmin_config; } -const struct xnn_reduce_config* xnn_init_f32_rmax_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_f32_rmax_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -794,8 +794,8 @@ const struct xnn_reduce_config* xnn_init_f32_rmax_config() { return &f32_rmax_config; } -const struct xnn_reduce_config* xnn_init_f32_rminmax_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_f32_rminmax_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -803,8 +803,8 @@ const struct xnn_reduce_config* xnn_init_f32_rminmax_config() { return &f32_rminmax_config; } -const struct xnn_reduce_config* xnn_init_f32_rmin_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_f32_rmin_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -812,8 +812,8 @@ const struct xnn_reduce_config* xnn_init_f32_rmin_config() { return &f32_rmin_config; } -const struct xnn_reduce_config* xnn_init_f32_rsum_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_f32_rsum_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -821,8 +821,8 @@ const struct xnn_reduce_config* xnn_init_f32_rsum_config() { return &f32_rsum_config; } -const struct xnn_reduce_config* xnn_init_s8_rmax_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_s8_rmax_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -830,8 +830,8 @@ const struct xnn_reduce_config* xnn_init_s8_rmax_config() { return &s8_rmax_config; } -const struct xnn_reduce_config* xnn_init_s8_rminmax_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_s8_rminmax_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -839,8 +839,8 @@ const struct xnn_reduce_config* xnn_init_s8_rminmax_config() { return &s8_rminmax_config; } -const struct xnn_reduce_config* xnn_init_s8_rmin_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_s8_rmin_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -848,8 +848,8 @@ const struct xnn_reduce_config* xnn_init_s8_rmin_config() { return &s8_rmin_config; } -const struct xnn_reduce_config* xnn_init_u8_rmax_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_u8_rmax_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -857,8 +857,8 @@ const struct xnn_reduce_config* xnn_init_u8_rmax_config() { return &u8_rmax_config; } -const struct xnn_reduce_config* xnn_init_u8_rminmax_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_u8_rminmax_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -866,8 +866,8 @@ const struct xnn_reduce_config* xnn_init_u8_rminmax_config() { return &u8_rminmax_config; } -const struct xnn_reduce_config* xnn_init_u8_rmin_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_u8_rmin_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -875,8 +875,8 @@ const struct xnn_reduce_config* xnn_init_u8_rmin_config() { return &u8_rmin_config; } -const struct xnn_reduce_config* xnn_init_qs8_rsum_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_qs8_rsum_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -884,8 +884,8 @@ const struct xnn_reduce_config* xnn_init_qs8_rsum_config() { return &qs8_rsum_config; } -const struct xnn_reduce_config* xnn_init_qu8_rsum_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_reduce_config* xnn_get_qu8_rsum_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/spmm-config.c b/src/configs/spmm-config.c index d91b682049d..1493376ed75 100644 --- a/src/configs/spmm-config.c +++ b/src/configs/spmm-config.c @@ -25,7 +25,7 @@ XNN_INIT_ONCE_GUARD(f32_spmm4); static void init_f16_spmm_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_spmm_config.ukernel = (xnn_spmm_ukernel_fn) xnn_f16_spmm_minmax_ukernel_32x1__neonfp16arith_pipelined; @@ -34,7 +34,7 @@ static void init_f16_spmm_config(void) { f16_spmm_config.nr = 1; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_spmm_config.ukernel = (xnn_spmm_ukernel_fn) xnn_f16_spmm_minmax_ukernel_32x1__neonfp16arith_pipelined; @@ -47,7 +47,7 @@ static void init_f16_spmm_config(void) { static void init_f32_spmm_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_spmm_config.ukernel = (xnn_spmm_ukernel_fn) xnn_f32_spmm_minmax_ukernel_32x1__neon; @@ -71,13 +71,13 @@ static void init_f32_spmm_config(void) { f32_spmm_config.mr = 32; f32_spmm_config.nr = 1; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_spmm_config.ukernel = (xnn_spmm_ukernel_fn) xnn_f32_spmm_minmax_ukernel_8vx1__rvv; f32_spmm_config.init.f32 = xnn_init_f32_minmax_scalar_params; f32_spmm_config.mr = 8 * hardware_config->vlenb / sizeof(float); f32_spmm_config.nr = 1; #elif XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->is_x86) { f32_spmm_config.ukernel = (xnn_spmm_ukernel_fn) xnn_f32_spmm_minmax_ukernel_32x1__wasmrelaxedsimd_x86; @@ -91,7 +91,7 @@ static void init_f32_spmm_config(void) { f32_spmm_config.nr = 1; } #elif XNN_ARCH_WASMSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->is_x86) { f32_spmm_config.ukernel = (xnn_spmm_ukernel_fn) xnn_f32_spmm_minmax_ukernel_32x1__wasmsimd_x86; @@ -119,7 +119,7 @@ static void init_f32_spmm_config(void) { static void init_f32_spmm2_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_spmm2_config.ukernel = (xnn_spmm_ukernel_fn) xnn_f32_spmm_minmax_ukernel_8x2__scalar; @@ -133,7 +133,7 @@ static void init_f32_spmm2_config(void) { f32_spmm2_config.mr = 32; f32_spmm2_config.nr = 2; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_spmm2_config.ukernel = (xnn_spmm_ukernel_fn) xnn_f32_spmm_minmax_ukernel_8vx2__rvv; f32_spmm2_config.init.f32 = xnn_init_f32_minmax_scalar_params; f32_spmm2_config.mr = 8 * hardware_config->vlenb / sizeof(float); @@ -158,7 +158,7 @@ static void init_f32_spmm4_config(void) { f32_spmm4_config.mr = 32; f32_spmm4_config.nr = 4; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_spmm4_config.ukernel = (xnn_spmm_ukernel_fn) xnn_f32_spmm_minmax_ukernel_4vx4__rvv; f32_spmm4_config.init.f32 = xnn_init_f32_minmax_scalar_params; f32_spmm4_config.mr = 4 * hardware_config->vlenb / sizeof(float); @@ -171,8 +171,8 @@ static void init_f32_spmm4_config(void) { #endif } -const struct xnn_spmm_config* xnn_init_f16_spmm_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_spmm_config* xnn_get_f16_spmm_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_chw_compatible_config(hardware_config)) { return NULL; } @@ -180,8 +180,8 @@ const struct xnn_spmm_config* xnn_init_f16_spmm_config() { return &f16_spmm_config; } -const struct xnn_spmm_config* xnn_init_f32_spmm_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_spmm_config* xnn_get_f32_spmm_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_chw_compatible_config(hardware_config)) { return NULL; } @@ -189,8 +189,8 @@ const struct xnn_spmm_config* xnn_init_f32_spmm_config() { return &f32_spmm_config; } -const struct xnn_spmm_config* xnn_init_f32_spmm2_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_spmm_config* xnn_get_f32_spmm2_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_chw_compatible_config(hardware_config)) { return NULL; } @@ -198,8 +198,8 @@ const struct xnn_spmm_config* xnn_init_f32_spmm2_config() { return &f32_spmm2_config; } -const struct xnn_spmm_config* xnn_init_f32_spmm4_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_spmm_config* xnn_get_f32_spmm4_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_chw_compatible_config(hardware_config)) { return NULL; } diff --git a/src/configs/transpose-config.c b/src/configs/transpose-config.c index e19275d24db..82f53ab4233 100644 --- a/src/configs/transpose-config.c +++ b/src/configs/transpose-config.c @@ -20,7 +20,7 @@ XNN_INIT_ONCE_GUARD(transpose); static void init_transpose_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { @@ -103,7 +103,7 @@ static void init_transpose_config(void) { .tile_size = 32, }; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); transpose_config.copy = (xnn_vunary_ukernel_fn) xnn_xx_copy_ukernel__scalar_memcpy; @@ -198,7 +198,7 @@ static void init_transpose_config(void) { .tile_size = 32, }; #if XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->vlenb >= 128) { transpose_config.x32 = (struct xnn_transpose_subconfig) { @@ -248,8 +248,8 @@ static void init_transpose_config(void) { #endif } -const struct xnn_transpose_config* xnn_init_transpose_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_transpose_config* xnn_get_transpose_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/unary-elementwise-config.c b/src/configs/unary-elementwise-config.c index 3b74ad65567..aaf6d485247 100644 --- a/src/configs/unary-elementwise-config.c +++ b/src/configs/unary-elementwise-config.c @@ -143,13 +143,13 @@ XNN_INIT_ONCE_GUARD(xx_copy); static void init_f16_abs_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_abs_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vabs_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_abs_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vabs_ukernel__neonfp16arith_u16; @@ -162,7 +162,7 @@ static void init_f16_abs_config(void) { static void init_f16_approxgelu_config(void) { #if (XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR) || \ (XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR) - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_approxgelu_config.ukernel = (xnn_vunary_ukernel_fn)xnn_f16_vapproxgelu_ukernel__neonfp16arith_rational_6_4_div_u16; @@ -174,21 +174,21 @@ static void init_f16_approxgelu_config(void) { static void init_f16_clamp_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_clamp_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vclamp_ukernel__neonfp16arith_u16; f16_clamp_config.init = (xnn_init_unary_uparams_fn) xnn_init_f16_clamp_scalar_params; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_clamp_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vclamp_ukernel__neonfp16arith_u16; f16_clamp_config.init = (xnn_init_unary_uparams_fn) xnn_init_f16_clamp_scalar_params; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_f16c)) { f16_clamp_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vclamp_ukernel__f16c_u16; @@ -200,7 +200,7 @@ static void init_f16_clamp_config(void) { static void init_f16_cosine_config(void) { #if (XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR) || \ (XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR) - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_cosine_config.ukernel = (xnn_vunary_ukernel_fn)xnn_f16_vcos_ukernel__neonfp16arith_rational_3_2_div_u16; @@ -212,21 +212,21 @@ static void init_f16_cosine_config(void) { static void init_f16_elu_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_elu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_velu_ukernel__neonfp16arith_rr1_p3_u16; f16_elu_config.init = (xnn_init_unary_uparams_fn) xnn_init_f16_elu_scalar_params; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_elu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_velu_ukernel__neonfp16arith_rr1_p3_u16; f16_elu_config.init = (xnn_init_unary_uparams_fn) xnn_init_f16_elu_scalar_params; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { f16_elu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_velu_ukernel__avx2_rr1_p3_u16; @@ -238,7 +238,7 @@ static void init_f16_elu_config(void) { static void init_f16_exp_config(void) { #if (XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR) || \ (XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR) - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_exp_config.ukernel = (xnn_vunary_ukernel_fn)xnn_f16_vexp_ukernel__neonfp16arith_poly_3_u32; @@ -251,7 +251,7 @@ static void init_f16_exp_config(void) { static void init_f16_gelu_config(void) { #if (XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR) || \ (XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR) - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_gelu_config.ukernel = (xnn_vunary_ukernel_fn)xnn_f16_vgelu_ukernel__neonfp16arith_rational_6_4_div_u16; @@ -263,19 +263,19 @@ static void init_f16_gelu_config(void) { static void init_f16_hswish_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_hswish_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vhswish_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_hswish_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vhswish_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_f16c)) { f16_hswish_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vhswish_ukernel__f16c_u16; @@ -285,21 +285,21 @@ static void init_f16_hswish_config(void) { static void init_f16_lrelu_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vlrelu_ukernel__neonfp16arith_u16; f16_lrelu_config.init = (xnn_init_unary_uparams_fn) xnn_init_f16_lrelu_scalar_params; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vlrelu_ukernel__neonfp16arith_u16; f16_lrelu_config.init = (xnn_init_unary_uparams_fn) xnn_init_f16_lrelu_scalar_params; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_f16c)) { f16_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vlrelu_ukernel__f16c_u16; @@ -310,13 +310,13 @@ static void init_f16_lrelu_config(void) { static void init_f16_neg_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_neg_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vneg_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_neg_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vneg_ukernel__neonfp16arith_u16; @@ -328,19 +328,19 @@ static void init_f16_neg_config(void) { static void init_f16_rndd_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rndd_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrndd_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rndd_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrndd_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_f16c)) { f16_rndd_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrndd_ukernel__f16c_u16; @@ -350,19 +350,19 @@ static void init_f16_rndd_config(void) { static void init_f16_rndne_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rndne_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrndne_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rndne_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrndne_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_f16c)) { f16_rndne_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrndne_ukernel__f16c_u16; @@ -372,19 +372,19 @@ static void init_f16_rndne_config(void) { static void init_f16_rndu_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rndu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrndu_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rndu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrndu_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_f16c)) { f16_rndu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrndu_ukernel__f16c_u16; @@ -394,19 +394,19 @@ static void init_f16_rndu_config(void) { static void init_f16_rndz_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rndz_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrndz_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rndz_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrndz_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_f16c)) { f16_rndz_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrndz_ukernel__f16c_u16; @@ -416,19 +416,19 @@ static void init_f16_rndz_config(void) { static void init_f16_rsqrt_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rsqrt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrsqrt_ukernel__neonfp16arith_rsqrt_u16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_rsqrt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrsqrt_ukernel__neonfp16arith_rsqrt_u16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_f16c)) { f16_rsqrt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vrsqrt_ukernel__f16c_rsqrt_u32; @@ -438,19 +438,19 @@ static void init_f16_rsqrt_config(void) { static void init_f16_sigmoid_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_sigmoid_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vsigmoid_ukernel__neonfp16arith_rr2_p2_nr1recps_u16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_sigmoid_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vsigmoid_ukernel__neonfp16arith_rr2_p2_nr1fma_u32; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { f16_sigmoid_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vsigmoid_ukernel__avx2_rr1_p2_rcp_u32; @@ -461,7 +461,7 @@ static void init_f16_sigmoid_config(void) { static void init_f16_sine_config(void) { #if (XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR) || \ (XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR) - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_sine_config.ukernel = (xnn_vunary_ukernel_fn)xnn_f16_vsin_ukernel__neonfp16arith_rational_3_2_div_u16; @@ -473,19 +473,19 @@ static void init_f16_sine_config(void) { static void init_f16_sqr_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_sqr_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vsqr_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_sqr_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vsqr_ukernel__neonfp16arith_u16; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_f16c)) { f16_sqr_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vsqr_ukernel__f16c_u16; @@ -495,19 +495,19 @@ static void init_f16_sqr_config(void) { static void init_f16_sqrt_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_sqrt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vsqrt_ukernel__neonfp16arith_nr1fma1adj_u8; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_sqrt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vsqrt_ukernel__aarch64_neonfp16arith_sqrt_u8; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_f16c)) { f16_sqrt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vsqrt_ukernel__f16c_rsqrt_u32; @@ -517,19 +517,19 @@ static void init_f16_sqrt_config(void) { static void init_f16_tanh_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_tanh_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vtanh_ukernel__neonfp16arith_expm1minus_rr1_p3h2ts_nr1fma_u32; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_tanh_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vtanh_ukernel__aarch64_neonfp16arith_expm1minus_rr1_p3h2ts_div_u32; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_fma3)) { f16_tanh_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_vtanh_ukernel__fma3_polynomial_p19h9t2_u32; @@ -541,7 +541,7 @@ static void init_f16_tanh_config(void) { static void init_f16_to_f32_cvt_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16)) { @@ -555,7 +555,7 @@ static void init_f16_to_f32_cvt_config(void) { #elif XNN_ARCH_ARM64 f16_to_f32_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_f32_vcvt_ukernel__neonfp16_u16; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -589,7 +589,7 @@ static void init_f16_to_qu8_cvt_config(void) { static void init_f16_to_qs8_cvt_config(void) { #if (XNN_ARCH_ARM || XNN_ARCH_ARM64) && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_to_qs8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f16_qs8_vcvt_ukernel__neonfp16arith_u32; @@ -603,7 +603,7 @@ static void init_f16_to_qs8_cvt_config(void) { static void init_f32_abs_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_abs_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vabs_ukernel__neon_u8; @@ -613,7 +613,7 @@ static void init_f32_abs_config(void) { #elif XNN_ARCH_ARM64 f32_abs_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vabs_ukernel__neon_u8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -636,7 +636,7 @@ static void init_f32_abs_config(void) { static void init_f32_approxgelu_config_impl(struct xnn_unary_elementwise_config* config, bool consistent_arithmetic) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { if ((hardware_config->arch_flags & xnn_arch_arm_neon_fma)) { @@ -650,7 +650,7 @@ static void init_f32_approxgelu_config_impl(struct xnn_unary_elementwise_config* #elif XNN_ARCH_ARM64 config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vapproxgelu_ukernel__neon_rational_12_10_div_u8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -682,7 +682,7 @@ static void init_f32_approxgelu_config() { static void init_f32_clamp_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_clamp_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vclamp_ukernel__neon_u16; @@ -695,7 +695,7 @@ static void init_f32_clamp_config(void) { f32_clamp_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vclamp_ukernel__neon_u16; f32_clamp_config.init = (xnn_init_unary_uparams_fn) xnn_init_f32_clamp_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -727,7 +727,7 @@ static void init_f32_clamp_config(void) { static void init_f32_cosine_config_impl(struct xnn_unary_elementwise_config* config, bool consistent_arithmetic) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vcos_ukernel__neon_rational_5_4_div_u16; @@ -737,7 +737,7 @@ static void init_f32_cosine_config_impl(struct xnn_unary_elementwise_config* con #elif XNN_ARCH_ARM64 config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vcos_ukernel__neon_rational_5_4_div_u16; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -754,7 +754,7 @@ static void init_f32_cosine_config_impl(struct xnn_unary_elementwise_config* con config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vcos_ukernel__sse2fma_rational_5_4_div_u8; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->is_x86) { config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vcos_ukernel__wasmsimd_rational_5_4_div_u8; @@ -775,7 +775,7 @@ static void init_f32_cosine_config() { static void init_f32_elu_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { if ((hardware_config->arch_flags & xnn_arch_arm_neon_fma)) { @@ -793,7 +793,7 @@ static void init_f32_elu_config(void) { f32_elu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_velu_ukernel__neonfma_rr1_lut16_p3_u16; f32_elu_config.init = (xnn_init_unary_uparams_fn) xnn_init_f32_elu_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -816,7 +816,7 @@ static void init_f32_elu_config(void) { f32_elu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_velu_ukernel__wasmrelaxedsimd_fma_rr2_p6_u16; f32_elu_config.init = (xnn_init_unary_uparams_fn) xnn_init_f32_elu_scalar_params; #else - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->is_x86) { f32_elu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_velu_ukernel__wasmsimd_x86_rr2_p6_u16; @@ -837,7 +837,7 @@ static void init_f32_elu_config(void) { static void init_f32_gelu_config_impl(struct xnn_unary_elementwise_config* config, bool consistent_arithmetic) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { if ((hardware_config->arch_flags & xnn_arch_arm_neon_fma)) { @@ -851,7 +851,7 @@ static void init_f32_gelu_config_impl(struct xnn_unary_elementwise_config* confi #elif XNN_ARCH_ARM64 config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vgelu_ukernel__neon_rational_12_10_div_u8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -883,7 +883,7 @@ static void init_f32_gelu_config() { static void init_f32_hswish_config_impl(struct xnn_unary_elementwise_config* config, bool consistent_arithmetic) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vhswish_ukernel__neon_u16; @@ -893,7 +893,7 @@ static void init_f32_hswish_config_impl(struct xnn_unary_elementwise_config* con #elif XNN_ARCH_ARM64 config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vhswish_ukernel__neon_u16; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -931,7 +931,7 @@ static void init_f32_hswish_config() { static void init_f32_exp_config_impl(struct xnn_unary_elementwise_config* config, bool consistent_arithmetic) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { config->ukernel = (xnn_vunary_ukernel_fn)xnn_f32_vexp_ukernel__neon_rational_3_2_div_u16; @@ -941,7 +941,7 @@ static void init_f32_exp_config_impl(struct xnn_unary_elementwise_config* config #elif XNN_ARCH_ARM64 config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vexp_ukernel__neon_rational_3_2_div_u16; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -973,7 +973,7 @@ static void init_f32_exp_config() { static void init_f32_log_config_impl(struct xnn_unary_elementwise_config* config, bool consistent_arithmetic) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vlog_ukernel__neon_rational_3_3_div_u8; @@ -983,7 +983,7 @@ static void init_f32_log_config_impl(struct xnn_unary_elementwise_config* config #elif XNN_ARCH_ARM64 config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vlog_ukernel__neon_rational_3_3_div_u8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -1015,7 +1015,7 @@ static void init_f32_log_config() { static void init_f32_lrelu_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vlrelu_ukernel__neon_u8; @@ -1028,7 +1028,7 @@ static void init_f32_lrelu_config(void) { f32_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vlrelu_ukernel__neon_u8; f32_lrelu_config.init = (xnn_init_unary_uparams_fn) xnn_init_f32_lrelu_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -1047,7 +1047,7 @@ static void init_f32_lrelu_config(void) { f32_lrelu_config.init = (xnn_init_unary_uparams_fn) xnn_init_f32_lrelu_scalar_params; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ARCH_WASMRELAXEDSIMD if (hardware_config->is_x86) { @@ -1067,7 +1067,7 @@ static void init_f32_lrelu_config(void) { } #endif #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vlrelu_ukernel__rvv_u4v; f32_lrelu_config.init = (xnn_init_unary_uparams_fn) xnn_init_f32_lrelu_scalar_params; #else @@ -1078,7 +1078,7 @@ static void init_f32_lrelu_config(void) { static void init_f32_neg_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_neg_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vneg_ukernel__neon_u8; @@ -1088,7 +1088,7 @@ static void init_f32_neg_config(void) { #elif XNN_ARCH_ARM64 f32_neg_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vneg_ukernel__neon_u8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -1111,7 +1111,7 @@ static void init_f32_neg_config(void) { static void init_f32_rndd_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { if ((hardware_config->arch_flags & xnn_arch_arm_neon_v8)) { @@ -1125,7 +1125,7 @@ static void init_f32_rndd_config(void) { #elif XNN_ARCH_ARM64 f32_rndd_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndd_ukernel__neonv8_u8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -1144,7 +1144,7 @@ static void init_f32_rndd_config(void) { #elif XNN_ARCH_HEXAGON && XNN_ENABLE_HVX f32_rndd_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndd_ukernel__hvx_u128; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_rndd_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndd_ukernel__rvv_u4v; #else f32_rndd_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndd_ukernel__scalar_libm_u1; @@ -1153,7 +1153,7 @@ static void init_f32_rndd_config(void) { static void init_f32_rndne_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { if ((hardware_config->arch_flags & xnn_arch_arm_neon_v8)) { @@ -1167,7 +1167,7 @@ static void init_f32_rndne_config(void) { #elif XNN_ARCH_ARM64 f32_rndne_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndne_ukernel__neonv8_u8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -1186,7 +1186,7 @@ static void init_f32_rndne_config(void) { #elif XNN_ARCH_HEXAGON && XNN_ENABLE_HVX f32_rndne_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndne_ukernel__hvx_u128; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_rndne_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndne_ukernel__rvv_u4v; #else f32_rndne_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndne_ukernel__scalar_libm_u1; @@ -1195,7 +1195,7 @@ static void init_f32_rndne_config(void) { static void init_f32_rndu_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { if ((hardware_config->arch_flags & xnn_arch_arm_neon_v8)) { @@ -1209,7 +1209,7 @@ static void init_f32_rndu_config(void) { #elif XNN_ARCH_ARM64 f32_rndu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndu_ukernel__neonv8_u8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -1228,7 +1228,7 @@ static void init_f32_rndu_config(void) { #elif XNN_ARCH_HEXAGON && XNN_ENABLE_HVX f32_rndu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndu_ukernel__hvx_u128; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_rndu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndu_ukernel__rvv_u4v; #else f32_rndu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndu_ukernel__scalar_libm_u1; @@ -1237,7 +1237,7 @@ static void init_f32_rndu_config(void) { static void init_f32_rndz_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { if ((hardware_config->arch_flags & xnn_arch_arm_neon_v8)) { @@ -1251,7 +1251,7 @@ static void init_f32_rndz_config(void) { #elif XNN_ARCH_ARM64 f32_rndz_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndz_ukernel__neonv8_u8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -1270,7 +1270,7 @@ static void init_f32_rndz_config(void) { #elif XNN_ARCH_HEXAGON && XNN_ENABLE_HVX f32_rndz_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndz_ukernel__hvx_u128; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_rndz_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndz_ukernel__rvv_u4v; #else f32_rndz_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrndz_ukernel__scalar_libm_u1; @@ -1279,7 +1279,7 @@ static void init_f32_rndz_config(void) { static void init_f32_sigmoid_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_sigmoid_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vsigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_u8; @@ -1289,7 +1289,7 @@ static void init_f32_sigmoid_config(void) { #elif XNN_ARCH_ARM64 f32_sigmoid_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vsigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_u16; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -1318,7 +1318,7 @@ static void init_f32_sigmoid_config(void) { static void init_f32_sqr_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_sqr_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vsqr_ukernel__neon_u8; @@ -1328,7 +1328,7 @@ static void init_f32_sqr_config(void) { #elif XNN_ARCH_ARM64 f32_sqr_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vsqr_ukernel__neon_u8; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -1353,7 +1353,7 @@ static void init_f32_sqrt_config_impl(struct xnn_unary_elementwise_config* confi #if XNN_ARCH_ARM64 config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vsqrt_ukernel__aarch64_neon_sqrt_u4; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (!consistent_arithmetic) { #if XNN_ENABLE_AVX512F @@ -1387,7 +1387,7 @@ static void init_f32_sqrt_config() { static void init_f32_rsqrt_config_impl(struct xnn_unary_elementwise_config* config, bool consistent_arithmetic) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrsqrt_ukernel__neon_rsqrt_u16; @@ -1395,7 +1395,7 @@ static void init_f32_rsqrt_config_impl(struct xnn_unary_elementwise_config* conf config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrsqrt_ukernel__scalar_rsqrt_u1; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (!consistent_arithmetic) { #if XNN_ENABLE_AVX512F @@ -1421,7 +1421,7 @@ static void init_f32_rsqrt_config_impl(struct xnn_unary_elementwise_config* conf } } #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vrsqrt_ukernel__rvv_rsqrt_u4v; #else config->ukernel = @@ -1436,7 +1436,7 @@ static void init_f32_rsqrt_config() { static void init_f32_sine_config_impl(struct xnn_unary_elementwise_config* config, bool consistent_arithmetic) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vsin_ukernel__neon_rational_5_4_div_u16; @@ -1446,7 +1446,7 @@ static void init_f32_sine_config_impl(struct xnn_unary_elementwise_config* confi #elif XNN_ARCH_ARM64 config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vsin_ukernel__neon_rational_5_4_div_u16; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -1463,7 +1463,7 @@ static void init_f32_sine_config_impl(struct xnn_unary_elementwise_config* confi config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vsin_ukernel__sse2fma_rational_5_4_div_u8; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->is_x86) { config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vsin_ukernel__wasmsimd_rational_5_4_div_u8; @@ -1484,7 +1484,7 @@ static void init_f32_sine_config() { static void init_f32_tanh_config_impl(struct xnn_unary_elementwise_config* config, bool consistent_arithmetic) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vtanh_ukernel__neon_rational_9_8_div_u16; @@ -1494,7 +1494,7 @@ static void init_f32_tanh_config_impl(struct xnn_unary_elementwise_config* confi #elif XNN_ARCH_ARM64 config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vtanh_ukernel__neon_rational_9_8_div_u16; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512F if ((hardware_config->arch_flags & xnn_arch_x86_avx512f)) { @@ -1511,7 +1511,7 @@ static void init_f32_tanh_config_impl(struct xnn_unary_elementwise_config* confi config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vtanh_ukernel__sse2fma_rational_9_8_div_u8; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->is_x86) { config->ukernel = (xnn_vunary_ukernel_fn) xnn_f32_vtanh_ukernel__wasmsimd_rational_9_8_div_u8; @@ -1532,7 +1532,7 @@ static void init_f32_tanh_config() { static void init_f32_to_f16_cvt_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16)) { @@ -1546,7 +1546,7 @@ static void init_f32_to_f16_cvt_config(void) { #elif XNN_ARCH_ARM64 f32_to_f16_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_f16_vcvt_ukernel__neonfp16_u16; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -1585,7 +1585,7 @@ static void init_f32_to_qp8_cvt_config(void) { static void init_f32_to_qs8_cvt_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { if ((hardware_config->arch_flags & xnn_arch_arm_neon_v8)) { @@ -1603,7 +1603,7 @@ static void init_f32_to_qs8_cvt_config(void) { f32_to_qs8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_qs8_vcvt_ukernel__neonv8_u32; f32_to_qs8_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_f32_qs8_cvt_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -1628,7 +1628,7 @@ static void init_f32_to_qs8_cvt_config(void) { f32_to_qs8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_qs8_vcvt_ukernel__wasmsimd_magic_u32; f32_to_qs8_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_f32_qs8_cvt_scalar_params; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_to_qs8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_qs8_vcvt_ukernel__rvv_u2v; f32_to_qs8_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_f32_qs8_cvt_scalar_params; #elif XNN_ARCH_HEXAGON && XNN_ENABLE_HVX @@ -1642,7 +1642,7 @@ static void init_f32_to_qs8_cvt_config(void) { static void init_f32_to_qu8_cvt_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { if ((hardware_config->arch_flags & xnn_arch_arm_neon_v8)) { @@ -1660,7 +1660,7 @@ static void init_f32_to_qu8_cvt_config(void) { f32_to_qu8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_qu8_vcvt_ukernel__neonv8_u32; f32_to_qu8_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_f32_qu8_cvt_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -1682,7 +1682,7 @@ static void init_f32_to_qu8_cvt_config(void) { f32_to_qu8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_qu8_vcvt_ukernel__wasmsimd_magic_u32; f32_to_qu8_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_f32_qu8_cvt_scalar_params; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); f32_to_qu8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_f32_qu8_vcvt_ukernel__rvv_u2v; f32_to_qu8_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_f32_qu8_cvt_scalar_params; #else @@ -1693,7 +1693,7 @@ static void init_f32_to_qu8_cvt_config(void) { static void init_qs8_cvt_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_v8)) { qs8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_vcvt_ukernel__neon_u32; @@ -1706,7 +1706,7 @@ static void init_qs8_cvt_config(void) { qs8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_vcvt_ukernel__neon_u32; qs8_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_qs8_cvt_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { qs8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_vcvt_ukernel__avx2_u32; @@ -1743,7 +1743,7 @@ static void init_qs8_cvt_config(void) { static void init_qs8_lrelu_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { qs8_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_vlrelu_ukernel__neon_u32; @@ -1756,7 +1756,7 @@ static void init_qs8_lrelu_config(void) { qs8_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_vlrelu_ukernel__neon_u32; qs8_lrelu_config.init = (xnn_init_unary_uparams_fn) xnn_init_qs8_lrelu_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { qs8_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_vlrelu_ukernel__avx2_u32; @@ -1775,7 +1775,7 @@ static void init_qs8_lrelu_config(void) { qs8_lrelu_config.init = (xnn_init_unary_uparams_fn) xnn_init_qs8_lrelu_scalar_params; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ARCH_WASMRELAXEDSIMD if (hardware_config->is_x86) { @@ -1795,7 +1795,7 @@ static void init_qs8_lrelu_config(void) { } #endif #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qs8_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_vlrelu_ukernel__rvv_u2v; qs8_lrelu_config.init = (xnn_init_unary_uparams_fn) xnn_init_qs8_lrelu_scalar_params; #else @@ -1806,14 +1806,14 @@ static void init_qs8_lrelu_config(void) { static void init_qs8_to_f16_cvt_config(void) { #if (XNN_ARCH_ARM || XNN_ARCH_ARM64) && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { qs8_to_f16_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_f16_vcvt_ukernel__neonfp16arith_u32; qs8_to_f16_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_qs8_f16_cvt_scalar_params; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { qs8_to_f16_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_f16_vcvt_ukernel__avx2_u16; @@ -1824,7 +1824,7 @@ static void init_qs8_to_f16_cvt_config(void) { static void init_qs8_to_f32_cvt_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { qs8_to_f32_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_f32_vcvt_ukernel__neon_u32; @@ -1837,7 +1837,7 @@ static void init_qs8_to_f32_cvt_config(void) { qs8_to_f32_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_f32_vcvt_ukernel__neon_u32; qs8_to_f32_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_qs8_f32_cvt_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -1862,7 +1862,7 @@ static void init_qs8_to_f32_cvt_config(void) { qs8_to_f32_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_f32_vcvt_ukernel__wasmsimd_u32; qs8_to_f32_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_qs8_f32_cvt_scalar_params; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qs8_to_f32_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qs8_f32_vcvt_ukernel__rvv_u2v; qs8_to_f32_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_qs8_f32_cvt_scalar_params; #else @@ -1873,7 +1873,7 @@ static void init_qs8_to_f32_cvt_config(void) { static void init_qu8_cvt_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { qu8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qu8_vcvt_ukernel__neon_u32; @@ -1886,7 +1886,7 @@ static void init_qu8_cvt_config(void) { qu8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qu8_vcvt_ukernel__neon_u32; qu8_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_qu8_cvt_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { qu8_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qu8_vcvt_ukernel__avx2_u32; @@ -1923,7 +1923,7 @@ static void init_qu8_cvt_config(void) { static void init_qu8_lrelu_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { qu8_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qu8_vlrelu_ukernel__neon_u32; @@ -1936,7 +1936,7 @@ static void init_qu8_lrelu_config(void) { qu8_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qu8_vlrelu_ukernel__neon_u32; qu8_lrelu_config.init = (xnn_init_unary_uparams_fn) xnn_init_qu8_lrelu_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { qu8_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qu8_vlrelu_ukernel__avx2_u32; @@ -1955,7 +1955,7 @@ static void init_qu8_lrelu_config(void) { qu8_lrelu_config.init = (xnn_init_unary_uparams_fn) xnn_init_qu8_lrelu_scalar_params; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ARCH_WASMRELAXEDSIMD if (hardware_config->is_x86) { @@ -1975,7 +1975,7 @@ static void init_qu8_lrelu_config(void) { } #endif #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qu8_lrelu_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qu8_vlrelu_ukernel__rvv_u2v; qu8_lrelu_config.init = (xnn_init_unary_uparams_fn) xnn_init_qu8_lrelu_scalar_params; #else @@ -1986,7 +1986,7 @@ static void init_qu8_lrelu_config(void) { static void init_qu8_to_f32_cvt_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { qu8_to_f32_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qu8_f32_vcvt_ukernel__neon_u32; @@ -1999,7 +1999,7 @@ static void init_qu8_to_f32_cvt_config(void) { qu8_to_f32_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qu8_f32_vcvt_ukernel__neon_u32; qu8_to_f32_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_qu8_f32_cvt_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -2024,7 +2024,7 @@ static void init_qu8_to_f32_cvt_config(void) { qu8_to_f32_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qu8_f32_vcvt_ukernel__wasmsimd_u32; qu8_to_f32_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_qu8_f32_cvt_scalar_params; #elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); qu8_to_f32_cvt_config.ukernel = (xnn_vunary_ukernel_fn) xnn_qu8_f32_vcvt_ukernel__rvv_u2v; qu8_to_f32_cvt_config.init = (xnn_init_unary_uparams_fn) xnn_init_qu8_f32_cvt_scalar_params; #else @@ -2035,7 +2035,7 @@ static void init_qu8_to_f32_cvt_config(void) { static void init_s8_clamp_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { s8_clamp_config.ukernel = (xnn_vunary_ukernel_fn) xnn_s8_vclamp_ukernel__neon_u64; @@ -2052,7 +2052,7 @@ static void init_s8_clamp_config(void) { s8_clamp_config.ukernel = (xnn_vunary_ukernel_fn) xnn_s8_vclamp_ukernel__rvv_u4v; s8_clamp_config.init = (xnn_init_unary_uparams_fn) xnn_init_qs8_clamp_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -2081,7 +2081,7 @@ static void init_s8_clamp_config(void) { static void init_u8_clamp_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { u8_clamp_config.ukernel = (xnn_vunary_ukernel_fn) xnn_u8_vclamp_ukernel__neon_u64; @@ -2097,7 +2097,7 @@ static void init_u8_clamp_config(void) { u8_clamp_config.ukernel = (xnn_vunary_ukernel_fn) xnn_u8_vclamp_ukernel__rvv_u4v; u8_clamp_config.init = (xnn_init_unary_uparams_fn) xnn_init_qu8_clamp_scalar_params; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX512SKX if ((hardware_config->arch_flags & xnn_arch_x86_avx512skx)) { @@ -2138,8 +2138,8 @@ static void init_xx_copy_config(void) { #endif } -const struct xnn_unary_elementwise_config* xnn_init_f16_abs_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_abs_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2147,8 +2147,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_abs_config() { return &f16_abs_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_approxgelu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_approxgelu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2156,8 +2156,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_approxgelu_config() { return &f16_approxgelu_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_clamp_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_clamp_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2165,8 +2165,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_clamp_config() { return &f16_clamp_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_cosine_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_cosine_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2174,8 +2174,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_cosine_config() { return &f16_cosine_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_elu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_elu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2183,8 +2183,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_elu_config() { return &f16_elu_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_exp_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_exp_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2192,8 +2192,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_exp_config() { return &f16_exp_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_gelu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_gelu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2201,8 +2201,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_gelu_config() { return &f16_gelu_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_hswish_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_hswish_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2210,8 +2210,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_hswish_config() { return &f16_hswish_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_lrelu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_lrelu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2219,8 +2219,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_lrelu_config() { return &f16_lrelu_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_neg_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_neg_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2228,8 +2228,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_neg_config() { return &f16_neg_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_rndd_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_rndd_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2237,8 +2237,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_rndd_config() { return &f16_rndd_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_rndne_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_rndne_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2246,8 +2246,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_rndne_config() { return &f16_rndne_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_rndu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_rndu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2255,8 +2255,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_rndu_config() { return &f16_rndu_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_rndz_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_rndz_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2264,8 +2264,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_rndz_config() { return &f16_rndz_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_rsqrt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_rsqrt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2273,8 +2273,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_rsqrt_config() { return &f16_rsqrt_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_sigmoid_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_sigmoid_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2282,8 +2282,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_sigmoid_config() { return &f16_sigmoid_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_sine_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_sine_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2291,8 +2291,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_sine_config() { return &f16_sine_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_sqr_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_sqr_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2300,8 +2300,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_sqr_config() { return &f16_sqr_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_sqrt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_sqrt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2309,8 +2309,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_sqrt_config() { return &f16_sqrt_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_tanh_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_tanh_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2318,8 +2318,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_tanh_config() { return &f16_tanh_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_to_f32_cvt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_to_f32_cvt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2327,8 +2327,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_to_f32_cvt_config() { return &f16_to_f32_cvt_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_to_qu8_cvt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_to_qu8_cvt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2336,8 +2336,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_to_qu8_cvt_config() { return &f16_to_qu8_cvt_config; } -const struct xnn_unary_elementwise_config* xnn_init_f16_to_qs8_cvt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f16_to_qs8_cvt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2345,8 +2345,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f16_to_qs8_cvt_config() { return &f16_to_qs8_cvt_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_abs_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_abs_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2354,8 +2354,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_abs_config() { return &f32_abs_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_approxgelu_config(uint32_t flags) { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_approxgelu_config(uint32_t flags) { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2367,8 +2367,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_approxgelu_config(uint32 } } -const struct xnn_unary_elementwise_config* xnn_init_f32_clamp_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_clamp_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2376,8 +2376,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_clamp_config() { return &f32_clamp_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_elu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_elu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2385,8 +2385,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_elu_config() { return &f32_elu_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_exp_config(uint32_t flags) { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_exp_config(uint32_t flags) { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2398,8 +2398,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_exp_config(uint32_t flag } } -const struct xnn_unary_elementwise_config* xnn_init_f32_gelu_config(uint32_t flags) { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_gelu_config(uint32_t flags) { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2411,8 +2411,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_gelu_config(uint32_t fla } } -const struct xnn_unary_elementwise_config* xnn_init_f32_hswish_config(uint32_t flags) { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_hswish_config(uint32_t flags) { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2424,8 +2424,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_hswish_config(uint32_t f } } -const struct xnn_unary_elementwise_config* xnn_init_f32_log_config(uint32_t flags) { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_log_config(uint32_t flags) { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2437,8 +2437,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_log_config(uint32_t flag } } -const struct xnn_unary_elementwise_config* xnn_init_f32_lrelu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_lrelu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2446,8 +2446,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_lrelu_config() { return &f32_lrelu_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_neg_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_neg_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2455,8 +2455,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_neg_config() { return &f32_neg_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_rndd_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_rndd_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2464,8 +2464,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_rndd_config() { return &f32_rndd_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_rndne_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_rndne_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2473,8 +2473,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_rndne_config() { return &f32_rndne_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_rndu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_rndu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2482,8 +2482,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_rndu_config() { return &f32_rndu_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_rndz_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_rndz_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2491,9 +2491,9 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_rndz_config() { return &f32_rndz_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_rsqrt_config(uint32_t flags) { +const struct xnn_unary_elementwise_config* xnn_get_f32_rsqrt_config(uint32_t flags) { const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2505,8 +2505,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_rsqrt_config(uint32_t fl } } -const struct xnn_unary_elementwise_config* xnn_init_f32_sigmoid_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_sigmoid_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2514,8 +2514,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_sigmoid_config() { return &f32_sigmoid_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_sine_config(uint32_t flags) { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_sine_config(uint32_t flags) { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2527,8 +2527,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_sine_config(uint32_t fla } } -const struct xnn_unary_elementwise_config* xnn_init_f32_cosine_config(uint32_t flags) { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_cosine_config(uint32_t flags) { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2540,8 +2540,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_cosine_config(uint32_t f } } -const struct xnn_unary_elementwise_config* xnn_init_f32_sqr_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_sqr_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2549,8 +2549,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_sqr_config() { return &f32_sqr_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_sqrt_config(uint32_t flags) { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_sqrt_config(uint32_t flags) { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2562,8 +2562,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_sqrt_config(uint32_t fla } } -const struct xnn_unary_elementwise_config* xnn_init_f32_tanh_config(uint32_t flags) { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_tanh_config(uint32_t flags) { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2575,8 +2575,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_tanh_config(uint32_t fla } } -const struct xnn_unary_elementwise_config* xnn_init_f32_to_f16_cvt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_to_f16_cvt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2584,9 +2584,9 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_to_f16_cvt_config() { return &f32_to_f16_cvt_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_to_qp8_cvt_config() { +const struct xnn_unary_elementwise_config* xnn_get_f32_to_qp8_cvt_config() { const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2594,8 +2594,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_to_qp8_cvt_config() { return &f32_to_qp8_cvt_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_to_qs8_cvt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_to_qs8_cvt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2603,8 +2603,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_to_qs8_cvt_config() { return &f32_to_qs8_cvt_config; } -const struct xnn_unary_elementwise_config* xnn_init_f32_to_qu8_cvt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_f32_to_qu8_cvt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2612,8 +2612,8 @@ const struct xnn_unary_elementwise_config* xnn_init_f32_to_qu8_cvt_config() { return &f32_to_qu8_cvt_config; } -const struct xnn_unary_elementwise_config* xnn_init_qs8_cvt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_qs8_cvt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2621,8 +2621,8 @@ const struct xnn_unary_elementwise_config* xnn_init_qs8_cvt_config() { return &qs8_cvt_config; } -const struct xnn_unary_elementwise_config* xnn_init_qs8_lrelu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_qs8_lrelu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2630,8 +2630,8 @@ const struct xnn_unary_elementwise_config* xnn_init_qs8_lrelu_config() { return &qs8_lrelu_config; } -const struct xnn_unary_elementwise_config* xnn_init_qs8_to_f16_cvt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_qs8_to_f16_cvt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -2639,8 +2639,8 @@ const struct xnn_unary_elementwise_config* xnn_init_qs8_to_f16_cvt_config() { return &qs8_to_f16_cvt_config; } -const struct xnn_unary_elementwise_config* xnn_init_qs8_to_f32_cvt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_qs8_to_f32_cvt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2648,8 +2648,8 @@ const struct xnn_unary_elementwise_config* xnn_init_qs8_to_f32_cvt_config() { return &qs8_to_f32_cvt_config; } -const struct xnn_unary_elementwise_config* xnn_init_qu8_cvt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_qu8_cvt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2657,8 +2657,8 @@ const struct xnn_unary_elementwise_config* xnn_init_qu8_cvt_config() { return &qu8_cvt_config; } -const struct xnn_unary_elementwise_config* xnn_init_qu8_lrelu_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_qu8_lrelu_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2666,8 +2666,8 @@ const struct xnn_unary_elementwise_config* xnn_init_qu8_lrelu_config() { return &qu8_lrelu_config; } -const struct xnn_unary_elementwise_config* xnn_init_qu8_to_f32_cvt_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_qu8_to_f32_cvt_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2675,8 +2675,8 @@ const struct xnn_unary_elementwise_config* xnn_init_qu8_to_f32_cvt_config() { return &qu8_to_f32_cvt_config; } -const struct xnn_unary_elementwise_config* xnn_init_s8_clamp_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_s8_clamp_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2684,8 +2684,8 @@ const struct xnn_unary_elementwise_config* xnn_init_s8_clamp_config() { return &s8_clamp_config; } -const struct xnn_unary_elementwise_config* xnn_init_u8_clamp_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_u8_clamp_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } @@ -2693,8 +2693,8 @@ const struct xnn_unary_elementwise_config* xnn_init_u8_clamp_config() { return &u8_clamp_config; } -const struct xnn_unary_elementwise_config* xnn_init_xx_copy_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unary_elementwise_config* xnn_get_xx_copy_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/unpool-config.c b/src/configs/unpool-config.c index 4a9ce321250..826babebb49 100644 --- a/src/configs/unpool-config.c +++ b/src/configs/unpool-config.c @@ -18,7 +18,7 @@ XNN_INIT_ONCE_GUARD(x32_unpool); static void init_x32_unpool_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { x32_unpool_config.unpool = (xnn_unpool_ukernel_fn) xnn_x32_unpool_ukernel__neon; @@ -37,8 +37,8 @@ static void init_x32_unpool_config(void) { } -const struct xnn_unpool_config* xnn_init_x32_unpool_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_unpool_config* xnn_get_x32_unpool_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/vmulcaddc-config.c b/src/configs/vmulcaddc-config.c index 899af8783b3..483b3b11e87 100644 --- a/src/configs/vmulcaddc-config.c +++ b/src/configs/vmulcaddc-config.c @@ -21,7 +21,7 @@ XNN_INIT_ONCE_GUARD(f32_vmulcaddc); static void init_f16_vmulcaddc_config(void) { #if XNN_ARCH_ARM && XNN_ENABLE_ARM_FP16_VECTOR && XNN_ENABLE_ARM_FP16_SCALAR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vmulcaddc_config.ukernel = (xnn_vmulcaddc_ukernel_fn) xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x; @@ -30,7 +30,7 @@ static void init_f16_vmulcaddc_config(void) { f16_vmulcaddc_config.row_tile = 2; } #elif XNN_ARCH_ARM64 && XNN_ENABLE_ARM_FP16_VECTOR - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon_fp16_arith)) { f16_vmulcaddc_config.ukernel = (xnn_vmulcaddc_ukernel_fn) xnn_f16_vmulcaddc_minmax_ukernel_c8__neonfp16arith_2x; @@ -39,7 +39,7 @@ static void init_f16_vmulcaddc_config(void) { f16_vmulcaddc_config.row_tile = 2; } #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_x86_avx2)) { f16_vmulcaddc_config.ukernel = (xnn_vmulcaddc_ukernel_fn) xnn_f16_vmulcaddc_minmax_ukernel_c8__fma3_2x; @@ -52,7 +52,7 @@ static void init_f16_vmulcaddc_config(void) { static void init_f32_vmulcaddc_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { f32_vmulcaddc_config.ukernel = (xnn_vmulcaddc_ukernel_fn) xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x; @@ -82,7 +82,7 @@ static void init_f32_vmulcaddc_config(void) { f32_vmulcaddc_config.channel_tile = 4; f32_vmulcaddc_config.row_tile = 2; #else - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->is_x86) { f32_vmulcaddc_config.ukernel = (xnn_vmulcaddc_ukernel_fn) xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x; @@ -104,8 +104,8 @@ static void init_f32_vmulcaddc_config(void) { #endif } -const struct xnn_vmulcaddc_config* xnn_init_f16_vmulcaddc_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_vmulcaddc_config* xnn_get_f16_vmulcaddc_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL || !xnn_is_f16_compatible_config(hardware_config)) { return NULL; } @@ -113,8 +113,8 @@ const struct xnn_vmulcaddc_config* xnn_init_f16_vmulcaddc_config() { return &f16_vmulcaddc_config; } -const struct xnn_vmulcaddc_config* xnn_init_f32_vmulcaddc_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_vmulcaddc_config* xnn_get_f32_vmulcaddc_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/x8-lut-config.c b/src/configs/x8-lut-config.c index 6381319506a..4916d249859 100644 --- a/src/configs/x8-lut-config.c +++ b/src/configs/x8-lut-config.c @@ -22,7 +22,7 @@ static void init_x8_lut_config(void) { #elif XNN_ARCH_ARM64 x8_lut_config.microkernel = xnn_x8_lut_ukernel__aarch64_neon_tbx128x4_u64; #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); #if XNN_ENABLE_AVX256VBMI @@ -44,7 +44,7 @@ static void init_x8_lut_config(void) { x8_lut_config.microkernel = xnn_x8_lut_ukernel__scalar_u4; } #elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if (hardware_config->is_x86) { @@ -65,8 +65,8 @@ static void init_x8_lut_config(void) { #endif } -const struct xnn_x8_lut_config* xnn_init_x8_lut_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_x8_lut_config* xnn_get_x8_lut_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/xx-fill-config.c b/src/configs/xx-fill-config.c index f3ce3ad08ed..69035d949ed 100644 --- a/src/configs/xx-fill-config.c +++ b/src/configs/xx-fill-config.c @@ -18,7 +18,7 @@ XNN_INIT_ONCE_GUARD(xx_fill); static void init_xx_fill_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { xx_fill_config.ukernel = (xnn_fill_ukernel_fn) xnn_xx_fill_ukernel__neon_u64; @@ -38,8 +38,8 @@ static void init_xx_fill_config(void) { #endif } -const struct xnn_xx_fill_config* xnn_init_xx_fill_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_xx_fill_config* xnn_get_xx_fill_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/configs/xx-pad-config.c b/src/configs/xx-pad-config.c index 7c1e56a5d50..507513c80b2 100644 --- a/src/configs/xx-pad-config.c +++ b/src/configs/xx-pad-config.c @@ -18,7 +18,7 @@ XNN_INIT_ONCE_GUARD(xx_pad); static void init_xx_pad_config(void) { #if XNN_ARCH_ARM - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); assert(hardware_config != NULL); if ((hardware_config->arch_flags & xnn_arch_arm_neon)) { xx_pad_config.ukernel = (xnn_pad_ukernel_fn) xnn_xx_pad_ukernel_p16__neon_u16; @@ -36,8 +36,8 @@ static void init_xx_pad_config(void) { #endif } -const struct xnn_xx_pad_config* xnn_init_xx_pad_config() { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); +const struct xnn_xx_pad_config* xnn_get_xx_pad_config() { + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { return NULL; } diff --git a/src/f32-dwconv/f32-dwconv-minmax.inc b/src/f32-dwconv/f32-dwconv-minmax.inc index f8b59d5ed18..4e3caa96c43 100644 --- a/src/f32-dwconv/f32-dwconv-minmax.inc +++ b/src/f32-dwconv/f32-dwconv-minmax.inc @@ -223,10 +223,10 @@ XNN_UKERNEL(0, xnn_f32_dwconv_minmax_ukernel_25p8c__wasmrelaxedsimd_fma_acc2, 8, #endif // XNN_ARCH_WASMRELAXEDSIMD #if XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_minmax_ukernel_3p8vc__rvv, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), 3, float, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_minmax_ukernel_4p8vc__rvv, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), 4, float, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_minmax_ukernel_9p8vc__rvv, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), 9, float, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_minmax_ukernel_25p8vc__rvv, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), 25, float, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_minmax_ukernel_3p8vc__rvv, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), 3, float, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_minmax_ukernel_4p8vc__rvv, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), 4, float, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_minmax_ukernel_9p8vc__rvv, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), 9, float, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_minmax_ukernel_25p8vc__rvv, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), 25, float, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) #endif // XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR XNN_UKERNEL(0, xnn_f32_dwconv_minmax_ukernel_3p1c__scalar, 1, false, 1, 3, float, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) diff --git a/src/f32-dwconv/f32-dwconv.inc b/src/f32-dwconv/f32-dwconv.inc index 862910f33ec..234857f318f 100644 --- a/src/f32-dwconv/f32-dwconv.inc +++ b/src/f32-dwconv/f32-dwconv.inc @@ -32,10 +32,10 @@ XNN_UKERNEL(0, xnn_f32_dwconv_ukernel_25p8c__wasmrelaxedsimd_fma, 8, false, 8, 2 #endif // XNN_ARCH_WASMRELAXEDSIMD #if XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_ukernel_3p8vc__rvv, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), 3, float, float, struct xnn_f32_default_params, NULL) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_ukernel_4p8vc__rvv, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), 4, float, float, struct xnn_f32_default_params, NULL) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_ukernel_9p8vc__rvv, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), 9, float, float, struct xnn_f32_default_params, NULL) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_ukernel_25p8vc__rvv, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(float)), 25, float, float, struct xnn_f32_default_params, NULL) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_ukernel_3p8vc__rvv, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), 3, float, float, struct xnn_f32_default_params, NULL) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_ukernel_4p8vc__rvv, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), 4, float, float, struct xnn_f32_default_params, NULL) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_ukernel_9p8vc__rvv, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), 9, float, float, struct xnn_f32_default_params, NULL) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_dwconv_ukernel_25p8vc__rvv, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(float)), 25, float, float, struct xnn_f32_default_params, NULL) #endif // XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR XNN_UKERNEL(0, xnn_f32_dwconv_ukernel_3p1c__scalar, 1, false, 1, 3, float, float, struct xnn_f32_default_params, NULL) diff --git a/src/f32-maxpool/f32-maxpool-minmax.inc b/src/f32-maxpool/f32-maxpool-minmax.inc index 71d5fd010c7..6c095ae36e8 100644 --- a/src/f32-maxpool/f32-maxpool-minmax.inc +++ b/src/f32-maxpool/f32-maxpool-minmax.inc @@ -19,8 +19,8 @@ XNN_UKERNEL(0, xnn_f32_maxpool_minmax_ukernel_9p__wasmsimd_u4, 4, 9, float, stru #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD #if XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_maxpool_minmax_ukernel_9p__rvv_u1v, (1*xnn_init_hardware_config()->vlenb/sizeof(float)), 9, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_maxpool_minmax_ukernel_9p__rvv_u2v, (2*xnn_init_hardware_config()->vlenb/sizeof(float)), 9, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_maxpool_minmax_ukernel_9p__rvv_u1v, (1*xnn_get_hardware_config()->vlenb/sizeof(float)), 9, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_f32_maxpool_minmax_ukernel_9p__rvv_u2v, (2*xnn_get_hardware_config()->vlenb/sizeof(float)), 9, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) #endif // XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR XNN_UKERNEL(0, xnn_f32_maxpool_minmax_ukernel_9p__scalar_u1, 1, 9, float, struct xnn_f32_minmax_params, xnn_init_f32_minmax_scalar_params) diff --git a/src/init.c b/src/init.c index 07cc6a04001..c3e4a2a6926 100644 --- a/src/init.c +++ b/src/init.c @@ -45,7 +45,7 @@ static void init_allocator_config(void) { } enum xnn_status xnn_initialize(const struct xnn_allocator* allocator) { - const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config(); + const struct xnn_hardware_config* hardware_config = xnn_get_hardware_config(); if (hardware_config == NULL) { xnn_log_error("XNNPACK initialization failed: hardware not supported"); return xnn_status_unsupported_hardware; diff --git a/src/microkernel-utils.c b/src/microkernel-utils.c index d33b5d85571..b0e8e34eb3a 100644 --- a/src/microkernel-utils.c +++ b/src/microkernel-utils.c @@ -35,7 +35,7 @@ bool xnn_should_inline_lhs_packing(const struct xnn_gemm_config *gemm_config, size_t m_packed_stride, size_t n_stride, size_t cn_stride, size_t mc, size_t nc) { const struct xnn_hardware_config *hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); // Select which cache we want the tiles to fit in. const size_t cache_bytes = hardware_config->l2_data_cache_bytes; @@ -68,7 +68,7 @@ size_t xnn_gemm_best_tile_size(size_t num_groups, size_t m, size_t n, size_t cn_stride, size_t mr, size_t nr, size_t num_threads) { const struct xnn_hardware_config *hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); // Adjust `mr` and `nr` if they are larger than `m` and `n`, respectively. mr = min(mr, m); diff --git a/src/operators/argmax-pooling-nhwc.c b/src/operators/argmax-pooling-nhwc.c index ad2dd6ab4bc..7bd7870dee0 100644 --- a/src/operators/argmax-pooling-nhwc.c +++ b/src/operators/argmax-pooling-nhwc.c @@ -53,7 +53,7 @@ enum xnn_status xnn_create_argmax_pooling2d_nhwc_f32( status = xnn_status_unsupported_hardware; - const struct xnn_argmaxpool_config* argmaxpool_config = xnn_init_f32_argmaxpool_config(); + const struct xnn_argmaxpool_config* argmaxpool_config = xnn_get_f32_argmaxpool_config(); if (argmaxpool_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", diff --git a/src/operators/average-pooling-nhwc.c b/src/operators/average-pooling-nhwc.c index e094780bc1d..5acc65f81aa 100644 --- a/src/operators/average-pooling-nhwc.c +++ b/src/operators/average-pooling-nhwc.c @@ -182,7 +182,7 @@ enum xnn_status xnn_create_average_pooling2d_nhwc_f16( } status = xnn_status_unsupported_hardware; - const struct xnn_avgpool_config* avgpool_config = xnn_init_f16_avgpool_config(); + const struct xnn_avgpool_config* avgpool_config = xnn_get_f16_avgpool_config(); if (avgpool_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_average_pooling_nhwc_f16)); @@ -260,7 +260,7 @@ enum xnn_status xnn_create_average_pooling2d_nhwc_f32( if (status != xnn_status_success) { goto error; } - const struct xnn_avgpool_config* avgpool_config = xnn_init_f32_avgpool_config(); + const struct xnn_avgpool_config* avgpool_config = xnn_get_f32_avgpool_config(); status = xnn_status_unsupported_hardware; if (avgpool_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", diff --git a/src/operators/batch-matrix-multiply-nc.c b/src/operators/batch-matrix-multiply-nc.c index a5d6ca8e59f..90b7fdf2db1 100644 --- a/src/operators/batch-matrix-multiply-nc.c +++ b/src/operators/batch-matrix-multiply-nc.c @@ -132,7 +132,7 @@ enum xnn_status create_batch_matrix_multiply_nc( enum xnn_status xnn_create_batch_matrix_multiply_nc_f16( uint32_t flags, xnn_operator_t* batch_matrix_multiply_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -161,7 +161,7 @@ enum xnn_status xnn_create_batch_matrix_multiply_nc_f16( enum xnn_status xnn_create_batch_matrix_multiply_nc_pf16( uint32_t flags, xnn_operator_t* batch_matrix_multiply_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_pf16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_pf16_gemm_config(); if (gemm_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -190,7 +190,7 @@ enum xnn_status xnn_create_batch_matrix_multiply_nc_pf16( enum xnn_status xnn_create_batch_matrix_multiply_nc_bf16_f32( uint32_t flags, xnn_operator_t* batch_matrix_multiply_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_bf16_f32_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_bf16_f32_gemm_config(); if (gemm_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -218,7 +218,7 @@ enum xnn_status xnn_create_batch_matrix_multiply_nc_bf16_f32( enum xnn_status xnn_create_batch_matrix_multiply_nc_f32( uint32_t flags, xnn_operator_t* batch_matrix_multiply_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_gemm_config(flags); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_gemm_config(flags); if (gemm_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -246,7 +246,7 @@ enum xnn_status xnn_create_batch_matrix_multiply_nc_f32( enum xnn_status xnn_create_batch_matrix_multiply_nc_pf32( uint32_t flags, xnn_operator_t* batch_matrix_multiply_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_pf32_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_pf32_gemm_config(); if (gemm_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -601,7 +601,7 @@ enum xnn_status xnn_create_batch_matrix_multiply_nc_qd8_f32_qc8w( const float* scale_b, uint32_t flags, xnn_operator_t* batch_matrix_multiply_op_out) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); return create_batch_matrix_multiply_nc_qx8_f32_qc8w( batch_size_b, k, n, data_b, scale_b, flags, gemm_config, xnn_operator_type_batch_matrix_multiply_nc_qd8_f32_qc8w, @@ -613,7 +613,7 @@ enum xnn_status xnn_create_batch_matrix_multiply_nc_qp8_f32_qc8w( const float* scale_b, uint32_t flags, xnn_operator_t* batch_matrix_multiply_op_out) { const struct xnn_gemm_config* gemm_config = - xnn_init_qp8_f32_qc8w_gemm_config(); + xnn_get_qp8_f32_qc8w_gemm_config(); return create_batch_matrix_multiply_nc_qx8_f32_qc8w( batch_size_b, k, n, data_b, scale_b, flags, gemm_config, xnn_operator_type_batch_matrix_multiply_nc_qp8_f32_qc8w, @@ -625,7 +625,7 @@ enum xnn_status xnn_create_batch_matrix_multiply_nc_qdu8_f32_qc8w( const float* scale_b, uint32_t flags, xnn_operator_t* batch_matrix_multiply_op_out) { const struct xnn_gemm_config* gemm_config = - xnn_init_qdu8_f32_qc8w_gemm_config(); + xnn_get_qdu8_f32_qc8w_gemm_config(); return create_batch_matrix_multiply_nc_qx8_f32_qc8w( batch_size_b, k, n, data_b, scale_b, flags, gemm_config, xnn_operator_type_batch_matrix_multiply_nc_qdu8_f32_qc8w, @@ -849,22 +849,22 @@ static enum xnn_status reshape_batch_matrix_multiply_nc( switch (batch_matrix_multiply_op->type) { case xnn_operator_type_batch_matrix_multiply_nc_qd8_f32_qc8w: if (inline_lhs_packing) { - packed_lh_config = xnn_init_f32_qdint8_pack_lh_config(); + packed_lh_config = xnn_get_f32_qdint8_pack_lh_config(); } break; case xnn_operator_type_batch_matrix_multiply_nc_qdu8_f32_qc8w: if (inline_lhs_packing) { - packed_lh_config = xnn_init_f32_qduint8_pack_lh_config(); + packed_lh_config = xnn_get_f32_qduint8_pack_lh_config(); } break; case xnn_operator_type_batch_matrix_multiply_nc_qp8_f32_qc8w: - packed_lh_config = xnn_init_qp8_pack_lh_config(); + packed_lh_config = xnn_get_qp8_pack_lh_config(); break; case xnn_operator_type_batch_matrix_multiply_nc_pf16: - packed_lh_config = xnn_init_x16_pack_lh_config(); + packed_lh_config = xnn_get_x16_pack_lh_config(); break; case xnn_operator_type_batch_matrix_multiply_nc_pf32: - packed_lh_config = xnn_init_x32_pack_lh_config(); + packed_lh_config = xnn_get_x32_pack_lh_config(); break; default: break; diff --git a/src/operators/binary-elementwise-nd.c b/src/operators/binary-elementwise-nd.c index f0089fafe31..f5660175be4 100644 --- a/src/operators/binary-elementwise-nd.c +++ b/src/operators/binary-elementwise-nd.c @@ -32,97 +32,97 @@ static const struct xnn_binary_elementwise_config* init_config( case xnn_binary_add: switch (datatype) { case xnn_datatype_fp32: - return xnn_init_f32_vadd_config(); + return xnn_get_f32_vadd_config(); case xnn_datatype_fp16: - return xnn_init_f16_vadd_config(); + return xnn_get_f16_vadd_config(); case xnn_datatype_qint8: - return xnn_init_qs8_vadd_config(); + return xnn_get_qs8_vadd_config(); case xnn_datatype_quint8: - return xnn_init_qu8_vadd_config(); + return xnn_get_qu8_vadd_config(); default: return NULL; } case xnn_binary_subtract: switch (datatype) { case xnn_datatype_fp32: - return xnn_init_f32_vsub_config(); + return xnn_get_f32_vsub_config(); case xnn_datatype_fp16: - return xnn_init_f16_vsub_config(); + return xnn_get_f16_vsub_config(); case xnn_datatype_qint8: *sign_b = -1; - return xnn_init_qs8_vadd_config(); + return xnn_get_qs8_vadd_config(); case xnn_datatype_quint8: *sign_b = -1; - return xnn_init_qu8_vadd_config(); + return xnn_get_qu8_vadd_config(); default: return NULL; } case xnn_binary_multiply: switch (datatype) { case xnn_datatype_fp32: - return xnn_init_f32_vmul_config(); + return xnn_get_f32_vmul_config(); case xnn_datatype_fp16: - return xnn_init_f16_vmul_config(); + return xnn_get_f16_vmul_config(); case xnn_datatype_qint8: - return xnn_init_qs8_vmul_config(); + return xnn_get_qs8_vmul_config(); case xnn_datatype_quint8: - return xnn_init_qu8_vmul_config(); + return xnn_get_qu8_vmul_config(); default: return NULL; } case xnn_binary_divide: switch (datatype) { case xnn_datatype_fp32: - return xnn_init_f32_vdiv_config(); + return xnn_get_f32_vdiv_config(); case xnn_datatype_fp16: - return xnn_init_f16_vdiv_config(); + return xnn_get_f16_vdiv_config(); default: return NULL; } case xnn_binary_maximum: switch (datatype) { case xnn_datatype_fp32: - return xnn_init_f32_vmax_config(); + return xnn_get_f32_vmax_config(); case xnn_datatype_fp16: - return xnn_init_f16_vmax_config(); + return xnn_get_f16_vmax_config(); default: return NULL; } case xnn_binary_minimum: switch (datatype) { case xnn_datatype_fp32: - return xnn_init_f32_vmin_config(); + return xnn_get_f32_vmin_config(); case xnn_datatype_fp16: - return xnn_init_f16_vmin_config(); + return xnn_get_f16_vmin_config(); default: return NULL; } case xnn_binary_copysign: switch (datatype) { case xnn_datatype_fp32: - return xnn_init_f32_vcopysign_config(); + return xnn_get_f32_vcopysign_config(); default: return NULL; } case xnn_binary_squared_difference: switch (datatype) { case xnn_datatype_fp32: - return xnn_init_f32_vsqrdiff_config(); + return xnn_get_f32_vsqrdiff_config(); case xnn_datatype_fp16: - return xnn_init_f16_vsqrdiff_config(); + return xnn_get_f16_vsqrdiff_config(); default: return NULL; } case xnn_binary_prelu: switch (datatype) { case xnn_datatype_fp32: - return xnn_init_f32_vprelu_config(); + return xnn_get_f32_vprelu_config(); case xnn_datatype_fp16: - return xnn_init_f16_vprelu_config(); + return xnn_get_f16_vprelu_config(); case xnn_datatype_qint8: - return xnn_init_qs8_vprelu_config(); + return xnn_get_qs8_vprelu_config(); case xnn_datatype_quint8: - return xnn_init_qu8_vprelu_config(); + return xnn_get_qu8_vprelu_config(); default: return NULL; } @@ -147,7 +147,7 @@ static enum xnn_status init_binary_elementwise_nd( xnn_log_debug( "unsupported operator %s for datatype %s, falling back to reference kernel", xnn_binary_operator_to_string(type), xnn_datatype_to_string(datatype)); - config = xnn_init_binary_reference_config(type, datatype); + config = xnn_get_binary_reference_config(type, datatype); } if (config == NULL) { xnn_log_error( diff --git a/src/operators/constant-pad-nd.c b/src/operators/constant-pad-nd.c index b19899d9254..fa2b7e0ea2e 100644 --- a/src/operators/constant-pad-nd.c +++ b/src/operators/constant-pad-nd.c @@ -83,14 +83,14 @@ static enum xnn_status create_constant_pad_nd( status = xnn_status_unsupported_hardware; - const struct xnn_xx_fill_config* fill_config = xnn_init_xx_fill_config(); + const struct xnn_xx_fill_config* fill_config = xnn_get_xx_fill_config(); if (fill_config == NULL) { xnn_log_error( "failed to create fill operator: unsupported hardware configuration"); goto error; } - const struct xnn_xx_pad_config* pad_config = xnn_init_xx_pad_config(); + const struct xnn_xx_pad_config* pad_config = xnn_get_xx_pad_config(); if (pad_config == NULL) { xnn_log_error( "failed to create pad operator: unsupported hardware configuration"); @@ -392,14 +392,14 @@ enum xnn_status run_constant_pad_nd( memset(&pad_context, 0, sizeof(pad_context)); constant_pad_op.dynamic_context.pad = &pad_context; - const struct xnn_xx_fill_config* fill_config = xnn_init_xx_fill_config(); + const struct xnn_xx_fill_config* fill_config = xnn_get_xx_fill_config(); if (fill_config == NULL) { xnn_log_error( "failed to create fill operator: unsupported hardware configuration"); return xnn_status_unsupported_hardware; } - const struct xnn_xx_pad_config* pad_config = xnn_init_xx_pad_config(); + const struct xnn_xx_pad_config* pad_config = xnn_get_xx_pad_config(); if (pad_config == NULL) { xnn_log_error( "failed to create pad operator: unsupported hardware configuration"); diff --git a/src/operators/convolution-nchw.c b/src/operators/convolution-nchw.c index 05d6ef7650d..6f8e84ebe53 100644 --- a/src/operators/convolution-nchw.c +++ b/src/operators/convolution-nchw.c @@ -400,14 +400,14 @@ enum xnn_status xnn_create_convolution2d_nchw_f16( status = xnn_status_unsupported_hardware; - const struct xnn_spmm_config* spmm_config = xnn_init_f16_spmm_config(); + const struct xnn_spmm_config* spmm_config = xnn_get_f16_spmm_config(); if (spmm_config == NULL) { xnn_log_error("failed to create %s operator: operations on data type are not supported", xnn_operator_type_to_string(operator_type)); goto error; } - const struct xnn_dwconv2d_chw_config* dwconv2d_chw_config = xnn_init_f16_dwconv2d_chw_config(); + const struct xnn_dwconv2d_chw_config* dwconv2d_chw_config = xnn_get_f16_dwconv2d_chw_config(); if (dwconv2d_chw_config == NULL) { xnn_log_error("failed to create %s operator: operations on data type are not supported", xnn_operator_type_to_string(operator_type)); @@ -537,7 +537,7 @@ enum xnn_status xnn_create_convolution2d_nchw_f16( xnn_pack_dconv_oki_w = (xnn_pack_dconv_oki_w_fn) xnn_pack_f32_to_f16_dconv_oki_w; } - const struct xnn_conv_hwc2chw_config* conv_hwc2chw_config = xnn_init_f16_conv_hwc2chw_3x3c3s2_config(); + const struct xnn_conv_hwc2chw_config* conv_hwc2chw_config = xnn_get_f16_conv_hwc2chw_3x3c3s2_config(); if (conv_hwc2chw_config == NULL) { status = xnn_status_unsupported_hardware; xnn_log_error("failed to create %s operator: operations on data type are not supported", @@ -751,7 +751,7 @@ enum xnn_status xnn_create_convolution2d_nchw_f32( status = xnn_status_unsupported_hardware; - const struct xnn_dwconv2d_chw_config* dwconv2d_chw_config = xnn_init_f32_dwconv2d_chw_config(); + const struct xnn_dwconv2d_chw_config* dwconv2d_chw_config = xnn_get_f32_dwconv2d_chw_config(); if (dwconv2d_chw_config == NULL) { xnn_log_error("failed to create %s operator: operations on data type are not supported", xnn_operator_type_to_string(operator_type)); @@ -846,21 +846,21 @@ enum xnn_status xnn_create_convolution2d_nchw_f32( convolution_op->weights_cache = weights_cache; } - const struct xnn_spmm_config* spmm_config = xnn_init_f32_spmm_config(); + const struct xnn_spmm_config* spmm_config = xnn_get_f32_spmm_config(); if (spmm_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_convolution_nchw_f32)); return xnn_status_unsupported_hardware; } - const struct xnn_spmm_config* spmm2_config = xnn_init_f32_spmm2_config(); + const struct xnn_spmm_config* spmm2_config = xnn_get_f32_spmm2_config(); if (spmm2_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_convolution_nchw_f32)); return xnn_status_unsupported_hardware; } - const struct xnn_spmm_config* spmm4_config = xnn_init_f32_spmm4_config(); + const struct xnn_spmm_config* spmm4_config = xnn_get_f32_spmm4_config(); if (spmm4_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -890,7 +890,7 @@ enum xnn_status xnn_create_convolution2d_nchw_f32( } case xnn_microkernel_type_conv2d_hwc2chw: { - const struct xnn_conv_hwc2chw_config* conv_hwc2chw_config = xnn_init_f32_conv_hwc2chw_3x3c3s2_config(); + const struct xnn_conv_hwc2chw_config* conv_hwc2chw_config = xnn_get_f32_conv_hwc2chw_3x3c3s2_config(); if (conv_hwc2chw_config == NULL) { status = xnn_status_unsupported_hardware; xnn_log_error("failed to create %s operator: operations on data type are not supported", diff --git a/src/operators/convolution-nhwc.c b/src/operators/convolution-nhwc.c index 00a1e2473b4..2ea253abf40 100644 --- a/src/operators/convolution-nhwc.c +++ b/src/operators/convolution-nhwc.c @@ -842,7 +842,7 @@ enum xnn_status xnn_create_convolution2d_nhwc_qd8_f16_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* convolution_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qd8_f16_qc8w_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qd8_f16_qc8w_igemm_config(); return create_convolution2d_nhwc_qx8_f16_qc8w(input_padding_top, input_padding_right, input_padding_bottom, input_padding_left, kernel_height, kernel_width, subsampling_height, subsampling_width, dilation_height, dilation_width, groups, group_input_channels, group_output_channels, input_channel_stride, output_channel_stride, @@ -875,7 +875,7 @@ enum xnn_status xnn_create_convolution2d_nhwc_qdu8_f16_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* convolution_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qdu8_f16_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qdu8_f16_qc8w_gemm_config(); return create_convolution2d_nhwc_qx8_f16_qc8w(input_padding_top, input_padding_right, input_padding_bottom, input_padding_left, kernel_height, kernel_width, subsampling_height, subsampling_width, dilation_height, dilation_width, groups, group_input_channels, group_output_channels, input_channel_stride, output_channel_stride, @@ -1002,7 +1002,7 @@ enum xnn_status xnn_create_convolution2d_nhwc_qd8_f32_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* convolution_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qd8_f32_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qd8_f32_qc8w_gemm_config(); return create_convolution2d_nhwc_qx8_f32_qc8w(input_padding_top, input_padding_right, input_padding_bottom, @@ -1038,7 +1038,7 @@ enum xnn_status xnn_create_convolution2d_nhwc_qdu8_f32_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* convolution_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qdu8_f32_qc8w_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qdu8_f32_qc8w_igemm_config(); return create_convolution2d_nhwc_qx8_f32_qc8w(input_padding_top, input_padding_right, input_padding_bottom, @@ -1122,7 +1122,7 @@ enum xnn_status xnn_create_convolution2d_nhwc_qu8( .kernel_zero_point = kernel_zero_point, }; - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); assert(gemm_config != NULL); union xnn_qu8_conv_minmax_params gemm_params; @@ -1131,7 +1131,7 @@ enum xnn_status xnn_create_convolution2d_nhwc_qu8( kernel_zero_point, requantization_scale, output_zero_point, output_min, output_max); } - const struct xnn_dwconv_config* dwconv_config = xnn_init_qu8_dwconv_config(); + const struct xnn_dwconv_config* dwconv_config = xnn_get_qu8_dwconv_config(); assert(dwconv_config != NULL); union xnn_qu8_conv_minmax_params dwconv_params; @@ -1263,7 +1263,7 @@ enum xnn_status xnn_create_convolution2d_nhwc_qs8( const struct xnn_qs8_packing_params packing_params = { .input_zero_point = input_zero_point, }; - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); assert(gemm_config != NULL); union xnn_qs8_qc8w_conv_minmax_params gemm_params; @@ -1272,7 +1272,7 @@ enum xnn_status xnn_create_convolution2d_nhwc_qs8( output_zero_point, output_min, output_max); } - const struct xnn_dwconv_config* dwconv_config = xnn_init_qs8_qc8w_dwconv_config(); + const struct xnn_dwconv_config* dwconv_config = xnn_get_qs8_qc8w_dwconv_config(); assert(dwconv_config != NULL); union xnn_qs8_qc8w_conv_minmax_params dwconv_params; @@ -1421,7 +1421,7 @@ enum xnn_status create_convolution2d_nhwc_qx8_qc8w( output_zero_point, output_min, output_max); } - const struct xnn_dwconv_config* dwconv_config = xnn_init_qs8_qc8w_dwconv_config(); + const struct xnn_dwconv_config* dwconv_config = xnn_get_qs8_qc8w_dwconv_config(); assert(dwconv_config != NULL); union xnn_qs8_qc8w_conv_minmax_params dwconv_params; @@ -1503,7 +1503,7 @@ enum xnn_status xnn_create_convolution2d_nhwc_qs8_qc8w( uint32_t flags, xnn_weights_cache_t weights_cache, xnn_operator_t* convolution_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); return create_convolution2d_nhwc_qx8_qc8w(input_padding_top, input_padding_right, input_padding_bottom, input_padding_left, kernel_height, kernel_width, subsampling_height, subsampling_width, dilation_height, dilation_width, groups, group_input_channels, group_output_channels, @@ -1561,7 +1561,7 @@ enum xnn_status xnn_create_convolution2d_nhwc_f16( return xnn_status_invalid_parameter; } - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_convolution_nhwc_f16)); @@ -1573,7 +1573,7 @@ enum xnn_status xnn_create_convolution2d_nhwc_f16( gemm_config->init.f16(&gemm_params, fp16_output_min, fp16_output_max); } - const struct xnn_dwconv_config* dwconv_config = xnn_init_f16_dwconv_config(); + const struct xnn_dwconv_config* dwconv_config = xnn_get_f16_dwconv_config(); if (dwconv_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_convolution_nhwc_f16)); @@ -1587,7 +1587,7 @@ enum xnn_status xnn_create_convolution2d_nhwc_f16( dwconv_ukernel->init.f16(&dwconv_params, fp16_output_min, fp16_output_max); } - const struct xnn_vmulcaddc_config* vmulcaddc_config = xnn_init_f16_vmulcaddc_config(); + const struct xnn_vmulcaddc_config* vmulcaddc_config = xnn_get_f16_vmulcaddc_config(); if (vmulcaddc_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_convolution_nhwc_f16)); @@ -1706,7 +1706,7 @@ enum xnn_status create_convolution2d_nhwc_f32( gemm_config->init.f32(&gemm_params, output_min, output_max); } - const struct xnn_dwconv_config* dwconv_config = xnn_init_f32_dwconv_config(); + const struct xnn_dwconv_config* dwconv_config = xnn_get_f32_dwconv_config(); if (dwconv_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_convolution_nhwc_f32)); @@ -1720,7 +1720,7 @@ enum xnn_status create_convolution2d_nhwc_f32( dwconv_ukernel->init.f32(&dwconv_params, output_min, output_max); } - const struct xnn_vmulcaddc_config* vmulcaddc_config = xnn_init_f32_vmulcaddc_config(); + const struct xnn_vmulcaddc_config* vmulcaddc_config = xnn_get_f32_vmulcaddc_config(); if (vmulcaddc_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_convolution_nhwc_f32)); @@ -1795,14 +1795,14 @@ enum xnn_status xnn_create_convolution2d_nhwc_f32( uint32_t flags, xnn_weights_cache_t weights_cache, xnn_operator_t* convolution_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_convolution_nhwc_f32)); return xnn_status_unsupported_hardware; } - const struct xnn_gemm_config* gemm_nr2_config = xnn_init_f32_gemm_nr2_config(flags); + const struct xnn_gemm_config* gemm_nr2_config = xnn_get_f32_gemm_nr2_config(flags); if (gemm_nr2_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_convolution_nhwc_f32)); @@ -2373,7 +2373,7 @@ static enum xnn_status reshape_dwconv( const size_t channel_tile = convolution_op->ukernel.dwconv.channel_tile; // Be defensive against bogus hardware_config cache size info, assume the L1 cache is at least 32KB. - const size_t cache_size = max(32768, xnn_init_hardware_config()->l1_data_cache_bytes / 2); + const size_t cache_size = max(32768, xnn_get_hardware_config()->l1_data_cache_bytes / 2); const size_t output_working_set_per_channel = (primary_tile << log2_input_element_size) + (primary_tile << log2_filter_element_size) + extra_weights_elements_size + (1 << log2_output_element_size); const size_t tile_size = divide_round_up(cache_size / output_working_set_per_channel, channel_tile) * channel_tile; diff --git a/src/operators/deconvolution-nhwc.c b/src/operators/deconvolution-nhwc.c index 2c4ea27d2d6..7e92429acfd 100644 --- a/src/operators/deconvolution-nhwc.c +++ b/src/operators/deconvolution-nhwc.c @@ -502,7 +502,7 @@ enum xnn_status create_deconvolution2d_nhwc_qs8_qc8w( return xnn_status_invalid_parameter; } - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); assert(gemm_config != NULL); union xnn_qs8_qc8w_conv_minmax_params params; @@ -780,7 +780,7 @@ enum xnn_status xnn_create_deconvolution2d_nhwc_qu8( return xnn_status_unsupported_parameter; } - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); assert(gemm_config != NULL); union xnn_qu8_conv_minmax_params params; @@ -868,7 +868,7 @@ enum xnn_status xnn_create_deconvolution2d_nhwc_f16( return xnn_status_invalid_parameter; } - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_deconvolution_nhwc_f16)); @@ -1028,7 +1028,7 @@ enum xnn_status xnn_create_deconvolution2d_nhwc_qd8_f32_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* deconvolution_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qd8_f32_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qd8_f32_qc8w_gemm_config(); return create_deconvolution2d_nhwc_qx8_f32_qc8w(output_padding_top, output_padding_right, output_padding_bottom, output_padding_left, kernel_height, kernel_width, @@ -1067,7 +1067,7 @@ enum xnn_status xnn_create_deconvolution2d_nhwc_qdu8_f32_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* deconvolution_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qdu8_f32_qc8w_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qdu8_f32_qc8w_igemm_config(); return create_deconvolution2d_nhwc_qx8_f32_qc8w(output_padding_top, output_padding_right, output_padding_bottom, output_padding_left, kernel_height, kernel_width, @@ -1126,14 +1126,14 @@ enum xnn_status xnn_create_deconvolution2d_nhwc_f32( return xnn_status_invalid_parameter; } - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_deconvolution_nhwc_f32)); return xnn_status_unsupported_hardware; } - const struct xnn_gemm_config* gemm_nr2_config = xnn_init_f32_gemm_nr2_config(flags); + const struct xnn_gemm_config* gemm_nr2_config = xnn_get_f32_gemm_nr2_config(flags); if (gemm_nr2_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_deconvolution_nhwc_f32)); diff --git a/src/operators/dynamic-fully-connected-nc.c b/src/operators/dynamic-fully-connected-nc.c index fbeaad7b4e7..e5d87ef4eac 100644 --- a/src/operators/dynamic-fully-connected-nc.c +++ b/src/operators/dynamic-fully-connected-nc.c @@ -202,7 +202,7 @@ enum xnn_status xnn_create_dynamic_fully_connected_nc_f16( uint32_t flags, xnn_operator_t* dynamic_fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_dynamic_fully_connected_nc_f16)); @@ -221,7 +221,7 @@ enum xnn_status xnn_create_dynamic_fully_connected_nc_pf16( uint32_t flags, xnn_operator_t* dynamic_fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_pf16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_pf16_gemm_config(); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_dynamic_fully_connected_nc_pf16)); @@ -299,7 +299,7 @@ enum xnn_status create_dynamic_fully_connected_nc_f32( enum xnn_status xnn_create_dynamic_fully_connected_nc_f32( float output_min, float output_max, uint32_t flags, xnn_operator_t* dynamic_fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_gemm_config(flags); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_gemm_config(flags); if (gemm_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -309,7 +309,7 @@ enum xnn_status xnn_create_dynamic_fully_connected_nc_f32( } const struct xnn_gemm_config* gemm_nr2_config = - xnn_init_f32_gemm_nr2_config(flags); + xnn_get_f32_gemm_nr2_config(flags); return create_dynamic_fully_connected_nc_f32( output_min, output_max, flags, gemm_config, gemm_nr2_config, @@ -320,7 +320,7 @@ enum xnn_status xnn_create_dynamic_fully_connected_nc_f32( enum xnn_status xnn_create_dynamic_fully_connected_nc_pf32( float output_min, float output_max, uint32_t flags, xnn_operator_t* dynamic_fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_pf32_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_pf32_gemm_config(); if (gemm_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -515,10 +515,10 @@ static enum xnn_status reshape_dynamic_fully_connected_nc( dynamic_fully_connected_op->flags & XNN_FLAG_INLINE_LHS_PACKING; switch (dynamic_fully_connected_op->type) { case xnn_operator_type_dynamic_fully_connected_nc_pf16: - packed_lh_config = xnn_init_x16_pack_lh_config(); + packed_lh_config = xnn_get_x16_pack_lh_config(); break; case xnn_operator_type_dynamic_fully_connected_nc_pf32: - packed_lh_config = xnn_init_x32_pack_lh_config(); + packed_lh_config = xnn_get_x32_pack_lh_config(); break; default: break; diff --git a/src/operators/fully-connected-nc.c b/src/operators/fully-connected-nc.c index 01c12f46308..a34fc949627 100644 --- a/src/operators/fully-connected-nc.c +++ b/src/operators/fully-connected-nc.c @@ -423,7 +423,7 @@ enum xnn_status xnn_create_fully_connected_nc_f16( uint32_t flags, xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); return create_fully_connected_nc_f16(input_channels, output_channels, input_stride, output_stride, kernel, bias, output_min, output_max, flags, weights_cache, gemm_config, @@ -443,7 +443,7 @@ enum xnn_status xnn_create_fully_connected_nc_pf16( uint32_t flags, xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_pf16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_pf16_gemm_config(); return create_fully_connected_nc_f16(input_channels, output_channels, input_stride, output_stride, kernel, bias, output_min, output_max, flags, weights_cache, gemm_config, xnn_operator_type_fully_connected_nc_pf16, fully_connected_op_out); @@ -559,7 +559,7 @@ enum xnn_status xnn_create_fully_connected_nc_qd8_f16_qc4w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qd8_f16_qc4w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qd8_f16_qc4w_gemm_config(); return create_fully_connected_nc_qx8_f16_qc4w(input_channels, output_channels, input_stride, output_stride, kernel_zero_point, kernel_scale, kernel, bias, output_min, output_max, flags, weights_cache, @@ -581,7 +581,7 @@ enum xnn_status xnn_create_fully_connected_nc_qdu8_f16_qc4w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qdu8_f16_qc4w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qdu8_f16_qc4w_gemm_config(); return create_fully_connected_nc_qx8_f16_qc4w(input_channels, output_channels, input_stride, output_stride, kernel_zero_point, kernel_scale, kernel, bias, output_min, output_max, flags, weights_cache, @@ -667,7 +667,7 @@ enum xnn_status xnn_create_fully_connected_nc_qd8_f16_qb4w( return xnn_status_invalid_parameter; } - const struct xnn_gemm_config* gemm_config = xnn_init_qd8_f16_qb4w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qd8_f16_qb4w_gemm_config(); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_fully_connected_nc_qd8_f16_qb4w)); @@ -817,7 +817,7 @@ enum xnn_status xnn_create_fully_connected_nc_qd8_f32_qc4w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qd8_f32_qc4w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qd8_f32_qc4w_gemm_config(); return create_fully_connected_nc_qx8_f32_qc4w(input_channels, output_channels, input_stride, output_stride, kernel_zero_point, kernel_scale, kernel, bias, output_min, output_max, flags, @@ -840,7 +840,7 @@ enum xnn_status xnn_create_fully_connected_nc_qdu8_f32_qc4w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qdu8_f32_qc4w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qdu8_f32_qc4w_gemm_config(); return create_fully_connected_nc_qx8_f32_qc4w(input_channels, output_channels, input_stride, output_stride, kernel_zero_point, kernel_scale, kernel, bias, output_min, output_max, flags, @@ -931,7 +931,7 @@ enum xnn_status xnn_create_fully_connected_nc_qp8_f32_qc4w( } const struct xnn_gemm_config* gemm_config = - xnn_init_qp8_f32_qc4w_gemm_config(); + xnn_get_qp8_f32_qc4w_gemm_config(); if (gemm_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -961,7 +961,7 @@ enum xnn_status xnn_create_fully_connected_nc_qp8_f32_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { const struct xnn_gemm_config* gemm_config = - xnn_init_qp8_f32_qc8w_gemm_config(); + xnn_get_qp8_f32_qc8w_gemm_config(); if (gemm_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -1021,7 +1021,7 @@ enum xnn_status xnn_create_fully_connected_nc_qp8_f32_qb4w( return xnn_status_invalid_parameter; } - const struct xnn_gemm_config* gemm_config = xnn_init_qp8_f32_qb4w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qp8_f32_qb4w_gemm_config(); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_fully_connected_nc_qp8_f32_qb4w)); @@ -1240,7 +1240,7 @@ enum xnn_status xnn_create_fully_connected_nc_qd8_f32_qb4w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qd8_f32_qb4w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qd8_f32_qb4w_gemm_config(); return create_fully_connected_nc_qx8_f32_qb4w(input_channels, output_channels, input_stride, output_stride, block_size, kernel_zero_point, kernel_scale, kernel, bias, output_min, output_max, flags, weights_cache, @@ -1293,7 +1293,7 @@ enum xnn_status xnn_create_fully_connected_nc_qd8_f32_qb4w_f16_scales( uint32_t flags, xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qd8_f32_qb4w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qd8_f32_qb4w_gemm_config(); return create_fully_connected_nc_qd8_f32_qb4w_f16_scales(input_channels, output_channels, input_stride, output_stride, block_size, kernel_zero_point, kernel_scale, kernel, bias, output_min, output_max, flags, weights_cache, @@ -1315,7 +1315,7 @@ enum xnn_status xnn_create_fully_connected_nc_qdu8_f32_qb4w_f16_scales( uint32_t flags, xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qdu8_f32_qb4w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qdu8_f32_qb4w_gemm_config(); return create_fully_connected_nc_qd8_f32_qb4w_f16_scales(input_channels, output_channels, input_stride, output_stride, block_size, kernel_zero_point, kernel_scale, kernel, bias, output_min, output_max, flags, weights_cache, @@ -1338,7 +1338,7 @@ enum xnn_status xnn_create_fully_connected_nc_qdu8_f32_qb4w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qdu8_f32_qb4w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qdu8_f32_qb4w_gemm_config(); return create_fully_connected_nc_qx8_f32_qb4w(input_channels, output_channels, input_stride, output_stride, block_size, kernel_zero_point, kernel_scale, kernel, bias, output_min, output_max, flags, weights_cache, @@ -1438,7 +1438,7 @@ enum xnn_status xnn_create_fully_connected_nc_qd8_f32_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qd8_f32_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qd8_f32_qc8w_gemm_config(); return create_fully_connected_nc_qdx8_f32_qc8w(input_channels, output_channels, input_stride, output_stride, kernel_scale, kernel, bias, output_min, output_max, flags, weights_cache, gemm_config, xnn_operator_type_fully_connected_nc_qd8_f32_qc8w, @@ -1459,7 +1459,7 @@ enum xnn_status xnn_create_fully_connected_nc_qdu8_f32_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qdu8_f32_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qdu8_f32_qc8w_gemm_config(); return create_fully_connected_nc_qdx8_f32_qc8w(input_channels, output_channels, input_stride, output_stride, kernel_scale, kernel, bias, output_min, output_max, flags, weights_cache, gemm_config, xnn_operator_type_fully_connected_nc_qdu8_f32_qc8w, @@ -1563,7 +1563,7 @@ enum xnn_status xnn_create_fully_connected_nc_qd8_f16_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qd8_f16_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qd8_f16_qc8w_gemm_config(); return create_fully_connected_nc_qx8_f16_qc8w(input_channels, output_channels, input_stride, output_stride, kernel_scale, kernel, bias, output_min, output_max, flags, weights_cache, gemm_config, xnn_operator_type_fully_connected_nc_qd8_f16_qc8w, @@ -1584,7 +1584,7 @@ enum xnn_status xnn_create_fully_connected_nc_qdu8_f16_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qdu8_f16_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qdu8_f16_qc8w_gemm_config(); return create_fully_connected_nc_qx8_f16_qc8w(input_channels, output_channels, input_stride, output_stride, kernel_scale, kernel, bias, output_min, output_max, flags, weights_cache, gemm_config, xnn_operator_type_fully_connected_nc_qdu8_f16_qc8w, @@ -1711,7 +1711,7 @@ enum xnn_status xnn_create_fully_connected_nc_bf16_f32( uint32_t flags, xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_bf16_f32_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_bf16_f32_gemm_config(); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_fully_connected_nc_bf16_f32)); @@ -1735,14 +1735,14 @@ enum xnn_status xnn_create_fully_connected_nc_f32( uint32_t flags, xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_gemm_config(flags); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_gemm_config(flags); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_fully_connected_nc_f32)); return xnn_status_unsupported_hardware; } - const struct xnn_gemm_config* gemm_nr2_config = xnn_init_f32_gemm_nr2_config(flags); + const struct xnn_gemm_config* gemm_nr2_config = xnn_get_f32_gemm_nr2_config(flags); // Select microkernel configuration based on output channels if (gemm_nr2_config != NULL) { @@ -1780,7 +1780,7 @@ enum xnn_status xnn_create_fully_connected_nc_pf32( uint32_t flags, xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_pf32_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_pf32_gemm_config(); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_fully_connected_nc_pf32)); @@ -1847,7 +1847,7 @@ enum xnn_status xnn_create_fully_connected_nc_f32_qc4w( } } - const struct xnn_gemm_config* gemm_config = xnn_init_f32_qc4w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_qc4w_gemm_config(); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_fully_connected_nc_f32_qc4w)); @@ -1936,7 +1936,7 @@ enum xnn_status xnn_create_fully_connected_nc_f32_qc8w( } } - const struct xnn_gemm_config* gemm_config = xnn_init_f32_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_qc8w_gemm_config(); if (gemm_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_fully_connected_nc_f32_qc8w)); @@ -2040,7 +2040,7 @@ enum xnn_status xnn_create_fully_connected_nc_qs8( return xnn_status_unsupported_parameter; } - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); assert(gemm_config != NULL); union xnn_qs8_qc8w_conv_minmax_params params; @@ -2199,7 +2199,7 @@ enum xnn_status xnn_create_fully_connected_nc_qs8_qc4w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc4w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc4w_gemm_config(); const struct xnn_qs8_qc4w_packing_params packing_params = { .input_zero_point = input_zero_point, .kernel_zero_point = kernel_zero_point }; return create_fully_connected_nc_qx8_qc8w(input_channels, output_channels, input_stride, output_stride, input_scale, kernel_scale, kernel, @@ -2227,7 +2227,7 @@ enum xnn_status xnn_create_fully_connected_nc_qs8_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); const struct xnn_qs8_packing_params packing_params = { .input_zero_point = input_zero_point}; return create_fully_connected_nc_qx8_qc8w(input_channels, output_channels, input_stride, output_stride, input_scale, kernel_scale, kernel, @@ -2255,7 +2255,7 @@ enum xnn_status xnn_create_fully_connected_nc_pqs8_qc8w( xnn_weights_cache_t weights_cache, xnn_operator_t* fully_connected_op_out) { - const struct xnn_gemm_config* gemm_config = xnn_init_pqs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_pqs8_qc8w_gemm_config(); const struct xnn_qs8_packing_params packing_params = { .input_zero_point = input_zero_point}; return create_fully_connected_nc_qx8_qc8w(input_channels, output_channels, input_stride, output_stride, input_scale, kernel_scale, kernel, @@ -2322,7 +2322,7 @@ enum xnn_status xnn_create_fully_connected_nc_qu8( return xnn_status_unsupported_parameter; } - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); assert(gemm_config != NULL); union xnn_qu8_conv_minmax_params params; @@ -2417,42 +2417,42 @@ static enum xnn_status reshape_fully_connected_nc( case xnn_operator_type_fully_connected_nc_qd8_f16_qc4w: case xnn_operator_type_fully_connected_nc_qd8_f16_qc8w: if (inline_lhs_packing) { - packed_lh_config = xnn_init_f16_qdint8_pack_lh_config(); + packed_lh_config = xnn_get_f16_qdint8_pack_lh_config(); } break; case xnn_operator_type_fully_connected_nc_qdu8_f16_qc4w: case xnn_operator_type_fully_connected_nc_qdu8_f16_qc8w: if (inline_lhs_packing) { - packed_lh_config = xnn_init_f16_qduint8_pack_lh_config(); + packed_lh_config = xnn_get_f16_qduint8_pack_lh_config(); } break; case xnn_operator_type_fully_connected_nc_qd8_f32_qb4w: case xnn_operator_type_fully_connected_nc_qd8_f32_qc4w: case xnn_operator_type_fully_connected_nc_qd8_f32_qc8w: if (inline_lhs_packing) { - packed_lh_config = xnn_init_f32_qdint8_pack_lh_config(); + packed_lh_config = xnn_get_f32_qdint8_pack_lh_config(); } break; case xnn_operator_type_fully_connected_nc_qdu8_f32_qb4w: case xnn_operator_type_fully_connected_nc_qdu8_f32_qc4w: case xnn_operator_type_fully_connected_nc_qdu8_f32_qc8w: if (inline_lhs_packing) { - packed_lh_config = xnn_init_f32_qduint8_pack_lh_config(); + packed_lh_config = xnn_get_f32_qduint8_pack_lh_config(); } break; case xnn_operator_type_fully_connected_nc_qp8_f32_qb4w: case xnn_operator_type_fully_connected_nc_qp8_f32_qc4w: case xnn_operator_type_fully_connected_nc_qp8_f32_qc8w: - packed_lh_config = xnn_init_qp8_pack_lh_config(); + packed_lh_config = xnn_get_qp8_pack_lh_config(); break; case xnn_operator_type_fully_connected_nc_pf16: - packed_lh_config = xnn_init_x16_pack_lh_config(); + packed_lh_config = xnn_get_x16_pack_lh_config(); break; case xnn_operator_type_fully_connected_nc_pf32: - packed_lh_config = xnn_init_x32_pack_lh_config(); + packed_lh_config = xnn_get_x32_pack_lh_config(); break; case xnn_operator_type_fully_connected_nc_pqs8_qc8w: - packed_lh_config = xnn_init_x8_pack_lh_config(); + packed_lh_config = xnn_get_x8_pack_lh_config(); break; default: break; diff --git a/src/operators/max-pooling-nhwc.c b/src/operators/max-pooling-nhwc.c index 2521f03f1a3..886a1fab4f4 100644 --- a/src/operators/max-pooling-nhwc.c +++ b/src/operators/max-pooling-nhwc.c @@ -177,7 +177,7 @@ enum xnn_status xnn_create_max_pooling2d_nhwc_s8( return xnn_status_invalid_parameter; } - const struct xnn_maxpool_config* maxpool_config = xnn_init_s8_maxpool_config(); + const struct xnn_maxpool_config* maxpool_config = xnn_get_s8_maxpool_config(); assert(maxpool_config != NULL); struct xnn_s8_minmax_params params; maxpool_config->init.s8(¶ms, output_min, output_max); @@ -216,7 +216,7 @@ enum xnn_status xnn_create_max_pooling2d_nhwc_u8( return xnn_status_invalid_parameter; } - const struct xnn_maxpool_config* maxpool_config = xnn_init_u8_maxpool_config(); + const struct xnn_maxpool_config* maxpool_config = xnn_get_u8_maxpool_config(); assert(maxpool_config != NULL); struct xnn_u8_minmax_params params; maxpool_config->init.u8(¶ms, output_min, output_max); @@ -269,7 +269,7 @@ enum xnn_status xnn_create_max_pooling2d_nhwc_f32( return xnn_status_invalid_parameter; } - const struct xnn_maxpool_config* maxpool_config = xnn_init_f32_maxpool_config(); + const struct xnn_maxpool_config* maxpool_config = xnn_get_f32_maxpool_config(); if (maxpool_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -331,7 +331,7 @@ enum xnn_status xnn_create_max_pooling2d_nhwc_f16( return xnn_status_invalid_parameter; } - const struct xnn_maxpool_config* maxpool_config = xnn_init_f16_maxpool_config(); + const struct xnn_maxpool_config* maxpool_config = xnn_get_f16_maxpool_config(); if (maxpool_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_max_pooling_nhwc_f16)); diff --git a/src/operators/pack-lh.c b/src/operators/pack-lh.c index 000f4873376..3cf7425490a 100644 --- a/src/operators/pack-lh.c +++ b/src/operators/pack-lh.c @@ -69,7 +69,7 @@ enum xnn_status create_pack_lh( enum xnn_status xnn_create_pack_lh_x32( uint32_t flags, xnn_operator_t* pack_lh_op_out) { - const struct xnn_pack_lh_config *pack_lh_config = xnn_init_x32_pack_lh_config(); + const struct xnn_pack_lh_config *pack_lh_config = xnn_get_x32_pack_lh_config(); return create_pack_lh(flags, pack_lh_config, xnn_operator_type_pack_lh_x32, pack_lh_op_out); } @@ -77,7 +77,7 @@ enum xnn_status xnn_create_pack_lh_x32( enum xnn_status xnn_create_pack_lh_x16( uint32_t flags, xnn_operator_t* pack_lh_op_out) { - const struct xnn_pack_lh_config *pack_lh_config = xnn_init_x16_pack_lh_config(); + const struct xnn_pack_lh_config *pack_lh_config = xnn_get_x16_pack_lh_config(); return create_pack_lh(flags, pack_lh_config, xnn_operator_type_pack_lh_x16, pack_lh_op_out); } @@ -85,7 +85,7 @@ enum xnn_status xnn_create_pack_lh_x16( enum xnn_status xnn_create_pack_lh_x8( uint32_t flags, xnn_operator_t* pack_lh_op_out) { - const struct xnn_pack_lh_config *pack_lh_config = xnn_init_x8_pack_lh_config(); + const struct xnn_pack_lh_config *pack_lh_config = xnn_get_x8_pack_lh_config(); return create_pack_lh(flags, pack_lh_config, xnn_operator_type_pack_lh_x8, pack_lh_op_out); } @@ -154,8 +154,8 @@ enum xnn_status xnn_reshape_pack_lh_x16(xnn_operator_t pack_lh_op, size_t* output_size_bytes, pthreadpool_t threadpool) { const struct xnn_gemm_config* gemm_config = - xnn_init_pf16_gemm_config(); - const struct xnn_pack_lh_config *pack_lh_config = xnn_init_x16_pack_lh_config(); + xnn_get_pf16_gemm_config(); + const struct xnn_pack_lh_config *pack_lh_config = xnn_get_x16_pack_lh_config(); return reshape_pack_lh(pack_lh_op, num_groups, batch_size, channels, output_size_bytes, xnn_operator_type_pack_lh_x16, /*element_size=*/sizeof(xnn_float16), gemm_config, @@ -168,8 +168,8 @@ enum xnn_status xnn_reshape_pack_lh_x8(xnn_operator_t pack_lh_op, size_t* output_size_bytes, pthreadpool_t threadpool) { const struct xnn_gemm_config* gemm_config = - xnn_init_pqs8_qc8w_gemm_config(); - const struct xnn_pack_lh_config *pack_lh_config = xnn_init_x8_pack_lh_config(); + xnn_get_pqs8_qc8w_gemm_config(); + const struct xnn_pack_lh_config *pack_lh_config = xnn_get_x8_pack_lh_config(); return reshape_pack_lh(pack_lh_op, num_groups, batch_size, channels, output_size_bytes, xnn_operator_type_pack_lh_x8, /*element_size=*/sizeof(int8_t), gemm_config, @@ -182,8 +182,8 @@ enum xnn_status xnn_reshape_pack_lh_x32(xnn_operator_t pack_lh_op, size_t* output_size_bytes, pthreadpool_t threadpool) { const struct xnn_gemm_config* gemm_config = - xnn_init_pf32_gemm_config(); - const struct xnn_pack_lh_config *pack_lh_config = xnn_init_x32_pack_lh_config(); + xnn_get_pf32_gemm_config(); + const struct xnn_pack_lh_config *pack_lh_config = xnn_get_x32_pack_lh_config(); return reshape_pack_lh(pack_lh_op, num_groups, batch_size, channels, output_size_bytes, xnn_operator_type_pack_lh_x32, /*element_size=*/sizeof(float), gemm_config, diff --git a/src/operators/reduce-nd.c b/src/operators/reduce-nd.c index 046cfc0d22c..a55ac5fe719 100644 --- a/src/operators/reduce-nd.c +++ b/src/operators/reduce-nd.c @@ -430,33 +430,33 @@ enum xnn_status xnn_create_reduce_nd( case xnn_datatype_fp16: { if (is_minmax) { log2_accumulator_element_size = 1; - fill_config = xnn_init_xx_fill_config(); + fill_config = xnn_get_xx_fill_config(); cvt_config = cvt_unused; if (operator_type == xnn_operator_type_reduce_min_nd) { - config = xnn_init_f16_rmin_config(); + config = xnn_get_f16_rmin_config(); } else { // max - config = xnn_init_f16_rmax_config(); + config = xnn_get_f16_rmax_config(); } } else { log2_accumulator_element_size = 2; - config = xnn_init_f16_f32acc_rsum_config(); + config = xnn_get_f16_f32acc_rsum_config(); fill_config = fill_unused; - cvt_config = xnn_init_f32_to_f16_cvt_config(); + cvt_config = xnn_get_f32_to_f16_cvt_config(); } break; } case xnn_datatype_fp32: { if (is_minmax) { - fill_config = xnn_init_xx_fill_config(); + fill_config = xnn_get_xx_fill_config(); if (operator_type == xnn_operator_type_reduce_min_nd) { - config = xnn_init_f32_rmin_config(); + config = xnn_get_f32_rmin_config(); } else { // max - config = xnn_init_f32_rmax_config(); + config = xnn_get_f32_rmax_config(); } } else { - config = xnn_init_f32_rsum_config(); + config = xnn_get_f32_rsum_config(); fill_config = fill_unused; } @@ -470,19 +470,19 @@ enum xnn_status xnn_create_reduce_nd( assert( input_quantization->zero_point == output_quantization->zero_point); log2_accumulator_element_size = 0; - fill_config = xnn_init_xx_fill_config(); + fill_config = xnn_get_xx_fill_config(); cvt_config = cvt_unused; if (operator_type == xnn_operator_type_reduce_min_nd) { - config = xnn_init_s8_rmin_config(); + config = xnn_get_s8_rmin_config(); } else { // max - config = xnn_init_s8_rmax_config(); + config = xnn_get_s8_rmax_config(); } } else { log2_accumulator_element_size = 2; - config = xnn_init_qs8_rsum_config(); + config = xnn_get_qs8_rsum_config(); fill_config = fill_unused; - cvt_config = xnn_init_unary_reference_config( + cvt_config = xnn_get_unary_reference_config( xnn_unary_convert, xnn_datatype_int32, xnn_datatype_qint8); } break; @@ -493,21 +493,21 @@ enum xnn_status xnn_create_reduce_nd( assert( input_quantization->zero_point == output_quantization->zero_point); log2_accumulator_element_size = 0; - fill_config = xnn_init_xx_fill_config(); + fill_config = xnn_get_xx_fill_config(); cvt_config = cvt_unused; if (operator_type == xnn_operator_type_reduce_min_nd) { - config = xnn_init_u8_rmin_config(); + config = xnn_get_u8_rmin_config(); } else { // max - config = xnn_init_u8_rmax_config(); + config = xnn_get_u8_rmax_config(); } } else { log2_accumulator_element_size = 2; - config = xnn_init_qu8_rsum_config(); + config = xnn_get_qu8_rsum_config(); // We just use an int32 -> qu8 conversion. This means we effectively // only have a 31-bit accumulator instead of 32-bit, but that seems // insignificant. - cvt_config = xnn_init_unary_reference_config( + cvt_config = xnn_get_unary_reference_config( xnn_unary_convert, xnn_datatype_int32, xnn_datatype_quint8); fill_config = fill_unused; } diff --git a/src/operators/resize-bilinear-nchw.c b/src/operators/resize-bilinear-nchw.c index 3b49d841995..b64917a7ea5 100644 --- a/src/operators/resize-bilinear-nchw.c +++ b/src/operators/resize-bilinear-nchw.c @@ -27,9 +27,9 @@ static const struct xnn_ibilinear_chw_config* get_ibilinear_nchw_config(enum xnn { switch (datatype) { case xnn_datatype_fp16: - return xnn_init_f16_ibilinear_chw_config(); + return xnn_get_f16_ibilinear_chw_config(); case xnn_datatype_fp32: - return xnn_init_f32_ibilinear_chw_config(); + return xnn_get_f32_ibilinear_chw_config(); default: return NULL; } diff --git a/src/operators/resize-bilinear-nhwc.c b/src/operators/resize-bilinear-nhwc.c index 9b49db22230..73fde3ab1d5 100644 --- a/src/operators/resize-bilinear-nhwc.c +++ b/src/operators/resize-bilinear-nhwc.c @@ -29,13 +29,13 @@ static const struct xnn_ibilinear_config* get_ibilinear_nhwc_config(enum xnn_dat { switch (datatype) { case xnn_datatype_qint8: - return xnn_init_s8_ibilinear_config(); + return xnn_get_s8_ibilinear_config(); case xnn_datatype_quint8: - return xnn_init_u8_ibilinear_config(); + return xnn_get_u8_ibilinear_config(); case xnn_datatype_fp16: - return xnn_init_f16_ibilinear_config(); + return xnn_get_f16_ibilinear_config(); case xnn_datatype_fp32: - return xnn_init_f32_ibilinear_config(); + return xnn_get_f32_ibilinear_config(); default: return NULL; } diff --git a/src/operators/rope-nthc.c b/src/operators/rope-nthc.c index 5ae28c203e3..4c626d6dd74 100644 --- a/src/operators/rope-nthc.c +++ b/src/operators/rope-nthc.c @@ -75,7 +75,7 @@ enum xnn_status xnn_create_rope_nthc_f16( uint32_t flags, xnn_operator_t* rope_op_out) { - const struct xnn_cmul_config* config = xnn_init_f16_cmul_config(); + const struct xnn_cmul_config* config = xnn_get_f16_cmul_config(); if (config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_rope_nthc_f16)); @@ -93,7 +93,7 @@ enum xnn_status xnn_create_rope_nthc_f32( uint32_t flags, xnn_operator_t* rope_op_out) { - const struct xnn_cmul_config* config = xnn_init_f32_cmul_config(); + const struct xnn_cmul_config* config = xnn_get_f32_cmul_config(); if (config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_rope_nthc_f32)); diff --git a/src/operators/slice-nd.c b/src/operators/slice-nd.c index 01e66e4d354..bd2e8b20715 100644 --- a/src/operators/slice-nd.c +++ b/src/operators/slice-nd.c @@ -52,7 +52,7 @@ static enum xnn_status create_slice_nd( status = xnn_status_unsupported_hardware; - const struct xnn_unary_elementwise_config* copy_config = xnn_init_xx_copy_config(); + const struct xnn_unary_elementwise_config* copy_config = xnn_get_xx_copy_config(); if (copy_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -411,7 +411,7 @@ static enum xnn_status xnn_run_slice_nd( } slice_op.num_compute_invocations = 1; - const struct xnn_unary_elementwise_config* copy_config = xnn_init_xx_copy_config(); + const struct xnn_unary_elementwise_config* copy_config = xnn_get_xx_copy_config(); if (copy_config == NULL) { xnn_log_error( "failed to run %s operator: unsupported hardware configuration", diff --git a/src/operators/softmax-nc.c b/src/operators/softmax-nc.c index 8346186ce4e..a35b1083889 100644 --- a/src/operators/softmax-nc.c +++ b/src/operators/softmax-nc.c @@ -105,10 +105,10 @@ enum xnn_status xnn_create_softmax_nc_qu8( } softmax_op->softmax.input_scale = input_scale; - const struct xnn_lut32norm_config* lut32norm_config = xnn_init_u8_lut32norm_config(); + const struct xnn_lut32norm_config* lut32norm_config = xnn_get_u8_lut32norm_config(); assert(lut32norm_config != NULL); - const struct xnn_reduce_config* rmax_config = xnn_init_u8_rmax_config(); + const struct xnn_reduce_config* rmax_config = xnn_get_u8_rmax_config(); assert(rmax_config != NULL); softmax_op->type = xnn_operator_type_softmax_nc_qu8; @@ -297,21 +297,21 @@ enum xnn_status xnn_create_softmax_nc_f16( xnn_operator_t* softmax_op_out) { const struct xnn_raddstoreexpminusmax_config* raddstoreexpminusmax_config = - xnn_init_f16_raddstoreexpminusmax_config(); + xnn_get_f16_raddstoreexpminusmax_config(); if (raddstoreexpminusmax_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_softmax_nc_f16)); return xnn_status_unsupported_hardware; } - const struct xnn_reduce_config* rmax_config = xnn_init_f16_rmax_config(); + const struct xnn_reduce_config* rmax_config = xnn_get_f16_rmax_config(); if (rmax_config == NULL) { xnn_log_error("failed to create %s operator: unsupported hardware configuration", xnn_operator_type_to_string(xnn_operator_type_softmax_nc_f16)); return xnn_status_unsupported_hardware; } - const struct xnn_binary_elementwise_config* vmul_config = xnn_init_f16_vmul_config(); + const struct xnn_binary_elementwise_config* vmul_config = xnn_get_f16_vmul_config(); if (vmul_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -333,7 +333,7 @@ enum xnn_status xnn_create_softmax_nc_f32( xnn_operator_t* softmax_op_out) { const struct xnn_raddstoreexpminusmax_config* raddstoreexpminusmax_config = - xnn_init_f32_raddstoreexpminusmax_config(); + xnn_get_f32_raddstoreexpminusmax_config(); if (raddstoreexpminusmax_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -341,7 +341,7 @@ enum xnn_status xnn_create_softmax_nc_f32( return xnn_status_unsupported_hardware; } - const struct xnn_reduce_config* rmax_config = xnn_init_f32_rmax_config(); + const struct xnn_reduce_config* rmax_config = xnn_get_f32_rmax_config(); if (rmax_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -349,7 +349,7 @@ enum xnn_status xnn_create_softmax_nc_f32( return xnn_status_unsupported_hardware; } - const struct xnn_binary_elementwise_config* vmul_config = xnn_init_f32_vmul_config(); + const struct xnn_binary_elementwise_config* vmul_config = xnn_get_f32_vmul_config(); if (vmul_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", diff --git a/src/operators/transpose-nd.c b/src/operators/transpose-nd.c index e8cf4da82c9..c08b6cf4f74 100644 --- a/src/operators/transpose-nd.c +++ b/src/operators/transpose-nd.c @@ -66,7 +66,7 @@ static enum xnn_status create_transpose_nd( goto error; } - const struct xnn_transpose_config* transpose_config = xnn_init_transpose_config(); + const struct xnn_transpose_config* transpose_config = xnn_get_transpose_config(); if (!transpose_config) { xnn_log_error( "failed to create transpose config: unsupported hardware configuration"); @@ -631,7 +631,7 @@ enum xnn_status run_transpose_nd( transpose_op.compute = &compute; transpose_op.num_compute_invocations = 1; - const struct xnn_transpose_config* transpose_config = xnn_init_transpose_config(); + const struct xnn_transpose_config* transpose_config = xnn_get_transpose_config(); if (!transpose_config) { return xnn_status_unsupported_hardware; } @@ -763,7 +763,7 @@ enum xnn_status create_depth_to_space_nchw2nhwc( } depth_to_space_op->num_compute_invocations = 1; - const struct xnn_transpose_config* transpose_config = xnn_init_transpose_config(); + const struct xnn_transpose_config* transpose_config = xnn_get_transpose_config(); if (!transpose_config) { xnn_log_error( "failed to create transpose config: unsupported hardware configuration"); @@ -1029,7 +1029,7 @@ static enum xnn_status create_depth_to_space_nhwc( } depth_to_space_op->num_compute_invocations = 1; - const struct xnn_transpose_config* transpose_config = xnn_init_transpose_config(); + const struct xnn_transpose_config* transpose_config = xnn_get_transpose_config(); if (!transpose_config) { xnn_log_error( "failed to create transpose config: unsupported hardware configuration"); @@ -1322,7 +1322,7 @@ static enum xnn_status create_space_to_depth_nhwc( } space_to_depth_op->num_compute_invocations = 1; - const struct xnn_transpose_config* transpose_config = xnn_init_transpose_config(); + const struct xnn_transpose_config* transpose_config = xnn_get_transpose_config(); if (!transpose_config) { xnn_log_error( "failed to create transpose config: unsupported hardware configuration"); diff --git a/src/operators/unary-elementwise-nc.c b/src/operators/unary-elementwise-nc.c index b8e5a305b6e..5e209444b83 100644 --- a/src/operators/unary-elementwise-nc.c +++ b/src/operators/unary-elementwise-nc.c @@ -57,7 +57,7 @@ static enum xnn_status init_lut_op( uint8_t* lookup_table = op->lookup_table; memcpy(lookup_table, lut, lookup_table_elements); - op->lut_config = xnn_init_x8_lut_config(); + op->lut_config = xnn_get_x8_lut_config(); op->state = xnn_run_state_invalid; @@ -92,23 +92,23 @@ static const struct xnn_unary_elementwise_config* get_config( if (input_datatype != output_datatype) { if (op_type == xnn_unary_convert) { if (input_datatype == xnn_datatype_fp32 && output_datatype == xnn_datatype_fp16) { - return xnn_init_f32_to_f16_cvt_config(); + return xnn_get_f32_to_f16_cvt_config(); } else if (input_datatype == xnn_datatype_fp32 && output_datatype == xnn_datatype_qint8) { - return xnn_init_f32_to_qs8_cvt_config(); + return xnn_get_f32_to_qs8_cvt_config(); } else if (input_datatype == xnn_datatype_fp32 && output_datatype == xnn_datatype_quint8) { - return xnn_init_f32_to_qu8_cvt_config(); + return xnn_get_f32_to_qu8_cvt_config(); } else if (input_datatype == xnn_datatype_fp32 && output_datatype == xnn_datatype_qpint8) { - return xnn_init_f32_to_qp8_cvt_config(); + return xnn_get_f32_to_qp8_cvt_config(); } else if (input_datatype == xnn_datatype_fp16 && output_datatype == xnn_datatype_fp32) { - return xnn_init_f16_to_f32_cvt_config(); + return xnn_get_f16_to_f32_cvt_config(); } else if (input_datatype == xnn_datatype_fp16 && output_datatype == xnn_datatype_qint8) { - return xnn_init_f16_to_qs8_cvt_config(); + return xnn_get_f16_to_qs8_cvt_config(); } else if (input_datatype == xnn_datatype_qint8 && output_datatype == xnn_datatype_fp16) { - return xnn_init_qs8_to_f16_cvt_config(); + return xnn_get_qs8_to_f16_cvt_config(); } else if (input_datatype == xnn_datatype_qint8 && output_datatype == xnn_datatype_fp32) { - return xnn_init_qs8_to_f32_cvt_config(); + return xnn_get_qs8_to_f32_cvt_config(); } else if (input_datatype == xnn_datatype_quint8 && output_datatype == xnn_datatype_fp32) { - return xnn_init_qu8_to_f32_cvt_config(); + return xnn_get_qu8_to_f32_cvt_config(); } } return NULL; @@ -122,11 +122,11 @@ static const struct xnn_unary_elementwise_config* get_config( xnn_log_debug("unsupported operator clamp for datatype QINT8: quantization parameters differ"); return NULL; } - return xnn_init_s8_clamp_config(); + return xnn_get_s8_clamp_config(); case xnn_unary_leaky_relu: - return xnn_init_qs8_lrelu_config(); + return xnn_get_qs8_lrelu_config(); case xnn_unary_convert: - return xnn_init_qs8_cvt_config(); + return xnn_get_qs8_cvt_config(); default: return NULL; } @@ -138,99 +138,99 @@ static const struct xnn_unary_elementwise_config* get_config( xnn_log_debug("unsupported operator clamp for datatype QUINT8: quantization parameters differ"); return NULL; } - return xnn_init_u8_clamp_config(); + return xnn_get_u8_clamp_config(); case xnn_unary_leaky_relu: - return xnn_init_qu8_lrelu_config(); + return xnn_get_qu8_lrelu_config(); case xnn_unary_convert: - return xnn_init_qu8_cvt_config(); + return xnn_get_qu8_cvt_config(); default: return NULL; } } else if (datatype == xnn_datatype_fp16) { switch (op_type) { case xnn_unary_abs: - return xnn_init_f16_abs_config(); + return xnn_get_f16_abs_config(); case xnn_unary_approxgelu: - return xnn_init_f16_approxgelu_config(); + return xnn_get_f16_approxgelu_config(); case xnn_unary_bankers_rounding: - return xnn_init_f16_rndne_config(); + return xnn_get_f16_rndne_config(); case xnn_unary_ceiling: - return xnn_init_f16_rndu_config(); + return xnn_get_f16_rndu_config(); case xnn_unary_clamp: - return xnn_init_f16_clamp_config(); + return xnn_get_f16_clamp_config(); case xnn_unary_cosine: - return xnn_init_f16_cosine_config(); + return xnn_get_f16_cosine_config(); case xnn_unary_elu: - return xnn_init_f16_elu_config(); + return xnn_get_f16_elu_config(); case xnn_unary_exp: - return xnn_init_f16_exp_config(); + return xnn_get_f16_exp_config(); case xnn_unary_gelu: - return xnn_init_f16_gelu_config(); + return xnn_get_f16_gelu_config(); case xnn_unary_floor: - return xnn_init_f16_rndd_config(); + return xnn_get_f16_rndd_config(); case xnn_unary_hardswish: - return xnn_init_f16_hswish_config(); + return xnn_get_f16_hswish_config(); case xnn_unary_leaky_relu: - return xnn_init_f16_lrelu_config(); + return xnn_get_f16_lrelu_config(); case xnn_unary_negate: - return xnn_init_f16_neg_config(); + return xnn_get_f16_neg_config(); case xnn_unary_reciprocal_square_root: - return xnn_init_f16_rsqrt_config(); + return xnn_get_f16_rsqrt_config(); case xnn_unary_sigmoid: - return xnn_init_f16_sigmoid_config(); + return xnn_get_f16_sigmoid_config(); case xnn_unary_sine: - return xnn_init_f16_sine_config(); + return xnn_get_f16_sine_config(); case xnn_unary_square_root: - return xnn_init_f16_sqrt_config(); + return xnn_get_f16_sqrt_config(); case xnn_unary_square: - return xnn_init_f16_sqr_config(); + return xnn_get_f16_sqr_config(); case xnn_unary_tanh: - return xnn_init_f16_tanh_config(); + return xnn_get_f16_tanh_config(); default: return NULL; } } else if (datatype == xnn_datatype_fp32) { switch (op_type) { case xnn_unary_abs: - return xnn_init_f32_abs_config(); + return xnn_get_f32_abs_config(); case xnn_unary_approxgelu: - return xnn_init_f32_approxgelu_config(flags); + return xnn_get_f32_approxgelu_config(flags); case xnn_unary_bankers_rounding: - return xnn_init_f32_rndne_config(); + return xnn_get_f32_rndne_config(); case xnn_unary_ceiling: - return xnn_init_f32_rndu_config(); + return xnn_get_f32_rndu_config(); case xnn_unary_clamp: - return xnn_init_f32_clamp_config(); + return xnn_get_f32_clamp_config(); case xnn_unary_cosine: - return xnn_init_f32_cosine_config(flags); + return xnn_get_f32_cosine_config(flags); case xnn_unary_elu: - return xnn_init_f32_elu_config(); + return xnn_get_f32_elu_config(); case xnn_unary_exp: - return xnn_init_f32_exp_config(flags); + return xnn_get_f32_exp_config(flags); case xnn_unary_floor: - return xnn_init_f32_rndd_config(); + return xnn_get_f32_rndd_config(); case xnn_unary_gelu: - return xnn_init_f32_gelu_config(flags); + return xnn_get_f32_gelu_config(flags); case xnn_unary_hardswish: - return xnn_init_f32_hswish_config(flags); + return xnn_get_f32_hswish_config(flags); case xnn_unary_leaky_relu: - return xnn_init_f32_lrelu_config(); + return xnn_get_f32_lrelu_config(); case xnn_unary_log: - return xnn_init_f32_log_config(flags); + return xnn_get_f32_log_config(flags); case xnn_unary_negate: - return xnn_init_f32_neg_config(); + return xnn_get_f32_neg_config(); case xnn_unary_reciprocal_square_root: - return xnn_init_f32_rsqrt_config(flags); + return xnn_get_f32_rsqrt_config(flags); case xnn_unary_sigmoid: - return xnn_init_f32_sigmoid_config(); + return xnn_get_f32_sigmoid_config(); case xnn_unary_sine: - return xnn_init_f32_sine_config(flags); + return xnn_get_f32_sine_config(flags); case xnn_unary_square_root: - return xnn_init_f32_sqrt_config(flags); + return xnn_get_f32_sqrt_config(flags); case xnn_unary_square: - return xnn_init_f32_sqr_config(); + return xnn_get_f32_sqr_config(); case xnn_unary_tanh: - return xnn_init_f32_tanh_config(flags); + return xnn_get_f32_tanh_config(flags); default: return NULL; } @@ -276,7 +276,7 @@ static enum xnn_status init_op( } // Fall back to reference. - config = xnn_init_unary_reference_config(op_type, input_datatype, output_datatype); + config = xnn_get_unary_reference_config(op_type, input_datatype, output_datatype); if (config) { if (xnn_datatype_size_bytes(input_datatype) == 1 && xnn_datatype_size_bytes(output_datatype) == 1) { // We can use a LUT for this op. @@ -797,7 +797,7 @@ enum xnn_status create_convert_nc_f16_qx8( enum xnn_operator_type expected_operator_type, xnn_operator_t* convert_op_out) { - const struct xnn_reduce_config* f16_rminmax_config = xnn_init_f16_rminmax_config(); + const struct xnn_reduce_config* f16_rminmax_config = xnn_get_f16_rminmax_config(); if (f16_rminmax_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -821,7 +821,7 @@ enum xnn_status create_convert_nc_f32_qx8( enum xnn_operator_type expected_operator_type, xnn_operator_t* convert_op_out) { - const struct xnn_reduce_config* f32_rminmax_config = xnn_init_f32_rminmax_config(); + const struct xnn_reduce_config* f32_rminmax_config = xnn_get_f32_rminmax_config(); if (f32_rminmax_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -842,32 +842,32 @@ enum xnn_status create_convert_nc_f32_qx8( enum xnn_status xnn_create_convert_nc_f16_qd8( uint32_t flags, xnn_operator_t* convert_op_out) { - return create_convert_nc_f16_qx8(flags, xnn_init_f16_to_qs8_cvt_config(), xnn_operator_type_convert_nc_f16_qd8, convert_op_out); + return create_convert_nc_f16_qx8(flags, xnn_get_f16_to_qs8_cvt_config(), xnn_operator_type_convert_nc_f16_qd8, convert_op_out); } enum xnn_status xnn_create_convert_nc_f16_qdu8( uint32_t flags, xnn_operator_t* convert_op_out) { - return create_convert_nc_f16_qx8(flags, xnn_init_f16_to_qu8_cvt_config(), xnn_operator_type_convert_nc_f16_qdu8, convert_op_out); + return create_convert_nc_f16_qx8(flags, xnn_get_f16_to_qu8_cvt_config(), xnn_operator_type_convert_nc_f16_qdu8, convert_op_out); } enum xnn_status xnn_create_convert_nc_f32_qd8( uint32_t flags, xnn_operator_t* convert_op_out) { - return create_convert_nc_f32_qx8(flags, xnn_init_f32_to_qs8_cvt_config(), xnn_operator_type_convert_nc_f32_qd8, convert_op_out); + return create_convert_nc_f32_qx8(flags, xnn_get_f32_to_qs8_cvt_config(), xnn_operator_type_convert_nc_f32_qd8, convert_op_out); } enum xnn_status xnn_create_convert_nc_f32_qdu8( uint32_t flags, xnn_operator_t* convert_op_out) { - return create_convert_nc_f32_qx8(flags, xnn_init_f32_to_qu8_cvt_config(), xnn_operator_type_convert_nc_f32_qdu8, convert_op_out); + return create_convert_nc_f32_qx8(flags, xnn_get_f32_to_qu8_cvt_config(), xnn_operator_type_convert_nc_f32_qdu8, convert_op_out); } enum xnn_status xnn_create_convert_nc_f32_qp8( uint32_t flags, const struct xnn_gemm_config* gemm_config, xnn_operator_t* convert_op_out) { const struct xnn_reduce_config* f32_rminmax_config = - xnn_init_f32_rminmax_config(); + xnn_get_f32_rminmax_config(); if (f32_rminmax_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", @@ -876,7 +876,7 @@ enum xnn_status xnn_create_convert_nc_f32_qp8( } enum xnn_status status = create_unary_elementwise_nc( - flags, xnn_init_f32_to_qp8_cvt_config(), + flags, xnn_get_f32_to_qp8_cvt_config(), /*params=*/NULL, /*params_size=*/0, xnn_operator_type_convert_nc_f32_qp8, convert_op_out); if (status == xnn_status_success) { @@ -891,7 +891,7 @@ enum xnn_status xnn_create_copy_nc_x8( xnn_operator_t* copy_op_out) { return create_unary_elementwise_nc( - flags, xnn_init_xx_copy_config(), + flags, xnn_get_xx_copy_config(), /*params=*/NULL, /*params_size=*/0, xnn_operator_type_copy_nc_x8, copy_op_out); } @@ -901,7 +901,7 @@ enum xnn_status xnn_create_copy_nc_x16( xnn_operator_t* copy_op_out) { return create_unary_elementwise_nc( - flags, xnn_init_xx_copy_config(), + flags, xnn_get_xx_copy_config(), /*params=*/NULL, /*params_size=*/0, xnn_operator_type_copy_nc_x16, copy_op_out); } @@ -911,7 +911,7 @@ enum xnn_status xnn_create_copy_nc_x32( xnn_operator_t* copy_op_out) { return create_unary_elementwise_nc( - flags, xnn_init_xx_copy_config(), + flags, xnn_get_xx_copy_config(), /*params=*/NULL, /*params_size=*/0, xnn_operator_type_copy_nc_x32, copy_op_out); } @@ -1465,7 +1465,7 @@ enum xnn_status xnn_run_copy_nc_x32( xnn_operator_type_copy_nc_x32, channels, input_stride, output_stride, batch_size, input, output, - xnn_init_xx_copy_config(), NULL, 0, + xnn_get_xx_copy_config(), NULL, 0, /*log2_input_size=*/XNN_LOG2_SIZEOF_UINT32_T, /*log2_output_size=*/XNN_LOG2_SIZEOF_UINT32_T, flags, diff --git a/src/operators/unpooling-nhwc.c b/src/operators/unpooling-nhwc.c index 54ad5bad4e7..3a3d6b1c87b 100644 --- a/src/operators/unpooling-nhwc.c +++ b/src/operators/unpooling-nhwc.c @@ -80,7 +80,7 @@ enum xnn_status xnn_create_unpooling2d_nhwc_x32( goto error; } - const struct xnn_unpool_config* unpool_config = xnn_init_x32_unpool_config(); + const struct xnn_unpool_config* unpool_config = xnn_get_x32_unpool_config(); if (unpool_config == NULL) { xnn_log_error( "failed to create %s operator: unsupported hardware configuration", diff --git a/src/pack-lh.cc b/src/pack-lh.cc index a722f128ed1..dff93bd5ed5 100644 --- a/src/pack-lh.cc +++ b/src/pack-lh.cc @@ -40,7 +40,7 @@ void pack_lh_fx_qd(size_t m, size_t k, size_t mr_packed, size_t kr, size_t sr, // Initialize a static pointer to the convert and minmax configs. Not using // static initialization since this potentially locks a mutex at each call, // and also not worried about it being initialized twice since the - // `xnn_init_*_config` calls are synced and should always produce the same + // `xnn_get_*_config` calls are synced and should always produce the same // result. static std::atomic convert_ukernel; if (!convert_ukernel) { @@ -130,7 +130,7 @@ void xnn_pack_lh_f32_qdint8(size_t m, size_t k, size_t mr_packed, size_t kr, size_t lhs_stride, void* lhs_packed) { pack_lh_fx_qd( m, k, mr_packed, kr, sr, m_idx_start, (const float*)lhs, lhs_stride, lhs_packed); @@ -141,7 +141,7 @@ void xnn_pack_lh_f32_qduint8(size_t m, size_t k, size_t mr_packed, size_t kr, size_t lhs_stride, void* lhs_packed) { pack_lh_fx_qd( m, k, mr_packed, kr, sr, m_idx_start, (const float*)lhs, lhs_stride, lhs_packed); @@ -152,7 +152,7 @@ void xnn_pack_lh_f16_qdint8(size_t m, size_t k, size_t mr_packed, size_t kr, size_t lhs_stride, void* lhs_packed) { pack_lh_fx_qd( m, k, mr_packed, kr, sr, m_idx_start, (const xnn_float16*)lhs, lhs_stride, lhs_packed); @@ -163,7 +163,7 @@ void xnn_pack_lh_f16_qduint8(size_t m, size_t k, size_t mr_packed, size_t kr, size_t lhs_stride, void* lhs_packed) { pack_lh_fx_qd( m, k, mr_packed, kr, sr, m_idx_start, (const xnn_float16*)lhs, lhs_stride, lhs_packed); diff --git a/src/qs8-dwconv/qs8-dwconv-minmax-fp32.inc b/src/qs8-dwconv/qs8-dwconv-minmax-fp32.inc index f24fa3f84bd..b74caa2d109 100644 --- a/src/qs8-dwconv/qs8-dwconv-minmax-fp32.inc +++ b/src/qs8-dwconv/qs8-dwconv-minmax-fp32.inc @@ -95,8 +95,8 @@ XNN_UKERNEL(0, xnn_qs8_dwconv_minmax_fp32_ukernel_25p16c__wasmsimd_mul16_add16, #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD #if XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR -XNN_UKERNEL(0, xnn_qs8_dwconv_minmax_fp32_ukernel_9p8vc__rvv, 8, false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(int32_t)), 9, int8_t, void, union xnn_qs8_conv_minmax_params, xnn_init_qs8_conv_minmax_fp32_scalar_params) -XNN_UKERNEL(0, xnn_qs8_dwconv_minmax_fp32_ukernel_25p8vc__rvv, 8, false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(int32_t)), 25, int8_t, void, union xnn_qs8_conv_minmax_params, xnn_init_qs8_conv_minmax_fp32_scalar_params) +XNN_UKERNEL(0, xnn_qs8_dwconv_minmax_fp32_ukernel_9p8vc__rvv, 8, false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(int32_t)), 9, int8_t, void, union xnn_qs8_conv_minmax_params, xnn_init_qs8_conv_minmax_fp32_scalar_params) +XNN_UKERNEL(0, xnn_qs8_dwconv_minmax_fp32_ukernel_25p8vc__rvv, 8, false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(int32_t)), 25, int8_t, void, union xnn_qs8_conv_minmax_params, xnn_init_qs8_conv_minmax_fp32_scalar_params) #endif // XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR XNN_UKERNEL(0, xnn_qs8_dwconv_minmax_fp32_ukernel_9p1c__scalar_fmagic, 1, false, 1, 9, int8_t, void, union xnn_qs8_conv_minmax_params, xnn_init_qs8_conv_minmax_fp32_scalar_params) diff --git a/src/qs8-qc8w-dwconv/qs8-qc8w-dwconv-minmax-fp32.inc b/src/qs8-qc8w-dwconv/qs8-qc8w-dwconv-minmax-fp32.inc index aacf48a5101..1652b2cd241 100644 --- a/src/qs8-qc8w-dwconv/qs8-qc8w-dwconv-minmax-fp32.inc +++ b/src/qs8-qc8w-dwconv/qs8-qc8w-dwconv-minmax-fp32.inc @@ -135,9 +135,9 @@ XNN_UKERNEL(0, xnn_qs8_qc8w_dwconv_minmax_fp32_ukernel_25p16c__wasmsimd_mul16_ad #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD #if XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR -XNN_UKERNEL(0, xnn_qs8_qc8w_dwconv_minmax_fp32_ukernel_3p8vc__rvv, 8, false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(int32_t)), 3, int8_t, void, union xnn_qs8_qc8w_conv_minmax_params, xnn_init_qs8_qc8w_conv_minmax_fp32_scalar_params) -XNN_UKERNEL(0, xnn_qs8_qc8w_dwconv_minmax_fp32_ukernel_9p8vc__rvv, 8, false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(int32_t)), 9, int8_t, void, union xnn_qs8_qc8w_conv_minmax_params, xnn_init_qs8_qc8w_conv_minmax_fp32_scalar_params) -XNN_UKERNEL(0, xnn_qs8_qc8w_dwconv_minmax_fp32_ukernel_25p8vc__rvv, 8, false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(int32_t)), 25, int8_t, void, union xnn_qs8_qc8w_conv_minmax_params, xnn_init_qs8_qc8w_conv_minmax_fp32_scalar_params) +XNN_UKERNEL(0, xnn_qs8_qc8w_dwconv_minmax_fp32_ukernel_3p8vc__rvv, 8, false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(int32_t)), 3, int8_t, void, union xnn_qs8_qc8w_conv_minmax_params, xnn_init_qs8_qc8w_conv_minmax_fp32_scalar_params) +XNN_UKERNEL(0, xnn_qs8_qc8w_dwconv_minmax_fp32_ukernel_9p8vc__rvv, 8, false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(int32_t)), 9, int8_t, void, union xnn_qs8_qc8w_conv_minmax_params, xnn_init_qs8_qc8w_conv_minmax_fp32_scalar_params) +XNN_UKERNEL(0, xnn_qs8_qc8w_dwconv_minmax_fp32_ukernel_25p8vc__rvv, 8, false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(int32_t)), 25, int8_t, void, union xnn_qs8_qc8w_conv_minmax_params, xnn_init_qs8_qc8w_conv_minmax_fp32_scalar_params) #endif // XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR XNN_UKERNEL(0, xnn_qs8_qc8w_dwconv_minmax_fp32_ukernel_3p1c__scalar_fmagic, 1, false, 1, 3, int8_t, void, union xnn_qs8_qc8w_conv_minmax_params, xnn_init_qs8_qc8w_conv_minmax_fp32_scalar_params) diff --git a/src/qu8-dwconv/qu8-dwconv-minmax-fp32.inc b/src/qu8-dwconv/qu8-dwconv-minmax-fp32.inc index ce762f9ad0d..803506c7bb6 100644 --- a/src/qu8-dwconv/qu8-dwconv-minmax-fp32.inc +++ b/src/qu8-dwconv/qu8-dwconv-minmax-fp32.inc @@ -67,8 +67,8 @@ XNN_UKERNEL(0, xnn_qu8_dwconv_minmax_fp32_ukernel_25p16c__wasmsimd_mul16, 16, fa #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD #if XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR -XNN_UKERNEL(0, xnn_qu8_dwconv_minmax_fp32_ukernel_9p8vc__rvv, 8, false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(int32_t)), 9, uint8_t, void, union xnn_qu8_conv_minmax_params, xnn_init_qu8_conv_minmax_fp32_scalar_params) -XNN_UKERNEL(0, xnn_qu8_dwconv_minmax_fp32_ukernel_25p8vc__rvv, 8, false, 8 * (xnn_init_hardware_config()->vlenb / sizeof(int32_t)), 25, uint8_t, void, union xnn_qu8_conv_minmax_params, xnn_init_qu8_conv_minmax_fp32_scalar_params) +XNN_UKERNEL(0, xnn_qu8_dwconv_minmax_fp32_ukernel_9p8vc__rvv, 8, false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(int32_t)), 9, uint8_t, void, union xnn_qu8_conv_minmax_params, xnn_init_qu8_conv_minmax_fp32_scalar_params) +XNN_UKERNEL(0, xnn_qu8_dwconv_minmax_fp32_ukernel_25p8vc__rvv, 8, false, 8 * (xnn_get_hardware_config()->vlenb / sizeof(int32_t)), 25, uint8_t, void, union xnn_qu8_conv_minmax_params, xnn_init_qu8_conv_minmax_fp32_scalar_params) #endif // XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR XNN_UKERNEL(0, xnn_qu8_dwconv_minmax_fp32_ukernel_9p1c__scalar_fmagic, 1, false, 1, 9, uint8_t, void, union xnn_qu8_conv_minmax_params, xnn_init_qu8_conv_minmax_fp32_scalar_params) diff --git a/src/reference/binary-elementwise.cc b/src/reference/binary-elementwise.cc index 82986c53ed3..b0e969c03be 100644 --- a/src/reference/binary-elementwise.cc +++ b/src/reference/binary-elementwise.cc @@ -352,7 +352,7 @@ struct CopysignOp { extern "C" { -const struct xnn_binary_elementwise_config* xnn_init_binary_reference_config( +const struct xnn_binary_elementwise_config* xnn_get_binary_reference_config( enum xnn_binary_operator type, enum xnn_datatype datatype) { switch (type) { case xnn_binary_add: diff --git a/src/reference/unary-elementwise.cc b/src/reference/unary-elementwise.cc index 1c50ab0cd24..772a926f005 100644 --- a/src/reference/unary-elementwise.cc +++ b/src/reference/unary-elementwise.cc @@ -574,11 +574,11 @@ const xnn_unary_elementwise_config* get_config(xnn_unary_operator op, extern "C" { -// If we could guarantee that xnn_init_*_config did not return NULL, we could +// If we could guarantee that xnn_get_*_config did not return NULL, we could // only support reference configs for the subset of ops/datatypes that we don't // have a microkernel for. But, that is not the case, so we need the full set of // reference ops implemented. -const xnn_unary_elementwise_config* xnn_init_unary_reference_config( +const xnn_unary_elementwise_config* xnn_get_unary_reference_config( xnn_unary_operator op, xnn_datatype input_datatype, xnn_datatype output_datatype) { if (op == xnn_unary_convert) { diff --git a/src/subgraph.c b/src/subgraph.c index 9cbb7fd4224..ef6b1756826 100644 --- a/src/subgraph.c +++ b/src/subgraph.c @@ -1023,7 +1023,7 @@ bool xnn_subgraph_rewrite_for_fp16(xnn_subgraph_t subgraph) { case xnn_node_type_rope: break; case xnn_node_type_pack_lh: - if (xnn_init_x16_pack_lh_config() != NULL) { + if (xnn_get_x16_pack_lh_config() != NULL) { break; } default: @@ -2203,41 +2203,41 @@ static bool convert_gemm_to_qduint8( const struct xnn_gemm_config* unsigned_config = NULL; if (input_datatype == xnn_datatype_fp32) { if (consumer_weights_type == xnn_datatype_qcint4) { - original_config = xnn_init_qd8_f32_qc4w_gemm_config(); - unsigned_config = xnn_init_qdu8_f32_qc4w_gemm_config(); + original_config = xnn_get_qd8_f32_qc4w_gemm_config(); + unsigned_config = xnn_get_qdu8_f32_qc4w_gemm_config(); } else if (consumer_weights_type == xnn_datatype_qcint8) { - original_config = xnn_init_qd8_f32_qc8w_gemm_config(); + original_config = xnn_get_qd8_f32_qc8w_gemm_config(); switch (consumer_type) { case xnn_node_type_batch_matrix_multiply: case xnn_node_type_fully_connected: - unsigned_config = xnn_init_qdu8_f32_qc8w_gemm_config(); + unsigned_config = xnn_get_qdu8_f32_qc8w_gemm_config(); break; case xnn_node_type_convolution_2d: case xnn_node_type_deconvolution_2d: - unsigned_config = xnn_init_qdu8_f32_qc8w_igemm_config(); + unsigned_config = xnn_get_qdu8_f32_qc8w_igemm_config(); break; default: XNN_UNREACHABLE; } } else if (consumer_weights_type == xnn_datatype_qbint4) { - original_config = xnn_init_qd8_f32_qb4w_gemm_config(); - unsigned_config = xnn_init_qdu8_f32_qb4w_gemm_config(); + original_config = xnn_get_qd8_f32_qb4w_gemm_config(); + unsigned_config = xnn_get_qdu8_f32_qb4w_gemm_config(); } } else if (input_datatype == xnn_datatype_fp16) { if (consumer_weights_type == xnn_datatype_qcint4) { - original_config = xnn_init_qd8_f16_qc4w_gemm_config(); - unsigned_config = xnn_init_qdu8_f16_qc4w_gemm_config(); + original_config = xnn_get_qd8_f16_qc4w_gemm_config(); + unsigned_config = xnn_get_qdu8_f16_qc4w_gemm_config(); } else if (consumer_weights_type == xnn_datatype_qcint8) { switch (consumer_type) { case xnn_node_type_batch_matrix_multiply: case xnn_node_type_fully_connected: - original_config = xnn_init_qd8_f16_qc8w_gemm_config(); - unsigned_config = xnn_init_qdu8_f16_qc8w_gemm_config(); + original_config = xnn_get_qd8_f16_qc8w_gemm_config(); + unsigned_config = xnn_get_qdu8_f16_qc8w_gemm_config(); break; case xnn_node_type_convolution_2d: case xnn_node_type_deconvolution_2d: - original_config = xnn_init_qd8_f16_qc8w_igemm_config(); - unsigned_config = xnn_init_qdu8_f16_qc8w_gemm_config(); + original_config = xnn_get_qd8_f16_qc8w_igemm_config(); + unsigned_config = xnn_get_qdu8_f16_qc8w_gemm_config(); break; default: XNN_UNREACHABLE; @@ -2290,7 +2290,7 @@ enum xnn_status xnn_subgraph_optimize_packed_lhs(xnn_subgraph_t subgraph, case xnn_datatype_fp16: if (input_datatype == output_datatype && kernel_datatype == xnn_datatype_fp16) { - if ((gemm_config = xnn_init_pf16_gemm_config())) { + if ((gemm_config = xnn_get_pf16_gemm_config())) { assumed_datatype = xnn_datatype_pfp16; } } @@ -2298,7 +2298,7 @@ enum xnn_status xnn_subgraph_optimize_packed_lhs(xnn_subgraph_t subgraph, case xnn_datatype_fp32: if (input_datatype == output_datatype && kernel_datatype == xnn_datatype_fp32) { - if ((gemm_config = xnn_init_pf32_gemm_config())) { + if ((gemm_config = xnn_get_pf32_gemm_config())) { assumed_datatype = xnn_datatype_pfp32; } } @@ -2306,7 +2306,7 @@ enum xnn_status xnn_subgraph_optimize_packed_lhs(xnn_subgraph_t subgraph, case xnn_datatype_qint8: if (input_datatype == output_datatype && kernel_datatype == xnn_datatype_qcint8) { - if ((gemm_config = xnn_init_pqs8_qc8w_gemm_config())) { + if ((gemm_config = xnn_get_pqs8_qc8w_gemm_config())) { assumed_datatype = xnn_datatype_pqint8; } } @@ -2318,17 +2318,17 @@ enum xnn_status xnn_subgraph_optimize_packed_lhs(xnn_subgraph_t subgraph, if (output_datatype == xnn_datatype_fp32) { switch (kernel_datatype) { case xnn_datatype_qbint4: - if ((gemm_config = xnn_init_qp8_f32_qb4w_gemm_config())) { + if ((gemm_config = xnn_get_qp8_f32_qb4w_gemm_config())) { assumed_datatype = xnn_datatype_qpint8; } break; case xnn_datatype_qcint4: - if ((gemm_config = xnn_init_qp8_f32_qc4w_gemm_config())) { + if ((gemm_config = xnn_get_qp8_f32_qc4w_gemm_config())) { assumed_datatype = xnn_datatype_qpint8; } break; case xnn_datatype_qcint8: - if ((gemm_config = xnn_init_qp8_f32_qc8w_gemm_config())) { + if ((gemm_config = xnn_get_qp8_f32_qc8w_gemm_config())) { assumed_datatype = xnn_datatype_qpint8; } break; @@ -2587,7 +2587,7 @@ enum xnn_status xnn_subgraph_optimize(xnn_subgraph_t subgraph, } const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); if (hardware_config == NULL) { xnn_log_error("failed to get hardware config"); return xnn_status_unsupported_hardware; diff --git a/src/x32-packw/x32-packw.inc b/src/x32-packw/x32-packw.inc index faef096bc3b..0b15928fbeb 100644 --- a/src/x32-packw/x32-packw.inc +++ b/src/x32-packw/x32-packw.inc @@ -129,18 +129,18 @@ XNN_UKERNEL(0, xnn_x32_packw_gemm_goi_ukernel_x64__scalar_float_u2, 64, 1, 1, 2, XNN_UKERNEL(0, xnn_x32_packw_gemm_goi_ukernel_x64__scalar_int_u2, 64, 1, 1, 2, 1) #if XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x1v__rvv_u2, 1, 1, 1, 2, xnn_init_hardware_config()->vlenb / sizeof(uint32_t)) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x1v__rvv_u4, 1, 1, 1, 4, xnn_init_hardware_config()->vlenb / sizeof(uint32_t)) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x1v__rvv_u8, 1, 1, 1, 8, xnn_init_hardware_config()->vlenb / sizeof(uint32_t)) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x2v__rvv_u2, 2, 1, 1, 2, xnn_init_hardware_config()->vlenb / sizeof(uint32_t)) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x2v__rvv_u4, 2, 1, 1, 4, xnn_init_hardware_config()->vlenb / sizeof(uint32_t)) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x2v__rvv_u8, 2, 1, 1, 8, xnn_init_hardware_config()->vlenb / sizeof(uint32_t)) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x4v__rvv_u2, 4, 1, 1, 2, xnn_init_hardware_config()->vlenb / sizeof(uint32_t)) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x4v__rvv_u4, 4, 1, 1, 4, xnn_init_hardware_config()->vlenb / sizeof(uint32_t)) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x4v__rvv_u8, 4, 1, 1, 8, xnn_init_hardware_config()->vlenb / sizeof(uint32_t)) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x8v__rvv_u2, 8, 1, 1, 2, xnn_init_hardware_config()->vlenb / sizeof(uint32_t)) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x8v__rvv_u4, 8, 1, 1, 4, xnn_init_hardware_config()->vlenb / sizeof(uint32_t)) -XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x8v__rvv_u8, 8, 1, 1, 8, xnn_init_hardware_config()->vlenb / sizeof(uint32_t)) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x1v__rvv_u2, 1, 1, 1, 2, xnn_get_hardware_config()->vlenb / sizeof(uint32_t)) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x1v__rvv_u4, 1, 1, 1, 4, xnn_get_hardware_config()->vlenb / sizeof(uint32_t)) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x1v__rvv_u8, 1, 1, 1, 8, xnn_get_hardware_config()->vlenb / sizeof(uint32_t)) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x2v__rvv_u2, 2, 1, 1, 2, xnn_get_hardware_config()->vlenb / sizeof(uint32_t)) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x2v__rvv_u4, 2, 1, 1, 4, xnn_get_hardware_config()->vlenb / sizeof(uint32_t)) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x2v__rvv_u8, 2, 1, 1, 8, xnn_get_hardware_config()->vlenb / sizeof(uint32_t)) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x4v__rvv_u2, 4, 1, 1, 2, xnn_get_hardware_config()->vlenb / sizeof(uint32_t)) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x4v__rvv_u4, 4, 1, 1, 4, xnn_get_hardware_config()->vlenb / sizeof(uint32_t)) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x4v__rvv_u8, 4, 1, 1, 8, xnn_get_hardware_config()->vlenb / sizeof(uint32_t)) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x8v__rvv_u2, 8, 1, 1, 2, xnn_get_hardware_config()->vlenb / sizeof(uint32_t)) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x8v__rvv_u4, 8, 1, 1, 4, xnn_get_hardware_config()->vlenb / sizeof(uint32_t)) +XNN_UKERNEL(xnn_arch_riscv_vector, xnn_x32_packw_gemm_goi_ukernel_x8v__rvv_u8, 8, 1, 1, 8, xnn_get_hardware_config()->vlenb / sizeof(uint32_t)) #endif // XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR #if XNN_ARCH_HEXAGON && XNN_ENABLE_HVX diff --git a/src/xnnpack/config.h b/src/xnnpack/config.h index 70a4020ad2d..913671e6eed 100644 --- a/src/xnnpack/config.h +++ b/src/xnnpack/config.h @@ -18,224 +18,224 @@ extern "C" { #endif -XNN_INTERNAL const struct xnn_x8_lut_config* xnn_init_x8_lut_config(); +XNN_INTERNAL const struct xnn_x8_lut_config* xnn_get_x8_lut_config(); -XNN_INTERNAL const struct xnn_transpose_config* xnn_init_transpose_config(); +XNN_INTERNAL const struct xnn_transpose_config* xnn_get_transpose_config(); -XNN_INTERNAL const struct xnn_cmul_config* xnn_init_f16_cmul_config(); -XNN_INTERNAL const struct xnn_cmul_config* xnn_init_f32_cmul_config(); +XNN_INTERNAL const struct xnn_cmul_config* xnn_get_f16_cmul_config(); +XNN_INTERNAL const struct xnn_cmul_config* xnn_get_f32_cmul_config(); XNN_INTERNAL const struct xnn_pack_lh_config* -xnn_init_f16_qdint8_pack_lh_config(); +xnn_get_f16_qdint8_pack_lh_config(); XNN_INTERNAL const struct xnn_pack_lh_config* -xnn_init_f16_qduint8_pack_lh_config(); +xnn_get_f16_qduint8_pack_lh_config(); XNN_INTERNAL const struct xnn_pack_lh_config* -xnn_init_f32_qdint8_pack_lh_config(); +xnn_get_f32_qdint8_pack_lh_config(); XNN_INTERNAL const struct xnn_pack_lh_config* -xnn_init_f32_qduint8_pack_lh_config(); -XNN_INTERNAL const struct xnn_pack_lh_config* xnn_init_qp8_pack_lh_config(); -XNN_INTERNAL const struct xnn_pack_lh_config* xnn_init_x8_pack_lh_config(); -XNN_INTERNAL const struct xnn_pack_lh_config* xnn_init_x16_pack_lh_config(); -XNN_INTERNAL const struct xnn_pack_lh_config* xnn_init_x32_pack_lh_config(); +xnn_get_f32_qduint8_pack_lh_config(); +XNN_INTERNAL const struct xnn_pack_lh_config* xnn_get_qp8_pack_lh_config(); +XNN_INTERNAL const struct xnn_pack_lh_config* xnn_get_x8_pack_lh_config(); +XNN_INTERNAL const struct xnn_pack_lh_config* xnn_get_x16_pack_lh_config(); +XNN_INTERNAL const struct xnn_pack_lh_config* xnn_get_x32_pack_lh_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f16_vadd_config(); +xnn_get_f16_vadd_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f16_vdiv_config(); +xnn_get_f16_vdiv_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f16_vmax_config(); +xnn_get_f16_vmax_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f16_vmin_config(); +xnn_get_f16_vmin_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f16_vmul_config(); +xnn_get_f16_vmul_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f16_vprelu_config(); +xnn_get_f16_vprelu_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f16_vsub_config(); +xnn_get_f16_vsub_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f16_vsqrdiff_config(); +xnn_get_f16_vsqrdiff_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f32_vadd_config(); +xnn_get_f32_vadd_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f32_vcopysign_config(); +xnn_get_f32_vcopysign_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f32_vdiv_config(); +xnn_get_f32_vdiv_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f32_vmax_config(); +xnn_get_f32_vmax_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f32_vmin_config(); +xnn_get_f32_vmin_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f32_vmul_config(); +xnn_get_f32_vmul_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f32_vprelu_config(); +xnn_get_f32_vprelu_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f32_vsub_config(); +xnn_get_f32_vsub_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_f32_vsqrdiff_config(); +xnn_get_f32_vsqrdiff_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_qs8_vadd_config(); +xnn_get_qs8_vadd_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_qs8_vmul_config(); +xnn_get_qs8_vmul_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_qs8_vprelu_config(); +xnn_get_qs8_vprelu_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_qu8_vadd_config(); +xnn_get_qu8_vadd_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_qu8_vmul_config(); +xnn_get_qu8_vmul_config(); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_qu8_vprelu_config(); +xnn_get_qu8_vprelu_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_abs_config(); +xnn_get_f16_abs_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_approxgelu_config(); +xnn_get_f16_approxgelu_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_clamp_config(); +xnn_get_f16_clamp_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_cosine_config(); +xnn_get_f16_cosine_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_elu_config(); +xnn_get_f16_elu_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_exp_config(); +xnn_get_f16_exp_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_gelu_config(); +xnn_get_f16_gelu_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_hswish_config(); +xnn_get_f16_hswish_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_lrelu_config(); +xnn_get_f16_lrelu_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_neg_config(); +xnn_get_f16_neg_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_relu_config(); +xnn_get_f16_relu_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_rndd_config(); +xnn_get_f16_rndd_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_rndne_config(); +xnn_get_f16_rndne_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_rndu_config(); +xnn_get_f16_rndu_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_rndz_config(); +xnn_get_f16_rndz_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_rsqrt_config(); +xnn_get_f16_rsqrt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_sigmoid_config(); +xnn_get_f16_sigmoid_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_sine_config(); +xnn_get_f16_sine_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_sqr_config(); +xnn_get_f16_sqr_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_sqrt_config(); +xnn_get_f16_sqrt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_tanh_config(); +xnn_get_f16_tanh_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_to_f32_cvt_config(); +xnn_get_f16_to_f32_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_to_qs8_cvt_config(); +xnn_get_f16_to_qs8_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f16_to_qu8_cvt_config(); +xnn_get_f16_to_qu8_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_abs_config(); +xnn_get_f32_abs_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_approxgelu_config(uint32_t flags); +xnn_get_f32_approxgelu_config(uint32_t flags); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_clamp_config(); +xnn_get_f32_clamp_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_cosine_config(uint32_t flags); +xnn_get_f32_cosine_config(uint32_t flags); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_elu_config(); +xnn_get_f32_elu_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_exp_config(uint32_t flags); +xnn_get_f32_exp_config(uint32_t flags); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_gelu_config(uint32_t flags); +xnn_get_f32_gelu_config(uint32_t flags); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_hswish_config(uint32_t flags); +xnn_get_f32_hswish_config(uint32_t flags); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_log_config(uint32_t flags); +xnn_get_f32_log_config(uint32_t flags); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_lrelu_config(); +xnn_get_f32_lrelu_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_neg_config(); +xnn_get_f32_neg_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_rndd_config(); +xnn_get_f32_rndd_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_rndne_config(); +xnn_get_f32_rndne_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_rndu_config(); +xnn_get_f32_rndu_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_rndz_config(); +xnn_get_f32_rndz_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_rsqrt_config(uint32_t flags); +xnn_get_f32_rsqrt_config(uint32_t flags); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_sigmoid_config(); +xnn_get_f32_sigmoid_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_sine_config(uint32_t flags); +xnn_get_f32_sine_config(uint32_t flags); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_sqr_config(); +xnn_get_f32_sqr_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_sqrt_config(uint32_t flags); +xnn_get_f32_sqrt_config(uint32_t flags); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_tanh_config(uint32_t flags); +xnn_get_f32_tanh_config(uint32_t flags); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_to_f16_cvt_config(); +xnn_get_f32_to_f16_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_to_qp8_cvt_config(); +xnn_get_f32_to_qp8_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_to_qs8_cvt_config(); +xnn_get_f32_to_qs8_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_f32_to_qu8_cvt_config(); +xnn_get_f32_to_qu8_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_qs16_to_qs8_cvt_config(); +xnn_get_qs16_to_qs8_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_qs8_cvt_config(); +xnn_get_qs8_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_qs8_lrelu_config(); +xnn_get_qs8_lrelu_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_qs8_to_f16_cvt_config(); +xnn_get_qs8_to_f16_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_qs8_to_f32_cvt_config(); +xnn_get_qs8_to_f32_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_qu8_cvt_config(); +xnn_get_qu8_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_qu8_lrelu_config(); +xnn_get_qu8_lrelu_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_qu8_to_f32_cvt_config(); +xnn_get_qu8_to_f32_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_s32_to_f32_cvt_config(); +xnn_get_s32_to_f32_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_s8_clamp_config(); +xnn_get_s8_clamp_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_u32_to_f32_cvt_config(); +xnn_get_u32_to_f32_cvt_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_u8_clamp_config(); +xnn_get_u8_clamp_config(); XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_xx_copy_config(); +xnn_get_xx_copy_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_f16_f32acc_rsum_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_f16_rmax_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_f16_rminmax_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_f16_rmin_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_f32_rmax_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_f32_rminmax_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_f32_rmin_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_f32_rsum_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_s8_rmax_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_s8_rminmax_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_s8_rmin_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_u8_rmax_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_u8_rminmax_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_u8_rmin_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_qs8_rsum_config(); -XNN_INTERNAL const struct xnn_reduce_config* xnn_init_qu8_rsum_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_f16_f32acc_rsum_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_f16_rmax_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_f16_rminmax_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_f16_rmin_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_f32_rmax_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_f32_rminmax_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_f32_rmin_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_f32_rsum_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_s8_rmax_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_s8_rminmax_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_s8_rmin_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_u8_rmax_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_u8_rminmax_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_u8_rmin_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_qs8_rsum_config(); +XNN_INTERNAL const struct xnn_reduce_config* xnn_get_qu8_rsum_config(); -XNN_INTERNAL const struct xnn_xx_fill_config* xnn_init_xx_fill_config(); +XNN_INTERNAL const struct xnn_xx_fill_config* xnn_get_xx_fill_config(); -XNN_INTERNAL const struct xnn_xx_pad_config* xnn_init_xx_pad_config(); +XNN_INTERNAL const struct xnn_xx_pad_config* xnn_get_xx_pad_config(); -XNN_INTERNAL const struct xnn_avgpool_config* xnn_init_f16_avgpool_config(); -XNN_INTERNAL const struct xnn_avgpool_config* xnn_init_f32_avgpool_config(); +XNN_INTERNAL const struct xnn_avgpool_config* xnn_get_f16_avgpool_config(); +XNN_INTERNAL const struct xnn_avgpool_config* xnn_get_f32_avgpool_config(); -XNN_INTERNAL const struct xnn_avgpool_config* xnn_init_f16_pavgpool_config(); -XNN_INTERNAL const struct xnn_avgpool_config* xnn_init_f32_pavgpool_config(); +XNN_INTERNAL const struct xnn_avgpool_config* xnn_get_f16_pavgpool_config(); +XNN_INTERNAL const struct xnn_avgpool_config* xnn_get_f32_pavgpool_config(); #define XNN_MAX_F16_DWCONV_UKERNELS 4 #define XNN_MAX_F32_DWCONV_UKERNELS 4 @@ -243,23 +243,23 @@ XNN_INTERNAL const struct xnn_avgpool_config* xnn_init_f32_pavgpool_config(); #define XNN_MAX_QS8_DWCONV_UKERNELS 2 #define XNN_MAX_QU8_DWCONV_UKERNELS 2 -XNN_INTERNAL const struct xnn_dwconv_config* xnn_init_f16_dwconv_config(); -XNN_INTERNAL const struct xnn_dwconv_config* xnn_init_f32_dwconv_config(); -XNN_INTERNAL const struct xnn_dwconv_config* xnn_init_qs8_qc8w_dwconv_config(); -XNN_INTERNAL const struct xnn_dwconv_config* xnn_init_qs8_dwconv_config(); -XNN_INTERNAL const struct xnn_dwconv_config* xnn_init_qu8_dwconv_config(); +XNN_INTERNAL const struct xnn_dwconv_config* xnn_get_f16_dwconv_config(); +XNN_INTERNAL const struct xnn_dwconv_config* xnn_get_f32_dwconv_config(); +XNN_INTERNAL const struct xnn_dwconv_config* xnn_get_qs8_qc8w_dwconv_config(); +XNN_INTERNAL const struct xnn_dwconv_config* xnn_get_qs8_dwconv_config(); +XNN_INTERNAL const struct xnn_dwconv_config* xnn_get_qu8_dwconv_config(); // Bilinear interpolation (2D). -XNN_INTERNAL const struct xnn_ibilinear_config* xnn_init_f16_ibilinear_config(); -XNN_INTERNAL const struct xnn_ibilinear_config* xnn_init_f32_ibilinear_config(); -XNN_INTERNAL const struct xnn_ibilinear_config* xnn_init_s8_ibilinear_config(); -XNN_INTERNAL const struct xnn_ibilinear_config* xnn_init_u8_ibilinear_config(); +XNN_INTERNAL const struct xnn_ibilinear_config* xnn_get_f16_ibilinear_config(); +XNN_INTERNAL const struct xnn_ibilinear_config* xnn_get_f32_ibilinear_config(); +XNN_INTERNAL const struct xnn_ibilinear_config* xnn_get_s8_ibilinear_config(); +XNN_INTERNAL const struct xnn_ibilinear_config* xnn_get_u8_ibilinear_config(); // Bilinear interpolation (2D) in CHW layout. XNN_INTERNAL const struct xnn_ibilinear_chw_config* -xnn_init_f16_ibilinear_chw_config(); +xnn_get_f16_ibilinear_chw_config(); XNN_INTERNAL const struct xnn_ibilinear_chw_config* -xnn_init_f32_ibilinear_chw_config(); +xnn_get_f32_ibilinear_chw_config(); static inline struct xnn_hmp_dqgemm_ukernel xnn_init_hmp_dqgemm_ukernel( xnn_dqgemm_ukernel_fn function) { @@ -352,76 +352,76 @@ static inline bool xnn_is_hmp_igemm_ukernel( #endif } -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_bf16_f32_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_f16_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_f32_gemm_config(uint32_t flags); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_f32_gemm_nr2_config(uint32_t flags); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_f32_igemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_f32_qc8w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_f32_qc4w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_pf16_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_pf32_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_pqs8_qc8w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qd8_f16_qb4w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qd8_f16_qc4w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qd8_f16_qc8w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qd8_f16_qc8w_igemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qd8_f32_qb4w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qd8_f32_qc4w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qd8_f32_qc8w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qp8_f32_qc4w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qp8_f32_qc8w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qp8_f32_qb4w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qdu8_f32_qc4w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qdu8_f16_qc8w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qdu8_f32_qc8w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qdu8_f32_qb4w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qdu8_f16_qc4w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_bf16_f32_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_f16_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_f32_gemm_config(uint32_t flags); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_f32_gemm_nr2_config(uint32_t flags); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_f32_igemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_f32_qc8w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_f32_qc4w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_pf16_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_pf32_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_pqs8_qc8w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qd8_f16_qb4w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qd8_f16_qc4w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qd8_f16_qc8w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qd8_f16_qc8w_igemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qd8_f32_qb4w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qd8_f32_qc4w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qd8_f32_qc8w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qp8_f32_qc4w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qp8_f32_qc8w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qp8_f32_qb4w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qdu8_f32_qc4w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qdu8_f16_qc8w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qdu8_f32_qc8w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qdu8_f32_qb4w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qdu8_f16_qc4w_gemm_config(); XNN_INTERNAL const struct xnn_gemm_config* -xnn_init_qdu8_f32_qc8w_igemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qs8_qc4w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qs8_qc8w_gemm_config(); -XNN_INTERNAL const struct xnn_gemm_config* xnn_init_qu8_gemm_config(); +xnn_get_qdu8_f32_qc8w_igemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qs8_qc4w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qs8_qc8w_gemm_config(); +XNN_INTERNAL const struct xnn_gemm_config* xnn_get_qu8_gemm_config(); -XNN_INTERNAL const struct xnn_maxpool_config* xnn_init_f16_maxpool_config(); -XNN_INTERNAL const struct xnn_maxpool_config* xnn_init_f32_maxpool_config(); -XNN_INTERNAL const struct xnn_maxpool_config* xnn_init_s8_maxpool_config(); -XNN_INTERNAL const struct xnn_maxpool_config* xnn_init_u8_maxpool_config(); +XNN_INTERNAL const struct xnn_maxpool_config* xnn_get_f16_maxpool_config(); +XNN_INTERNAL const struct xnn_maxpool_config* xnn_get_f32_maxpool_config(); +XNN_INTERNAL const struct xnn_maxpool_config* xnn_get_s8_maxpool_config(); +XNN_INTERNAL const struct xnn_maxpool_config* xnn_get_u8_maxpool_config(); // Sparse Matrix-Dense Matrix Multiplication (NR=1 block). -XNN_INTERNAL const struct xnn_spmm_config* xnn_init_f16_spmm_config(); -XNN_INTERNAL const struct xnn_spmm_config* xnn_init_f32_spmm_config(); +XNN_INTERNAL const struct xnn_spmm_config* xnn_get_f16_spmm_config(); +XNN_INTERNAL const struct xnn_spmm_config* xnn_get_f32_spmm_config(); // Sparse Matrix-Dense Matrix Multiplication (NR=2 block). -XNN_INTERNAL const struct xnn_spmm_config* xnn_init_f32_spmm2_config(); +XNN_INTERNAL const struct xnn_spmm_config* xnn_get_f32_spmm2_config(); // Sparse Matrix-Dense Matrix Multiplication (NR=4 block). -XNN_INTERNAL const struct xnn_spmm_config* xnn_init_f32_spmm4_config(); +XNN_INTERNAL const struct xnn_spmm_config* xnn_get_f32_spmm4_config(); XNN_INTERNAL const struct xnn_dwconv2d_chw_config* -xnn_init_f16_dwconv2d_chw_config(); +xnn_get_f16_dwconv2d_chw_config(); XNN_INTERNAL const struct xnn_dwconv2d_chw_config* -xnn_init_f32_dwconv2d_chw_config(); +xnn_get_f32_dwconv2d_chw_config(); // Direct 3x3 stride-2 Convolution with 3 input channels and HWC->CHW layout // conversion. XNN_INTERNAL const struct xnn_conv_hwc2chw_config* -xnn_init_f16_conv_hwc2chw_3x3c3s2_config(); +xnn_get_f16_conv_hwc2chw_3x3c3s2_config(); XNN_INTERNAL const struct xnn_conv_hwc2chw_config* -xnn_init_f32_conv_hwc2chw_3x3c3s2_config(); +xnn_get_f32_conv_hwc2chw_3x3c3s2_config(); -XNN_INTERNAL const struct xnn_vmulcaddc_config* xnn_init_f16_vmulcaddc_config(); -XNN_INTERNAL const struct xnn_vmulcaddc_config* xnn_init_f32_vmulcaddc_config(); +XNN_INTERNAL const struct xnn_vmulcaddc_config* xnn_get_f16_vmulcaddc_config(); +XNN_INTERNAL const struct xnn_vmulcaddc_config* xnn_get_f32_vmulcaddc_config(); XNN_INTERNAL const struct xnn_raddstoreexpminusmax_config* -xnn_init_f16_raddstoreexpminusmax_config(); +xnn_get_f16_raddstoreexpminusmax_config(); XNN_INTERNAL const struct xnn_raddstoreexpminusmax_config* -xnn_init_f32_raddstoreexpminusmax_config(); +xnn_get_f32_raddstoreexpminusmax_config(); XNN_INTERNAL const struct xnn_argmaxpool_config* -xnn_init_f32_argmaxpool_config(); +xnn_get_f32_argmaxpool_config(); -XNN_INTERNAL const struct xnn_lut32norm_config* xnn_init_u8_lut32norm_config(); +XNN_INTERNAL const struct xnn_lut32norm_config* xnn_get_u8_lut32norm_config(); -XNN_INTERNAL const struct xnn_unpool_config* xnn_init_x32_unpool_config(); +XNN_INTERNAL const struct xnn_unpool_config* xnn_get_x32_unpool_config(); #ifdef __cplusplus } // extern "C" diff --git a/src/xnnpack/hardware-config.h b/src/xnnpack/hardware-config.h index 8c5e19f986b..3912281b5d3 100644 --- a/src/xnnpack/hardware-config.h +++ b/src/xnnpack/hardware-config.h @@ -102,7 +102,7 @@ struct xnn_hardware_config { size_t l2_data_cache_num_sets; }; -XNN_INTERNAL const struct xnn_hardware_config* xnn_init_hardware_config(); +XNN_INTERNAL const struct xnn_hardware_config* xnn_get_hardware_config(); static inline bool xnn_is_bf16_compatible_config( const struct xnn_hardware_config* hardware_config) { diff --git a/src/xnnpack/isa-checks.h b/src/xnnpack/isa-checks.h index 802f0d848c5..5099ff84494 100644 --- a/src/xnnpack/isa-checks.h +++ b/src/xnnpack/isa-checks.h @@ -17,7 +17,7 @@ inline size_t get_batch_scale(size_t element_size) { #if XNN_ARCH_RISCV const struct xnn_hardware_config* hardware_config = - xnn_init_hardware_config(); + xnn_get_hardware_config(); return hardware_config ? std::max(1, hardware_config->vlenb / element_size) : 1; @@ -34,7 +34,7 @@ size_t get_batch_scale() { #define TEST_REQUIRES_ARCH_FLAGS(FLAGS) \ do { \ const struct xnn_hardware_config* hardware_config = \ - xnn_init_hardware_config(); \ + xnn_get_hardware_config(); \ if (hardware_config == nullptr || \ (hardware_config->arch_flags & (FLAGS)) != (FLAGS)) { \ GTEST_SKIP(); \ diff --git a/src/xnnpack/reference-config.h b/src/xnnpack/reference-config.h index 8e6fa5587a0..0e6ed4ac6d9 100644 --- a/src/xnnpack/reference-config.h +++ b/src/xnnpack/reference-config.h @@ -17,11 +17,11 @@ extern "C" { #endif XNN_INTERNAL const struct xnn_unary_elementwise_config* -xnn_init_unary_reference_config(enum xnn_unary_operator op, +xnn_get_unary_reference_config(enum xnn_unary_operator op, enum xnn_datatype input_datatype, enum xnn_datatype output_datatype); XNN_INTERNAL const struct xnn_binary_elementwise_config* -xnn_init_binary_reference_config(enum xnn_binary_operator op, +xnn_get_binary_reference_config(enum xnn_binary_operator op, enum xnn_datatype datatype); #ifdef __cplusplus diff --git a/test/f32-argmaxpool.cc b/test/f32-argmaxpool.cc index 41fdee9eaf6..1843d53d575 100644 --- a/test/f32-argmaxpool.cc +++ b/test/f32-argmaxpool.cc @@ -346,7 +346,7 @@ #if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_eq_1v_onetile) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); ArgMaxPoolMicrokernelTester() .pooling_elements(9) .channels(channel_tile) @@ -355,7 +355,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_eq_1v_onetile_with_input_offset) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); ArgMaxPoolMicrokernelTester() .pooling_elements(9) .channels(channel_tile) @@ -365,7 +365,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_eq_1v_subtile) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) { ArgMaxPoolMicrokernelTester() .pooling_elements(pooling_elements) @@ -376,7 +376,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_eq_1v_subtile_with_input_offset) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) { ArgMaxPoolMicrokernelTester() .pooling_elements(pooling_elements) @@ -388,7 +388,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_eq_1v_multitile) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t pooling_elements = 2; pooling_elements <= 3 * 9; pooling_elements++) { ArgMaxPoolMicrokernelTester() .pooling_elements(pooling_elements) @@ -399,7 +399,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_eq_1v_multitile_with_input_offset) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t pooling_elements = 2; pooling_elements <= 3 * 9; pooling_elements++) { ArgMaxPoolMicrokernelTester() .pooling_elements(pooling_elements) @@ -411,7 +411,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_div_1v_onetile) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = channel_tile * 2; channels < channel_tile * 3; channels += channel_tile) { ArgMaxPoolMicrokernelTester() .pooling_elements(9) @@ -422,7 +422,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_div_1v_onetile_with_input_offset) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = channel_tile * 2; channels < channel_tile * 3; channels += channel_tile) { ArgMaxPoolMicrokernelTester() .pooling_elements(9) @@ -435,7 +435,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_div_1v_subtile) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) { - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = channel_tile * 2; channels < channel_tile * 3; channels += channel_tile) { ArgMaxPoolMicrokernelTester() .pooling_elements(pooling_elements) @@ -448,7 +448,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_div_1v_subtile_with_input_offset) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) { - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = channel_tile * 2; channels < channel_tile * 3; channels += channel_tile) { ArgMaxPoolMicrokernelTester() .pooling_elements(pooling_elements) @@ -462,7 +462,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_div_1v_multitile) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t pooling_elements = 2; pooling_elements <= 3 * 9; pooling_elements++) { - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = channel_tile * 2; channels < channel_tile * 3; channels += channel_tile) { ArgMaxPoolMicrokernelTester() .pooling_elements(pooling_elements) @@ -475,7 +475,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_div_1v_multitile_with_input_offset) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t pooling_elements = 2; pooling_elements <= 3 * 9; pooling_elements++) { - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = channel_tile * 2; channels < channel_tile * 3; channels += channel_tile) { ArgMaxPoolMicrokernelTester() .pooling_elements(pooling_elements) @@ -488,7 +488,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_lt_1v_onetile) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = 1; channels < channel_tile; channels++) { ArgMaxPoolMicrokernelTester() .pooling_elements(9) @@ -499,7 +499,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_lt_1v_onetile_with_input_offset) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = 1; channels < channel_tile; channels++) { ArgMaxPoolMicrokernelTester() .pooling_elements(9) @@ -511,7 +511,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_lt_1v_subtile) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) { for (size_t channels = 1; channels < channel_tile; channels++) { ArgMaxPoolMicrokernelTester() @@ -524,7 +524,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_lt_1v_subtile_with_input_offset) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) { for (size_t channels = 1; channels < channel_tile; channels++) { ArgMaxPoolMicrokernelTester() @@ -538,7 +538,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_gt_1v_onetile) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = channel_tile+1; channels < channel_tile * 2; channels++) { ArgMaxPoolMicrokernelTester() .pooling_elements(9) @@ -549,7 +549,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_gt_1v_onetile_with_input_offset) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = channel_tile+1; channels < channel_tile * 2; channels++) { ArgMaxPoolMicrokernelTester() .pooling_elements(9) @@ -562,7 +562,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_gt_1v_subtile) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) { - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = channel_tile+1; channels < channel_tile * 2; channels++) { ArgMaxPoolMicrokernelTester() .pooling_elements(pooling_elements) @@ -575,7 +575,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_gt_1v_subtile_with_input_offset) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) { - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = channel_tile+1; channels < channel_tile * 2; channels++) { ArgMaxPoolMicrokernelTester() .pooling_elements(pooling_elements) @@ -589,7 +589,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_gt_1v_multitile) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t pooling_elements = 2; pooling_elements <= 3 * 9; pooling_elements++) { - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = channel_tile+1; channels < channel_tile * 2; channels++) { ArgMaxPoolMicrokernelTester() .pooling_elements(pooling_elements) @@ -602,7 +602,7 @@ TEST(F32_ARGMAXPOOL_9P8X__RVV_U1V, channels_gt_1v_multitile_with_input_offset) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t pooling_elements = 2; pooling_elements <= 3 * 9; pooling_elements++) { - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = channel_tile+1; channels < channel_tile * 2; channels++) { ArgMaxPoolMicrokernelTester() .pooling_elements(pooling_elements) @@ -617,7 +617,7 @@ TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) { for (size_t pooling_elements = 2; pooling_elements <= 25; pooling_elements = xnnpack::NextPrime(pooling_elements)) { - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = 1; channels <= channel_tile * 5; channels += channel_tile-1) { ArgMaxPoolMicrokernelTester() .output_pixels(output_pixels) @@ -633,7 +633,7 @@ TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) { for (size_t pooling_elements = 2; pooling_elements <= 25; pooling_elements = xnnpack::NextPrime(pooling_elements)) { - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = 1; channels <= channel_tile * 5; channels += channel_tile-1) { ArgMaxPoolMicrokernelTester() .output_pixels(output_pixels) @@ -650,7 +650,7 @@ TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) { for (size_t pooling_elements = 2; pooling_elements <= 25; pooling_elements = xnnpack::NextPrime(pooling_elements)) { - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = 1; channels <= channel_tile * 5; channels += channel_tile-1) { ArgMaxPoolMicrokernelTester() .output_pixels(output_pixels) @@ -667,7 +667,7 @@ TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) { for (size_t pooling_elements = 2; pooling_elements <= 25; pooling_elements = xnnpack::NextPrime(pooling_elements)) { - const size_t channel_tile = (1 * xnn_init_hardware_config()->vlenb / sizeof(float)); + const size_t channel_tile = (1 * xnn_get_hardware_config()->vlenb / sizeof(float)); for (size_t channels = 1; channels <= channel_tile * 5; channels += channel_tile-1) { for (size_t step = 2; step <= pooling_elements; step++) { ArgMaxPoolMicrokernelTester() diff --git a/test/f32-conv-hwc2chw.cc b/test/f32-conv-hwc2chw.cc index d6260e2c41c..27940b3a87e 100644 --- a/test/f32-conv-hwc2chw.cc +++ b/test/f32-conv-hwc2chw.cc @@ -1644,8 +1644,8 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) - .output_channels(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) + .output_channels(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .input_width(1) .input_height(3) .Test(xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_1x1, xnn_init_f32_minmax_scalar_params); @@ -1659,8 +1659,8 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) - .output_channels(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) + .output_channels(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .input_width(input_width) .input_height(3) .Test(xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_1x1, xnn_init_f32_minmax_scalar_params); @@ -1669,7 +1669,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_1X1, output_channels_lt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = 1; output_channels < output_channels_tile; output_channels++) { for (size_t input_width = 1; input_width < 8; input_width += 1) { ConvHWC2CHWMicrokernelTester() @@ -1677,7 +1677,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(3) @@ -1688,7 +1688,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_1X1, output_channels_div_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = output_channels_tile * 2; output_channels <= output_channels_tile * 4; output_channels += output_channels_tile) { for (size_t input_width = 1; input_width < 8; input_width += 1) { ConvHWC2CHWMicrokernelTester() @@ -1696,7 +1696,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(3) @@ -1707,7 +1707,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_1X1, output_channels_gt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = output_channels_tile + 1; output_channels < output_channels_tile * 2; output_channels++) { for (size_t input_width = 1; input_width < 8; input_width += 1) { ConvHWC2CHWMicrokernelTester() @@ -1715,7 +1715,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(3) @@ -1726,7 +1726,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_1X1, input_height_lt_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 3; input_height++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 8; input_width += 1) { @@ -1735,7 +1735,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding(1) // padded input height of at least 3 required .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(input_height) @@ -1747,7 +1747,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_1X1, input_height_gt_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 4; input_height <= 9; input_height++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 8; input_width += 1) { @@ -1756,7 +1756,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(input_height) @@ -1768,7 +1768,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_1X1, padding_top) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t padding_top = 0; padding_top <= 1; padding_top++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 4; output_channels += output_channels_tile * 2 - 1) { for (size_t input_width = 1; input_width < 8; input_width += 1) { @@ -1778,7 +1778,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .padding_width(1) .padding_top(padding_top) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(9) @@ -1790,7 +1790,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_1X1, padding_bottom) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t padding_bottom = 0; padding_bottom <= 1; padding_bottom++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 4; output_channels += output_channels_tile * 2 - 1) { for (size_t input_width = 1; input_width < 8; input_width += 1) { @@ -1800,7 +1800,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .padding_width(1) .padding_bottom(padding_bottom) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(9) @@ -1812,7 +1812,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_1X1, output_y_start) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_y_start = 1; output_y_start <= 3; output_y_start++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 8; input_width += 1) { @@ -1821,7 +1821,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(9) @@ -1834,7 +1834,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_1X1, output_y_end) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_y_end = 2; output_y_end < 5; output_y_end++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 8; input_width += 1) { @@ -1843,7 +1843,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(9) @@ -1856,7 +1856,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_1X1, qmin) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 8; input_width += 1) { ConvHWC2CHWMicrokernelTester() @@ -1864,7 +1864,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(6) @@ -1876,7 +1876,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_1X1, qmax) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 8; input_width += 1) { ConvHWC2CHWMicrokernelTester() @@ -1884,7 +1884,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(6) @@ -1904,8 +1904,8 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) - .output_channels(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) + .output_channels(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .input_width(2) .input_height(3) .Test(xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x1, xnn_init_f32_minmax_scalar_params); @@ -1919,8 +1919,8 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) - .output_channels(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) + .output_channels(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .input_width(input_width) .input_height(3) .Test(xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x1, xnn_init_f32_minmax_scalar_params); @@ -1935,8 +1935,8 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) - .output_channels(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) + .output_channels(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .input_width(input_width) .input_height(3) .Test(xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x1, xnn_init_f32_minmax_scalar_params); @@ -1951,8 +1951,8 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) - .output_channels(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) + .output_channels(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .input_width(input_width) .input_height(3) .Test(xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x1, xnn_init_f32_minmax_scalar_params); @@ -1961,7 +1961,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X1, output_channels_lt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = 1; output_channels < output_channels_tile; output_channels++) { for (size_t input_width = 1; input_width < 16; input_width += 3) { ConvHWC2CHWMicrokernelTester() @@ -1969,7 +1969,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(3) @@ -1980,7 +1980,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X1, output_channels_div_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = output_channels_tile * 2; output_channels <= output_channels_tile * 4; output_channels += output_channels_tile) { for (size_t input_width = 1; input_width < 16; input_width += 3) { ConvHWC2CHWMicrokernelTester() @@ -1988,7 +1988,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(3) @@ -1999,7 +1999,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X1, output_channels_gt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = output_channels_tile + 1; output_channels < output_channels_tile * 2; output_channels++) { for (size_t input_width = 1; input_width < 16; input_width += 3) { ConvHWC2CHWMicrokernelTester() @@ -2007,7 +2007,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(3) @@ -2018,7 +2018,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X1, input_height_lt_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 3; input_height++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 16; input_width += 3) { @@ -2027,7 +2027,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding(1) // padded input height of at least 3 required .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(input_height) @@ -2039,7 +2039,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X1, input_height_gt_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 4; input_height <= 9; input_height++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 16; input_width += 3) { @@ -2048,7 +2048,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(input_height) @@ -2060,7 +2060,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X1, padding_top) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t padding_top = 0; padding_top <= 1; padding_top++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 4; output_channels += output_channels_tile * 2 - 1) { for (size_t input_width = 1; input_width < 16; input_width += 3) { @@ -2070,7 +2070,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .padding_width(1) .padding_top(padding_top) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(9) @@ -2082,7 +2082,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X1, padding_bottom) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t padding_bottom = 0; padding_bottom <= 1; padding_bottom++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 4; output_channels += output_channels_tile * 2 - 1) { for (size_t input_width = 1; input_width < 16; input_width += 3) { @@ -2092,7 +2092,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .padding_width(1) .padding_bottom(padding_bottom) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(9) @@ -2104,7 +2104,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X1, output_y_start) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_y_start = 1; output_y_start <= 3; output_y_start++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 16; input_width += 3) { @@ -2113,7 +2113,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(9) @@ -2126,7 +2126,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X1, output_y_end) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_y_end = 2; output_y_end < 5; output_y_end++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 16; input_width += 3) { @@ -2135,7 +2135,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(9) @@ -2148,7 +2148,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X1, qmin) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 16; input_width += 3) { ConvHWC2CHWMicrokernelTester() @@ -2156,7 +2156,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(6) @@ -2168,7 +2168,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X1, qmax) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 16; input_width += 3) { ConvHWC2CHWMicrokernelTester() @@ -2176,7 +2176,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(6) @@ -2196,8 +2196,8 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) - .output_channels(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) + .output_channels(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .input_width(4) .input_height(3) .Test(xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x2, xnn_init_f32_minmax_scalar_params); @@ -2211,8 +2211,8 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) - .output_channels(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) + .output_channels(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .input_width(input_width) .input_height(3) .Test(xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x2, xnn_init_f32_minmax_scalar_params); @@ -2227,8 +2227,8 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) - .output_channels(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) + .output_channels(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .input_width(input_width) .input_height(3) .Test(xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x2, xnn_init_f32_minmax_scalar_params); @@ -2243,8 +2243,8 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) - .output_channels(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) + .output_channels(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .input_width(input_width) .input_height(3) .Test(xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x2, xnn_init_f32_minmax_scalar_params); @@ -2253,7 +2253,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X2, output_channels_lt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = 1; output_channels < output_channels_tile; output_channels++) { for (size_t input_width = 1; input_width < 32; input_width += 7) { ConvHWC2CHWMicrokernelTester() @@ -2261,7 +2261,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(3) @@ -2272,7 +2272,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X2, output_channels_div_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = output_channels_tile * 2; output_channels <= output_channels_tile * 4; output_channels += output_channels_tile) { for (size_t input_width = 1; input_width < 32; input_width += 7) { ConvHWC2CHWMicrokernelTester() @@ -2280,7 +2280,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(3) @@ -2291,7 +2291,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X2, output_channels_gt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = output_channels_tile + 1; output_channels < output_channels_tile * 2; output_channels++) { for (size_t input_width = 1; input_width < 32; input_width += 7) { ConvHWC2CHWMicrokernelTester() @@ -2299,7 +2299,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(3) @@ -2310,7 +2310,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X2, input_height_lt_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 3; input_height++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 32; input_width += 7) { @@ -2319,7 +2319,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding(1) // padded input height of at least 3 required .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(input_height) @@ -2331,7 +2331,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X2, input_height_gt_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 4; input_height <= 9; input_height++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 32; input_width += 7) { @@ -2340,7 +2340,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(input_height) @@ -2352,7 +2352,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X2, padding_top) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t padding_top = 0; padding_top <= 1; padding_top++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 4; output_channels += output_channels_tile * 2 - 1) { for (size_t input_width = 1; input_width < 32; input_width += 7) { @@ -2362,7 +2362,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .padding_width(1) .padding_top(padding_top) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(9) @@ -2374,7 +2374,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X2, padding_bottom) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t padding_bottom = 0; padding_bottom <= 1; padding_bottom++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 4; output_channels += output_channels_tile * 2 - 1) { for (size_t input_width = 1; input_width < 32; input_width += 7) { @@ -2384,7 +2384,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .padding_width(1) .padding_bottom(padding_bottom) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(9) @@ -2396,7 +2396,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X2, output_y_start) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_y_start = 1; output_y_start <= 3; output_y_start++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 32; input_width += 7) { @@ -2405,7 +2405,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(9) @@ -2418,7 +2418,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X2, output_y_end) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_y_end = 2; output_y_end < 5; output_y_end++) { for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 32; input_width += 7) { @@ -2427,7 +2427,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(9) @@ -2440,7 +2440,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X2, qmin) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 32; input_width += 7) { ConvHWC2CHWMicrokernelTester() @@ -2448,7 +2448,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(6) @@ -2460,7 +2460,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { TEST(F32_CONV_HWC2CHW_3X3S2P1C3X2V__RVV_2X2, qmax) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t output_channels_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t output_channels_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t output_channels = 1; output_channels < output_channels_tile * 2; output_channels += output_channels_tile - 1) { for (size_t input_width = 1; input_width < 32; input_width += 7) { ConvHWC2CHWMicrokernelTester() @@ -2468,7 +2468,7 @@ TEST(F32_CONV_HWC2CHW_3X3S2P1C3X4__SCALAR_1X1, qmax) { .subsampling(2) .padding_width(1) .input_channels(3) - .output_channels_tile(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .output_channels_tile(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .output_channels(output_channels) .input_width(input_width) .input_height(6) diff --git a/test/f32-dwconv2d-chw.cc b/test/f32-dwconv2d-chw.cc index b25dcea4c44..3553f63ee96 100644 --- a/test/f32-dwconv2d-chw.cc +++ b/test/f32-dwconv2d-chw.cc @@ -37543,7 +37543,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_5X1V, output_width_eq_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); DWConv2DMicrokernelTester() - .input_width((1 * xnn_init_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) + .input_width((1 * xnn_get_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) .input_height(5) .kernel_height(3) .kernel_width(3) @@ -37557,7 +37557,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_5X1V, output_width_div_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 1 + 0; input_width < 8 * width_tile * 1 + 0; input_width += 1) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -37575,7 +37575,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_5X1V, output_width_lt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(1) @@ -37593,7 +37593,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_5X1V, output_width_gt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 1 + 1; input_width < 2 * width_tile * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -37611,7 +37611,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_5X1V, output_height_div_5) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 10; input_height < 40; input_height += 5) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -37631,7 +37631,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_5X1V, output_height_lt_5) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 5; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -37651,7 +37651,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_5X1V, output_height_gt_5) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 6; input_height < 26; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -37675,7 +37675,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_6X1V, output_width_eq_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); DWConv2DMicrokernelTester() - .input_width((1 * xnn_init_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) + .input_width((1 * xnn_get_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) .input_height(6) .kernel_height(3) .kernel_width(3) @@ -37689,7 +37689,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_6X1V, output_width_div_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 1 + 0; input_width < 8 * width_tile * 1 + 0; input_width += 1) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -37707,7 +37707,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_6X1V, output_width_lt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(1) @@ -37725,7 +37725,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_6X1V, output_width_gt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 1 + 1; input_width < 2 * width_tile * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -37743,7 +37743,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_6X1V, output_height_div_6) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 12; input_height < 48; input_height += 6) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -37763,7 +37763,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_6X1V, output_height_lt_6) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 6; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -37783,7 +37783,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_6X1V, output_height_gt_6) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 7; input_height < 31; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -37807,7 +37807,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_7X1V, output_width_eq_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); DWConv2DMicrokernelTester() - .input_width((1 * xnn_init_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) + .input_width((1 * xnn_get_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) .input_height(7) .kernel_height(3) .kernel_width(3) @@ -37821,7 +37821,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_7X1V, output_width_div_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 1 + 0; input_width < 8 * width_tile * 1 + 0; input_width += 1) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -37839,7 +37839,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_7X1V, output_width_lt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(1) @@ -37857,7 +37857,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_7X1V, output_width_gt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 1 + 1; input_width < 2 * width_tile * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -37875,7 +37875,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_7X1V, output_height_div_7) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 14; input_height < 56; input_height += 7) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -37895,7 +37895,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_7X1V, output_height_lt_7) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 7; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -37915,7 +37915,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_7X1V, output_height_gt_7) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 8; input_height < 36; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -37939,7 +37939,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_8X1V, output_width_eq_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); DWConv2DMicrokernelTester() - .input_width((1 * xnn_init_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) + .input_width((1 * xnn_get_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) .input_height(8) .kernel_height(3) .kernel_width(3) @@ -37953,7 +37953,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_8X1V, output_width_div_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 1 + 0; input_width < 8 * width_tile * 1 + 0; input_width += 1) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -37971,7 +37971,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_8X1V, output_width_lt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(1) @@ -37989,7 +37989,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_8X1V, output_width_gt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 1 + 1; input_width < 2 * width_tile * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38007,7 +38007,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_8X1V, output_height_div_8) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 16; input_height < 64; input_height += 8) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38027,7 +38027,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_8X1V, output_height_lt_8) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 8; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38047,7 +38047,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_8X1V, output_height_gt_8) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 9; input_height < 41; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38071,7 +38071,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_1X2V, output_width_eq_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); DWConv2DMicrokernelTester() - .input_width((2 * xnn_init_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) + .input_width((2 * xnn_get_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) .input_height(1) .kernel_height(3) .kernel_width(3) @@ -38085,7 +38085,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_1X2V, output_width_div_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 1 + 0; input_width < 8 * width_tile * 1 + 0; input_width += 2) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38103,7 +38103,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_1X2V, output_width_lt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(2) @@ -38121,7 +38121,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_1X2V, output_width_gt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 1 + 1; input_width < 2 * width_tile * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38139,7 +38139,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_1X2V, output_height_gt_1) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 2; input_height < 3; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38163,7 +38163,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_2X2V, output_width_eq_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); DWConv2DMicrokernelTester() - .input_width((2 * xnn_init_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) + .input_width((2 * xnn_get_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) .input_height(2) .kernel_height(3) .kernel_width(3) @@ -38177,7 +38177,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_2X2V, output_width_div_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 1 + 0; input_width < 8 * width_tile * 1 + 0; input_width += 2) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38195,7 +38195,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_2X2V, output_width_lt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(2) @@ -38213,7 +38213,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_2X2V, output_width_gt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 1 + 1; input_width < 2 * width_tile * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38231,7 +38231,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_2X2V, output_height_div_2) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 4; input_height < 16; input_height += 2) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38251,7 +38251,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_2X2V, output_height_lt_2) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 2; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38271,7 +38271,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_2X2V, output_height_gt_2) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 3; input_height < 5; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38295,7 +38295,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_3X2V, output_width_eq_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); DWConv2DMicrokernelTester() - .input_width((2 * xnn_init_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) + .input_width((2 * xnn_get_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) .input_height(3) .kernel_height(3) .kernel_width(3) @@ -38309,7 +38309,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_3X2V, output_width_div_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 1 + 0; input_width < 8 * width_tile * 1 + 0; input_width += 2) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38327,7 +38327,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_3X2V, output_width_lt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(2) @@ -38345,7 +38345,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_3X2V, output_width_gt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 1 + 1; input_width < 2 * width_tile * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38363,7 +38363,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_3X2V, output_height_div_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 6; input_height < 24; input_height += 3) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38383,7 +38383,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_3X2V, output_height_lt_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 3; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38403,7 +38403,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_3X2V, output_height_gt_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 4; input_height < 7; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38427,7 +38427,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_4X2V, output_width_eq_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); DWConv2DMicrokernelTester() - .input_width((2 * xnn_init_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) + .input_width((2 * xnn_get_hardware_config()->vlenb / sizeof(float) - 1) * 1 + 1) .input_height(4) .kernel_height(3) .kernel_width(3) @@ -38441,7 +38441,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_4X2V, output_width_div_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 1 + 0; input_width < 8 * width_tile * 1 + 0; input_width += 2) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38459,7 +38459,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_4X2V, output_width_lt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(2) @@ -38477,7 +38477,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_4X2V, output_width_gt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 1 + 1; input_width < 2 * width_tile * 1 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38495,7 +38495,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_4X2V, output_height_div_4) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 8; input_height < 32; input_height += 4) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38515,7 +38515,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_4X2V, output_height_lt_4) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 4; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38535,7 +38535,7 @@ TEST(F32_DWCONV2D_CHW_3X3P1__RVV_4X2V, output_height_gt_4) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 5; input_height < 9; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 1 + 1; input_width += width_tile * 1 - 1) { DWConv2DMicrokernelTester() @@ -38558,7 +38558,7 @@ #if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_5X1V, output_width_eq_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = (width_tile - 1) * 2 + 1; input_width < width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38576,7 +38576,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_5X1V, output_width_div_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 2 + 0; input_width < 8 * width_tile * 2 + 0; input_width += 2) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38594,7 +38594,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_5X1V, output_width_lt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(2) @@ -38612,7 +38612,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_5X1V, output_width_gt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 2 + 1; input_width < 2 * width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38630,7 +38630,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_5X1V, output_height_eq_5) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 9; input_height < 11; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -38650,7 +38650,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_5X1V, output_height_div_5) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 20; input_height < 80; input_height += 10) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -38670,7 +38670,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_5X1V, output_height_lt_5) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 9; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -38690,7 +38690,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_5X1V, output_height_gt_5) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 11; input_height < 51; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -38710,7 +38710,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_5X1V, padding_top_eq_1) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 2; input_height < 32; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -38733,7 +38733,7 @@ #if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_6X1V, output_width_eq_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = (width_tile - 1) * 2 + 1; input_width < width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38751,7 +38751,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_6X1V, output_width_div_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 2 + 0; input_width < 8 * width_tile * 2 + 0; input_width += 2) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38769,7 +38769,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_6X1V, output_width_lt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(2) @@ -38787,7 +38787,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_6X1V, output_width_gt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 2 + 1; input_width < 2 * width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38805,7 +38805,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_6X1V, output_height_eq_6) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 11; input_height < 13; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -38825,7 +38825,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_6X1V, output_height_div_6) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 24; input_height < 96; input_height += 12) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -38845,7 +38845,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_6X1V, output_height_lt_6) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 11; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -38865,7 +38865,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_6X1V, output_height_gt_6) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 13; input_height < 61; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -38885,7 +38885,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_6X1V, padding_top_eq_1) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 2; input_height < 38; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -38908,7 +38908,7 @@ #if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_7X1V, output_width_eq_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = (width_tile - 1) * 2 + 1; input_width < width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38926,7 +38926,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_7X1V, output_width_div_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 2 + 0; input_width < 8 * width_tile * 2 + 0; input_width += 2) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38944,7 +38944,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_7X1V, output_width_lt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(2) @@ -38962,7 +38962,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_7X1V, output_width_gt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 2 + 1; input_width < 2 * width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -38980,7 +38980,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_7X1V, output_height_eq_7) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 13; input_height < 15; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39000,7 +39000,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_7X1V, output_height_div_7) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 28; input_height < 112; input_height += 14) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39020,7 +39020,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_7X1V, output_height_lt_7) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 13; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39040,7 +39040,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_7X1V, output_height_gt_7) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 15; input_height < 71; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39060,7 +39060,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_7X1V, padding_top_eq_1) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 2; input_height < 44; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39083,7 +39083,7 @@ #if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_8X1V, output_width_eq_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = (width_tile - 1) * 2 + 1; input_width < width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39101,7 +39101,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_8X1V, output_width_div_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 2 + 0; input_width < 8 * width_tile * 2 + 0; input_width += 2) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39119,7 +39119,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_8X1V, output_width_lt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(2) @@ -39137,7 +39137,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_8X1V, output_width_gt_1v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 2 + 1; input_width < 2 * width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39155,7 +39155,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_8X1V, output_height_eq_8) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 15; input_height < 17; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39175,7 +39175,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_8X1V, output_height_div_8) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 32; input_height < 128; input_height += 16) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39195,7 +39195,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_8X1V, output_height_lt_8) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 15; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39215,7 +39215,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_8X1V, output_height_gt_8) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 17; input_height < 81; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39235,7 +39235,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_8X1V, padding_top_eq_1) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 1 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 1 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 2; input_height < 50; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39258,7 +39258,7 @@ #if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_1X2V, output_width_eq_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = (width_tile - 1) * 2 + 1; input_width < width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39276,7 +39276,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_1X2V, output_width_div_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 2 + 0; input_width < 8 * width_tile * 2 + 0; input_width += 4) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39294,7 +39294,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_1X2V, output_width_lt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(4) @@ -39312,7 +39312,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_1X2V, output_width_gt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 2 + 1; input_width < 2 * width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39330,7 +39330,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_1X2V, output_height_eq_1) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 3; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39350,7 +39350,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_1X2V, output_height_gt_1) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 3; input_height < 5; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39370,7 +39370,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_1X2V, padding_top_eq_1) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 2; input_height < 8; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39393,7 +39393,7 @@ #if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_2X2V, output_width_eq_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = (width_tile - 1) * 2 + 1; input_width < width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39411,7 +39411,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_2X2V, output_width_div_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 2 + 0; input_width < 8 * width_tile * 2 + 0; input_width += 4) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39429,7 +39429,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_2X2V, output_width_lt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(4) @@ -39447,7 +39447,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_2X2V, output_width_gt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 2 + 1; input_width < 2 * width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39465,7 +39465,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_2X2V, output_height_eq_2) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 3; input_height < 5; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39485,7 +39485,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_2X2V, output_height_div_2) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 8; input_height < 32; input_height += 4) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39505,7 +39505,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_2X2V, output_height_lt_2) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 3; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39525,7 +39525,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_2X2V, output_height_gt_2) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 5; input_height < 9; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39545,7 +39545,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_2X2V, padding_top_eq_1) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 2; input_height < 14; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39568,7 +39568,7 @@ #if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_3X2V, output_width_eq_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = (width_tile - 1) * 2 + 1; input_width < width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39586,7 +39586,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_3X2V, output_width_div_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 2 + 0; input_width < 8 * width_tile * 2 + 0; input_width += 4) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39604,7 +39604,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_3X2V, output_width_lt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(4) @@ -39622,7 +39622,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_3X2V, output_width_gt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 2 + 1; input_width < 2 * width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39640,7 +39640,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_3X2V, output_height_eq_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 5; input_height < 7; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39660,7 +39660,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_3X2V, output_height_div_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 12; input_height < 48; input_height += 6) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39680,7 +39680,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_3X2V, output_height_lt_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 5; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39700,7 +39700,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_3X2V, output_height_gt_3) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 7; input_height < 13; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39720,7 +39720,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_3X2V, padding_top_eq_1) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 2; input_height < 20; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39743,7 +39743,7 @@ #if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_4X2V, output_width_eq_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = (width_tile - 1) * 2 + 1; input_width < width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39761,7 +39761,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_4X2V, output_width_div_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 2 * width_tile * 2 + 0; input_width < 8 * width_tile * 2 + 0; input_width += 4) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39779,7 +39779,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_4X2V, output_width_lt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = 1; input_width < (width_tile - 1) * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(4) @@ -39797,7 +39797,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_4X2V, output_width_gt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_width = width_tile * 2 + 1; input_width < 2 * width_tile * 2 + 1; input_width++) { DWConv2DMicrokernelTester() .input_width(input_width) @@ -39815,7 +39815,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_4X2V, output_height_eq_4) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 7; input_height < 9; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39835,7 +39835,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_4X2V, output_height_div_4) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 16; input_height < 64; input_height += 8) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39855,7 +39855,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_4X2V, output_height_lt_4) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 1; input_height < 7; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39875,7 +39875,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_4X2V, output_height_gt_4) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 9; input_height < 17; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() @@ -39895,7 +39895,7 @@ TEST(F32_DWCONV2D_CHW_3X3S2P1__RVV_4X2V, padding_top_eq_1) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - size_t width_tile = 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + size_t width_tile = 2 * xnn_get_hardware_config()->vlenb / sizeof(float); for (size_t input_height = 2; input_height < 26; input_height++) { for (size_t input_width = 1; input_width < 5 * width_tile * 2 + 1; input_width += width_tile * 2 - 1) { DWConv2DMicrokernelTester() diff --git a/test/f32-gemm-2.cc b/test/f32-gemm-2.cc index 7eb8e4f9b54..867dc27401f 100644 --- a/test/f32-gemm-2.cc +++ b/test/f32-gemm-2.cc @@ -282,7 +282,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(float); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(float); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/f32-gemm-minmax-2.cc b/test/f32-gemm-minmax-2.cc index dcd57c86dc5..fe2ec4ab120 100644 --- a/test/f32-gemm-minmax-2.cc +++ b/test/f32-gemm-minmax-2.cc @@ -558,7 +558,7 @@ std::vector CreateTests2( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(float); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(float); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/f32-gemm-minmax.cc b/test/f32-gemm-minmax.cc index 99a16496575..33e8b2db92e 100644 --- a/test/f32-gemm-minmax.cc +++ b/test/f32-gemm-minmax.cc @@ -558,7 +558,7 @@ std::vector CreateTests2( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(float); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(float); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/f32-gemm-relu-2.cc b/test/f32-gemm-relu-2.cc index 617669039b7..3331dc02d79 100644 --- a/test/f32-gemm-relu-2.cc +++ b/test/f32-gemm-relu-2.cc @@ -282,7 +282,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(float); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(float); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/f32-gemm-relu.cc b/test/f32-gemm-relu.cc index 80c9f11545b..92a33ee220b 100644 --- a/test/f32-gemm-relu.cc +++ b/test/f32-gemm-relu.cc @@ -282,7 +282,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(float); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(float); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/f32-gemm.cc b/test/f32-gemm.cc index 65653ab4a1b..0415fd524dd 100644 --- a/test/f32-gemm.cc +++ b/test/f32-gemm.cc @@ -282,7 +282,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(float); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(float); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/f32-igemm-2.cc b/test/f32-igemm-2.cc index 600832632d4..6760da9053a 100644 --- a/test/f32-igemm-2.cc +++ b/test/f32-igemm-2.cc @@ -282,7 +282,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(float); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(float); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/f32-igemm-minmax-2.cc b/test/f32-igemm-minmax-2.cc index 3f2e425bd97..3bd888ad444 100644 --- a/test/f32-igemm-minmax-2.cc +++ b/test/f32-igemm-minmax-2.cc @@ -558,7 +558,7 @@ std::vector CreateTests2( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(float); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(float); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/f32-igemm-minmax.cc b/test/f32-igemm-minmax.cc index c46d4de4e83..3d7051ef997 100644 --- a/test/f32-igemm-minmax.cc +++ b/test/f32-igemm-minmax.cc @@ -558,7 +558,7 @@ std::vector CreateTests2( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(float); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(float); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/f32-igemm-relu-2.cc b/test/f32-igemm-relu-2.cc index 9eb73c8a0da..ce573c1a80b 100644 --- a/test/f32-igemm-relu-2.cc +++ b/test/f32-igemm-relu-2.cc @@ -282,7 +282,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(float); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(float); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/f32-igemm-relu.cc b/test/f32-igemm-relu.cc index 7edbb9723d1..ee8a32a49d2 100644 --- a/test/f32-igemm-relu.cc +++ b/test/f32-igemm-relu.cc @@ -282,7 +282,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(float); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(float); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/f32-igemm.cc b/test/f32-igemm.cc index f233553baed..b66ef9ab5cf 100644 --- a/test/f32-igemm.cc +++ b/test/f32-igemm.cc @@ -282,7 +282,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(float); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(float); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/f32-raddstoreexpminusmax.cc b/test/f32-raddstoreexpminusmax.cc index bea87b8a772..6818a902d8c 100644 --- a/test/f32-raddstoreexpminusmax.cc +++ b/test/f32-raddstoreexpminusmax.cc @@ -613,15 +613,15 @@ TEST(F32_RADDSTOREEXPMINUSMAX__RVV_RR2_P6_U2V, elements_eq_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); RAddStoreExpMinusMaxMicrokernelTester() - .elements(2 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .elements(2 * xnn_get_hardware_config()->vlenb / sizeof(float)) .Test(xnn_f32_raddstoreexpminusmax_ukernel__rvv_rr2_p6_u2v, nullptr); } TEST(F32_RADDSTOREEXPMINUSMAX__RVV_RR2_P6_U2V, elements_div_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - for (size_t elements = 4 * xnn_init_hardware_config()->vlenb / sizeof(float); - elements < 20 * xnn_init_hardware_config()->vlenb / sizeof(float); - elements += 2 * xnn_init_hardware_config()->vlenb / sizeof(float)) { + for (size_t elements = 4 * xnn_get_hardware_config()->vlenb / sizeof(float); + elements < 20 * xnn_get_hardware_config()->vlenb / sizeof(float); + elements += 2 * xnn_get_hardware_config()->vlenb / sizeof(float)) { RAddStoreExpMinusMaxMicrokernelTester() .elements(elements) .Test(xnn_f32_raddstoreexpminusmax_ukernel__rvv_rr2_p6_u2v, nullptr); @@ -631,7 +631,7 @@ TEST(F32_RADDSTOREEXPMINUSMAX__RVV_RR2_P6_U2V, elements_lt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t elements = 1; - elements < 2 * xnn_init_hardware_config()->vlenb / sizeof(float); + elements < 2 * xnn_get_hardware_config()->vlenb / sizeof(float); elements++) { RAddStoreExpMinusMaxMicrokernelTester() .elements(elements) @@ -641,8 +641,8 @@ TEST(F32_RADDSTOREEXPMINUSMAX__RVV_RR2_P6_U2V, elements_gt_2v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - for (size_t elements = 2 * xnn_init_hardware_config()->vlenb / sizeof(float) + 1; - elements < 4 * xnn_init_hardware_config()->vlenb / sizeof(float); + for (size_t elements = 2 * xnn_get_hardware_config()->vlenb / sizeof(float) + 1; + elements < 4 * xnn_get_hardware_config()->vlenb / sizeof(float); elements += 4) { RAddStoreExpMinusMaxMicrokernelTester() .elements(elements) @@ -656,15 +656,15 @@ TEST(F32_RADDSTOREEXPMINUSMAX__RVV_RR2_P6_U4V, elements_eq_4v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); RAddStoreExpMinusMaxMicrokernelTester() - .elements(4 * xnn_init_hardware_config()->vlenb / sizeof(float)) + .elements(4 * xnn_get_hardware_config()->vlenb / sizeof(float)) .Test(xnn_f32_raddstoreexpminusmax_ukernel__rvv_rr2_p6_u4v, nullptr); } TEST(F32_RADDSTOREEXPMINUSMAX__RVV_RR2_P6_U4V, elements_div_4v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - for (size_t elements = 8 * xnn_init_hardware_config()->vlenb / sizeof(float); - elements < 40 * xnn_init_hardware_config()->vlenb / sizeof(float); - elements += 4 * xnn_init_hardware_config()->vlenb / sizeof(float)) { + for (size_t elements = 8 * xnn_get_hardware_config()->vlenb / sizeof(float); + elements < 40 * xnn_get_hardware_config()->vlenb / sizeof(float); + elements += 4 * xnn_get_hardware_config()->vlenb / sizeof(float)) { RAddStoreExpMinusMaxMicrokernelTester() .elements(elements) .Test(xnn_f32_raddstoreexpminusmax_ukernel__rvv_rr2_p6_u4v, nullptr); @@ -674,7 +674,7 @@ TEST(F32_RADDSTOREEXPMINUSMAX__RVV_RR2_P6_U4V, elements_lt_4v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); for (size_t elements = 1; - elements < 4 * xnn_init_hardware_config()->vlenb / sizeof(float); + elements < 4 * xnn_get_hardware_config()->vlenb / sizeof(float); elements++) { RAddStoreExpMinusMaxMicrokernelTester() .elements(elements) @@ -684,8 +684,8 @@ TEST(F32_RADDSTOREEXPMINUSMAX__RVV_RR2_P6_U4V, elements_gt_4v) { TEST_REQUIRES_ARCH_FLAGS(xnn_arch_riscv_vector); - for (size_t elements = 4 * xnn_init_hardware_config()->vlenb / sizeof(float) + 1; - elements < 8 * xnn_init_hardware_config()->vlenb / sizeof(float); + for (size_t elements = 4 * xnn_get_hardware_config()->vlenb / sizeof(float) + 1; + elements < 8 * xnn_get_hardware_config()->vlenb / sizeof(float); elements += 8) { RAddStoreExpMinusMaxMicrokernelTester() .elements(elements) diff --git a/test/gemm-microkernel-tester.cc b/test/gemm-microkernel-tester.cc index e3c4f66c31c..50005746371 100644 --- a/test/gemm-microkernel-tester.cc +++ b/test/gemm-microkernel-tester.cc @@ -2308,7 +2308,7 @@ void GemmMicrokernelTester::Test_PF32( // Get the LHS packing config. const struct xnn_pack_lh_config* pack_lh_config = - xnn_init_x32_pack_lh_config(); + xnn_get_x32_pack_lh_config(); ASSERT_NE(pack_lh_config, nullptr); // Loop over the iterations. @@ -2425,7 +2425,7 @@ void GemmMicrokernelTester::Test_PF16( // Get the LHS packing config. const struct xnn_pack_lh_config* pack_lh_config = - xnn_init_x16_pack_lh_config(); + xnn_get_x16_pack_lh_config(); ASSERT_NE(pack_lh_config, nullptr); // Loop over the iterations. @@ -2545,7 +2545,7 @@ void GemmMicrokernelTester::Test_PQS8( // Get the LHS packing config. const struct xnn_pack_lh_config* pack_lh_config = - xnn_init_x8_pack_lh_config(); + xnn_get_x8_pack_lh_config(); ASSERT_NE(pack_lh_config, nullptr); xnnpack::fill_uniform_random_bits(a.data(), a.size(), rng); diff --git a/test/operators/argmax-pooling-nhwc.cc b/test/operators/argmax-pooling-nhwc.cc index f630a69beab..c51500fd505 100644 --- a/test/operators/argmax-pooling-nhwc.cc +++ b/test/operators/argmax-pooling-nhwc.cc @@ -16,7 +16,7 @@ constexpr size_t max_pooling_size = 25; TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_1xM_pool) { const struct xnn_argmaxpool_config* argmaxpool_config = - xnn_init_f32_argmaxpool_config(); + xnn_get_f32_argmaxpool_config(); ASSERT_NE(argmaxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pooling_size; pool_size++) { @@ -34,7 +34,7 @@ TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_1xM_pool) { TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_1xM_pool_with_padding) { const struct xnn_argmaxpool_config* argmaxpool_config = - xnn_init_f32_argmaxpool_config(); + xnn_get_f32_argmaxpool_config(); ASSERT_NE(argmaxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 3; pool_size <= max_pooling_size; pool_size++) { @@ -58,7 +58,7 @@ TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_1xM_pool_with_padding) { TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_1xM_pool_with_tf_same_padding) { const struct xnn_argmaxpool_config* argmaxpool_config = - xnn_init_f32_argmaxpool_config(); + xnn_get_f32_argmaxpool_config(); ASSERT_NE(argmaxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 3; pool_size <= max_pooling_size; pool_size++) { @@ -80,7 +80,7 @@ TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_1xM_pool_with_tf_same_padding) { TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_Mx1_pool) { const struct xnn_argmaxpool_config* argmaxpool_config = - xnn_init_f32_argmaxpool_config(); + xnn_get_f32_argmaxpool_config(); ASSERT_NE(argmaxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pooling_size; pool_size++) { @@ -98,7 +98,7 @@ TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_Mx1_pool) { TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_Mx1_pool_with_padding) { const struct xnn_argmaxpool_config* argmaxpool_config = - xnn_init_f32_argmaxpool_config(); + xnn_get_f32_argmaxpool_config(); ASSERT_NE(argmaxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pooling_size; pool_size++) { @@ -122,7 +122,7 @@ TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_Mx1_pool_with_padding) { TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_Mx1_pool_with_tf_same_padding) { const struct xnn_argmaxpool_config* argmaxpool_config = - xnn_init_f32_argmaxpool_config(); + xnn_get_f32_argmaxpool_config(); ASSERT_NE(argmaxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pooling_size; pool_size++) { @@ -144,7 +144,7 @@ TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_Mx1_pool_with_tf_same_padding) { TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_pool_with_input_stride) { const struct xnn_argmaxpool_config* argmaxpool_config = - xnn_init_f32_argmaxpool_config(); + xnn_get_f32_argmaxpool_config(); ASSERT_NE(argmaxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pooling_size; pool_size++) { @@ -172,7 +172,7 @@ TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_pool_with_input_stride) { TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_pool_with_output_stride) { const struct xnn_argmaxpool_config* argmaxpool_config = - xnn_init_f32_argmaxpool_config(); + xnn_get_f32_argmaxpool_config(); ASSERT_NE(argmaxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pooling_size; pool_size++) { @@ -200,7 +200,7 @@ TEST(ARGMAX_POOLING_NHWC_F32, unit_batch_small_pool_with_output_stride) { TEST(ARGMAX_POOLING_NHWC_F32, small_batch_small_pool) { const struct xnn_argmaxpool_config* argmaxpool_config = - xnn_init_f32_argmaxpool_config(); + xnn_get_f32_argmaxpool_config(); ASSERT_NE(argmaxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pooling_size; pool_size++) { @@ -226,7 +226,7 @@ TEST(ARGMAX_POOLING_NHWC_F32, small_batch_small_pool) { TEST(ARGMAX_POOLING_NHWC_F32, small_batch_small_pool_with_input_stride) { const struct xnn_argmaxpool_config* argmaxpool_config = - xnn_init_f32_argmaxpool_config(); + xnn_get_f32_argmaxpool_config(); ASSERT_NE(argmaxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pooling_size; pool_size++) { @@ -254,7 +254,7 @@ TEST(ARGMAX_POOLING_NHWC_F32, small_batch_small_pool_with_input_stride) { TEST(ARGMAX_POOLING_NHWC_F32, small_batch_small_pool_with_output_stride) { const struct xnn_argmaxpool_config* argmaxpool_config = - xnn_init_f32_argmaxpool_config(); + xnn_get_f32_argmaxpool_config(); ASSERT_NE(argmaxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pooling_size; pool_size++) { diff --git a/test/operators/average-pooling-nhwc.cc b/test/operators/average-pooling-nhwc.cc index b142c3a72c6..b200471a01f 100644 --- a/test/operators/average-pooling-nhwc.cc +++ b/test/operators/average-pooling-nhwc.cc @@ -36,7 +36,7 @@ static std::pair LargePoolSize(size_t min_elements) { TEST(AVERAGE_POOLING_NHWC_F16, small_pool) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -62,7 +62,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_pool) { TEST(AVERAGE_POOLING_NHWC_F16, small_pool_multithreaded) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -80,7 +80,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_pool_multithreaded) { TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -118,7 +118,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_stride) { TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -156,7 +156,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -194,7 +194,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_tf_same_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -256,7 +256,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_tf_same_padding) { TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_tf_same_padding_multithreaded) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -275,7 +275,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_tf_same_padding_multithreaded) { TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -303,7 +303,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -331,7 +331,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -359,7 +359,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -390,7 +390,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_pool_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -418,7 +418,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -458,7 +458,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_stride) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -498,7 +498,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -538,7 +538,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_tf_same_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -604,7 +604,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_tf_same_padding) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -634,7 +634,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -664,7 +664,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -694,7 +694,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -727,7 +727,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_pool_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F16, large_pool) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -753,7 +753,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_pool) { TEST(AVERAGE_POOLING_NHWC_F16, large_pool_multithreaded) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -771,7 +771,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_pool_multithreaded) { TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -807,7 +807,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_stride) { TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -859,7 +859,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -895,7 +895,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_tf_same_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -955,7 +955,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_tf_same_padding) { TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -981,7 +981,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1007,7 +1007,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1033,7 +1033,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1059,7 +1059,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_tf_same_padding_multithreaded) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1090,7 +1090,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_pool_with_tf_same_padding_multithreaded) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1118,7 +1118,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1156,7 +1156,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_stride) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1194,7 +1194,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1232,7 +1232,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_tf_same_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1296,7 +1296,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_tf_same_padding) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1324,7 +1324,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1352,7 +1352,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1380,7 +1380,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1408,7 +1408,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_multithreaded) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f16_avgpool_config(); + xnn_get_f16_avgpool_config(); if (avgpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1430,7 +1430,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_pool_multithreaded) { TEST(AVERAGE_POOLING_NHWC_F16, small_image) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1454,7 +1454,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_image) { TEST(AVERAGE_POOLING_NHWC_F16, small_image_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1499,7 +1499,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_image_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F16, small_image_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1544,7 +1544,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_image_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F16, small_image_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1570,7 +1570,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_image_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F16, small_image_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1596,7 +1596,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_image_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F16, small_image_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1622,7 +1622,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_image_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F16, small_image_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1651,7 +1651,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, small_image_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1677,7 +1677,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1726,7 +1726,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1775,7 +1775,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1803,7 +1803,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1831,7 +1831,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1859,7 +1859,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -1890,7 +1890,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_small_image_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F16, large_image) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1914,7 +1914,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_image) { TEST(AVERAGE_POOLING_NHWC_F16, large_image_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -1960,7 +1960,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_image_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F16, large_image_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2006,7 +2006,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_image_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F16, large_image_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2032,7 +2032,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_image_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F16, large_image_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2058,7 +2058,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_image_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F16, large_image_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2084,7 +2084,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_image_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F16, large_image_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2113,7 +2113,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, large_image_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2139,7 +2139,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2189,7 +2189,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2239,7 +2239,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2267,7 +2267,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2295,7 +2295,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2323,7 +2323,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2351,7 +2351,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F16, batched_large_image_multithreaded) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -2520,7 +2520,7 @@ TEST(AVERAGE_POOLING_NHWC_F16, setup_global_to_local) { TEST(AVERAGE_POOLING_NHWC_F32, small_pool) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2544,7 +2544,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_pool) { TEST(AVERAGE_POOLING_NHWC_F32, small_pool_multithreaded) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2560,7 +2560,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_pool_multithreaded) { TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2596,7 +2596,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_stride) { TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2632,7 +2632,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2668,7 +2668,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_tf_same_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2728,7 +2728,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_tf_same_padding) { TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_tf_same_padding_multithreaded) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2745,7 +2745,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_tf_same_padding_multithreaded) { TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2771,7 +2771,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2797,7 +2797,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2823,7 +2823,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2852,7 +2852,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_pool_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2878,7 +2878,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2916,7 +2916,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_stride) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2954,7 +2954,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -2992,7 +2992,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_tf_same_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -3056,7 +3056,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_tf_same_padding) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -3084,7 +3084,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -3112,7 +3112,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -3140,7 +3140,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -3171,7 +3171,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_pool_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F32, large_pool) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3195,7 +3195,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_pool) { TEST(AVERAGE_POOLING_NHWC_F32, large_pool_multithreaded) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3211,7 +3211,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_pool_multithreaded) { TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3247,7 +3247,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_stride) { TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3299,7 +3299,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3335,7 +3335,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_tf_same_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3395,7 +3395,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_tf_same_padding) { TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3421,7 +3421,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3447,7 +3447,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3473,7 +3473,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3499,7 +3499,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_tf_same_padding_multithreaded) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile + 1); @@ -3528,7 +3528,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_pool_with_tf_same_padding_multithreaded) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3554,7 +3554,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3592,7 +3592,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_stride) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3630,7 +3630,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3668,7 +3668,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_tf_same_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3732,7 +3732,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_tf_same_padding) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3760,7 +3760,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3788,7 +3788,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3816,7 +3816,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3844,7 +3844,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_multithreaded) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -3864,7 +3864,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_pool_multithreaded) { TEST(AVERAGE_POOLING_NHWC_F32, small_image) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -3888,7 +3888,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_image) { TEST(AVERAGE_POOLING_NHWC_F32, small_image_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -3933,7 +3933,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_image_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F32, small_image_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -3978,7 +3978,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_image_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F32, small_image_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -4004,7 +4004,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_image_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F32, small_image_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -4030,7 +4030,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_image_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F32, small_image_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -4056,7 +4056,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_image_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F32, small_image_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -4085,7 +4085,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, small_image_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -4111,7 +4111,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -4160,7 +4160,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -4209,7 +4209,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -4237,7 +4237,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -4265,7 +4265,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -4293,7 +4293,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = SmallPoolSize(avgpool_config->primary_tile); @@ -4324,7 +4324,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_small_image_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F32, large_image) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4348,7 +4348,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_image) { TEST(AVERAGE_POOLING_NHWC_F32, large_image_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4394,7 +4394,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_image_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F32, large_image_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4440,7 +4440,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_image_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F32, large_image_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4466,7 +4466,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_image_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F32, large_image_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4492,7 +4492,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_image_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F32, large_image_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4518,7 +4518,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_image_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F32, large_image_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4547,7 +4547,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, large_image_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4573,7 +4573,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_with_width_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4623,7 +4623,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_with_width_padding) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_with_height_padding) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4673,7 +4673,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_with_height_padding) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_with_input_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4701,7 +4701,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_with_input_stride) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_with_output_stride) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4729,7 +4729,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_with_output_stride) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_with_qmin) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4757,7 +4757,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_with_qmin) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_with_qmax) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); @@ -4785,7 +4785,7 @@ TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_with_qmax) { TEST(AVERAGE_POOLING_NHWC_F32, batched_large_image_multithreaded) { const struct xnn_avgpool_config* avgpool_config = - xnn_init_f32_avgpool_config(); + xnn_get_f32_avgpool_config(); ASSERT_NE(avgpool_config, nullptr); const std::pair pooling_size = LargePoolSize(avgpool_config->primary_tile * 2); diff --git a/test/operators/batch-matrix-multiply-operator-tester.h b/test/operators/batch-matrix-multiply-operator-tester.h index cafbf6d76b8..9f2f8d3d7b0 100644 --- a/test/operators/batch-matrix-multiply-operator-tester.h +++ b/test/operators/batch-matrix-multiply-operator-tester.h @@ -638,7 +638,7 @@ class BatchMatMulOperatorTester { void TestQP8F32QC8W() const { const struct xnn_gemm_config* gemm_config = - xnn_init_qp8_f32_qc8w_gemm_config(); + xnn_get_qp8_f32_qc8w_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); } diff --git a/test/operators/convert-nc.cc b/test/operators/convert-nc.cc index 43e9ce61db1..6dadfe92767 100644 --- a/test/operators/convert-nc.cc +++ b/test/operators/convert-nc.cc @@ -318,7 +318,7 @@ class ConvertOperatorTester { // The parameters of the GEMM config are used as packing parameters. const struct xnn_gemm_config* gemm_config = - xnn_init_f32_gemm_nr2_config(/*flags=*/0); + xnn_get_f32_gemm_nr2_config(/*flags=*/0); xnnpack::Buffer input( (batch_size() - 1) * input_stride() + channels(), @@ -340,7 +340,7 @@ class ConvertOperatorTester { ASSERT_EQ(xnn_status_success, xnn_create_convert_nc_f32_qp8( - 0, xnn_init_qp8_f32_qc4w_gemm_config(), &convert_op)); + 0, xnn_get_qp8_f32_qc4w_gemm_config(), &convert_op)); ASSERT_NE(nullptr, convert_op); // Smart pointer to automatically delete convert op. diff --git a/test/operators/deconvolution-nhwc-qd8-f32-qc8w.cc b/test/operators/deconvolution-nhwc-qd8-f32-qc8w.cc index a6e251f4048..dfdec964b90 100644 --- a/test/operators/deconvolution-nhwc-qd8-f32-qc8w.cc +++ b/test/operators/deconvolution-nhwc-qd8-f32-qc8w.cc @@ -20,7 +20,7 @@ constexpr size_t kStridedInputWidth = 5; TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -32,7 +32,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -47,7 +47,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -62,7 +62,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_varying_input_height) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -76,7 +76,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_varying_input_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -91,7 +91,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_varying_output_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -104,7 +104,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -117,7 +117,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -130,7 +130,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -143,7 +143,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -159,7 +159,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_1x1_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -172,7 +172,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -188,7 +188,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -204,7 +204,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_varying_input_height) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -219,7 +219,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_varying_input_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -235,7 +235,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_varying_output_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -249,7 +249,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -263,7 +263,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -277,7 +277,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -291,7 +291,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -308,7 +308,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_1x1_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -321,7 +321,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -337,7 +337,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -353,7 +353,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_varying_input_height) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -368,7 +368,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_varying_input_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -384,7 +384,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_varying_output_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -398,7 +398,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -412,7 +412,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -426,7 +426,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -440,7 +440,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -457,7 +457,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_1x1_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -471,7 +471,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -489,7 +489,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -507,7 +507,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -524,7 +524,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -541,7 +541,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -556,7 +556,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -571,7 +571,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -586,7 +586,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -601,7 +601,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -618,7 +618,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_1x1_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -631,7 +631,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, Kx3) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -646,7 +646,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, Kx3) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3xK) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -661,7 +661,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3xK) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_height_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -680,7 +680,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_height_padding) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_width_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -699,7 +699,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_width_padding) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_height_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -717,7 +717,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_height_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_width_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -734,7 +734,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_width_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -750,7 +750,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_input_height) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -766,7 +766,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -781,7 +781,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_input_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -797,7 +797,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_varying_output_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_height_dilation) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -813,7 +813,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_height_dilation) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_width_dilation) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -830,7 +830,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_width_dilation) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_height_dilation_and_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -846,7 +846,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_width_dilation_and_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -861,7 +861,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -875,7 +875,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -889,7 +889,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -903,7 +903,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -917,7 +917,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -931,7 +931,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_3x3) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -947,7 +947,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_3x3) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -961,7 +961,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_Kx3) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -977,7 +977,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_Kx3) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3xK) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -993,7 +993,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3xK) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_height_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -1013,7 +1013,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_height_padding) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_width_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -1033,7 +1033,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_width_padding) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_height_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -1052,7 +1052,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_height_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_width_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -1070,7 +1070,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_width_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -1087,7 +1087,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_input_height) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -1104,7 +1104,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -1120,7 +1120,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_input_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -1137,7 +1137,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_varying_output_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_height_dilation) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -1154,7 +1154,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_height_dilation) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_width_dilation) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -1172,7 +1172,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_width_dilation) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_height_dilation_and_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1189,7 +1189,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_width_dilation_and_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1205,7 +1205,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1220,7 +1220,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1235,7 +1235,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1250,7 +1250,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1265,7 +1265,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -1280,7 +1280,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_grouped_3x3) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1297,7 +1297,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_grouped_3x3) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1311,7 +1311,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_Kx3) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -1327,7 +1327,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_Kx3) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3xK) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -1343,7 +1343,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3xK) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_height_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -1363,7 +1363,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_height_padding) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_width_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -1383,7 +1383,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_width_padding) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_height_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -1402,7 +1402,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_height_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_width_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -1420,7 +1420,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_width_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -1437,7 +1437,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_input_height) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -1454,7 +1454,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -1470,7 +1470,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_input_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -1487,7 +1487,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_varying_output_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_height_dilation) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -1504,7 +1504,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_height_dilation) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_width_dilation) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -1522,7 +1522,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_width_dilation) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_height_dilation_and_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1539,7 +1539,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_width_dilation_and_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1555,7 +1555,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1570,7 +1570,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1585,7 +1585,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1600,7 +1600,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1615,7 +1615,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -1630,7 +1630,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_batched_3x3) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1648,7 +1648,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_batched_3x3) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1663,7 +1663,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_Kx3) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -1680,7 +1680,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_Kx3) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3xK) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -1698,7 +1698,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3xK) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_varying_height_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -1720,7 +1720,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_varying_width_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -1742,7 +1742,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_varying_height_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -1763,7 +1763,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_varying_width_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -1783,7 +1783,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -1801,7 +1801,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -1820,7 +1820,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -1838,7 +1838,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -1857,7 +1857,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_height_dilation) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -1875,7 +1875,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_width_dilation) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -1894,7 +1894,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_width_dilation) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_height_dilation_and_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1912,7 +1912,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_width_dilation_and_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1929,7 +1929,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1945,7 +1945,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1961,7 +1961,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1977,7 +1977,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1993,7 +1993,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -2009,7 +2009,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_batched_grouped_3x3) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2027,7 +2027,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_batched_grouped_3x3) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2041,7 +2041,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, Kx3s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -2057,7 +2057,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, Kx3s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3xKs2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -2073,7 +2073,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3xKs2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3sSx1) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -2090,7 +2090,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3sSx1) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s1xS) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -2107,7 +2107,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s1xS) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_height_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -2127,7 +2127,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_height_padding) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_width_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -2147,7 +2147,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_width_padding) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_height_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -2165,7 +2165,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_height_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_width_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -2182,7 +2182,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_width_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -2199,7 +2199,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_input_height) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -2216,7 +2216,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -2232,7 +2232,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_input_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -2249,7 +2249,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_varying_output_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2264,7 +2264,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2279,7 +2279,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2294,7 +2294,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2309,7 +2309,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -2324,7 +2324,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_3x3s2_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_3x3s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2342,7 +2342,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_3x3s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2357,7 +2357,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_Kx3s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -2374,7 +2374,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_Kx3s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3xKs2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -2391,7 +2391,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3xKs2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3sSx1) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -2409,7 +2409,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3sSx1) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s1xS) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -2427,7 +2427,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s1xS) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_height_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -2448,7 +2448,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_height_padding) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_width_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -2469,7 +2469,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_width_padding) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_height_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -2488,7 +2488,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_height_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_width_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -2506,7 +2506,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_width_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -2524,7 +2524,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_input_height) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -2542,7 +2542,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -2559,7 +2559,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_input_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -2577,7 +2577,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_varying_output_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2593,7 +2593,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2609,7 +2609,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2625,7 +2625,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2641,7 +2641,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -2657,7 +2657,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_3x3s2_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_grouped_3x3s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2676,7 +2676,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_grouped_3x3s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2691,7 +2691,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_Kx3s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -2708,7 +2708,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_Kx3s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3xKs2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -2725,7 +2725,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3xKs2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3sSx1) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -2743,7 +2743,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3sSx1) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s1xS) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -2761,7 +2761,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s1xS) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_height_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -2782,7 +2782,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_height_padding) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_width_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -2803,7 +2803,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_width_padding) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_height_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -2822,7 +2822,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_height_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_width_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -2840,7 +2840,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_width_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -2858,7 +2858,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_input_height) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -2876,7 +2876,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -2893,7 +2893,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_input_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -2911,7 +2911,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_varying_output_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2927,7 +2927,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2943,7 +2943,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2959,7 +2959,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2975,7 +2975,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -2991,7 +2991,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_3x3s2_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_batched_3x3s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3010,7 +3010,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_batched_3x3s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3026,7 +3026,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_Kx3s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -3044,7 +3044,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_Kx3s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3xKs2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -3062,7 +3062,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3xKs2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3sSx1) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -3081,7 +3081,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3sSx1) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s1xS) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -3101,7 +3101,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s1xS) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_varying_height_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -3124,7 +3124,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_varying_width_padding) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -3147,7 +3147,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_varying_height_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -3168,7 +3168,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_varying_width_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -3188,7 +3188,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -3208,7 +3208,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -3228,7 +3228,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -3247,7 +3247,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -3266,7 +3266,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3284,7 +3284,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3301,7 +3301,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3318,7 +3318,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3335,7 +3335,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -3352,7 +3352,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_3x3s2_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_batched_grouped_3x3s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3371,7 +3371,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_batched_grouped_3x3s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3384,7 +3384,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, Kx2sKx2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -3399,7 +3399,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, Kx2sKx2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2xKs2xK) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -3414,7 +3414,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2xKs2xK) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_height_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3428,7 +3428,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_height_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_width_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3442,7 +3442,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_width_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -3458,7 +3458,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_varying_input_height) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -3474,7 +3474,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -3489,7 +3489,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_varying_input_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -3505,7 +3505,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_varying_output_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3519,7 +3519,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3533,7 +3533,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3547,7 +3547,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3561,7 +3561,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -3575,7 +3575,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, kernel_2x2s2_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_2x2s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3592,7 +3592,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_2x2s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3606,7 +3606,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_Kx2sKx2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -3622,7 +3622,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_Kx2sKx2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2xKs2xK) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -3638,7 +3638,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2xKs2xK) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_height_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3653,7 +3653,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_height_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_width_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3668,7 +3668,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_width_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -3685,7 +3685,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_varying_input_height) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -3702,7 +3702,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -3718,7 +3718,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_varying_input_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -3735,7 +3735,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_varying_output_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3750,7 +3750,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3765,7 +3765,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3780,7 +3780,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3795,7 +3795,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -3810,7 +3810,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, grouped_2x2s2_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_grouped_2x2s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3828,7 +3828,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_grouped_2x2s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3842,7 +3842,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_Kx2sKx2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -3858,7 +3858,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_Kx2sKx2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2xKs2xK) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -3874,7 +3874,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2xKs2xK) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_height_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3889,7 +3889,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_height_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_width_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3904,7 +3904,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_width_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -3921,7 +3921,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_varying_input_height) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -3938,7 +3938,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_varying_input_width) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -3954,7 +3954,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_varying_input_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -3971,7 +3971,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_varying_output_channels) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3986,7 +3986,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4001,7 +4001,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_with_output_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4016,7 +4016,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4031,7 +4031,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -4046,7 +4046,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_2x2s2_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_batched_2x2s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4064,7 +4064,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_batched_2x2s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4079,7 +4079,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_Kx2sKx2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -4096,7 +4096,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_Kx2sKx2) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2xKs2xK) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -4113,7 +4113,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2xKs2xK) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_height_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4129,7 +4129,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_height_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_width_adjustment) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4146,7 +4146,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_width_adjustment) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_varying_input_height) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -4165,7 +4165,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_varying_input_width) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -4184,7 +4184,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_varying_input_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -4202,7 +4202,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_varying_output_channels) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -4220,7 +4220,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_with_input_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4237,7 +4237,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_with_input_stride) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_with_output_stride) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4253,7 +4253,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_with_qmin) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4269,7 +4269,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_with_qmin) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_with_qmax) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4285,7 +4285,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_with_qmax) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_without_bias) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -4301,7 +4301,7 @@ TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, batched_grouped_2x2s2_without_bias) { TEST(DECONVOLUTION_NHWC_QD8_F32_QC8W, weights_cache_batched_grouped_2x2s2) { const struct xnn_gemm_config* gemm_config = - xnn_init_qd8_f32_qc8w_gemm_config(); + xnn_get_qd8_f32_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) diff --git a/test/operators/deconvolution-nhwc.cc b/test/operators/deconvolution-nhwc.cc index 14008343e92..3a9e25aa7ac 100644 --- a/test/operators/deconvolution-nhwc.cc +++ b/test/operators/deconvolution-nhwc.cc @@ -19,7 +19,7 @@ constexpr size_t kStridedInputWidth = 5; /**************************** Future GEMM path ****************************/ TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -30,7 +30,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -44,7 +44,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -58,7 +58,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -71,7 +71,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -85,7 +85,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -97,7 +97,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -109,7 +109,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -121,7 +121,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -133,7 +133,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -148,7 +148,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_1x1_without_bias) { * ****************************/ TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -160,7 +160,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -175,7 +175,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -190,7 +190,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -204,7 +204,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -219,7 +219,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -232,7 +232,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -245,7 +245,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -258,7 +258,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -271,7 +271,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -287,7 +287,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_1x1_without_bias) { * ****************************/ TEST(DECONVOLUTION_NHWC_QC8, batched_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -299,7 +299,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_1x1) { } TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -314,7 +314,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -329,7 +329,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -343,7 +343,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -358,7 +358,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -371,7 +371,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -384,7 +384,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -397,7 +397,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -410,7 +410,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -426,7 +426,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_1x1_without_bias) { * ****************************/ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -439,7 +439,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -455,7 +455,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -471,7 +471,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -486,7 +486,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -502,7 +502,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -516,7 +516,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -530,7 +530,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -544,7 +544,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -558,7 +558,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -574,7 +574,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_1x1_without_bias) { /**************************** CONV path ****************************/ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -586,7 +586,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3) { } TEST(DECONVOLUTION_NHWC_QC8, Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -600,7 +600,7 @@ TEST(DECONVOLUTION_NHWC_QC8, Kx3) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -614,7 +614,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3xK) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -632,7 +632,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -650,7 +650,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -667,7 +667,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -683,7 +683,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -698,7 +698,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -713,7 +713,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -727,7 +727,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -742,7 +742,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -757,7 +757,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -772,7 +772,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_width_dilation) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -786,7 +786,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_height_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -800,7 +800,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_width_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -813,7 +813,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -826,7 +826,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -839,7 +839,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -852,7 +852,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -865,7 +865,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_QC8, weights_cache_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -880,7 +880,7 @@ TEST(DECONVOLUTION_NHWC_QC8, weights_cache_3x3) { /**************************** CONV path, grouped ****************************/ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -893,7 +893,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -908,7 +908,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_Kx3) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -923,7 +923,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3xK) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -942,7 +942,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -961,7 +961,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -979,7 +979,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -996,7 +996,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -1012,7 +1012,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -1028,7 +1028,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -1043,7 +1043,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -1059,7 +1059,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -1075,7 +1075,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -1091,7 +1091,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_width_dilation) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1106,7 +1106,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_height_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1121,7 +1121,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_width_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1135,7 +1135,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1149,7 +1149,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1163,7 +1163,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1177,7 +1177,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -1191,7 +1191,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_QC8, weights_cache_grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -1207,7 +1207,7 @@ TEST(DECONVOLUTION_NHWC_QC8, weights_cache_grouped_3x3) { /**************************** CONV path, batched ****************************/ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1220,7 +1220,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3) { } TEST(DECONVOLUTION_NHWC_QC8, batched_Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -1235,7 +1235,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_Kx3) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -1250,7 +1250,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3xK) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -1269,7 +1269,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -1288,7 +1288,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -1306,7 +1306,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -1323,7 +1323,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -1339,7 +1339,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -1355,7 +1355,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -1370,7 +1370,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -1386,7 +1386,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -1402,7 +1402,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -1418,7 +1418,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_width_dilation) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1433,7 +1433,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_height_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1448,7 +1448,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_width_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1462,7 +1462,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1476,7 +1476,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1490,7 +1490,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1504,7 +1504,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -1518,7 +1518,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_QC8, weights_cache_batched_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1535,7 +1535,7 @@ TEST(DECONVOLUTION_NHWC_QC8, weights_cache_batched_3x3) { * ****************************/ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1549,7 +1549,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -1565,7 +1565,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_Kx3) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -1581,7 +1581,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3xK) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -1601,7 +1601,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -1621,7 +1621,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -1640,7 +1640,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -1658,7 +1658,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -1675,7 +1675,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -1692,7 +1692,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -1708,7 +1708,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -1725,7 +1725,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -1742,7 +1742,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -1760,7 +1760,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_width_dilation) { TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1777,7 +1777,7 @@ TEST(DECONVOLUTION_NHWC_QC8, TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1793,7 +1793,7 @@ TEST(DECONVOLUTION_NHWC_QC8, } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1808,7 +1808,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1823,7 +1823,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1838,7 +1838,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1853,7 +1853,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -1868,7 +1868,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_QC8, weights_cache_batched_grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -1929,7 +1929,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3_setup_changing_width) { /**************************** SUBCONV2D/IGEMM path ****************************/ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -1942,7 +1942,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2) { } TEST(DECONVOLUTION_NHWC_QC8, Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -1957,7 +1957,7 @@ TEST(DECONVOLUTION_NHWC_QC8, Kx3s2) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -1972,7 +1972,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3xKs2) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -1988,7 +1988,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -2004,7 +2004,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -2023,7 +2023,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -2042,7 +2042,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -2059,7 +2059,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -2075,7 +2075,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -2091,7 +2091,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -2107,7 +2107,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -2122,7 +2122,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -2138,7 +2138,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2152,7 +2152,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2166,7 +2166,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2180,7 +2180,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2194,7 +2194,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -2208,7 +2208,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QC8, weights_cache_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2225,7 +2225,7 @@ TEST(DECONVOLUTION_NHWC_QC8, weights_cache_3x3s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2239,7 +2239,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -2255,7 +2255,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_Kx3s2) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -2271,7 +2271,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3xKs2) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -2288,7 +2288,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -2305,7 +2305,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -2325,7 +2325,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -2345,7 +2345,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -2363,7 +2363,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -2380,7 +2380,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -2397,7 +2397,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -2414,7 +2414,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -2430,7 +2430,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -2447,7 +2447,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2462,7 +2462,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2477,7 +2477,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2492,7 +2492,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2507,7 +2507,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -2522,7 +2522,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QC8, weights_cache_grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -2540,7 +2540,7 @@ TEST(DECONVOLUTION_NHWC_QC8, weights_cache_grouped_3x3s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2554,7 +2554,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2) { } TEST(DECONVOLUTION_NHWC_QC8, batched_Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -2570,7 +2570,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_Kx3s2) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -2586,7 +2586,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3xKs2) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -2603,7 +2603,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -2620,7 +2620,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -2640,7 +2640,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -2660,7 +2660,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -2678,7 +2678,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -2695,7 +2695,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -2712,7 +2712,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -2729,7 +2729,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -2745,7 +2745,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -2762,7 +2762,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2777,7 +2777,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2792,7 +2792,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2807,7 +2807,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2822,7 +2822,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -2837,7 +2837,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QC8, weights_cache_batched_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2855,7 +2855,7 @@ TEST(DECONVOLUTION_NHWC_QC8, weights_cache_batched_3x3s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -2870,7 +2870,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -2887,7 +2887,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_Kx3s2) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -2904,7 +2904,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3xKs2) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -2922,7 +2922,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -2940,7 +2940,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -2961,7 +2961,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -2982,7 +2982,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -3001,7 +3001,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -3019,7 +3019,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -3037,7 +3037,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -3055,7 +3055,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -3072,7 +3072,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -3090,7 +3090,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3106,7 +3106,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3122,7 +3122,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3138,7 +3138,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3154,7 +3154,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -3170,7 +3170,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QC8, weights_cache_batched_grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3236,7 +3236,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_3x3s2_setup_changing_width) { /**************************** SUBCONV2D/GEMM path ****************************/ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3248,7 +3248,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2) { } TEST(DECONVOLUTION_NHWC_QC8, Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -3262,7 +3262,7 @@ TEST(DECONVOLUTION_NHWC_QC8, Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -3276,7 +3276,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3289,7 +3289,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3302,7 +3302,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -3317,7 +3317,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -3332,7 +3332,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -3346,7 +3346,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -3361,7 +3361,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3374,7 +3374,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3387,7 +3387,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3400,7 +3400,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3413,7 +3413,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -3426,7 +3426,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QC8, weights_cache_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3442,7 +3442,7 @@ TEST(DECONVOLUTION_NHWC_QC8, weights_cache_2x2s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3455,7 +3455,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -3470,7 +3470,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -3485,7 +3485,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3499,7 +3499,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3513,7 +3513,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -3529,7 +3529,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -3545,7 +3545,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -3560,7 +3560,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -3576,7 +3576,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3590,7 +3590,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3604,7 +3604,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3618,7 +3618,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3632,7 +3632,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -3646,7 +3646,7 @@ TEST(DECONVOLUTION_NHWC_QC8, grouped_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QC8, weights_cache_grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -3663,7 +3663,7 @@ TEST(DECONVOLUTION_NHWC_QC8, weights_cache_grouped_2x2s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3676,7 +3676,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2) { } TEST(DECONVOLUTION_NHWC_QC8, batched_Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -3691,7 +3691,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_QC8, batched_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -3706,7 +3706,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3720,7 +3720,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3734,7 +3734,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -3750,7 +3750,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -3766,7 +3766,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -3781,7 +3781,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -3797,7 +3797,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3811,7 +3811,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3825,7 +3825,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3839,7 +3839,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3853,7 +3853,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -3867,7 +3867,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QC8, weights_cache_batched_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3884,7 +3884,7 @@ TEST(DECONVOLUTION_NHWC_QC8, weights_cache_batched_2x2s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3898,7 +3898,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -3914,7 +3914,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -3930,7 +3930,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3945,7 +3945,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -3960,7 +3960,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -3977,7 +3977,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -3994,7 +3994,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -4010,7 +4010,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -4027,7 +4027,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4042,7 +4042,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4057,7 +4057,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4072,7 +4072,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4087,7 +4087,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -4102,7 +4102,7 @@ TEST(DECONVOLUTION_NHWC_QC8, batched_grouped_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QC8, weights_cache_batched_grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qs8_qc8w_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qs8_qc8w_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4164,7 +4164,7 @@ TEST(DECONVOLUTION_NHWC_QC8, kernel_2x2s2_setup_changing_width) { /**************************** Future GEMM path ****************************/ TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4175,7 +4175,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -4189,7 +4189,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -4203,7 +4203,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -4216,7 +4216,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -4230,7 +4230,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4242,7 +4242,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4254,7 +4254,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4266,7 +4266,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4278,7 +4278,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -4293,7 +4293,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_1x1_without_bias) { * ****************************/ TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4305,7 +4305,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -4320,7 +4320,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -4335,7 +4335,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -4349,7 +4349,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -4364,7 +4364,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4377,7 +4377,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4390,7 +4390,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4403,7 +4403,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4416,7 +4416,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -4432,7 +4432,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_1x1_without_bias) { * ****************************/ TEST(DECONVOLUTION_NHWC_QU8, batched_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4444,7 +4444,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_1x1) { } TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -4459,7 +4459,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -4474,7 +4474,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -4488,7 +4488,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -4503,7 +4503,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4516,7 +4516,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4529,7 +4529,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4542,7 +4542,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4555,7 +4555,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -4571,7 +4571,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_1x1_without_bias) { * ****************************/ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4584,7 +4584,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -4600,7 +4600,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -4616,7 +4616,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -4631,7 +4631,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -4647,7 +4647,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4661,7 +4661,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4675,7 +4675,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4689,7 +4689,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -4703,7 +4703,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -4719,7 +4719,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_1x1_without_bias) { /**************************** CONV path ****************************/ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4731,7 +4731,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3) { } TEST(DECONVOLUTION_NHWC_QU8, Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -4745,7 +4745,7 @@ TEST(DECONVOLUTION_NHWC_QU8, Kx3) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -4759,7 +4759,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3xK) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -4777,7 +4777,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -4795,7 +4795,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -4812,7 +4812,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -4828,7 +4828,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -4843,7 +4843,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -4858,7 +4858,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -4872,7 +4872,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -4887,7 +4887,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -4902,7 +4902,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -4917,7 +4917,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_width_dilation) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4931,7 +4931,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_height_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4945,7 +4945,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_width_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4958,7 +4958,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4971,7 +4971,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4984,7 +4984,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -4997,7 +4997,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -5010,7 +5010,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_QU8, weights_cache_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -5025,7 +5025,7 @@ TEST(DECONVOLUTION_NHWC_QU8, weights_cache_3x3) { /**************************** CONV path, grouped ****************************/ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -5038,7 +5038,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -5053,7 +5053,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_Kx3) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -5068,7 +5068,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3xK) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -5087,7 +5087,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -5106,7 +5106,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -5124,7 +5124,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -5141,7 +5141,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -5157,7 +5157,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -5173,7 +5173,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -5188,7 +5188,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -5204,7 +5204,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -5220,7 +5220,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -5236,7 +5236,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_width_dilation) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -5251,7 +5251,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_height_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -5266,7 +5266,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_width_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -5280,7 +5280,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -5294,7 +5294,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -5308,7 +5308,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -5322,7 +5322,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -5336,7 +5336,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_QU8, weights_cache_grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -5352,7 +5352,7 @@ TEST(DECONVOLUTION_NHWC_QU8, weights_cache_grouped_3x3) { /**************************** CONV path, batched ****************************/ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5365,7 +5365,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3) { } TEST(DECONVOLUTION_NHWC_QU8, batched_Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -5380,7 +5380,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_Kx3) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -5395,7 +5395,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3xK) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -5414,7 +5414,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -5433,7 +5433,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -5451,7 +5451,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -5468,7 +5468,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -5484,7 +5484,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -5500,7 +5500,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -5515,7 +5515,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -5531,7 +5531,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -5547,7 +5547,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -5563,7 +5563,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_width_dilation) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5578,7 +5578,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_height_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5593,7 +5593,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_width_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5607,7 +5607,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5621,7 +5621,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5635,7 +5635,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5649,7 +5649,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -5663,7 +5663,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_QU8, weights_cache_batched_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5680,7 +5680,7 @@ TEST(DECONVOLUTION_NHWC_QU8, weights_cache_batched_3x3) { * ****************************/ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5694,7 +5694,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -5710,7 +5710,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_Kx3) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -5726,7 +5726,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3xK) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -5746,7 +5746,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -5766,7 +5766,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -5785,7 +5785,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -5803,7 +5803,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -5820,7 +5820,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -5837,7 +5837,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -5853,7 +5853,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -5870,7 +5870,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -5887,7 +5887,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -5905,7 +5905,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_width_dilation) { TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5922,7 +5922,7 @@ TEST(DECONVOLUTION_NHWC_QU8, TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5938,7 +5938,7 @@ TEST(DECONVOLUTION_NHWC_QU8, } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5953,7 +5953,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5968,7 +5968,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5983,7 +5983,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -5998,7 +5998,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -6013,7 +6013,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_QU8, weights_cache_batched_grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -6074,7 +6074,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3_setup_changing_width) { /**************************** SUBCONV2D/IGEMM path ****************************/ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -6087,7 +6087,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2) { } TEST(DECONVOLUTION_NHWC_QU8, Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -6102,7 +6102,7 @@ TEST(DECONVOLUTION_NHWC_QU8, Kx3s2) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -6117,7 +6117,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3xKs2) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -6133,7 +6133,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -6149,7 +6149,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -6168,7 +6168,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -6187,7 +6187,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -6204,7 +6204,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -6220,7 +6220,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -6236,7 +6236,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -6252,7 +6252,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -6267,7 +6267,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -6283,7 +6283,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -6297,7 +6297,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -6311,7 +6311,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -6325,7 +6325,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -6339,7 +6339,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -6353,7 +6353,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QU8, weights_cache_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -6370,7 +6370,7 @@ TEST(DECONVOLUTION_NHWC_QU8, weights_cache_3x3s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -6384,7 +6384,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -6400,7 +6400,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_Kx3s2) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -6416,7 +6416,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3xKs2) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -6433,7 +6433,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -6450,7 +6450,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -6470,7 +6470,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -6490,7 +6490,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -6508,7 +6508,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -6525,7 +6525,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -6542,7 +6542,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -6559,7 +6559,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -6575,7 +6575,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -6592,7 +6592,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -6607,7 +6607,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -6622,7 +6622,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -6637,7 +6637,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -6652,7 +6652,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -6667,7 +6667,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QU8, weights_cache_grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -6685,7 +6685,7 @@ TEST(DECONVOLUTION_NHWC_QU8, weights_cache_grouped_3x3s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -6699,7 +6699,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2) { } TEST(DECONVOLUTION_NHWC_QU8, batched_Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -6715,7 +6715,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_Kx3s2) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -6731,7 +6731,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3xKs2) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -6748,7 +6748,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -6765,7 +6765,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -6785,7 +6785,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -6805,7 +6805,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -6823,7 +6823,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -6840,7 +6840,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -6857,7 +6857,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -6874,7 +6874,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -6890,7 +6890,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -6907,7 +6907,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -6922,7 +6922,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -6937,7 +6937,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -6952,7 +6952,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -6967,7 +6967,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -6982,7 +6982,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QU8, weights_cache_batched_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7000,7 +7000,7 @@ TEST(DECONVOLUTION_NHWC_QU8, weights_cache_batched_3x3s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7015,7 +7015,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -7032,7 +7032,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_Kx3s2) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -7049,7 +7049,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3xKs2) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -7067,7 +7067,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -7085,7 +7085,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -7106,7 +7106,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -7127,7 +7127,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -7146,7 +7146,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -7164,7 +7164,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -7182,7 +7182,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -7200,7 +7200,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -7217,7 +7217,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -7235,7 +7235,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7251,7 +7251,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7267,7 +7267,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7283,7 +7283,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7299,7 +7299,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -7315,7 +7315,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QU8, weights_cache_batched_grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7381,7 +7381,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_3x3s2_setup_changing_width) { /**************************** SUBCONV2D/GEMM path ****************************/ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7393,7 +7393,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2) { } TEST(DECONVOLUTION_NHWC_QU8, Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -7407,7 +7407,7 @@ TEST(DECONVOLUTION_NHWC_QU8, Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -7421,7 +7421,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7434,7 +7434,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7447,7 +7447,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -7462,7 +7462,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -7477,7 +7477,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -7491,7 +7491,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -7506,7 +7506,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7519,7 +7519,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7532,7 +7532,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7545,7 +7545,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7558,7 +7558,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -7571,7 +7571,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QU8, weights_cache_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7587,7 +7587,7 @@ TEST(DECONVOLUTION_NHWC_QU8, weights_cache_2x2s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7600,7 +7600,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -7615,7 +7615,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -7630,7 +7630,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7644,7 +7644,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7658,7 +7658,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -7674,7 +7674,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -7690,7 +7690,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -7705,7 +7705,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -7721,7 +7721,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7735,7 +7735,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7749,7 +7749,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7763,7 +7763,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7777,7 +7777,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -7791,7 +7791,7 @@ TEST(DECONVOLUTION_NHWC_QU8, grouped_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QU8, weights_cache_grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -7808,7 +7808,7 @@ TEST(DECONVOLUTION_NHWC_QU8, weights_cache_grouped_2x2s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7821,7 +7821,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2) { } TEST(DECONVOLUTION_NHWC_QU8, batched_Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -7836,7 +7836,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_QU8, batched_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -7851,7 +7851,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7865,7 +7865,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7879,7 +7879,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -7895,7 +7895,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -7911,7 +7911,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -7926,7 +7926,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -7942,7 +7942,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7956,7 +7956,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7970,7 +7970,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7984,7 +7984,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -7998,7 +7998,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -8012,7 +8012,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QU8, weights_cache_batched_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -8029,7 +8029,7 @@ TEST(DECONVOLUTION_NHWC_QU8, weights_cache_batched_2x2s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -8043,7 +8043,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -8059,7 +8059,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -8075,7 +8075,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -8090,7 +8090,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -8105,7 +8105,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -8122,7 +8122,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -8139,7 +8139,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -8155,7 +8155,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -8172,7 +8172,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -8187,7 +8187,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -8202,7 +8202,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -8217,7 +8217,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -8232,7 +8232,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -8247,7 +8247,7 @@ TEST(DECONVOLUTION_NHWC_QU8, batched_grouped_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_QU8, weights_cache_batched_grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_qu8_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_qu8_gemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -8309,7 +8309,7 @@ TEST(DECONVOLUTION_NHWC_QU8, kernel_2x2s2_setup_changing_width) { /**************************** Future GEMM path ****************************/ TEST(DECONVOLUTION_NHWC_F16, kernel_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8322,7 +8322,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_1x1) { } TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8336,7 +8336,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8352,7 +8352,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8368,7 +8368,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8383,7 +8383,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8399,7 +8399,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8413,7 +8413,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8427,7 +8427,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8441,7 +8441,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8455,7 +8455,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8472,7 +8472,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_1x1_without_bias) { * ****************************/ TEST(DECONVOLUTION_NHWC_F16, grouped_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8486,7 +8486,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_1x1) { } TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8501,7 +8501,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8518,7 +8518,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8535,7 +8535,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8551,7 +8551,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8568,7 +8568,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8583,7 +8583,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8598,7 +8598,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8613,7 +8613,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8628,7 +8628,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8646,7 +8646,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_1x1_without_bias) { * ****************************/ TEST(DECONVOLUTION_NHWC_F16, batched_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8660,7 +8660,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_1x1) { } TEST(DECONVOLUTION_NHWC_F16, batched_1x1_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8675,7 +8675,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_1x1_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, batched_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8692,7 +8692,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, batched_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8709,7 +8709,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, batched_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8725,7 +8725,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8742,7 +8742,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8757,7 +8757,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8772,7 +8772,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8787,7 +8787,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, batched_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8802,7 +8802,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, batched_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8820,7 +8820,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_1x1_without_bias) { * ****************************/ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8835,7 +8835,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8851,7 +8851,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8869,7 +8869,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8887,7 +8887,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8904,7 +8904,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8922,7 +8922,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8938,7 +8938,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8954,7 +8954,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8970,7 +8970,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -8986,7 +8986,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9004,7 +9004,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_1x1_without_bias) { /**************************** CONV path ****************************/ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9018,7 +9018,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9033,7 +9033,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9049,7 +9049,7 @@ TEST(DECONVOLUTION_NHWC_F16, Kx3) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9065,7 +9065,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3xK) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9085,7 +9085,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9105,7 +9105,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9124,7 +9124,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9142,7 +9142,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9159,7 +9159,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9176,7 +9176,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9192,7 +9192,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9209,7 +9209,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9226,7 +9226,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9243,7 +9243,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_width_dilation) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9259,7 +9259,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_height_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9275,7 +9275,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_width_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9290,7 +9290,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9305,7 +9305,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9320,7 +9320,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9335,7 +9335,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9350,7 +9350,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_F16, weights_cache_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9367,7 +9367,7 @@ TEST(DECONVOLUTION_NHWC_F16, weights_cache_3x3) { /**************************** CONV path, grouped ****************************/ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9382,7 +9382,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9398,7 +9398,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, grouped_Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9415,7 +9415,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_Kx3) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9432,7 +9432,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3xK) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9453,7 +9453,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9474,7 +9474,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9494,7 +9494,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9513,7 +9513,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9531,7 +9531,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9549,7 +9549,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9566,7 +9566,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9584,7 +9584,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9602,7 +9602,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9620,7 +9620,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_width_dilation) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9637,7 +9637,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_height_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9654,7 +9654,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_width_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9670,7 +9670,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9686,7 +9686,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9702,7 +9702,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9718,7 +9718,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9734,7 +9734,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_F16, weights_cache_grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9752,7 +9752,7 @@ TEST(DECONVOLUTION_NHWC_F16, weights_cache_grouped_3x3) { /**************************** CONV path, batched ****************************/ TEST(DECONVOLUTION_NHWC_F16, batched_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9767,7 +9767,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9783,7 +9783,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, batched_Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9800,7 +9800,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_Kx3) { } TEST(DECONVOLUTION_NHWC_F16, batched_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9817,7 +9817,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3xK) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9838,7 +9838,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9859,7 +9859,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9879,7 +9879,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9898,7 +9898,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9916,7 +9916,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9934,7 +9934,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9951,7 +9951,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9969,7 +9969,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -9987,7 +9987,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10005,7 +10005,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_width_dilation) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10022,7 +10022,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_height_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10039,7 +10039,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_width_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10055,7 +10055,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10071,7 +10071,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10087,7 +10087,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10103,7 +10103,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10119,7 +10119,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_F16, weights_cache_batched_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10138,7 +10138,7 @@ TEST(DECONVOLUTION_NHWC_F16, weights_cache_batched_3x3) { * ****************************/ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10154,7 +10154,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10171,7 +10171,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10189,7 +10189,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_Kx3) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10207,7 +10207,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3xK) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10229,7 +10229,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10251,7 +10251,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10272,7 +10272,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10292,7 +10292,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10311,7 +10311,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10330,7 +10330,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10348,7 +10348,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10367,7 +10367,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10386,7 +10386,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10406,7 +10406,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_width_dilation) { TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10425,7 +10425,7 @@ TEST(DECONVOLUTION_NHWC_F16, TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10443,7 +10443,7 @@ TEST(DECONVOLUTION_NHWC_F16, } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10460,7 +10460,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10477,7 +10477,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10494,7 +10494,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10511,7 +10511,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10528,7 +10528,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_F16, weights_cache_batched_grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10591,7 +10591,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3_setup_changing_width) { /**************************** SUBCONV2D/IGEMM path ****************************/ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10606,7 +10606,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10622,7 +10622,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10639,7 +10639,7 @@ TEST(DECONVOLUTION_NHWC_F16, Kx3s2) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10656,7 +10656,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3xKs2) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10674,7 +10674,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10692,7 +10692,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10713,7 +10713,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10734,7 +10734,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10753,7 +10753,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10771,7 +10771,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10789,7 +10789,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10807,7 +10807,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10824,7 +10824,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10842,7 +10842,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10858,7 +10858,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10874,7 +10874,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10890,7 +10890,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10906,7 +10906,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10922,7 +10922,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F16, weights_cache_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10941,7 +10941,7 @@ TEST(DECONVOLUTION_NHWC_F16, weights_cache_3x3s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10957,7 +10957,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10974,7 +10974,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, grouped_Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -10992,7 +10992,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_Kx3s2) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11010,7 +11010,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3xKs2) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11029,7 +11029,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11048,7 +11048,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11070,7 +11070,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11092,7 +11092,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11112,7 +11112,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11131,7 +11131,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11150,7 +11150,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11169,7 +11169,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11187,7 +11187,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11206,7 +11206,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11223,7 +11223,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11240,7 +11240,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11257,7 +11257,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11274,7 +11274,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11291,7 +11291,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F16, weights_cache_grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11311,7 +11311,7 @@ TEST(DECONVOLUTION_NHWC_F16, weights_cache_grouped_3x3s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11327,7 +11327,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11344,7 +11344,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, batched_Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11362,7 +11362,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_Kx3s2) { } TEST(DECONVOLUTION_NHWC_F16, batched_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11380,7 +11380,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3xKs2) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11399,7 +11399,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11418,7 +11418,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11440,7 +11440,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11462,7 +11462,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11482,7 +11482,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11501,7 +11501,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11520,7 +11520,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11539,7 +11539,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11557,7 +11557,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11576,7 +11576,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11593,7 +11593,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11610,7 +11610,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11627,7 +11627,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11644,7 +11644,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11661,7 +11661,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F16, weights_cache_batched_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11681,7 +11681,7 @@ TEST(DECONVOLUTION_NHWC_F16, weights_cache_batched_3x3s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11698,7 +11698,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11716,7 +11716,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11735,7 +11735,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_Kx3s2) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11754,7 +11754,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3xKs2) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11774,7 +11774,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11794,7 +11794,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11817,7 +11817,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11840,7 +11840,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11861,7 +11861,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11881,7 +11881,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11901,7 +11901,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11921,7 +11921,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11940,7 +11940,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11960,7 +11960,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11978,7 +11978,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -11996,7 +11996,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12014,7 +12014,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12032,7 +12032,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12050,7 +12050,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F16, weights_cache_batched_grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12101,7 +12101,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_3x3s2_setup_changing_width) { /**************************** SUBCONV2D/GEMM path ****************************/ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12115,7 +12115,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12130,7 +12130,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12146,7 +12146,7 @@ TEST(DECONVOLUTION_NHWC_F16, Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12162,7 +12162,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12177,7 +12177,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12192,7 +12192,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12209,7 +12209,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12226,7 +12226,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12242,7 +12242,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12259,7 +12259,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12274,7 +12274,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12289,7 +12289,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12304,7 +12304,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12319,7 +12319,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12334,7 +12334,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F16, weights_cache_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12352,7 +12352,7 @@ TEST(DECONVOLUTION_NHWC_F16, weights_cache_2x2s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12367,7 +12367,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12383,7 +12383,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, grouped_Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12400,7 +12400,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12417,7 +12417,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12433,7 +12433,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12449,7 +12449,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12467,7 +12467,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12485,7 +12485,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12502,7 +12502,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12520,7 +12520,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12536,7 +12536,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12552,7 +12552,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12568,7 +12568,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12584,7 +12584,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12600,7 +12600,7 @@ TEST(DECONVOLUTION_NHWC_F16, grouped_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F16, weights_cache_grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12619,7 +12619,7 @@ TEST(DECONVOLUTION_NHWC_F16, weights_cache_grouped_2x2s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12634,7 +12634,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2) { } TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12650,7 +12650,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, batched_Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12667,7 +12667,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_F16, batched_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12684,7 +12684,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12700,7 +12700,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12716,7 +12716,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12734,7 +12734,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12752,7 +12752,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12769,7 +12769,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12787,7 +12787,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12803,7 +12803,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12819,7 +12819,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12835,7 +12835,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12851,7 +12851,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12867,7 +12867,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F16, weights_cache_batched_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12886,7 +12886,7 @@ TEST(DECONVOLUTION_NHWC_F16, weights_cache_batched_2x2s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12902,7 +12902,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_with_fp32_weights) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12919,7 +12919,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_with_fp32_weights) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12937,7 +12937,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12955,7 +12955,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12972,7 +12972,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -12989,7 +12989,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -13008,7 +13008,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -13027,7 +13027,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -13045,7 +13045,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -13064,7 +13064,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -13081,7 +13081,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -13098,7 +13098,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -13115,7 +13115,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -13132,7 +13132,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -13149,7 +13149,7 @@ TEST(DECONVOLUTION_NHWC_F16, batched_grouped_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F16, weights_cache_batched_grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f16_gemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f16_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -13213,7 +13213,7 @@ TEST(DECONVOLUTION_NHWC_F16, kernel_2x2s2_setup_changing_width) { /**************************** Future GEMM path ****************************/ TEST(DECONVOLUTION_NHWC_F32, kernel_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13224,7 +13224,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_1x1) { } TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -13238,7 +13238,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -13252,7 +13252,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -13265,7 +13265,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -13279,7 +13279,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13291,7 +13291,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13303,7 +13303,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13315,7 +13315,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13327,7 +13327,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -13342,7 +13342,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_1x1_without_bias) { * ****************************/ TEST(DECONVOLUTION_NHWC_F32, grouped_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13354,7 +13354,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_1x1) { } TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -13369,7 +13369,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -13384,7 +13384,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -13398,7 +13398,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -13413,7 +13413,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13426,7 +13426,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13439,7 +13439,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13452,7 +13452,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13465,7 +13465,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -13481,7 +13481,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_1x1_without_bias) { * ****************************/ TEST(DECONVOLUTION_NHWC_F32, batched_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -13493,7 +13493,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_1x1) { } TEST(DECONVOLUTION_NHWC_F32, batched_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -13508,7 +13508,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, batched_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -13523,7 +13523,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, batched_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -13537,7 +13537,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -13552,7 +13552,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -13565,7 +13565,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -13578,7 +13578,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -13591,7 +13591,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, batched_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -13604,7 +13604,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, batched_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -13620,7 +13620,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_1x1_without_bias) { * ****************************/ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -13633,7 +13633,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -13649,7 +13649,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -13665,7 +13665,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -13680,7 +13680,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -13696,7 +13696,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -13710,7 +13710,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -13724,7 +13724,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -13738,7 +13738,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -13752,7 +13752,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -13768,7 +13768,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_1x1_without_bias) { /**************************** CONV path ****************************/ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13780,7 +13780,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3) { } TEST(DECONVOLUTION_NHWC_F32, Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -13794,7 +13794,7 @@ TEST(DECONVOLUTION_NHWC_F32, Kx3) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -13808,7 +13808,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3xK) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -13826,7 +13826,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -13844,7 +13844,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -13861,7 +13861,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -13877,7 +13877,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -13892,7 +13892,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -13907,7 +13907,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -13921,7 +13921,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -13936,7 +13936,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -13951,7 +13951,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -13966,7 +13966,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_width_dilation) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13980,7 +13980,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_height_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -13994,7 +13994,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_width_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14007,7 +14007,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14020,7 +14020,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14033,7 +14033,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14046,7 +14046,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -14059,7 +14059,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_F32, weights_cache_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14074,7 +14074,7 @@ TEST(DECONVOLUTION_NHWC_F32, weights_cache_3x3) { /**************************** CONV path, grouped ****************************/ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14087,7 +14087,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3) { } TEST(DECONVOLUTION_NHWC_F32, grouped_Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -14102,7 +14102,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_Kx3) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -14117,7 +14117,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3xK) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -14136,7 +14136,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -14155,7 +14155,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -14173,7 +14173,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -14190,7 +14190,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -14206,7 +14206,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -14222,7 +14222,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -14237,7 +14237,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -14253,7 +14253,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -14269,7 +14269,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -14285,7 +14285,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_width_dilation) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14300,7 +14300,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_height_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14315,7 +14315,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_width_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14329,7 +14329,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14343,7 +14343,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14357,7 +14357,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14371,7 +14371,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -14385,7 +14385,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_F32, weights_cache_grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kUnstridedInputHeight, kUnstridedInputWidth) @@ -14401,7 +14401,7 @@ TEST(DECONVOLUTION_NHWC_F32, weights_cache_grouped_3x3) { /**************************** CONV path, batched ****************************/ TEST(DECONVOLUTION_NHWC_F32, batched_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -14414,7 +14414,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3) { } TEST(DECONVOLUTION_NHWC_F32, batched_Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -14429,7 +14429,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_Kx3) { } TEST(DECONVOLUTION_NHWC_F32, batched_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -14444,7 +14444,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3xK) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -14463,7 +14463,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -14482,7 +14482,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -14500,7 +14500,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -14517,7 +14517,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -14533,7 +14533,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -14549,7 +14549,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -14564,7 +14564,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -14580,7 +14580,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -14596,7 +14596,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -14612,7 +14612,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_width_dilation) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -14627,7 +14627,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_height_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -14642,7 +14642,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_width_dilation_and_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -14656,7 +14656,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -14670,7 +14670,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -14684,7 +14684,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -14698,7 +14698,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -14712,7 +14712,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_F32, weights_cache_batched_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -14729,7 +14729,7 @@ TEST(DECONVOLUTION_NHWC_F32, weights_cache_batched_3x3) { * ****************************/ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -14743,7 +14743,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_Kx3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 1; kernel_height <= 4; kernel_height *= 2) { DeconvolutionOperatorTester() @@ -14759,7 +14759,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_Kx3) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 1; kernel_width <= 4; kernel_width *= 2) { DeconvolutionOperatorTester() @@ -14775,7 +14775,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3xK) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -14795,7 +14795,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -14815,7 +14815,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 1; adjustment_height <= 2; adjustment_height++) { @@ -14834,7 +14834,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 1; adjustment_width <= 2; adjustment_width++) { DeconvolutionOperatorTester() @@ -14852,7 +14852,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kUnstridedInputHeight - 2; input_height <= kUnstridedInputHeight + 2; input_height++) { @@ -14869,7 +14869,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kUnstridedInputWidth - 2; input_width <= kUnstridedInputWidth + 2; input_width++) { @@ -14886,7 +14886,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -14902,7 +14902,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -14919,7 +14919,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_height_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_height = 2; dilation_height <= 3; dilation_height++) { DeconvolutionOperatorTester() @@ -14936,7 +14936,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_height_dilation) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_width_dilation) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t dilation_width = 2; dilation_width <= 3; dilation_width++) { DeconvolutionOperatorTester() @@ -14954,7 +14954,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_width_dilation) { TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_height_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -14971,7 +14971,7 @@ TEST(DECONVOLUTION_NHWC_F32, TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_width_dilation_and_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -14987,7 +14987,7 @@ TEST(DECONVOLUTION_NHWC_F32, } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -15002,7 +15002,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -15017,7 +15017,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -15032,7 +15032,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -15047,7 +15047,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -15062,7 +15062,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3_without_bias) { } TEST(DECONVOLUTION_NHWC_F32, weights_cache_batched_grouped_3x3) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -15123,7 +15123,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3_setup_changing_width) { /**************************** SUBCONV2D/IGEMM path ****************************/ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15136,7 +15136,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2) { } TEST(DECONVOLUTION_NHWC_F32, Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -15151,7 +15151,7 @@ TEST(DECONVOLUTION_NHWC_F32, Kx3s2) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -15166,7 +15166,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3xKs2) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -15182,7 +15182,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -15198,7 +15198,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -15217,7 +15217,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -15236,7 +15236,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -15253,7 +15253,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -15269,7 +15269,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -15285,7 +15285,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -15301,7 +15301,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -15316,7 +15316,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -15332,7 +15332,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15346,7 +15346,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15360,7 +15360,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15374,7 +15374,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15388,7 +15388,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -15402,7 +15402,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F32, weights_cache_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15416,7 +15416,7 @@ TEST(DECONVOLUTION_NHWC_F32, weights_cache_3x3s2) { } TEST(DECONVOLUTION_NHWC_F32, stress_weights_cache_5x5s4) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15432,7 +15432,7 @@ TEST(DECONVOLUTION_NHWC_F32, stress_weights_cache_5x5s4) { * ****************************/ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15446,7 +15446,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2) { } TEST(DECONVOLUTION_NHWC_F32, grouped_Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -15462,7 +15462,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_Kx3s2) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -15478,7 +15478,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3xKs2) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -15495,7 +15495,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -15512,7 +15512,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -15532,7 +15532,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -15552,7 +15552,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -15570,7 +15570,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -15587,7 +15587,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -15604,7 +15604,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -15621,7 +15621,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -15637,7 +15637,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -15654,7 +15654,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15669,7 +15669,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15684,7 +15684,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15699,7 +15699,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15714,7 +15714,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -15729,7 +15729,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F32, weights_cache_grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -15747,7 +15747,7 @@ TEST(DECONVOLUTION_NHWC_F32, weights_cache_grouped_3x3s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -15761,7 +15761,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2) { } TEST(DECONVOLUTION_NHWC_F32, batched_Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -15777,7 +15777,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_Kx3s2) { } TEST(DECONVOLUTION_NHWC_F32, batched_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -15793,7 +15793,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3xKs2) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -15810,7 +15810,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -15827,7 +15827,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -15847,7 +15847,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -15867,7 +15867,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -15885,7 +15885,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -15902,7 +15902,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -15919,7 +15919,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -15936,7 +15936,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -15952,7 +15952,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -15969,7 +15969,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -15984,7 +15984,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -15999,7 +15999,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -16014,7 +16014,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -16029,7 +16029,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -16044,7 +16044,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F32, weights_cache_batched_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -16062,7 +16062,7 @@ TEST(DECONVOLUTION_NHWC_F32, weights_cache_batched_3x3s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -16077,7 +16077,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_Kx3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 2; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -16094,7 +16094,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_Kx3s2) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3xKs2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 2; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -16111,7 +16111,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3xKs2) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3sSx1) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_height = 2; stride_height <= 3; stride_height++) { DeconvolutionOperatorTester() @@ -16129,7 +16129,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3sSx1) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s1xS) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t stride_width = 2; stride_width <= 3; stride_width++) { DeconvolutionOperatorTester() @@ -16147,7 +16147,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s1xS) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_height_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_top = 0; padding_top <= 2; padding_top++) { for (size_t padding_bottom = 0; padding_bottom <= 2; padding_bottom++) { @@ -16168,7 +16168,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_height_padding) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_width_padding) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t padding_left = 0; padding_left <= 2; padding_left++) { for (size_t padding_right = 0; padding_right <= 2; padding_right++) { @@ -16189,7 +16189,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_width_padding) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_height = 0; adjustment_height <= 1; adjustment_height++) { @@ -16208,7 +16208,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t adjustment_width = 0; adjustment_width <= 1; adjustment_width++) { DeconvolutionOperatorTester() @@ -16226,7 +16226,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -16244,7 +16244,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -16262,7 +16262,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -16279,7 +16279,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -16297,7 +16297,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -16313,7 +16313,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -16329,7 +16329,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -16345,7 +16345,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -16361,7 +16361,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -16377,7 +16377,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_3x3s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F32, weights_cache_batched_grouped_3x3s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -16440,7 +16440,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_3x3s2_setup_changing_width) { /**************************** SUBCONV2D/GEMM path ****************************/ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16452,7 +16452,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2) { } TEST(DECONVOLUTION_NHWC_F32, Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -16466,7 +16466,7 @@ TEST(DECONVOLUTION_NHWC_F32, Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_F32, kernel_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -16480,7 +16480,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16493,7 +16493,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16506,7 +16506,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -16521,7 +16521,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -16536,7 +16536,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -16550,7 +16550,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -16565,7 +16565,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16578,7 +16578,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16591,7 +16591,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16604,7 +16604,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16617,7 +16617,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -16630,7 +16630,7 @@ TEST(DECONVOLUTION_NHWC_F32, kernel_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F32, weights_cache_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16646,7 +16646,7 @@ TEST(DECONVOLUTION_NHWC_F32, weights_cache_2x2s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16659,7 +16659,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2) { } TEST(DECONVOLUTION_NHWC_F32, grouped_Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -16674,7 +16674,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_F32, grouped_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -16689,7 +16689,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16703,7 +16703,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16717,7 +16717,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -16733,7 +16733,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -16749,7 +16749,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -16764,7 +16764,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -16780,7 +16780,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16794,7 +16794,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16808,7 +16808,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16822,7 +16822,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16836,7 +16836,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -16850,7 +16850,7 @@ TEST(DECONVOLUTION_NHWC_F32, grouped_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F32, weights_cache_grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .input_size(kStridedInputHeight, kStridedInputWidth) @@ -16867,7 +16867,7 @@ TEST(DECONVOLUTION_NHWC_F32, weights_cache_grouped_2x2s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -16880,7 +16880,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2) { } TEST(DECONVOLUTION_NHWC_F32, batched_Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -16895,7 +16895,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_F32, batched_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -16910,7 +16910,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -16924,7 +16924,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -16938,7 +16938,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -16954,7 +16954,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -16970,7 +16970,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 1; input_channels <= 16; input_channels *= 4) { DeconvolutionOperatorTester() @@ -16985,7 +16985,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -17001,7 +17001,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -17015,7 +17015,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -17029,7 +17029,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -17043,7 +17043,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -17057,7 +17057,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -17071,7 +17071,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F32, weights_cache_batched_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -17088,7 +17088,7 @@ TEST(DECONVOLUTION_NHWC_F32, weights_cache_batched_2x2s2) { * ****************************/ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -17102,7 +17102,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_Kx2sKx2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_height = 3; kernel_height <= 5; kernel_height++) { DeconvolutionOperatorTester() @@ -17118,7 +17118,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_Kx2sKx2) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2xKs2xK) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t kernel_width = 3; kernel_width <= 5; kernel_width++) { DeconvolutionOperatorTester() @@ -17134,7 +17134,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2xKs2xK) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_height_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -17149,7 +17149,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_height_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_width_adjustment) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -17164,7 +17164,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_width_adjustment) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_varying_input_height) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_height = kStridedInputHeight - 2; input_height <= kStridedInputHeight + 2; input_height++) { @@ -17181,7 +17181,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_varying_input_height) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_varying_input_width) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_width = kStridedInputWidth - 2; input_width <= kStridedInputWidth + 2; input_width++) { @@ -17198,7 +17198,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_varying_input_width) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_varying_input_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t input_channels = 14; input_channels <= 20; input_channels++) { DeconvolutionOperatorTester() @@ -17214,7 +17214,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_varying_input_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_varying_output_channels) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); for (size_t output_channels = 1; output_channels <= gemm_config->nr * 2; output_channels *= 2) { @@ -17231,7 +17231,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_varying_output_channels) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_with_input_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -17246,7 +17246,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_with_input_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_with_output_stride) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -17261,7 +17261,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_with_output_stride) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_with_qmin) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -17276,7 +17276,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_with_qmin) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_with_qmax) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) @@ -17291,7 +17291,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_with_qmax) { } TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_without_bias) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .has_bias(false) @@ -17306,7 +17306,7 @@ TEST(DECONVOLUTION_NHWC_F32, batched_grouped_2x2s2_without_bias) { } TEST(DECONVOLUTION_NHWC_F32, weights_cache_batched_grouped_2x2s2) { - const struct xnn_gemm_config* gemm_config = xnn_init_f32_igemm_config(); + const struct xnn_gemm_config* gemm_config = xnn_get_f32_igemm_config(); ASSERT_NE(gemm_config, nullptr); DeconvolutionOperatorTester() .batch_size(2) diff --git a/test/operators/fully-connected-operator-tester.h b/test/operators/fully-connected-operator-tester.h index d63f4850f3c..d2e52f16571 100644 --- a/test/operators/fully-connected-operator-tester.h +++ b/test/operators/fully-connected-operator-tester.h @@ -1095,7 +1095,7 @@ class FullyConnectedOperatorTester { void TestQP8F32QC4W() const { // Get the parameters of this GEMM, skip if not available. const struct xnn_gemm_config* gemm_config = - xnn_init_qp8_f32_qc4w_gemm_config(); + xnn_get_qp8_f32_qc4w_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); } @@ -1325,7 +1325,7 @@ class FullyConnectedOperatorTester { void TestQP8F32QC8W() const { // Get the parameters of this GEMM, skip if not available. const struct xnn_gemm_config* gemm_config = - xnn_init_qp8_f32_qc8w_gemm_config(); + xnn_get_qp8_f32_qc8w_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); } @@ -1538,7 +1538,7 @@ class FullyConnectedOperatorTester { void TestQP8F32QB4W() const { // Get the parameters of this GEMM, skip if not available. const struct xnn_gemm_config* gemm_config = - xnn_init_qp8_f32_qb4w_gemm_config(); + xnn_get_qp8_f32_qb4w_gemm_config(); if (gemm_config == nullptr) { GTEST_SKIP(); } diff --git a/test/operators/max-pooling-nhwc.cc b/test/operators/max-pooling-nhwc.cc index 2ccd5f4ac2f..4412476f964 100644 --- a/test/operators/max-pooling-nhwc.cc +++ b/test/operators/max-pooling-nhwc.cc @@ -18,7 +18,7 @@ constexpr int max_pool_size = 25; TEST(MAX_POOLING_NHWC_S8, unit_batch_small_1xM_pool) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -36,7 +36,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_1xM_pool) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_1xM_pool_with_padding) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 3; pool_size <= max_pool_size; pool_size++) { @@ -60,7 +60,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_1xM_pool_with_padding) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_1xM_pool_with_tf_same_padding) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 3; pool_size <= max_pool_size; pool_size++) { @@ -82,7 +82,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_1xM_pool_with_tf_same_padding) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_1xM_pool_with_stride) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -101,7 +101,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_1xM_pool_with_stride) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_1xM_pool_with_dilation) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -122,7 +122,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_1xM_pool_with_dilation) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_Mx1_pool) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -140,7 +140,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_Mx1_pool) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_Mx1_pool_with_padding) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -164,7 +164,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_Mx1_pool_with_padding) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_Mx1_pool_with_tf_same_padding) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -186,7 +186,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_Mx1_pool_with_tf_same_padding) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_Mx1_pool_with_stride) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -205,7 +205,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_Mx1_pool_with_stride) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_Mx1_pool_with_dilation) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -226,7 +226,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_Mx1_pool_with_dilation) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_pool_with_input_stride) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -254,7 +254,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_pool_with_input_stride) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_pool_with_output_stride) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -282,7 +282,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_pool_with_output_stride) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_pool_with_qmin) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -310,7 +310,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_pool_with_qmin) { TEST(MAX_POOLING_NHWC_S8, unit_batch_small_pool_with_qmax) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -338,7 +338,7 @@ TEST(MAX_POOLING_NHWC_S8, unit_batch_small_pool_with_qmax) { TEST(MAX_POOLING_NHWC_S8, small_batch_small_pool) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -364,7 +364,7 @@ TEST(MAX_POOLING_NHWC_S8, small_batch_small_pool) { TEST(MAX_POOLING_NHWC_S8, small_batch_small_pool_with_input_stride) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -392,7 +392,7 @@ TEST(MAX_POOLING_NHWC_S8, small_batch_small_pool_with_input_stride) { TEST(MAX_POOLING_NHWC_S8, small_batch_small_pool_with_output_stride) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_s8_maxpool_config(); + xnn_get_s8_maxpool_config(); ASSERT_NE(maxpool_config, nullptr); for (size_t channels = 1; channels <= 100; channels += 15) { for (size_t pool_size = 2; pool_size <= max_pool_size; pool_size++) { @@ -940,7 +940,7 @@ TEST(MAX_POOLING_NHWC_U8, setup_swap_height_and_width) { #ifndef XNN_EXCLUDE_F16_TESTS TEST(MAX_POOLING_NHWC_F16, unit_batch_small_1xM_pool) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -960,7 +960,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_1xM_pool) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_1xM_pool_with_padding) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -986,7 +986,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_1xM_pool_with_padding) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_1xM_pool_with_tf_same_padding) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1010,7 +1010,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_1xM_pool_with_tf_same_padding) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_1xM_pool_with_stride) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1031,7 +1031,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_1xM_pool_with_stride) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_1xM_pool_with_dilation) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1054,7 +1054,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_1xM_pool_with_dilation) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_Mx1_pool) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1074,7 +1074,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_Mx1_pool) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_Mx1_pool_with_padding) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1100,7 +1100,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_Mx1_pool_with_padding) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_Mx1_pool_with_tf_same_padding) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1124,7 +1124,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_Mx1_pool_with_tf_same_padding) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_Mx1_pool_with_stride) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1145,7 +1145,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_Mx1_pool_with_stride) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_Mx1_pool_with_dilation) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1168,7 +1168,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_Mx1_pool_with_dilation) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_pool_with_input_stride) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1198,7 +1198,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_pool_with_input_stride) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_pool_with_output_stride) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1228,7 +1228,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_pool_with_output_stride) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_pool_with_qmin) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1258,7 +1258,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_pool_with_qmin) { TEST(MAX_POOLING_NHWC_F16, unit_batch_small_pool_with_qmax) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1288,7 +1288,7 @@ TEST(MAX_POOLING_NHWC_F16, unit_batch_small_pool_with_qmax) { TEST(MAX_POOLING_NHWC_F16, small_batch_small_pool) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1316,7 +1316,7 @@ TEST(MAX_POOLING_NHWC_F16, small_batch_small_pool) { TEST(MAX_POOLING_NHWC_F16, small_batch_small_pool_with_input_stride) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } @@ -1346,7 +1346,7 @@ TEST(MAX_POOLING_NHWC_F16, small_batch_small_pool_with_input_stride) { TEST(MAX_POOLING_NHWC_F16, small_batch_small_pool_with_output_stride) { const struct xnn_maxpool_config* maxpool_config = - xnn_init_f16_maxpool_config(); + xnn_get_f16_maxpool_config(); if (maxpool_config == nullptr) { GTEST_SKIP(); // F16 unsupported. } diff --git a/test/qd8-f32-qc4w-gemm-minmax-2.cc b/test/qd8-f32-qc4w-gemm-minmax-2.cc index acbe1923db0..1d2fb8ecbbe 100644 --- a/test/qd8-f32-qc4w-gemm-minmax-2.cc +++ b/test/qd8-f32-qc4w-gemm-minmax-2.cc @@ -322,7 +322,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qd8-f32-qc4w-gemm-minmax-3.cc b/test/qd8-f32-qc4w-gemm-minmax-3.cc index 8fdacb9bf62..e22e458284d 100644 --- a/test/qd8-f32-qc4w-gemm-minmax-3.cc +++ b/test/qd8-f32-qc4w-gemm-minmax-3.cc @@ -322,7 +322,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qd8-f32-qc4w-gemm-minmax-4.cc b/test/qd8-f32-qc4w-gemm-minmax-4.cc index d16111c9b7a..bcc0668494e 100644 --- a/test/qd8-f32-qc4w-gemm-minmax-4.cc +++ b/test/qd8-f32-qc4w-gemm-minmax-4.cc @@ -322,7 +322,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qd8-f32-qc4w-gemm-minmax.cc b/test/qd8-f32-qc4w-gemm-minmax.cc index d6ee9a01a7f..f5878ca101b 100644 --- a/test/qd8-f32-qc4w-gemm-minmax.cc +++ b/test/qd8-f32-qc4w-gemm-minmax.cc @@ -322,7 +322,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qd8-f32-qc8w-gemm-minmax-2.cc b/test/qd8-f32-qc8w-gemm-minmax-2.cc index 2484fe10b23..290dba5519b 100644 --- a/test/qd8-f32-qc8w-gemm-minmax-2.cc +++ b/test/qd8-f32-qc8w-gemm-minmax-2.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qd8-f32-qc8w-gemm-minmax-3.cc b/test/qd8-f32-qc8w-gemm-minmax-3.cc index 9c872be0b52..5b53810179b 100644 --- a/test/qd8-f32-qc8w-gemm-minmax-3.cc +++ b/test/qd8-f32-qc8w-gemm-minmax-3.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qd8-f32-qc8w-gemm-minmax-4.cc b/test/qd8-f32-qc8w-gemm-minmax-4.cc index 03c2151b3f7..732603b22b0 100644 --- a/test/qd8-f32-qc8w-gemm-minmax-4.cc +++ b/test/qd8-f32-qc8w-gemm-minmax-4.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qd8-f32-qc8w-gemm-minmax.cc b/test/qd8-f32-qc8w-gemm-minmax.cc index 0c088124cff..7802c0613b0 100644 --- a/test/qd8-f32-qc8w-gemm-minmax.cc +++ b/test/qd8-f32-qc8w-gemm-minmax.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qd8-f32-qc8w-igemm-minmax-2.cc b/test/qd8-f32-qc8w-igemm-minmax-2.cc index 8d20ea50cd2..b836dbfed4b 100644 --- a/test/qd8-f32-qc8w-igemm-minmax-2.cc +++ b/test/qd8-f32-qc8w-igemm-minmax-2.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qd8-f32-qc8w-igemm-minmax-3.cc b/test/qd8-f32-qc8w-igemm-minmax-3.cc index 93abef3c03a..0428343a362 100644 --- a/test/qd8-f32-qc8w-igemm-minmax-3.cc +++ b/test/qd8-f32-qc8w-igemm-minmax-3.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qd8-f32-qc8w-igemm-minmax.cc b/test/qd8-f32-qc8w-igemm-minmax.cc index 5d83f0d9d00..1c1d51e80f0 100644 --- a/test/qd8-f32-qc8w-igemm-minmax.cc +++ b/test/qd8-f32-qc8w-igemm-minmax.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qs8-qc8w-gemm-minmax-fp32-2.cc b/test/qs8-qc8w-gemm-minmax-fp32-2.cc index 583e52ef456..055a159fd48 100644 --- a/test/qs8-qc8w-gemm-minmax-fp32-2.cc +++ b/test/qs8-qc8w-gemm-minmax-fp32-2.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qs8-qc8w-gemm-minmax-fp32-3.cc b/test/qs8-qc8w-gemm-minmax-fp32-3.cc index 48853a35106..767ec14745e 100644 --- a/test/qs8-qc8w-gemm-minmax-fp32-3.cc +++ b/test/qs8-qc8w-gemm-minmax-fp32-3.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qs8-qc8w-gemm-minmax-fp32.cc b/test/qs8-qc8w-gemm-minmax-fp32.cc index 86925d6f0de..0b6c59bb7cb 100644 --- a/test/qs8-qc8w-gemm-minmax-fp32.cc +++ b/test/qs8-qc8w-gemm-minmax-fp32.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qs8-qc8w-igemm-minmax-fp32-2.cc b/test/qs8-qc8w-igemm-minmax-fp32-2.cc index f6ddbaad13c..f1304b0319e 100644 --- a/test/qs8-qc8w-igemm-minmax-fp32-2.cc +++ b/test/qs8-qc8w-igemm-minmax-fp32-2.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qs8-qc8w-igemm-minmax-fp32-3.cc b/test/qs8-qc8w-igemm-minmax-fp32-3.cc index 51c0c735037..c7b2fe27abf 100644 --- a/test/qs8-qc8w-igemm-minmax-fp32-3.cc +++ b/test/qs8-qc8w-igemm-minmax-fp32-3.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/qs8-qc8w-igemm-minmax-fp32.cc b/test/qs8-qc8w-igemm-minmax-fp32.cc index 8592876da24..ae9d0f18181 100644 --- a/test/qs8-qc8w-igemm-minmax-fp32.cc +++ b/test/qs8-qc8w-igemm-minmax-fp32.cc @@ -292,7 +292,7 @@ std::vector CreateTests1( std::string kbs = std::to_string(k_block); std::string kb2s = std::to_string(k_block * 2); std::string akbs = std::to_string(adj_k_block); - nr = nr * xnn_init_hardware_config()->vlenb / sizeof(int32_t); + nr = nr * xnn_get_hardware_config()->vlenb / sizeof(int32_t); std::string nrs = std::to_string(nr); const GemmMicrokernelTester tester = GemmMicrokernelTester() diff --git a/test/subgraph/input-output.cc b/test/subgraph/input-output.cc index 67c97320b95..ea4379b8060 100644 --- a/test/subgraph/input-output.cc +++ b/test/subgraph/input-output.cc @@ -35,7 +35,7 @@ INSTANTIATE_TEST_SUITE_P( TEST_P(InputOutput, ConditionalReadWrite) { const bool rewrite_for_fp16 = GetParam(); if (rewrite_for_fp16 && - !xnn_is_f16_compatible_config(xnn_init_hardware_config())) { + !xnn_is_f16_compatible_config(xnn_get_hardware_config())) { GTEST_SKIP() << "No FP16 support detected."; } @@ -120,7 +120,7 @@ TEST_P(InputOutput, ConditionalReadWrite) { TEST_P(InputOutput, SlidingWindow) { const bool rewrite_for_fp16 = GetParam(); if (rewrite_for_fp16 && - !xnn_is_f16_compatible_config(xnn_init_hardware_config())) { + !xnn_is_f16_compatible_config(xnn_get_hardware_config())) { GTEST_SKIP() << "No FP16 support detected."; } @@ -188,7 +188,7 @@ TEST_P(InputOutput, SlidingWindow) { TEST_P(InputOutput, MultipleWrites) { const bool rewrite_for_fp16 = GetParam(); if (rewrite_for_fp16 && - !xnn_is_f16_compatible_config(xnn_init_hardware_config())) { + !xnn_is_f16_compatible_config(xnn_get_hardware_config())) { GTEST_SKIP() << "No FP16 support detected."; } diff --git a/tools/generate-argmaxpool-test.py b/tools/generate-argmaxpool-test.py index 7286e17a328..07351b1881b 100755 --- a/tools/generate-argmaxpool-test.py +++ b/tools/generate-argmaxpool-test.py @@ -625,7 +625,7 @@ def generate_test_cases( ctype = {"f16": "uint16_t", "f32": "float"}[datatype] channel_scaled_tile = { "rvv": ( - "(%s * xnn_init_hardware_config()->vlenb / sizeof(%s))" + "(%s * xnn_get_hardware_config()->vlenb / sizeof(%s))" % (str(channel_tile), ctype) ) }[isa] diff --git a/tools/generate-conv-hwc2chw-test.py b/tools/generate-conv-hwc2chw-test.py index 941dd67deeb..a5a8318f871 100755 --- a/tools/generate-conv-hwc2chw-test.py +++ b/tools/generate-conv-hwc2chw-test.py @@ -491,7 +491,7 @@ def generate_test_cases( is_vector = "" if (vector_tile): ctype = {"f16": "uint16_t", "f32": "float"}[datatype] - output_channels_scale = {"rvv": " * xnn_init_hardware_config()->vlenb / sizeof(%s)" % ctype}[isa] + output_channels_scale = {"rvv": " * xnn_get_hardware_config()->vlenb / sizeof(%s)" % ctype}[isa] is_vector = "v" test_args = [ukernel, init_fn] diff --git a/tools/generate-dwconv2d-chw-test.py b/tools/generate-dwconv2d-chw-test.py index 4cdf54117aa..1e99ad33ae2 100755 --- a/tools/generate-dwconv2d-chw-test.py +++ b/tools/generate-dwconv2d-chw-test.py @@ -374,7 +374,7 @@ def generate_test_cases( is_vector = "" if (vector_tile): ctype = {"f16": "uint16_t", "f32": "float"}[datatype] - width_scale = {"rvv": " * xnn_init_hardware_config()->vlenb / sizeof(%s)" % ctype}[isa] + width_scale = {"rvv": " * xnn_get_hardware_config()->vlenb / sizeof(%s)" % ctype}[isa] is_vector = "v" test_args = [ukernel, init_fn] diff --git a/tools/generate-gemm-test.py b/tools/generate-gemm-test.py index 697d574a51f..0459cb9c489 100755 --- a/tools/generate-gemm-test.py +++ b/tools/generate-gemm-test.py @@ -776,7 +776,7 @@ def generate_test_cases( }[input_datatype] ) nr_scale = { - "rvv": " * xnn_init_hardware_config()->vlenb / sizeof(%s)" % accum_type + "rvv": " * xnn_get_hardware_config()->vlenb / sizeof(%s)" % accum_type }[isa] test_fun_name = "".join(ukernel.split("_")[1:4]).upper() if test_fun_name in {"QP8F32QC8W"}: diff --git a/tools/generate-raddstoreexpminusmax-test.py b/tools/generate-raddstoreexpminusmax-test.py index 5df2f7b4d6d..92ea1e556bb 100755 --- a/tools/generate-raddstoreexpminusmax-test.py +++ b/tools/generate-raddstoreexpminusmax-test.py @@ -142,9 +142,9 @@ def generate_test_cases(ukernel, init_fn, elements_tile, vector_tile, isa): if vector_tile: ctype = {"f16": "uint16_t", "f32": "float"}[datatype] elements_scale = { - "rvv": " * xnn_init_hardware_config()->vlenb / sizeof(%s)" % ctype, + "rvv": " * xnn_get_hardware_config()->vlenb / sizeof(%s)" % ctype, "rvvfp16arith": ( - " * xnn_init_hardware_config()->vlenb / sizeof(%s)" % ctype + " * xnn_get_hardware_config()->vlenb / sizeof(%s)" % ctype ), }[isa] diff --git a/tools/generate-reduce-discontiguous-test.py b/tools/generate-reduce-discontiguous-test.py index 1cf9bd64e65..38ce6cbc5f3 100755 --- a/tools/generate-reduce-discontiguous-test.py +++ b/tools/generate-reduce-discontiguous-test.py @@ -401,7 +401,7 @@ def generate_test_cases( }[datatype] channel_scaled_tile = { "rvv": ( - "(%s*xnn_init_hardware_config()->vlenb/sizeof(%s))" + "(%s*xnn_get_hardware_config()->vlenb/sizeof(%s))" % (str(channel_tile), ctype) ) }[isa] diff --git a/tools/generate-reduce-test.py b/tools/generate-reduce-test.py index 730398e9e01..b0fea2fce64 100755 --- a/tools/generate-reduce-test.py +++ b/tools/generate-reduce-test.py @@ -205,9 +205,9 @@ def generate_test_cases( "f32": "float", }[datatype] batch_scale = { - "rvv": " * xnn_init_hardware_config()->vlenb / sizeof(%s)" % ctype, + "rvv": " * xnn_get_hardware_config()->vlenb / sizeof(%s)" % ctype, "rvvfp16arith": ( - " * xnn_init_hardware_config()->vlenb / sizeof(%s)" % ctype + " * xnn_get_hardware_config()->vlenb / sizeof(%s)" % ctype ), }[isa] return xngen.preprocess( diff --git a/tools/generate-spmm-test.py b/tools/generate-spmm-test.py index 39da7a9093f..4b7db70b250 100755 --- a/tools/generate-spmm-test.py +++ b/tools/generate-spmm-test.py @@ -418,7 +418,7 @@ def generate_test_cases(ukernel, init_fn, mr, nr, k_block, vector_tile, is_pipel is_vector = "" if vector_tile: ctype = {"f16": "uint16_t", "f32": "float"}[datatype] - mr_scale = {"rvv": " * xnn_init_hardware_config()->vlenb / sizeof(%s)" % ctype}[isa] + mr_scale = {"rvv": " * xnn_get_hardware_config()->vlenb / sizeof(%s)" % ctype}[isa] is_vector = "v" next_prime_for_output_stride = "xnnpack::NextPrime(" + str(mr) + str(mr_scale) + " * 2 + 1)" else: