@@ -24,8 +24,7 @@ mod pl011;
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mod pl031;
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use crate :: pl031:: Rtc ;
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- use arm_gic:: gicv3:: { IntId , Trigger } ;
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- use arm_gic:: { irq_enable, wfi} ;
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+ use arm_gic:: { irq_enable, wfi, IntId , Trigger } ;
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use chrono:: { TimeZone , Utc } ;
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use core:: hint:: spin_loop;
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// ANCHOR: imports
@@ -63,8 +62,9 @@ extern "C" fn main(x0: u64, x1: u64, x2: u64, x3: u64) {
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// SAFETY: `GICD_BASE_ADDRESS` and `GICR_BASE_ADDRESS` are the base
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// addresses of a GICv3 distributor and redistributor respectively, and
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// nothing else accesses those address ranges.
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- let mut gic = unsafe { GicV3 :: new ( GICD_BASE_ADDRESS , GICR_BASE_ADDRESS ) } ;
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- gic. setup ( ) ;
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+ let mut gic =
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+ unsafe { GicV3 :: new ( GICD_BASE_ADDRESS , GICR_BASE_ADDRESS , 1 , 0x20000 ) } ;
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+ gic. setup ( 0 ) ;
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// ANCHOR_END: main
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// SAFETY: `PL031_BASE_ADDRESS` is the base address of a PL031 device, and
@@ -75,10 +75,10 @@ extern "C" fn main(x0: u64, x1: u64, x2: u64, x3: u64) {
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info ! ( "RTC: {time}" ) ;
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GicV3 :: set_priority_mask ( 0xff ) ;
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- gic. set_interrupt_priority ( PL031_IRQ , 0x80 ) ;
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- gic. set_trigger ( PL031_IRQ , Trigger :: Level ) ;
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+ gic. set_interrupt_priority ( PL031_IRQ , None , 0x80 ) ;
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+ gic. set_trigger ( PL031_IRQ , None , Trigger :: Level ) ;
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irq_enable ( ) ;
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- gic. enable_interrupt ( PL031_IRQ , true ) ;
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+ gic. enable_interrupt ( PL031_IRQ , None , true ) ;
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// Wait for 3 seconds, without interrupts.
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let target = timestamp + 3 ;
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