refactor: impl ReadReady for Console

Author: mkroening

src/arch/aarch64/kernel/serial.rs

@@ -1,6 +1,6 @@
 use core::arch::asm;
 
-use embedded_io::{ErrorType, Read, Write};
+use embedded_io::{ErrorType, Read, ReadReady, Write};
 
 use crate::errno::Errno;
 
@@ -18,10 +18,6 @@ impl SerialDevice {
 
 		Self { addr: base as u32 }
 	}
-
-	pub fn can_read(&self) -> bool {
-		false
-	}
 }
 
 impl ErrorType for SerialDevice {
@@ -35,6 +31,12 @@ impl Read for SerialDevice {
 	}
 }
 
+impl ReadReady for SerialDevice {
+	fn read_ready(&mut self) -> Result<bool, Self::Error> {
+		Ok(false)
+	}
+}
+
 impl Write for SerialDevice {
 	fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
 		let port = core::ptr::with_exposed_provenance_mut::<u8>(self.addr as usize);

src/arch/riscv64/kernel/serial.rs

@@ -1,4 +1,4 @@
-use embedded_io::{ErrorType, Read, Write};
+use embedded_io::{ErrorType, Read, ReadReady, Write};
 
 use crate::errno::Errno;
 
@@ -8,10 +8,6 @@ impl SerialDevice {
 	pub fn new() -> Self {
 		Self {}
 	}
-
-	pub fn can_read(&self) -> bool {
-		false
-	}
 }
 
 impl ErrorType for SerialDevice {
@@ -25,6 +21,12 @@ impl Read for SerialDevice {
 	}
 }
 
+impl ReadReady for SerialDevice {
+	fn read_ready(&mut self) -> Result<bool, Self::Error> {
+		Ok(false)
+	}
+}
+
 impl Write for SerialDevice {
 	fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
 		for byte in buf {

src/arch/x86_64/kernel/serial.rs

@@ -1,7 +1,7 @@
 use alloc::collections::VecDeque;
 use alloc::vec::Vec;
 
-use embedded_io::{ErrorType, Read, Write};
+use embedded_io::{ErrorType, Read, ReadReady, Write};
 use hermit_sync::{InterruptTicketMutex, Lazy};
 
 #[cfg(feature = "pci")]
@@ -44,10 +44,6 @@ impl SerialDevice {
 	pub fn new() -> Self {
 		Self {}
 	}
-
-	pub fn can_read(&self) -> bool {
-		!UART_DEVICE.lock().buffer.is_empty()
-	}
 }
 
 impl ErrorType for SerialDevice {
@@ -68,6 +64,13 @@ impl Read for SerialDevice {
 	}
 }
 
+impl ReadReady for SerialDevice {
+	fn read_ready(&mut self) -> Result<bool, Self::Error> {
+		let read_ready = !UART_DEVICE.lock().buffer.is_empty();
+		Ok(read_ready)
+	}
+}
+
 impl Write for SerialDevice {
 	fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
 		let mut guard = UART_DEVICE.lock();

src/console.rs

@@ -2,7 +2,7 @@
 
 use core::{fmt, mem};
 
-use embedded_io::{ErrorType, Read, Write};
+use embedded_io::{ErrorType, Read, ReadReady, Write};
 use heapless::Vec;
 use hermit_sync::{InterruptTicketMutex, Lazy};
 
@@ -24,18 +24,6 @@ pub(crate) enum IoDevice {
 	Virtio(VirtioUART),
 }
 
-impl IoDevice {
-	pub fn can_read(&self) -> bool {
-		match self {
-			#[cfg(not(target_arch = "riscv64"))]
-			IoDevice::Uhyve(s) => s.can_read(),
-			IoDevice::Uart(s) => s.can_read(),
-			#[cfg(feature = "console")]
-			IoDevice::Virtio(s) => s.can_read(),
-		}
-	}
-}
-
 impl ErrorType for IoDevice {
 	type Error = Errno;
 }
@@ -52,6 +40,18 @@ impl Read for IoDevice {
 	}
 }
 
+impl ReadReady for IoDevice {
+	fn read_ready(&mut self) -> Result<bool, Self::Error> {
+		match self {
+			#[cfg(not(target_arch = "riscv64"))]
+			IoDevice::Uhyve(s) => s.read_ready(),
+			IoDevice::Uart(s) => s.read_ready(),
+			#[cfg(feature = "console")]
+			IoDevice::Virtio(s) => s.read_ready(),
+		}
+	}
+}
+
 impl Write for IoDevice {
 	fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
 		match self {
@@ -85,10 +85,6 @@ impl UhyveSerial {
 	pub const fn new() -> Self {
 		Self {}
 	}
-
-	pub fn can_read(&self) -> bool {
-		false
-	}
 }
 
 #[cfg(not(target_arch = "riscv64"))]
@@ -104,6 +100,13 @@ impl Read for UhyveSerial {
 	}
 }
 
+#[cfg(not(target_arch = "riscv64"))]
+impl ReadReady for UhyveSerial {
+	fn read_ready(&mut self) -> Result<bool, Self::Error> {
+		Ok(false)
+	}
+}
+
 #[cfg(not(target_arch = "riscv64"))]
 impl Write for UhyveSerial {
 	fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
@@ -129,10 +132,6 @@ impl Console {
 		}
 	}
 
-	pub fn can_read(&self) -> bool {
-		self.device.can_read()
-	}
-
 	#[cfg(feature = "console")]
 	pub fn replace_device(&mut self, device: IoDevice) {
 		self.device = device;
@@ -149,6 +148,12 @@ impl Read for Console {
 	}
 }
 
+impl ReadReady for Console {
+	fn read_ready(&mut self) -> Result<bool, Self::Error> {
+		self.device.read_ready()
+	}
+}
+
 impl Write for Console {
 	/// Writes a buffer to the console.
 	/// The content is buffered until a newline is encountered or the internal buffer is full.

src/drivers/console/mod.rs

@@ -10,7 +10,7 @@ cfg_if::cfg_if! {
 
 use alloc::vec::Vec;
 
-use embedded_io::{ErrorType, Read, Write};
+use embedded_io::{ErrorType, Read, ReadReady, Write};
 use smallvec::SmallVec;
 use virtio::FeatureBits;
 use virtio::console::Config;
@@ -68,14 +68,6 @@ impl VirtioUART {
 	pub const fn new() -> Self {
 		Self {}
 	}
-
-	pub fn can_read(&self) -> bool {
-		if let Some(drv) = get_console_driver() {
-			drv.lock().has_packet()
-		} else {
-			false
-		}
-	}
 }
 
 impl ErrorType for VirtioUART {
@@ -92,6 +84,16 @@ impl Read for VirtioUART {
 	}
 }
 
+impl ReadReady for VirtioUART {
+	fn read_ready(&mut self) -> Result<bool, Self::Error> {
+		if let Some(drv) = get_console_driver() {
+			Ok(drv.lock().has_packet())
+		} else {
+			Ok(false)
+		}
+	}
+}
+
 impl Write for VirtioUART {
 	fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
 		if let Some(drv) = get_console_driver() {

src/fd/stdio.rs

@@ -3,7 +3,7 @@ use core::future;
 use core::task::Poll;
 
 use async_trait::async_trait;
-use embedded_io::{Read, Write};
+use embedded_io::{Read, ReadReady, Write};
 use uhyve_interface::parameters::WriteParams;
 use uhyve_interface::{GuestVirtAddr, Hypercall};
 
@@ -20,7 +20,7 @@ pub struct GenericStdin;
 #[async_trait]
 impl ObjectInterface for GenericStdin {
 	async fn poll(&self, event: PollEvent) -> io::Result<PollEvent> {
-		let available = if CONSOLE.lock().can_read() {
+		let available = if CONSOLE.lock().read_ready()? {
 			PollEvent::POLLIN | PollEvent::POLLRDNORM | PollEvent::POLLRDBAND
 		} else {
 			PollEvent::empty()