diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..674b962
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,182 @@
+# Top level makefile, repo tool should create a link on this file at the root
+# of the build environement.
+
+.DEFAULT_GOAL := image
+
+# Parallelism is managed by bitbake for this project
+.NOTPARALLEL:
+
+# In this makefile, all targets are phony because dependencies are managed at the bitbake level.
+# We don't need to specify all targets here because no files named like them exist at the top level directory.
+.PHONY : bbcache
+
+# Use a default build tag when none is set by the caller
+NOWDATE := $(shell date +"%Y%m%d%H%M%S")
+BUILD_TAG ?= custom_build_$(USER)@$(HOSTNAME)$(NOWDATE)
+BB_DL_DIR ?= $(CURDIR)/bbcache/downloads
+BB_SSTATE_DIR ?= $(CURDIR)/bbcache/sstate-cache
+
+###############################################################################
+# Main targets
+###############################################################################
+setup: _setup-sdkhost_linux64
+
+cleansstate: _check_setup_was_done
+ /bin/bash -c "source out/current/poky/oe-init-build-env $(CURDIR)/out/current/build ; $(CURDIR)/device-software/utils/invalidate_sstate.sh $(CURDIR)/out/current/build"
+
+devtools_package: _check_setup_was_done
+ /bin/bash -c "source out/current/poky/oe-init-build-env $(CURDIR)/out/current/build ; $(CURDIR)/device-software/utils/create_devtools_package.sh $(CURDIR)/out/current/build"
+
+sdk: _check_setup_was_done
+ /bin/bash -c "source out/current/poky/oe-init-build-env $(CURDIR)/out/current/build ; bitbake edison-image -c populate_sdk"
+
+src-package: pub
+ ./device-software/utils/create_src_package.sh
+ mv edison-src.tgz $(CURDIR)/pub/edison-src-$(BUILD_TAG).tgz
+
+clean:
+ rm -rf out
+
+u-boot linux-externalsrc edison-image meta-toolchain bootimg: _check_setup_was_done
+ /bin/bash -c "source out/current/poky/oe-init-build-env $(CURDIR)/out/current/build ; bitbake -c cleansstate $@ ; bitbake $@"
+ ./device-software/utils/flash/postBuild.sh $(CURDIR)/out/current/build
+
+bootloader: u-boot
+
+image: edison-image
+
+kernel: linux-externalsrc bootimg
+
+toolchain: meta-toolchain
+
+flash: _check_postbuild_was_done
+ ./out/current/build/toFlash/flashall.sh
+
+flash-kernel: _check_postbuild_was_done
+ dd if=./out/current/build/toFlash/edison-image-edison.hddimg | ssh root@192.168.2.15 "dd of=/dev/disk/by-partlabel/boot bs=1M"
+ ssh root@192.168.2.15 "/sbin/reboot -f"
+
+flash-bootloader: _check_postbuild_was_done
+ dfu-util -d 8087:0a99 --alt u-boot0 -D ./out/current/build/toFlash/u-boot-edison.bin -R
+
+cscope:
+ find linux-kernel/ u-boot -regex '.*\.\(c\|cpp\|h\)$\' > cscope.files
+ cscope -R -b -k
+
+list:
+ @sh -c "$(MAKE) -p _no_targets | awk -F':' '/^[a-zA-Z0-9][^\$$#\/\\t=]*:([^=]|$$)/ {split(\$$1,A,/ /);for(i in A)print A[i]}' | sort"
+
+debian_image:
+ $(MAKE) setup SETUP_ARGS="$(SETUP_ARGS) --deb_packages"
+ $(MAKE) image
+ @echo '*******************************'
+ @echo '*******************************'
+ @echo 'Now run the following command to create the debian rootfs:'
+ @echo 'sudo $(CURDIR)/device-software/utils/create-debian-image.sh --build_dir=$(CURDIR)/out/current/build'
+ @echo 'and run a regular make flash'
+ @echo '*******************************'
+
+help:
+ @echo 'Main targets:'
+ @echo ' help - show this help'
+ @echo ' clean - remove the out and pub directory'
+ @echo ' setup - prepare the build env for later build operations'
+ @echo ' cleansstate - clean the sstate for some recipes to work-around some bitbake limitations'
+ @echo ' image - build the flashable edison image, results are in out/current/build/toFlash'
+ @echo ' flash - flash the current build image'
+ @echo ' sdk - build the SDK for the current build'
+ @echo ' toolchain - build the cross compilation toolchain for the current build'
+ @echo ' src-package - create the external source package'
+ @echo ' devtools_package - build some extra dev tools packages, results are in out/current/build/devtools_packages/'
+ @echo
+ @echo 'Continuous Integration targets:'
+ @sh -c "$(MAKE) -p _no_targets | awk -F':' '/^ci_[a-zA-Z0-9][^\$$#\/\\t=]*:([^=]|$$)/ {split(\$$1,A,/ /);for(i in A)print \" \"A[i]}' | sort"
+ @echo
+ @echo 'Environment variables:'
+ @echo ' BUILD_TAG - set the build name used for e.g. artifact file naming'
+ @echo ' BB_DL_DIR - defines the directory (absolute path) where bitbake places downloaded files (defaults to bbcache/downloads)'
+ @echo ' BB_SSTATE_DIR - defines the directory (absolute path) where bitbake places shared-state files (defaults to bbcache/sstate-cache)'
+ @echo ' SETUP_ARGS - control advanced behaviour of the setup script (run ./device-software/setup.sh --help for more details)'
+
+###############################################################################
+# Private targets
+###############################################################################
+
+_no_targets:
+
+_check_setup_was_done:
+ @if [ ! -f $(CURDIR)/out/current/build/conf/local.conf ]; then echo Please run \"make setup\" first ; exit 1 ; fi
+
+_check_postbuild_was_done:
+ @if [ ! -f $(CURDIR)/out/current/build/toFlash/flashall.sh ]; then echo Please run \"make image/bootloader/kernel\" first ; exit 1 ; fi
+
+_setup-sdkhost_%: pub bbcache
+ @echo Setup buildenv for SDK host $*
+ @mkdir -p out/$*
+ ./device-software/setup.sh $(SETUP_ARGS) --dl_dir=$(BB_DL_DIR) --sstate_dir=$(BB_SSTATE_DIR) --build_dir=$(CURDIR)/out/$* --build_name=$(BUILD_TAG) --sdk_host=$*
+ @rm -f out/current
+ @ln -s $(CURDIR)/out/$* $(CURDIR)/out/current
+ @if [ $* = macosx ]; then /bin/bash -c "source out/current/poky/oe-init-build-env $(CURDIR)/out/current/build ; bitbake odcctools2-crosssdk -c cleansstate" ; echo "Please make sure that OSX-sdk.zip is available in your bitbake download directory" ; fi
+
+pub:
+ @mkdir -p $@
+
+bbcache:
+ @mkdir -p bbcache
+ @mkdir -p $(BB_DL_DIR)
+ @mkdir -p $(BB_SSTATE_DIR)
+
+_image_archive:
+ cd $(CURDIR)/out/current/build/toFlash ; zip -r $(CURDIR)/pub/edison-image-$(BUILD_TAG).zip `ls`
+ cd $(CURDIR)/out/current/build/symbols ; zip -r $(CURDIR)/pub/symbols-$(BUILD_TAG).zip `ls`
+
+_devtools_package_archive:
+ cd $(CURDIR)/out/current/build/devtools_packages ; zip -r $(CURDIR)/pub/edison-devtools-packages-$(BUILD_TAG).zip `ls`
+
+_sdk_archive_%:
+ cd $(CURDIR)/out/$*/build/tmp/deploy/sdk ; zip -r $(CURDIR)/pub/edison-sdk-$*-$(BUILD_TAG).zip `ls *-edison-image-*`
+
+_toolchain_archive_%:
+ cd $(CURDIR)/out/$*/build/tmp/deploy/sdk ; zip -r $(CURDIR)/pub/edison-meta-toolchain-$*-$(BUILD_TAG).zip `ls *-meta-toolchain-*`
+
+
+###############################################################################
+# Continuous Integration targets: one per checkbox available in jenkins
+# Each target places the the end-user artifact in the pub/ directory
+###############################################################################
+
+ci_image: setup cleansstate devtools_package _devtools_package_archive image _image_archive
+
+_ci_sdk_%:
+ $(MAKE) _setup-sdkhost_$* cleansstate sdk _sdk_archive_$*
+
+_ci_toolchain_%:
+ $(MAKE) _setup-sdkhost_$* cleansstate toolchain _toolchain_archive_$*
+
+ci_sdk_win32: _ci_sdk_win32
+ci_sdk_win64: _ci_sdk_win64
+ci_sdk_linux32: _ci_sdk_linux32
+ci_sdk_linux64: _ci_sdk_linux64
+ci_sdk_macosx: _ci_sdk_macosx
+ci_toolchain_win32: _ci_toolchain_win32
+ci_toolchain_win64: _ci_toolchain_win64
+ci_toolchain_linux32: _ci_toolchain_linux32
+ci_toolchain_linux64: _ci_toolchain_linux64
+ci_toolchain_macosx: _ci_toolchain_macosx
+
+ci_image-from-src-package-and-GPL-LGPL-sources_archive: setup src-package
+ cp $(CURDIR)/pub/edison-src-$(BUILD_TAG).tgz $(CURDIR)/out/current
+ cd $(CURDIR)/out/current ; tar -xvf edison-src-$(BUILD_TAG).tgz
+ cd $(CURDIR)/out/current/edison-src ; /bin/bash -c "SETUP_ARGS=\"$(SETUP_ARGS) --create_src_archive\" make setup cleansstate image _image_archive"
+ cd $(CURDIR)/out/current/edison-src/out/current/build/toFlash ; zip -r $(CURDIR)/pub/edison-image-from-src-package-$(BUILD_TAG).zip `ls`
+ cd $(CURDIR)/out/current/edison-src/out/current/build/tmp/deploy/sources ; zip -r $(CURDIR)/pub/edison-GPL_LGPL-sources-$(BUILD_TAG).zip `ls`
+
+ci_full:
+ $(MAKE) ci_image BUILD_TAG=$(BUILD_TAG)
+ $(MAKE) ci_image-from-src-package-and-GPL-LGPL-sources_archive BUILD_TAG=$(BUILD_TAG)
+ $(MAKE) ci_sdk_win32 ci_toolchain_win32 BUILD_TAG=$(BUILD_TAG)
+ $(MAKE) ci_sdk_win64 ci_toolchain_win64 BUILD_TAG=$(BUILD_TAG)
+ $(MAKE) ci_sdk_linux32 ci_toolchain_linux32 BUILD_TAG=$(BUILD_TAG)
+ $(MAKE) ci_sdk_linux64 ci_toolchain_linux64 BUILD_TAG=$(BUILD_TAG)
+ $(MAKE) ci_sdk_macosx ci_toolchain_macosx BUILD_TAG=$(BUILD_TAG)
+
diff --git a/arduino/clloader/clloader.c b/arduino/clloader/clloader.c
index f2a6952..73a0296 100644
--- a/arduino/clloader/clloader.c
+++ b/arduino/clloader/clloader.c
@@ -2729,12 +2729,15 @@ int clantonLoaderFSM(int argc, char * argv[])
fprintf(stderr, "host: %s\n", rbuf_from_host);
errors = 0;
/* TODO: bring out state change of BAUD/LINE and replace magic string */
- if (strncmp(CL_LOADER_CMD_HOST_START_DOWNLOAD_CMD,
- rbuf_from_host,
- (size_t)strlen(CL_LOADER_CMD_HOST_START_DOWNLOAD_CMD)) == 0) {
+ if (strncmp(downloadCMD, rbuf_from_host,
+ ((size_t)strlen(rbuf_from_host)-1)) == 0) {
// We got a special command to start download
clantonLeavePassThroughState = TRUE;
-
+ } else if (strncmp(CL_LOADER_CMD_HOST_START_DOWNLOAD_CMD,
+ rbuf_from_host,
+ ((size_t)strlen(rbuf_from_host)-1)) == 0) {
+ // Old command string. Allow to download anyway.
+ clantonLeavePassThroughState = TRUE;
} else {
write(mystate.tty_slave,rbuf_from_host,ret); //todo check write status
}
diff --git a/arduino/clloader/clloader.h b/arduino/clloader/clloader.h
index c9dd595..749672f 100644
--- a/arduino/clloader/clloader.h
+++ b/arduino/clloader/clloader.h
@@ -22,6 +22,7 @@
#define MAX_ARGS 0x20
#define CL_LOADER_CMD_HOST_START_DOWNLOAD_CMD "~sketch download"
+#define downloadCMD "~sketch downloadEdison"
#define CL_LOADER_CMD_STARTCHAR '#'
#define CL_LOADER_CMD_START_SKETCH_APP "#Start Sketch:" /* filename args and exec i/o wrapper */
diff --git a/broadcom_cws/bluetooth/firmware/BCM43341B0_002.001.014.0123.0168.hcd b/broadcom_cws/bluetooth/firmware/BCM43341B0_002.001.014.0123.0168.hcd
new file mode 100644
index 0000000..d20e2e2
Binary files /dev/null and b/broadcom_cws/bluetooth/firmware/BCM43341B0_002.001.014.0123.0168.hcd differ
diff --git a/broadcom_cws/wlan/driver_bcm43x/wl_cfg80211.c b/broadcom_cws/wlan/driver_bcm43x/wl_cfg80211.c
index f77d761..a665633 100644
--- a/broadcom_cws/wlan/driver_bcm43x/wl_cfg80211.c
+++ b/broadcom_cws/wlan/driver_bcm43x/wl_cfg80211.c
@@ -287,7 +287,7 @@ common_iface_combinations[] = {
#endif
#ifndef IBSS_COALESCE_ALLOWED
-#define IBSS_COALESCE_ALLOWED 0
+#define IBSS_COALESCE_ALLOWED 1
#endif
#ifndef IBSS_INITIAL_SCAN_ALLOWED
@@ -2606,6 +2606,7 @@ channel_to_chanspec(struct wiphy *wiphy, struct net_device *dev, u32 channel, u3
}
for (i = 0; i < dtoh32(list->count); i++) {
c = dtoh32(list->element[i]);
+ c = wl_chspec_driver_to_host(c);
if (channel <= CH_MAX_2G_CHANNEL) {
if (!CHSPEC_IS20(c))
continue;
@@ -2657,6 +2658,8 @@ channel_to_chanspec(struct wiphy *wiphy, struct net_device *dev, u32 channel, u3
if (buf)
kfree(buf);
#undef LOCAL_BUF_SIZE
+ if (ret_c)
+ ret_c = wl_chspec_host_to_driver(ret_c);
WL_INFO(("return chanspec %x %d\n", ret_c, bw));
return ret_c;
}
@@ -2738,7 +2741,10 @@ wl_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
s32 err = 0;
size_t join_params_size;
chanspec_t chanspec = 0;
- u32 param[2] = {0, 0};
+ struct {
+ u32 band;
+ u32 bw_cap;
+ } param = {0, 0};
u32 bw_cap = 0;
WL_TRACE(("In\n"));
@@ -2808,16 +2814,35 @@ wl_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
cfg->ibss_starter = true;
}
if (chan) {
- if (chan->band == IEEE80211_BAND_5GHZ)
- param[0] = WLC_BAND_5G;
- else if (chan->band == IEEE80211_BAND_2GHZ)
- param[0] = WLC_BAND_2G;
- err = wldev_iovar_getint(dev, "bw_cap", param);
- if (unlikely(err)) {
- WL_ERR(("Get bw_cap Failed (%d)\n", err));
- return err;
+ if (chan->band == IEEE80211_BAND_5GHZ) {
+ param.band = WLC_BAND_5G;
+ err = wldev_iovar_getbuf(dev, "bw_cap", ¶m, sizeof(param),
+ cfg->ioctl_buf, WLC_IOCTL_SMLEN, &cfg->ioctl_buf_sync);
+ if (err) {
+ if (err != BCME_UNSUPPORTED) {
+ WL_ERR(("bw_cap failed, %d\n", err));
+ return err;
+ } else {
+ err = wldev_iovar_getint(dev, "mimo_bw_cap", &bw_cap);
+ if (err) {
+ WL_ERR(("error get mimo_bw_cap (%d)\n", err));
+ }
+ if (bw_cap != WLC_N_BW_20ALL)
+ bw_cap = WL_CHANSPEC_BW_40;
+ }
+ }
+ else {
+ if (WL_BW_CAP_80MHZ(cfg->ioctl_buf[0]))
+ bw_cap = WL_CHANSPEC_BW_80;
+ else if (WL_BW_CAP_40MHZ(cfg->ioctl_buf[0]))
+ bw_cap = WL_CHANSPEC_BW_40;
+ else
+ bw_cap = WL_CHANSPEC_BW_20;
+ }
}
- bw_cap = param[0];
+ else if (chan->band == IEEE80211_BAND_2GHZ)
+ bw_cap = WL_CHANSPEC_BW_20;
+
chanspec = channel_to_chanspec(wiphy, dev, cfg->channel, bw_cap);
}
/*
@@ -2851,9 +2876,11 @@ wl_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
}
}
- join_params.params.chanspec_list[0] = chanspec;
- join_params.params.chanspec_num = 1;
- wldev_iovar_setint(dev, "chanspec", chanspec);
+ if (chan) {
+ join_params.params.chanspec_list[0] = chanspec;
+ join_params.params.chanspec_num = 1;
+ wldev_iovar_setint(dev, "chanspec", chanspec);
+ }
join_params_size = sizeof(join_params);
/* Disable Authentication, IBSS will add key if it required */
diff --git a/device-software/meta-edison-devtools/recipes-connectivity/bcm43340-tools/dhdutil.bb b/device-software/meta-edison-devtools/recipes-connectivity/bcm43340-tools/dhdutil.bb
new file mode 100644
index 0000000..3f08096
--- /dev/null
+++ b/device-software/meta-edison-devtools/recipes-connectivity/bcm43340-tools/dhdutil.bb
@@ -0,0 +1,15 @@
+SUMMARY = "dhdutil utility"
+DESCRIPTION = "dhdutil utility for BCM chipset"
+SECTION = "test-tools"
+LICENSE = "CLOSED"
+
+PV = "r1.141"
+PR = "r47"
+
+S = "${EDISONREPO_TOP_DIR}/broadcom_tools/wlan/dhdutil"
+
+do_install() {
+ install -v -d ${D}/usr/sbin/
+ install -m 0755 ${B}/dhdutil ${D}/usr/sbin
+}
+
diff --git a/device-software/meta-edison-devtools/recipes-connectivity/bcm43340-tools/wlx.bb b/device-software/meta-edison-devtools/recipes-connectivity/bcm43340-tools/wlx.bb
new file mode 100644
index 0000000..3d88e6e
--- /dev/null
+++ b/device-software/meta-edison-devtools/recipes-connectivity/bcm43340-tools/wlx.bb
@@ -0,0 +1,19 @@
+SUMMARY = "wlx utility"
+DESCRIPTION = "wlx utility for BCM chipset"
+SECTION = "test-tools"
+LICENSE = "CLOSED"
+
+PV = "r6.10.190"
+PR = "r40"
+
+S = "${EDISONREPO_TOP_DIR}/broadcom_tools/wlan/wlx"
+
+do_compile () {
+ oe_runmake -C wl/exe
+}
+
+do_install() {
+ install -v -d ${D}/usr/sbin/
+ install -m 0755 ${B}/wl/exe/wlx ${D}/usr/sbin
+}
+
diff --git a/device-software/meta-edison-devtools/recipes-connectivity/wfa-tool/wfa-tool.bb b/device-software/meta-edison-devtools/recipes-connectivity/wfa-tool/wfa-tool.bb
index 24a78e1..1d21cfe 100644
--- a/device-software/meta-edison-devtools/recipes-connectivity/wfa-tool/wfa-tool.bb
+++ b/device-software/meta-edison-devtools/recipes-connectivity/wfa-tool/wfa-tool.bb
@@ -20,8 +20,11 @@ do_install() {
install -m 0755 ${S}/scripts/wfa_stop_ping ${D}/usr/sbin
install -m 0755 ${S}/scripts/wfa_start_dhcp_client ${D}/usr/sbin
install -m 0755 ${S}/scripts/wfa_stop_dhcp_client ${D}/usr/sbin
+ install -m 0755 ${S}/scripts/wfa_start_dhcp_server ${D}/usr/sbin
+ install -m 0755 ${S}/scripts/wfa_stop_dhcp_server ${D}/usr/sbin
install -v -d ${D}${sysconfdir}/sigma
+ install -m 644 ${S}/scripts/udhcpd.conf ${D}${sysconfdir}/sigma
install -m 644 ${S}/certificates/cas.pem ${D}${sysconfdir}/sigma
install -m 644 ${S}/certificates/root.pem ${D}${sysconfdir}/sigma
install -m 644 ${S}/certificates/wifiuser.pem ${D}${sysconfdir}/sigma
diff --git a/device-software/meta-edison-distro/conf/distro/poky-edison.conf b/device-software/meta-edison-distro/conf/distro/poky-edison.conf
index 3a9c247..a0e7466 100644
--- a/device-software/meta-edison-distro/conf/distro/poky-edison.conf
+++ b/device-software/meta-edison-distro/conf/distro/poky-edison.conf
@@ -6,8 +6,8 @@ PREFERRED_VERSION_linux-yocto = "3.10%"
PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot"
PREFERRED_VERSION_u-boot ?= "2014.04-1"
PREFERRED_VERSION_u-boot-fw-utils ?= "2014.04-1"
-PREFERRED_VERSION_connman ?= "1.24"
-PREFERRED_VERSION_openssl ?= "1.0.1g"
+PREFERRED_VERSION_connman ?= "1.27"
+PREFERRED_VERSION_openssl ?= "1.0.1j"
PREFERRED_VERSION_systemd ?= "213+gitAUTOINC+c9679c652b"
DISTRO_FEATURES = "systemd alsa argp bluetooth ext2 largefile usbgadget usbhost wifi xattr nfs zeroconf pci ${DISTRO_FEATURES_LIBC}"
diff --git a/device-software/meta-edison-distro/recipes-connectivity/bluetooth-rfkill-event/files/bcm43341.conf b/device-software/meta-edison-distro/recipes-connectivity/bluetooth-rfkill-event/files/bcm43341.conf
index dc4ea4f..d43b051 100644
--- a/device-software/meta-edison-distro/recipes-connectivity/bluetooth-rfkill-event/files/bcm43341.conf
+++ b/device-software/meta-edison-distro/recipes-connectivity/bluetooth-rfkill-event/files/bcm43341.conf
@@ -28,5 +28,5 @@ fw_patch = /etc/firmware/bcm43341.hcd
uart_dev = /dev/ttyMFD0
# SCO settings
-# N/A now
-# scopcm =
+# configure sco routing to Transport (HCI);
+scopcm = 1,0,0,0,0,0,0,0,0,0
diff --git a/device-software/meta-edison-distro/recipes-connectivity/bluetooth-rfkill-event/files/bluetooth_rfkill_event.c b/device-software/meta-edison-distro/recipes-connectivity/bluetooth-rfkill-event/files/bluetooth_rfkill_event.c
index 368328c..9d69805 100644
--- a/device-software/meta-edison-distro/recipes-connectivity/bluetooth-rfkill-event/files/bluetooth_rfkill_event.c
+++ b/device-software/meta-edison-distro/recipes-connectivity/bluetooth-rfkill-event/files/bluetooth_rfkill_event.c
@@ -298,24 +298,25 @@ void load_bd_add(void)
fp = fopen(BD_ADD_FACTORY_FILE, "r");
- /* if BD add file has not been provisioned use default one */
+ /* if BD add file has not been provisioned do not send VSC to set BD address: the one configured in OTP will be used or default FW one */
if (fp == NULL)
{
- memcpy(factory_bd_add, default_bd_addr, sizeof(factory_bd_add));
- main_opts.bd_add = factory_bd_add;
- main_opts.set_bd = TRUE;
+ main_opts.set_bd = FALSE;
return;
}
ret = fscanf(fp, "%17c", factory_bd_add);
- /* if factory BD address is not well formatted or not present use default one*/
+ /* if factory BD address is not well formatted or not present do not send VSC to set BD address: the one configured in OTP will be used or default FW one */
if (!(ret == 1 && check_bd_format(factory_bd_add)))
{
- memcpy(factory_bd_add, default_bd_addr, sizeof(factory_bd_add));
+ main_opts.set_bd = FALSE;
+ }
+ else
+ {
+ main_opts.bd_add = factory_bd_add;
+ main_opts.set_bd = TRUE;
}
- main_opts.bd_add = factory_bd_add;
- main_opts.set_bd = TRUE;
fclose(fp);
diff --git a/device-software/meta-edison-distro/recipes-connectivity/bluez5/bluez5_5.15.bbappend b/device-software/meta-edison-distro/recipes-connectivity/bluez5/bluez5_5.15.bbappend
index a4672a5..3aad093 100644
--- a/device-software/meta-edison-distro/recipes-connectivity/bluez5/bluez5_5.15.bbappend
+++ b/device-software/meta-edison-distro/recipes-connectivity/bluez5/bluez5_5.15.bbappend
@@ -1,19 +1,22 @@
-# overwrite to 5.18 version and its checksum
+# overwrite to 5.24 version and its checksum
-PV = "5.18"
+PV = "5.24"
-SRC_URI[md5sum] = "9c71404f86287cd9441e86783be3aae1"
-SRC_URI[sha256sum] = "8c8bb13db83d0de6c85def2da8dfa0a758aff595405fb57a00719ed94d558340"
+SRC_URI[md5sum] = "37b785185fb98269b45e51b254bd8d3d"
+SRC_URI[sha256sum] = "e870c5fba0bf3496856fc720e2d217856fcf40b59829f8cc0c05902ebb9fb837"
# to get bluetooth.conf
FILESEXTRAPATHS_prepend := "${THISDIR}/files/"
-# few overwrite for 5.18 version
+# few overwrite for 5.24 version
SRC_URI = "\
${KERNELORG_MIRROR}/linux/bluetooth/bluez-${PV}.tar.xz \
file://bluetooth.conf \
+ file://obex_set_dbus_session_service.patch \
"
+RDEPENDS_${PN} += "eglibc-gconv-utf-16"
+
PACKAGECONFIG[alsa] = ""
EXTRA_OECONF = "\
@@ -24,6 +27,7 @@ EXTRA_OECONF = "\
--enable-datafiles \
${@base_contains('DISTRO_FEATURES', 'systemd', '--with-systemdsystemunitdir=${systemd_unitdir}/system/', '--disable-systemd', d)} \
--enable-library \
+ --enable-experimental \
"
do_install_append() {
@@ -43,6 +47,16 @@ do_install_append() {
if [ -f ${S}/src/main.conf ]; then
install -m 0644 ${S}/src/main.conf ${D}/${sysconfdir}/bluetooth/
fi
+ if [ -f ${S}/tools/obexctl ]; then
+ install -m 0755 ${S}/tools/obexctl ${D}${bindir}
+ fi
+
+ if ${@base_contains('DISTRO_FEATURES','systemd','true','false',d)}; then
+ # Copy file service
+ install -d ${D}/${systemd_unitdir}/system
+ install -m 644 ${S}/obexd/src/obex.service ${D}/${systemd_unitdir}/system/
+ fi
+
# at_console doesn't really work with the current state of OE, so punch some more holes so people can actually use BT
install -m 0644 ${WORKDIR}/bluetooth.conf ${D}/${sysconfdir}/dbus-1/system.d/
}
diff --git a/device-software/meta-edison-distro/recipes-connectivity/bluez5/files/bluetooth.conf b/device-software/meta-edison-distro/recipes-connectivity/bluez5/files/bluetooth.conf
index e21e72e..162c803 100644
--- a/device-software/meta-edison-distro/recipes-connectivity/bluez5/files/bluetooth.conf
+++ b/device-software/meta-edison-distro/recipes-connectivity/bluez5/files/bluetooth.conf
@@ -9,8 +9,16 @@
+
+
+
+
+
+
+
+
diff --git a/device-software/meta-edison-distro/recipes-connectivity/bluez5/files/obex_set_dbus_session_service.patch b/device-software/meta-edison-distro/recipes-connectivity/bluez5/files/obex_set_dbus_session_service.patch
new file mode 100644
index 0000000..4000aaf
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/bluez5/files/obex_set_dbus_session_service.patch
@@ -0,0 +1,10 @@
+--- a/obexd/src/obex.service.in 2014-10-30 14:40:00.832479049 +0100
++++ b/obexd/src/obex.service.in 2014-10-30 14:40:41.032477622 +0100
+@@ -4,6 +4,7 @@
+ [Service]
+ Type=dbus
+ BusName=org.bluez.obex
++Environment="DBUS_SESSION_BUS_ADDRESS=unix:path=/var/run/dbus/system_bus_socket"
+ ExecStart=@libexecdir@/obexd
+
+ [Install]
diff --git a/device-software/meta-edison-distro/recipes-connectivity/connman/connman/disable_p2p.patch b/device-software/meta-edison-distro/recipes-connectivity/connman/connman/disable_p2p.patch
new file mode 100644
index 0000000..6cce2e3
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/connman/connman/disable_p2p.patch
@@ -0,0 +1,15 @@
+--- a/gsupplicant/supplicant.c
++++ b/gsupplicant/supplicant.c
+@@ -1963,8 +1963,11 @@
+ if (g_strcmp0(key, "Capabilities") == 0) {
+ supplicant_dbus_property_foreach(iter, interface_capability,
+ interface);
++#if 0
++ /* Disable temporarely p2p */
+ if (interface->mode_capa & G_SUPPLICANT_CAPABILITY_MODE_P2P)
+ interface->p2p_support = true;
++#endif
+ } else if (g_strcmp0(key, "State") == 0) {
+ const char *str = NULL;
+
+
diff --git a/device-software/meta-edison-distro/recipes-connectivity/connman/connman_1.27.bb b/device-software/meta-edison-distro/recipes-connectivity/connman/connman_1.27.bb
new file mode 100644
index 0000000..70993ac
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/connman/connman_1.27.bb
@@ -0,0 +1,11 @@
+require connman.inc
+
+SRC_URI = "${KERNELORG_MIRROR}/linux/network/${BPN}/${BP}.tar.xz \
+ file://0001-plugin.h-Change-visibility-to-default-for-debug-symb.patch \
+ file://add_xuser_dbus_permission.patch \
+ file://disable_p2p.patch \
+ file://connman \
+ "
+SRC_URI[md5sum] = "4f4b3be54da000c65b153c1b9afcadf2"
+SRC_URI[sha256sum] = "13997824c076af150c68d6d79e48277216e8192278a5c6615cfd4905d65600f5"
+RRECOMMENDS_${PN} = "connman-conf"
diff --git a/device-software/meta-edison-distro/recipes-connectivity/connman/connman_1.27.bbappend b/device-software/meta-edison-distro/recipes-connectivity/connman/connman_1.27.bbappend
new file mode 100644
index 0000000..80e7b38
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/connman/connman_1.27.bbappend
@@ -0,0 +1,35 @@
+
+
+LIC_FILES_CHKSUM = "file://COPYING;md5=12f884d2ae1ff87c09e5b7ccc2c4ca7e \
+ file://src/main.c;beginline=1;endline=20;md5=486a279a6ab0c8d152bcda3a5b5edc36"
+
+PACKAGECONFIG ??= "wispr \
+ ${@base_contains('DISTRO_FEATURES', 'wifi','wifi', '', d)} \
+ ${@base_contains('DISTRO_FEATURES', 'bluetooth','bluetooth', '', d)} \
+"
+
+PACKAGECONFIG[bluetooth] = "--enable-bluetooth, --disable-bluetooth, bluez5"
+PACKAGECONFIG[3g] = ""
+
+SYSTEMD_AUTO_ENABLE = "disable"
+
+do_configure_append () {
+ # Do not usb0 as it is used for SSH connection
+ sed -i "s/ExecStart=.*/& --nodevice=usb0/" ${S}/src/connman.service
+}
+
+
+# These used to be plugins, but now they are core
+RPROVIDES_${PN} = "\
+ connman-plugin-loopback \
+ connman-plugin-ethernet \
+ ${@base_contains('PACKAGECONFIG', 'bluetooth','connman-plugin-bluetooth', '', d)} \
+ ${@base_contains('PACKAGECONFIG', 'wifi','connman-plugin-wifi', '', d)} \
+ "
+
+RDEPENDS_${PN} = "\
+ dbus \
+ ${@base_contains('PACKAGECONFIG', 'bluetooth', 'bluez5', '', d)} \
+ ${@base_contains('PACKAGECONFIG', 'wifi','wpa-supplicant', '', d)} \
+ "
+
diff --git a/device-software/meta-edison-distro/recipes-connectivity/hostapd/files/hostapd.conf-sane b/device-software/meta-edison-distro/recipes-connectivity/hostapd/files/hostapd.conf-sane
index da81096..3e7d794 100644
--- a/device-software/meta-edison-distro/recipes-connectivity/hostapd/files/hostapd.conf-sane
+++ b/device-software/meta-edison-distro/recipes-connectivity/hostapd/files/hostapd.conf-sane
@@ -424,7 +424,7 @@ wmm_ac_vo_acm=0
# 0 = disabled (default)
# 1 = enabled
# Note: You will also need to enable WMM for full HT functionality.
-#ieee80211n=1
+ieee80211n=1
# ht_capab: HT capabilities (list of flags)
# LDPC coding capability: [LDPC] = supported
diff --git a/device-software/meta-edison-distro/recipes-connectivity/hostapd/files/udhcpd-for-hostapd.conf b/device-software/meta-edison-distro/recipes-connectivity/hostapd/files/udhcpd-for-hostapd.conf
index e25d704..1015e39 100644
--- a/device-software/meta-edison-distro/recipes-connectivity/hostapd/files/udhcpd-for-hostapd.conf
+++ b/device-software/meta-edison-distro/recipes-connectivity/hostapd/files/udhcpd-for-hostapd.conf
@@ -83,7 +83,7 @@ pidfile /var/run/udhcpd-wlan0.pid #default: /var/run/udhcpd.pid
# lines. The only option with a default is 'lease'.
# Currently supported options, for more info, see options.c
-#opt subnet
+opt subnet 255.255.255.0
#opt timezone
#opt router
#opt timesvr
diff --git a/device-software/meta-edison-distro/recipes-connectivity/openssh/openssh/sshdgenkeys.service b/device-software/meta-edison-distro/recipes-connectivity/openssh/openssh/sshdgenkeys.service
index 25d27ae..e8133e4 100644
--- a/device-software/meta-edison-distro/recipes-connectivity/openssh/openssh/sshdgenkeys.service
+++ b/device-software/meta-edison-distro/recipes-connectivity/openssh/openssh/sshdgenkeys.service
@@ -2,6 +2,6 @@
Description=OpenSSH Key Generation
[Service]
-ExecStart=@BASE_BINDIR@/sh -c "if ! sshd -t > /dev/null ; then rm /etc/ssh/*_key* ; ssh-keygen -A ; sync ; fi"
+ExecStart=@BASE_BINDIR@/sh -c "if ! sshd -t &> /dev/null ; then rm /etc/ssh/*_key* ; ssh-keygen -A ; sync ; fi"
Type=oneshot
RemainAfterExit=yes
diff --git a/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-0195.patch b/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-0195.patch
new file mode 100644
index 0000000..0c43919
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-0195.patch
@@ -0,0 +1,40 @@
+commit 208d54db20d58c9a5e45e856a0650caadd7d9612
+Author: Dr. Stephen Henson
+Date: Tue May 13 18:48:31 2014 +0100
+
+ Fix for CVE-2014-0195
+
+ A buffer overrun attack can be triggered by sending invalid DTLS fragments
+ to an OpenSSL DTLS client or server. This is potentially exploitable to
+ run arbitrary code on a vulnerable client or server.
+
+ Fixed by adding consistency check for DTLS fragments.
+
+ Thanks to Jüri Aedla for reporting this issue.
+
+Patch borrowed from Fedora
+Upstream-Status: Backport
+Signed-off-by: Paul Eggleton
+
+diff --git a/ssl/d1_both.c b/ssl/d1_both.c
+index 2e8cf68..07f67f8 100644
+--- a/ssl/d1_both.c
++++ b/ssl/d1_both.c
+@@ -627,7 +627,16 @@ dtls1_reassemble_fragment(SSL *s, struct hm_header_st* msg_hdr, int *ok)
+ frag->msg_header.frag_off = 0;
+ }
+ else
++ {
+ frag = (hm_fragment*) item->data;
++ if (frag->msg_header.msg_len != msg_hdr->msg_len)
++ {
++ item = NULL;
++ frag = NULL;
++ goto err;
++ }
++ }
++
+
+ /* If message is already reassembled, this must be a
+ * retransmit and can be dropped.
+
diff --git a/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-0198.patch b/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-0198.patch
new file mode 100644
index 0000000..12dcfb7
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-0198.patch
@@ -0,0 +1,38 @@
+From: Matt Caswell
+Date: Sun, 11 May 2014 23:38:37 +0000 (+0100)
+Subject: Fixed NULL pointer dereference. See PR#3321
+X-Git-Url: https://git.openssl.org/gitweb/?p=openssl.git;a=commitdiff_plain;h=b107586
+
+Fixed NULL pointer dereference. See PR#3321
+
+Patch borrowed from Fedora
+Upstream-Status: Backport
+Signed-off-by: Paul Eggleton
+
+---
+
+diff --git a/ssl/s3_pkt.c b/ssl/s3_pkt.c
+index 40eb0dd..d961d12 100644
+--- a/ssl/s3_pkt.c
++++ b/ssl/s3_pkt.c
+@@ -657,9 +657,6 @@ static int do_ssl3_write(SSL *s, int type, const unsigned char *buf,
+ SSL3_BUFFER *wb=&(s->s3->wbuf);
+ SSL_SESSION *sess;
+
+- if (wb->buf == NULL)
+- if (!ssl3_setup_write_buffer(s))
+- return -1;
+
+ /* first check if there is a SSL3_BUFFER still being written
+ * out. This will happen with non blocking IO */
+@@ -675,6 +672,10 @@ static int do_ssl3_write(SSL *s, int type, const unsigned char *buf,
+ /* if it went, fall through and send more stuff */
+ }
+
++ if (wb->buf == NULL)
++ if (!ssl3_setup_write_buffer(s))
++ return -1;
++
+ if (len == 0 && !create_empty_fragment)
+ return 0;
+
diff --git a/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-0221.patch b/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-0221.patch
new file mode 100644
index 0000000..bf730a8
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-0221.patch
@@ -0,0 +1,38 @@
+commit d30e582446b027868cdabd0994681643682045a4
+Author: Dr. Stephen Henson
+Date: Fri May 16 13:00:45 2014 +0100
+
+ Fix CVE-2014-0221
+
+ Unnecessary recursion when receiving a DTLS hello request can be used to
+ crash a DTLS client. Fixed by handling DTLS hello request without recursion.
+
+ Thanks to Imre Rad (Search-Lab Ltd.) for discovering this issue.
+
+Patch borrowed from Fedora
+Upstream-Status: Backport
+Signed-off-by: Paul Eggleton
+
+diff --git a/ssl/d1_both.c b/ssl/d1_both.c
+index 07f67f8..4c2fd03 100644
+--- a/ssl/d1_both.c
++++ b/ssl/d1_both.c
+@@ -793,6 +793,7 @@ dtls1_get_message_fragment(SSL *s, int st1, int stn, long max, int *ok)
+ int i,al;
+ struct hm_header_st msg_hdr;
+
++ redo:
+ /* see if we have the required fragment already */
+ if ((frag_len = dtls1_retrieve_buffered_fragment(s,max,ok)) || *ok)
+ {
+@@ -851,8 +852,7 @@ dtls1_get_message_fragment(SSL *s, int st1, int stn, long max, int *ok)
+ s->msg_callback_arg);
+
+ s->init_num = 0;
+- return dtls1_get_message_fragment(s, st1, stn,
+- max, ok);
++ goto redo;
+ }
+ else /* Incorrectly formated Hello request */
+ {
+
diff --git a/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-0224.patch b/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-0224.patch
new file mode 100644
index 0000000..0ed1d12
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-0224.patch
@@ -0,0 +1,103 @@
+Fix for CVE-2014-0224
+
+Only accept change cipher spec when it is expected instead of at any
+time. This prevents premature setting of session keys before the master
+secret is determined which an attacker could use as a MITM attack.
+
+Thanks to KIKUCHI Masashi (Lepidum Co. Ltd.) for reporting this issue
+and providing the initial fix this patch is based on.
+
+
+Patch borrowed from Fedora
+Upstream-Status: Backport
+Signed-off-by: Paul Eggleton
+
+
+diff -up openssl-1.0.1e/ssl/ssl3.h.keying-mitm openssl-1.0.1e/ssl/ssl3.h
+--- openssl-1.0.1e/ssl/ssl3.h.keying-mitm 2014-06-02 19:48:04.518100562 +0200
++++ openssl-1.0.1e/ssl/ssl3.h 2014-06-02 19:48:04.642103429 +0200
+@@ -388,6 +388,7 @@ typedef struct ssl3_buffer_st
+ #define TLS1_FLAGS_TLS_PADDING_BUG 0x0008
+ #define TLS1_FLAGS_SKIP_CERT_VERIFY 0x0010
+ #define TLS1_FLAGS_KEEP_HANDSHAKE 0x0020
++#define SSL3_FLAGS_CCS_OK 0x0080
+
+ /* SSL3_FLAGS_SGC_RESTART_DONE is set when we
+ * restart a handshake because of MS SGC and so prevents us
+diff -up openssl-1.0.1e/ssl/s3_clnt.c.keying-mitm openssl-1.0.1e/ssl/s3_clnt.c
+--- openssl-1.0.1e/ssl/s3_clnt.c.keying-mitm 2013-02-11 16:26:04.000000000 +0100
++++ openssl-1.0.1e/ssl/s3_clnt.c 2014-06-02 19:49:57.042701985 +0200
+@@ -559,6 +559,7 @@ int ssl3_connect(SSL *s)
+ case SSL3_ST_CR_FINISHED_A:
+ case SSL3_ST_CR_FINISHED_B:
+
++ s->s3->flags |= SSL3_FLAGS_CCS_OK;
+ ret=ssl3_get_finished(s,SSL3_ST_CR_FINISHED_A,
+ SSL3_ST_CR_FINISHED_B);
+ if (ret <= 0) goto end;
+@@ -916,6 +917,7 @@ int ssl3_get_server_hello(SSL *s)
+ SSLerr(SSL_F_SSL3_GET_SERVER_HELLO,SSL_R_ATTEMPT_TO_REUSE_SESSION_IN_DIFFERENT_CONTEXT);
+ goto f_err;
+ }
++ s->s3->flags |= SSL3_FLAGS_CCS_OK;
+ s->hit=1;
+ }
+ else /* a miss or crap from the other end */
+diff -up openssl-1.0.1e/ssl/s3_pkt.c.keying-mitm openssl-1.0.1e/ssl/s3_pkt.c
+--- openssl-1.0.1e/ssl/s3_pkt.c.keying-mitm 2014-06-02 19:48:04.640103383 +0200
++++ openssl-1.0.1e/ssl/s3_pkt.c 2014-06-02 19:48:04.643103452 +0200
+@@ -1298,6 +1298,15 @@ start:
+ goto f_err;
+ }
+
++ if (!(s->s3->flags & SSL3_FLAGS_CCS_OK))
++ {
++ al=SSL_AD_UNEXPECTED_MESSAGE;
++ SSLerr(SSL_F_SSL3_READ_BYTES,SSL_R_CCS_RECEIVED_EARLY);
++ goto f_err;
++ }
++
++ s->s3->flags &= ~SSL3_FLAGS_CCS_OK;
++
+ rr->length=0;
+
+ if (s->msg_callback)
+@@ -1432,7 +1441,7 @@ int ssl3_do_change_cipher_spec(SSL *s)
+
+ if (s->s3->tmp.key_block == NULL)
+ {
+- if (s->session == NULL)
++ if (s->session == NULL || s->session->master_key_length == 0)
+ {
+ /* might happen if dtls1_read_bytes() calls this */
+ SSLerr(SSL_F_SSL3_DO_CHANGE_CIPHER_SPEC,SSL_R_CCS_RECEIVED_EARLY);
+diff -up openssl-1.0.1e/ssl/s3_srvr.c.keying-mitm openssl-1.0.1e/ssl/s3_srvr.c
+--- openssl-1.0.1e/ssl/s3_srvr.c.keying-mitm 2014-06-02 19:48:04.630103151 +0200
++++ openssl-1.0.1e/ssl/s3_srvr.c 2014-06-02 19:48:04.643103452 +0200
+@@ -673,6 +673,7 @@ int ssl3_accept(SSL *s)
+ case SSL3_ST_SR_CERT_VRFY_A:
+ case SSL3_ST_SR_CERT_VRFY_B:
+
++ s->s3->flags |= SSL3_FLAGS_CCS_OK;
+ /* we should decide if we expected this one */
+ ret=ssl3_get_cert_verify(s);
+ if (ret <= 0) goto end;
+@@ -700,6 +701,7 @@ int ssl3_accept(SSL *s)
+
+ case SSL3_ST_SR_FINISHED_A:
+ case SSL3_ST_SR_FINISHED_B:
++ s->s3->flags |= SSL3_FLAGS_CCS_OK;
+ ret=ssl3_get_finished(s,SSL3_ST_SR_FINISHED_A,
+ SSL3_ST_SR_FINISHED_B);
+ if (ret <= 0) goto end;
+@@ -770,7 +772,10 @@ int ssl3_accept(SSL *s)
+ s->s3->tmp.next_state=SSL3_ST_SR_FINISHED_A;
+ #else
+ if (s->s3->next_proto_neg_seen)
++ {
++ s->s3->flags |= SSL3_FLAGS_CCS_OK;
+ s->s3->tmp.next_state=SSL3_ST_SR_NEXT_PROTO_A;
++ }
+ else
+ s->s3->tmp.next_state=SSL3_ST_SR_FINISHED_A;
+ #endif
diff --git a/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-3470.patch b/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-3470.patch
new file mode 100644
index 0000000..025727f
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl/openssl-1.0.1e-cve-2014-3470.patch
@@ -0,0 +1,31 @@
+commit 4ad43d511f6cf064c66eb4bfd0fb0919b5dd8a86
+Author: Dr. Stephen Henson
+Date: Thu May 29 15:00:05 2014 +0100
+
+ Fix CVE-2014-3470
+
+ Check session_cert is not NULL before dereferencing it.
+
+Patch borrowed from Fedora
+Upstream-Status: Backport
+Signed-off-by: Paul Eggleton
+
+
+diff --git a/ssl/s3_clnt.c b/ssl/s3_clnt.c
+index d35376d..4324f8d 100644
+--- a/ssl/s3_clnt.c
++++ b/ssl/s3_clnt.c
+@@ -2511,6 +2511,13 @@ int ssl3_send_client_key_exchange(SSL *s)
+ int ecdh_clnt_cert = 0;
+ int field_size = 0;
+
++ if (s->session->sess_cert == NULL)
++ {
++ ssl3_send_alert(s,SSL3_AL_FATAL,SSL_AD_UNEXPECTED_MESSAGE);
++ SSLerr(SSL_F_SSL3_SEND_CLIENT_KEY_EXCHANGE,SSL_R_UNEXPECTED_MESSAGE);
++ goto err;
++ }
++
+ /* Did we send out the client's
+ * ECDH share for use in premaster
+ * computation as part of client certificate?
diff --git a/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl_1.0.1j.bb b/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl_1.0.1j.bb
new file mode 100644
index 0000000..ecb31d0
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/openssl/openssl_1.0.1j.bb
@@ -0,0 +1,54 @@
+require openssl.inc
+
+# For target side versions of openssl enable support for OCF Linux driver
+# if they are available.
+DEPENDS += "cryptodev-linux"
+
+CFLAG += "-DHAVE_CRYPTODEV -DUSE_CRYPTODEV_DIGESTS"
+
+LIC_FILES_CHKSUM = "file://LICENSE;md5=f9a8f968107345e0b75aa8c2ecaa7ec8"
+
+export DIRS = "crypto ssl apps engines"
+export OE_LDFLAGS="${LDFLAGS}"
+
+SRC_URI += "file://configure-targets.patch \
+ file://shared-libs.patch \
+ file://oe-ldflags.patch \
+ file://engines-install-in-libdir-ssl.patch \
+ file://openssl-fix-link.patch \
+ file://debian/version-script.patch \
+ file://debian/pic.patch \
+ file://debian/c_rehash-compat.patch \
+ file://debian/ca.patch \
+ file://debian/make-targets.patch \
+ file://debian/no-rpath.patch \
+ file://debian/man-dir.patch \
+ file://debian/man-section.patch \
+ file://debian/no-symbolic.patch \
+ file://debian/debian-targets.patch \
+ file://openssl_fix_for_x32.patch \
+ file://fix-cipher-des-ede3-cfb1.patch \
+ file://openssl-avoid-NULL-pointer-dereference-in-EVP_DigestInit_ex.patch \
+ file://openssl-avoid-NULL-pointer-dereference-in-dh_pub_encode.patch \
+ file://initial-aarch64-bits.patch \
+ file://find.pl \
+ file://openssl-fix-des.pod-error.patch \
+ "
+
+SRC_URI[md5sum] = "f7175c9cd3c39bb1907ac8bba9df8ed3"
+SRC_URI[sha256sum] = "1b60ca8789ba6f03e8ef20da2293b8dc131c39d83814e775069f02d26354edf3"
+
+PACKAGES =+ " \
+ ${PN}-engines \
+ ${PN}-engines-dbg \
+ "
+
+FILES_${PN}-engines = "${libdir}/ssl/engines/*.so ${libdir}/engines"
+FILES_${PN}-engines-dbg = "${libdir}/ssl/engines/.debug"
+
+PARALLEL_MAKE = ""
+PARALLEL_MAKEINST = ""
+
+do_configure_prepend() {
+ cp ${WORKDIR}/find.pl ${S}/util/find.pl
+}
diff --git a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/defconfig-gnutls b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/defconfig-gnutls
index 4f0b510..71f42e6 100644
--- a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/defconfig-gnutls
+++ b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/defconfig-gnutls
@@ -420,6 +420,10 @@ CONFIG_CTRL_IFACE_DBUS_NEW=y
# external RADIUS server can be supported with hostapd.
CONFIG_AP=y
+# P2P (Wi-Fi Direct)
+# This can be used to enable P2P support in wpa_supplicant. See README-P2P for
+# more information on P2P operations.
+CONFIG_P2P=y
CONFIG_BGSCAN_SIMPLE=y
# Autoscan
@@ -432,8 +436,5 @@ CONFIG_AUTOSCAN_EXPONENTIAL=y
# For periodic module:
#CONFIG_AUTOSCAN_PERIODIC=y
-# WPA_CLI Private commands
-# This enables private commands usage by wpa_cli
-#
-CFLAGS += -DEDISON_USE_PRIVATE_BCM_CMD
-CONFIG_USE_VENDOR_PRIVATE_CMD=y
+CFLAGS += -DEDISON_TARGET
+CFLAGS += -DANDROID_P2P
diff --git a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/p2p_supplicant.conf-sane b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/p2p_supplicant.conf-sane
new file mode 100644
index 0000000..62e2236
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/p2p_supplicant.conf-sane
@@ -0,0 +1,12 @@
+ctrl_interface=/var/run/wpa_supplicant
+ctrl_interface_group=0
+config_methods=virtual_push_button virtual_display push_button keypad
+update_config=1
+fast_reauth=1
+device_name=Edison
+manufacturer=Intel
+model_name=Edison
+p2p_ssid_postfix=-Edison
+persistent_reconnect=1
+
+
diff --git a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/udhcpd-p2p.conf b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/udhcpd-p2p.conf
new file mode 100644
index 0000000..dcd92f2
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/udhcpd-p2p.conf
@@ -0,0 +1,107 @@
+# Sample udhcpd configuration file (/etc/udhcpd.conf)
+
+# The start and end of the IP lease block
+
+start 192.168.42.20 #default: 192.168.0.20
+end 192.168.42.254 #default: 192.168.0.254
+
+
+# The interface that udhcpd will use
+
+interface INTERFACE #default: eth0
+
+
+# The maximim number of leases (includes addressesd reserved
+# by OFFER's, DECLINE's, and ARP conficts
+
+#max_leases 254 #default: 254
+
+
+# If remaining is true (default), udhcpd will store the time
+# remaining for each lease in the udhcpd leases file. This is
+# for embedded systems that cannot keep time between reboots.
+# If you set remaining to no, the absolute time that the lease
+# expires at will be stored in the dhcpd.leases file.
+
+#remaining yes #default: yes
+
+
+# The time period at which udhcpd will write out a dhcpd.leases
+# file. If this is 0, udhcpd will never automatically write a
+# lease file. (specified in seconds)
+
+#auto_time 7200 #default: 7200 (2 hours)
+
+
+# The amount of time that an IP will be reserved (leased) for if a
+# DHCP decline message is received (seconds).
+
+#decline_time 3600 #default: 3600 (1 hour)
+
+
+# The amount of time that an IP will be reserved (leased) for if an
+# ARP conflct occurs. (seconds
+
+#conflict_time 3600 #default: 3600 (1 hour)
+
+
+# How long an offered address is reserved (leased) in seconds
+
+#offer_time 60 #default: 60 (1 minute)
+
+# If a lease to be given is below this value, the full lease time is
+# instead used (seconds).
+
+#min_lease 60 #defult: 60
+
+
+# The location of the leases file
+
+#lease_file /var/lib/misc/udhcpd.leases #defualt: /var/lib/misc/udhcpd.leases
+
+# The location of the pid file
+pidfile /var/run/udhcpd-INTERFACE.pid #default: /var/run/udhcpd.pid
+
+# Every time udhcpd writes a leases file, the below script will be called.
+# Useful for writing the lease file to flash every few hours.
+
+#notify_file #default: (no script)
+
+#notify_file dumpleases # <--- useful for debugging
+
+# The following are bootp specific options, setable by udhcpd.
+
+#siaddr 192.168.0.22 #default: 0.0.0.0
+
+#sname zorak #default: (none)
+
+#boot_file /var/nfs_root #default: (none)
+
+# The remainer of options are DHCP options and can be specifed with the
+# keyword 'opt' or 'option'. If an option can take multiple items, such
+# as the dns option, they can be listed on the same line, or multiple
+# lines. The only option with a default is 'lease'.
+
+# Currently supported options, for more info, see options.c
+opt subnet 255.255.255.0
+#opt timezone
+#opt router
+#opt timesvr
+#opt namesvr
+#opt dns
+#opt logsvr
+#opt cookiesvr
+#opt lprsvr
+#opt bootsize
+#opt domain
+#opt swapsvr
+#opt rootpath
+#opt ipttl
+#opt mtu
+#opt broadcast
+#opt wins
+#opt lease
+#opt ntpsrv
+#opt tftp
+#opt bootfile
+
diff --git a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa-supplicant-android-4.4.4_r2.0.1.patch b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa-supplicant-android-4.4.4_r2.0.1.patch
new file mode 100644
index 0000000..ceee40d
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa-supplicant-android-4.4.4_r2.0.1.patch
@@ -0,0 +1,184 @@
+
+--- a/wpa_supplicant/src/drivers/driver_nl80211.c 2014-10-01 16:44:14.819137037 +0200
++++ b/wpa_supplicant/src/drivers/driver_nl80211.c 2014-10-01 16:37:16.979149254 +0200
+@@ -321,7 +321,7 @@
+ struct wpa_driver_scan_params *params);
+ static int android_pno_stop(struct i802_bss *bss);
+ #endif /* ANDROID */
+-#ifdef ANDROID_P2P
++#if defined(ANDROID_P2P) && !defined(EDISON_TARGET)
+ int wpa_driver_set_p2p_noa(void *priv, u8 count, int start, int duration);
+ int wpa_driver_get_p2p_noa(void *priv, u8 *buf, size_t len);
+ int wpa_driver_set_p2p_ps(void *priv, int legacy_ps, int opp_ps, int ctwindow);
+@@ -10329,7 +10329,7 @@
+ "opp_ps=%d ctwindow=%d)", legacy_ps, opp_ps, ctwindow);
+
+ if (opp_ps != -1 || ctwindow != -1)
+-#ifdef ANDROID_P2P
++#if defined(ANDROID_P2P) && !defined(EDISON_TARGET)
+ wpa_driver_set_p2p_ps(priv, legacy_ps, opp_ps, ctwindow);
+ #else
+ return -1; /* Not yet supported */
+@@ -10832,7 +10832,7 @@
+ .update_ft_ies = wpa_driver_nl80211_update_ft_ies,
+ .get_mac_addr = wpa_driver_nl80211_get_macaddr,
+ .get_survey = wpa_driver_nl80211_get_survey,
+-#ifdef ANDROID_P2P
++#if defined(ANDROID_P2P) && !defined(EDISON_TARGET)
+ .set_noa = wpa_driver_set_p2p_noa,
+ .get_noa = wpa_driver_get_p2p_noa,
+ .set_ap_wps_ie = wpa_driver_set_ap_wps_p2p_ie,
+
+--- a/wpa_supplicant/wpa_cli.c 2014-10-01 16:52:31.123122526 +0200
++++ b/wpa_supplicant/wpa_cli.c 2014-10-01 17:05:59.043098904 +0200
+@@ -3625,7 +3625,8 @@
+ continue;
+ #endif /* _DIRENT_HAVE_D_TYPE */
+ if (os_strcmp(dent->d_name, ".") == 0 ||
+- os_strcmp(dent->d_name, "..") == 0)
++ os_strcmp(dent->d_name, "..") == 0 ||
++ os_strstr(dent->d_name, "p2p"))
+ continue;
+ printf("Selected interface '%s'\n", dent->d_name);
+ ifname = os_strdup(dent->d_name);
+
+--- a/wpa_supplicant/p2p_supplicant.c 2014-09-26 12:09:39.856249682 +0200
++++ b/wpa_supplicant/p2p_supplicant.c 2014-12-17 16:42:39.535846212 +0100
+@@ -3061,6 +3061,13 @@
+ int cla, op;
+
+ if (wpa_s->hw.modes == NULL) {
++ wpa_printf(MSG_DEBUG, "P2P: Driver did not support fetching. "
++ "Use supported channels retrieved on interface wlan0");
++ wpa_s = wpa_s->global->ifaces;
++
++ }
++
++ if (wpa_s->hw.modes == NULL) {
+ wpa_printf(MSG_DEBUG, "P2P: Driver did not support fetching "
+ "of all supported channels; assume dualband "
+ "support");
+@@ -3172,7 +3179,8 @@
+ }
+
+
+-int wpas_p2p_add_p2pdev_interface(struct wpa_supplicant *wpa_s)
++int wpas_p2p_add_p2pdev_interface(struct wpa_supplicant *wpa_s,
++ const char *conf_p2p_dev)
+ {
+ struct wpa_interface iface;
+ struct wpa_supplicant *p2pdev_wpa_s;
+@@ -3198,7 +3206,20 @@
+ iface.ifname = wpa_s->pending_interface_name;
+ iface.driver = wpa_s->driver->name;
+ iface.driver_param = wpa_s->conf->driver_param;
+- iface.confname = wpa_s->confname;
++
++ /*
++ * If a P2P Device configuration file was given, use it as the interface
++ * configuration file (instead of using parent's configuration file.
++ */
++ if (conf_p2p_dev) {
++ iface.confname = conf_p2p_dev;
++ iface.ctrl_interface = NULL;
++ } else {
++ iface.confname = wpa_s->confname;
++ iface.ctrl_interface = wpa_s->conf->ctrl_interface;
++ }
++ iface.conf_p2p_dev = NULL;
++
+ p2pdev_wpa_s = wpa_supplicant_add_iface(wpa_s->global, &iface);
+ if (!p2pdev_wpa_s) {
+ wpa_printf(MSG_DEBUG, "P2P: Failed to add P2P Device interface");
+
+--- a/wpa_supplicant/main.c 2014-09-26 12:09:39.856249682 +0200
++++ b/wpa_supplicant/main.c 2014-12-17 16:42:39.535846212 +0100
+@@ -83,6 +83,9 @@
+ #endif /* CONFIG_DBUS */
+ printf(" -v = show version\n"
+ " -W = wait for a control interface monitor before starting\n"
++#ifdef CONFIG_P2P
++ " -m = Configuration file for the P2P Device interface\n"
++#endif /* CONFIG_P2P */
+ " -N = start describing new interface\n");
+
+ printf("example:\n"
+@@ -160,7 +163,7 @@
+
+ for (;;) {
+ c = getopt(argc, argv,
+- "b:Bc:C:D:de:f:g:G:hi:I:KLNo:O:p:P:qsTtuvW");
++ "b:Bc:C:D:de:f:g:G:hi:I:KLm:No:O:p:P:qsTtuvW");
+ if (c < 0)
+ break;
+ switch (c) {
+@@ -220,6 +223,11 @@
+ license();
+ exitcode = 0;
+ goto out;
++#ifdef CONFIG_P2P
++ case 'm':
++ iface->conf_p2p_dev = optarg;
++ break;
++#endif /* CONFIG_P2P */
+ case 'o':
+ params.override_driver = optarg;
+ break;
+@@ -311,7 +319,7 @@
+ if (wpa_s->global->p2p == NULL &&
+ (wpa_s->drv_flags &
+ WPA_DRIVER_FLAGS_DEDICATED_P2P_DEVICE) &&
+- wpas_p2p_add_p2pdev_interface(wpa_s) < 0)
++ wpas_p2p_add_p2pdev_interface(wpa_s, iface->conf_p2p_dev) < 0)
+ exitcode = -1;
+ #endif /* CONFIG_P2P */
+ }
+
+--- a/wpa_supplicant/p2p_supplicant.h 2014-09-26 12:09:39.856249682 +0200
++++ b/wpa_supplicant/p2p_supplicant.h 2014-12-17 16:42:39.535846212 +0100
+@@ -19,7 +19,8 @@
+ int wpas_p2p_init(struct wpa_global *global, struct wpa_supplicant *wpa_s);
+ void wpas_p2p_deinit(struct wpa_supplicant *wpa_s);
+ void wpas_p2p_deinit_global(struct wpa_global *global);
+-int wpas_p2p_add_p2pdev_interface(struct wpa_supplicant *wpa_s);
++int wpas_p2p_add_p2pdev_interface(struct wpa_supplicant *wpa_s,
++ const char *conf_p2p_dev);
+ int wpas_p2p_connect(struct wpa_supplicant *wpa_s, const u8 *peer_addr,
+ const char *pin, enum p2p_wps_method wps_method,
+ int persistent_group, int auto_join, int join,
+
+--- a/wpa_supplicant/wpa_supplicant_i.h 2014-09-26 12:09:39.856249682 +0200
++++ b/wpa_supplicant/wpa_supplicant_i.h 2014-12-17 16:42:39.535846212 +0100
+@@ -63,6 +63,17 @@
+ */
+ const char *confanother;
+
++#ifdef CONFIG_P2P
++ /**
++ * conf_p2p_dev - Configuration file used to hold the
++ * P2P Device configuration parameters.
++ *
++ * This can also be %NULL. In such a case, if a P2P Device dedicated
++ * interfaces is created, the main configuration file will be used.
++ */
++ const char *conf_p2p_dev;
++#endif /* CONFIG_P2P */
++
+ /**
+ * ctrl_interface - Control interface parameter
+ *
+
+@@ -904,0 +904,0 @@
+--- a/wpa_supplicant/scan.c 2014-09-26 12:09:39.856249682 +0200
++++ b/wpa_supplicant/scan.c 2014-12-17 16:42:39.535846212 +0100
+@@ -904,7 +904,7 @@
+ */
+ void wpa_supplicant_req_scan(struct wpa_supplicant *wpa_s, int sec, int usec)
+ {
+-#ifndef ANDROID
++#if !defined(ANDROID) && !defined(EDISON_TARGET)
+ /* If there's at least one network that should be specifically scanned
+ * then don't cancel the scan and reschedule. Some drivers do
+ * background scanning which generates frequent scan results, and that
+
+
diff --git a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_cli-actions.sh b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_cli-actions.sh
index b4bd8d8..77b9086 100644
--- a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_cli-actions.sh
+++ b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_cli-actions.sh
@@ -3,8 +3,10 @@
# This script file is passed as parameter to wpa_cli, started as a daemon,
# so that the wpa_supplicant events are sent to this script
# and actions executed, like :
-# - start DHCP client when Wifi is connected.
-# - stop DHCP client when Wifi is disconnected.
+# - start DHCP client when STA is connected.
+# - stop DHCP client when STA is disconnected.
+# - start DHCP client when P2P-GC is connected.
+# - stop DHCP server when P2P-GO is disconnected.
#
# This script skips events if connmand (connman.service) is started
# Indeed, it is considered that the Wifi connection is managed through
@@ -36,11 +38,14 @@ kill_daemon() {
echo "event $CMD received from wpa_supplicant"
-# if connman is started, ignore the connmand.
-# DHCP connection is triggerd by connman
+# if Connman is started, ignore wpa_supplicant
+# STA connection event because the DHCP connection
+# is triggerd by Connman
if [ `systemctl is-active connman` == "active" ] ; then
- echo "event $CMD ignored because is started"
- exit 0
+ if [ "$CMD" = "CONNECTED" ] || [ "$CMD" = "DISCONNECTED" ] ; then
+ echo "event $CMD ignored because Connman is started"
+ exit 0
+ fi
fi
if [ "$CMD" = "CONNECTED" ]; then
@@ -53,3 +58,31 @@ if [ "$CMD" = "DISCONNECTED" ]; then
ifconfig $IFNAME 0.0.0.0
fi
+if [ "$CMD" = "P2P-GROUP-STARTED" ]; then
+ GIFNAME=$3
+ if [ "$4" = "GO" ]; then
+ kill_daemon udhcpc /var/run/udhcpc-$GIFNAME.pid
+ ifconfig $GIFNAME 192.168.42.1 up
+ cp /etc/wpa_supplicant/udhcpd-p2p.conf /etc/wpa_supplicant/udhcpd-p2p-itf.conf
+ sed -i "s/INTERFACE/$GIFNAME/" /etc/wpa_supplicant/udhcpd-p2p-itf.conf
+ udhcpd /etc/wpa_supplicant/udhcpd-p2p-itf.conf
+ fi
+ if [ "$4" = "client" ]; then
+ kill_daemon udhcpc /var/run/udhcpc-$GIFNAME.pid
+ kill_daemon udhcpd /var/run/udhcpd-$GIFNAME.pid
+ udhcpc -i $GIFNAME -p /var/run/udhcpc-$GIFNAME.pid
+ fi
+fi
+
+if [ "$CMD" = "P2P-GROUP-REMOVED" ]; then
+ GIFNAME=$3
+ if [ "$4" = "GO" ]; then
+ kill_daemon udhcpd /var/run/udhcpd-$GIFNAME.pid
+ ifconfig $GIFNAME 0.0.0.0
+ fi
+ if [ "$4" = "client" ]; then
+ kill_daemon udhcpc /var/run/udhcpc-$GIFNAME.pid
+ ifconfig $GIFNAME 0.0.0.0
+ fi
+fi
+
diff --git a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant.conf-sane b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant.conf-sane
index e737c3c..4d37989 100644
--- a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant.conf-sane
+++ b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant.conf-sane
@@ -1,5 +1,10 @@
ctrl_interface=/var/run/wpa_supplicant
ctrl_interface_group=0
+config_methods=virtual_push_button virtual_display push_button keypad
update_config=1
-ap_scan=1
+fast_reauth=1
+device_name=Edison
+manufacturer=Intel
+model_name=Edison
+
diff --git a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant.service b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant.service
index ce95f18..ec363aa 100644
--- a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant.service
+++ b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant.service
@@ -6,14 +6,16 @@ After=sys-subsystem-net-devices-wlan0.device
[Service]
Type=simple
-# start wpa_supplicant service
-ExecStart=/usr/sbin/wpa_supplicant -c/etc/wpa_supplicant/wpa_supplicant.conf -iwlan0 -Dnl80211 -u -O /var/run/wpa_supplicant
+# start wpa_supplicant service :
+# - the second interface p2p-dev-wlan0 is automatically created at startup
+# - the file wpa_supplicant is common to both interfaces wlan0 and p2p-dev-wlan0
+ExecStart=/usr/sbin/wpa_supplicant -u -c/etc/wpa_supplicant/wpa_supplicant.conf -iwlan0 -Dnl80211 -puse_p2p_group_interface=1p2p_device=1 -m/etc/wpa_supplicant/p2p_supplicant.conf -O /var/run/wpa_supplicant -e /etc/wpa_supplicant/entropy.bin
# start wpa_supplicant_event service after the start of wpa_supplicant service
-ExecStartPost=/bin/systemctl start wpa_supplicant_event
+ExecStartPost=/bin/systemctl start wpa_supplicant_wlan0_event ; /bin/systemctl start wpa_supplicant_p2p_event
# stop wpa_supplicant_event service after the stop of wpa_supplicant service
-ExecStopPost=/bin/systemctl stop wpa_supplicant_event
+ExecStopPost=/bin/systemctl stop wpa_supplicant_wlan0_event ; /bin/systemctl stop wpa_supplicant_p2p_event
[Install]
WantedBy=multi-user.target
diff --git a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant_p2p_event.service b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant_p2p_event.service
new file mode 100644
index 0000000..b5445a2
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant_p2p_event.service
@@ -0,0 +1,13 @@
+[Unit]
+Description=Daemon to receive the wpa_supplicant event
+Requires=sys-subsystem-net-devices-wlan0.device
+After=sys-subsystem-net-devices-wlan0.device
+
+[Service]
+Type=simple
+ExecStart=/usr/sbin/wpa_cli -a /etc/wpa_supplicant/wpa_cli-actions.sh -i p2p-dev-wlan0
+Restart=on-failure
+RestartSec=1
+
+[Install]
+WantedBy=multi-user.target
diff --git a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant_wlan0_event.service b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant_wlan0_event.service
new file mode 100644
index 0000000..7428b4c
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant/wpa_supplicant_wlan0_event.service
@@ -0,0 +1,13 @@
+[Unit]
+Description=Daemon to receive the wpa_supplicant event
+Requires=sys-subsystem-net-devices-wlan0.device
+After=sys-subsystem-net-devices-wlan0.device
+
+[Service]
+Type=simple
+ExecStart=/usr/sbin/wpa_cli -a /etc/wpa_supplicant/wpa_cli-actions.sh -i wlan0
+Restart=on-failure
+RestartSec=1
+
+[Install]
+WantedBy=multi-user.target
diff --git a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant_2.1.bbappend b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant_2.1.bbappend
index ecbfd5c..5063afd 100644
--- a/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant_2.1.bbappend
+++ b/device-software/meta-edison-distro/recipes-connectivity/wpa_supplicant/wpa-supplicant_2.1.bbappend
@@ -1,33 +1,37 @@
LIC_FILES_CHKSUM = "file://COPYING;md5=ab87f20cd7e8c0d0a6539b34d3791d0e \
- file://README;md5=a07250b28e857455336bb59fc31cb845 \
- file://wpa_supplicant/wpa_supplicant.c;beginline=1;endline=12;md5=e8e021e30f3a6ab7c341b66b86626a5a"
+ file://README;md5=5c7cc1ea1a4d82b1cbe9a02fe92881b8 \
+ file://wpa_supplicant/wpa_supplicant.c;beginline=1;endline=12;md5=cba4fa09fa364da845ca546f21008909"
RRECOMMENDS_${PN} = "wpa-supplicant-passphrase wpa-supplicant-cli"
-SYSTEMD_SERVICE_${PN} = "wpa_supplicant.service wpa_supplicant_event.service"
+
+SYSTEMD_SERVICE_${PN} = "wpa_supplicant.service wpa_supplicant_wlan0_event.service wpa_supplicant_p2p_event.service"
FILESEXTRAPATHS_prepend := "${THISDIR}/wpa-supplicant:"
+PV = "android-4.4.4_r2.0.1"
+
BASE_SRC_URI = "file://defconfig-gnutls \
- file://wpa_supplicant.conf \
file://wpa_supplicant.conf-sane \
+ file://p2p_supplicant.conf-sane \
file://99_wpa_supplicant \
file://fi.w1.wpa_supplicant1.service \
+ file://udhcpd-p2p.conf \
file://wpa_supplicant.service \
- file://wpa_supplicant_event.service \
+ file://wpa_supplicant_wlan0_event.service \
+ file://wpa_supplicant_p2p_event.service \
file://wpa-supplicant.sh \
+ file://wpa-supplicant-${PV}.patch \
file://wpa_cli-actions.sh "
-PV = "2.2"
-
SRC_URI = "${BASE_SRC_URI} \
- http://hostap.epitest.fi/releases/wpa_supplicant-${PV}.tar.gz "
+ git://android.googlesource.com/platform/external/wpa_supplicant_8;protocol=https;tag=android-4.4.4_r2.0.1"
+S = "${WORKDIR}/git"
PR = "r1"
-SRC_URI[md5sum] = "238e8e888bbd558e1a57e3eb28d1dd07"
-SRC_URI[sha256sum] = "e0d8b8fd68a659636eaba246bb2caacbf53d22d53b2b6b90eb4b4fef0993c8ed"
-
+SRC_URI[md5sum] = "f2ed8fef72cf63d8d446a2d0a6da630a"
+SRC_URI[sha256sum] = "eaaa5bf3055270e521b2dff64f2d203ec8040f71958b8588269a82c00c9d7b6a"
FILES_${PN} += "${datadir}/dbus-1/system-services/* \
${systemd_unitdir}/system/ \
@@ -52,6 +56,7 @@ do_install () {
install -d ${D}${sysconfdir}/wpa_supplicant
install -m 600 ${WORKDIR}/wpa_supplicant.conf-sane ${D}${sysconfdir}/wpa_supplicant/wpa_supplicant.conf
+ install -m 600 ${WORKDIR}/p2p_supplicant.conf-sane ${D}${sysconfdir}/wpa_supplicant/p2p_supplicant.conf
install -d ${D}/${sysconfdir}/dbus-1/system.d
install -m 644 ${S}/wpa_supplicant/dbus/dbus-wpa_supplicant.conf ${D}/${sysconfdir}/dbus-1/system.d
@@ -70,7 +75,11 @@ do_install () {
# Install wpa_supplicant_event service for udhcp client start/stop based on wifi connection/disconnection
install -m 755 ${WORKDIR}/wpa_cli-actions.sh ${D}${sysconfdir}/wpa_supplicant
- install -m 644 ${WORKDIR}/wpa_supplicant_event.service ${D}${systemd_unitdir}/system
+ install -m 644 ${WORKDIR}/wpa_supplicant_wlan0_event.service ${D}${systemd_unitdir}/system
+ install -m 644 ${WORKDIR}/wpa_supplicant_p2p_event.service ${D}${systemd_unitdir}/system
+
+ # Install udhcp server configuration file for P2P GO
+ install -m 644 ${WORKDIR}/udhcpd-p2p.conf ${D}${sysconfdir}/wpa_supplicant
fi
install -d ${D}/etc/default/volatiles
diff --git a/device-software/meta-edison-distro/recipes-core/base-files/base-files/media-sdcard.automount b/device-software/meta-edison-distro/recipes-core/base-files/base-files/media-sdcard.automount
new file mode 100644
index 0000000..a577591
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-core/base-files/base-files/media-sdcard.automount
@@ -0,0 +1,11 @@
+[Unit]
+Description=Automount for SDCard
+ConditionPathExists=/dev/mmcblk1p1
+RefuseManualStart=true
+RefuseManualStop=true
+
+[Automount]
+Where=/media/sdcard
+
+[Install]
+WantedBy=local-fs.target
diff --git a/device-software/meta-edison-distro/recipes-core/base-files/base-files/media-sdcard.mount b/device-software/meta-edison-distro/recipes-core/base-files/base-files/media-sdcard.mount
index c7d52ac..a9d310b 100644
--- a/device-software/meta-edison-distro/recipes-core/base-files/base-files/media-sdcard.mount
+++ b/device-software/meta-edison-distro/recipes-core/base-files/base-files/media-sdcard.mount
@@ -1,10 +1,7 @@
[Unit]
Description=Mount for SDCard
-Requires=dev-mmcblk1p1.device
-After=dev-mmcblk1p1.device
-
-[Install]
-WantedBy=default.target
+BindsTo=dev-mmcblk1p1.device
+Conflicts=media-sdcard.automount
[Mount]
What=/dev/mmcblk1p1
diff --git a/device-software/meta-edison-distro/recipes-core/base-files/base-files/share/dot.profile b/device-software/meta-edison-distro/recipes-core/base-files/base-files/share/dot.profile
new file mode 100644
index 0000000..4f1d2a0
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-core/base-files/base-files/share/dot.profile
@@ -0,0 +1,9 @@
+# ~/.profile: executed by Bourne-compatible login shells.
+
+if [ -f ~/.bashrc ]; then
+ . ~/.bashrc
+fi
+
+# path set by /etc/profile
+# export PATH
+
diff --git a/device-software/meta-edison-distro/recipes-core/base-files/base-files_3.0.14.bbappend b/device-software/meta-edison-distro/recipes-core/base-files/base-files_3.0.14.bbappend
index 13e7606..dd8d96a 100644
--- a/device-software/meta-edison-distro/recipes-core/base-files/base-files_3.0.14.bbappend
+++ b/device-software/meta-edison-distro/recipes-core/base-files/base-files_3.0.14.bbappend
@@ -1,26 +1,33 @@
FILESEXTRAPATHS_prepend := "${THISDIR}/base-files:"
SRC_URI += "file://fstab"
SRC_URI += "file://media-sdcard.mount"
+SRC_URI += "file://media-sdcard.automount"
SRC_URI += "file://factory.mount"
+SRC_URI += "file://share/dot.profile"
# override default volatile to suppress var/log link creation
volatiles = "tmp"
do_install_append() {
install -m 0644 ${WORKDIR}/fstab ${D}${sysconfdir}/fstab
+ install -m 0755 ${WORKDIR}/share/dot.profile ${D}${sysconfdir}/skel/.profile
# enable mount of the SDCard in /media/sdcard when inserted
install -d ${D}${systemd_unitdir}/system
install -c -m 0644 ${WORKDIR}/media-sdcard.mount ${D}${systemd_unitdir}/system
+ install -c -m 0644 ${WORKDIR}/media-sdcard.automount ${D}${systemd_unitdir}/system
install -c -m 0644 ${WORKDIR}/factory.mount ${D}${systemd_unitdir}/system
# Enable the service
+ install -d ${D}${sysconfdir}/systemd/system/local-fs.target.wants
+ ln -sf ${systemd_unitdir}/system/media-sdcard.automount \
+ ${D}${sysconfdir}/systemd/system/local-fs.target.wants/media-sdcard.automount
install -d ${D}${sysconfdir}/systemd/system/default.target.wants
- ln -sf ${systemd_unitdir}/system/media-sdcard.mount \
- ${D}${sysconfdir}/systemd/system/default.target.wants/media-sdcard.mount
- ln -sf ${systemd_unitdir}/system/factory.mount \
+ ln -sf ${systemd_unitdir}/system/factory.mount \
${D}${sysconfdir}/systemd/system/default.target.wants/factory.mount
}
FILES_${PN} += "${base_libdir}/systemd/system/*.mount"
+FILES_${PN} += "${base_libdir}/systemd/system/*.automount"
FILES_${PN} += "${sysconfdir}/systemd/system/default.target.wants/*.mount"
+FILES_${PN} += "${sysconfdir}/systemd/system/local-fs.target.wants/*.automount"
diff --git a/device-software/meta-edison-distro/recipes-core/busybox/busybox_1.22.1.bbappend b/device-software/meta-edison-distro/recipes-core/busybox/busybox_1.22.1.bbappend
index 7ce27a9..faf18af 100644
--- a/device-software/meta-edison-distro/recipes-core/busybox/busybox_1.22.1.bbappend
+++ b/device-software/meta-edison-distro/recipes-core/busybox/busybox_1.22.1.bbappend
@@ -1,4 +1,5 @@
-# to get brctl configuration settings
-FILESEXTRAPATHS_prepend := "${THISDIR}/files/"
+# to get brctl and log configuration settings
+FILESEXTRAPATHS_prepend := "${THISDIR}/files/:"
-SRC_URI += "file://brctl-utilities.cfg"
+SRC_URI += "file://brctl-utilities.cfg \
+ file://busybox-log.cfg "
diff --git a/device-software/meta-edison-distro/recipes-core/busybox/files/busybox-log.cfg b/device-software/meta-edison-distro/recipes-core/busybox/files/busybox-log.cfg
new file mode 100644
index 0000000..7b7408f
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-core/busybox/files/busybox-log.cfg
@@ -0,0 +1,3 @@
+CONFIG_KLOGD=n
+CONFIG_SYSLOGD=n
+
diff --git a/device-software/meta-edison-distro/recipes-core/first-install/files/first-install.service b/device-software/meta-edison-distro/recipes-core/first-install/files/first-install.service
index 4c00f71..3ebb9d7 100644
--- a/device-software/meta-edison-distro/recipes-core/first-install/files/first-install.service
+++ b/device-software/meta-edison-distro/recipes-core/first-install/files/first-install.service
@@ -4,6 +4,6 @@ OnFailure=reboot.target
Requires=dev-disk-by\x2dpartlabel-home.device dev-disk-by\x2dpartlabel-update.device
After=dev-disk-by\x2dpartlabel-home.device dev-disk-by\x2dpartlabel-update.device
[Service]
-ExecStart=@BASE_BINDIR@/sh @BASE_SBINDIR@/first-install.sh systemd-service
+ExecStart=@BASE_BINDIR@/sh -c "shell='sh'; if [ -f /bin/bash ]; then shell='bash'; fi; @BASE_BINDIR@/$shell @BASE_SBINDIR@/first-install.sh systemd-service"
StandardOutput=journal+console
diff --git a/device-software/meta-edison-distro/recipes-core/first-install/files/first-install.sh b/device-software/meta-edison-distro/recipes-core/first-install/files/first-install.sh
index d429c8a..1b29245 100644
--- a/device-software/meta-edison-distro/recipes-core/first-install/files/first-install.sh
+++ b/device-software/meta-edison-distro/recipes-core/first-install/files/first-install.sh
@@ -1,9 +1,11 @@
-#!/bin/sh
+#!/bin/bash
# first install script to do post flash install
# global variable set to 1 if output is systemd journal
fi_journal_out=0
+export PATH="$PATH:/usr/sbin/"
+
# handle argument, if first-install is called from systemd service
# arg1 is "systemd-service"
if [ "$1" == "systemd-service" ]; then fi_journal_out=1; fi;
@@ -48,11 +50,11 @@ exit_first_install () {
# next reboot will be on multi-user target
fw_setenv bootargs_target multi-user
fi
-
- fi_echo "Rebooting...."
# dump journal to log file
journalctl -u first-install -o short-iso >> /first-install.log
- reboot
+ systemctl daemon-reload
+ systemctl stop home.mount
+ systemctl default
}
# continue normal flow or exit on error code
@@ -128,15 +130,17 @@ mkfs.ext4 -m0 /dev/disk/by-partlabel/home
fi_assert $? "Formatting home partition"
# backup initial /home/root directory
-cp -R /home/root /tmp
+mkdir /tmp/oldhome
+cp -R /home/* /tmp/oldhome/
fi_assert $? "Backup home/root contents of rootfs"
# mount home partition on /home
mount /dev/disk/by-partlabel/home /home
fi_assert $? "Mount /home partition"
-# copy back contents to /home
-mv /tmp/root /home
+# copy back contents to /home and cleanup
+mv /tmp/oldhome/* /home/
+rm -rf /tmp/oldhome
fi_assert $? "Restore home/root contents on new /home partition"
# create a fat32 primary partition on all available space
diff --git a/device-software/meta-edison-distro/recipes-core/images/edison-image.bb b/device-software/meta-edison-distro/recipes-core/images/edison-image.bb
index cea51da..f106657 100644
--- a/device-software/meta-edison-distro/recipes-core/images/edison-image.bb
+++ b/device-software/meta-edison-distro/recipes-core/images/edison-image.bb
@@ -49,7 +49,8 @@ IMAGE_INSTALL += "connman-tools"
IMAGE_INSTALL += "wireless-tools"
IMAGE_INSTALL += "wpa-supplicant"
IMAGE_INSTALL += "hostapd-daemon"
-IMAGE_INSTALL += "bluez5"
+IMAGE_INSTALL += "bluez5-dev"
+IMAGE_INSTALL += "bluez5-obex"
IMAGE_INSTALL += "kernel-modules"
IMAGE_INSTALL += "ethtool"
IMAGE_INSTALL += "iptables"
@@ -57,15 +58,15 @@ IMAGE_INSTALL += "libstdc++"
IMAGE_INSTALL += "u-boot"
IMAGE_INSTALL += "u-boot-fw-utils"
IMAGE_INSTALL += "file"
-IMAGE_INSTALL += "otg"
IMAGE_INSTALL += "pciutils"
IMAGE_INSTALL += "usbutils"
IMAGE_INSTALL += "ldd"
IMAGE_INSTALL += "i2c-tools"
IMAGE_INSTALL += "watchdog-sample"
IMAGE_INSTALL += "pwr-button-handler"
-IMAGE_INSTALL += "libwebsockets"
+IMAGE_INSTALL += "blink-led"
IMAGE_INSTALL += "first-install"
+IMAGE_INSTALL += "resize-rootfs"
IMAGE_INSTALL += "systemd-analyze"
IMAGE_INSTALL += "wget"
IMAGE_INSTALL += "ota-update"
@@ -73,10 +74,17 @@ IMAGE_INSTALL += "ota-update"
# Allows to enable OpenMP feature
IMAGE_INSTALL += "libgomp"
+# Add audio firmware
+IMAGE_INSTALL += "sst-fw-bin"
+
+# ALSA lib and utilities
+IMAGE_INSTALL += "alsa-lib"
+IMAGE_INSTALL += "alsa-utils-alsamixer alsa-utils-alsactl alsa-utils-aplay alsa-utils-amixer"
+
# Python and some basic modules
IMAGE_INSTALL += "python"
IMAGE_INSTALL += "python-dbus python-smartpm python-pygobject python-argparse"
-IMAGE_INSTALL += "python-distutils python-pkgutil python-audio python-image python-imaging python-email python-netserver python-xmlrpc python-ctypes python-html python-json python-compile python-misc python-numbers python-unittest"
+IMAGE_INSTALL += "python-distutils python-pkgutil python-audio python-image python-imaging python-email python-netserver python-xmlrpc python-ctypes python-html python-json python-compile python-misc python-numbers python-unittest python-pydoc"
# Wifi firmware
IMAGE_INSTALL += "bcm43340-fw"
@@ -91,12 +99,21 @@ IMAGE_INSTALL += "bcm43340-mod"
IMAGE_FEATURES += "tools-debug"
IMAGE_INSTALL += "crashlog"
+# Clean corrupted journald entries
+IMAGE_INSTALL += "cleanjournal"
+
# Adds various other tools
IMAGE_INSTALL += "tcpdump"
IMAGE_INSTALL += "net-tools"
IMAGE_INSTALL += "lsof"
IMAGE_INSTALL += "iperf"
+# Add pulseaudio
+IMAGE_INSTALL += "pulseaudio-server libpulsecore libpulsecommon libpulse libpulse-simple pulseaudio-misc pulseaudio-service"
+
+# Add Mplayer
+IMAGE_INSTALL += "mplayer"
+
# Those are necessary to manually create partitions and file systems on the eMMC
IMAGE_INSTALL += "parted"
IMAGE_INSTALL += "e2fsprogs-e2fsck e2fsprogs-mke2fs e2fsprogs-tune2fs e2fsprogs-badblocks libcomerr libss libe2p libext2fs dosfstools"
@@ -106,3 +123,8 @@ IMAGE_INSTALL += "tzdata"
# SWIG
IMAGE_INSTALL += "swig"
+
+# INTEL MCU FW
+IMAGE_INSTALL += "mcu-fw-load"
+IMAGE_INSTALL += "mcu-fw-bin"
+
diff --git a/device-software/meta-edison-distro/recipes-core/ota-update/files/ota-update.sh b/device-software/meta-edison-distro/recipes-core/ota-update/files/ota-update.sh
index 5d00b6d..cfbe8ea 100644
--- a/device-software/meta-edison-distro/recipes-core/ota-update/files/ota-update.sh
+++ b/device-software/meta-edison-distro/recipes-core/ota-update/files/ota-update.sh
@@ -54,7 +54,9 @@ exit_ota_update () {
fi_echo "Rebooting...."
# dump journal to log file
journalctl -u ota-update -o short-iso >> /ota-update.log
- reboot
+ systemctl daemon-reload
+ systemctl stop home.mount
+ systemctl default
}
# continue normal flow or exit on error code
diff --git a/device-software/meta-edison-distro/recipes-core/readline/files/readline-fix-segfault-when-pressing-DEL-key-twice.patch b/device-software/meta-edison-distro/recipes-core/readline/files/readline-fix-segfault-when-pressing-DEL-key-twice.patch
new file mode 100644
index 0000000..4dcaf89
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-core/readline/files/readline-fix-segfault-when-pressing-DEL-key-twice.patch
@@ -0,0 +1,39 @@
+From 8acbcaa6b3d855f3e85e6a108db323278584091e Mon Sep 17 00:00:00 2001
+From: Loic Akue
+Date: Mon, 3 Nov 2014 16:26:42 +0100
+Subject: [PATCH] bug readline
+
+| READLINE PATCH REPORT
+| =====================
+|
+|Readline-Release: 6.3
+|Patch-ID: readline63-002
+|
+|Bug-Reported-by: Anatol Pomozov
+|Bug-Reference-ID:
+|Bug-Reference-URL: http://lists.gnu.org/archive/html/bug-readline/2014-03/msg00010.html
+|
+|Bug-Description:
+|
+|When in callback mode, some readline commands can cause readline to seg
+|fault by passing invalid contexts to callback functions.
+
+Signed-off-by: Loic Akue
+
+diff --git a/readline.c b/readline.c
+index 03eefa6..55c0522 100644
+--- a/readline.c
++++ b/readline.c
+@@ -744,7 +744,8 @@ _rl_dispatch_callback (cxt)
+ r = _rl_subseq_result (r, cxt->oldmap, cxt->okey, (cxt->flags & KSEQ_SUBSEQ));
+
+ RL_CHECK_SIGNALS ();
+- if (r == 0) /* success! */
++ /* We only treat values < 0 specially to simulate recursion. */
++ if (r >= 0 || (r == -1 && (cxt->flags & KSEQ_SUBSEQ) == 0)) /* success! or failure! */
+ {
+ _rl_keyseq_chain_dispose ();
+ RL_UNSETSTATE (RL_STATE_MULTIKEY);
+--
+1.7.9.5
+
diff --git a/device-software/meta-edison-distro/recipes-core/readline/readline_6.3.bbappend b/device-software/meta-edison-distro/recipes-core/readline/readline_6.3.bbappend
new file mode 100644
index 0000000..c8ecc36
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-core/readline/readline_6.3.bbappend
@@ -0,0 +1,4 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+SRC_URI += "\
+ file://readline-fix-segfault-when-pressing-DEL-key-twice.patch \
+ "
diff --git a/device-software/meta-edison-distro/recipes-core/resize-rootfs/files/resize-rootfs.service b/device-software/meta-edison-distro/recipes-core/resize-rootfs/files/resize-rootfs.service
new file mode 100644
index 0000000..708226f
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-core/resize-rootfs/files/resize-rootfs.service
@@ -0,0 +1,14 @@
+[Unit]
+Description=Increases rootfs image size to fit partition
+Requires=dev-disk-by\x2dpartlabel-rootfs.device
+After=dev-disk-by\x2dpartlabel-rootfs.device
+
+[Service]
+Type=oneshot
+ExecStart=/sbin/resize2fs /dev/disk/by-partlabel/rootfs
+ExecStart=/bin/systemctl disable resize-rootfs.service
+
+StandardOutput=journal+console
+
+[Install]
+WantedBy=default.target
diff --git a/device-software/meta-edison-distro/recipes-core/resize-rootfs/resize-rootfs.bb b/device-software/meta-edison-distro/recipes-core/resize-rootfs/resize-rootfs.bb
new file mode 100644
index 0000000..f91e4ba
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-core/resize-rootfs/resize-rootfs.bb
@@ -0,0 +1,24 @@
+DESCRIPTION = "Resize Rootfs systemd service"
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6"
+
+SRC_URI = "file://resize-rootfs.service"
+
+inherit systemd
+
+SYSTEMD_SERVICE_${PN} = "resize-rootfs.service"
+
+RDEPENDS_${PN} = "systemd e2fsprogs-resize2fs"
+
+do_install() {
+ install -d ${D}${systemd_unitdir}/system
+ install -c -m 0644 ${WORKDIR}/resize-rootfs.service ${D}${systemd_unitdir}/system
+}
+
+FILES_${PN} = "${base_libdir}/systemd/system/resize-rootfs.service"
+
+# As this package is tied to systemd, only build it when we're also building systemd.
+python () {
+ if not oe.utils.contains ('DISTRO_FEATURES', 'systemd', True, False, d):
+ raise bb.parse.SkipPackage("'systemd' not in DISTRO_FEATURES")
+}
diff --git a/device-software/meta-edison-distro/recipes-core/systemd/files/edison-machine-id.service b/device-software/meta-edison-distro/recipes-core/systemd/files/edison-machine-id.service
new file mode 100644
index 0000000..3caa836
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-core/systemd/files/edison-machine-id.service
@@ -0,0 +1,14 @@
+[Unit]
+Description= Generate unique machine-id
+After=systemd-remount-fs.service
+
+[Service]
+Type=oneshot
+ExecStartPre=/bin/umount /etc/machine-id
+ExecStart=/bin/systemd-machine-id-setup
+ExecStartPost=/bin/systemctl disable edison-machine-id
+StandardOutput=journal+console
+
+[Install]
+WantedBy=basic.target
+
diff --git a/device-software/meta-edison-distro/recipes-core/systemd/files/hsu-pm-runtime.service b/device-software/meta-edison-distro/recipes-core/systemd/files/hsu-pm-runtime.service
index 1b9f277..e81b6ff 100644
--- a/device-software/meta-edison-distro/recipes-core/systemd/files/hsu-pm-runtime.service
+++ b/device-software/meta-edison-distro/recipes-core/systemd/files/hsu-pm-runtime.service
@@ -6,6 +6,7 @@ After=getty.target
[Service]
Type=oneshot
ExecStart=/bin/sh -c 'echo auto > /sys/devices/pci0000:00/0000:00:04.3/power/control'
+ExecStart=/bin/sh -c 'echo auto > /sys/devices/pci0000:00/0000:00:04.1/power/control'
StandardOutput=null
[Install]
diff --git a/device-software/meta-edison-distro/recipes-core/systemd/files/usb0.network b/device-software/meta-edison-distro/recipes-core/systemd/files/usb0.network
new file mode 100644
index 0000000..b7d1042
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-core/systemd/files/usb0.network
@@ -0,0 +1,6 @@
+[Match]
+Name=usb0
+
+[Network]
+Address=192.168.2.15/24
+
diff --git a/device-software/meta-edison-distro/recipes-core/systemd/systemd_%.bbappend b/device-software/meta-edison-distro/recipes-core/systemd/systemd_%.bbappend
index 23bcc0c..07b6cb2 100644
--- a/device-software/meta-edison-distro/recipes-core/systemd/systemd_%.bbappend
+++ b/device-software/meta-edison-distro/recipes-core/systemd/systemd_%.bbappend
@@ -4,13 +4,15 @@ SRC_URI += "file://journald.conf \
file://system.conf \
file://systemd-reboot-service.patch \
file://hsu-pm-runtime.service \
- file://spi-disable-pm-runtime.service"
+ file://usb0.network \
+ file://edison-machine-id.service"
do_install_append() {
# Push the custom conf files on target
install -m 0644 ${WORKDIR}/journald.conf ${D}${sysconfdir}/systemd
install -m 0644 ${WORKDIR}/system.conf ${D}${sysconfdir}/systemd
install -m 0644 ${WORKDIR}/timesyncd.conf ${D}${sysconfdir}/systemd
+ install -m 0644 ${WORKDIR}/usb0.network ${D}${sysconfdir}/systemd/network
# enable timesyncd service
install -d ${D}${sysconfdir}/systemd/system/sysinit.target.wants
@@ -22,11 +24,11 @@ do_install_append() {
install -m 0644 ${WORKDIR}/hsu-pm-runtime.service \
${D}${systemd_unitdir}/system/hsu-pm-runtime.service
- # enable a custom service to disable the ssp_spi driver's runtime pm
- install -d ${D}${sysconfdir}/systemd/system/default.target.wants
- install -m 0644 ${WORKDIR}/spi-disable-pm-runtime.service \
- ${D}${systemd_unitdir}/system/spi-disable-pm-runtime.service
- ln -sf ${systemd_unitdir}/system/spi-disable-pm-runtime.service \
- ${D}${sysconfdir}/systemd/system/default.target.wants/spi-disable-pm-runtime.service
+ # enable a custom service to provide a persistant machine-id value to Edison
+ install -d ${D}${sysconfdir}/systemd/system/basic.target.wants
+ install -m 0644 ${WORKDIR}/edison-machine-id.service \
+ ${D}${systemd_unitdir}/system/edison-machine-id.service
+ ln -sf ${systemd_unitdir}/system/edison-machine-id.service \
+ ${D}${sysconfdir}/systemd/system/basic.target.wants/edison-machine-id.service
}
diff --git a/device-software/meta-edison-distro/recipes-devtools/e2fsprogs/e2fsprogs_%.bbappend b/device-software/meta-edison-distro/recipes-devtools/e2fsprogs/e2fsprogs_%.bbappend
new file mode 100644
index 0000000..01a6d33
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-devtools/e2fsprogs/e2fsprogs_%.bbappend
@@ -0,0 +1,11 @@
+# Add resize2fs tool
+
+
+EXTRA_OECONF += "\
+ --enable-resizer \
+"
+
+PACKAGES =+ "e2fsprogs-resize2fs"
+
+FILES_e2fsprogs-resize2fs = "${base_sbindir}/resize2fs"
+
diff --git a/device-software/meta-edison-distro/recipes-devtools/swig/swig.inc b/device-software/meta-edison-distro/recipes-devtools/swig/swig.inc
new file mode 100644
index 0000000..5571a55
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-devtools/swig/swig.inc
@@ -0,0 +1,63 @@
+DESCRIPTION = "SWIG - Simplified Wrapper and Interface Generator"
+HOMEPAGE = "http://swig.sourceforge.net/"
+LICENSE = "BSD & GPLv3"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=e7807a6282784a7dde4c846626b08fc6 \
+ file://LICENSE-GPL;md5=d32239bcb673463ab874e80d47fae504 \
+ file://LICENSE-UNIVERSITIES;md5=8ce9dcc8f7c994de4a408b205c72ba08"
+
+SECTION = "devel"
+
+DEPENDS = "libpcre python"
+
+SRC_URI = "${SOURCEFORGE_MIRROR}/${BPN}/${BPN}-${PV}.tar.gz"
+
+inherit autotools pythonnative
+
+EXTRA_OECONF = " \
+ --with-python=${PYTHON} \
+ --without-allegrocl \
+ --without-android \
+ --without-boost \
+ --without-chicken \
+ --without-clisp \
+ --without-csharp \
+ --without-d \
+ --without-gcj \
+ --without-go \
+ --without-guile \
+ --without-java \
+ --without-lua \
+ --without-mzscheme \
+ --without-ocaml \
+ --without-octave \
+ --without-perl5 \
+ --without-pike \
+ --without-php \
+ --without-python3 \
+ --without-r \
+ --without-ruby \
+ --without-tcl \
+"
+
+BBCLASSEXTEND = "native nativesdk"
+
+do_configure() {
+ install -m 0755 ${STAGING_DATADIR_NATIVE}/gnu-config/config.guess ${S}/Tools/config
+ install -m 0755 ${STAGING_DATADIR_NATIVE}/gnu-config/config.sub ${S}/Tools/config
+ install -m 0755 ${STAGING_DATADIR_NATIVE}/gnu-config/config.guess ${S}
+ install -m 0755 ${STAGING_DATADIR_NATIVE}/gnu-config/config.sub ${S}
+ oe_runconf
+}
+
+do_install_append_class-nativesdk() {
+ cd ${D}${bindir}
+ ln -s swig swig2.0
+}
+
+def swiglib_relpath(d):
+ swiglib = d.getVar('datadir', True) + "/" + d.getVar('BPN', True) + "/" + d.getVar('PV', True)
+ return os.path.relpath(swiglib, d.getVar('bindir', True))
+
+do_install_append_class-native() {
+ create_wrapper ${D}${bindir}/swig SWIG_LIB='`dirname $''realpath`'/${@swiglib_relpath(d)}
+}
\ No newline at end of file
diff --git a/device-software/meta-edison-distro/recipes-devtools/swig/swig/0001-Use-proc-self-exe-for-swig-swiglib-on-non-Win32-plat.patch b/device-software/meta-edison-distro/recipes-devtools/swig/swig/0001-Use-proc-self-exe-for-swig-swiglib-on-non-Win32-plat.patch
new file mode 100644
index 0000000..4115469
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-devtools/swig/swig/0001-Use-proc-self-exe-for-swig-swiglib-on-non-Win32-plat.patch
@@ -0,0 +1,56 @@
+---
+ Source/Modules/main.cxx | 24 ++++++++++++++++++++++--
+ 1 file changed, 22 insertions(+), 2 deletions(-)
+
+diff --git a/Source/Modules/main.cxx b/Source/Modules/main.cxx
+index d2f5d3b..cbb0a12 100644
+--- a/Source/Modules/main.cxx
++++ b/Source/Modules/main.cxx
+@@ -26,6 +26,11 @@ char cvsroot_main_cxx[] = "$Id$";
+ #include "cparse.h"
+ #include
+ #include // for INT_MAX
++#ifndef _WIN32
++#include
++#include // for readlink
++#include // for stat
++#endif
+
+ // Global variables
+
+@@ -902,9 +907,9 @@ int SWIG_main(int argc, char *argv[], Language *l) {
+
+ // Check for SWIG_LIB environment variable
+ if ((c = getenv("SWIG_LIB")) == (char *) 0) {
++ char *p;
+ #if defined(_WIN32)
+ char buf[MAX_PATH];
+- char *p;
+ if (!(GetModuleFileName(0, buf, MAX_PATH) == 0 || (p = strrchr(buf, '\\')) == 0)) {
+ *(p + 1) = '\0';
+ SwigLib = NewStringf("%sLib", buf); // Native windows installation path
+@@ -914,7 +919,22 @@ int SWIG_main(int argc, char *argv[], Language *l) {
+ if (Len(SWIG_LIB_WIN_UNIX) > 0)
+ SwigLibWinUnix = NewString(SWIG_LIB_WIN_UNIX); // Unix installation path using a drive letter (for msys/mingw)
+ #else
+- SwigLib = NewString(SWIG_LIB);
++ char buf[PATH_MAX];
++ if (0 < ::readlink("/proc/self/exe", buf, sizeof(buf)) &&
++ (p = ::strstr(buf, "/bin/swig"))) {
++ int major, minor, patch;
++ const int ret = ::sscanf(VERSION, "%d.%d.%d", &major, &minor, &patch);
++ if (3 == ret) {
++ const ::ptrdiff_t dir_part_len = p - buf;
++ ::snprintf(p, PATH_MAX - dir_part_len, "/share/swig/%d.%d.%d", major, minor, patch);
++ struct ::stat stat_res;
++ if (0 == ::stat(buf, &stat_res) && S_ISDIR(stat_res.st_mode)) {
++ SwigLib = NewString(buf);
++ }
++ }
++ }
++ if (NULL == SwigLib)
++ SwigLib = NewString(SWIG_LIB);
+ #endif
+ } else {
+ SwigLib = NewString(c);
+--
diff --git a/device-software/meta-edison-distro/recipes-devtools/swig/swig/0001-configure-use-pkg-config-for-pcre-detection.patch b/device-software/meta-edison-distro/recipes-devtools/swig/swig/0001-configure-use-pkg-config-for-pcre-detection.patch
new file mode 100644
index 0000000..5a05d7b
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-devtools/swig/swig/0001-configure-use-pkg-config-for-pcre-detection.patch
@@ -0,0 +1,55 @@
+---
+ configure.ac | 38 +++++++-------------------------------
+ 1 file changed, 7 insertions(+), 31 deletions(-)
+
+diff --git a/configure.ac b/configure.ac
+index 0c984b7..6edcec1 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -70,38 +70,14 @@ AC_MSG_RESULT([$with_pcre])
+
+ dnl To make configuring easier, check for a locally built PCRE using the Tools/pcre-build.sh script
+ if test x"${with_pcre}" = xyes ; then
+- AC_MSG_CHECKING([whether to use local PCRE])
+- local_pcre_config=no
+- if test -z $PCRE_CONFIG; then
+- if test -f `pwd`/pcre/pcre-swig-install/bin/pcre-config; then
+- PCRE_CONFIG=`pwd`/pcre/pcre-swig-install/bin/pcre-config
+- local_pcre_config=$PCRE_CONFIG
+- fi
+- fi
+- AC_MSG_RESULT([$local_pcre_config])
+-fi
+-AS_IF([test "x$with_pcre" != xno],
+- [AX_PATH_GENERIC([pcre],
+- [], dnl Minimal version of PCRE we need -- accept any
+- [], dnl custom sed script for version parsing is not needed
+- [AC_DEFINE([HAVE_PCRE], [1], [Define if you have PCRE library])
+- LIBS="$LIBS $PCRE_LIBS"
+- CPPFLAGS="$CPPFLAGS $PCRE_CFLAGS"
+- ],
+- [AC_MSG_FAILURE([
+- Cannot find pcre-config script from PCRE (Perl Compatible Regular Expressions)
+- library package. This dependency is needed for configure to complete,
+- Either:
+- - Install the PCRE developer package on your system (preferred approach).
+- - Download the PCRE source tarball, build and install on your system
+- as you would for any package built from source distribution.
+- - Use the Tools/pcre-build.sh script to build PCRE just for SWIG to statically
+- link against. Run 'Tools/pcre-build.sh --help' for instructions.
+- (quite easy and does not require privileges to install PCRE on your system)
+- - Use configure --without-pcre to disable regular expressions support in SWIG
+- (not recommended).])
+- ])
++ PKG_CHECK_MODULES([PCRE], [libpcre], [
++ AC_DEFINE([HAVE_PCRE], [1], [Define if you have PCRE library])
++ LIBS="$LIBS $PCRE_LIBS"
++ CPPFLAGS="$CPPFLAGS $PCRE_CFLAGS"
++ ], [
++ AC_MSG_WARN([$PCRE_PKG_ERRORS])
+ ])
++fi
+
+
+ dnl CCache
+--
diff --git a/device-software/meta-edison-distro/recipes-devtools/swig/swig_3.0.2.bb b/device-software/meta-edison-distro/recipes-devtools/swig/swig_3.0.2.bb
new file mode 100644
index 0000000..ac41914
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-devtools/swig/swig_3.0.2.bb
@@ -0,0 +1,8 @@
+require ${BPN}.inc
+
+SRC_URI += "file://0001-Use-proc-self-exe-for-swig-swiglib-on-non-Win32-plat.patch \
+ file://0001-configure-use-pkg-config-for-pcre-detection.patch \
+ "
+
+SRC_URI[md5sum] = "62f9b0d010cef36a13a010dc530d0d41"
+SRC_URI[sha256sum] = "a2669657cabcedc371f63c0457407a183e0b6b2ef4e7e303c1ec9a3964cc7813"
diff --git a/device-software/meta-edison-distro/recipes-multimedia/alsa/alsa-utils_%.bbappend b/device-software/meta-edison-distro/recipes-multimedia/alsa/alsa-utils_%.bbappend
new file mode 100644
index 0000000..ae82a2b
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-multimedia/alsa/alsa-utils_%.bbappend
@@ -0,0 +1,13 @@
+# Provide default alsa configuration for Edison
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files/"
+
+SRC_URI += "\
+ file://asound.state \
+"
+
+do_install_append() {
+ install -v -d ${D}/var/lib/alsa/
+ install -m 644 ${WORKDIR}/asound.state ${D}/var/lib/alsa/
+}
+
diff --git a/device-software/meta-edison-distro/recipes-multimedia/alsa/files/asound.state b/device-software/meta-edison-distro/recipes-multimedia/alsa/files/asound.state
new file mode 100644
index 0000000..18aa6e2
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-multimedia/alsa/files/asound.state
@@ -0,0 +1,14141 @@
+state.wm8958audio {
+ control.1 {
+ iface MIXER
+ name 'ssp1_out mux 0'
+ value fm
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 fm
+ item.1 bt
+ }
+ }
+ control.2 {
+ iface MIXER
+ name 'aware_out aware 0 switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.3 {
+ iface MIXER
+ name 'modem_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.4 {
+ iface MIXER
+ name 'modem_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.5 {
+ iface MIXER
+ name 'modem_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.6 {
+ iface MIXER
+ name 'modem_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.7 {
+ iface MIXER
+ name 'modem_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.8 {
+ iface MIXER
+ name 'modem_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.9 {
+ iface MIXER
+ name 'modem_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.10 {
+ iface MIXER
+ name 'modem_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.11 {
+ iface MIXER
+ name 'modem_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.12 {
+ iface MIXER
+ name 'modem_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.13 {
+ iface MIXER
+ name 'modem_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.14 {
+ iface MIXER
+ name 'modem_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.15 {
+ iface MIXER
+ name 'modem_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.16 {
+ iface MIXER
+ name 'modem_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.17 {
+ iface MIXER
+ name 'modem_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.18 {
+ iface MIXER
+ name 'modem_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.19 {
+ iface MIXER
+ name 'fm_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.20 {
+ iface MIXER
+ name 'fm_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.21 {
+ iface MIXER
+ name 'fm_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.22 {
+ iface MIXER
+ name 'fm_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.23 {
+ iface MIXER
+ name 'fm_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.24 {
+ iface MIXER
+ name 'fm_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.25 {
+ iface MIXER
+ name 'fm_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.26 {
+ iface MIXER
+ name 'fm_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.27 {
+ iface MIXER
+ name 'fm_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.28 {
+ iface MIXER
+ name 'fm_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.29 {
+ iface MIXER
+ name 'fm_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.30 {
+ iface MIXER
+ name 'fm_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.31 {
+ iface MIXER
+ name 'fm_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.32 {
+ iface MIXER
+ name 'fm_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.33 {
+ iface MIXER
+ name 'fm_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.34 {
+ iface MIXER
+ name 'fm_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.35 {
+ iface MIXER
+ name 'bt_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.36 {
+ iface MIXER
+ name 'bt_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.37 {
+ iface MIXER
+ name 'bt_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.38 {
+ iface MIXER
+ name 'bt_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.39 {
+ iface MIXER
+ name 'bt_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.40 {
+ iface MIXER
+ name 'bt_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.41 {
+ iface MIXER
+ name 'bt_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.42 {
+ iface MIXER
+ name 'bt_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.43 {
+ iface MIXER
+ name 'bt_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.44 {
+ iface MIXER
+ name 'bt_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
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+ name 'bt_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.46 {
+ iface MIXER
+ name 'bt_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.47 {
+ iface MIXER
+ name 'bt_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.48 {
+ iface MIXER
+ name 'bt_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.49 {
+ iface MIXER
+ name 'bt_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.50 {
+ iface MIXER
+ name 'bt_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.51 {
+ iface MIXER
+ name 'codec_out1 mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.52 {
+ iface MIXER
+ name 'codec_out1 mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.53 {
+ iface MIXER
+ name 'codec_out1 mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.54 {
+ iface MIXER
+ name 'codec_out1 mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.55 {
+ iface MIXER
+ name 'codec_out1 mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.56 {
+ iface MIXER
+ name 'codec_out1 mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.57 {
+ iface MIXER
+ name 'codec_out1 mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.58 {
+ iface MIXER
+ name 'codec_out1 mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.59 {
+ iface MIXER
+ name 'codec_out1 mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.60 {
+ iface MIXER
+ name 'codec_out1 mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.61 {
+ iface MIXER
+ name 'codec_out1 mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.62 {
+ iface MIXER
+ name 'codec_out1 mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.63 {
+ iface MIXER
+ name 'codec_out1 mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.64 {
+ iface MIXER
+ name 'codec_out1 mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.65 {
+ iface MIXER
+ name 'codec_out1 mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.66 {
+ iface MIXER
+ name 'codec_out1 mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.67 {
+ iface MIXER
+ name 'codec_out0 mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.68 {
+ iface MIXER
+ name 'codec_out0 mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.69 {
+ iface MIXER
+ name 'codec_out0 mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.70 {
+ iface MIXER
+ name 'codec_out0 mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.71 {
+ iface MIXER
+ name 'codec_out0 mix 0 sprot_loop_in'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.72 {
+ iface MIXER
+ name 'codec_out0 mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.73 {
+ iface MIXER
+ name 'codec_out0 mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.74 {
+ iface MIXER
+ name 'codec_out0 mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.75 {
+ iface MIXER
+ name 'codec_out0 mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.76 {
+ iface MIXER
+ name 'codec_out0 mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.77 {
+ iface MIXER
+ name 'codec_out0 mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.78 {
+ iface MIXER
+ name 'codec_out0 mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.79 {
+ iface MIXER
+ name 'codec_out0 mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.80 {
+ iface MIXER
+ name 'codec_out0 mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.81 {
+ iface MIXER
+ name 'codec_out0 mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.82 {
+ iface MIXER
+ name 'codec_out0 mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.83 {
+ iface MIXER
+ name 'rxspeech_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.84 {
+ iface MIXER
+ name 'rxspeech_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.85 {
+ iface MIXER
+ name 'rxspeech_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.86 {
+ iface MIXER
+ name 'rxspeech_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.87 {
+ iface MIXER
+ name 'rxspeech_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.88 {
+ iface MIXER
+ name 'rxspeech_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.89 {
+ iface MIXER
+ name 'rxspeech_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.90 {
+ iface MIXER
+ name 'rxspeech_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.91 {
+ iface MIXER
+ name 'rxspeech_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.92 {
+ iface MIXER
+ name 'rxspeech_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.93 {
+ iface MIXER
+ name 'rxspeech_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.94 {
+ iface MIXER
+ name 'rxspeech_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.95 {
+ iface MIXER
+ name 'rxspeech_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.96 {
+ iface MIXER
+ name 'rxspeech_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.97 {
+ iface MIXER
+ name 'rxspeech_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.98 {
+ iface MIXER
+ name 'rxspeech_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.99 {
+ iface MIXER
+ name 'speech_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.100 {
+ iface MIXER
+ name 'speech_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.101 {
+ iface MIXER
+ name 'speech_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.102 {
+ iface MIXER
+ name 'speech_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.103 {
+ iface MIXER
+ name 'speech_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.104 {
+ iface MIXER
+ name 'speech_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.105 {
+ iface MIXER
+ name 'speech_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.106 {
+ iface MIXER
+ name 'speech_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.107 {
+ iface MIXER
+ name 'speech_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.108 {
+ iface MIXER
+ name 'speech_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.109 {
+ iface MIXER
+ name 'speech_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.110 {
+ iface MIXER
+ name 'speech_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.111 {
+ iface MIXER
+ name 'speech_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.112 {
+ iface MIXER
+ name 'speech_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.113 {
+ iface MIXER
+ name 'speech_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.114 {
+ iface MIXER
+ name 'speech_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.115 {
+ iface MIXER
+ name 'hf_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.116 {
+ iface MIXER
+ name 'hf_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.117 {
+ iface MIXER
+ name 'hf_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.118 {
+ iface MIXER
+ name 'hf_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.119 {
+ iface MIXER
+ name 'hf_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.120 {
+ iface MIXER
+ name 'hf_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.121 {
+ iface MIXER
+ name 'hf_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.122 {
+ iface MIXER
+ name 'hf_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.123 {
+ iface MIXER
+ name 'hf_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.124 {
+ iface MIXER
+ name 'hf_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.125 {
+ iface MIXER
+ name 'hf_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.126 {
+ iface MIXER
+ name 'hf_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.127 {
+ iface MIXER
+ name 'hf_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.128 {
+ iface MIXER
+ name 'hf_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.129 {
+ iface MIXER
+ name 'hf_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.130 {
+ iface MIXER
+ name 'hf_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.131 {
+ iface MIXER
+ name 'hf_sns_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.132 {
+ iface MIXER
+ name 'hf_sns_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.133 {
+ iface MIXER
+ name 'hf_sns_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.134 {
+ iface MIXER
+ name 'hf_sns_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.135 {
+ iface MIXER
+ name 'hf_sns_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.136 {
+ iface MIXER
+ name 'hf_sns_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.137 {
+ iface MIXER
+ name 'hf_sns_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.138 {
+ iface MIXER
+ name 'hf_sns_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.139 {
+ iface MIXER
+ name 'hf_sns_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.140 {
+ iface MIXER
+ name 'hf_sns_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.141 {
+ iface MIXER
+ name 'hf_sns_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.142 {
+ iface MIXER
+ name 'hf_sns_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.143 {
+ iface MIXER
+ name 'hf_sns_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.144 {
+ iface MIXER
+ name 'hf_sns_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.145 {
+ iface MIXER
+ name 'hf_sns_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.146 {
+ iface MIXER
+ name 'hf_sns_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.147 {
+ iface MIXER
+ name 'vad_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.148 {
+ iface MIXER
+ name 'vad_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.149 {
+ iface MIXER
+ name 'vad_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.150 {
+ iface MIXER
+ name 'vad_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.151 {
+ iface MIXER
+ name 'vad_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.152 {
+ iface MIXER
+ name 'vad_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.153 {
+ iface MIXER
+ name 'vad_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.154 {
+ iface MIXER
+ name 'vad_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.155 {
+ iface MIXER
+ name 'vad_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.156 {
+ iface MIXER
+ name 'vad_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.157 {
+ iface MIXER
+ name 'vad_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.158 {
+ iface MIXER
+ name 'vad_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.159 {
+ iface MIXER
+ name 'vad_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.160 {
+ iface MIXER
+ name 'vad_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.161 {
+ iface MIXER
+ name 'vad_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.162 {
+ iface MIXER
+ name 'vad_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.163 {
+ iface MIXER
+ name 'aware_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.164 {
+ iface MIXER
+ name 'aware_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.165 {
+ iface MIXER
+ name 'aware_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.166 {
+ iface MIXER
+ name 'aware_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.167 {
+ iface MIXER
+ name 'aware_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.168 {
+ iface MIXER
+ name 'aware_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.169 {
+ iface MIXER
+ name 'aware_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.170 {
+ iface MIXER
+ name 'aware_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.171 {
+ iface MIXER
+ name 'aware_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.172 {
+ iface MIXER
+ name 'aware_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.173 {
+ iface MIXER
+ name 'aware_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.174 {
+ iface MIXER
+ name 'aware_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.175 {
+ iface MIXER
+ name 'aware_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.176 {
+ iface MIXER
+ name 'aware_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.177 {
+ iface MIXER
+ name 'aware_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.178 {
+ iface MIXER
+ name 'aware_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.179 {
+ iface MIXER
+ name 'voip_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.180 {
+ iface MIXER
+ name 'voip_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.181 {
+ iface MIXER
+ name 'voip_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.182 {
+ iface MIXER
+ name 'voip_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.183 {
+ iface MIXER
+ name 'voip_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.184 {
+ iface MIXER
+ name 'voip_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.185 {
+ iface MIXER
+ name 'voip_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.186 {
+ iface MIXER
+ name 'voip_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.187 {
+ iface MIXER
+ name 'voip_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.188 {
+ iface MIXER
+ name 'voip_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.189 {
+ iface MIXER
+ name 'voip_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.190 {
+ iface MIXER
+ name 'voip_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.191 {
+ iface MIXER
+ name 'voip_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.192 {
+ iface MIXER
+ name 'voip_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.193 {
+ iface MIXER
+ name 'voip_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.194 {
+ iface MIXER
+ name 'voip_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.195 {
+ iface MIXER
+ name 'media_loop2_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.196 {
+ iface MIXER
+ name 'media_loop2_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.197 {
+ iface MIXER
+ name 'media_loop2_out mix 0 codec_in0'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.198 {
+ iface MIXER
+ name 'media_loop2_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.199 {
+ iface MIXER
+ name 'media_loop2_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.200 {
+ iface MIXER
+ name 'media_loop2_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.201 {
+ iface MIXER
+ name 'media_loop2_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.202 {
+ iface MIXER
+ name 'media_loop2_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.203 {
+ iface MIXER
+ name 'media_loop2_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.204 {
+ iface MIXER
+ name 'media_loop2_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.205 {
+ iface MIXER
+ name 'media_loop2_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.206 {
+ iface MIXER
+ name 'media_loop2_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.207 {
+ iface MIXER
+ name 'media_loop2_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.208 {
+ iface MIXER
+ name 'media_loop2_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.209 {
+ iface MIXER
+ name 'media_loop2_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.210 {
+ iface MIXER
+ name 'media_loop2_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.211 {
+ iface MIXER
+ name 'media_loop1_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.212 {
+ iface MIXER
+ name 'media_loop1_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.213 {
+ iface MIXER
+ name 'media_loop1_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.214 {
+ iface MIXER
+ name 'media_loop1_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.215 {
+ iface MIXER
+ name 'media_loop1_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.216 {
+ iface MIXER
+ name 'media_loop1_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.217 {
+ iface MIXER
+ name 'media_loop1_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.218 {
+ iface MIXER
+ name 'media_loop1_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.219 {
+ iface MIXER
+ name 'media_loop1_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.220 {
+ iface MIXER
+ name 'media_loop1_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.221 {
+ iface MIXER
+ name 'media_loop1_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.222 {
+ iface MIXER
+ name 'media_loop1_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.223 {
+ iface MIXER
+ name 'media_loop1_out mix 0 pcm0_in'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.224 {
+ iface MIXER
+ name 'media_loop1_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.225 {
+ iface MIXER
+ name 'media_loop1_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.226 {
+ iface MIXER
+ name 'media_loop1_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.227 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.228 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.229 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.230 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.231 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.232 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 media_loop1_in'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.233 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.234 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.235 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.236 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.237 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.238 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.239 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.240 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.241 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.242 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.243 {
+ iface MIXER
+ name 'pcm2_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.244 {
+ iface MIXER
+ name 'pcm2_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.245 {
+ iface MIXER
+ name 'pcm2_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.246 {
+ iface MIXER
+ name 'pcm2_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.247 {
+ iface MIXER
+ name 'pcm2_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.248 {
+ iface MIXER
+ name 'pcm2_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.249 {
+ iface MIXER
+ name 'pcm2_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.250 {
+ iface MIXER
+ name 'pcm2_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.251 {
+ iface MIXER
+ name 'pcm2_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.252 {
+ iface MIXER
+ name 'pcm2_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.253 {
+ iface MIXER
+ name 'pcm2_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.254 {
+ iface MIXER
+ name 'pcm2_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.255 {
+ iface MIXER
+ name 'pcm2_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.256 {
+ iface MIXER
+ name 'pcm2_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.257 {
+ iface MIXER
+ name 'pcm2_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.258 {
+ iface MIXER
+ name 'pcm2_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.259 {
+ iface MIXER
+ name 'pcm1_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.260 {
+ iface MIXER
+ name 'pcm1_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.261 {
+ iface MIXER
+ name 'pcm1_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.262 {
+ iface MIXER
+ name 'pcm1_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.263 {
+ iface MIXER
+ name 'pcm1_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.264 {
+ iface MIXER
+ name 'pcm1_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.265 {
+ iface MIXER
+ name 'pcm1_out mix 0 media_loop2_in'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.266 {
+ iface MIXER
+ name 'pcm1_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.267 {
+ iface MIXER
+ name 'pcm1_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.268 {
+ iface MIXER
+ name 'pcm1_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.269 {
+ iface MIXER
+ name 'pcm1_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.270 {
+ iface MIXER
+ name 'pcm1_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.271 {
+ iface MIXER
+ name 'pcm1_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.272 {
+ iface MIXER
+ name 'pcm1_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.273 {
+ iface MIXER
+ name 'pcm1_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.274 {
+ iface MIXER
+ name 'pcm1_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.275 {
+ iface MIXER
+ name 'pcm0_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.276 {
+ iface MIXER
+ name 'pcm0_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.277 {
+ iface MIXER
+ name 'pcm0_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.278 {
+ iface MIXER
+ name 'pcm0_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.279 {
+ iface MIXER
+ name 'pcm0_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.280 {
+ iface MIXER
+ name 'pcm0_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.281 {
+ iface MIXER
+ name 'pcm0_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.282 {
+ iface MIXER
+ name 'pcm0_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.283 {
+ iface MIXER
+ name 'pcm0_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.284 {
+ iface MIXER
+ name 'pcm0_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.285 {
+ iface MIXER
+ name 'pcm0_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.286 {
+ iface MIXER
+ name 'pcm0_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.287 {
+ iface MIXER
+ name 'pcm0_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.288 {
+ iface MIXER
+ name 'pcm0_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.289 {
+ iface MIXER
+ name 'pcm0_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.290 {
+ iface MIXER
+ name 'pcm0_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.291 {
+ iface MIXER
+ name 'media1_out mix 0 media0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.292 {
+ iface MIXER
+ name 'media1_out mix 0 media1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.293 {
+ iface MIXER
+ name 'media1_out mix 0 media2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.294 {
+ iface MIXER
+ name 'media1_out mix 0 media3_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.295 {
+ iface MIXER
+ name 'media0_out mix 0 media0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.296 {
+ iface MIXER
+ name 'media0_out mix 0 media1_in'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.297 {
+ iface MIXER
+ name 'media0_out mix 0 media2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.298 {
+ iface MIXER
+ name 'media0_out mix 0 media3_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.299 {
+ iface MIXER
+ name 'media0_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.300 {
+ iface MIXER
+ name 'media0_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.301 {
+ iface MIXER
+ name 'media0_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.302 {
+ iface MIXER
+ name 'media1_in gain 0 rampduration'
+ value 50
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.303 {
+ iface MIXER
+ name 'media1_in gain 0 mute'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.304 {
+ iface MIXER
+ name 'media1_in gain 0 volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.305 {
+ iface MIXER
+ name 'media2_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.306 {
+ iface MIXER
+ name 'media2_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.307 {
+ iface MIXER
+ name 'media2_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.308 {
+ iface MIXER
+ name 'media3_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.309 {
+ iface MIXER
+ name 'media3_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.310 {
+ iface MIXER
+ name 'media3_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.311 {
+ iface MIXER
+ name 'pcm0_in gain 0 rampduration'
+ value 50
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.312 {
+ iface MIXER
+ name 'pcm0_in gain 0 mute'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.313 {
+ iface MIXER
+ name 'pcm0_in gain 0 volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.314 {
+ iface MIXER
+ name 'pcm1_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.315 {
+ iface MIXER
+ name 'pcm1_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.316 {
+ iface MIXER
+ name 'pcm1_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.317 {
+ iface MIXER
+ name 'low_pcm0_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.318 {
+ iface MIXER
+ name 'low_pcm0_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.319 {
+ iface MIXER
+ name 'low_pcm0_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.320 {
+ iface MIXER
+ name 'pcm1_out gain 0 rampduration'
+ value 50
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.321 {
+ iface MIXER
+ name 'pcm1_out gain 0 mute'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.322 {
+ iface MIXER
+ name 'pcm1_out gain 0 volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.323 {
+ iface MIXER
+ name 'pcm2_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.324 {
+ iface MIXER
+ name 'pcm2_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.325 {
+ iface MIXER
+ name 'pcm2_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.326 {
+ iface MIXER
+ name 'voip_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.327 {
+ iface MIXER
+ name 'voip_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.328 {
+ iface MIXER
+ name 'voip_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.329 {
+ iface MIXER
+ name 'voip_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.330 {
+ iface MIXER
+ name 'voip_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.331 {
+ iface MIXER
+ name 'voip_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.332 {
+ iface MIXER
+ name 'tone_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.333 {
+ iface MIXER
+ name 'tone_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.334 {
+ iface MIXER
+ name 'tone_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.335 {
+ iface MIXER
+ name 'aware_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.336 {
+ iface MIXER
+ name 'aware_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.337 {
+ iface MIXER
+ name 'aware_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.338 {
+ iface MIXER
+ name 'vad_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.339 {
+ iface MIXER
+ name 'vad_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.340 {
+ iface MIXER
+ name 'vad_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.341 {
+ iface MIXER
+ name 'hf_sns_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.342 {
+ iface MIXER
+ name 'hf_sns_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.343 {
+ iface MIXER
+ name 'hf_sns_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.344 {
+ iface MIXER
+ name 'hf_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.345 {
+ iface MIXER
+ name 'hf_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.346 {
+ iface MIXER
+ name 'hf_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.347 {
+ iface MIXER
+ name 'speech_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.348 {
+ iface MIXER
+ name 'speech_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.349 {
+ iface MIXER
+ name 'speech_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.350 {
+ iface MIXER
+ name 'txspeech_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.351 {
+ iface MIXER
+ name 'txspeech_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.352 {
+ iface MIXER
+ name 'txspeech_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.353 {
+ iface MIXER
+ name 'rxspeech_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.354 {
+ iface MIXER
+ name 'rxspeech_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.355 {
+ iface MIXER
+ name 'rxspeech_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.356 {
+ iface MIXER
+ name 'speech_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.357 {
+ iface MIXER
+ name 'speech_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.358 {
+ iface MIXER
+ name 'speech_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.359 {
+ iface MIXER
+ name 'codec_in0 gain 0 rampduration'
+ value 50
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.360 {
+ iface MIXER
+ name 'codec_in0 gain 0 mute'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.361 {
+ iface MIXER
+ name 'codec_in0 gain 0 volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.362 {
+ iface MIXER
+ name 'codec_in1 gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.363 {
+ iface MIXER
+ name 'codec_in1 gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.364 {
+ iface MIXER
+ name 'codec_in1 gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.365 {
+ iface MIXER
+ name 'codec_out0 gain 0 rampduration'
+ value 50
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.366 {
+ iface MIXER
+ name 'codec_out0 gain 0 mute'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.367 {
+ iface MIXER
+ name 'codec_out0 gain 0 volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.368 {
+ iface MIXER
+ name 'codec_out1 gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.369 {
+ iface MIXER
+ name 'codec_out1 gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.370 {
+ iface MIXER
+ name 'codec_out1 gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.371 {
+ iface MIXER
+ name 'bt_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.372 {
+ iface MIXER
+ name 'bt_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.373 {
+ iface MIXER
+ name 'bt_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.374 {
+ iface MIXER
+ name 'fm_out gain 0 rampduration'
+ value 5
+ comment {
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+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.459 {
+ iface MIXER
+ name 'probe out1 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.460 {
+ iface MIXER
+ name 'probe out2 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.461 {
+ iface MIXER
+ name 'probe out3 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.462 {
+ iface MIXER
+ name 'probe out4 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.463 {
+ iface MIXER
+ name 'probe out5 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.464 {
+ iface MIXER
+ name 'probe out6 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.465 {
+ iface MIXER
+ name 'probe out7 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.466 {
+ iface MIXER
+ name 'probe in0 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.467 {
+ iface MIXER
+ name 'probe in1 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.468 {
+ iface MIXER
+ name 'probe in2 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.469 {
+ iface MIXER
+ name 'probe in3 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.470 {
+ iface MIXER
+ name 'probe in4 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.471 {
+ iface MIXER
+ name 'probe in5 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.472 {
+ iface MIXER
+ name 'probe in6 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.473 {
+ iface MIXER
+ name 'probe in7 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.474 {
+ iface MIXER
+ name 'AIF1.1 DRC'
+ value '00980845000000000000'
+ comment {
+ access 'read write'
+ type BYTES
+ count 10
+ }
+ }
+ control.475 {
+ iface MIXER
+ name 'AIF1.2 DRC'
+ value '00980845000000000000'
+ comment {
+ access 'read write'
+ type BYTES
+ count 10
+ }
+ }
+ control.476 {
+ iface MIXER
+ name 'AIF2 DRC'
+ value '00980845000000000000'
+ comment {
+ access 'read write'
+ type BYTES
+ count 10
+ }
+ }
+ control.477 {
+ iface MIXER
+ name 'AIF1DAC1 EQ1 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.478 {
+ iface MIXER
+ name 'AIF1DAC1 EQ2 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.479 {
+ iface MIXER
+ name 'AIF1DAC1 EQ3 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.480 {
+ iface MIXER
+ name 'AIF1DAC1 EQ4 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.481 {
+ iface MIXER
+ name 'AIF1DAC1 EQ5 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.482 {
+ iface MIXER
+ name 'AIF1DAC2 EQ1 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.483 {
+ iface MIXER
+ name 'AIF1DAC2 EQ2 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.484 {
+ iface MIXER
+ name 'AIF1DAC2 EQ3 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.485 {
+ iface MIXER
+ name 'AIF1DAC2 EQ4 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.486 {
+ iface MIXER
+ name 'AIF1DAC2 EQ5 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.487 {
+ iface MIXER
+ name 'AIF2 EQ1 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.488 {
+ iface MIXER
+ name 'AIF2 EQ2 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.489 {
+ iface MIXER
+ name 'AIF2 EQ3 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.490 {
+ iface MIXER
+ name 'AIF2 EQ4 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.491 {
+ iface MIXER
+ name 'AIF2 EQ5 Volume'
+ value 12
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1200
+ dbmax 1900
+ dbvalue.0 0
+ }
+ }
+ control.492 {
+ iface MIXER
+ name 'IN1L Volume'
+ value 11
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1650
+ dbmax 3000
+ dbvalue.0 0
+ }
+ }
+ control.493 {
+ iface MIXER
+ name 'IN1L Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.494 {
+ iface MIXER
+ name 'IN1L ZC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.495 {
+ iface MIXER
+ name 'IN1R Volume'
+ value 11
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1650
+ dbmax 3000
+ dbvalue.0 0
+ }
+ }
+ control.496 {
+ iface MIXER
+ name 'IN1R Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.497 {
+ iface MIXER
+ name 'IN1R ZC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.498 {
+ iface MIXER
+ name 'IN2L Volume'
+ value 11
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1650
+ dbmax 3000
+ dbvalue.0 0
+ }
+ }
+ control.499 {
+ iface MIXER
+ name 'IN2L Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.500 {
+ iface MIXER
+ name 'IN2L ZC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.501 {
+ iface MIXER
+ name 'IN2R Volume'
+ value 11
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 31'
+ dbmin -1650
+ dbmax 3000
+ dbvalue.0 0
+ }
+ }
+ control.502 {
+ iface MIXER
+ name 'IN2R Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.503 {
+ iface MIXER
+ name 'IN2R ZC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.504 {
+ iface MIXER
+ name 'MIXINL IN2L Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin 0
+ dbmax 3000
+ dbvalue.0 0
+ }
+ }
+ control.505 {
+ iface MIXER
+ name 'MIXINL IN1L Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin 0
+ dbmax 3000
+ dbvalue.0 0
+ }
+ }
+ control.506 {
+ iface MIXER
+ name 'MIXINL Output Record Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -9999999
+ dbmax 600
+ dbvalue.0 -9999999
+ }
+ }
+ control.507 {
+ iface MIXER
+ name 'MIXINL IN1LP Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -9999999
+ dbmax 600
+ dbvalue.0 -9999999
+ }
+ }
+ control.508 {
+ iface MIXER
+ name 'MIXINL Direct Voice Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 6'
+ dbmin -9999999
+ dbmax 300
+ dbvalue.0 -9999999
+ }
+ }
+ control.509 {
+ iface MIXER
+ name 'MIXINR IN2R Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin 0
+ dbmax 3000
+ dbvalue.0 0
+ }
+ }
+ control.510 {
+ iface MIXER
+ name 'MIXINR IN1R Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin 0
+ dbmax 3000
+ dbvalue.0 0
+ }
+ }
+ control.511 {
+ iface MIXER
+ name 'MIXINR Output Record Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -9999999
+ dbmax 600
+ dbvalue.0 -9999999
+ }
+ }
+ control.512 {
+ iface MIXER
+ name 'MIXINR IN1RP Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -9999999
+ dbmax 600
+ dbvalue.0 -9999999
+ }
+ }
+ control.513 {
+ iface MIXER
+ name 'MIXINR Direct Voice Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 6'
+ dbmin -9999999
+ dbmax 300
+ dbvalue.0 -9999999
+ }
+ }
+ control.514 {
+ iface MIXER
+ name 'Left Output Mixer IN2RN Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.515 {
+ iface MIXER
+ name 'Left Output Mixer IN2LN Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.516 {
+ iface MIXER
+ name 'Left Output Mixer IN2LP Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.517 {
+ iface MIXER
+ name 'Left Output Mixer IN1L Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.518 {
+ iface MIXER
+ name 'Left Output Mixer IN1R Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.519 {
+ iface MIXER
+ name 'Left Output Mixer Right Input Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.520 {
+ iface MIXER
+ name 'Left Output Mixer Left Input Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.521 {
+ iface MIXER
+ name 'Left Output Mixer DAC Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.522 {
+ iface MIXER
+ name 'Right Output Mixer IN2LN Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.523 {
+ iface MIXER
+ name 'Right Output Mixer IN2RN Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.524 {
+ iface MIXER
+ name 'Right Output Mixer IN1L Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.525 {
+ iface MIXER
+ name 'Right Output Mixer IN1R Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.526 {
+ iface MIXER
+ name 'Right Output Mixer IN2RP Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.527 {
+ iface MIXER
+ name 'Right Output Mixer Left Input Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.528 {
+ iface MIXER
+ name 'Right Output Mixer Right Input Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.529 {
+ iface MIXER
+ name 'Right Output Mixer DAC Volume'
+ value 7
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -2100
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.530 {
+ iface MIXER
+ name 'Output Volume'
+ value.0 57
+ value.1 57
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 63'
+ dbmin -5700
+ dbmax 600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.531 {
+ iface MIXER
+ name 'Output Switch'
+ value.0 true
+ value.1 true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.532 {
+ iface MIXER
+ name 'Output ZC Switch'
+ value.0 true
+ value.1 true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.533 {
+ iface MIXER
+ name 'Earpiece Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.534 {
+ iface MIXER
+ name 'Earpiece Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -600
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.535 {
+ iface MIXER
+ name 'SPKL Input Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -300
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.536 {
+ iface MIXER
+ name 'SPKL IN1LP Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -300
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.537 {
+ iface MIXER
+ name 'SPKL Output Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -300
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.538 {
+ iface MIXER
+ name 'SPKR Input Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -300
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.539 {
+ iface MIXER
+ name 'SPKR IN1RP Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -300
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.540 {
+ iface MIXER
+ name 'SPKR Output Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -300
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.541 {
+ iface MIXER
+ name 'Speaker Mixer Volume'
+ value.0 3
+ value.1 3
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 3'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.542 {
+ iface MIXER
+ name 'Speaker Volume'
+ value.0 57
+ value.1 57
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 63'
+ dbmin -5700
+ dbmax 600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.543 {
+ iface MIXER
+ name 'Speaker Switch'
+ value.0 true
+ value.1 true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.544 {
+ iface MIXER
+ name 'Speaker ZC Switch'
+ value.0 true
+ value.1 true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.545 {
+ iface MIXER
+ name 'Speaker Boost Volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 7'
+ dbmin 0
+ dbmax 1200
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.546 {
+ iface MIXER
+ name 'Speaker Reference'
+ value SPKVDD/2
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 SPKVDD/2
+ item.1 VMID
+ }
+ }
+ control.547 {
+ iface MIXER
+ name 'Speaker Mode'
+ value 'Class D'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'Class D'
+ item.1 'Class AB'
+ }
+ }
+ control.548 {
+ iface MIXER
+ name 'Headphone Volume'
+ value.0 45
+ value.1 45
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 63'
+ dbmin -5700
+ dbmax 600
+ dbvalue.0 -1200
+ dbvalue.1 -1200
+ }
+ }
+ control.549 {
+ iface MIXER
+ name 'Headphone Switch'
+ value.0 true
+ value.1 true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.550 {
+ iface MIXER
+ name 'Headphone ZC Switch'
+ value.0 true
+ value.1 true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.551 {
+ iface MIXER
+ name 'LINEOUT1N Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.552 {
+ iface MIXER
+ name 'LINEOUT1P Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.553 {
+ iface MIXER
+ name 'LINEOUT1 Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -600
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.554 {
+ iface MIXER
+ name 'LINEOUT2N Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.555 {
+ iface MIXER
+ name 'LINEOUT2P Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.556 {
+ iface MIXER
+ name 'LINEOUT2 Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -600
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.557 {
+ iface MIXER
+ name 'AIF1ADC1 Volume'
+ value.0 110
+ value.1 110
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 120'
+ dbmin -9999999
+ dbmax 1800
+ dbvalue.0 1050
+ dbvalue.1 1050
+ }
+ }
+ control.558 {
+ iface MIXER
+ name 'AIF1ADC2 Volume'
+ value.0 96
+ value.1 96
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 120'
+ dbmin -9999999
+ dbmax 1800
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.559 {
+ iface MIXER
+ name 'AIF2ADC Volume'
+ value.0 96
+ value.1 96
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 120'
+ dbmin -9999999
+ dbmax 1800
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.560 {
+ iface MIXER
+ name 'AIF1ADCL Source'
+ value Left
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 Left
+ item.1 Right
+ }
+ }
+ control.561 {
+ iface MIXER
+ name 'AIF1ADCR Source'
+ value Right
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 Left
+ item.1 Right
+ }
+ }
+ control.562 {
+ iface MIXER
+ name 'AIF2ADCL Source'
+ value Left
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 Left
+ item.1 Right
+ }
+ }
+ control.563 {
+ iface MIXER
+ name 'AIF2ADCR Source'
+ value Right
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 Left
+ item.1 Right
+ }
+ }
+ control.564 {
+ iface MIXER
+ name 'AIF1DACL Source'
+ value Left
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 Left
+ item.1 Right
+ }
+ }
+ control.565 {
+ iface MIXER
+ name 'AIF1DACR Source'
+ value Right
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 Left
+ item.1 Right
+ }
+ }
+ control.566 {
+ iface MIXER
+ name 'AIF2DACL Source'
+ value Left
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 Left
+ item.1 Right
+ }
+ }
+ control.567 {
+ iface MIXER
+ name 'AIF2DACR Source'
+ value Right
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 Left
+ item.1 Right
+ }
+ }
+ control.568 {
+ iface MIXER
+ name 'AIF1DAC1 Volume'
+ value.0 96
+ value.1 96
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 96'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.569 {
+ iface MIXER
+ name 'AIF1DAC2 Volume'
+ value.0 96
+ value.1 96
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 96'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.570 {
+ iface MIXER
+ name 'AIF2DAC Volume'
+ value.0 96
+ value.1 96
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 96'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.571 {
+ iface MIXER
+ name 'AIF1 Boost Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 3'
+ dbmin 0
+ dbmax 1800
+ dbvalue.0 0
+ }
+ }
+ control.572 {
+ iface MIXER
+ name 'AIF2 Boost Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 3'
+ dbmin 0
+ dbmax 1800
+ dbvalue.0 0
+ }
+ }
+ control.573 {
+ iface MIXER
+ name 'AIF1DAC1 EQ Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.574 {
+ iface MIXER
+ name 'AIF1DAC2 EQ Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.575 {
+ iface MIXER
+ name 'AIF2 EQ Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.576 {
+ iface MIXER
+ name 'AIF1DAC1 DRC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.577 {
+ iface MIXER
+ name 'AIF1ADC1L DRC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.578 {
+ iface MIXER
+ name 'AIF1ADC1R DRC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.579 {
+ iface MIXER
+ name 'AIF1DAC2 DRC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.580 {
+ iface MIXER
+ name 'AIF1ADC2L DRC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.581 {
+ iface MIXER
+ name 'AIF1ADC2R DRC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.582 {
+ iface MIXER
+ name 'AIF2DAC DRC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.583 {
+ iface MIXER
+ name 'AIF2ADCL DRC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.584 {
+ iface MIXER
+ name 'AIF2ADCR DRC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.585 {
+ iface MIXER
+ name 'DAC1 Right Sidetone Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 12'
+ dbmin -3600
+ dbmax 0
+ dbvalue.0 -3600
+ }
+ }
+ control.586 {
+ iface MIXER
+ name 'DAC1 Left Sidetone Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 12'
+ dbmin -3600
+ dbmax 0
+ dbvalue.0 -3600
+ }
+ }
+ control.587 {
+ iface MIXER
+ name 'DAC2 Right Sidetone Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 12'
+ dbmin -3600
+ dbmax 0
+ dbvalue.0 -3600
+ }
+ }
+ control.588 {
+ iface MIXER
+ name 'DAC2 Left Sidetone Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 12'
+ dbmin -3600
+ dbmax 0
+ dbvalue.0 -3600
+ }
+ }
+ control.589 {
+ iface MIXER
+ name 'Sidetone HPF Mux'
+ value '2.7kHz'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '2.7kHz'
+ item.1 '1.35kHz'
+ item.2 '675Hz'
+ item.3 '370Hz'
+ item.4 '180Hz'
+ item.5 '90Hz'
+ item.6 '45Hz'
+ }
+ }
+ control.590 {
+ iface MIXER
+ name 'Sidetone HPF Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.591 {
+ iface MIXER
+ name 'AIF1ADC1 HPF Mode'
+ value HiFi
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 HiFi
+ item.1 'Voice 1'
+ item.2 'Voice 2'
+ item.3 'Voice 3'
+ }
+ }
+ control.592 {
+ iface MIXER
+ name 'AIF1ADC1 HPF Switch'
+ value.0 false
+ value.1 false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.593 {
+ iface MIXER
+ name 'AIF1ADC2 HPF Mode'
+ value HiFi
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 HiFi
+ item.1 'Voice 1'
+ item.2 'Voice 2'
+ item.3 'Voice 3'
+ }
+ }
+ control.594 {
+ iface MIXER
+ name 'AIF1ADC2 HPF Switch'
+ value.0 false
+ value.1 false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.595 {
+ iface MIXER
+ name 'AIF2ADC HPF Mode'
+ value HiFi
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 HiFi
+ item.1 'Voice 1'
+ item.2 'Voice 2'
+ item.3 'Voice 3'
+ }
+ }
+ control.596 {
+ iface MIXER
+ name 'AIF2ADC HPF Switch'
+ value.0 false
+ value.1 false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.597 {
+ iface MIXER
+ name 'ADC OSR'
+ value 'High Performance'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'Low Power'
+ item.1 'High Performance'
+ }
+ }
+ control.598 {
+ iface MIXER
+ name 'DAC OSR'
+ value 'Low Power'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'Low Power'
+ item.1 'High Performance'
+ }
+ }
+ control.599 {
+ iface MIXER
+ name 'DAC1 Volume'
+ value.0 96
+ value.1 96
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 112'
+ dbmin -9999999
+ dbmax 1200
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.600 {
+ iface MIXER
+ name 'DAC1 Switch'
+ value.0 true
+ value.1 true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.601 {
+ iface MIXER
+ name 'DAC2 Volume'
+ value.0 96
+ value.1 96
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 112'
+ dbmin -9999999
+ dbmax 1200
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.602 {
+ iface MIXER
+ name 'DAC2 Switch'
+ value.0 false
+ value.1 false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.603 {
+ iface MIXER
+ name 'SPKL DAC2 Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -300
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.604 {
+ iface MIXER
+ name 'SPKL DAC1 Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -300
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.605 {
+ iface MIXER
+ name 'SPKR DAC2 Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -300
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.606 {
+ iface MIXER
+ name 'SPKR DAC1 Volume'
+ value 1
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 1'
+ dbmin -300
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.607 {
+ iface MIXER
+ name 'AIF1DAC1 3D Stereo Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 15'
+ dbmin -1600
+ dbmax 1145
+ dbvalue.0 -1600
+ }
+ }
+ control.608 {
+ iface MIXER
+ name 'AIF1DAC1 3D Stereo Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.609 {
+ iface MIXER
+ name 'AIF1DAC2 3D Stereo Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 15'
+ dbmin -1600
+ dbmax 1145
+ dbvalue.0 -1600
+ }
+ }
+ control.610 {
+ iface MIXER
+ name 'AIF1DAC2 3D Stereo Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.611 {
+ iface MIXER
+ name 'AIF2DAC 3D Stereo Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 15'
+ dbmin -1600
+ dbmax 1145
+ dbvalue.0 -1600
+ }
+ }
+ control.612 {
+ iface MIXER
+ name 'AIF2DAC 3D Stereo Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.613 {
+ iface MIXER
+ name 'MIXINL MIXOUTL Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin 0
+ dbmax 6300
+ dbvalue.0 0
+ }
+ }
+ control.614 {
+ iface MIXER
+ name 'MIXINR MIXOUTR Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin 0
+ dbmax 6300
+ dbvalue.0 0
+ }
+ }
+ control.615 {
+ iface MIXER
+ name 'AIF3 Boost Volume'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 3'
+ dbmin 0
+ dbmax 1800
+ dbvalue.0 0
+ }
+ }
+ control.616 {
+ iface MIXER
+ name 'AIF1DAC1 Noise Gate Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.617 {
+ iface MIXER
+ name 'AIF1DAC1 Noise Gate Hold Time'
+ value '30ms'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '30ms'
+ item.1 '125ms'
+ item.2 '250ms'
+ item.3 '500ms'
+ }
+ }
+ control.618 {
+ iface MIXER
+ name 'AIF1DAC1 Noise Gate Threshold Volume'
+ value 3
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -10200
+ dbmax -6000
+ dbvalue.0 -8400
+ }
+ }
+ control.619 {
+ iface MIXER
+ name 'AIF1DAC2 Noise Gate Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.620 {
+ iface MIXER
+ name 'AIF1DAC2 Noise Gate Hold Time'
+ value '30ms'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '30ms'
+ item.1 '125ms'
+ item.2 '250ms'
+ item.3 '500ms'
+ }
+ }
+ control.621 {
+ iface MIXER
+ name 'AIF1DAC2 Noise Gate Threshold Volume'
+ value 3
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -10200
+ dbmax -6000
+ dbvalue.0 -8400
+ }
+ }
+ control.622 {
+ iface MIXER
+ name 'AIF2DAC Noise Gate Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.623 {
+ iface MIXER
+ name 'AIF2DAC Noise Gate Hold Time'
+ value '30ms'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '30ms'
+ item.1 '125ms'
+ item.2 '250ms'
+ item.3 '500ms'
+ }
+ }
+ control.624 {
+ iface MIXER
+ name 'AIF2DAC Noise Gate Threshold Volume'
+ value 3
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 7'
+ dbmin -10200
+ dbmax -6000
+ dbvalue.0 -8400
+ }
+ }
+ control.625 {
+ iface MIXER
+ name 'AIF1DAC1 MBC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.626 {
+ iface MIXER
+ name 'AIF1DAC2 MBC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.627 {
+ iface MIXER
+ name 'AIF2DAC MBC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.628 {
+ iface MIXER
+ name 'AIF1DAC1 VSS Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.629 {
+ iface MIXER
+ name 'AIF1DAC2 VSS Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.630 {
+ iface MIXER
+ name 'AIF2DAC VSS Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.631 {
+ iface MIXER
+ name 'AIF1DAC1 HPF1 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.632 {
+ iface MIXER
+ name 'AIF1DAC2 HPF1 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.633 {
+ iface MIXER
+ name 'AIF2DAC HPF1 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.634 {
+ iface MIXER
+ name 'AIF1DAC1 HPF2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.635 {
+ iface MIXER
+ name 'AIF1DAC2 HPF2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.636 {
+ iface MIXER
+ name 'AIF2DAC HPF2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.637 {
+ iface MIXER
+ name 'AIF1DAC1 Enhanced EQ Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.638 {
+ iface MIXER
+ name 'AIF1DAC2 Enhanced EQ Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.639 {
+ iface MIXER
+ name 'AIF2DAC Enhanced EQ Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.640 {
+ iface MIXER
+ name 'ADCR Mux'
+ value DMIC
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 ADC
+ item.1 DMIC
+ }
+ }
+ control.641 {
+ iface MIXER
+ name 'ADCL Mux'
+ value DMIC
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 ADC
+ item.1 DMIC
+ }
+ }
+ control.642 {
+ iface MIXER
+ name 'Right Headphone Mux'
+ value Mixer
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 Mixer
+ item.1 DAC
+ }
+ }
+ control.643 {
+ iface MIXER
+ name 'Left Headphone Mux'
+ value Mixer
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 Mixer
+ item.1 DAC
+ }
+ }
+ control.644 {
+ iface MIXER
+ name 'SPKR DAC2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.645 {
+ iface MIXER
+ name 'SPKR Input Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.646 {
+ iface MIXER
+ name 'SPKR IN1RP Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.647 {
+ iface MIXER
+ name 'SPKR Output Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.648 {
+ iface MIXER
+ name 'SPKR DAC1 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.649 {
+ iface MIXER
+ name 'SPKL DAC2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.650 {
+ iface MIXER
+ name 'SPKL Input Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.651 {
+ iface MIXER
+ name 'SPKL IN1LP Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.652 {
+ iface MIXER
+ name 'SPKL Output Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.653 {
+ iface MIXER
+ name 'SPKL DAC1 Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.654 {
+ iface MIXER
+ name 'AIF3ADC Mux'
+ value AIF1ADCDAT
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 AIF1ADCDAT
+ item.1 AIF2ADCDAT
+ item.2 AIF2DACDAT
+ item.3 'Mono PCM'
+ }
+ }
+ control.655 {
+ iface MIXER
+ name 'AIF2DACR Mux'
+ value AIF2
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 AIF2
+ item.1 AIF3
+ }
+ }
+ control.656 {
+ iface MIXER
+ name 'AIF2DACL Mux'
+ value AIF2
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 AIF2
+ item.1 AIF3
+ }
+ }
+ control.657 {
+ iface MIXER
+ name 'Mono PCM Out Mux'
+ value None
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 None
+ item.1 AIF2ADCL
+ item.2 AIF2ADCR
+ }
+ }
+ control.658 {
+ iface MIXER
+ name 'AIF2 Loopback'
+ value None
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 None
+ item.1 ADCDAT
+ }
+ }
+ control.659 {
+ iface MIXER
+ name 'AIF1 Loopback'
+ value None
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 None
+ item.1 ADCDAT
+ }
+ }
+ control.660 {
+ iface MIXER
+ name 'AIF2ADC Mux'
+ value AIF2ADCDAT
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 AIF2ADCDAT
+ item.1 AIF3DACDAT
+ }
+ }
+ control.661 {
+ iface MIXER
+ name 'AIF2DAC Mux'
+ value AIF2DACDAT
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 AIF2DACDAT
+ item.1 AIF3DACDAT
+ }
+ }
+ control.662 {
+ iface MIXER
+ name 'AIF1DAC Mux'
+ value AIF1DACDAT
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 AIF1DACDAT
+ item.1 AIF3DACDAT
+ }
+ }
+ control.663 {
+ iface MIXER
+ name 'DAC1R Mixer Right Sidetone Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.664 {
+ iface MIXER
+ name 'DAC1R Mixer Left Sidetone Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.665 {
+ iface MIXER
+ name 'DAC1R Mixer AIF2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.666 {
+ iface MIXER
+ name 'DAC1R Mixer AIF1.2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.667 {
+ iface MIXER
+ name 'DAC1R Mixer AIF1.1 Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.668 {
+ iface MIXER
+ name 'DAC1L Mixer Right Sidetone Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.669 {
+ iface MIXER
+ name 'DAC1L Mixer Left Sidetone Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.670 {
+ iface MIXER
+ name 'DAC1L Mixer AIF2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.671 {
+ iface MIXER
+ name 'DAC1L Mixer AIF1.2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.672 {
+ iface MIXER
+ name 'DAC1L Mixer AIF1.1 Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.673 {
+ iface MIXER
+ name 'Right Sidetone'
+ value ADC/DMIC1
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 ADC/DMIC1
+ item.1 DMIC2
+ }
+ }
+ control.674 {
+ iface MIXER
+ name 'Left Sidetone'
+ value ADC/DMIC1
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 ADC/DMIC1
+ item.1 DMIC2
+ }
+ }
+ control.675 {
+ iface MIXER
+ name 'AIF2DAC2R Mixer Right Sidetone Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.676 {
+ iface MIXER
+ name 'AIF2DAC2R Mixer Left Sidetone Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.677 {
+ iface MIXER
+ name 'AIF2DAC2R Mixer AIF2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.678 {
+ iface MIXER
+ name 'AIF2DAC2R Mixer AIF1.2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.679 {
+ iface MIXER
+ name 'AIF2DAC2R Mixer AIF1.1 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.680 {
+ iface MIXER
+ name 'AIF2DAC2L Mixer Right Sidetone Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.681 {
+ iface MIXER
+ name 'AIF2DAC2L Mixer Left Sidetone Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.682 {
+ iface MIXER
+ name 'AIF2DAC2L Mixer AIF2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.683 {
+ iface MIXER
+ name 'AIF2DAC2L Mixer AIF1.2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.684 {
+ iface MIXER
+ name 'AIF2DAC2L Mixer AIF1.1 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.685 {
+ iface MIXER
+ name 'AIF1ADC2R Mixer DMIC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.686 {
+ iface MIXER
+ name 'AIF1ADC2R Mixer AIF2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.687 {
+ iface MIXER
+ name 'AIF1ADC2L Mixer DMIC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.688 {
+ iface MIXER
+ name 'AIF1ADC2L Mixer AIF2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.689 {
+ iface MIXER
+ name 'AIF1ADC1R Mixer ADC/DMIC Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.690 {
+ iface MIXER
+ name 'AIF1ADC1R Mixer AIF2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.691 {
+ iface MIXER
+ name 'AIF1ADC1L Mixer ADC/DMIC Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.692 {
+ iface MIXER
+ name 'AIF1ADC1L Mixer AIF2 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.693 {
+ iface MIXER
+ name 'LINEOUT2P Mixer Right Output Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.694 {
+ iface MIXER
+ name 'LINEOUT2N Mixer Left Output Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.695 {
+ iface MIXER
+ name 'LINEOUT2N Mixer Right Output Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.696 {
+ iface MIXER
+ name 'LINEOUT1P Mixer Left Output Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.697 {
+ iface MIXER
+ name 'LINEOUT1N Mixer Left Output Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.698 {
+ iface MIXER
+ name 'LINEOUT1N Mixer Right Output Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.699 {
+ iface MIXER
+ name 'SPKR Boost Direct Voice Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.700 {
+ iface MIXER
+ name 'SPKR Boost SPKL Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.701 {
+ iface MIXER
+ name 'SPKR Boost SPKR Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.702 {
+ iface MIXER
+ name 'SPKL Boost Direct Voice Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.703 {
+ iface MIXER
+ name 'SPKL Boost SPKL Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.704 {
+ iface MIXER
+ name 'SPKL Boost SPKR Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.705 {
+ iface MIXER
+ name 'Earpiece Mixer Direct Voice Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.706 {
+ iface MIXER
+ name 'Earpiece Mixer Left Output Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.707 {
+ iface MIXER
+ name 'Earpiece Mixer Right Output Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.708 {
+ iface MIXER
+ name 'Right Output Mixer Left Input Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.709 {
+ iface MIXER
+ name 'Right Output Mixer Right Input Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.710 {
+ iface MIXER
+ name 'Right Output Mixer IN2LN Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.711 {
+ iface MIXER
+ name 'Right Output Mixer IN2RN Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.712 {
+ iface MIXER
+ name 'Right Output Mixer IN1L Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.713 {
+ iface MIXER
+ name 'Right Output Mixer IN1R Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.714 {
+ iface MIXER
+ name 'Right Output Mixer IN2RP Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.715 {
+ iface MIXER
+ name 'Right Output Mixer DAC Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.716 {
+ iface MIXER
+ name 'Left Output Mixer Right Input Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.717 {
+ iface MIXER
+ name 'Left Output Mixer Left Input Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.718 {
+ iface MIXER
+ name 'Left Output Mixer IN2RN Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.719 {
+ iface MIXER
+ name 'Left Output Mixer IN2LN Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.720 {
+ iface MIXER
+ name 'Left Output Mixer IN2LP Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.721 {
+ iface MIXER
+ name 'Left Output Mixer IN1R Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.722 {
+ iface MIXER
+ name 'Left Output Mixer IN1L Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.723 {
+ iface MIXER
+ name 'Left Output Mixer DAC Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.724 {
+ iface MIXER
+ name 'MIXINR IN2R Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.725 {
+ iface MIXER
+ name 'MIXINR IN1R Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.726 {
+ iface MIXER
+ name 'MIXINL IN2L Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.727 {
+ iface MIXER
+ name 'MIXINL IN1L Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.728 {
+ iface MIXER
+ name 'IN2R PGA IN2RP Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.729 {
+ iface MIXER
+ name 'IN2R PGA IN2RN Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.730 {
+ iface MIXER
+ name 'IN2L PGA IN2LP Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.731 {
+ iface MIXER
+ name 'IN2L PGA IN2LN Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.732 {
+ iface MIXER
+ name 'IN1R PGA IN1RP Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.733 {
+ iface MIXER
+ name 'IN1R PGA IN1RN Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.734 {
+ iface MIXER
+ name 'IN1L PGA IN1LP Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.735 {
+ iface MIXER
+ name 'IN1L PGA IN1LN Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+}
+state.dummyaudio {
+ control.1 {
+ iface MIXER
+ name 'ssp1_out mux 0'
+ value fm
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 fm
+ item.1 bt
+ }
+ }
+ control.2 {
+ iface MIXER
+ name 'aware_out aware 0 switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.3 {
+ iface MIXER
+ name 'modem_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.4 {
+ iface MIXER
+ name 'modem_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.5 {
+ iface MIXER
+ name 'modem_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.6 {
+ iface MIXER
+ name 'modem_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.7 {
+ iface MIXER
+ name 'modem_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.8 {
+ iface MIXER
+ name 'modem_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.9 {
+ iface MIXER
+ name 'modem_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.10 {
+ iface MIXER
+ name 'modem_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.11 {
+ iface MIXER
+ name 'modem_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.12 {
+ iface MIXER
+ name 'modem_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.13 {
+ iface MIXER
+ name 'modem_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.14 {
+ iface MIXER
+ name 'modem_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.15 {
+ iface MIXER
+ name 'modem_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.16 {
+ iface MIXER
+ name 'modem_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.17 {
+ iface MIXER
+ name 'modem_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.18 {
+ iface MIXER
+ name 'modem_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.19 {
+ iface MIXER
+ name 'fm_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.20 {
+ iface MIXER
+ name 'fm_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.21 {
+ iface MIXER
+ name 'fm_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.22 {
+ iface MIXER
+ name 'fm_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.23 {
+ iface MIXER
+ name 'fm_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.24 {
+ iface MIXER
+ name 'fm_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.25 {
+ iface MIXER
+ name 'fm_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.26 {
+ iface MIXER
+ name 'fm_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.27 {
+ iface MIXER
+ name 'fm_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.28 {
+ iface MIXER
+ name 'fm_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.29 {
+ iface MIXER
+ name 'fm_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.30 {
+ iface MIXER
+ name 'fm_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.31 {
+ iface MIXER
+ name 'fm_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.32 {
+ iface MIXER
+ name 'fm_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.33 {
+ iface MIXER
+ name 'fm_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.34 {
+ iface MIXER
+ name 'fm_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.35 {
+ iface MIXER
+ name 'bt_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.36 {
+ iface MIXER
+ name 'bt_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.37 {
+ iface MIXER
+ name 'bt_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.38 {
+ iface MIXER
+ name 'bt_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.39 {
+ iface MIXER
+ name 'bt_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.40 {
+ iface MIXER
+ name 'bt_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.41 {
+ iface MIXER
+ name 'bt_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.42 {
+ iface MIXER
+ name 'bt_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.43 {
+ iface MIXER
+ name 'bt_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.44 {
+ iface MIXER
+ name 'bt_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.45 {
+ iface MIXER
+ name 'bt_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.46 {
+ iface MIXER
+ name 'bt_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.47 {
+ iface MIXER
+ name 'bt_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.48 {
+ iface MIXER
+ name 'bt_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.49 {
+ iface MIXER
+ name 'bt_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.50 {
+ iface MIXER
+ name 'bt_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.51 {
+ iface MIXER
+ name 'codec_out1 mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.52 {
+ iface MIXER
+ name 'codec_out1 mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.53 {
+ iface MIXER
+ name 'codec_out1 mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.54 {
+ iface MIXER
+ name 'codec_out1 mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.55 {
+ iface MIXER
+ name 'codec_out1 mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.56 {
+ iface MIXER
+ name 'codec_out1 mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.57 {
+ iface MIXER
+ name 'codec_out1 mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.58 {
+ iface MIXER
+ name 'codec_out1 mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.59 {
+ iface MIXER
+ name 'codec_out1 mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.60 {
+ iface MIXER
+ name 'codec_out1 mix 0 speech_in'
+ value false
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+ value false
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+ count 1
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+ value false
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+ count 1
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+ count 1
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+ count 1
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+ value false
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+ count 1
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+ count 1
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+ count 1
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+ value false
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+ value false
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+ value false
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+ count 1
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+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ name 'speech_out mix 0 media_loop1_in'
+ value false
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+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ name 'speech_out mix 0 txspeech_in'
+ value false
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+ type BOOLEAN
+ count 1
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+ name 'speech_out mix 0 speech_in'
+ value false
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+ count 1
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+ name 'speech_out mix 0 tone_in'
+ value false
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+ type BOOLEAN
+ count 1
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+ type BOOLEAN
+ count 1
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+ value false
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+ count 1
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+ value false
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+ count 1
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+ count 1
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+ count 1
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+ count 1
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+ value false
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+ count 1
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+ value false
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+ count 1
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+ value false
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+ count 1
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+ count 1
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+ value false
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+ count 1
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+ value false
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+ value false
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+ count 1
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+ name 'hf_sns_out mix 0 voip_in'
+ value false
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+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ value false
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+ count 1
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+ value false
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+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ count 1
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+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ value false
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+ value false
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+ count 1
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+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ value false
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+ type BOOLEAN
+ count 1
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+ value false
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+ count 1
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+ value false
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+ value false
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+ type BOOLEAN
+ count 1
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+ count 1
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+ count 1
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+ name 'aware_out mix 0 sprot_loop_in'
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+ type BOOLEAN
+ count 1
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+ name 'aware_out mix 0 sidetone_in'
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+ type BOOLEAN
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+ type BOOLEAN
+ count 1
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+ name 'aware_out mix 0 speech_in'
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+ count 1
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+ name 'aware_out mix 0 tone_in'
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+ count 1
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+ name 'aware_out mix 0 voip_in'
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+ type BOOLEAN
+ count 1
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+ name 'aware_out mix 0 pcm0_in'
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+ count 1
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+ name 'aware_out mix 0 pcm1_in'
+ value false
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+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.177 {
+ iface MIXER
+ name 'aware_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.178 {
+ iface MIXER
+ name 'aware_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.179 {
+ iface MIXER
+ name 'voip_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.180 {
+ iface MIXER
+ name 'voip_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.181 {
+ iface MIXER
+ name 'voip_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.182 {
+ iface MIXER
+ name 'voip_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.183 {
+ iface MIXER
+ name 'voip_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.184 {
+ iface MIXER
+ name 'voip_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.185 {
+ iface MIXER
+ name 'voip_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.186 {
+ iface MIXER
+ name 'voip_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.187 {
+ iface MIXER
+ name 'voip_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.188 {
+ iface MIXER
+ name 'voip_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.189 {
+ iface MIXER
+ name 'voip_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.190 {
+ iface MIXER
+ name 'voip_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.191 {
+ iface MIXER
+ name 'voip_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.192 {
+ iface MIXER
+ name 'voip_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.193 {
+ iface MIXER
+ name 'voip_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.194 {
+ iface MIXER
+ name 'voip_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.195 {
+ iface MIXER
+ name 'media_loop2_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.196 {
+ iface MIXER
+ name 'media_loop2_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.197 {
+ iface MIXER
+ name 'media_loop2_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.198 {
+ iface MIXER
+ name 'media_loop2_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.199 {
+ iface MIXER
+ name 'media_loop2_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.200 {
+ iface MIXER
+ name 'media_loop2_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.201 {
+ iface MIXER
+ name 'media_loop2_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.202 {
+ iface MIXER
+ name 'media_loop2_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.203 {
+ iface MIXER
+ name 'media_loop2_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.204 {
+ iface MIXER
+ name 'media_loop2_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.205 {
+ iface MIXER
+ name 'media_loop2_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.206 {
+ iface MIXER
+ name 'media_loop2_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.207 {
+ iface MIXER
+ name 'media_loop2_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.208 {
+ iface MIXER
+ name 'media_loop2_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.209 {
+ iface MIXER
+ name 'media_loop2_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.210 {
+ iface MIXER
+ name 'media_loop2_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.211 {
+ iface MIXER
+ name 'media_loop1_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.212 {
+ iface MIXER
+ name 'media_loop1_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.213 {
+ iface MIXER
+ name 'media_loop1_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.214 {
+ iface MIXER
+ name 'media_loop1_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.215 {
+ iface MIXER
+ name 'media_loop1_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.216 {
+ iface MIXER
+ name 'media_loop1_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.217 {
+ iface MIXER
+ name 'media_loop1_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.218 {
+ iface MIXER
+ name 'media_loop1_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.219 {
+ iface MIXER
+ name 'media_loop1_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.220 {
+ iface MIXER
+ name 'media_loop1_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.221 {
+ iface MIXER
+ name 'media_loop1_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.222 {
+ iface MIXER
+ name 'media_loop1_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.223 {
+ iface MIXER
+ name 'media_loop1_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.224 {
+ iface MIXER
+ name 'media_loop1_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.225 {
+ iface MIXER
+ name 'media_loop1_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.226 {
+ iface MIXER
+ name 'media_loop1_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.227 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.228 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.229 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.230 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.231 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.232 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.233 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.234 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.235 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.236 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.237 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.238 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.239 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.240 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.241 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.242 {
+ iface MIXER
+ name 'sprot_loop_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.243 {
+ iface MIXER
+ name 'pcm2_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.244 {
+ iface MIXER
+ name 'pcm2_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.245 {
+ iface MIXER
+ name 'pcm2_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.246 {
+ iface MIXER
+ name 'pcm2_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.247 {
+ iface MIXER
+ name 'pcm2_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.248 {
+ iface MIXER
+ name 'pcm2_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.249 {
+ iface MIXER
+ name 'pcm2_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.250 {
+ iface MIXER
+ name 'pcm2_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.251 {
+ iface MIXER
+ name 'pcm2_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.252 {
+ iface MIXER
+ name 'pcm2_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.253 {
+ iface MIXER
+ name 'pcm2_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.254 {
+ iface MIXER
+ name 'pcm2_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.255 {
+ iface MIXER
+ name 'pcm2_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.256 {
+ iface MIXER
+ name 'pcm2_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.257 {
+ iface MIXER
+ name 'pcm2_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.258 {
+ iface MIXER
+ name 'pcm2_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.259 {
+ iface MIXER
+ name 'pcm1_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.260 {
+ iface MIXER
+ name 'pcm1_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.261 {
+ iface MIXER
+ name 'pcm1_out mix 0 codec_in0'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.262 {
+ iface MIXER
+ name 'pcm1_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.263 {
+ iface MIXER
+ name 'pcm1_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.264 {
+ iface MIXER
+ name 'pcm1_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.265 {
+ iface MIXER
+ name 'pcm1_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.266 {
+ iface MIXER
+ name 'pcm1_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.267 {
+ iface MIXER
+ name 'pcm1_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.268 {
+ iface MIXER
+ name 'pcm1_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.269 {
+ iface MIXER
+ name 'pcm1_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.270 {
+ iface MIXER
+ name 'pcm1_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.271 {
+ iface MIXER
+ name 'pcm1_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.272 {
+ iface MIXER
+ name 'pcm1_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.273 {
+ iface MIXER
+ name 'pcm1_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.274 {
+ iface MIXER
+ name 'pcm1_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.275 {
+ iface MIXER
+ name 'pcm0_out mix 0 modem_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.276 {
+ iface MIXER
+ name 'pcm0_out mix 0 bt_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.277 {
+ iface MIXER
+ name 'pcm0_out mix 0 codec_in0'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.278 {
+ iface MIXER
+ name 'pcm0_out mix 0 codec_in1'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.279 {
+ iface MIXER
+ name 'pcm0_out mix 0 sprot_loop_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.280 {
+ iface MIXER
+ name 'pcm0_out mix 0 media_loop1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.281 {
+ iface MIXER
+ name 'pcm0_out mix 0 media_loop2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.282 {
+ iface MIXER
+ name 'pcm0_out mix 0 sidetone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.283 {
+ iface MIXER
+ name 'pcm0_out mix 0 txspeech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.284 {
+ iface MIXER
+ name 'pcm0_out mix 0 speech_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.285 {
+ iface MIXER
+ name 'pcm0_out mix 0 tone_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.286 {
+ iface MIXER
+ name 'pcm0_out mix 0 voip_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.287 {
+ iface MIXER
+ name 'pcm0_out mix 0 pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.288 {
+ iface MIXER
+ name 'pcm0_out mix 0 pcm1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.289 {
+ iface MIXER
+ name 'pcm0_out mix 0 low_pcm0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.290 {
+ iface MIXER
+ name 'pcm0_out mix 0 fm_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.291 {
+ iface MIXER
+ name 'media1_out mix 0 media0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.292 {
+ iface MIXER
+ name 'media1_out mix 0 media1_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.293 {
+ iface MIXER
+ name 'media1_out mix 0 media2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.294 {
+ iface MIXER
+ name 'media1_out mix 0 media3_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.295 {
+ iface MIXER
+ name 'media0_out mix 0 media0_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.296 {
+ iface MIXER
+ name 'media0_out mix 0 media1_in'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.297 {
+ iface MIXER
+ name 'media0_out mix 0 media2_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.298 {
+ iface MIXER
+ name 'media0_out mix 0 media3_in'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.299 {
+ iface MIXER
+ name 'media0_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.300 {
+ iface MIXER
+ name 'media0_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.301 {
+ iface MIXER
+ name 'media0_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.302 {
+ iface MIXER
+ name 'media1_in gain 0 rampduration'
+ value 50
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.303 {
+ iface MIXER
+ name 'media1_in gain 0 mute'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.304 {
+ iface MIXER
+ name 'media1_in gain 0 volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.305 {
+ iface MIXER
+ name 'media2_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.306 {
+ iface MIXER
+ name 'media2_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.307 {
+ iface MIXER
+ name 'media2_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.308 {
+ iface MIXER
+ name 'media3_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.309 {
+ iface MIXER
+ name 'media3_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.310 {
+ iface MIXER
+ name 'media3_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.311 {
+ iface MIXER
+ name 'pcm0_in gain 0 rampduration'
+ value 50
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.312 {
+ iface MIXER
+ name 'pcm0_in gain 0 mute'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.313 {
+ iface MIXER
+ name 'pcm0_in gain 0 volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.314 {
+ iface MIXER
+ name 'pcm1_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.315 {
+ iface MIXER
+ name 'pcm1_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.316 {
+ iface MIXER
+ name 'pcm1_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.317 {
+ iface MIXER
+ name 'low_pcm0_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.318 {
+ iface MIXER
+ name 'low_pcm0_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.319 {
+ iface MIXER
+ name 'low_pcm0_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.320 {
+ iface MIXER
+ name 'pcm1_out gain 0 rampduration'
+ value 50
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.321 {
+ iface MIXER
+ name 'pcm1_out gain 0 mute'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.322 {
+ iface MIXER
+ name 'pcm1_out gain 0 volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.323 {
+ iface MIXER
+ name 'pcm2_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.324 {
+ iface MIXER
+ name 'pcm2_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.325 {
+ iface MIXER
+ name 'pcm2_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.326 {
+ iface MIXER
+ name 'voip_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.327 {
+ iface MIXER
+ name 'voip_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.328 {
+ iface MIXER
+ name 'voip_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.329 {
+ iface MIXER
+ name 'voip_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.330 {
+ iface MIXER
+ name 'voip_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.331 {
+ iface MIXER
+ name 'voip_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.332 {
+ iface MIXER
+ name 'tone_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.333 {
+ iface MIXER
+ name 'tone_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.334 {
+ iface MIXER
+ name 'tone_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.335 {
+ iface MIXER
+ name 'aware_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.336 {
+ iface MIXER
+ name 'aware_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.337 {
+ iface MIXER
+ name 'aware_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.338 {
+ iface MIXER
+ name 'vad_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.339 {
+ iface MIXER
+ name 'vad_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.340 {
+ iface MIXER
+ name 'vad_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.341 {
+ iface MIXER
+ name 'hf_sns_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.342 {
+ iface MIXER
+ name 'hf_sns_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.343 {
+ iface MIXER
+ name 'hf_sns_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.344 {
+ iface MIXER
+ name 'hf_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.345 {
+ iface MIXER
+ name 'hf_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.346 {
+ iface MIXER
+ name 'hf_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.347 {
+ iface MIXER
+ name 'speech_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.348 {
+ iface MIXER
+ name 'speech_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.349 {
+ iface MIXER
+ name 'speech_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.350 {
+ iface MIXER
+ name 'txspeech_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.351 {
+ iface MIXER
+ name 'txspeech_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.352 {
+ iface MIXER
+ name 'txspeech_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.353 {
+ iface MIXER
+ name 'rxspeech_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.354 {
+ iface MIXER
+ name 'rxspeech_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.355 {
+ iface MIXER
+ name 'rxspeech_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.356 {
+ iface MIXER
+ name 'speech_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.357 {
+ iface MIXER
+ name 'speech_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.358 {
+ iface MIXER
+ name 'speech_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.359 {
+ iface MIXER
+ name 'codec_in0 gain 0 rampduration'
+ value 50
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.360 {
+ iface MIXER
+ name 'codec_in0 gain 0 mute'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.361 {
+ iface MIXER
+ name 'codec_in0 gain 0 volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.362 {
+ iface MIXER
+ name 'codec_in1 gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.363 {
+ iface MIXER
+ name 'codec_in1 gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.364 {
+ iface MIXER
+ name 'codec_in1 gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.365 {
+ iface MIXER
+ name 'codec_out0 gain 0 rampduration'
+ value 50
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.366 {
+ iface MIXER
+ name 'codec_out0 gain 0 mute'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.367 {
+ iface MIXER
+ name 'codec_out0 gain 0 volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.368 {
+ iface MIXER
+ name 'codec_out1 gain 0 rampduration'
+ value 50
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.369 {
+ iface MIXER
+ name 'codec_out1 gain 0 mute'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.370 {
+ iface MIXER
+ name 'codec_out1 gain 0 volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.371 {
+ iface MIXER
+ name 'bt_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.372 {
+ iface MIXER
+ name 'bt_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.373 {
+ iface MIXER
+ name 'bt_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.374 {
+ iface MIXER
+ name 'fm_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.375 {
+ iface MIXER
+ name 'fm_out gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.376 {
+ iface MIXER
+ name 'fm_out gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.377 {
+ iface MIXER
+ name 'bt_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.378 {
+ iface MIXER
+ name 'bt_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.379 {
+ iface MIXER
+ name 'bt_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.380 {
+ iface MIXER
+ name 'fm_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.381 {
+ iface MIXER
+ name 'fm_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.382 {
+ iface MIXER
+ name 'fm_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.383 {
+ iface MIXER
+ name 'modem_in gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.384 {
+ iface MIXER
+ name 'modem_in gain 0 mute'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.385 {
+ iface MIXER
+ name 'modem_in gain 0 volume'
+ value.0 -1440
+ value.1 -1440
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '-1440 - 360'
+ dbmin -14400
+ dbmax 3600
+ dbvalue.0 -14400
+ dbvalue.1 -14400
+ }
+ }
+ control.386 {
+ iface MIXER
+ name 'modem_out gain 0 rampduration'
+ value 5
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '5 - 5000'
+ }
+ }
+ control.387 {
+ iface MIXER
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+ iface MIXER
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+ iface MIXER
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+ iface MIXER
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+ iface MIXER
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+ iface MIXER
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+ iface MIXER
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+ value 5
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+ control.399 {
+ iface MIXER
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+ iface MIXER
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+ iface MIXER
+ name 'sidetone_in gain 0 rampduration'
+ value 5
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+ access 'read write'
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+ control.402 {
+ iface MIXER
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+ iface MIXER
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+ iface MIXER
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+ value '000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
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+ iface MIXER
+ name 'codec_out interleaver slot 0'
+ value codec_out0_0
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 none
+ item.1 codec_out0_0
+ item.2 codec_out0_1
+ item.3 codec_out1_0
+ item.4 codec_out1_1
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+ control.448 {
+ iface MIXER
+ name 'codec_out interleaver slot 1'
+ value codec_out0_1
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 none
+ item.1 codec_out0_0
+ item.2 codec_out0_1
+ item.3 codec_out1_0
+ item.4 codec_out1_1
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+ control.449 {
+ iface MIXER
+ name 'codec_out interleaver slot 2'
+ value codec_out1_0
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 none
+ item.1 codec_out0_0
+ item.2 codec_out0_1
+ item.3 codec_out1_0
+ item.4 codec_out1_1
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+ control.450 {
+ iface MIXER
+ name 'codec_out interleaver slot 3'
+ value codec_out1_1
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 none
+ item.1 codec_out0_0
+ item.2 codec_out0_1
+ item.3 codec_out1_0
+ item.4 codec_out1_1
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+ control.451 {
+ iface MIXER
+ name 'codec_in deinterleaver codec_in0_0'
+ value 'slot 0'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 none
+ item.1 'slot 0'
+ item.2 'slot 1'
+ item.3 'slot 2'
+ item.4 'slot 3'
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+ control.452 {
+ iface MIXER
+ name 'codec_in deinterleaver codec_in0_1'
+ value 'slot 1'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 none
+ item.1 'slot 0'
+ item.2 'slot 1'
+ item.3 'slot 2'
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+ control.453 {
+ iface MIXER
+ name 'codec_in deinterleaver codec_in1_0'
+ value 'slot 2'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 none
+ item.1 'slot 0'
+ item.2 'slot 1'
+ item.3 'slot 2'
+ item.4 'slot 3'
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+ control.454 {
+ iface MIXER
+ name 'codec_in deinterleaver codec_in1_1'
+ value 'slot 3'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 none
+ item.1 'slot 0'
+ item.2 'slot 1'
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+ item.4 'slot 3'
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+ control.455 {
+ iface MIXER
+ name 'domain voice mode 0'
+ value narrowband
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 narrowband
+ item.1 wideband
+ }
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+ control.456 {
+ iface MIXER
+ name 'domain bt mode 0'
+ value narrowband
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 narrowband
+ item.1 wideband
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+ iface MIXER
+ name 'sst debug byte control'
+ value '0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+ comment {
+ access 'read write'
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+ count 512
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+ control.458 {
+ iface MIXER
+ name 'probe out0 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
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+ control.459 {
+ iface MIXER
+ name 'probe out1 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
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+ control.460 {
+ iface MIXER
+ name 'probe out2 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
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+ control.461 {
+ iface MIXER
+ name 'probe out3 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.462 {
+ iface MIXER
+ name 'probe out4 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.463 {
+ iface MIXER
+ name 'probe out5 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.464 {
+ iface MIXER
+ name 'probe out6 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.465 {
+ iface MIXER
+ name 'probe out7 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.466 {
+ iface MIXER
+ name 'probe in0 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.467 {
+ iface MIXER
+ name 'probe in1 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.468 {
+ iface MIXER
+ name 'probe in2 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.469 {
+ iface MIXER
+ name 'probe in3 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.470 {
+ iface MIXER
+ name 'probe in4 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.471 {
+ iface MIXER
+ name 'probe in5 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.472 {
+ iface MIXER
+ name 'probe in6 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+ control.473 {
+ iface MIXER
+ name 'probe in7 connection'
+ value 'media0_in gain'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'media0_in gain'
+ item.1 'media1_in gain'
+ item.2 'media2_in gain'
+ item.3 'media3_in gain'
+ item.4 'pcm0_in gain'
+ item.5 'pcm1_in gain'
+ item.6 'pcm1_out gain'
+ item.7 'pcm2_out gain'
+ item.8 'voip_in gain'
+ item.9 'voip_out gain'
+ item.10 'aware_out gain'
+ item.11 'vad_out gain'
+ item.12 'hf_sns_out gain'
+ item.13 'hf_out gain'
+ item.14 'speech_out gain'
+ item.15 'txspeech_in gain'
+ item.16 'rxspeech_out gain'
+ item.17 'speech_in gain'
+ item.18 'media_loop1_out gain'
+ item.19 'media_loop2_out gain'
+ item.20 'tone_in gain'
+ item.21 'codec_out0 gain'
+ item.22 'codec_out1 gain'
+ item.23 'bt_out gain'
+ item.24 'fm_out gain'
+ item.25 'modem_out gain'
+ item.26 'codec_in0 gain'
+ item.27 'codec_in1 gain'
+ item.28 'bt_in gain'
+ item.29 'fm_in gain'
+ item.30 'modem_in gain'
+ }
+ }
+}
diff --git a/device-software/meta-edison-distro/recipes-multimedia/libav/libav_0.8.9.bbappend b/device-software/meta-edison-distro/recipes-multimedia/libav/libav_0.8.9.bbappend
new file mode 100644
index 0000000..939e988
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-multimedia/libav/libav_0.8.9.bbappend
@@ -0,0 +1,23 @@
+# Disable features that have potential commercial licensing restrictions
+EXTRA_OECONF += "\
+ --disable-encoder=libmp3lame \
+ --disable-decoder=mp3 \
+ --disable-decoder=mp3adu \
+ --disable-decoder=mp3adufloat \
+ --disable-decoder=mp3float \
+ --disable-decoder=mp3on4 \
+ --disable-decoder=mp3on4float \
+ --disable-muxer=mp3 \
+ --disable-demuxer=mp3 \
+ --disable-bsf=mp3_header_decompress \
+ --disable-bsf=mp3_header_compress \
+ \
+ --disable-encoder=mpeg2video \
+ --disable-decoder=mpeg2video \
+ --disable-hwaccel=mpeg2_vaapi\
+ --disable-hwaccel=mpeg2_dxva2\
+ --disable-muxer=mpeg2dvd \
+ --disable-muxer=mpeg2svcd \
+ --disable-muxer=mpeg2video \
+ --disable-muxer=mpeg2vob \
+"
diff --git a/device-software/meta-edison-distro/recipes-multimedia/mplayer/mplayer-common.bb b/device-software/meta-edison-distro/recipes-multimedia/mplayer/mplayer-common.bb
new file mode 100644
index 0000000..889bb95
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-multimedia/mplayer/mplayer-common.bb
@@ -0,0 +1,22 @@
+# Copyright Matthias Hentges (c) 2006
+# License: MIT (see COPYING.MIT)
+
+DESCRIPTION = "Preconfigured mplayer preferences"
+
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COREBASE}/meta/COPYING.MIT;md5=3da9cfbcb788c80a0384361b4de20420"
+
+PV = "0.0.1"
+
+SRC_URI = "file://mplayer.conf"
+
+# Yes, really /usr/etc!!!
+do_install() {
+ install -d "${D}/usr${sysconfdir}/mplayer"
+
+ install -m 0644 ${WORKDIR}/mplayer.conf "${D}/usr${sysconfdir}/mplayer"
+}
+
+FILES_${PN} = "/usr${sysconfdir}/mplayer"
+
+inherit allarch
diff --git a/device-software/meta-edison-distro/recipes-multimedia/mplayer/mplayer-common/mplayer.conf b/device-software/meta-edison-distro/recipes-multimedia/mplayer/mplayer-common/mplayer.conf
new file mode 100644
index 0000000..37ad65f
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-multimedia/mplayer/mplayer-common/mplayer.conf
@@ -0,0 +1,15 @@
+
+# You probably shouldn't touch these
+ac=mad,
+ao=alsa,
+
+# Required on SL-Cxxxx for correct rotation in the *VT*,
+# breaks rotation in X!
+# vf=rotate=1
+
+# Enable fullscreen display by default
+# fs=true
+
+# Drop frames to keep audio and video in sync
+framedrop=true
+
diff --git a/device-software/meta-edison-distro/recipes-multimedia/mplayer/mplayer2/cross.compile.codec-cfg.patch b/device-software/meta-edison-distro/recipes-multimedia/mplayer/mplayer2/cross.compile.codec-cfg.patch
new file mode 100644
index 0000000..7b290b5
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-multimedia/mplayer/mplayer2/cross.compile.codec-cfg.patch
@@ -0,0 +1,16 @@
+Upstream-Status: Pending
+Signed-off-by: Martin Jansa
+
+diff --git a/Makefile b/Makefile
+index 6013ca3..28c6383 100644
+--- a/Makefile
++++ b/Makefile
+@@ -600,7 +602,7 @@ mplayer$(EXESUF):
+ $(CC) -o $@ $^ $(EXTRALIBS)
+
+ codec-cfg$(EXESUF): codec-cfg.c codec-cfg.h
+- $(HOST_CC) -O -DCODECS2HTML -I. -o $@ $<
++ $(BUILD_CC) -O -DCODECS2HTML -I. -Iffmpeg -o $@ $<
+
+ codecs.conf.h: codec-cfg$(EXESUF) etc/codecs.conf
+ ./$^ > $@
diff --git a/device-software/meta-edison-distro/recipes-multimedia/mplayer/mplayer2_git.bb b/device-software/meta-edison-distro/recipes-multimedia/mplayer/mplayer2_git.bb
new file mode 100644
index 0000000..820bffa
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-multimedia/mplayer/mplayer2_git.bb
@@ -0,0 +1,161 @@
+DESCRIPTION = "Open Source multimedia player."
+SECTION = "multimedia"
+HOMEPAGE = "http://www.mplayerhq.hu/"
+DEPENDS = "libtheora ffmpeg zlib libpng jpeg liba52 freetype fontconfig alsa-lib lzo ncurses lame pulseaudio \
+ ${@base_conditional('ENTERPRISE_DISTRO', '1', '', 'libmad liba52 lame', d)}"
+
+RDEPENDS_${PN} = "mplayer-common"
+PROVIDES = "mplayer"
+RPROVIDES_${PN} = "mplayer"
+RCONFLICTS_${PN} = "mplayer"
+
+LICENSE = "GPLv3"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=d32239bcb673463ab874e80d47fae504"
+
+SRC_URI = "git://repo.or.cz/mplayer.git;protocol=git;branch=master \
+ file://cross.compile.codec-cfg.patch \
+"
+
+SRCREV = "e3f5043233336d8b4b0731c6a8b42a8fda5535ac"
+
+ARM_INSTRUCTION_SET = "arm"
+
+PV = "2.0+gitr${SRCPV}"
+PR = "r8"
+
+PARALLEL_MAKE = ""
+
+S = "${WORKDIR}/git"
+
+FILES_${PN} = "${bindir}/mplayer ${libdir} /usr/etc/mplayer/"
+CONFFILES_${PN} += "/usr/etc/mplayer/input.conf \
+ /usr/etc/mplayer/example.conf \
+ /usr/etc/mplayer/codecs.conf \
+ "
+
+inherit autotools pkgconfig
+
+EXTRA_OECONF = " \
+ --prefix=/usr \
+ --mandir=${mandir} \
+ --target=${SIMPLE_TARGET_SYS} \
+ \
+ --disable-fontconfig \
+ --disable-libass \
+ --disable-lirc \
+ --disable-lircc \
+ --disable-joystick \
+ --disable-vm \
+ --disable-xf86keysym \
+ --disable-tv \
+ --disable-tv-v4l1 \
+ --disable-tv-v4l2 \
+ --disable-tv-bsdbt848 \
+ --enable-rtc \
+ --disable-networking \
+ --disable-smb \
+ --disable-live \
+ --disable-dvdnav \
+ --disable-dvdread \
+ --disable-dvdread-internal \
+ --disable-libdvdcss-internal \
+ --disable-cdparanoia \
+ --enable-freetype \
+ --disable-sortsub \
+ --disable-fribidi \
+ --disable-enca \
+ --disable-ftp \
+ --disable-vstream \
+ \
+ --disable-gif \
+ --disable-png \
+ --disable-jpeg \
+ --disable-libcdio \
+ --disable-qtx \
+ --disable-xanim \
+ --disable-real \
+ --disable-xvid \
+ \
+ --disable-mpg123 \
+ --disable-speex \
+ --enable-theora \
+ --disable-ladspa \
+ --disable-libdv \
+ --disable-mad \
+ --disable-xmms \
+ --disable-musepack \
+ \
+ --disable-gl \
+ --disable-vesa \
+ --disable-svga \
+ --disable-sdl \
+ --disable-aa \
+ --disable-caca \
+ --disable-ggi \
+ --disable-ggiwmh \
+ --disable-directx \
+ --disable-dxr3 \
+ --disable-dvb \
+ --disable-mga \
+ --disable-xmga \
+ --disable-xv \
+ --disable-vm \
+ --disable-xinerama \
+ --disable-x11 \
+ --disable-fbdev \
+ --disable-3dfx \
+ --disable-tdfxfb \
+ --disable-s3fb \
+ --disable-directfb \
+ --disable-bl \
+ --disable-tdfxvid \
+ --disable-tga \
+ --disable-pnm \
+ --disable-md5sum \
+ \
+ --disable-alsa \
+ --disable-ossaudio \
+ --disable-arts \
+ --disable-esd \
+ --enable-pulse \
+ --disable-jack \
+ --disable-openal \
+ --disable-nas \
+ --disable-sgiaudio \
+ --disable-sunaudio \
+ --disable-win32waveout \
+ --enable-select \
+ \
+ --extra-libs=' -lstdc++ -lvorbis ' \
+"
+
+EXTRA_OECONF_append_armv6 = " --enable-armv6"
+EXTRA_OECONF_append_armv7a = " --enable-armv6 --enable-neon"
+
+FULL_OPTIMIZATION = "-fexpensive-optimizations -fomit-frame-pointer -frename-registers -O4 -ffast-math"
+BUILD_OPTIMIZATION = "${FULL_OPTIMIZATION}"
+
+CFLAGS_append = " -I${S}/libdvdread4 "
+
+do_configure() {
+ sed -i 's|/usr/include|${STAGING_INCDIR}|g' ${S}/configure
+ sed -i 's|/usr/lib|${STAGING_LIBDIR}|g' ${S}/configure
+ sed -i 's|/usr/\S*include[\w/]*||g' ${S}/configure
+ sed -i 's|/usr/\S*lib[\w/]*||g' ${S}/configure
+ sed -i 's|_install_strip="-s"|_install_strip=""|g' ${S}/configure
+ sed -i 's|HOST_CC|BUILD_CC|' ${S}/Makefile
+
+ export SIMPLE_TARGET_SYS="$(echo ${TARGET_SYS} | sed s:${TARGET_VENDOR}::g)"
+ ./configure ${EXTRA_OECONF}
+}
+
+do_compile () {
+ oe_runmake
+}
+
+do_install_append() {
+ install -d ${D}/usr/etc/mplayer
+ install ${S}/etc/input.conf ${D}/usr/etc/mplayer/
+ install ${S}/etc/example.conf ${D}/usr/etc/mplayer/
+ install ${S}/etc/codecs.conf ${D}/usr/etc/mplayer/
+}
diff --git a/device-software/meta-edison-distro/recipes-multimedia/pulseaudio/files/pulseaudio.service b/device-software/meta-edison-distro/recipes-multimedia/pulseaudio/files/pulseaudio.service
new file mode 100644
index 0000000..0f43b1f
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-multimedia/pulseaudio/files/pulseaudio.service
@@ -0,0 +1,12 @@
+[Unit]
+Description=PulseAudio Sound System
+After=alsa-restore.service
+
+[Service]
+BusName=org.pulseaudio.Server
+ExecStart=/usr/bin/pulseaudio --system --resample-method=src-sinc-fastest
+Restart=always
+
+[Install]
+WantedBy=multi-user.target
+
diff --git a/device-software/meta-edison-distro/recipes-multimedia/pulseaudio/files/system.pa b/device-software/meta-edison-distro/recipes-multimedia/pulseaudio/files/system.pa
new file mode 100644
index 0000000..77e5a35
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-multimedia/pulseaudio/files/system.pa
@@ -0,0 +1,66 @@
+#!/usr/bin/pulseaudio -nF
+#
+# This file is part of PulseAudio.
+#
+# PulseAudio is free software; you can redistribute it and/or modify it
+# under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# PulseAudio is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with PulseAudio; if not, write to the Free Software Foundation,
+# Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+# This startup script is used only if PulseAudio is started in system
+# mode.
+
+### Automatically load driver modules depending on the hardware available
+.ifexists module-udev-detect.so
+load-module module-udev-detect
+.else
+### Use the static hardware detection module (for systems that lack udev/hal support)
+load-module module-detect
+.endif
+
+### Load several protocols
+.ifexists module-esound-protocol-unix.so
+load-module module-esound-protocol-unix
+.endif
+load-module module-native-protocol-unix
+
+### Load bluetooth modules
+.ifexists module-bluetooth-policy.so
+load-module module-bluetooth-policy
+.endif
+
+.ifexists module-bluez5-discover.so
+load-module module-bluez5-discover
+.endif
+
+### Automatically restore the volume of streams and devices
+load-module module-stream-restore
+load-module module-device-restore
+
+### Automatically restore the default sink/source when changed by the user
+### during runtime
+### NOTE: This should be loaded as early as possible so that subsequent modules
+### that look up the default sink/source get the right value
+load-module module-default-device-restore
+
+### Automatically move streams to the default sink if the sink they are
+### connected to dies, similar for sources
+load-module module-rescue-streams
+
+### Make sure we always have a sink around, even if it is a null sink.
+load-module module-always-sink
+
+### Automatically suspend sinks/sources that become idle for too long
+load-module module-suspend-on-idle
+
+### Enable positioned event sounds
+load-module module-position-event-sounds
\ No newline at end of file
diff --git a/device-software/meta-edison-distro/recipes-multimedia/pulseaudio/pulseaudio-service_1.0.bb b/device-software/meta-edison-distro/recipes-multimedia/pulseaudio/pulseaudio-service_1.0.bb
new file mode 100644
index 0000000..e8e10b5
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-multimedia/pulseaudio/pulseaudio-service_1.0.bb
@@ -0,0 +1,28 @@
+DESCRIPTION = "Pulseaudio systemd service"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+
+inherit systemd useradd
+
+DEPENDS = "pulseaudio"
+
+SRC_URI += "\
+ file://pulseaudio.service \
+ "
+
+SYSTEMD_SERVICE_${PN} = "pulseaudio.service"
+
+FILES_${PN} = " \
+ ${systemd_unitdir} \
+"
+
+USERADD_PACKAGES = "pulseaudio-service"
+GROUPMEMS_PARAM_pulseaudio-service = " --add root --group audio"
+
+do_install_append() {
+ if ${@base_contains('DISTRO_FEATURES','systemd','true','false',d)}; then
+ install -d ${D}${systemd_unitdir}/system
+ install -m 0644 ${WORKDIR}/pulseaudio.service ${D}/${systemd_unitdir}/system/
+ fi
+}
+
diff --git a/device-software/meta-edison-distro/recipes-multimedia/pulseaudio/pulseaudio_5.0.bbappend b/device-software/meta-edison-distro/recipes-multimedia/pulseaudio/pulseaudio_5.0.bbappend
new file mode 100644
index 0000000..7900344
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-multimedia/pulseaudio/pulseaudio_5.0.bbappend
@@ -0,0 +1,22 @@
+# Overlay the pulseaudio recipe to embed bluetooth modules for A2DP
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files/"
+
+SRC_URI += "\
+ file://system.pa \
+ "
+
+PACKAGECONFIG ??= "${@base_contains('DISTRO_FEATURES', 'bluetooth', 'bluez5', '', d)} \
+ ${@base_contains('DISTRO_FEATURES', 'systemd', 'systemd', '', d)} \
+ ${@base_contains('DISTRO_FEATURES', 'zeroconf', 'avahi', '', d)} \
+ ${@base_contains('DISTRO_FEATURES', 'x11', 'x11', '', d)}"
+
+RDEPENDS_pulseaudio-server += " \
+ pulseaudio-module-loopback \
+ pulseaudio-module-bluez5-discover \
+ pulseaudio-module-bluez5-device \
+ pulseaudio-module-bluetooth-policy"
+
+do_install_append() {
+ install -m 0644 ${WORKDIR}/system.pa ${D}/${sysconfdir}/pulse/
+}
diff --git a/device-software/meta-edison-distro/recipes-support/blink-led/blink-led_0.1.bb b/device-software/meta-edison-distro/recipes-support/blink-led/blink-led_0.1.bb
new file mode 100644
index 0000000..9fff7d2
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-support/blink-led/blink-led_0.1.bb
@@ -0,0 +1,23 @@
+DESCRIPTION = "Blinks the Edison LED"
+SECTION = "base"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files/"
+
+SRC_URI = "file://blink-led"
+SRC_URI += "file://blink-led.service"
+
+S = "${WORKDIR}"
+
+do_install() {
+ install -d ${D}${bindir}
+ install -m 0755 blink-led ${D}${bindir}
+
+ # Copy service file
+ install -d ${D}/${systemd_unitdir}/system
+ install -m 644 ${WORKDIR}/blink-led.service ${D}/${systemd_unitdir}/system
+}
+
+FILES_${PN} += "${base_libdir}/systemd/system/blink-led.service"
+FILES_${PN} += "${bindir}/blink-led"
diff --git a/device-software/meta-edison-distro/recipes-support/blink-led/files/blink-led b/device-software/meta-edison-distro/recipes-support/blink-led/files/blink-led
new file mode 100755
index 0000000..f8b884f
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-support/blink-led/files/blink-led
@@ -0,0 +1,109 @@
+#!/usr/bin/env python
+
+#
+# Edison LED blinker
+#
+# Copyright (c) 2014, Intel Corporation.
+# Fabien Chereau
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+# This is a very poor implementation as it uses subprocesses for init
+
+import subprocess
+import time
+import argparse
+import signal
+import sys
+
+initial_led_state = "high"
+
+def write_led(value):
+ with open("/sys/class/gpio/gpio40/direction","w") as lf:
+ lf.write(value)
+
+def blink_once():
+ write_led("low")
+ time.sleep(1./args.frequency*args.duty_cycle)
+ write_led("high")
+ time.sleep(1./args.frequency*(1.-args.duty_cycle))
+
+def deinit_led_gpio():
+ # Revert to default state with LED activated
+ write_led(initial_led_state)
+
+ # Deinit LED GPIO
+ subprocess.call("""
+ echo 40 >/sys/class/gpio/unexport
+ echo 214 >/sys/class/gpio/unexport
+ echo 243 >/sys/class/gpio/unexport
+ echo 261 >/sys/class/gpio/unexport
+ """, shell=True)
+
+def signal_term_handler(signal, frame):
+ print 'Signal intercepted: de-initing LED GPIOs'
+ deinit_led_gpio()
+ sys.exit(0)
+
+
+parser = argparse.ArgumentParser(description='Blink the Edison Arduino board LED.')
+parser.add_argument('--frequency', type=float, default=4, help='blink frequency in Hz')
+parser.add_argument('--duration', type=float, default=-1, help='duration of the blink in seconds. Negative value means no timeout, i.e. it will stop when the program is killed.')
+parser.add_argument('--duty_cycle', type=float, default=0.5, help='duty cycle between 0 and 1')
+
+args = parser.parse_args()
+
+# Allows to quit cleanly with CRTL+C or SIGTERM (systemd use SIGTERM to kill a service by default)
+signal.signal(signal.SIGTERM, signal_term_handler)
+signal.signal(signal.SIGINT, signal_term_handler)
+
+# Init GPIO mux for LED control
+subprocess.call("""
+echo 40 >/sys/class/gpio/export
+echo 214 >/sys/class/gpio/export
+echo 243 >/sys/class/gpio/export
+echo 261 >/sys/class/gpio/export
+echo high >/sys/class/gpio/gpio214/direction
+echo mode0 > /sys/kernel/debug/gpio_debug/gpio40/current_pinmux
+echo low >/sys/class/gpio/gpio243/direction
+echo high >/sys/class/gpio/gpio261/direction
+echo low >/sys/class/gpio/gpio214/direction""", shell=True)
+
+# Save current LED value for reverting to proper state at exit
+try:
+ lf = open("/sys/class/gpio/gpio40/value","r")
+ v = lf.read()
+ lf.close()
+ if v[0] == '0':
+ initial_led_state = "low"
+ else:
+ initial_led_state = "high"
+except:
+ print "Can't get current LED state"
+
+# Blink LED
+if args.duration >= 0:
+ for i in range(0, int(args.duration*args.frequency)):
+ blink_once()
+else:
+ while True:
+ blink_once()
+
+deinit_led_gpio()
+
diff --git a/device-software/meta-edison-distro/recipes-support/blink-led/files/blink-led.service b/device-software/meta-edison-distro/recipes-support/blink-led/files/blink-led.service
new file mode 100644
index 0000000..3dcb2ab
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-support/blink-led/files/blink-led.service
@@ -0,0 +1,10 @@
+[Unit]
+Description=Edison Arduino board LED Blinker
+
+[Service]
+ExecStart=/usr/bin/blink-led
+Restart=on-failure
+
+[Install]
+WantedBy=basic.target
+
diff --git a/device-software/meta-edison-distro/recipes-support/cleanjournal/cleanjournal.bb b/device-software/meta-edison-distro/recipes-support/cleanjournal/cleanjournal.bb
new file mode 100644
index 0000000..cc21638
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-support/cleanjournal/cleanjournal.bb
@@ -0,0 +1,31 @@
+DESCRIPTION = "Cleanjournal tool. Remove all corrupted journald entries at startup."
+SECTION = "base"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+
+
+SRC_URI += "file://cleanjournal.service"
+SRC_URI += "file://clean_journal.sh"
+
+SYSTEMD_SERVICE_${PN} = "cleanjournal.service"
+
+RDEPENDS_${PN} = "systemd"
+DEPENDS = "systemd"
+inherit systemd
+
+do_install() {
+ # install service file
+ install -d ${D}${systemd_unitdir}/system
+ install -c -m 0644 ${WORKDIR}/cleanjournal.service ${D}${systemd_unitdir}/system
+
+ # install cleanjournal script
+ install -d ${D}${sbindir}
+ install -c -m 0755 ${WORKDIR}/clean_journal.sh ${D}${sbindir}
+}
+
+# As this package is tied to systemd, only build it when we're also building systemd.
+python () {
+ if not oe.utils.contains ('DISTRO_FEATURES', 'systemd', True, False, d):
+ raise bb.parse.SkipPackage("'systemd' not in DISTRO_FEATURES")
+}
+
diff --git a/device-software/meta-edison-distro/recipes-support/cleanjournal/files/clean_journal.sh b/device-software/meta-edison-distro/recipes-support/cleanjournal/files/clean_journal.sh
new file mode 100644
index 0000000..5758d09
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-support/cleanjournal/files/clean_journal.sh
@@ -0,0 +1,60 @@
+#!/bin/sh
+
+#
+# Cleanjournal script
+#
+# Copyright (c) 2014, Intel Corporation.
+# Fabien Rodriguez
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+#
+
+#
+# This script checks if the remaining space in root partition is lower than 10%.
+# In that case, the corrupted journald entries (ended by '~') will be deleted
+# one by one until remaining space becomes greater or equal to 10%.
+# At each boot, the script is launched by systemd at startup.
+#
+
+# max allowed free space is 10%
+max_allowed_free_space=10
+
+# check remaining space and update clean_journal_needed variable
+check_free_space() {
+ current_free_space=$(df -h | grep /dev/root | awk '{print 100 - $5}' | sed 's/%//')
+ if [ "$current_free_space" -lt "$max_allowed_free_space" ]; then
+ clean_journal_needed=true
+ else
+ clean_journal_needed=false
+ fi
+}
+
+check_free_space
+if [ "$clean_journal_needed" = true ]; then
+ # delete each journald corrupted entry
+ # until remaining space becomes greater than 10%
+ for corrupted_journal_file in $(find /var/log/journal/ -name '*~'); do
+ rm "$corrupted_journal_file"
+ check_free_space
+ if [ "$clean_journal_needed" = false ]; then
+ break
+ fi
+ done
+fi
+
diff --git a/device-software/meta-edison-distro/recipes-support/cleanjournal/files/cleanjournal.service b/device-software/meta-edison-distro/recipes-support/cleanjournal/files/cleanjournal.service
new file mode 100644
index 0000000..ab704f3
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-support/cleanjournal/files/cleanjournal.service
@@ -0,0 +1,10 @@
+[Unit]
+Description=Cleanjournal service
+
+[Service]
+ExecStart=/usr/sbin/clean_journal.sh
+Restart=no
+
+[Install]
+WantedBy=basic.target
+
diff --git a/device-software/meta-edison-distro/recipes-support/crashlog/files/retrieve_crashlog.sh b/device-software/meta-edison-distro/recipes-support/crashlog/files/retrieve_crashlog.sh
index dcb987c..a7f007c 100755
--- a/device-software/meta-edison-distro/recipes-support/crashlog/files/retrieve_crashlog.sh
+++ b/device-software/meta-edison-distro/recipes-support/crashlog/files/retrieve_crashlog.sh
@@ -34,32 +34,65 @@
#
ipanic_console_path=/proc/emmc_ipanic_console
-crashlog_path=/home/root/
+crashlog_path=/home/root
# line containing 'WAKESRC' looks like:
-# '[ 0.530153] [BOOT] WAKESRC=[real reset] (osnib)'
-# wakesrc is the 6th field with [ and ] separators
+# 'Jan 01 00:00:12 edison kernel: [BOOT] WAKESRC=[real reset] (osnib)'
+# wakesrc is the 4th field with [ and ] separators
# List of available wake sources is in driver/platform/x86/intel_scu_ipcutil.c
-wakesrc=`dmesg | grep WAKESRC | awk -F'[][]' '{print $6}'`
+wakesrc=$(journalctl -k -b -0 | grep WAKESRC | awk -F'[][]' '{print $4}')
# any watchdog boot implies a crash
-tmp=`echo -n "${wakesrc}" | grep watchdog`
+tmp=$(echo -n "${wakesrc}" | grep watchdog)
if [ -n "${tmp}" ]; then
- # get the last sequence number (ie for crashlog_00001, get the 1)
- last_file_sequence_number=`ls ${crashlog_path}/crashlog_* | tail -1 | awk -F_ '{print $NF}'`
- if [ -z $last_file_sequence_number ]; then
- last_file_sequence_number="0"
- fi
-
- new_file_sequence_number=`expr ${last_file_sequence_number} + 1`
- new_file_name=`printf "${crashlog_path}/crashlog_%05d\n" $new_file_sequence_number`
- echo "****** Wake Source is [ ${wakesrc} ] ******" > ${new_file_name}
-
- if [ -e ${ipanic_console_path} ]; then
- # we got an epanic trace - standard case
- cat ${ipanic_console_path} >> ${new_file_name}
- echo clear > ${ipanic_console_path}
- fi
+ # get the last sequence number (ie for crashlog_00001, get the 1)
+ last_sequence_number=$(ls ${crashlog_path}/crashlog_* | tail -1 | awk -F_ '{print $NF}' | awk -F. '{print $NR}')
+ if [ -z $last_sequence_number ]; then
+ last_sequence_number="0"
+ fi
+
+ new_sequence_number=$(expr ${last_sequence_number} + 1)
+ new_name=$(printf "crashlog_%05d" $new_sequence_number)
+
+ # create working directory
+ mkdir ${crashlog_path}/${new_name}
+
+ # write crashfile
+ crashfile_path=${crashlog_path}/${new_name}/crashfile
+
+ event="CRASH"
+ manufacturer="Intel Corporation"
+ product_name=$(cat /factory/hardware_model)
+ version=$(cat /factory/hardware_version)
+ serial_number=$(cat /factory/serial_number)
+ linux_version=$(uname -a)
+ build_version=$(cat /etc/version)
+ date=$(date)
+
+ echo "EVENT=${event}" > ${crashfile_path}
+ echo "Manufacturer : ${manufacturer}" >> ${crashfile_path}
+ echo "Product name : ${product_name}" >> ${crashfile_path}
+ echo "Version : ${version}" >> ${crashfile_path}
+ echo "Serial Number : ${serial_number}" >> ${crashfile_path}
+ echo "Linux version : ${linux_version}" >> ${crashfile_path}
+ echo "Build version : ${build_version}" >> ${crashfile_path}
+ echo "Date : ${date}" >> ${crashfile_path}
+ echo -e "Wake source : ${wakesrc}" >> ${crashfile_path}
+
+ # write full journal binary & logs from previous boot
+ journalctl -b -1 -o short-monotonic > ${crashlog_path}/${new_name}/journal_logs
+ journalctl -b -1 -o export > ${crashlog_path}/${new_name}/journal_binary
+
+ # write panic trace
+ if [ -e ${ipanic_console_path} ]; then
+ cat ${ipanic_console_path} > ${crashlog_path}/${new_name}/panic
+ echo clear > ${ipanic_console_path}
+ fi
+
+ # create archive and clear folder
+ tar -zcf ${crashlog_path}/${new_name}.tar.gz -C ${crashlog_path} ${new_name}
+ rm -rf ${crashlog_path}/${new_name}
+
fi
diff --git a/device-software/meta-edison-distro/recipes-support/edison-mcu/files/intel_mcu.bin b/device-software/meta-edison-distro/recipes-support/edison-mcu/files/intel_mcu.bin
new file mode 100644
index 0000000..dcf0544
Binary files /dev/null and b/device-software/meta-edison-distro/recipes-support/edison-mcu/files/intel_mcu.bin differ
diff --git a/device-software/meta-edison-distro/recipes-support/edison-mcu/files/mcu_fw_loader.service b/device-software/meta-edison-distro/recipes-support/edison-mcu/files/mcu_fw_loader.service
new file mode 100644
index 0000000..0057ab6
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-support/edison-mcu/files/mcu_fw_loader.service
@@ -0,0 +1,10 @@
+[Unit]
+Description=Daemon to load edison mcu app binary
+After=syslog.target
+
+[Service]
+ExecStart=/etc/intel_mcu/mcu_fw_loader.sh
+
+[Install]
+WantedBy=multi-user.target
+
diff --git a/device-software/meta-edison-distro/recipes-support/edison-mcu/files/mcu_fw_loader.sh b/device-software/meta-edison-distro/recipes-support/edison-mcu/files/mcu_fw_loader.sh
new file mode 100644
index 0000000..734352d
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-support/edison-mcu/files/mcu_fw_loader.sh
@@ -0,0 +1,12 @@
+#!/bin/sh
+#author: JiuJin Hong (jiujinx.hong@intel.com)
+if [ ! -d "/sys/devices/platform/intel_mcu" ];then
+ exit
+fi
+
+if [ ! -f "/lib/firmware/intel_mcu.bin" ];then
+ exit
+fi
+
+echo "load mcu app" > /sys/devices/platform/intel_mcu/control
+
diff --git a/device-software/meta-edison-distro/recipes-support/edison-mcu/mcu-fw-bin_0.1.bb b/device-software/meta-edison-distro/recipes-support/edison-mcu/mcu-fw-bin_0.1.bb
new file mode 100644
index 0000000..eafb813
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-support/edison-mcu/mcu-fw-bin_0.1.bb
@@ -0,0 +1,17 @@
+DESCRIPTION = "This is edison mcu fw binary."
+HOMEPAGE = "http://www.intel.com"
+LICENSE = "CLOSED"
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files/"
+
+SRC_URI = "file://intel_mcu.bin"
+
+S = "${WORKDIR}"
+
+do_install () {
+ install -v -d ${D}/${base_libdir}/firmware/
+ install -m 644 intel_mcu.bin ${D}/${base_libdir}/firmware/
+}
+
+FILES_${PN} = "${base_libdir}/firmware/"
+
diff --git a/device-software/meta-edison-distro/recipes-support/edison-mcu/mcu-fw-load_0.1.bb b/device-software/meta-edison-distro/recipes-support/edison-mcu/mcu-fw-load_0.1.bb
new file mode 100644
index 0000000..a48aa10
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-support/edison-mcu/mcu-fw-load_0.1.bb
@@ -0,0 +1,23 @@
+DESCRIPTION = "This is intel mcu app download daemon."
+HOMEPAGE = "http://www.intel.com"
+LICENSE = "CLOSED"
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files/"
+
+SRC_URI = "file://mcu_fw_loader.service \
+ file://mcu_fw_loader.sh"
+
+SYSTEMD_SERVICE_${PN} = "mcu_fw_loader.service"
+
+S = "${WORKDIR}"
+
+inherit systemd
+
+do_install () {
+ install -d ${D}${sysconfdir}/intel_mcu/
+ install -m 0755 mcu_fw_loader.sh ${D}${sysconfdir}/intel_mcu/
+
+ install -d ${D}${systemd_unitdir}/system/
+ install -m 0644 mcu_fw_loader.service ${D}${systemd_unitdir}/system/
+}
+
diff --git a/device-software/meta-edison-distro/recipes-support/edison-sst/files/fw_sst_119a.bin b/device-software/meta-edison-distro/recipes-support/edison-sst/files/fw_sst_119a.bin
new file mode 100644
index 0000000..b704fb6
Binary files /dev/null and b/device-software/meta-edison-distro/recipes-support/edison-sst/files/fw_sst_119a.bin differ
diff --git a/device-software/meta-edison-distro/recipes-support/edison-sst/sst-fw-bin_0.1.bb b/device-software/meta-edison-distro/recipes-support/edison-sst/sst-fw-bin_0.1.bb
new file mode 100644
index 0000000..a6c7021
--- /dev/null
+++ b/device-software/meta-edison-distro/recipes-support/edison-sst/sst-fw-bin_0.1.bb
@@ -0,0 +1,19 @@
+DESCRIPTION = "This is edison sst fw binary."
+HOMEPAGE = "http://www.intel.com"
+LICENSE = "CLOSED"
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files/"
+
+SRC_URI = "file://fw_sst_119a.bin"
+
+S = "${WORKDIR}"
+
+do_install () {
+ install -v -d ${D}/${base_libdir}/firmware/
+ install -m 644 fw_sst_119a.bin ${D}/${base_libdir}/firmware/
+}
+
+INSANE_SKIP_${PN} = "arch"
+
+FILES_${PN} = "${base_libdir}/firmware/"
+
diff --git a/device-software/meta-edison-distro/recipes-support/pwr-button-handler/files/pwr-button-handler.c b/device-software/meta-edison-distro/recipes-support/pwr-button-handler/files/pwr-button-handler.c
index 2f41578..d598160 100644
--- a/device-software/meta-edison-distro/recipes-support/pwr-button-handler/files/pwr-button-handler.c
+++ b/device-software/meta-edison-distro/recipes-support/pwr-button-handler/files/pwr-button-handler.c
@@ -46,8 +46,6 @@
/* We use 2 seconds for now */
#define EDISON_OOBE_PRESS_TIMEOUT 2
-#define CALLED_COMMAND_ON_TIMEOUT "/usr/bin/configure_edison --enableOneTimeSetup"
-
struct input_event {
struct timeval time;
unsigned short type;
@@ -64,10 +62,22 @@ int main(int argc, char **argv)
int fd, n;
ssize_t len;
+ if (argc!=3)
+ {
+ printf("Usage:\n");
+ printf(" %s \"command_line1\" \"command_line2\"\n", argv[0]);
+ printf(" command_line1: a command line to execute when the PWR button is pressed for more than 2s\n");
+ printf(" command_line2: a second command line to execute when the PWR button is released (after being pressed for more than 2s)\n");
+ return -1;
+ }
+
+
/* Time of the last press event.
We reset this to zero when the button is released */
time_t time_at_last_press = 0;
+ int event_already_fired = 0;
+
fd = open("/dev/input/event1", O_RDONLY);
if (fd < 0) {
perror("Can't open /dev/input/event1 device");
@@ -79,14 +89,24 @@ int main(int argc, char **argv)
p.events = POLLIN;
while (1) {
- n = poll(&p, 1, -1);
+ /* Refresh every 20 ms if the user already started pressing the button */
+ n = poll(&p, 1, time_at_last_press==0 ? -1 : 20);
if (n < 0) {
perror("Failed to poll /dev/input/event1 device");
break;
}
-
- if (n == 0)
+ if (n==0) {
+ /* Poll timed out */
+ gettimeofday(&tv, NULL);
+ if (tv.tv_sec - time_at_last_press >= EDISON_OOBE_PRESS_TIMEOUT && event_already_fired == 0)
+ {
+ event_already_fired = 1;
+ printf("Edison PWR button was pressed more than 2s\n");
+ fflush(stdout);
+ system(argv[1]);
+ }
continue;
+ }
len = read(fd, &event, sizeof(event));
if (len < 0) {
@@ -99,7 +119,7 @@ int main(int argc, char **argv)
break;
}
- /* ignore non KEY event, and non RM button events */
+ /* ignore non KEY event, and non PWR button events */
if (event.type != EV_KEY || event.code != KEY_POWER)
continue;
@@ -116,6 +136,7 @@ int main(int argc, char **argv)
{
case 1: /* Regular press */
assert(time_at_last_press==0);
+ assert(event_already_fired==0);
time_at_last_press = tv.tv_sec;
break;
case 2: /* Auto repeat press */
@@ -126,14 +147,14 @@ int main(int argc, char **argv)
}
break;
case 0: /* Release */
- if (tv.tv_sec - time_at_last_press >= EDISON_OOBE_PRESS_TIMEOUT)
+ if (event_already_fired != 0)
{
- time_at_last_press = 0;
- printf("Edison PWR button was pressed more than 2s, starting OOBE service..\n");
+ printf("Edison PWR button was pressed more than 2s and released\n");
fflush(stdout);
- system(CALLED_COMMAND_ON_TIMEOUT);
+ system(argv[2]);
}
time_at_last_press = 0;
+ event_already_fired = 0;
break;
default:
printf("Warning: unhandled PWR button event value: %u\n", event.value);
diff --git a/device-software/meta-edison-distro/recipes-support/pwr-button-handler/files/pwr-button-handler.service b/device-software/meta-edison-distro/recipes-support/pwr-button-handler/files/pwr-button-handler.service
index 48e9266..a53c10b 100644
--- a/device-software/meta-edison-distro/recipes-support/pwr-button-handler/files/pwr-button-handler.service
+++ b/device-software/meta-edison-distro/recipes-support/pwr-button-handler/files/pwr-button-handler.service
@@ -2,7 +2,7 @@
Description=Edison PWR button handler
[Service]
-ExecStart=/usr/bin/pwr_button_handler
+ExecStart=/usr/bin/pwr_button_handler "/bin/systemctl start blink-led" "sh -c \"/bin/systemctl stop blink-led && /usr/bin/configure_edison --enableOneTimeSetup\""
Restart=on-failure
[Install]
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/c-ares/c-ares_1.10.0.bb b/device-software/meta-edison-middleware/recipes-connectivity/c-ares/c-ares_1.10.0.bb
new file mode 100644
index 0000000..0d1ef9d
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-connectivity/c-ares/c-ares_1.10.0.bb
@@ -0,0 +1,13 @@
+DESCRIPTION = "C library for asynchronous DNS requests (including name resolves)"
+HOMEPAGE = "http://c-ares.haxx.se/"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://README;beginline=17;endline=23;md5=d08205a43bc63c12cf394ac1d2cce7c3"
+
+PR = "r0"
+
+SRC_URI = "http://c-ares.haxx.se/download/c-ares-${PV}.tar.gz"
+
+SRC_URI[md5sum] = "1196067641411a75d3cbebe074fd36d8"
+SRC_URI[sha256sum] = "3d701674615d1158e56a59aaede7891f2dde3da0f46a6d3c684e0ae70f52d3db"
+
+inherit autotools
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/mdns/files/build.patch b/device-software/meta-edison-middleware/recipes-connectivity/mdns/files/build.patch
new file mode 100644
index 0000000..a1a2c89
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-connectivity/mdns/files/build.patch
@@ -0,0 +1,191 @@
+--- a/Clients/Makefile
++++ b/Clients/Makefile
+@@ -30,9 +30,17 @@ TARGETS = build/dns-sd build/dns-sd64
+ LIBS =
+ else
+ TARGETS = build/dns-sd
++# Set up diverging paths for debug vs. prod builds
++DEBUG?=1
++ifeq ($(DEBUG),1)
++LIBS = -L../mDNSPosix/build/debug/ -ldns_sd
++else
+ LIBS = -L../mDNSPosix/build/prod/ -ldns_sd
+ endif
+
++
++endif
++
+ all: $(TARGETS)
+
+ clean:
+@@ -42,10 +50,10 @@ build:
+ mkdir build
+
+ build/dns-sd: build dns-sd.c ClientCommon.c
+- cc $(filter %.c %.o, $+) $(LIBS) -I../mDNSShared -Wall -o $@
++ $(CC) $(filter %.c %.o, $+) $(LIBS) -I../mDNSShared -Wall -o $@
+
+ build/dns-sd64: build dns-sd.c ClientCommon.c
+- cc $(filter %.c %.o, $+) $(LIBS) -I../mDNSShared -Wall -o $@ -m64
++ $(CC) $(filter %.c %.o, $+) $(LIBS) -I../mDNSShared -Wall -o $@ -m64
+
+ # Note, we can make a 'fat' version of dns-sd using 'lipo', as shown below, but we
+ # don't, because we don't want or need a 'fat' version of dns-sd, because it will
+--- a/mDNSPosix/Makefile
++++ b/mDNSPosix/Makefile
+@@ -50,6 +50,7 @@
+
+ LIBVERS = 1
+
++POSIXDIR = ../mDNSPosix
+ COREDIR = ../mDNSCore
+ SHAREDDIR ?= ../mDNSShared
+ JDK = /usr/jdk
+@@ -57,11 +58,11 @@ JDK = /usr/jdk
+ CC = @cc
+ BISON = @bison
+ FLEX = @flex
+-LD = ld -shared
++LD =@LD
+ CP = cp
+ RM = rm
+ LN = ln -s -f
+-CFLAGS_COMMON = -I$(COREDIR) -I$(SHAREDDIR) -I$(OBJDIR) -fwrapv -W -Wall -DPID_FILE=\"/var/run/mdnsd.pid\" -DMDNS_UDS_SERVERPATH=\"/var/run/mdnsd\"
++CFLAGS_COMMON = -I$(POSIXDIR) -I$(COREDIR) -I$(SHAREDDIR) -I$(OBJDIR) -fwrapv -W -Wall -DPID_FILE=\"/var/run/mdnsd.pid\" -DMDNS_UDS_SERVERPATH=\"/var/run/mdnsd\"
+ CFLAGS_PTHREAD =
+ LINKOPTS =
+ LINKOPTS_PTHREAD = -lpthread
+@@ -69,7 +70,7 @@ LDSUFFIX = so
+ JAVACFLAGS_OS = -fPIC -shared -ldns_sd
+
+ # Set up diverging paths for debug vs. prod builds
+-DEBUG=0
++DEBUG?=1
+ ifeq ($(DEBUG),1)
+ CFLAGS_DEBUG = -g -DMDNS_DEBUGMSGS=2
+ OBJDIR = objects/debug
+@@ -103,6 +104,7 @@ else
+ ifeq ($(findstring linux,$(os)),linux)
+ CFLAGS_OS = -D_GNU_SOURCE -DHAVE_IPV6 -DNOT_HAVE_SA_LEN -DUSES_NETLINK -DHAVE_LINUX -DTARGET_OS_LINUX -fno-strict-aliasing
+ LD = gcc -shared
++LINKOPTS = --hash-style=gnu
+ FLEXFLAGS_OS = -l
+ JAVACFLAGS_OS += -I$(JDK)/include/linux
+
+@@ -210,7 +212,7 @@ endif
+ endif
+ endif
+
+-CFLAGS = $(CFLAGS_COMMON) $(CFLAGS_OS) $(CFLAGS_DEBUG)
++CFLAGS_BUILD = $(CFLAGS) $(CFLAGS_COMMON) $(CFLAGS_OS) $(CFLAGS_DEBUG)
+
+ #############################################################################
+
+@@ -246,8 +248,7 @@ Daemon: setup $(BUILDDIR)/mdnsd
+ @echo "Responder daemon done"
+
+ $(BUILDDIR)/mdnsd: $(DAEMONOBJS)
+- $(CC) -o $@ $+ $(LINKOPTS)
+- @$(STRIP) $@
++ $(CC) -o $@ $+
+
+ # libdns_sd target builds the client library
+ libdns_sd: setup $(BUILDDIR)/libdns_sd.$(LDSUFFIX)
+@@ -256,22 +257,18 @@ libdns_sd: setup $(BUILDDIR)/libdns_sd.$
+ CLIENTLIBOBJS = $(OBJDIR)/dnssd_clientlib.c.so.o $(OBJDIR)/dnssd_clientstub.c.so.o $(OBJDIR)/dnssd_ipc.c.so.o
+
+ $(BUILDDIR)/libdns_sd.$(LDSUFFIX): $(CLIENTLIBOBJS)
+- @$(LD) $(LINKOPTS) -o $@ $+
+- @$(STRIP) $@
++ $(LD) -shared $(LINKOPTS) -o $@ $+
+
+-Clients: setup libdns_sd ../Clients/build/dns-sd
++Clients: setup libdns_sd
++ @$(MAKE) -C ../Clients DEBUG=${DEBUG}
+ @echo "Clients done"
+
+-../Clients/build/dns-sd:
+- @$(MAKE) -C ../Clients
+-
+ # nss_mdns target builds the Name Service Switch module
+ nss_mdns: setup $(BUILDDIR)/$(NSSLIBFILE)
+ @echo "Name Service Switch module done"
+
+ $(BUILDDIR)/$(NSSLIBFILE): $(CLIENTLIBOBJS) $(OBJDIR)/nss_mdns.c.so.o
+- @$(LD) $(LINKOPTS) -o $@ $+
+- @$(STRIP) $@
++ $(LD) -shared $(LINKOPTS) -o $@ $+
+
+ #############################################################################
+
+@@ -469,55 +466,55 @@ dnsextd: setup $(BUILDDIR)/dnsextd
+ @echo "dnsextd done"
+
+ $(BUILDDIR)/mDNSClientPosix: $(APPOBJ) $(OBJDIR)/Client.c.o
+- $(CC) $+ -o $@ $(LINKOPTS)
++ $(CC) $+ -o $@
+
+ $(BUILDDIR)/mDNSResponderPosix: $(COMMONOBJ) $(OBJDIR)/Responder.c.o
+- $(CC) $+ -o $@ $(LINKOPTS)
++ $(CC) $+ -o $@
+
+ $(BUILDDIR)/mDNSProxyResponderPosix: $(COMMONOBJ) $(OBJDIR)/ProxyResponder.c.o
+- $(CC) $+ -o $@ $(LINKOPTS)
++ $(CC) $+ -o $@
+
+ $(BUILDDIR)/mDNSIdentify: $(SPECIALOBJ) $(OBJDIR)/Identify.c.o
+- $(CC) $+ -o $@ $(LINKOPTS)
++ $(CC) $+ -o $@
+
+ $(OBJDIR)/Identify.c.o: $(COREDIR)/mDNS.c # Note: Identify.c textually imports mDNS.c
+
+ $(BUILDDIR)/mDNSNetMonitor: $(SPECIALOBJ) $(OBJDIR)/NetMonitor.c.o
+- $(CC) $+ -o $@ $(LINKOPTS)
++ $(CC) $+ -o $@
+
+ $(OBJDIR)/NetMonitor.c.o: $(COREDIR)/mDNS.c # Note: NetMonitor.c textually imports mDNS.c
+
+ $(BUILDDIR)/dnsextd: $(DNSEXTDOBJ) $(OBJDIR)/dnsextd.c.threadsafe.o
+- $(CC) $+ -o $@ $(LINKOPTS) $(LINKOPTS_PTHREAD)
++ $(CC) $+ -o $@ $(LINKOPTS_PTHREAD)
+
+ #############################################################################
+
+ # Implicit rules
+ $(OBJDIR)/%.c.o: %.c
+- $(CC) $(CFLAGS) -c -o $@ $<
++ $(CC) $(CFLAGS_BUILD) -c -o $@ $<
+
+ $(OBJDIR)/%.c.o: $(COREDIR)/%.c
+- $(CC) $(CFLAGS) -c -o $@ $<
++ $(CC) $(CFLAGS_BUILD) -c -o $@ $<
+
+ $(OBJDIR)/%.c.o: $(SHAREDDIR)/%.c
+- $(CC) $(CFLAGS) -c -o $@ $<
++ $(CC) $(CFLAGS_BUILD) -c -o $@ $<
+
+ $(OBJDIR)/%.c.threadsafe.o: %.c
+- $(CC) $(CFLAGS) $(CFLAGS_PTHREAD) -D_REENTRANT -c -o $@ $<
++ $(CC) $(CFLAGS_BUILD) $(CFLAGS_PTHREAD) -D_REENTRANT -c -o $@ $<
+
+ $(OBJDIR)/%.c.threadsafe.o: $(SHAREDDIR)/%.c
+- $(CC) $(CFLAGS) $(CFLAGS_PTHREAD) -D_REENTRANT -c -o $@ $<
++ $(CC) $(CFLAGS_BUILD) $(CFLAGS_PTHREAD) -D_REENTRANT -c -o $@ $<
+
+ $(OBJDIR)/%.c.so.o: %.c
+- $(CC) $(CFLAGS) -c -fPIC -o $@ $<
++ $(CC) $(CFLAGS_BUILD) -c -fPIC -o $@ $<
+
+ $(OBJDIR)/%.c.so.o: $(SHAREDDIR)/%.c
+- $(CC) $(CFLAGS) -c -fPIC -o $@ $<
++ $(CC) $(CFLAGS_BUILD) -c -fPIC -o $@ $<
+
+ $(OBJDIR)/%.y.o: $(SHAREDDIR)/%.y
+ $(BISON) -o $(OBJDIR)/$*.c -d $<
+- $(CC) $(CFLAGS) -c -o $@ $(OBJDIR)/$*.c
++ $(CC) $(CFLAGS_BUILD) -c -o $@ $(OBJDIR)/$*.c
+
+ $(OBJDIR)/%.l.o: $(SHAREDDIR)/%.l
+ $(FLEX) $(FLEXFLAGS_OS) -i -o$(OBJDIR)/$*.l.c $<
+- $(CC) $(CFLAGS) -Wno-error -c -o $@ $(OBJDIR)/$*.l.c
++ $(CC) $(CFLAGS_BUILD) -Wno-error -c -o $@ $(OBJDIR)/$*.l.c
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/mdns/files/mdns.service b/device-software/meta-edison-middleware/recipes-connectivity/mdns/files/mdns.service
index 5732e78..531d142 100644
--- a/device-software/meta-edison-middleware/recipes-connectivity/mdns/files/mdns.service
+++ b/device-software/meta-edison-middleware/recipes-connectivity/mdns/files/mdns.service
@@ -3,7 +3,11 @@ Description=Zero-configuration networking
After=network.target
[Service]
+Type=forking
+ExecStartPre=/bin/rm -f /var/run/mdnsd.pid
ExecStart=/usr/sbin/mdnsd
+ExecReload=/bin/kill -HUP $MAINPID
+PIDFile=/var/run/mdnsd.pid
Restart=always
RestartSec=10s
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/mdns/mdns_544.bb b/device-software/meta-edison-middleware/recipes-connectivity/mdns/mdns_544.bb
index e1633b1..1d3f0bd 100644
--- a/device-software/meta-edison-middleware/recipes-connectivity/mdns/mdns_544.bb
+++ b/device-software/meta-edison-middleware/recipes-connectivity/mdns/mdns_544.bb
@@ -1,28 +1,33 @@
DESCRIPTION = "Bonjour, also known as zero-configuration networking, enables automatic discovery of computers, devices, and services on IP networks."
HOMEPAGE = "http://developer.apple.com/networking/bonjour/"
LICENSE = "Apache-2.0"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=31c50371921e0fb731003bbc665f29bf"
-S = "${EDISONREPO_TOP_DIR}/mw/mdns"
+PR = "r1"
-SRC_URI = "file://mdns.service"
-
-LIC_FILES_CHKSUM = " \
- file://LICENSE;md5=31c50371921e0fb731003bbc665f29bf \
+SRC_URI = "http://opensource.apple.com/tarballs/mDNSResponder/mDNSResponder-${PV}.tar.gz \
+ file://build.patch \
+ file://mdns.service \
"
+SRC_URI[md5sum] = "39142ab70bd82a096801ce346f86cbab"
+SRC_URI[sha256sum] = "c6ad1d53c28d28c0e3689bdf5efd9ce6f5c4c3692e8ad76e5eeb4d0c248929ac"
+
PARALLEL_MAKE = ""
+S = "${WORKDIR}/mDNSResponder-544"
+
do_compile() {
cd mDNSPosix
- oe_runmake os=linux
+ oe_runmake os=linux DEBUG=0
}
do_install () {
install -d ${D}${sbindir}
- install -m 0755 mDNSPosix/build/debug/mdnsd ${D}${sbindir}
+ install -m 0755 mDNSPosix/build/prod/mdnsd ${D}${sbindir}
install -d ${D}${libdir}
- cp mDNSPosix/build/debug/libdns_sd.so ${D}${libdir}/libdns_sd.so.1
+ cp mDNSPosix/build/prod/libdns_sd.so ${D}${libdir}/libdns_sd.so.1
chmod 0644 ${D}${libdir}/libdns_sd.so.1
ln -s libdns_sd.so.1 ${D}${libdir}/libdns_sd.so
@@ -36,7 +41,7 @@ do_install () {
install -m 0755 Clients/build/dns-sd ${D}${bindir}
install -d ${D}${libdir}
- oe_libinstall -C mDNSPosix/build/debug -so libnss_mdns-0.2 ${D}${libdir}
+ oe_libinstall -C mDNSPosix/build/prod -so libnss_mdns-0.2 ${D}${libdir}
ln -s libnss_mdns-0.2.so ${D}${libdir}/libnss_mdns.so.2
install -d ${D}${sysconfdir}
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/mosquitto/files/build.patch b/device-software/meta-edison-middleware/recipes-connectivity/mosquitto/files/build.patch
new file mode 100644
index 0000000..48c0653
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-connectivity/mosquitto/files/build.patch
@@ -0,0 +1,71 @@
+Index: mosquitto-1.3.4/client/Makefile
+===================================================================
+--- mosquitto-1.3.4.orig/client/Makefile
++++ mosquitto-1.3.4/client/Makefile
+@@ -21,8 +21,8 @@ sub_client.o : sub_client.c ../lib/libmo
+
+ install : all
+ $(INSTALL) -d ${DESTDIR}$(prefix)/bin
+- $(INSTALL) -s --strip-program=$(STRIP) mosquitto_pub ${DESTDIR}${prefix}/bin/mosquitto_pub
+- $(INSTALL) -s --strip-program=$(STRIP) mosquitto_sub ${DESTDIR}${prefix}/bin/mosquitto_sub
++ $(INSTALL) mosquitto_pub ${DESTDIR}${prefix}/bin/mosquitto_pub
++ $(INSTALL) mosquitto_sub ${DESTDIR}${prefix}/bin/mosquitto_sub
+
+ uninstall :
+ -rm -f ${DESTDIR}${prefix}/bin/mosquitto_pub
+Index: mosquitto-1.3.4/config.mk
+===================================================================
+--- mosquitto-1.3.4.orig/config.mk
++++ mosquitto-1.3.4/config.mk
+@@ -213,7 +213,7 @@ endif
+
+
+ INSTALL?=install
+-prefix=/usr/local
++prefix=/usr
+ mandir=${prefix}/share/man
+ localedir=${prefix}/share/locale
+ STRIP?=strip
+Index: mosquitto-1.3.4/lib/Makefile
+===================================================================
+--- mosquitto-1.3.4.orig/lib/Makefile
++++ mosquitto-1.3.4/lib/Makefile
+@@ -25,7 +25,7 @@ all : libmosquitto.so.${SOVERSION} libmo
+
+ install : all
+ $(INSTALL) -d ${DESTDIR}$(prefix)/lib${LIB_SUFFIX}/
+- $(INSTALL) -s --strip-program=$(STRIP) libmosquitto.so.${SOVERSION} ${DESTDIR}${prefix}/lib${LIB_SUFFIX}/libmosquitto.so.${SOVERSION}
++ $(INSTALL) libmosquitto.so.${SOVERSION} ${DESTDIR}${prefix}/lib${LIB_SUFFIX}/libmosquitto.so.${SOVERSION}
+ ln -sf libmosquitto.so.${SOVERSION} ${DESTDIR}${prefix}/lib${LIB_SUFFIX}/libmosquitto.so
+ $(INSTALL) -d ${DESTDIR}${prefix}/include/
+ $(INSTALL) mosquitto.h ${DESTDIR}${prefix}/include/mosquitto.h
+Index: mosquitto-1.3.4/lib/cpp/Makefile
+===================================================================
+--- mosquitto-1.3.4.orig/lib/cpp/Makefile
++++ mosquitto-1.3.4/lib/cpp/Makefile
+@@ -10,7 +10,7 @@ all : libmosquittopp.so.${SOVERSION}
+
+ install : all
+ $(INSTALL) -d ${DESTDIR}$(prefix)/lib${LIB_SUFFIX}/
+- $(INSTALL) -s --strip-program=$(STRIP) libmosquittopp.so.${SOVERSION} ${DESTDIR}${prefix}/lib${LIB_SUFFIX}/libmosquittopp.so.${SOVERSION}
++ $(INSTALL) libmosquittopp.so.${SOVERSION} ${DESTDIR}${prefix}/lib${LIB_SUFFIX}/libmosquittopp.so.${SOVERSION}
+ ln -sf libmosquittopp.so.${SOVERSION} ${DESTDIR}${prefix}/lib${LIB_SUFFIX}/libmosquittopp.so
+ $(INSTALL) -d ${DESTDIR}${prefix}/include/
+ $(INSTALL) mosquittopp.h ${DESTDIR}${prefix}/include/mosquittopp.h
+Index: mosquitto-1.3.4/src/Makefile
+===================================================================
+--- mosquitto-1.3.4.orig/src/Makefile
++++ mosquitto-1.3.4/src/Makefile
+@@ -100,10 +100,10 @@ mosquitto_passwd.o : mosquitto_passwd.c
+
+ install : all
+ $(INSTALL) -d ${DESTDIR}$(prefix)/sbin
+- $(INSTALL) -s --strip-program=$(STRIP) mosquitto ${DESTDIR}${prefix}/sbin/mosquitto
++ $(INSTALL) mosquitto ${DESTDIR}${prefix}/sbin/mosquitto
+ $(INSTALL) mosquitto_plugin.h ${DESTDIR}${prefix}/include/mosquitto_plugin.h
+ ifeq ($(WITH_TLS),yes)
+- $(INSTALL) -s --strip-program=$(STRIP) mosquitto_passwd ${DESTDIR}${prefix}/bin/mosquitto_passwd
++ $(INSTALL) mosquitto_passwd ${DESTDIR}${prefix}/bin/mosquitto_passwd
+ endif
+
+ uninstall :
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/mosquitto/files/mosquitto.service b/device-software/meta-edison-middleware/recipes-connectivity/mosquitto/files/mosquitto.service
new file mode 100644
index 0000000..25f68fa
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-connectivity/mosquitto/files/mosquitto.service
@@ -0,0 +1,15 @@
+[Unit]
+Description=Mosquitto - lightweight server implementation of the MQTT and MQTT-SN protocols
+ConditionPathExists=/etc/mosquitto/mosquitto.conf
+After=network.target
+
+[Service]
+Type=simple
+ExecStartPre=/bin/rm -f /var/run/mosquitto.pid
+ExecStart=/usr/sbin/mosquitto -c /etc/mosquitto/mosquitto.conf
+ExecReload=/bin/kill -HUP $MAINPID
+PIDFile=/var/run/mosquitto.pid
+Restart=on-failure
+
+[Install]
+WantedBy=multi-user.target
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/mosquitto/mosquitto_1.3.4.bb b/device-software/meta-edison-middleware/recipes-connectivity/mosquitto/mosquitto_1.3.4.bb
new file mode 100644
index 0000000..84c3307
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-connectivity/mosquitto/mosquitto_1.3.4.bb
@@ -0,0 +1,55 @@
+SUMMARY = "Open source MQTT v3.1 implemention"
+DESCRIPTION = "Mosquitto is an open source (BSD licensed) message broker that implements the MQ Telemetry Transport protocol version 3.1. MQTT provides a lightweight method of carrying out messaging using a publish/subscribe model. "
+HOMEPAGE = "http://mosquitto.org/"
+SECTION = "console/network"
+LICENSE = "BSD"
+LIC_FILES_CHKSUM = "file://LICENSE.txt;md5=89aa5ea5f32e4260d84c5d185ee3add4"
+
+DEPENDS = "openssl c-ares"
+
+PR = "r0"
+
+SRC_URI = "http://mosquitto.org/files/source/mosquitto-${PV}.tar.gz \
+ file://build.patch \
+ file://mosquitto.service \
+"
+
+SRC_URI[md5sum] = "9d729849efd74c6e3eee17a4a002e1e9"
+SRC_URI[sha256sum] = "0a3982d6b875a458909c8828731da04772035468700fa7eb2f0885f4bd6d0dbc"
+
+inherit autotools
+
+do_install_append () {
+ install -d ${D}${libbir}
+ install -m 0644 lib/libmosquitto.a ${D}${libdir}/
+
+ install -d ${D}${systemd_unitdir}/system/
+ install -m 0644 ${WORKDIR}/mosquitto.service ${D}${systemd_unitdir}/system/
+
+ cp ${D}${sysconfdir}/mosquitto/mosquitto.conf.example ${D}${sysconfdir}/mosquitto/mosquitto.conf
+ sed 's/#user mosquitto/user root/' -i ${D}${sysconfdir}/mosquitto/mosquitto.conf
+}
+
+PACKAGES += "libmosquitto1 libmosquittopp1 ${PN}-clients ${PN}-python"
+
+FILES_${PN} = "${sbindir}/mosquitto \
+ ${bindir}/mosquitto_passwd \
+ ${sysconfdir} \
+ ${systemd_unitdir}/system/mosquitto.service \
+"
+
+FILES_libmosquitto1 = "${libdir}/libmosquitto.so.1"
+
+FILES_libmosquittopp1 = "${libdir}/libmosquittopp.so.1"
+
+FILES_${PN}-clients = "${bindir}/mosquitto_pub \
+ ${bindir}/mosquitto_sub \
+"
+
+FILES_${PN}-staticdev += "${libdir}/libmosquitto.a"
+
+FILES_${PN}-python = "/usr/lib/python2.7/site-packages"
+
+inherit systemd
+
+SYSTEMD_SERVICE_${PN} = "mosquitto.service"
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/paho-mqtt/files/makefile.patch b/device-software/meta-edison-middleware/recipes-connectivity/paho-mqtt/files/makefile.patch
new file mode 100644
index 0000000..4d1e25b
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-connectivity/paho-mqtt/files/makefile.patch
@@ -0,0 +1,19 @@
+---
+ Makefile | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/Makefile b/Makefile
+index 33bd2d0..84262bd 100644
+--- a/Makefile
++++ b/Makefile
+@@ -115,7 +115,8 @@ LDFLAGS_AS = -shared -Wl,-soname,lib${MQTTLIB_AS}.so.${MAJOR_VERSION} -lpthread
+
+ all: build
+
+-build: | mkdir ${MQTTLIB_C_TARGET} ${MQTTLIB_CS_TARGET} ${MQTTLIB_A_TARGET} ${MQTTLIB_AS_TARGET} ${MQTTVERSION_TARGET} ${SYNC_SAMPLES} ${ASYNC_SAMPLES} ${SYNC_TESTS} ${SYNC_SSL_TESTS} ${ASYNC_TESTS} ${ASYNC_SSL_TESTS}
++build: | mkdir ${MQTTLIB_C_TARGET} ${MQTTLIB_CS_TARGET} ${MQTTLIB_A_TARGET} ${MQTTLIB_AS_TARGET}
++#${MQTTVERSION_TARGET} ${SYNC_SAMPLES} ${ASYNC_SAMPLES} ${SYNC_TESTS} ${SYNC_SSL_TESTS} ${ASYNC_TESTS} ${ASYNC_SSL_TESTS}
+
+ clean:
+ rm -rf ${blddir}/*
+--
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/paho-mqtt/paho-mqtt_3.1.bb b/device-software/meta-edison-middleware/recipes-connectivity/paho-mqtt/paho-mqtt_3.1.bb
index 7f3bd2f..37cab21 100644
--- a/device-software/meta-edison-middleware/recipes-connectivity/paho-mqtt/paho-mqtt_3.1.bb
+++ b/device-software/meta-edison-middleware/recipes-connectivity/paho-mqtt/paho-mqtt_3.1.bb
@@ -1,13 +1,24 @@
DESCRIPTION = "Paho MQTT - user libraries for the MQTT and MQTT-SN protocols"
+DESCRIPTION = "Client implementation of open and standard messaging protocols for Machine-to-Machine (M2M) and Internet of Things (IoT)."
+HOMEPAGE = "http://www.eclipse.org/paho/"
+SECTION = "console/network"
LICENSE = "EPL-1.0 | EDL-1.0"
-S = "${EDISONREPO_TOP_DIR}/mw/mqtt"
-
LIC_FILES_CHKSUM = " \
- file://edl-v10;md5=3adfcc70f5aeb7a44f3f9b495aa1fbf3 \
- file://epl-v10;md5=659c8e92a40b6df1d9e3dccf5ae45a08 \
+ file://edl-v10;md5=3adfcc70f5aeb7a44f3f9b495aa1fbf3 \
+ file://epl-v10;md5=659c8e92a40b6df1d9e3dccf5ae45a08 \
+"
+
+PR = "r1"
+
+SRC_URI = "git://git.eclipse.org/gitroot/paho/org.eclipse.paho.mqtt.c.git;protocol=http \
+ file://makefile.patch \
"
+SRCREV = "93a064dbe9fd2fc84b8bb2701e10d2de8004a11c"
+
+S = "${WORKDIR}/git"
+
do_compile() {
oe_runmake
}
@@ -25,4 +36,4 @@ do_install() {
}
DEPENDS = "openssl"
-
+RDEPENDS_${PN} = "openssl"
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/sshpass/sshpass.inc b/device-software/meta-edison-middleware/recipes-connectivity/sshpass/sshpass.inc
new file mode 100644
index 0000000..b19ae43
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-connectivity/sshpass/sshpass.inc
@@ -0,0 +1,10 @@
+DESCRIPTION = "Non-interactive ssh password auth"
+HOMEPAGE = "http://sshpass.sourceforge.net/"
+SECTION = "console/network"
+LICENSE = "GPLv2"
+
+SRC_URI = "${SOURCEFORGE_MIRROR}/sshpass/sshpass-${PV}.tar.gz"
+
+INC_PR = "r0"
+
+inherit autotools
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/sshpass/sshpass_1.05.bb b/device-software/meta-edison-middleware/recipes-connectivity/sshpass/sshpass_1.05.bb
new file mode 100644
index 0000000..a345dbd
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-connectivity/sshpass/sshpass_1.05.bb
@@ -0,0 +1,8 @@
+PR = "${INC_PR}.0"
+
+require sshpass.inc
+
+LIC_FILES_CHKSUM = "file://COPYING;md5=94d55d512a9ba36caa9b7df079bae19f"
+
+SRC_URI[md5sum] = "c52d65fdee0712af6f77eb2b60974ac7"
+SRC_URI[sha256sum] = "c3f78752a68a0c3f62efb3332cceea0c8a1f04f7cf6b46e00ec0c3000bc8483e"
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/zeromq/cppzmq_git.bb b/device-software/meta-edison-middleware/recipes-connectivity/zeromq/cppzmq_git.bb
new file mode 100644
index 0000000..26e89b1
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-connectivity/zeromq/cppzmq_git.bb
@@ -0,0 +1,19 @@
+DESCRIPTION = "C++ bindings for ZeroMQ"
+HOMEPAGE = "http://www.zeromq.org"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=db174eaf7b55a34a7c89551197f66e94"
+DEPENDS = "zeromq"
+SRCREV = "ee47ae4cddc304741526c9bb2035f98c3274e0ec"
+
+SRC_URI = "git://github.com/zeromq/cppzmq.git"
+
+S = "${WORKDIR}/git"
+
+do_install () {
+ install -d ${D}/usr/include
+ install -m 0755 ${S}/zmq.hpp ${D}/usr/include/
+}
+
+PACKAGES = "${PN}-dev"
+
+RDEPENDS_${PN}-dev = "zeromq-dev"
diff --git a/device-software/meta-edison-middleware/recipes-connectivity/zeromq/zeromq_4.0.4.bb b/device-software/meta-edison-middleware/recipes-connectivity/zeromq/zeromq_4.0.4.bb
index 64235d4..2b6b225 100644
--- a/device-software/meta-edison-middleware/recipes-connectivity/zeromq/zeromq_4.0.4.bb
+++ b/device-software/meta-edison-middleware/recipes-connectivity/zeromq/zeromq_4.0.4.bb
@@ -2,7 +2,7 @@ DESCRIPTION = "Zeromq - The Intelligent Transport Layer"
HOMEPAGE = "http://www.zeromq.org"
LICENSE = "LGPLv3+"
-PR = "r1"
+PR = "r2"
LIC_FILES_CHKSUM = " \
file://COPYING.LESSER;md5=d5311495d952062e0e4fbba39cbf3de1 \
@@ -13,7 +13,3 @@ SRC_URI[md5sum] = "f3c3defbb5ef6cc000ca65e529fdab3b"
SRC_URI[sha256sum] = "1ef71d46e94f33e27dd5a1661ed626cd39be4d2d6967792a275040e34457d399"
inherit autotools gettext
-
-do_configure_prepend() {
- ./autogen.sh
-}
diff --git a/device-software/meta-edison-middleware/recipes-core/images/edison-image.bbappend b/device-software/meta-edison-middleware/recipes-core/images/edison-image.bbappend
index 976bdf3..c43c465 100644
--- a/device-software/meta-edison-middleware/recipes-core/images/edison-image.bbappend
+++ b/device-software/meta-edison-middleware/recipes-core/images/edison-image.bbappend
@@ -1,19 +1,28 @@
IMAGE_INSTALL += "packagegroup-core-buildessential"
-IMAGE_INSTALL += "zeromq zeromq-dev"
-IMAGE_INSTALL += "rsmb"
-IMAGE_INSTALL += "nodejs"
-IMAGE_INSTALL += "paho-mqtt paho-mqtt-dev"
-IMAGE_INSTALL += "mdns mdns-dev"
+IMAGE_INSTALL += "iotkit-opkg"
+IMAGE_INSTALL += "zeromq-dev"
+IMAGE_INSTALL += "cppzmq-dev"
+IMAGE_INSTALL += "paho-mqtt-dev"
+IMAGE_INSTALL += "mdns-dev"
IMAGE_INSTALL += "iotkit-comm-js"
-IMAGE_INSTALL += "iotkit-comm-c iotkit-comm-c-dev"
+IMAGE_INSTALL += "iotkit-comm-c-dev"
IMAGE_INSTALL += "iotkit-agent"
+IMAGE_INSTALL += "iotkit-lib-c-dev"
IMAGE_INSTALL += "xdk-daemon"
IMAGE_INSTALL += "oobe"
+# mosquitto and dependencies
+IMAGE_INSTALL += "mosquitto-dev"
+IMAGE_INSTALL += "mosquitto-clients"
+
+# node and sub-components
+IMAGE_INSTALL += "nodejs-dev"
+IMAGE_INSTALL += "nodejs-npm"
+
# MRAA
-IMAGE_INSTALL += "mraa mraa-dev"
+IMAGE_INSTALL += "mraa-dev"
IMAGE_INSTALL += "mraa-doc"
# UPM
-IMAGE_INSTALL += "upm upm-dev"
+IMAGE_INSTALL += "upm-dev"
diff --git a/device-software/meta-edison-middleware/recipes-devtools/iotkit-agent/iotkit-agent_0.2.0.bb b/device-software/meta-edison-middleware/recipes-devtools/iotkit-agent/iotkit-agent_0.2.0.bb
new file mode 100644
index 0000000..29d7d70
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-devtools/iotkit-agent/iotkit-agent_0.2.0.bb
@@ -0,0 +1,84 @@
+DESCRIPTION = "Transparently implements the necessary message formats and transport security as well as device registration"
+HOMEPAGE = "http://enableiot.com"
+LICENSE = "BSD-2-Clause & BSD-3-Clause & GPL-2.0 & Apache-2.0 & MIT & PD"
+
+LIC_FILES_CHKSUM = "file://${WORKDIR}/git/LICENSE;md5=30c8ae0368f724cf5f753d08bf033034"
+
+DEPENDS = "nodejs-native"
+
+SRC_URI = "git://github.com/intel-iot-devkit/iotkit-agent.git;protocol=https;branch=dprelease;tag=prod-v${PV}"
+
+S = "${WORKDIR}/git"
+
+do_compile () {
+ # changing the home directory to the working directory, the .npmrc will be created in this directory
+ export HOME=${WORKDIR}
+
+ # does not build dev packages
+ npm config set dev false
+
+ # access npm registry using http
+ npm set strict-ssl false
+ npm config set registry http://registry.npmjs.org/
+
+ # configure http proxy if neccessary
+ if [ -n "${http_proxy}" ]; then
+ npm config set proxy ${http_proxy}
+ fi
+ if [ -n "${HTTP_PROXY}" ]; then
+ npm config set proxy ${HTTP_PROXY}
+ fi
+
+ # configure cache to be in working directory
+ npm set cache ${WORKDIR}/npm_cache
+
+ # clear local cache prior to each compile
+ npm cache clear
+
+ # compile and install node modules in source directory
+ npm --arch=${TARGET_ARCH} --production --verbose install
+}
+
+do_install () {
+ install -d ${D}${libdir}
+ install -d ${D}${libdir}/node_modules/
+ install -d ${D}${libdir}/node_modules/iotkit-agent/
+ install -d ${D}${sysconfdir}/iotkit-agent/
+ install -d ${D}${libdir}/node_modules/iotkit-agent/config/
+ install -m 0644 ${S}/package.json ${D}${libdir}/node_modules/iotkit-agent/
+ install -m 0644 ${S}/config/config.json ${D}${sysconfdir}/iotkit-agent/
+ install -d ${D}${datadir}/iotkit-agent/
+ install -d ${D}${bindir}
+
+ cp -r ${S}/node_modules ${D}${libdir}/node_modules/iotkit-agent/
+ cp -r ${S}/admin ${D}${libdir}/node_modules/iotkit-agent/
+ cp -r ${S}/api ${D}${libdir}/node_modules/iotkit-agent/
+ cp -r ${S}/bin ${D}${libdir}/node_modules/iotkit-agent/
+ cp -r ${S}/certs ${D}${datadir}/iotkit-agent/
+ cp -r ${S}/data ${D}${datadir}/iotkit-agent/
+ cp -r ${S}/lib ${D}${libdir}/node_modules/iotkit-agent/
+ cp -r ${S}/listeners ${D}${libdir}/node_modules/iotkit-agent/
+ install -m 0644 ${S}/config/index.js ${D}${libdir}/node_modules/iotkit-agent/config
+ install -m 0755 ${S}/iotkit-admin.js ${D}${libdir}/node_modules/iotkit-agent/
+ install -m 0755 ${S}/iotkit-agent.js ${D}${libdir}/node_modules/iotkit-agent/
+ ln -s ../lib/node_modules/iotkit-agent/iotkit-agent.js ${D}${bindir}/iotkit-agent
+ ln -s ../lib/node_modules/iotkit-agent/iotkit-admin.js ${D}${bindir}/iotkit-admin
+
+ install -d ${D}${systemd_unitdir}/system/
+ install -m 0644 ${S}/iotkit-agent.service ${D}${systemd_unitdir}/system/
+}
+
+inherit systemd
+
+# since the agent requires registration before running we don't want to start
+# the systemd service by default
+SYSTEMD_AUTO_ENABLE = "disable"
+SYSTEMD_SERVICE_${PN} = "iotkit-agent.service"
+
+FILES_${PN} = "${libdir}/node_modules/ \
+ ${bindir}/iotkit-agent \
+ ${bindir}/iotkit-admin \
+ ${datadir}/iotkit-agent/ \
+ ${sysconfdir}/iotkit-agent/"
+
+PACKAGES = "${PN}"
diff --git a/device-software/meta-edison-middleware/recipes-devtools/iotkit-comm-c/iotkit-comm-c_0.1.1.bb b/device-software/meta-edison-middleware/recipes-devtools/iotkit-comm-c/iotkit-comm-c_0.1.1.bb
index ffcb8f3..c1c0260 100644
--- a/device-software/meta-edison-middleware/recipes-devtools/iotkit-comm-c/iotkit-comm-c_0.1.1.bb
+++ b/device-software/meta-edison-middleware/recipes-devtools/iotkit-comm-c/iotkit-comm-c_0.1.1.bb
@@ -1,12 +1,17 @@
DESCRIPTION = "Inter of Things communication library for device-to-device and device-to-cloud messaging"
-LICENSE = "LGPLv2.1"
+LICENSE = "MIT"
-S = "${EDISONREPO_TOP_DIR}/mw/iecf-c"
+PR = "r2"
+
+SRC_URI = "git://github.com/intel-iot-devkit/iotkit-comm-c.git;protocol=git"
+SRCREV = "2367175b07852a8d2600677f5d893af49973f422"
LIC_FILES_CHKSUM = " \
- file://LICENSE;md5=1a6d268fd218675ffea8be556788b780 \
+ file://COPYING;md5=e8db6501ed294e65418a933925d12058 \
"
+S = "${WORKDIR}/git"
+
DEPENDS = "zeromq mdns paho-mqtt"
inherit pkgconfig cmake
@@ -33,7 +38,9 @@ do_install() {
install -d ${D}${libdir}
install ${B}/lib/libiotkit-comm/libiotkit-comm.so ${D}${libdir}/
install ${B}/lib/plugins/libiotkitpubsub/libiotkit-agent-client.so ${D}${libdir}/
+ install ${B}/lib/plugins/libiotkitpubsub/libiotkit-agent-service.so ${D}${libdir}/
install ${B}/lib/plugins/libmqttpubsub/libmqttpubsub-client.so ${D}${libdir}/
+ install ${B}/lib/plugins/libmqttpubsub/libmqttpubsub-service.so ${D}${libdir}/
install ${B}/lib/plugins/libzmqpubsub/libzmqpubsub-client.so ${D}${libdir}/
install ${B}/lib/plugins/libzmqpubsub/libzmqpubsub-service.so ${D}${libdir}/
install ${B}/lib/plugins/libzmqreqrep/libzmqreqrep-client.so ${D}${libdir}/
@@ -97,10 +104,10 @@ do_install() {
}
FILES_${PN} += "${libdir}"
-RDEPENDS_${PN} = "zeromq mdns paho-mqtt rsmb"
+RDEPENDS_${PN} = "zeromq mdns paho-mqtt mosquitto sshpass"
PACKAGES += "${PN}-tests"
-RDEPENDS_${PN}-tests += "${PN} gcov"
+RDEPENDS_${PN}-tests += "${PN} gcov cmake"
FILES_${PN}-dev = "${includedir} ${datadir}/iotkit-comm/examples/c/"
FILES_${PN}-dbg += "${datadir}/iotkit-comm/examples/c/.debug/ ${datadir}/iotkit-comm/tests/c/iotkitpubsub/.debug/ ${datadir}/iotkit-comm/tests/c/mqttpubsub/.debug/ ${datadir}/iotkit-comm/tests/c/zmqpubsub/.debug/ ${datadir}/iotkit-comm/tests/c/libiotkit-comm/.debug/ ${datadir}/iotkit-comm/tests/c/zmqreqrep/.debug/"
diff --git a/device-software/meta-edison-middleware/recipes-devtools/iotkit-comm-js/iotkit-comm-js_0.1.1.bb b/device-software/meta-edison-middleware/recipes-devtools/iotkit-comm-js/iotkit-comm-js_0.1.1.bb
index 864e46e..8b0d20f 100644
--- a/device-software/meta-edison-middleware/recipes-devtools/iotkit-comm-js/iotkit-comm-js_0.1.1.bb
+++ b/device-software/meta-edison-middleware/recipes-devtools/iotkit-comm-js/iotkit-comm-js_0.1.1.bb
@@ -1,12 +1,17 @@
DESCRIPTION = "Inter of Things communication library for device-to-device and device-to-cloud messaging"
-LICENSE = "LGPLv2.1"
+LICENSE = "MIT"
-S = "${EDISONREPO_TOP_DIR}/mw/iecf-js"
+PR = "r2"
+
+SRC_URI = "git://github.com/intel-iot-devkit/iotkit-comm-js.git;protocol=git"
+SRCREV = "5ccea56e88755c9f6e3cd37bb5fc5d747b8496aa"
LIC_FILES_CHKSUM = " \
- file://LICENSE;md5=1a6d268fd218675ffea8be556788b780 \
+ file://COPYING;md5=e8db6501ed294e65418a933925d12058 \
"
+S = "${WORKDIR}/git"
+
DEPENDS = "nodejs-native zeromq mdns paho-mqtt"
do_compile () {
@@ -35,14 +40,14 @@ do_compile () {
npm cache clear
# compile and install node modules in source directory
- npm --arch=${TARGET_ARCH} --production --verbose install
+ npm --arch=${TARGET_ARCH} --verbose install
}
do_install () {
install -d ${D}${libdir}/node_modules/iotkit-comm/
cp -r ${S}/node_modules ${D}${libdir}/node_modules/iotkit-comm/
install -m 644 ${S}/package.json ${D}${libdir}/node_modules/iotkit-comm/
- install -m 644 ${S}/LICENSE ${D}${libdir}/node_modules/iotkit-comm/
+ install -m 644 ${S}/COPYING ${D}${libdir}/node_modules/iotkit-comm/
install -m 644 ${S}/README.md ${D}${libdir}/node_modules/iotkit-comm/
install -m 644 ${S}/jsdoc-conf.json ${D}${libdir}/node_modules/iotkit-comm/
cp -r ${S}/lib ${D}${libdir}/node_modules/iotkit-comm/
@@ -50,12 +55,46 @@ do_install () {
cp -r ${S}/doc ${D}${libdir}/node_modules/iotkit-comm/
install -d ${D}${datadir}/iotkit-comm/examples/node
cp -r ${S}/example/* ${D}${datadir}/iotkit-comm/examples/node
+
+ chmod 755 ${D}${libdir}/node_modules/iotkit-comm/lib/setup.js
+ install -d ${D}${bindir}
+ ln -s ../lib/node_modules/iotkit-comm/lib/setup.js ${D}${bindir}/iotkit-comm
}
-INHIBIT_PACKAGE_DEBUG_SPLIT = "1"
INHIBIT_PACKAGE_STRIP = "1"
-FILES_${PN} = "${libdir}/node_modules/ ${datadir}/iotkit-comm/examples"
-RDEPENDS_${PN} = "nodejs zeromq mdns paho-mqtt rsmb"
+PACKAGES = "${PN} ${PN}-test-dependencies"
+
+FILES_${PN}-test-dependencies = " \
+ ${libdir}/node_modules/iotkit-comm/node_modules/.bin/istanbul \
+ ${libdir}/node_modules/iotkit-comm/node_modules/.bin/jsdoc \
+ ${libdir}/node_modules/iotkit-comm/node_modules/.bin/mocha \
+ ${libdir}/node_modules/iotkit-comm/node_modules/.bin/_mocha \
+ ${libdir}/node_modules/iotkit-comm/node_modules/chai/ \
+ ${libdir}/node_modules/iotkit-comm/node_modules/istanbul/ \
+ ${libdir}/node_modules/iotkit-comm/node_modules/jsdoc/ \
+ ${libdir}/node_modules/iotkit-comm/node_modules/mocha/ \
+"
+
+FILES_${PN} = " \
+ ${libdir}/node_modules/iotkit-comm/doc/ \
+ ${libdir}/node_modules/iotkit-comm/jsdoc-conf.json \
+ ${libdir}/node_modules/iotkit-comm/COPYING \
+ ${libdir}/node_modules/iotkit-comm/lib/ \
+ ${libdir}/node_modules/iotkit-comm/package.json \
+ ${libdir}/node_modules/iotkit-comm/README.md \
+ ${libdir}/node_modules/iotkit-comm/test \
+ ${libdir}/node_modules/iotkit-comm/node_modules/.bin/mqtt_pub \
+ ${libdir}/node_modules/iotkit-comm/node_modules/.bin/mqtt_sub \
+ ${libdir}/node_modules/iotkit-comm/node_modules/async/ \
+ ${libdir}/node_modules/iotkit-comm/node_modules/commander/ \
+ ${libdir}/node_modules/iotkit-comm/node_modules/mdns2/ \
+ ${libdir}/node_modules/iotkit-comm/node_modules/mqtt/ \
+ ${libdir}/node_modules/iotkit-comm/node_modules/read/ \
+ ${libdir}/node_modules/iotkit-comm/node_modules/zmq/ \
+ ${datadir}/iotkit-comm/examples/ \
+ ${bindir}/iotkit-comm \
+"
-PACKAGES = "${PN}"
+RDEPENDS_${PN} = "nodejs zeromq mdns paho-mqtt mosquitto sshpass"
+RDEPENDS_${PN}-test-dependencies = "${PN}"
diff --git a/device-software/meta-edison-middleware/recipes-devtools/iotkit-lib-c/iotkit-lib-c_0.1.0.bb b/device-software/meta-edison-middleware/recipes-devtools/iotkit-lib-c/iotkit-lib-c_0.1.0.bb
new file mode 100644
index 0000000..629cee7
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-devtools/iotkit-lib-c/iotkit-lib-c_0.1.0.bb
@@ -0,0 +1,49 @@
+SUMMARY = "Transparently implements the necessary message formats and transport security as well as device registration"
+SECTION = "libs"
+HOMEPAGE = "http://enableiot.com"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://COPYING;md5=e8db6501ed294e65418a933925d12058"
+
+DEPENDS = "nodejs-native swig-native curl"
+
+PR = "r1"
+
+SRC_URI = "git://github.com/enableiot/iotkit-lib-c.git;protocol=https;tag=v1.4.0"
+
+S = "${WORKDIR}/git"
+
+EXTRA_OECMAKE += " -DSTAGING_DIR_TARGET=${STAGING_DIR_TARGET}"
+
+inherit distutils-base pkgconfig python-dir cmake
+
+do_compile_prepend () {
+ # when yocto builds in ${D} it does not have access to ../git/.git so git
+ # describe --tags fails. In order not to tag our version as dirty we use this
+ # trick
+ sed -i 's/-dirty//' src/version.c
+}
+
+do_install_prepend () {
+ # Copy config file
+ install -d ${D}${sysconfdir}/iotkit-lib
+ install -d ${D}${datadir}/iotkit-lib
+ install -m 644 ${S}/config/config.json ${D}${sysconfdir}/iotkit-lib/
+
+ # Copy test programs
+ cp -r ${B}/tests/ ${D}${datadir}/iotkit-lib/
+ rm -rf ${D}${datadir}/iotkit-lib/tests/CMakeFiles/
+ touch ${D}${datadir}/iotkit-lib/.setup.done
+}
+
+PACKAGES =+ "${PN}-tests"
+
+FILES_${PN}-dbg += "${libdir}/node_modules/iotkitjs/.debug/ \
+ ${PYTHON_SITEPACKAGES_DIR}/.debug/ \
+ ${datadir}/iotkit-lib/tests/.debug/"
+
+FILES_${PN}-tests = "${datadir}/iotkit-lib/tests/*"
+
+FILES_${PN} += "${sysconfdir} \
+ ${datadir}/iotkit-lib/.setup.done"
+
+RDEPENDS_${PN}-tests += "${PN} gcov cmake"
diff --git a/device-software/meta-edison-middleware/recipes-devtools/iotkit-opkg/files/iotkit.conf b/device-software/meta-edison-middleware/recipes-devtools/iotkit-opkg/files/iotkit.conf
new file mode 100644
index 0000000..a44c5c0
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-devtools/iotkit-opkg/files/iotkit.conf
@@ -0,0 +1 @@
+src iotkit http://iotdk.intel.com/repos/1.1/intelgalactic
diff --git a/device-software/meta-edison-middleware/recipes-devtools/iotkit-opkg/iotkit-opkg_0.0.1.bb b/device-software/meta-edison-middleware/recipes-devtools/iotkit-opkg/iotkit-opkg_0.0.1.bb
new file mode 100644
index 0000000..019c9ba
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-devtools/iotkit-opkg/iotkit-opkg_0.0.1.bb
@@ -0,0 +1,22 @@
+DESCRIPTION="This configures the opkg sources for the iotkit packages"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+
+SRC_URI = " \
+ file://iotkit.conf \
+"
+
+PR = "r0"
+
+do_install() {
+ install -d ${D}${sysconfdir}/opkg
+ install -m 0644 ${WORKDIR}/iotkit.conf ${D}${sysconfdir}/opkg
+}
+
+
+RDEPENDS_${PN} = "opkg"
+
+FILES_${PN} = "${sysconfdir}/opkg"
+
+PACKAGES = "${PN}"
+
diff --git a/device-software/meta-edison-middleware/recipes-devtools/mraa/mraa_0.5.2.bb b/device-software/meta-edison-middleware/recipes-devtools/mraa/mraa_0.5.2.bb
new file mode 100644
index 0000000..787c36b
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-devtools/mraa/mraa_0.5.2.bb
@@ -0,0 +1,27 @@
+SUMMARY = "Low Level Skeleton Library for Communication on Intel platforms"
+SECTION = "libs"
+AUTHOR = "Brendan Le Foll, Tom Ingleby"
+
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://COPYING;md5=e8db6501ed294e65418a933925d12058"
+
+DEPENDS = "nodejs swig-native"
+
+SRC_URI = "git://github.com/intel-iot-devkit/mraa.git;protocol=git"
+SRCREV = "bb3228ad5854b5f289c32737a6a106b139e24a05"
+
+S = "${WORKDIR}/git"
+
+inherit distutils-base pkgconfig python-dir cmake
+
+FILES_${PN}-doc += "${datadir}/mraa/examples/"
+
+FILES_${PN}-dbg += "${libdir}/node_modules/mraajs/.debug/ \
+ ${PYTHON_SITEPACKAGES_DIR}/.debug/"
+
+do_compile_prepend () {
+ # when yocto builds in ${D} it does not have access to ../git/.git so git
+ # describe --tags fails. In order not to tag our version as dirty we use this
+ # trick
+ sed -i 's/-dirty//' src/version.c
+}
\ No newline at end of file
diff --git a/device-software/meta-edison-middleware/recipes-devtools/nodejs/nodejs_0.10.28.bb b/device-software/meta-edison-middleware/recipes-devtools/nodejs/nodejs_0.10.28.bb
index c2eb76f..a463bc8 100644
--- a/device-software/meta-edison-middleware/recipes-devtools/nodejs/nodejs_0.10.28.bb
+++ b/device-software/meta-edison-middleware/recipes-devtools/nodejs/nodejs_0.10.28.bb
@@ -7,6 +7,8 @@ LIC_FILES_CHKSUM = "file://LICENSE;md5=4a31e6c424761191227143b86f58a1ef"
DEPENDS = "openssl"
DEPENDS_class-target = "nodejs-native"
+PR = "r1"
+
SRC_URI = "git://github.com/joyent/node.git;protocol=https;branch=v0.10;tag=v0.10.28"
S = "${WORKDIR}/git"
@@ -20,8 +22,7 @@ ARCHFLAGS ?= ""
# Node is way too cool to use proper autotools, so we install two wrappers to forcefully inject proper arch cflags to workaround gypi
do_configure () {
export LD="${CXX}"
-
- ./configure --prefix=${prefix} --without-snapshot ${ARCHFLAGS}
+ ./configure --prefix=${prefix} --without-snapshot --shared-openssl ${ARCHFLAGS}
}
do_compile () {
@@ -50,6 +51,17 @@ do_install_append_class-target () {
fi
}
+do_install_append_class-native() {
+ # /usr/bin/npm is symlink to /usr/lib/node_modules/npm/bin/npm-cli.js
+ # use sed on npm-cli.js because otherwise symlink is replaced with normal file and
+ # npm-cli.js continues to use old shebang
+ sed "1s^.*^#\!/usr/bin/env node^g" -i ${D}${libdir}/node_modules/npm/bin/npm-cli.js
+}
+
+do_install_append_class-target() {
+ sed "1s^.*^#\!${bindir}/env node^g" -i ${D}${libdir}/node_modules/npm/bin/npm-cli.js
+}
+
pkg_postinst_${PN} () {
sed -e '/^PATH=/aNODE_PATH=\/usr\/lib\/node_modules\/' \
-e 's/\(^export\)\(.*\)/\1 NODE_PATH\2/' \
@@ -62,10 +74,12 @@ pkg_prerm_${PN} () {
-i $D/etc/profile
}
-RDEPENDS_${PN} = "curl python-shell python-datetime python-subprocess python-crypt python-textutils \
- python-netclient python-ctypes python-misc python-compiler python-multiprocessing"
-
+RDEPENDS_${PN} = "curl"
RDEPENDS_${PN}_class-native = ""
-FILES_${PN} += "${libdir}/node/wafadmin ${libdir}/node_modules ${libdir}/dtrace"
+PACKAGES += "${PN}-npm"
+FILES_${PN}-npm = "${libdir}/node_modules ${bindir}/npm"
+RDEPENDS_${PN}-npm = "python-shell python-datetime python-subprocess python-crypt python-textutils \
+ python-netclient python-ctypes python-misc python-compiler python-multiprocessing"
+
BBCLASSEXTEND = "native"
diff --git a/device-software/meta-edison-middleware/recipes-devtools/oobe/oobe_0.0.1.bb b/device-software/meta-edison-middleware/recipes-devtools/oobe/oobe_0.0.1.bb
index 92b4ec2..ebf73d0 100644
--- a/device-software/meta-edison-middleware/recipes-devtools/oobe/oobe_0.0.1.bb
+++ b/device-software/meta-edison-middleware/recipes-devtools/oobe/oobe_0.0.1.bb
@@ -1,21 +1,48 @@
DESCRIPTION="The out-of-box configuration service"
-LICENSE = "LGPLv2.1"
+LICENSE = "MIT"
S = "${EDISONREPO_TOP_DIR}/mw/oobe"
LIC_FILES_CHKSUM = " \
- file://LICENSE;md5=1a6d268fd218675ffea8be556788b780 \
+ file://LICENSE;md5=ea398a763463b76b18da15f013c0c531 \
"
DEPENDS = "nodejs-native"
do_compile() {
+ # changing the home directory to the working directory, the .npmrc will be created in this directory
+ export HOME=${WORKDIR}
+
+ # does not build dev packages
+ npm config set dev false
+
+ # access npm registry using http
+ npm set strict-ssl false
+ npm config set registry http://registry.npmjs.org/
+
+ # configure http proxy if neccessary
+ if [ -n "${http_proxy}" ]; then
+ npm config set proxy ${http_proxy}
+ fi
+ if [ -n "${HTTP_PROXY}" ]; then
+ npm config set proxy ${HTTP_PROXY}
+ fi
+
+ # configure cache to be in working directory
+ npm set cache ${WORKDIR}/npm_cache
+
+ # clear local cache prior to each compile
+ npm cache clear
+
+ # compile and install node modules in source directory
+ npm --arch=${TARGET_ARCH} --verbose install
}
do_install() {
install -d ${D}${libdir}/edison_config_tools
install -d ${D}/var/lib/edison_config_tools
cp -r ${S}/src/public ${D}${libdir}/edison_config_tools
+ cp -r ${S}/node_modules ${D}${libdir}/edison_config_tools
install -m 0644 ${S}/src/server.js ${D}${libdir}/edison_config_tools/edison-config-server.js
install -d ${D}${systemd_unitdir}/system/
install -m 0644 ${S}/src/edison_config.service ${D}${systemd_unitdir}/system/
diff --git a/device-software/meta-edison-middleware/recipes-devtools/upm/upm_0.1.8.bb b/device-software/meta-edison-middleware/recipes-devtools/upm/upm_0.1.8.bb
new file mode 100644
index 0000000..b259d42
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-devtools/upm/upm_0.1.8.bb
@@ -0,0 +1,17 @@
+SUMMARY = "Sensor/Actuator repository for Mraa"
+SECTION = "libs"
+AUTHOR = "Brendan Le Foll, Tom Ingleby, Yevgeniy Kiveisha"
+
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://COPYING;md5=e8db6501ed294e65418a933925d12058"
+
+DEPENDS = "nodejs swig-native mraa"
+
+SRC_URI = "git://github.com/intel-iot-devkit/upm.git;protocol=git"
+SRCREV = "88eaced5a23c23d1cfe3badfe8deeedda582ae50"
+
+S = "${WORKDIR}/git"
+
+inherit distutils-base pkgconfig python-dir cmake
+
+FILES_${PN}-doc += "${datadir}/upm/examples/"
\ No newline at end of file
diff --git a/device-software/meta-edison-middleware/recipes-devtools/xdk-daemon/xdk-daemon_0.0.27.bb b/device-software/meta-edison-middleware/recipes-devtools/xdk-daemon/xdk-daemon_0.0.27.bb
new file mode 100644
index 0000000..90eb588
--- /dev/null
+++ b/device-software/meta-edison-middleware/recipes-devtools/xdk-daemon/xdk-daemon_0.0.27.bb
@@ -0,0 +1,68 @@
+DESCRIPTION = "Provides communication to the Intel XDK"
+LICENSE = "Proprietary"
+
+LIC_FILES_CHKSUM = "file://LICENSE;md5=8a05f85865f8c4b9ba29798e539f93b7"
+
+DEPENDS = "nodejs-native mdns"
+RDEPENDS_${PN} = "libarchive-bin"
+
+PR = "r0"
+
+# URI should point to some external http:// server
+SRC_URI = "file://xdk-daemon-${PV}.tar.bz2"
+
+# we don't care about debug for the few binary node modules
+INHIBIT_PACKAGE_DEBUG_SPLIT = "1"
+
+do_compile () {
+ # changing the home directory to the working directory, the .npmrc will be created in this directory
+ export HOME=${WORKDIR}
+
+ # does not build dev packages
+ npm config set dev false
+
+ # access npm registry using http
+ npm set strict-ssl false
+ npm config set registry http://registry.npmjs.org/
+
+ # configure http proxy if neccessary
+ if [ -n "${http_proxy}" ]; then
+ npm config set proxy ${http_proxy}
+ fi
+ if [ -n "${HTTP_PROXY}" ]; then
+ npm config set proxy ${HTTP_PROXY}
+ fi
+
+ # configure cache to be in working directory
+ npm set cache ${WORKDIR}/npm_cache
+
+ # clear local cache prior to each compile
+ npm cache clear
+
+ npm install --arch=${TARGET_ARCH}
+ cd current/ && npm install --arch=${TARGET_ARCH}
+ cd node-inspector-server && npm install --arch=${TARGET_ARCH}
+
+ sed -i '/TM/d' ${S}/xdk-daemon
+}
+
+do_install () {
+ install -d ${D}/opt/xdk-daemon/
+ cp -a ${S}/* ${D}/opt/xdk-daemon/
+
+ install -d ${D}${systemd_unitdir}/system/
+ install -m 0644 ${S}/xdk-daemon.service ${D}${systemd_unitdir}/system/
+
+ install -d ${D}${bindir}
+ ln -s /opt/xdk-daemon/current/xdk-whitelist ${D}${bindir}/xdk-whitelist
+}
+
+inherit systemd
+
+SYSTEMD_SERVICE_${PN} = "xdk-daemon.service"
+
+FILES_${PN} = "/opt/xdk-daemon/ \
+ ${systemd_unitdir}/system/xdk-daemon.service \
+ ${bindir}/"
+
+PACKAGES = "${PN}"
diff --git a/device-software/meta-edison/conf/machine/edison.conf b/device-software/meta-edison/conf/machine/edison.conf
index 0dcd102..6bc5606 100644
--- a/device-software/meta-edison/conf/machine/edison.conf
+++ b/device-software/meta-edison/conf/machine/edison.conf
@@ -14,7 +14,7 @@ UBOOT_MACHINE = "edison_config"
module_autoload_bcm_bt_lpm = "bcm_bt_lpm"
module_autoload_bcm4334x = "bcm4334x"
-module_conf_bcm4334x = "options bcm4334x firmware_path=/etc/firmware/fw_bcmdhd.bin nvram_path=/etc/firmware/bcmdhd.cal"
+module_conf_bcm4334x = "options bcm4334x firmware_path=/etc/firmware/fw_bcmdhd.bin nvram_path=/etc/firmware/bcmdhd.cal op_mode=4"
module_autoload_g_multi = "g_multi"
# FIXME: file parameter should be based on partition UUID (from U-Boot) or fixed
# with label (label seems to work, but driver is probed too early)
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/files/edison.env b/device-software/meta-edison/recipes-bsp/u-boot/files/edison.env
new file mode 100644
index 0000000..bd5a551
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/files/edison.env
@@ -0,0 +1,56 @@
+# Edison Environment File
+# Main part
+
+# Partition definition
+partitions=uuid_disk=${uuid_disk};name=u-boot0,start=1MiB,size=2MiB,uuid=${uuid_uboot0};name=u-boot-env0,size=1MiB,uuid=${uuid_uboot_env0};name=u-boot1,size=2MiB,uuid=${uuid_uboot1};name=u-boot-env1,size=1MiB,uuid=${uuid_uboot_env1};name=factory,size=1MiB,uuid=${uuid_factory};name=panic,size=24MiB,uuid=${uuid_panic};name=boot,size=32MiB,uuid=${uuid_boot};name=rootfs,size=1536MiB,uuid=${uuid_rootfs};name=update,size=768MiB,uuid=${uuid_update};name=home,size=-,uuid=${uuid_home};
+
+# Dfu Alternate setting definition
+do_dfu_alt_info_mmc=setenv dfu_alt_info "ifwi${hardware_id} mmc 0 8192 mmcpart 1;ifwib${hardware_id} mmc 0 8192 mmcpart 2;u-boot0 part 0 1;u-boot-env0 part 0 2;u-boot1 part 0 3;u-boot-env1 part 0 4;boot part 0 7;rootfs part 0 8;update part 0 9;home part 0 10;vmlinuz fat 0 7;initrd fat 0 7"
+dfu_alt_info_ram=kernel ram ${loadaddr} 0x800000
+do_dfu_alt_info_ifwi=setenv dfu_alt_info "ifwi${hardware_id} mmc 0 8192 mmcpart 1;ifwib${hardware_id} mmc 0 8192 mmcpart 2"
+dfu_alt_info_reset=reset ram 0x0 0x0
+
+# Kernel load configuration
+bootargs_console=console=ttyMFD2 earlyprintk=ttyMFD2,keep
+bootargs_debug=loglevel=4
+do_bootargs_rootfs=setenv bootargs_rootfs rootwait root=PARTUUID=${uuid_rootfs} rootfstype=ext4
+first_install_retry=0
+first_install_max_retries=3
+ota_update_retry=0
+ota_update_max_retries=3
+do_compute_target=if itest.b ${first_install_retry} -gt ${first_install_max_retries} || itest.b ${ota_update_retry} -gt ${ota_update_max_retries}; then echo "Switch to Rescue target"; setenv bootargs_target rescue; saveenv; fi
+mmc-bootargs=run do_bootargs_rootfs; setenv bootargs ${bootargs_rootfs} ${bootargs_console} ${bootargs_debug} g_multi.ethernet_config=${bootargs_ethconfig} systemd.unit=${bootargs_target}.target hardware_id=${hardware_id} g_multi.iSerialNumber=${serial#} g_multi.dev_addr=${usb0addr}
+loadaddr=0x100000
+load_kernel=fatload mmc 0:7 ${loadaddr} vmlinuz
+
+# Main functions
+do_partition_done=0
+do_partition=if itest.b ${do_partition_done} -eq 1; then echo "Partitioning already done..."; else run do_force_partition ; fi
+do_force_partition=echo "Partitioning using GPT"; gpt write mmc 0 ${partitions} ; mmc rescan; setenv do_partition_done 1 ; saveenv
+do_flash_ifwi=run do_dfu_alt_info_ifwi ; dfu 0 mmc 0
+do_flash_os=if itest.b ${do_flash_os_done} -eq 1 ; then echo "Flashing already done..." ; else run do_force_flash_os; fi
+do_force_flash_os=run do_dfu_alt_info_mmc ; sleep 1 ; setenv do_flash_os_done 1 ; saveenv ; dfu 0 mmc 0
+do_flashall=run do_partition;run do_flash_ifwi;run do_flash_os
+do_dnx=setenv dfu_alt_info ${dfu_alt_info_ram};dfu 0 ram 0 ram;run bootcmd
+init_dfu=run do_dfu_alt_info_mmc ; saveenv
+
+# Handle different boot mode
+bootcmd=echo "Target:${target_name}"; run do_partition; run do_handle_bootargs_mode;
+
+do_handle_bootargs_mode=run do_preprocess_bootargs_mode; if itest.s $bootargs_mode == "ota" ; then run do_ota; fi; if itest.s $bootargs_mode == "boot" ; then run do_boot; fi; if itest.s $bootargs_mode == "flash"; then run do_flash; fi; run do_fallback; exit;
+do_preprocess_bootargs_mode=if env exists bootargs_mode ; then ; else setenv bootargs_mode "boot" ;fi;
+
+do_fallback=echo "Unknown boot mode: $bootargs_mode"; env delete -f bootargs_mode; saveenv; echo "Resetting to default boot mode and reboot..."; reset;
+do_boot=run boot_target_cmd;
+do_flash=run do_force_flash_os;
+
+# OTA settings
+ota_script_addr=0x100000
+do_ota_init=setenv ota_status 1 ; env delete -f bootargs_mode
+do_load_ota_scr=if fatload mmc 0:9 $ota_script_addr ota_update.scr ; then setenv ota_status 0 ; else setenv ota_status 1 ; fi
+do_source_ota_scr=if test $ota_status -eq 0 ; then if source $ota_script_addr ; then setenv ota_status 0 ; else setenv ota_status 2 ; fi ; fi
+
+# do_ota_clean can be overriden by ota script
+do_ota_clean=saveenv ; reset
+
+do_ota=run do_ota_init ; run do_load_ota_scr ; run do_source_ota_scr ; run do_ota_clean
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/files/fw_env.config b/device-software/meta-edison/recipes-bsp/u-boot/files/fw_env.config
new file mode 100644
index 0000000..392bb8e
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/files/fw_env.config
@@ -0,0 +1,11 @@
+# Configuration file for fw_(printenv/setenv) utility.
+# Up to two entries are valid, in this case the redundant
+# environment sector is assumed present.
+# Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash.
+# Futhermore, if the Flash sector size is ommitted, this value is assumed to
+# be the same as the Environment size, which is valid for NOR and SPI-dataflash
+
+# MTD device name Device offset Env. size Flash sector size Number of sectors
+# On Edison, the u-boot environments are located on partitions 2 and 4 and both have a size of 64kB
+/dev/mmcblk0p2 0x0000 0x10000
+/dev/mmcblk0p4 0x0000 0x10000
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/blankcdc.env b/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/blankcdc.env
new file mode 100644
index 0000000..a04d786
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/blankcdc.env
@@ -0,0 +1,10 @@
+# U-Boot blank environment with CDC ECM ethernet config for gadget multi
+# used to erase all partitions and first boot setup
+target_name=blank
+bootdelay=1
+do_flash_os_done=1
+bootargs_target=first-install
+bootargs_ethconfig=cdc
+dfu_to_sec=3
+do_probe_dfu=run do_dfu_alt_info_mmc ; dfu 0 mmc 0 $dfu_to_sec
+boot_target_cmd=run do_flash_os;run do_probe_dfu;run do_compute_target;run mmc-bootargs;run load_kernel;zboot ${loadaddr}
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/blankrndis.env b/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/blankrndis.env
new file mode 100644
index 0000000..1fcf1ba
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/blankrndis.env
@@ -0,0 +1,10 @@
+# U-Boot blank environment with RNDIS ethernet config for gadget multi
+# used to erase all partitions and first boot setup
+target_name=blank
+bootdelay=1
+do_flash_os_done=1
+bootargs_target=first-install
+bootargs_ethconfig=rndis
+dfu_to_sec=3
+do_probe_dfu=run do_dfu_alt_info_mmc ; dfu 0 mmc 0 $dfu_to_sec
+boot_target_cmd=run do_flash_os;run do_probe_dfu;run do_compute_target;run mmc-bootargs;run load_kernel;zboot ${loadaddr}
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/defaultcdc.env b/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/defaultcdc.env
new file mode 100644
index 0000000..6a0edda
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/defaultcdc.env
@@ -0,0 +1,10 @@
+# U-Boot default environment
+# default end-user environment
+target_name=default
+bootdelay=1
+do_flash_os_done=1
+bootargs_target=multi-user
+bootargs_ethconfig=cdc
+dfu_to_sec=3
+do_probe_dfu=run do_dfu_alt_info_mmc ; dfu 0 mmc 0 $dfu_to_sec
+boot_target_cmd=run do_flash_os;run do_probe_dfu;run do_compute_target;run mmc-bootargs;run load_kernel;zboot ${loadaddr}
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/defaultrndis.env b/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/defaultrndis.env
new file mode 100644
index 0000000..84768c5
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/defaultrndis.env
@@ -0,0 +1,10 @@
+# U-Boot default environment
+# default end-user environment
+target_name=default
+bootdelay=1
+do_flash_os_done=1
+bootargs_target=multi-user
+bootargs_ethconfig=rndis
+dfu_to_sec=3
+do_probe_dfu=run do_dfu_alt_info_mmc ; dfu 0 mmc 0 $dfu_to_sec
+boot_target_cmd=run do_flash_os;run do_probe_dfu;run do_compute_target;run mmc-bootargs;run load_kernel;zboot ${loadaddr}
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/ifwi.env b/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/ifwi.env
new file mode 100644
index 0000000..e0a1286
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/ifwi.env
@@ -0,0 +1,7 @@
+# U-Boot IFWI environment
+# IFWI testing mode
+# this env is stitched with xfstk binary , do only dfu
+target_name=ifwi
+bootdelay=1
+do_flash_os_done=0
+boot_target_cmd=run do_partition;run do_force_flash_os
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/prod.env b/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/prod.env
new file mode 100644
index 0000000..7e68939
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/files/target_env/prod.env
@@ -0,0 +1,6 @@
+# U-Boot production environment
+# used in factory for flashing and calibrating
+target_name=prod
+bootdelay=3
+do_flash_os_done=0
+boot_target_cmd=run do_flash_ifwi;run do_force_flash_os
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/files/upstream_to_edison.patch b/device-software/meta-edison/recipes-bsp/u-boot/files/upstream_to_edison.patch
new file mode 100644
index 0000000..a44e3d1
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/files/upstream_to_edison.patch
@@ -0,0 +1,11157 @@
+From 084994e3140fb25fc9e0c96b48d03693bee7b28b Mon Sep 17 00:00:00 2001
+From: Jenkins
+Date: Fri, 30 Jan 2015 14:23:54 +0100
+Subject: [PATCH] Squashed all commits from upstream to Edison
+
+Change-Id: I1966c64a6433cfe814361fe44e46a8313db9e653
+---
+ Makefile | 1 +
+ arch/x86/config.mk | 4 +-
+ arch/x86/cpu/config.mk | 2 +-
+ arch/x86/cpu/start.S | 2 +
+ arch/x86/cpu/tangier/Makefile | 1 +
+ arch/x86/cpu/tangier/board_id.c | 33 +
+ arch/x86/cpu/tangier/car.S | 13 +
+ arch/x86/cpu/tangier/pci.c | 49 +
+ arch/x86/cpu/tangier/sdram.c | 139 ++
+ arch/x86/cpu/tangier/tables.c | 26 +
+ arch/x86/cpu/tangier/tangier.c | 171 ++
+ arch/x86/include/asm/apic.h | 91 +
+ arch/x86/include/asm/arch-tangier/clk.h | 3 +
+ arch/x86/include/asm/arch-tangier/intel-mid.h | 29 +
+ arch/x86/include/asm/arch-tangier/ipchecksum.h | 37 +
+ arch/x86/include/asm/arch-tangier/mmc.h | 11 +
+ arch/x86/include/asm/arch-tangier/sysinfo.h | 62 +
+ arch/x86/include/asm/arch-tangier/tables.h | 294 ++++
+ arch/x86/include/asm/arch-tangier/timestamp.h | 59 +
+ arch/x86/include/asm/delay.h | 6 +
+ arch/x86/include/asm/io.h | 48 +
+ arch/x86/include/asm/mpspec.h | 74 +
+ arch/x86/include/asm/msr-index.h | 46 +-
+ arch/x86/include/asm/sfi.h | 119 ++
+ arch/x86/lib/Makefile | 1 +
+ arch/x86/lib/sfi.c | 162 ++
+ arch/x86/lib/tsc_timer.c | 6 +-
+ arch/x86/lib/zimage.c | 4 +
+ board/intel/edison/Makefile | 1 +
+ board/intel/edison/config.mk | 7 +
+ board/intel/edison/edison.c | 54 +
+ board/intel/edison/edison_start.S | 13 +
+ boards.cfg | 1 +
+ common/Makefile | 2 +
+ common/board_f.c | 20 +-
+ common/cmd_dfu.c | 46 +-
+ common/cmd_fastboot.c | 28 +
+ common/cmd_gpt.c | 2 +-
+ common/cmd_itest.c | 3 +-
+ common/cmd_part.c | 135 +-
+ disk/part_efi.c | 8 +-
+ drivers/dfu/dfu.c | 12 +
+ drivers/dfu/dfu_mmc.c | 48 +-
+ drivers/misc/Makefile | 1 +
+ drivers/misc/intel_scu_ipc.c | 150 ++
+ drivers/mmc/Makefile | 1 +
+ drivers/mmc/tangier_sdhci.c | 38 +
+ drivers/serial/Makefile | 1 +
+ drivers/serial/serial.c | 1 +
+ drivers/serial/serial_tng.c | 252 +++
+ drivers/usb/dwc3/Kconfig | 26 +
+ drivers/usb/dwc3/Makefile | 8 +
+ drivers/usb/dwc3/core.h | 814 +++++++++
+ drivers/usb/dwc3/debug.h | 49 +
+ drivers/usb/dwc3/debugfs.c | 521 ++++++
+ drivers/usb/dwc3/dwc3-omap.c | 418 +++++
+ drivers/usb/dwc3/dwc3-pci.c | 187 ++
+ drivers/usb/dwc3/dwc3_core.c | 513 ++++++
+ drivers/usb/dwc3/dwc3_ep0.c | 851 +++++++++
+ drivers/usb/dwc3/dwc3_gadget.c | 2184 ++++++++++++++++++++++++
+ drivers/usb/dwc3/dwc3_host.c | 102 ++
+ drivers/usb/dwc3/dwc3_misc.c | 20 +
+ drivers/usb/dwc3/gadget.h | 186 ++
+ drivers/usb/dwc3/io.h | 54 +
+ drivers/usb/dwc3/misc.h | 269 +++
+ drivers/usb/gadget/Makefile | 1 +
+ drivers/usb/gadget/f_dfu.c | 1 +
+ drivers/usb/gadget/f_fastboot.c | 559 ++++++
+ drivers/usb/gadget/g_fastboot.h | 20 +
+ drivers/usb/gadget/u_fastboot.c | 308 ++++
+ examples/standalone/Makefile | 4 +
+ fs/fat/fat.c | 37 +-
+ include/android_image.h | 102 ++
+ include/configs/coreboot.h | 1 +
+ include/configs/edison.h | 268 +++
+ include/dfu.h | 7 +
+ include/intel_scu_ipc.h | 69 +
+ include/linux/usb/gadget.h | 15 +-
+ include/usb/fastboot.h | 100 ++
+ pft-config.xml | 28 +
+ 80 files changed, 9997 insertions(+), 42 deletions(-)
+ create mode 100644 arch/x86/cpu/tangier/Makefile
+ create mode 100644 arch/x86/cpu/tangier/board_id.c
+ create mode 100644 arch/x86/cpu/tangier/car.S
+ create mode 100644 arch/x86/cpu/tangier/pci.c
+ create mode 100644 arch/x86/cpu/tangier/sdram.c
+ create mode 100644 arch/x86/cpu/tangier/tables.c
+ create mode 100644 arch/x86/cpu/tangier/tangier.c
+ create mode 100644 arch/x86/include/asm/apic.h
+ create mode 100644 arch/x86/include/asm/arch-tangier/clk.h
+ create mode 100644 arch/x86/include/asm/arch-tangier/intel-mid.h
+ create mode 100644 arch/x86/include/asm/arch-tangier/ipchecksum.h
+ create mode 100644 arch/x86/include/asm/arch-tangier/mmc.h
+ create mode 100644 arch/x86/include/asm/arch-tangier/sysinfo.h
+ create mode 100644 arch/x86/include/asm/arch-tangier/tables.h
+ create mode 100644 arch/x86/include/asm/arch-tangier/timestamp.h
+ create mode 100644 arch/x86/include/asm/delay.h
+ create mode 100644 arch/x86/include/asm/mpspec.h
+ create mode 100644 arch/x86/include/asm/sfi.h
+ create mode 100644 arch/x86/lib/sfi.c
+ create mode 100644 board/intel/edison/Makefile
+ create mode 100644 board/intel/edison/config.mk
+ create mode 100644 board/intel/edison/edison.c
+ create mode 100644 board/intel/edison/edison.h
+ create mode 100644 board/intel/edison/edison_start.S
+ create mode 100644 common/cmd_fastboot.c
+ create mode 100644 drivers/misc/intel_scu_ipc.c
+ create mode 100644 drivers/mmc/tangier_sdhci.c
+ create mode 100644 drivers/serial/serial_tng.c
+ create mode 100644 drivers/usb/dwc3/Kconfig
+ create mode 100644 drivers/usb/dwc3/Makefile
+ create mode 100644 drivers/usb/dwc3/core.h
+ create mode 100644 drivers/usb/dwc3/debug.h
+ create mode 100644 drivers/usb/dwc3/debugfs.c
+ create mode 100644 drivers/usb/dwc3/dwc3-omap.c
+ create mode 100644 drivers/usb/dwc3/dwc3-pci.c
+ create mode 100644 drivers/usb/dwc3/dwc3_core.c
+ create mode 100644 drivers/usb/dwc3/dwc3_ep0.c
+ create mode 100644 drivers/usb/dwc3/dwc3_gadget.c
+ create mode 100644 drivers/usb/dwc3/dwc3_host.c
+ create mode 100644 drivers/usb/dwc3/dwc3_misc.c
+ create mode 100644 drivers/usb/dwc3/gadget.h
+ create mode 100644 drivers/usb/dwc3/io.h
+ create mode 100644 drivers/usb/dwc3/misc.h
+ create mode 100644 drivers/usb/gadget/f_fastboot.c
+ create mode 100644 drivers/usb/gadget/g_fastboot.h
+ create mode 100644 drivers/usb/gadget/u_fastboot.c
+ create mode 100644 include/android_image.h
+ create mode 100644 include/configs/edison.h
+ create mode 100644 include/intel_scu_ipc.h
+ create mode 100644 include/usb/fastboot.h
+ create mode 100644 pft-config.xml
+
+diff --git a/Makefile b/Makefile
+index c91c10e..3846d2c 100644
+--- a/Makefile
++++ b/Makefile
+@@ -612,6 +612,7 @@ libs-y += drivers/usb/gadget/
+ libs-y += drivers/usb/host/
+ libs-y += drivers/usb/musb/
+ libs-y += drivers/usb/musb-new/
++libs-y += drivers/usb/dwc3/
+ libs-y += drivers/usb/phy/
+ libs-y += drivers/usb/ulpi/
+ libs-y += common/
+diff --git a/arch/x86/config.mk b/arch/x86/config.mk
+index 38cb7c9..9048a50 100644
+--- a/arch/x86/config.mk
++++ b/arch/x86/config.mk
+@@ -15,7 +15,8 @@ PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \
+ $(call cc-option, -mpreferred-stack-boundary=2)
+ PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
+ PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
+-PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0
++#PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0
++PLATFORM_CPPFLAGS += -m32
+
+ # Support generic board on x86
+ __HAVE_ARCH_GENERIC_BOARD := y
+@@ -23,6 +24,7 @@ __HAVE_ARCH_GENERIC_BOARD := y
+ PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
+
+ PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions
++PLATFORM_LDFLAGS += -m elf_i386
+
+ LDFLAGS_FINAL += --gc-sections -pie
+ LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3
+diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk
+index c1568cac..42a4425 100644
+--- a/arch/x86/cpu/config.mk
++++ b/arch/x86/cpu/config.mk
+@@ -5,7 +5,7 @@
+ # SPDX-License-Identifier: GPL-2.0+
+ #
+
+-CROSS_COMPILE ?= i386-linux-
++#CROSS_COMPILE ?= i386-linux-
+
+ PLATFORM_CPPFLAGS += -DCONFIG_X86 -D__I386__ -march=i386 -Werror
+
+diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
+index 329bb3a..e4d1c53 100644
+--- a/arch/x86/cpu/start.S
++++ b/arch/x86/cpu/start.S
+@@ -50,6 +50,7 @@ _start:
+ movw $GD_FLG_COLD_BOOT, %bx
+ 1:
+
++#ifndef CONFIG_INHERIT_GDT
+ /* Load the segement registes to match the gdt loaded in start16.S */
+ movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax
+ movw %ax, %fs
+@@ -57,6 +58,7 @@ _start:
+ movw %ax, %gs
+ movw %ax, %es
+ movw %ax, %ss
++#endif
+
+ /* Clear the interrupt vectors */
+ lidt blank_idt_ptr
+diff --git a/arch/x86/cpu/tangier/Makefile b/arch/x86/cpu/tangier/Makefile
+new file mode 100644
+index 0000000..2ef428b
+--- /dev/null
++++ b/arch/x86/cpu/tangier/Makefile
+@@ -0,0 +1 @@
++obj-y += car.o tangier.o pci.o sdram.o tables.o
+diff --git a/arch/x86/cpu/tangier/board_id.c b/arch/x86/cpu/tangier/board_id.c
+new file mode 100644
+index 0000000..b13b051
+--- /dev/null
++++ b/arch/x86/cpu/tangier/board_id.c
+@@ -0,0 +1,33 @@
++#include
++#include
++#include
++
++int _get_board_id(void)
++{
++ u8 i = 0;
++ u8 data = -1;
++ int value = 0;
++
++ for (i = 0x79; i <= 0x7c; i++) {
++ intel_scu_ipc_ioread8(i, &data);
++ value |= (data & 0x1) << (0x7c - i);
++ data = -1;
++ }
++
++ printf("[SCU_IPC_DEBUG] board ID: %x\n", value);
++
++ return value;
++}
++
++int get_board_id(void)
++{
++ static int clt_board_id = CLT_BOARD_NOT_IDENTIFIED;
++
++ if (clt_board_id != CLT_BOARD_NOT_IDENTIFIED)
++ return clt_board_id;
++
++ clt_board_id = _get_board_id();
++
++ return clt_board_id;
++}
++
+diff --git a/arch/x86/cpu/tangier/car.S b/arch/x86/cpu/tangier/car.S
+new file mode 100644
+index 0000000..6982106
+--- /dev/null
++++ b/arch/x86/cpu/tangier/car.S
+@@ -0,0 +1,13 @@
++/*
++ * Copyright (c) 2011 The Chromium OS Authors.
++ * (C) Copyright 2010-2011
++ * Graeme Russ,
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++.section .text
++
++.globl car_init
++car_init:
++ jmp car_init_ret
+diff --git a/arch/x86/cpu/tangier/pci.c b/arch/x86/cpu/tangier/pci.c
+new file mode 100644
+index 0000000..af5ff2c
+--- /dev/null
++++ b/arch/x86/cpu/tangier/pci.c
+@@ -0,0 +1,49 @@
++/*
++ * Copyright (c) 2011 The Chromium OS Authors.
++ * (C) Copyright 2008,2009
++ * Graeme Russ,
++ *
++ * (C) Copyright 2002
++ * Daniel Engström, Omicron Ceti AB,
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include
++#include
++#include
++
++static struct pci_controller tangier_hose;
++
++static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
++ struct pci_config_table *table)
++{
++ u8 secondary;
++ hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
++ hose->last_busno = max(hose->last_busno, secondary);
++ pci_hose_scan_bus(hose, secondary);
++}
++
++static struct pci_config_table pci_tangier_config_table[] = {
++ /* vendor, device, class, bus, dev, func */
++ { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
++ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
++ {}
++};
++
++void pci_init_board(void)
++{
++ tangier_hose.config_table = pci_tangier_config_table;
++ tangier_hose.first_busno = 0;
++ tangier_hose.last_busno = 0;
++
++ pci_set_region(tangier_hose.regions + 0, 0x0, 0x0, 0xffffffff,
++ PCI_REGION_MEM);
++ tangier_hose.region_count = 1;
++
++ pci_setup_type1(&tangier_hose);
++
++ pci_register_hose(&tangier_hose);
++
++ pci_hose_scan(&tangier_hose);
++}
+diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c
+new file mode 100644
+index 0000000..f18b45e
+--- /dev/null
++++ b/arch/x86/cpu/tangier/sdram.c
+@@ -0,0 +1,139 @@
++/*
++ * Copyright (c) 2011 The Chromium OS Authors.
++ * (C) Copyright 2010,2011
++ * Graeme Russ,
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#ifdef CONFIG_SFI
++#include
++#endif
++
++DECLARE_GLOBAL_DATA_PTR;
++
++unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
++{
++#ifdef CONFIG_SFI
++ return sfi_setup_e820(max_entries, entries);
++#else
++ return 0;
++#endif
++}
++
++/*
++ * This function looks for the highest region of memory lower than 4GB which
++ * has enough space for U-Boot where U-Boot is aligned on a page boundary. It
++ * overrides the default implementation found elsewhere which simply picks the
++ * end of ram, wherever that may be. The location of the stack, the relocation
++ * address, and how far U-Boot is moved by relocation are set in the global
++ * data structure.
++ */
++ulong board_get_usable_ram_top(ulong total_size)
++{
++ uintptr_t dest_addr = 0x000000003F4FFFFF;
++/*
++ * int i;
++ *
++ * for (i = 0; i < lib_sysinfo.n_memranges; i++) {
++ * struct memrange *memrange = &lib_sysinfo.memrange[i];
++ * [> Force U-Boot to relocate to a page aligned address. <]
++ * uint64_t start = roundup(memrange->base, 1 << 12);
++ * uint64_t end = memrange->base + memrange->size;
++ *
++ * [> Ignore non-memory regions. <]
++ * if (memrange->type != CB_MEM_RAM)
++ * continue;
++ *
++ * [> Filter memory over 4GB. <]
++ * if (end > 0xffffffffULL)
++ * end = 0x100000000ULL;
++ * [> Skip this region if it's too small. <]
++ * if (end - start < total_size)
++ * continue;
++ *
++ * [> Use this address if it's the largest so far. <]
++ * if (end > dest_addr)
++ * dest_addr = end;
++ * }
++ *
++ * [> If no suitable area was found, return an error. <]
++ * if (!dest_addr)
++ * panic("No available memory found for relocation");
++ */
++
++ return (ulong)dest_addr;
++}
++
++int dram_init_f(void)
++{
++/*
++ * int i;
++ * phys_size_t ram_size = 0;
++ *
++ * for (i = 0; i < lib_sysinfo.n_memranges; i++) {
++ * struct memrange *memrange = &lib_sysinfo.memrange[i];
++ * unsigned long long end = memrange->base + memrange->size;
++ *
++ * if (memrange->type == CB_MEM_RAM && end > ram_size)
++ * ram_size = end;
++ * }
++ * gd->ram_size = ram_size;
++ * if (ram_size == 0)
++ * return -1;
++ */
++#ifdef CONFIG_SFI
++ gd->ram_size = sfi_get_ram_size();
++#endif
++ return 0;
++}
++
++int dram_init_banksize(void)
++{
++/*
++ * int i, j;
++ *
++ * if (CONFIG_NR_DRAM_BANKS) {
++ * for (i = 0, j = 0; i < lib_sysinfo.n_memranges; i++) {
++ * struct memrange *memrange = &lib_sysinfo.memrange[i];
++ *
++ * if (memrange->type == CB_MEM_RAM) {
++ * gd->bd->bi_dram[j].start = memrange->base;
++ * gd->bd->bi_dram[j].size = memrange->size;
++ * j++;
++ * if (j >= CONFIG_NR_DRAM_BANKS)
++ * break;
++ * }
++ * }
++ * }
++ */
++/*
++ *0: 0000000000000000-0000000000097FFF ( 0K - 608K) ram
++ *3: 0000000000100000-0000000003FFFFFF ( 1M - 64M) ram
++ *5: 0000000006000000-000000003F4FFFFF ( 96M - 1013M) ram
++ */
++ gd->bd->bi_dram[0].start = 0x0;
++ gd->bd->bi_dram[0].size = 0x97FFF;
++
++ gd->bd->bi_dram[1].start = 0x100000;
++ gd->bd->bi_dram[1].size = 0x3FFFFFF - gd->bd->bi_dram[1].start;
++
++ gd->bd->bi_dram[2].start = 0x6000000;
++ gd->bd->bi_dram[2].size = 0x3F4FFFFF - gd->bd->bi_dram[2].start;
++
++ return 0;
++}
++
++int dram_init(void)
++{
++ return dram_init_banksize();
++}
+diff --git a/arch/x86/cpu/tangier/tables.c b/arch/x86/cpu/tangier/tables.c
+new file mode 100644
+index 0000000..0568877
+--- /dev/null
++++ b/arch/x86/cpu/tangier/tables.c
+@@ -0,0 +1,26 @@
++/*
++ * This file is part of the libpayload project.
++ *
++ * Copyright (C) 2008 Advanced Micro Devices, Inc.
++ * Copyright (C) 2009 coresystems GmbH
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ */
++
++#include
++#include
++#include
++#include
++
++/*
++ * This needs to be in the .data section so that it's copied over during
++ * relocation. By default it's put in the .bss section which is simply filled
++ * with zeroes when transitioning from "ROM", which is really RAM, to other
++ * RAM.
++ */
++struct sysinfo_t lib_sysinfo __attribute__ ((section(".data")));
++
++int get_coreboot_info(struct sysinfo_t *info)
++{
++ return 0;
++}
+diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c
+new file mode 100644
+index 0000000..0fbe401
+--- /dev/null
++++ b/arch/x86/cpu/tangier/tangier.c
+@@ -0,0 +1,171 @@
++/*
++ * Copyright (c) 2011 The Chromium OS Authors.
++ * (C) Copyright 2008
++ * Graeme Russ, graeme.russ@gmail.com.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++DECLARE_GLOBAL_DATA_PTR;
++
++/*
++ * Miscellaneous platform dependent initializations
++ */
++int cpu_init_f(void)
++{
++ timer_set_base(1);
++ return 0;
++}
++
++int board_early_init_f(void)
++{
++ return 0;
++}
++
++int board_early_init_r(void)
++{
++ return 0;
++}
++
++int board_late_init(void)
++{
++ if (!getenv("serial#")) {
++
++ struct mmc *mmc = find_mmc_device(0);
++ unsigned char emmc_ssn[16];
++ char ssn[33];
++ char usb_gadget_addr[18];
++
++ if (mmc) {
++ int i;
++
++ md5((unsigned char *)mmc->cid, sizeof(mmc->cid), emmc_ssn);
++
++ for (i = 0; i < 16; i++)
++ snprintf(&(ssn[2*i]), 2, "%02x", emmc_ssn[i]);
++
++ snprintf(&(usb_gadget_addr[0]), sizeof(usb_gadget_addr),
++ "02:00:86:%02x:%02x:%02x", emmc_ssn[13], emmc_ssn[14],
++ emmc_ssn[15]);
++ setenv("usb0addr", usb_gadget_addr);
++ setenv("serial#", ssn);
++ saveenv();
++ }
++ }
++
++ if (!getenv("hardware_id")) {
++ union ipc_ifwi_version v;
++ int ret;
++ char hardware_id[4];
++
++ ret = intel_scu_ipc_command(IPCMSG_GET_FW_REVISION, 1,
++ NULL, 0, (u32 *) &(v.raw[0]), 4);
++ if (ret < 0) {
++ printf("Can't retrieve hardware revision\n");
++ }
++
++ snprintf(hardware_id, sizeof(hardware_id), "%02X", v.fw.hardware_id);
++ setenv("hardware_id", hardware_id);
++ saveenv();
++ }
++
++
++ return 0;
++}
++
++void show_boot_progress(int val)
++{
++ outb(val, 0x80);
++}
++
++int last_stage_init(void)
++{
++ /*
++ *if (gd->flags & GD_FLG_COLD_BOOT)
++ * timestamp_add_to_bootstage();
++ */
++
++ return 0;
++}
++
++int board_final_cleanup(void)
++{
++
++ return 0;
++}
++
++void panic_puts(const char *str)
++{
++}
++
++int board_mmc_init(bd_t * bis)
++{
++ int index = 0;
++ unsigned int base = CONFIG_SYS_EMMC_PORT_BASE + (0x40000 * index);
++
++ return tangier_sdhci_init(base, index, 4);
++}
++
++/* ovveride get_tbclk_mhz code see tsc_timer */
++/* Get the speed of the TSC timer in MHz */
++unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
++{
++ u32 ratio , bus_freq;
++ u64 platform_info = native_read_msr(MSR_PLATFORM_INFO);
++ u64 msr_fsb_freq = native_read_msr(MSR_FSB_FREQ);
++
++ /* compute and correct ratio if necessary */
++ ratio = ((platform_info >> 8) & 0xff);
++ if(!ratio)
++ {
++ ratio = 4;
++ debug("Read a zero ratio, force tsc ratio to 4 ...\n");
++ }
++
++ /* compute fsb */
++ bus_freq = (u32) (msr_fsb_freq & 0x7);
++ /* lookup real bus freq in kHz according to its index */
++ switch(bus_freq)
++ {
++ case 2:
++ bus_freq = FSB_FREQ_133SKU;
++ break;
++ case 3:
++ bus_freq = FSB_FREQ_167SKU;
++ break;
++ case 4:
++ bus_freq = FSB_FREQ_83SKU;
++ break;
++ case 5:
++ bus_freq = FSB_FREQ_400SKU;
++ break;
++ case 6:
++ bus_freq = FSB_FREQ_267SKU;
++ break;
++ case 7:
++ bus_freq = FSB_FREQ_333SKU;
++ break;
++ default: /* handle also 0 and 1 */
++ bus_freq = FSB_FREQ_100SKU;
++ break;
++ }
++ // return Freq in Mhz
++ return ((bus_freq * ratio)/1000);
++}
++
++void reset_cpu(ulong addr)
++{
++ intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
++}
+diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
+new file mode 100644
+index 0000000..7b63f48
+--- /dev/null
++++ b/arch/x86/include/asm/apic.h
+@@ -0,0 +1,91 @@
++#ifndef _APIC_H_
++#define _APIC_H_
++
++#include
++
++#define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
++#define APIC_DEFAULT_PHYS_BASE 0xfee00000
++
++#define ALL (0xff << 24)
++#define NONE (0)
++#define DISABLED (1 << 16)
++#define ENABLED (0 << 16)
++#define TRIGGER_EDGE (0 << 15)
++#define TRIGGER_LEVEL (1 << 15)
++#define POLARITY_HIGH (0 << 13)
++#define POLARITY_LOW (1 << 13)
++#define PHYSICAL_DEST (0 << 11)
++#define LOGICAL_DEST (1 << 11)
++#define ExtINT (7 << 8)
++#define NMI (4 << 8)
++#define SMI (2 << 8)
++#define INT (1 << 8)
++
++#define SET_APIC_LOGICAL_ID(x) ((x) << 24)
++
++#define APIC_LVR 0x30
++#define APIC_INTEGRATED(x) ((x) & 0xF0u)
++#define GET_APIC_VERSION(x) ((x) & 0xFFu)
++#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
++#define APIC_TASKPRI 0x80
++#define APIC_EOI 0xB0
++#define APIC_LDR 0xD0
++#define APIC_DFR 0xE0
++#define APIC_SPIV 0xF0
++
++#define APIC_TPRI_MASK 0xFFu
++#define APIC_LDR_MASK (0xFFu << 24)
++#define APIC_DFR_VALUE 0xFFFFFFFFul
++#define APIC_VECTOR_MASK 0x000FF
++#define APIC_SPIV_APIC_ENABLED (1 << 8)
++#define APIC_SPIV_FOCUS_DISABLED (1 << 9)
++
++#define LOCAL_TIMER_VECTOR 0xef
++#define ERROR_APIC_VECTOR 0xfe
++#define SPURIOUS_APIC_VECTOR 0xff
++
++#define APIC_ISR 0x100
++#define APIC_ESR 0x280
++#define APIC_LVTCMCI 0x2f0
++#define APIC_DM_NMI 0x00400
++#define APIC_LVTT 0x320
++#define APIC_LVTTHMR 0x330
++#define APIC_LVTPC 0x340
++#define APIC_LVT0 0x350
++#define APIC_LVT_TIMER_PERIODIC (1 << 17)
++#define SET_APIC_TIMER_BASE(x) (((x) << 18))
++#define APIC_TIMER_BASE_DIV 0x2
++#define APIC_LVT1 0x360
++#define APIC_LVTERR 0x370
++#define APIC_TMICT 0x380
++#ifdef CONFIG_X86_MRFLD
++#define APIC_TMICT_INIT_CNT 0x144b50
++#else
++#define APIC_TMICT_INIT_CNT 0xf3c00
++#endif
++#define APIC_TMCCT 0x390
++#define APIC_TDCR 0x3E0
++#define APIC_TDR_DIV_TMBASE (1 << 2)
++#define APIC_TDR_DIV_1 0xB
++#define APIC_TDR_DIV_2 0x0
++#define APIC_TDR_DIV_4 0x1
++#define APIC_TDR_DIV_8 0x2
++#define APIC_TDR_DIV_16 0x3
++#define APIC_TDR_DIV_32 0x8
++#define APIC_TDR_DIV_64 0x9
++#define APIC_TDR_DIV_128 0xA
++#define APIC_LVT_MASKED (1 << 16)
++#define APIC_DM_EXTINT 0x00700
++
++#define LAPIC_ID 0x020
++
++extern unsigned int lapic_timer_frequency;
++
++extern void apic_init(void);
++extern void apic_ack_irq(void);
++extern void apic_timer_setup(unsigned int clocks, int oneshot, int irqen);
++extern void apic_spurious_isr(void);
++extern void apic_mask_irq(void);
++extern void apic_unmask_irq(void);
++
++#endif /* _APIC_H_ */
+diff --git a/arch/x86/include/asm/arch-tangier/clk.h b/arch/x86/include/asm/arch-tangier/clk.h
+new file mode 100644
+index 0000000..ab887aa
+--- /dev/null
++++ b/arch/x86/include/asm/arch-tangier/clk.h
+@@ -0,0 +1,3 @@
++#ifndef _CLK_H
++#define _CLK_H
++#endif
+diff --git a/arch/x86/include/asm/arch-tangier/intel-mid.h b/arch/x86/include/asm/arch-tangier/intel-mid.h
+new file mode 100644
+index 0000000..de4857c
+--- /dev/null
++++ b/arch/x86/include/asm/arch-tangier/intel-mid.h
+@@ -0,0 +1,29 @@
++#ifndef _ASM_X86_INTEL_MID_H
++#define _ASM_X86_INTEL_MID_H
++
++/*
++ * Penwell uses spread spectrum clock, so the freq number is not exactly
++ * the same as reported by MSR based on SDM.
++ * CLVP A0 has 100MHz FSB and CLVP B0 has 133MHz FSB.
++ */
++#define FSB_FREQ_83SKU 83200
++#define FSB_FREQ_100SKU 99840
++#define FSB_FREQ_133SKU 133000
++
++#define FSB_FREQ_167SKU 167000
++#define FSB_FREQ_200SKU 200000
++#define FSB_FREQ_267SKU 267000
++#define FSB_FREQ_333SKU 333000
++#define FSB_FREQ_400SKU 400000
++
++/* Bus Select SoC Fuse value */
++#define BSEL_SOC_FUSE_MASK 0x7
++#define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */
++#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */
++#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */
++
++extern unsigned int loops_per_jiffy;
++
++extern unsigned long calibrate_tsc(void);
++
++#endif /* _ASM_X86_INTEL_MID_H */
+diff --git a/arch/x86/include/asm/arch-tangier/ipchecksum.h b/arch/x86/include/asm/arch-tangier/ipchecksum.h
+new file mode 100644
+index 0000000..1d73b4d
+--- /dev/null
++++ b/arch/x86/include/asm/arch-tangier/ipchecksum.h
+@@ -0,0 +1,37 @@
++/*
++ * This file is part of the libpayload project.
++ *
++ * It has originally been taken from the FreeBSD project.
++ *
++ * Copyright (c) 2001 Charles Mott
++ * Copyright (c) 2008 coresystems GmbH
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
++ * SUCH DAMAGE.
++ */
++
++#ifndef _COREBOOT_IPCHECKSUM_H
++#define _COREBOOT_IPCHECKSUM_H
++
++unsigned short ipchksum(const void *vptr, unsigned long nbytes);
++
++#endif
+diff --git a/arch/x86/include/asm/arch-tangier/mmc.h b/arch/x86/include/asm/arch-tangier/mmc.h
+new file mode 100644
+index 0000000..2200a7f
+--- /dev/null
++++ b/arch/x86/include/asm/arch-tangier/mmc.h
+@@ -0,0 +1,11 @@
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++int tangier_mmc_init(struct mmc *mmc);
++int tangier_sdhci_init(u32 regbase, int index, int bus_width);
+diff --git a/arch/x86/include/asm/arch-tangier/sysinfo.h b/arch/x86/include/asm/arch-tangier/sysinfo.h
+new file mode 100644
+index 0000000..8e4a61d
+--- /dev/null
++++ b/arch/x86/include/asm/arch-tangier/sysinfo.h
+@@ -0,0 +1,62 @@
++/*
++ * This file is part of the libpayload project.
++ *
++ * Copyright (C) 2008 Advanced Micro Devices, Inc.
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ */
++
++#ifndef _COREBOOT_SYSINFO_H
++#define _COREBOOT_SYSINFO_H
++
++#include
++#include
++#include
++#include
++
++/* Allow a maximum of 16 memory range definitions. */
++#define SYSINFO_MAX_MEM_RANGES 16
++/* Allow a maximum of 8 GPIOs */
++#define SYSINFO_MAX_GPIOS 8
++
++struct sysinfo_t {
++ int n_memranges;
++ struct memrange {
++ unsigned long long base;
++ unsigned long long size;
++ unsigned int type;
++ } memrange[SYSINFO_MAX_MEM_RANGES];
++
++ u32 cmos_range_start;
++ u32 cmos_range_end;
++ u32 cmos_checksum_location;
++ u32 vbnv_start;
++ u32 vbnv_size;
++
++ char *version;
++ char *extra_version;
++ char *build;
++ char *compile_time;
++ char *compile_by;
++ char *compile_host;
++ char *compile_domain;
++ char *compiler;
++ char *linker;
++ char *assembler;
++
++ struct cb_framebuffer *framebuffer;
++
++ int num_gpios;
++ struct cb_gpio gpios[SYSINFO_MAX_GPIOS];
++
++ void *vdat_addr;
++ u32 vdat_size;
++ void *tstamp_table;
++ void *cbmem_cons;
++
++ struct cb_serial *serial;
++};
++
++extern struct sysinfo_t lib_sysinfo;
++
++#endif
+diff --git a/arch/x86/include/asm/arch-tangier/tables.h b/arch/x86/include/asm/arch-tangier/tables.h
+new file mode 100644
+index 0000000..0d02fe0
+--- /dev/null
++++ b/arch/x86/include/asm/arch-tangier/tables.h
+@@ -0,0 +1,294 @@
++/*
++ * This file is part of the libpayload project.
++ *
++ * Copyright (C) 2008 Advanced Micro Devices, Inc.
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ */
++
++#ifndef _COREBOOT_TABLES_H
++#define _COREBOOT_TABLES_H
++
++#include
++
++struct cbuint64 {
++ u32 lo;
++ u32 hi;
++};
++
++struct cb_header {
++ u8 signature[4];
++ u32 header_bytes;
++ u32 header_checksum;
++ u32 table_bytes;
++ u32 table_checksum;
++ u32 table_entries;
++};
++
++struct cb_record {
++ u32 tag;
++ u32 size;
++};
++
++#define CB_TAG_UNUSED 0x0000
++#define CB_TAG_MEMORY 0x0001
++
++struct cb_memory_range {
++ struct cbuint64 start;
++ struct cbuint64 size;
++ u32 type;
++};
++
++#define CB_MEM_RAM 1
++#define CB_MEM_RESERVED 2
++#define CB_MEM_ACPI 3
++#define CB_MEM_NVS 4
++#define CB_MEM_UNUSABLE 5
++#define CB_MEM_VENDOR_RSVD 6
++#define CB_MEM_TABLE 16
++
++struct cb_memory {
++ u32 tag;
++ u32 size;
++ struct cb_memory_range map[0];
++};
++
++#define CB_TAG_HWRPB 0x0002
++
++struct cb_hwrpb {
++ u32 tag;
++ u32 size;
++ u64 hwrpb;
++};
++
++#define CB_TAG_MAINBOARD 0x0003
++
++struct cb_mainboard {
++ u32 tag;
++ u32 size;
++ u8 vendor_idx;
++ u8 part_number_idx;
++ u8 strings[0];
++};
++
++#define CB_TAG_VERSION 0x0004
++#define CB_TAG_EXTRA_VERSION 0x0005
++#define CB_TAG_BUILD 0x0006
++#define CB_TAG_COMPILE_TIME 0x0007
++#define CB_TAG_COMPILE_BY 0x0008
++#define CB_TAG_COMPILE_HOST 0x0009
++#define CB_TAG_COMPILE_DOMAIN 0x000a
++#define CB_TAG_COMPILER 0x000b
++#define CB_TAG_LINKER 0x000c
++#define CB_TAG_ASSEMBLER 0x000d
++
++struct cb_string {
++ u32 tag;
++ u32 size;
++ u8 string[0];
++};
++
++#define CB_TAG_SERIAL 0x000f
++
++struct cb_serial {
++ u32 tag;
++ u32 size;
++#define CB_SERIAL_TYPE_IO_MAPPED 1
++#define CB_SERIAL_TYPE_MEMORY_MAPPED 2
++ u32 type;
++ u32 baseaddr;
++ u32 baud;
++};
++
++#define CB_TAG_CONSOLE 0x00010
++
++struct cb_console {
++ u32 tag;
++ u32 size;
++ u16 type;
++};
++
++#define CB_TAG_CONSOLE_SERIAL8250 0
++#define CB_TAG_CONSOLE_VGA 1 /* OBSOLETE */
++#define CB_TAG_CONSOLE_BTEXT 2 /* OBSOLETE */
++#define CB_TAG_CONSOLE_LOGBUF 3
++#define CB_TAG_CONSOLE_SROM 4 /* OBSOLETE */
++#define CB_TAG_CONSOLE_EHCI 5
++
++#define CB_TAG_FORWARD 0x00011
++
++struct cb_forward {
++ u32 tag;
++ u32 size;
++ u64 forward;
++};
++
++#define CB_TAG_FRAMEBUFFER 0x0012
++struct cb_framebuffer {
++ u32 tag;
++ u32 size;
++
++ u64 physical_address;
++ u32 x_resolution;
++ u32 y_resolution;
++ u32 bytes_per_line;
++ u8 bits_per_pixel;
++ u8 red_mask_pos;
++ u8 red_mask_size;
++ u8 green_mask_pos;
++ u8 green_mask_size;
++ u8 blue_mask_pos;
++ u8 blue_mask_size;
++ u8 reserved_mask_pos;
++ u8 reserved_mask_size;
++};
++
++#define CB_TAG_GPIO 0x0013
++#define GPIO_MAX_NAME_LENGTH 16
++struct cb_gpio {
++ u32 port;
++ u32 polarity;
++ u32 value;
++ u8 name[GPIO_MAX_NAME_LENGTH];
++};
++
++struct cb_gpios {
++ u32 tag;
++ u32 size;
++
++ u32 count;
++ struct cb_gpio gpios[0];
++};
++
++#define CB_TAG_FDT 0x0014
++struct cb_fdt {
++ uint32_t tag;
++ uint32_t size; /* size of the entire entry */
++ /* the actual FDT gets placed here */
++};
++
++#define CB_TAG_VDAT 0x0015
++struct cb_vdat {
++ uint32_t tag;
++ uint32_t size; /* size of the entire entry */
++ void *vdat_addr;
++ uint32_t vdat_size;
++};
++
++#define CB_TAG_TIMESTAMPS 0x0016
++#define CB_TAG_CBMEM_CONSOLE 0x0017
++#define CB_TAG_MRC_CACHE 0x0018
++struct cb_cbmem_tab {
++ uint32_t tag;
++ uint32_t size;
++ void *cbmem_tab;
++};
++
++#define CB_TAG_VBNV 0x0019
++struct cb_vbnv {
++ uint32_t tag;
++ uint32_t size;
++ uint32_t vbnv_start;
++ uint32_t vbnv_size;
++};
++
++#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
++struct cb_cmos_option_table {
++ u32 tag;
++ u32 size;
++ u32 header_length;
++};
++
++#define CB_TAG_OPTION 0x00c9
++#define CMOS_MAX_NAME_LENGTH 32
++struct cb_cmos_entries {
++ u32 tag;
++ u32 size;
++ u32 bit;
++ u32 length;
++ u32 config;
++ u32 config_id;
++ u8 name[CMOS_MAX_NAME_LENGTH];
++};
++
++
++#define CB_TAG_OPTION_ENUM 0x00ca
++#define CMOS_MAX_TEXT_LENGTH 32
++struct cb_cmos_enums {
++ u32 tag;
++ u32 size;
++ u32 config_id;
++ u32 value;
++ u8 text[CMOS_MAX_TEXT_LENGTH];
++};
++
++#define CB_TAG_OPTION_DEFAULTS 0x00cb
++#define CMOS_IMAGE_BUFFER_SIZE 128
++struct cb_cmos_defaults {
++ u32 tag;
++ u32 size;
++ u32 name_length;
++ u8 name[CMOS_MAX_NAME_LENGTH];
++ u8 default_set[CMOS_IMAGE_BUFFER_SIZE];
++};
++
++#define CB_TAG_OPTION_CHECKSUM 0x00cc
++#define CHECKSUM_NONE 0
++#define CHECKSUM_PCBIOS 1
++struct cb_cmos_checksum {
++ u32 tag;
++ u32 size;
++ u32 range_start;
++ u32 range_end;
++ u32 location;
++ u32 type;
++};
++
++/* Helpful macros */
++
++#define MEM_RANGE_COUNT(_rec) \
++ (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
++
++#define MEM_RANGE_PTR(_rec, _idx) \
++ (((u8 *) (_rec)) + sizeof(*(_rec)) \
++ + (sizeof((_rec)->map[0]) * (_idx)))
++
++#define MB_VENDOR_STRING(_mb) \
++ (((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
++
++#define MB_PART_STRING(_mb) \
++ (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
++
++#define UNPACK_CB64(_in) \
++ ((((u64) _in.hi) << 32) | _in.lo)
++
++struct sysinfo_t;
++
++int get_coreboot_info(struct sysinfo_t *info);
++
++#define CBMEM_TOC_RESERVED 512
++#define MAX_CBMEM_ENTRIES 16
++#define CBMEM_MAGIC 0x434f5245
++
++struct cbmem_entry {
++ u32 magic;
++ u32 id;
++ u64 base;
++ u64 size;
++} __packed;
++
++#define CBMEM_ID_FREESPACE 0x46524545
++#define CBMEM_ID_GDT 0x4c474454
++#define CBMEM_ID_ACPI 0x41435049
++#define CBMEM_ID_CBTABLE 0x43425442
++#define CBMEM_ID_PIRQ 0x49525154
++#define CBMEM_ID_MPTABLE 0x534d5054
++#define CBMEM_ID_RESUME 0x5245534d
++#define CBMEM_ID_RESUME_SCRATCH 0x52455343
++#define CBMEM_ID_SMBIOS 0x534d4254
++#define CBMEM_ID_TIMESTAMP 0x54494d45
++#define CBMEM_ID_MRCDATA 0x4d524344
++#define CBMEM_ID_CONSOLE 0x434f4e53
++#define CBMEM_ID_NONE 0x00000000
++
++#endif
+diff --git a/arch/x86/include/asm/arch-tangier/timestamp.h b/arch/x86/include/asm/arch-tangier/timestamp.h
+new file mode 100644
+index 0000000..fcfc1d5
+--- /dev/null
++++ b/arch/x86/include/asm/arch-tangier/timestamp.h
+@@ -0,0 +1,59 @@
++/*
++ * This file is part of the coreboot project.
++ *
++ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
++ */
++
++#ifndef __COREBOOT_TIMESTAMP_H__
++#define __COREBOOT_TIMESTAMP_H__
++
++enum timestamp_id {
++ /* coreboot specific timestamp IDs */
++ TS_START_ROMSTAGE = 1,
++ TS_BEFORE_INITRAM = 2,
++ TS_AFTER_INITRAM = 3,
++ TS_END_ROMSTAGE = 4,
++ TS_START_COPYRAM = 8,
++ TS_END_COPYRAM = 9,
++ TS_START_RAMSTAGE = 10,
++ TS_DEVICE_ENUMERATE = 30,
++ TS_DEVICE_CONFIGURE = 40,
++ TS_DEVICE_ENABLE = 50,
++ TS_DEVICE_INITIALIZE = 60,
++ TS_DEVICE_DONE = 70,
++ TS_CBMEM_POST = 75,
++ TS_WRITE_TABLES = 80,
++ TS_LOAD_PAYLOAD = 90,
++ TS_ACPI_WAKE_JUMP = 98,
++ TS_SELFBOOT_JUMP = 99,
++
++ /* U-Boot entry IDs start at 1000 */
++ TS_U_BOOT_INITTED = 1000, /* This is where u-boot starts */
++ TS_U_BOOT_START_KERNEL = 1100, /* Right before jumping to kernel. */
++};
++
++void timestamp_init(void);
++void timestamp_add(enum timestamp_id id, uint64_t ts_time);
++void timestamp_add_now(enum timestamp_id id);
++
++/**
++ * timestamp_add_to_bootstage - Add important coreboot timestamps to bootstage
++ *
++ * @return 0 if ok, -1 if no timestamps were found
++ */
++int timestamp_add_to_bootstage(void);
++
++#endif
+diff --git a/arch/x86/include/asm/delay.h b/arch/x86/include/asm/delay.h
+new file mode 100644
+index 0000000..18682f2
+--- /dev/null
++++ b/arch/x86/include/asm/delay.h
+@@ -0,0 +1,6 @@
++#ifndef _ASM_X86_DELAY_H
++#define _ASM_X86_DELAY_H
++
++extern void use_tsc_delay(void);
++
++#endif /* _ASM_X86_DELAY_H */
+diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
+index 86bac90..9530cf7 100644
+--- a/arch/x86/include/asm/io.h
++++ b/arch/x86/include/asm/io.h
+@@ -69,6 +69,54 @@
+ #define memcpy_fromio(a,b,c) memcpy((a),(b),(c))
+ #define memcpy_toio(a,b,c) memcpy((a),(b),(c))
+
++#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v), a)
++#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a))
++
++#define out_le32(a,v) out_arch(l,le32,a,v)
++#define out_le16(a,v) out_arch(w,le16,a,v)
++
++#define in_le32(a) in_arch(l,le32,a)
++#define in_le16(a) in_arch(w,le16,a)
++
++#define out_be32(a,v) out_arch(l,be32,a,v)
++#define out_be16(a,v) out_arch(w,be16,a,v)
++
++#define in_be32(a) in_arch(l,be32,a)
++#define in_be16(a) in_arch(w,be16,a)
++
++#define out_8(a,v) __raw_writeb(v, a)
++#define in_8(a) __raw_readb(a)
++
++#define clrbits(type, addr, clear) \
++ out_##type((addr), in_##type(addr) & ~(clear))
++
++#define setbits(type, addr, set) \
++ out_##type((addr), in_##type(addr) | (set))
++
++#define clrsetbits(type, addr, clear, set) \
++ out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
++
++#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
++#define setbits_be32(addr, set) setbits(be32, addr, set)
++#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
++
++#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
++#define setbits_le32(addr, set) setbits(le32, addr, set)
++#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
++
++#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
++#define setbits_be16(addr, set) setbits(be16, addr, set)
++#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
++
++#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
++#define setbits_le16(addr, set) setbits(le16, addr, set)
++#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
++
++#define clrbits_8(addr, clear) clrbits(8, addr, clear)
++#define setbits_8(addr, set) setbits(8, addr, set)
++#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
++
++
+ /*
+ * ISA space is 'always mapped' on a typical x86 system, no need to
+ * explicitly ioremap() it. The fact that the ISA IO space is mapped
+diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
+new file mode 100644
+index 0000000..7609db4
+--- /dev/null
++++ b/arch/x86/include/asm/mpspec.h
+@@ -0,0 +1,74 @@
++#ifndef _ASM_X86_MPSPEC_H
++#define _ASM_X86_MPSPEC_H
++
++/* from apicdef.h */
++# define MAX_IO_APICS 64
++# define MAX_LOCAL_APIC 256
++
++#define SFI_MTMR_MAX_NUM 8
++
++#define MP_PROCESSOR 0
++#define MP_BUS 1
++#define MP_IOAPIC 2
++#define MP_INTSRC 3
++#define MP_LINTSRC 4
++
++#define BITS_PER_BYTE 8
++
++#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
++
++#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC)
++
++#define MAX_MP_BUSSES 260
++
++struct physid_mask {
++ unsigned long mask[PHYSID_ARRAY_SIZE];
++};
++
++typedef struct physid_mask physid_mask_t;
++
++#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
++#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
++
++#define physids_empty(map) \
++ bitmap_empty((map).mask, MAX_LOCAL_APIC)
++
++enum mp_irq_source_types {
++ mp_INT = 0,
++ mp_NMI = 1,
++ mp_SMI = 2,
++ mp_ExtINT = 3
++};
++
++#define MP_APIC_ALL 0xFF
++
++enum mp_bustype {
++ MP_BUS_ISA = 1,
++ MP_BUS_EISA,
++ MP_BUS_PCI,
++ MP_BUS_MCA,
++};
++
++#define MPC_APIC_USABLE 0x01
++
++struct mpc_ioapic {
++ unsigned char type;
++ unsigned char apicid;
++ unsigned char apicver;
++ unsigned char flags;
++ unsigned int apicaddr;
++};
++
++struct mpc_intsrc {
++ unsigned char type;
++ unsigned char irqtype;
++ unsigned short irqflag;
++ unsigned char srcbus;
++ unsigned char srcbusirq;
++ unsigned char dstapic;
++ unsigned char dstirq;
++};
++
++#define MAX_IRQ_SOURCES 256
++
++#endif
+diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
+index 0a36e17..a03b6da 100644
+--- a/arch/x86/include/asm/msr-index.h
++++ b/arch/x86/include/asm/msr-index.h
+@@ -1,12 +1,3 @@
+-/*
+- * Taken from the linux kernel file of the same name
+- *
+- * (C) Copyright 2012
+- * Graeme Russ,
+- *
+- * SPDX-License-Identifier: GPL-2.0+
+- */
+-
+ #ifndef _ASM_X86_MSR_INDEX_H
+ #define _ASM_X86_MSR_INDEX_H
+
+@@ -44,6 +35,7 @@
+ #define MSR_IA32_PERFCTR0 0x000000c1
+ #define MSR_IA32_PERFCTR1 0x000000c2
+ #define MSR_FSB_FREQ 0x000000cd
++#define MSR_PLATFORM_INFO 0x000000ce
+
+ #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
+ #define NHM_C3_AUTO_DEMOTE (1UL << 25)
+@@ -65,6 +57,13 @@
+ #define MSR_OFFCORE_RSP_0 0x000001a6
+ #define MSR_OFFCORE_RSP_1 0x000001a7
+
++#define MSR_LBR_SELECT 0x000001c8
++#define MSR_LBR_TOS 0x000001c9
++#define MSR_LBR_NHM_FROM 0x00000680
++#define MSR_LBR_NHM_TO 0x000006c0
++#define MSR_LBR_CORE_FROM 0x00000040
++#define MSR_LBR_CORE_TO 0x00000060
++
+ #define MSR_IA32_PEBS_ENABLE 0x000003f1
+ #define MSR_IA32_DS_AREA 0x00000600
+ #define MSR_IA32_PERF_CAPABILITIES 0x00000345
+@@ -91,8 +90,8 @@
+ #define MSR_IA32_LASTINTTOIP 0x000001de
+
+ /* DEBUGCTLMSR bits (others vary by model): */
+-#define DEBUGCTLMSR_LBR (1UL << 0)
+-#define DEBUGCTLMSR_BTF (1UL << 1)
++#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
++#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
+ #define DEBUGCTLMSR_TR (1UL << 6)
+ #define DEBUGCTLMSR_BTS (1UL << 7)
+ #define DEBUGCTLMSR_BTINT (1UL << 8)
+@@ -127,6 +126,7 @@
+ complete list. */
+
+ #define MSR_AMD64_PATCH_LEVEL 0x0000008b
++#define MSR_AMD64_TSC_RATIO 0xc0000104
+ #define MSR_AMD64_NB_CFG 0xc001001f
+ #define MSR_AMD64_PATCH_LOADER 0xc0010020
+ #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
+@@ -237,12 +237,19 @@
+ #define MSR_IA32_APICBASE_ENABLE (1<<11)
+ #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
+
++#define MSR_IA32_TSCDEADLINE 0x000006e0
++
+ #define MSR_IA32_UCODE_WRITE 0x00000079
+ #define MSR_IA32_UCODE_REV 0x0000008b
+
+ #define MSR_IA32_PERF_STATUS 0x00000198
+ #define MSR_IA32_PERF_CTL 0x00000199
+
++#define MSR_IA32_POWER_MISC 0x00000120
++
++#define ENABLE_ULFM_AUTOCM (1 << 2)
++#define ENABLE_INDP_AUTOCM (1 << 3)
++
+ #define MSR_IA32_MPERF 0x000000e7
+ #define MSR_IA32_APERF 0x000000e8
+
+@@ -267,6 +274,9 @@
+ #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
+
+ #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
++#define ENERGY_PERF_BIAS_PERFORMANCE 0
++#define ENERGY_PERF_BIAS_NORMAL 6
++#define ENERGY_PERF_BIAS_POWERSAVE 15
+
+ #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
+
+@@ -319,6 +329,8 @@
+ #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37)
+ #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
+ #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
++#define MSR_IA32_TSC_DEADLINE 0x000006E0
++
+
+ /* P4/Xeon+ specific */
+ #define MSR_IA32_MCG_EAX 0x00000180
+@@ -446,6 +458,18 @@
+ #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
+ #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
+ #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
++#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
++#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
++#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
++#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
++
++/* VMX_BASIC bits and bitmasks */
++#define VMX_BASIC_VMCS_SIZE_SHIFT 32
++#define VMX_BASIC_64 0x0001000000000000LLU
++#define VMX_BASIC_MEM_TYPE_SHIFT 50
++#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
++#define VMX_BASIC_MEM_TYPE_WB 6LLU
++#define VMX_BASIC_INOUT 0x0040000000000000LLU
+
+ /* AMD-V MSRs */
+
+diff --git a/arch/x86/include/asm/sfi.h b/arch/x86/include/asm/sfi.h
+new file mode 100644
+index 0000000..3d18f6e
+--- /dev/null
++++ b/arch/x86/include/asm/sfi.h
+@@ -0,0 +1,119 @@
++/* Copyright (c) 2012 Intel
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef _SFI_H
++#define _SFI_H
++
++#include
++#include
++
++/* Memory type definitions */
++enum sfi_mem_type {
++ SFI_MEM_RESERVED,
++ SFI_LOADER_CODE,
++ SFI_LOADER_DATA,
++ SFI_BOOT_SERVICE_CODE,
++ SFI_BOOT_SERVICE_DATA,
++ SFI_RUNTIME_SERVICE_CODE,
++ SFI_RUNTIME_SERVICE_DATA,
++ SFI_MEM_CONV,
++ SFI_MEM_UNUSABLE,
++ SFI_ACPI_RECLAIM,
++ SFI_ACPI_NVS,
++ SFI_MEM_MMIO,
++ SFI_MEM_IOPORT,
++ SFI_PAL_CODE,
++ SFI_MEM_TYPEMAX,
++};
++
++#define SFI_SYST_MAGIC 0x54535953
++#define SFI_MMAP_MAGIC 0x50414d4d
++
++struct sfi_mem_entry {
++ enum sfi_mem_type type;
++ u64 phy_start;
++ u64 vir_start;
++ u64 pages;
++ u64 attrib;
++} __attribute__ ((packed));
++
++struct sfi_apic_table_entry {
++ u64 phys_addr; /* phy base addr for APIC reg */
++} __attribute__ ((packed));
++
++struct sfi_timer_table_entry {
++ u64 phys_addr; /* phy base addr for the timer */
++ u32 freq_hz; /* in HZ */
++ u32 irq;
++} __attribute__ ((packed));
++
++struct sfi_table_header {
++ char signature[4];
++ u32 length;
++ u8 revision;
++ u8 checksum;
++ char oem_id[6];
++ char oem_table_id[8];
++} __attribute__ ((packed));
++
++struct sfi_quad_word {
++ u32 low;
++ u32 high;
++};
++
++struct sfi_table {
++ struct sfi_table_header header;
++ union {
++ u64 pentry[1];
++ struct sfi_quad_word entry[1];
++ };
++} __attribute__ ((packed));
++
++#define SFI_TBL_HEADER_LEN 24
++
++#define SFI_GET_NUM_ENTRIES(ptable, entry_type) \
++ ((ptable->header.length - sizeof(struct sfi_table_header)) / \
++ (sizeof(entry_type)))
++
++#define SFI_GET_ENTRY_NUM(ptable, entry) \
++ ((ptable->header.length - SFI_TBL_HEADER_LEN) / \
++ (sizeof(struct entry)))
++
++#define SFI_BASE_ADDR 0x000E0000
++#define SFI_LENGTH 0x00020000
++
++extern int sfi_mtimer_num;
++
++void sfi_parse_mtmr(void);
++struct sfi_timer_table_entry *sfi_get_mtmr(int hint);
++void fill_memranges_from_e820(struct sysinfo_t *info);
++
++#ifdef CONFIG_X86_IO_APIC
++int sfi_parse_ioapic(void);
++#endif /* CONFIG_X86_IO_APIC */
++
++#ifdef CONFIG_DETECT_RAM_SIZE_WORKAROUND
++unsigned long long sfi_get_max_usable_ram(struct sysinfo_t *info);
++#endif
++
++#ifdef CONFIG_SFI
++extern phys_size_t sfi_get_ram_size(void);
++extern unsigned sfi_setup_e820(unsigned max_entries, struct e820entry *entries);
++#endif
++
++#endif /* _SFI_H */
+diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
+index f7303ab..85274ab 100644
+--- a/arch/x86/lib/Makefile
++++ b/arch/x86/lib/Makefile
+@@ -19,6 +19,7 @@ obj-y += string.o
+ obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o
+ obj-$(CONFIG_VIDEO_VGA) += video.o
+ obj-$(CONFIG_CMD_ZBOOT) += zimage.o
++obj-$(CONFIG_SFI) += sfi.o
+
+ LIBGCC := $(notdir $(NORMAL_LIBGCC))
+ extra-y := $(LIBGCC)
+diff --git a/arch/x86/lib/sfi.c b/arch/x86/lib/sfi.c
+new file mode 100644
+index 0000000..675ad88
+--- /dev/null
++++ b/arch/x86/lib/sfi.c
+@@ -0,0 +1,162 @@
++#include
++#include
++#include
++
++#define SFI_BASE_ADDR 0x000E0000
++#define SFI_LENGTH 0x00020000
++#define SFI_TABLE_LENGTH 16
++
++static int sfi_table_check(struct sfi_table_header *sbh)
++{
++ char chksum = 0;
++ char *pos = (char *)sbh;
++ int i;
++
++ if (sbh->length < SFI_TABLE_LENGTH)
++ return -1;
++
++ if (sbh->length > SFI_LENGTH)
++ return -1;
++
++ for (i = 0; i < sbh->length; i++)
++ chksum += *pos++;
++
++ if (chksum)
++ error("sfi: Invalid checksum\n");
++
++ /* checksum is ok if zero */
++ return chksum;
++}
++
++static unsigned long sfi_search_mmap(void)
++{
++ u32 i = 0;
++ u32 *pos = (u32 *) SFI_BASE_ADDR;
++ u32 *end = (u32 *) (SFI_BASE_ADDR + SFI_LENGTH);
++ struct sfi_table_header *sbh;
++ struct sfi_table *sb;
++ u32 sys_entry_cnt = 0;
++
++ /* Find SYST table */
++ for (; pos < end; pos += 4) {
++ if (*pos == SFI_SYST_MAGIC) {
++ if (!sfi_table_check((struct sfi_table_header *)pos))
++ break;
++ }
++ }
++
++ if (pos >= end) {
++ error("failed to locate SFI SYST table\n");
++ return 0;
++ }
++
++ /* map table pointers */
++ sb = (struct sfi_table *)pos;
++ sbh = (struct sfi_table_header *)sb;
++
++ sys_entry_cnt = (sbh->length - sizeof(struct sfi_table_header)) >> 3;
++
++ /* Search through each SYST entry for MMAP table */
++ for (i = 0; i < sys_entry_cnt; i++) {
++ sbh = (struct sfi_table_header *)sb->entry[i].low;
++ if (*(u32 *) sbh->signature == SFI_MMAP_MAGIC) {
++ if (!sfi_table_check((struct sfi_table_header *)sbh))
++ return (unsigned long)sbh;
++ }
++ }
++
++ return 0;
++}
++
++unsigned sfi_setup_e820(unsigned max_entries, struct e820entry *entries)
++{
++ struct sfi_table *sb;
++ struct sfi_mem_entry *mentry;
++ unsigned long long start, end, size;
++ int i, num, type, total;
++
++ total = 0;
++
++ /* search for sfi mmap table */
++ sb = (struct sfi_table *)sfi_search_mmap();
++ if (!sb) {
++ error("failed to locate SFI MMAP table\n");
++ return 0;
++ }
++ debug("will use sfi mmap table for e820 table\n");
++ num = SFI_GET_ENTRY_NUM(sb, sfi_mem_entry);
++ mentry = (struct sfi_mem_entry *)sb->pentry;
++
++ for (i = 0; i < num; i++) {
++ start = mentry->phy_start;
++ size = mentry->pages << 12;
++ end = start + size;
++
++ if (start > end)
++ continue;
++
++ /* translate SFI mmap type to E820 map type */
++ switch (mentry->type) {
++ case SFI_MEM_CONV:
++ type = E820_RAM;
++ break;
++ case SFI_MEM_UNUSABLE:
++ case SFI_RUNTIME_SERVICE_DATA:
++ mentry++;
++ continue;
++ default:
++ type = E820_RESERVED;
++ }
++
++ if (total == E820MAX)
++ break;
++ entries[total].addr = start;
++ entries[total].size = size;
++ entries[total++].type = type;
++
++ mentry++;
++ }
++
++ return total;
++}
++
++phys_size_t sfi_get_ram_size(void)
++{
++ struct sfi_table *sb;
++ struct sfi_mem_entry *mentry;
++ unsigned long long start, end, size;
++ int i, num;
++ phys_size_t ram = 0;
++
++ /* search for sfi mmap table */
++ sb = (struct sfi_table *)sfi_search_mmap();
++ if (!sb) {
++ error("failed to locate SFI MMAP table\n");
++ return 0;
++ }
++ debug("will use sfi mmap table for e820 table\n");
++ num = SFI_GET_ENTRY_NUM(sb, sfi_mem_entry);
++ mentry = (struct sfi_mem_entry *)sb->pentry;
++
++ for (i = 0; i < num; i++, mentry++) {
++ if (mentry->type != SFI_MEM_CONV)
++ continue;
++
++ start = mentry->phy_start;
++ size = mentry->pages << 12;
++ end = start + size;
++
++ if (start > end)
++ continue;
++
++ if (ram < end)
++ ram = end;
++ }
++
++ /* round up to 512mb */
++ ram = (ram + (512 * 1024 * 1024 - 1)) & ~(512 * 1024 * 1024 - 1);
++
++ debug("ram size %llu\n", ram);
++
++ return ram;
++}
+diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c
+index 8b38702..bd751ed 100644
+--- a/arch/x86/lib/tsc_timer.c
++++ b/arch/x86/lib/tsc_timer.c
+@@ -34,13 +34,13 @@ u64 __attribute__((no_instrument_function)) get_ticks(void)
+ return now_tick - gd->arch.tsc_base;
+ }
+
+-#define PLATFORM_INFO_MSR 0xce
++
+
+ /* Get the speed of the TSC timer in MHz */
+-unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
++unsigned __weak __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
+ {
+ u32 ratio;
+- u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
++ u64 platform_info = native_read_msr(MSR_PLATFORM_INFO);
+
+ /* 100MHz times Max Non Turbo ratio */
+ ratio = (platform_info >> 8) & 0xff;
+diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
+index 1dab3cc..e1387bb 100644
+--- a/arch/x86/lib/zimage.c
++++ b/arch/x86/lib/zimage.c
+@@ -252,6 +252,10 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
+ hdr->setup_move_size = 0x9100;
+ }
+
++#ifdef CONFIG_INTEL_MID
++ hdr->hardware_subarch = X86_SUBARCH_MRST;
++#endif
++
+ /* build command line at COMMAND_LINE_OFFSET */
+ build_command_line(cmd_line, auto_boot);
+ return 0;
+diff --git a/board/intel/edison/Makefile b/board/intel/edison/Makefile
+new file mode 100644
+index 0000000..a29f512
+--- /dev/null
++++ b/board/intel/edison/Makefile
+@@ -0,0 +1 @@
++obj-y += edison_start.o edison.o
+diff --git a/board/intel/edison/config.mk b/board/intel/edison/config.mk
+new file mode 100644
+index 0000000..0c05dd0
+--- /dev/null
++++ b/board/intel/edison/config.mk
+@@ -0,0 +1,7 @@
++#
++# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
++#
++# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause
++#
++
++HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
+diff --git a/board/intel/edison/edison.c b/board/intel/edison/edison.c
+new file mode 100644
+index 0000000..8d8a6e6
+--- /dev/null
++++ b/board/intel/edison/edison.c
+@@ -0,0 +1,54 @@
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#ifndef CONFIG_WATCHDOG_HEARTBEAT
++#define WATCHDOG_HEARTBEAT 30
++#else
++#define WATCHDOG_HEARTBEAT CONFIG_WATCHDOG_HEARTBEAT
++#endif
++
++enum {
++ SCU_WATCHDOG_START = 0,
++ SCU_WATCHDOG_STOP,
++ SCU_WATCHDOG_KEEPALIVE,
++ SCU_WATCHDOG_SET_ACTION_ON_TIMEOUT
++};
++
++#define IPC_CMD(cmd, sub) (sub << 12 | cmd)
++
++int board_usb_init(int index, enum usb_init_type init)
++{
++ return usb_gadget_init_udc();
++}
++
++void watchdog_reset(void)
++{
++ ulong now = timer_get_us();
++
++ /* do not flood SCU */
++ if (unlikely((now - gd->arch.tsc_prev) > (WATCHDOG_HEARTBEAT * 1000000)))
++ {
++ gd->arch.tsc_prev = now;
++ intel_scu_ipc_send_command(IPC_CMD(IPCMSG_WATCHDOG_TIMER,
++ SCU_WATCHDOG_KEEPALIVE));
++ }
++}
++
++int watchdog_disable(void)
++{
++ return (intel_scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER,
++ SCU_WATCHDOG_STOP));
++}
++
++int watchdog_init(void)
++{
++ return (intel_scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER,
++ SCU_WATCHDOG_START));
++}
+diff --git a/board/intel/edison/edison.h b/board/intel/edison/edison.h
+new file mode 100644
+index 0000000..e69de29
+diff --git a/board/intel/edison/edison_start.S b/board/intel/edison/edison_start.S
+new file mode 100644
+index 0000000..932fe6c
+--- /dev/null
++++ b/board/intel/edison/edison_start.S
+@@ -0,0 +1,13 @@
++/*
++ * Copyright (c) 2011 The Chromium OS Authors.
++ * (C) Copyright 2008
++ * Graeme Russ, graeme.russ@gmail.com.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++/* board early intialization */
++.globl early_board_init
++early_board_init:
++ /* No 32-bit board specific initialisation */
++ jmp early_board_init_ret
+diff --git a/boards.cfg b/boards.cfg
+index b4203f1..bf4c268 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -1191,6 +1191,7 @@ Active sparc leon3 - gaisler -
+ Active sparc leon3 - gaisler - gr_xc3s_1500 - -
+ Active sparc leon3 - gaisler - grsim - -
+ Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 -
++Active x86 sivermont tangier intel edison edison edison:SYS_USB_OTG_BASE=0xf9100000,SYS_EMMC_PORT_BASE=0xff3fc000,SYS_TEXT_BASE=0x1101000 -
+ # The following were moved to "Orphan" in March, 2014
+ Orphan blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards
+ Orphan blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards
+diff --git a/common/Makefile b/common/Makefile
+index cecd81a..3c65100 100644
+--- a/common/Makefile
++++ b/common/Makefile
+@@ -175,6 +175,8 @@ obj-$(CONFIG_CMD_SPL) += cmd_spl.o
+ obj-$(CONFIG_CMD_ZIP) += cmd_zip.o
+ obj-$(CONFIG_CMD_ZFS) += cmd_zfs.o
+
++COBJS-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o
++
+ # others
+ obj-$(CONFIG_BOOTSTAGE) += bootstage.o
+ obj-$(CONFIG_CONSOLE_MUX) += iomux.o
+diff --git a/common/board_f.c b/common/board_f.c
+index f285bad..52b715c 100644
+--- a/common/board_f.c
++++ b/common/board_f.c
+@@ -280,7 +280,7 @@ __weak int arch_cpu_init(void)
+ return 0;
+ }
+
+-#ifdef CONFIG_OF_HOSTFILE
++#if defined(CONFIG_USE_FDT) && defined(CONFIG_OF_HOSTFILE)
+
+ static int read_fdt_from_file(void)
+ {
+@@ -335,6 +335,7 @@ static int setup_ram_buf(void)
+ }
+ #endif
+
++#ifdef CONFIG_USE_FDT
+ static int setup_fdt(void)
+ {
+ #ifdef CONFIG_OF_EMBED
+@@ -354,6 +355,7 @@ static int setup_fdt(void)
+ (uintptr_t)gd->fdt_blob);
+ return 0;
+ }
++#endif
+
+ /* Get the top of usable RAM */
+ __weak ulong board_get_usable_ram_top(ulong total_size)
+@@ -549,6 +551,7 @@ static int reserve_global_data(void)
+ return 0;
+ }
+
++#ifdef CONFIG_USE_FDT
+ static int reserve_fdt(void)
+ {
+ /*
+@@ -567,6 +570,7 @@ static int reserve_fdt(void)
+
+ return 0;
+ }
++#endif
+
+ static int reserve_stacks(void)
+ {
+@@ -724,6 +728,7 @@ static int setup_dram_config(void)
+ return 0;
+ }
+
++#ifdef CONFIG_USE_FDT
+ static int reloc_fdt(void)
+ {
+ if (gd->new_fdt) {
+@@ -733,6 +738,7 @@ static int reloc_fdt(void)
+
+ return 0;
+ }
++#endif
+
+ static int setup_reloc(void)
+ {
+@@ -789,7 +795,9 @@ static init_fnc_t init_sequence_f[] = {
+ setup_ram_buf,
+ #endif
+ setup_mon_len,
++#ifdef CONFIG_USE_FDT
+ setup_fdt,
++#endif
+ trace_early_init,
+ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+ /* TODO: can this go into arch_cpu_init()? */
+@@ -798,12 +806,12 @@ static init_fnc_t init_sequence_f[] = {
+ arch_cpu_init, /* basic arch cpu dependent setup */
+ #ifdef CONFIG_X86
+ cpu_init_f, /* TODO(sjg@chromium.org): remove */
+-# ifdef CONFIG_OF_CONTROL
++#if defined(CONFIG_USE_FDT) && defined(CONFIG_OF_CONTROL)
+ find_fdt, /* TODO(sjg@chromium.org): remove */
+ # endif
+ #endif
+ mark_bootstage,
+-#ifdef CONFIG_OF_CONTROL
++#if defined(CONFIG_USE_FDT) && defined(CONFIG_OF_CONTROL)
+ fdtdec_check_fdt,
+ #endif
+ #if defined(CONFIG_BOARD_EARLY_INIT_F)
+@@ -847,7 +855,7 @@ static init_fnc_t init_sequence_f[] = {
+ #ifdef CONFIG_SANDBOX
+ sandbox_early_getopt_check,
+ #endif
+-#ifdef CONFIG_OF_CONTROL
++#if defined(CONFIG_USE_FDT) && defined(CONFIG_OF_CONTROL)
+ fdtdec_prepare_fdt,
+ #endif
+ display_options, /* say that we are here */
+@@ -945,7 +953,9 @@ static init_fnc_t init_sequence_f[] = {
+ #endif
+ setup_machine,
+ reserve_global_data,
++#ifdef CONFIG_USE_FDT
+ reserve_fdt,
++#endif
+ reserve_stacks,
+ setup_dram_config,
+ show_dram_config,
+@@ -960,7 +970,9 @@ static init_fnc_t init_sequence_f[] = {
+ setup_board_extra,
+ #endif
+ INIT_FUNC_WATCHDOG_RESET
++#ifdef CONFIG_USE_FDT
+ reloc_fdt,
++#endif
+ setup_reloc,
+ #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
+ jump_to_copy,
+diff --git a/common/cmd_dfu.c b/common/cmd_dfu.c
+index 5547678..ac7db5e 100644
+--- a/common/cmd_dfu.c
++++ b/common/cmd_dfu.c
+@@ -21,7 +21,9 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ char *usb_controller = argv[1];
+ char *interface = argv[2];
+ char *devstring = argv[3];
+-
++#ifdef CONFIG_DFU_TIMEOUT
++ ulong dfu_timeout = 0 * 1000;
++#endif
+ char *s = "dfu";
+ int ret, i = 0;
+
+@@ -34,11 +36,20 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ dfu_show_entities();
+ goto done;
+ }
++#ifdef CONFIG_DFU_TIMEOUT
++ if (argc > 4)
++ dfu_timeout = simple_strtoul(argv[4], NULL, 0) * 1000 ;
++#endif
+
+ int controller_index = simple_strtoul(usb_controller, NULL, 0);
+ board_usb_init(controller_index, USB_INIT_DEVICE);
+-
+ g_dnl_register(s);
++
++#ifdef CONFIG_DFU_TIMEOUT
++ ulong time_activity_start = get_timer(0);
++ ulong time_inactivity_start = time_activity_start + dfu_timeout;
++ ulong next_print_time = 0;
++#endif
+ while (1) {
+ if (dfu_reset())
+ /*
+@@ -48,10 +59,32 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ */
+ if (++i == 10)
+ goto exit;
+-
++#ifdef CONFIG_DFU_TIMEOUT
++ if (dfu_enum_done() && (time_inactivity_start != time_activity_start))
++ {
++ time_inactivity_start = time_activity_start;
++ debug("\nDFU connection established\n");
++ }
++#endif
+ if (ctrlc())
+ goto exit;
++#ifdef CONFIG_DFU_TIMEOUT
++ if (time_activity_start != time_inactivity_start)
++ {
++ ulong cur_time = get_timer(time_activity_start);
+
++ if ( cur_time > dfu_timeout )
++ {
++ debug("\nInactivity Timeout, Abort Dfu\n");
++ goto exit;
++ }
++ if ( next_print_time == 0 || (get_timer(next_print_time)> 800))
++ {
++ debug("\rAborting in %lu sec", (dfu_timeout - cur_time)/1000);
++ next_print_time = get_timer(0);
++ }
++ }
++#endif
+ usb_gadget_handle_interrupts();
+ }
+ exit:
+@@ -67,9 +100,16 @@ done:
+
+ U_BOOT_CMD(dfu, CONFIG_SYS_MAXARGS, 1, do_dfu,
+ "Device Firmware Upgrade",
++#ifdef CONFIG_DFU_TIMEOUT
++ " [list|timeout]\n"
++#else
+ " [list]\n"
++#endif
+ " - device firmware upgrade via \n"
+ " on device , attached to interface\n"
+ " \n"
+ " [list] - list available alt settings\n"
++#ifdef CONFIG_DFU_TIMEOUT
++ " [timeout] - specify inactivity timeout in sec, doesn't work whit list"
++#endif
+ );
+diff --git a/common/cmd_fastboot.c b/common/cmd_fastboot.c
+new file mode 100644
+index 0000000..9a656dd
+--- /dev/null
++++ b/common/cmd_fastboot.c
+@@ -0,0 +1,28 @@
++#include
++#include
++#include
++
++static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
++{
++ int ret = 1;
++
++ if (!fastboot_init()) {
++ printf("Fastboot entered...\n");
++
++ ret = 0;
++
++ while (1) {
++ if (fastboot_poll())
++ break;
++ }
++ }
++
++ fastboot_shutdown();
++ return ret;
++}
++
++U_BOOT_CMD(
++ fastboot, 1, 1, do_fastboot,
++ "fastboot- use USB Fastboot protocol\n",
++ ""
++);
+diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c
+index e38422d..c8317b4 100644
+--- a/common/cmd_gpt.c
++++ b/common/cmd_gpt.c
+@@ -54,7 +54,7 @@ static int extract_env(const char *str, char **env)
+ if (e == NULL) {
+ #ifdef CONFIG_RANDOM_UUID
+ debug("%s unset. ", str);
+- gen_rand_uuid_str(uuid_str, UUID_STR_FORMAT_STD);
++ gen_rand_uuid_str(uuid_str, UUID_STR_FORMAT_GUID);
+ setenv(s, uuid_str);
+
+ e = getenv(s);
+diff --git a/common/cmd_itest.c b/common/cmd_itest.c
+index ae2527b..a965b15 100644
+--- a/common/cmd_itest.c
++++ b/common/cmd_itest.c
+@@ -63,7 +63,8 @@ static long evalexp(char *s, int w)
+ l = simple_strtoul(s, NULL, 16);
+ }
+
+- return (l & ((1 << (w * 8)) - 1));
++ /* avoid overflow on mask calculus */
++ return ((sizeof(long) <= w )? l : (l & ((1 << (w * 8)) - 1)));
+ }
+
+ static char * evalstr(char *s)
+diff --git a/common/cmd_part.c b/common/cmd_part.c
+index 1424854..79c0297 100644
+--- a/common/cmd_part.c
++++ b/common/cmd_part.c
+@@ -21,11 +21,127 @@
+ #include
+ #include
+ #include
++#include
+
+ #ifndef CONFIG_PARTITION_UUIDS
+ #error CONFIG_PARTITION_UUIDS must be enabled for CONFIG_CMD_PART to be enabled
+ #endif
+
++int do_part_info(int argc, char * const argv[])
++{
++ int part;
++ block_dev_desc_t *dev_desc;
++ disk_partition_t info;
++ char buf_convert[20];
++ if (argc < 2)
++ return CMD_RET_USAGE;
++ if (argc > 5)
++ return CMD_RET_USAGE;
++
++ part = get_device_and_partition(argv[0], argv[1], &dev_desc, &info, 0);
++ if (part < 0)
++ return 1;
++
++ snprintf(buf_convert, sizeof(buf_convert), LBAF, info.start);
++ if (argc > 2)
++ setenv(argv[2], buf_convert);
++ else
++ printf("Partition start :0x%s\n", buf_convert);
++
++ snprintf(buf_convert, sizeof(buf_convert), LBAF, info.size);
++ if (argc > 3)
++ setenv(argv[3], buf_convert);
++ else
++ printf("Partition size :0x%s\n", buf_convert);
++
++ snprintf(buf_convert, sizeof(buf_convert), "%lx", info.blksz);
++ if (argc > 4)
++ setenv(argv[4], buf_convert);
++ else
++ printf("Block size :0x%s bytes\n", buf_convert);
++ return 0;
++}
++
++#define MAX_SEARCH_PARTITIONS 128
++int do_part_find(int argc, char * const argv[])
++{
++ int part, dev, i, ret=1;
++ block_dev_desc_t *dev_desc;
++ disk_partition_t info;
++ size_t mnb_of;
++ const char *value_str;
++ char *dup_str = NULL;
++ const char *criteria_str;
++ char buf_str[4];
++
++ if (argc < 3)
++ return CMD_RET_USAGE;
++ if (argc > 4)
++ return CMD_RET_USAGE;
++
++ dev = get_device(argv[0], argv[1], &dev_desc);
++ if (dev < 0)
++ return 1;
++
++ /* check and split criteria:value */
++ value_str = strchr(argv[2],':');
++ if (!value_str)
++ return CMD_RET_USAGE;
++
++ dup_str = strdup(argv[2]);
++ if(!dup_str)
++ return 1;
++
++ if ( (value_str - argv[2]) > strlen(dup_str) )
++ return 1;
++
++ dup_str[value_str - argv[2]] = 0;
++ criteria_str = dup_str;
++ value_str++;
++
++ if(!strcmp(criteria_str, "uuid"))
++ mnb_of = offsetof(disk_partition_t, uuid);
++ else if(!strcmp(criteria_str, "label"))
++ mnb_of = offsetof(disk_partition_t, name);
++ else {
++ printf("Bad criteria: %s\n", criteria_str);
++ ret = CMD_RET_USAGE;
++ goto end_of_part_find;
++ }
++
++ part=-1;
++ for (i = 1; i <= MAX_SEARCH_PARTITIONS; i++) {
++ ret = get_partition_info(dev_desc, i, &info);
++ if (ret)
++ continue;
++
++ if(!strcmp(((char*)&info + mnb_of), value_str)) {
++ part = i;
++ ret = 0;
++ break;
++ }
++ }
++
++ if ( part == -1) {
++ printf("No partition found\n");
++ ret = 1;
++ goto end_of_part_find;
++ }
++
++ snprintf(buf_str, sizeof(buf_str), "%d", part);
++ if ( argc > 3)
++ setenv(argv[3],buf_str);
++ else
++ printf("Partition %s correspond to %s == %s\n",
++ buf_str, criteria_str, value_str);
++
++end_of_part_find:
++ if( dup_str )
++ free (dup_str);
++
++ return ret;
++}
++
+ int do_part_uuid(int argc, char * const argv[])
+ {
+ int part;
+@@ -75,17 +191,30 @@ int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ return do_part_uuid(argc - 2, argv + 2);
+ else if (!strcmp(argv[1], "list"))
+ return do_part_list(argc - 2, argv + 2);
+-
++ else if (!strcmp(argv[1], "info"))
++ return do_part_info(argc - 2, argv + 2);
++ else if (!strcmp(argv[1], "find"))
++ return do_part_find(argc - 2, argv + 2);
+ return CMD_RET_USAGE;
+ }
+
+ U_BOOT_CMD(
+- part, 5, 1, do_part,
++ part, 7, 1, do_part,
+ "disk partition related commands",
++ "find :\n"
++ " - print first partition number corresponding to criteria:valuei\n"
++ " - criteria could be label or uuid\n"
++ "part find : \n"
++ " - set environment variable to first partition number corresponding to criteria:valuei\n"
++ " - criteria could be label or uuid\n"
+ "uuid :\n"
+ " - print partition UUID\n"
+ "part uuid : \n"
+ " - set environment variable to partition UUID\n"
+ "part list \n"
+- " - print a device's partition table"
++ " - print a device's partition table\n"
++ "part info : \n"
++ " - set environment variable varname-start to partition start in blocks\n"
++ " - set environment variable varname-size to partition size in blocks\n"
++ " - set environment variable varname-blcksize to partition block size in bytes\n"
+ );
+diff --git a/disk/part_efi.c b/disk/part_efi.c
+index 216a292..4b32049 100644
+--- a/disk/part_efi.c
++++ b/disk/part_efi.c
+@@ -201,10 +201,12 @@ static int set_protective_mbr(block_dev_desc_t *dev_desc)
+ ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, p_mbr, 1);
+ memset(p_mbr, 0, sizeof(*p_mbr));
+
+- if (p_mbr == NULL) {
+- printf("%s: calloc failed!\n", __func__);
++ /* Read MBR to backup boot_code if it exists */
++ if (dev_desc->block_read(dev_desc->dev, 0, 1, p_mbr) != 1) {
++ error("** Can't read from device %d **\n", dev_desc->dev);
+ return -1;
+ }
++
+ /* Append signature */
+ p_mbr->signature = MSDOS_MBR_SIGNATURE;
+ p_mbr->partition_record[0].sys_ind = EFI_PMBR_OSTYPE_EFI_GPT;
+@@ -324,7 +326,7 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
+ str_uuid = partitions[i].uuid;
+ bin_uuid = gpt_e[i].unique_partition_guid.b;
+
+- if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_STD)) {
++ if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_GUID)) {
+ printf("Partition no. %d: invalid guid: %s\n",
+ i, str_uuid);
+ return -1;
+diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
+index 8a09aaf..fa4bfc3 100644
+--- a/drivers/dfu/dfu.c
++++ b/drivers/dfu/dfu.c
+@@ -17,6 +17,7 @@
+ #include
+
+ static bool dfu_reset_request;
++static bool dfu_enum_request;
+ static LIST_HEAD(dfu_list);
+ static int dfu_alt_num;
+ static int alt_num_cnt;
+@@ -31,6 +32,16 @@ void dfu_trigger_reset()
+ dfu_reset_request = true;
+ }
+
++bool dfu_enum_done(void)
++{
++ return dfu_enum_request;
++}
++
++void dfu_trigger_enum_done()
++{
++ dfu_enum_request = true;
++}
++
+ static int dfu_find_alt_num(const char *s)
+ {
+ int i = 0;
+@@ -61,6 +72,7 @@ int dfu_init_env_entities(char *interface, int dev)
+ return ret;
+ }
+
++ dfu_enum_request = false;
+ free(env_bkp);
+ return 0;
+ }
+diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c
+index 651cfff..a7224b6 100644
+--- a/drivers/dfu/dfu_mmc.c
++++ b/drivers/dfu/dfu_mmc.c
+@@ -18,11 +18,29 @@ static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE)
+ dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE];
+ static long dfu_file_buf_len;
+
++static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part)
++{
++ int ret;
++
++ if (part == mmc->part_num)
++ return 0;
++
++ ret = mmc_switch_part(dfu->dev_num, part);
++ if (ret) {
++ error("Cannot switch to partition %d\n", part);
++ return ret;
++ }
++ mmc->part_num = part;
++
++ return 0;
++}
++
+ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
+ u64 offset, void *buf, long *len)
+ {
+ struct mmc *mmc = find_mmc_device(dfu->dev_num);
+ u32 blk_start, blk_count, n = 0;
++ int ret, part_num_bkp = 0;
+
+ /*
+ * We must ensure that we work in lba_blk_size chunks, so ALIGN
+@@ -39,6 +57,13 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
+ return -EINVAL;
+ }
+
++ if (dfu->data.mmc.partition_access != DFU_NOT_SUPPORTED) {
++ part_num_bkp = mmc->part_num;
++ ret = mmc_access_part(dfu, mmc, dfu->data.mmc.partition_access);
++ if (ret)
++ return ret;
++ }
++
+ debug("%s: %s dev: %d start: %d cnt: %d buf: 0x%p\n", __func__,
+ op == DFU_OP_READ ? "MMC READ" : "MMC WRITE", dfu->dev_num,
+ blk_start, blk_count, buf);
+@@ -57,9 +82,17 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
+
+ if (n != blk_count) {
+ error("MMC operation failed");
++ if (dfu->data.mmc.partition_access != DFU_NOT_SUPPORTED)
++ mmc_access_part(dfu, mmc, part_num_bkp);
+ return -EIO;
+ }
+
++ if (dfu->data.mmc.partition_access != DFU_NOT_SUPPORTED) {
++ ret = mmc_access_part(dfu, mmc, part_num_bkp);
++ if (ret)
++ return ret;
++ }
++
+ return 0;
+ }
+
+@@ -193,12 +226,22 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s)
+ char *st;
+
+ dfu->dev_type = DFU_DEV_MMC;
++ dfu->data.mmc.partition_access = DFU_NOT_SUPPORTED;
++
+ st = strsep(&s, " ");
+ if (!strcmp(st, "mmc")) {
+ dfu->layout = DFU_RAW_ADDR;
+ dfu->data.mmc.lba_start = simple_strtoul(s, &s, 16);
+- dfu->data.mmc.lba_size = simple_strtoul(++s, &s, 16);
++ s++;
++ dfu->data.mmc.lba_size = simple_strtoul(s, &s, 16);
+ dfu->data.mmc.lba_blk_size = get_mmc_blk_size(dfu->dev_num);
++ if (*s) {
++ s++;
++ st = strsep(&s, " ");
++ if (!strcmp(st, "mmcpart"))
++ dfu->data.mmc.partition_access =
++ simple_strtoul(s, &s, 0);
++ }
+ } else if (!strcmp(st, "fat")) {
+ dfu->layout = DFU_FS_FAT;
+ } else if (!strcmp(st, "ext4")) {
+@@ -236,7 +279,8 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s)
+
+ if (dfu->layout == DFU_FS_EXT4 || dfu->layout == DFU_FS_FAT) {
+ dfu->data.mmc.dev = simple_strtoul(s, &s, 10);
+- dfu->data.mmc.part = simple_strtoul(++s, &s, 10);
++ s++;
++ dfu->data.mmc.part = simple_strtoul(s, &s, 10);
+ }
+
+ dfu->read_medium = dfu_read_medium_mmc;
+diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
+index 2f2e48f..889fe05 100644
+--- a/drivers/misc/Makefile
++++ b/drivers/misc/Makefile
+@@ -23,3 +23,4 @@ obj-$(CONFIG_PDSP188x) += pdsp188x.o
+ obj-$(CONFIG_STATUS_LED) += status_led.o
+ obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
+ obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
++obj-$(CONFIG_INTEL_SCU) += intel_scu_ipc.o
+diff --git a/drivers/misc/intel_scu_ipc.c b/drivers/misc/intel_scu_ipc.c
+new file mode 100644
+index 0000000..5843fc8
+--- /dev/null
++++ b/drivers/misc/intel_scu_ipc.c
+@@ -0,0 +1,150 @@
++#include
++#include
++#include
++#include
++
++#define IPC_STATUS_ADDR 0x04
++#define IPC_SPTR_ADDR 0x08
++#define IPC_DPTR_ADDR 0x0C
++#define IPC_READ_BUFFER 0x90
++#define IPC_WRITE_BUFFER 0x80
++#define IPC_IOC 0x100
++
++/*
++ * Command Register (Write Only):
++ * A write to this register results in an interrupt to the SCU core processor
++ * Format:
++ * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
++ */
++void intel_scu_ipc_send_command(u32 cmd)
++{
++ writel(cmd | IPC_IOC, CONFIG_SCU_IPC_BASE);
++}
++
++/*
++ * IPC Write Buffer (Write Only):
++ * 16-byte buffer for sending data associated with IPC command to
++ * SCU. Size of the data is specified in the IPC_COMMAND_REG register
++ */
++void ipc_data_writel(u32 data, u32 offset)
++{ /* Write ipc data */
++ writel(data, CONFIG_SCU_IPC_BASE + IPC_WRITE_BUFFER + offset);
++}
++
++/*
++ * Status Register (Read Only):
++ * Driver will read this register to get the ready/busy status of the IPC
++ * block and error status of the IPC command that was just processed by SCU
++ * Format:
++ * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
++ */
++
++u32 ipc_read_status(void)
++{
++ return readl(CONFIG_SCU_IPC_BASE + IPC_STATUS_ADDR);
++}
++
++u8 ipc_data_readb(u32 offset)
++{ /* Read ipc byte data */
++ return readb(CONFIG_SCU_IPC_BASE + IPC_READ_BUFFER + offset);
++}
++
++u32 ipc_data_readl(u32 offset)
++{ /* Read ipc u32 data */
++ return readl(CONFIG_SCU_IPC_BASE + IPC_READ_BUFFER + offset);
++}
++
++int intel_scu_ipc_check_status(void)
++{
++ int ret = 0;
++ int status = 0;
++ int loop_count = 3000000;
++
++ while ((ipc_read_status() & 1) && --loop_count)
++ udelay(1);
++ if (loop_count == 0)
++ ret = -ETIMEDOUT;
++
++ status = ipc_read_status();
++
++ if (status & 0x2) {
++ printf("%s() status=0x%08x\n", __func__, status);
++ return -EIO;
++ }
++ status++;
++ return ret;
++}
++
++/**
++ * intel_scu_ipc_simple_command - send a simple command
++ * @cmd: command
++ * @sub: sub type
++ *
++ * Issue a simple command to the SCU. Do not use this interface if
++ * you must then access data as any data values may be overwritten
++ * by another SCU access by the time this function returns.
++ *
++ * This function may sleep. Locking for SCU accesses is handled for
++ * the caller.
++ */
++int intel_scu_ipc_simple_command(int cmd, int sub)
++{
++ int err = 0;
++
++ intel_scu_ipc_send_command(sub << 12 | cmd);
++ err = intel_scu_ipc_check_status();
++ return err;
++}
++
++int intel_scu_ipc_raw_cmd(u32 cmd, u32 sub, u8 * in, u8 inlen, u32 * out,
++ u32 outlen, u32 dptr, u32 sptr)
++{
++ int i, err;
++ u32 wbuf[4];
++
++ if (inlen > 16)
++ return -EINVAL;
++
++ memcpy(wbuf, in, inlen);
++
++ writel(dptr, CONFIG_SCU_IPC_BASE + IPC_DPTR_ADDR);
++ writel(sptr, CONFIG_SCU_IPC_BASE + IPC_SPTR_ADDR);
++
++ /**
++ * SRAM controller don't support 8bit write, it only supports
++ * 32bit write, so we have to write into the WBUF in 32bit,
++ * and SCU FW will use the inlen to determine the actual input
++ * data length in the WBUF.
++ */
++ for (i = 0; i < ((inlen + 3) / 4); i++)
++ ipc_data_writel(wbuf[i], 4 * i);
++
++ /**
++ * Watchdog IPC command is an exception here using double word
++ * as the unit of input data size because of some historical
++ * reasons and SCU FW is doing so.
++ */
++ if ((cmd & 0xFF) == IPCMSG_WATCHDOG_TIMER)
++ inlen = (inlen + 3) / 4;
++
++ intel_scu_ipc_send_command((inlen << 16) | (sub << 12) | cmd);
++ err = intel_scu_ipc_check_status();
++
++ for (i = 0; i < outlen; i++)
++ *out++ = ipc_data_readl(4 * i);
++
++ return err;
++}
++
++int intel_scu_ipc_command(u32 cmd, u32 sub, u8 * in, u8 inlen,
++ u32 * out, u32 outlen)
++{
++ int ret;
++ ret = intel_scu_ipc_raw_cmd(cmd, sub, in, inlen, out, outlen, 0, 0);
++ return ret;
++}
++
++int init_scu_ipc(void)
++{
++ return 0;
++}
+diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
+index 931922b..c88b42b 100644
+--- a/drivers/mmc/Makefile
++++ b/drivers/mmc/Makefile
+@@ -30,6 +30,7 @@ obj-$(CONFIG_DWMMC) += dw_mmc.o
+ obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
+ obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
+ obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
++obj-$(CONFIG_TANGIER_SDHCI) += tangier_sdhci.o
+ ifdef CONFIG_SPL_BUILD
+ obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
+ else
+diff --git a/drivers/mmc/tangier_sdhci.c b/drivers/mmc/tangier_sdhci.c
+new file mode 100644
+index 0000000..3337651
+--- /dev/null
++++ b/drivers/mmc/tangier_sdhci.c
+@@ -0,0 +1,38 @@
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++int tangier_sdhci_init(u32 regbase, int index, int bus_width)
++{
++ struct sdhci_host *host = NULL;
++
++ host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
++ if (!host) {
++ printf("sdhci__host malloc fail!\n");
++ return 1;
++ }
++
++ memset(host, 0x00, sizeof(struct sdhci_host));
++
++ host->name = "tangier_sdhci";
++ host->ioaddr = (void *)regbase;
++
++ host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
++ SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
++ SDHCI_QUIRK_WAIT_SEND_CMD;
++ host->voltages = MMC_VDD_165_195; //MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
++ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
++
++ host->index = index;
++
++ host->host_caps = MMC_MODE_HC;
++
++ add_sdhci(host, 200000000, 400000);
++
++ return 0;
++}
+diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
+index 571c18f..1bdf0f5 100644
+--- a/drivers/serial/Makefile
++++ b/drivers/serial/Makefile
+@@ -6,6 +6,7 @@
+ #
+
+ obj-y += serial.o
++obj-y += serial_tng.o
+
+ obj-$(CONFIG_ALTERA_UART) += altera_uart.o
+ obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
+index df05bde..9e493dc 100644
+--- a/drivers/serial/serial.c
++++ b/drivers/serial/serial.c
+@@ -159,6 +159,7 @@ serial_initfunc(sa1100_serial_initialize);
+ serial_initfunc(sh_serial_initialize);
+ serial_initfunc(arm_dcc_initialize);
+ serial_initfunc(mxs_auart_initialize);
++serial_initfunc(tng_serial_initialize);
+ serial_initfunc(arc_serial_initialize);
+
+ /**
+diff --git a/drivers/serial/serial_tng.c b/drivers/serial/serial_tng.c
+new file mode 100644
+index 0000000..d6d6753
+--- /dev/null
++++ b/drivers/serial/serial_tng.c
+@@ -0,0 +1,252 @@
++/*
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering,
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#include
++#include
++
++#include
++
++#define cpu_relax() asm volatile("rep; nop")
++
++#define UART_GLOBAL 0xff010000
++
++#define UART_OFFSET 0x80
++
++#define SERIAL_BASE_ADDR (UART_GLOBAL + (UART_OFFSET * (dev_index + 1)))
++
++#define XMTRDY 0x20
++#define LSR_DR (0x01)
++
++#define DLAB 0x80
++
++#define TXR 0 /* Transmit register (WRITE) */
++#define RXR 0 /* Receive register (READ) */
++#define IER 1 /* Interrupt Enable */
++#define IIR 2 /* Interrupt ID */
++#define FCR 2 /* FIFO control */
++#define LCR 3 /* Line control */
++#define MCR 4 /* Modem control */
++#define LSR 5 /* Line Status */
++#define MSR 6 /* Modem Status */
++#define DLL 0 /* Divisor Latch Low */
++#define DLH 1 /* Divisor latch High */
++#define MUL 0x34 /* DDS Multiplier */
++#define DIV 0x38 /* DDS Divisor */
++
++/* Multi serial device functions */
++#define DECLARE_TNG_SERIAL_FUNCTIONS(port) \
++ int tng_serial##port##_init(void) \
++ { \
++ return serial_init_dev(port); \
++ } \
++ int tng_serial##port##_shutdown(void) \
++ { \
++ return serial_shutdown_dev(port); \
++ } \
++ void tng_serial##port##_setbrg(void) \
++ { \
++ serial_setbrg_dev(port); \
++ } \
++ int tng_serial##port##_getc(void) \
++ { \
++ return serial_getc_dev(port); \
++ } \
++ int tng_serial##port##_tstc(void) \
++ { \
++ return serial_tstc_dev(port); \
++ } \
++ void tng_serial##port##_putc(const char c) \
++ { \
++ serial_putc_dev(port, c); \
++ } \
++ void tng_serial##port##_puts(const char *s) \
++ { \
++ serial_puts_dev(port, s); \
++ }
++
++#define INIT_TNG_SERIAL_STRUCTURE(port, __name) { \
++ .name = __name, \
++ .start = tng_serial##port##_init, \
++ .stop = tng_serial##port##_shutdown, \
++ .setbrg = tng_serial##port##_setbrg, \
++ .getc = tng_serial##port##_getc, \
++ .tstc = tng_serial##port##_tstc, \
++ .putc = tng_serial##port##_putc, \
++ .puts = tng_serial##port##_puts, \
++}
++
++#ifdef CONFIG_HWFLOW
++static int hwflow;
++#endif
++
++void _serial_setbrg(const int dev_index)
++{
++ return;
++}
++
++static inline void serial_setbrg_dev(unsigned int dev_index)
++{
++ _serial_setbrg(dev_index);
++}
++
++/*
++ * Initialise the serial port.
++ */
++static int serial_init_dev(const int dev_index)
++{
++ unsigned char c;
++ unsigned divisor = 16;
++
++ c = readb(SERIAL_BASE_ADDR + LCR);
++ writeb(c | DLAB, SERIAL_BASE_ADDR + LCR);
++ writeb(divisor & 0xff, SERIAL_BASE_ADDR + DLL);
++ writeb((divisor >> 8) & 0xff, SERIAL_BASE_ADDR + DLH);
++ writeb(c & ~DLAB, SERIAL_BASE_ADDR + LCR);
++ writeb(0x2, SERIAL_BASE_ADDR + IER); /* TIE enable */
++ writeb(0x3, SERIAL_BASE_ADDR + LCR); /* 8n1 */
++ writeb(0, SERIAL_BASE_ADDR + FCR); /* no fifo */
++ writeb(0x3, SERIAL_BASE_ADDR + MCR); /* DTR + RTS */
++ writeb(7, SERIAL_BASE_ADDR + FCR);
++ writel(0x2ee0, SERIAL_BASE_ADDR + MUL);
++ writel(0x3d09, SERIAL_BASE_ADDR + DIV);
++
++ return 0;
++}
++
++/*
++ * Shutdown the serial port.
++ */
++static int serial_shutdown_dev(const int dev_index)
++{
++ unsigned char c;
++
++ writeb(0x0, SERIAL_BASE_ADDR + IER); /* TIE disable */
++ c = readb(SERIAL_BASE_ADDR + MCR);
++ writeb(c & ~0x08, SERIAL_BASE_ADDR + MCR); /* DTR + RTS */
++ c = readb(SERIAL_BASE_ADDR + LCR);
++ writeb(c & ~0x40, SERIAL_BASE_ADDR + LCR);
++ writeb(0x7, SERIAL_BASE_ADDR + FCR);
++ writeb(0x0, SERIAL_BASE_ADDR + FCR); /* no fifo */
++
++ return 0;
++}
++
++/*
++ * Read a single byte from the serial port.
++ */
++int _serial_getc(const int dev_index)
++{
++ while ((readb(SERIAL_BASE_ADDR + LSR) & LSR_DR) == 0) {
++ if (gd->have_console)
++ break;
++ }
++
++ return readb(SERIAL_BASE_ADDR + RXR) & 0xff;
++}
++
++static inline int serial_getc_dev(unsigned int dev_index)
++{
++ return _serial_getc(dev_index);
++}
++
++/*
++ * Output a single byte to the serial port.
++ */
++void _serial_putc(const char c, const int dev_index)
++{
++ while ((readb(SERIAL_BASE_ADDR + LSR) & XMTRDY) == 0)
++ cpu_relax();
++
++ writeb(c, SERIAL_BASE_ADDR + TXR);
++
++ /* If \n, also do \r */
++ if (c == '\n')
++ serial_putc('\r');
++}
++
++static inline void serial_putc_dev(unsigned int dev_index, const char c)
++{
++ _serial_putc(c, dev_index);
++}
++
++/*
++ * Test whether a character is in the RX buffer
++ */
++int _serial_tstc(const int dev_index)
++{
++ return (readb(SERIAL_BASE_ADDR + LSR) & LSR_DR) != 0;
++}
++
++static inline int serial_tstc_dev(unsigned int dev_index)
++{
++ return _serial_tstc(dev_index);
++}
++
++void _serial_puts(const char *s, const int dev_index)
++{
++ while (*s) {
++ _serial_putc(*s++, dev_index);
++ }
++ return;
++}
++
++static inline void serial_puts_dev(int dev_index, const char *s)
++{
++ return _serial_puts(s, dev_index);
++}
++
++DECLARE_TNG_SERIAL_FUNCTIONS(0);
++struct serial_device tng_serial0_device =
++INIT_TNG_SERIAL_STRUCTURE(0, "tng_serial0");
++DECLARE_TNG_SERIAL_FUNCTIONS(1);
++struct serial_device tng_serial1_device =
++INIT_TNG_SERIAL_STRUCTURE(1, "tng_serial1");
++DECLARE_TNG_SERIAL_FUNCTIONS(2);
++struct serial_device tng_serial2_device =
++INIT_TNG_SERIAL_STRUCTURE(2, "tng_serial2");
++
++__weak struct serial_device *default_serial_console(void)
++{
++#if defined(CONFIG_SYS_TNG_SERIAL0)
++ return &tng_serial0_device;
++#elif defined(CONFIG_SYS_TNG_SERIAL1)
++ return &tng_serial1_device;
++#elif defined(CONFIG_SYS_TNG_SERIAL2)
++ return &tng_serial2_device;
++#else
++#error "CONFIG_SERIAL? missing."
++#endif
++}
++
++void tng_serial_initialize(void)
++{
++#if defined(CONFIG_SYS_TNG_SERIAL0)
++ serial_init_dev(0);
++ serial_register(&tng_serial0_device);
++#endif
++#if defined(CONFIG_SYS_TNG_SERIAL1)
++ serial_init_dev(1);
++ serial_register(&tng_serial1_device);
++#endif
++#if defined(CONFIG_SYS_TNG_SERIAL2)
++ serial_init_dev(2);
++ serial_register(&tng_serial2_device);
++#endif
++}
+diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
+new file mode 100644
+index 0000000..2c05ec9
+--- /dev/null
++++ b/drivers/usb/dwc3/Kconfig
+@@ -0,0 +1,26 @@
++config USB_DWC3
++ tristate "DesignWare USB3 DRD Core Support"
++ depends on (USB || USB_GADGET)
++ select USB_OTG_UTILS
++ select USB_XHCI_PLATFORM
++ help
++ Say Y or M here if your system has a Dual Role SuperSpeed
++ USB controller based on the DesignWare USB3 IP Core.
++
++ If you choose to build this driver is a dynamically linked
++ module, the module will be called dwc3.ko.
++
++if USB_DWC3
++
++config USB_DWC3_DEBUG
++ bool "Enable Debugging Messages"
++ help
++ Say Y here to enable debugging messages on DWC3 Driver.
++
++config USB_DWC3_VERBOSE
++ bool "Enable Verbose Debugging Messages"
++ depends on USB_DWC3_DEBUG
++ help
++ Say Y here to enable verbose debugging messages on DWC3 Driver.
++
++endif
+diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
+new file mode 100644
+index 0000000..1b5d353
+--- /dev/null
++++ b/drivers/usb/dwc3/Makefile
+@@ -0,0 +1,8 @@
++obj-$(CONFIG_USB_DWC3) += dwc3_core.o dwc3_ep0.o dwc3_misc.o
++obj-$(CONFIG_USB_DWC3_GADGET) += dwc3_gadget.o
++obj-$(CONFIG_USB_DWC3_HOST) += dwc3_host.o
++
++ccflags-y := $(call cc-option,-Wno-unused-variable) \
++ $(call cc-option,-Wno-unused-but-set-variable) \
++ $(call cc-option,-Wno-unused-label)
++
+diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
+new file mode 100644
+index 0000000..46f0c2f
+--- /dev/null
++++ b/drivers/usb/dwc3/core.h
+@@ -0,0 +1,814 @@
++/**
++ * core.h - DesignWare USB3 DRD Core Header
++ *
++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Authors: Felipe Balbi ,
++ * Sebastian Andrzej Siewior
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __DRIVERS_USB_DWC3_CORE_H
++#define __DRIVERS_USB_DWC3_CORE_H
++
++#include
++#include
++#include
++#include "misc.h"
++
++/* Global constants */
++#define DWC3_ENDPOINTS_NUM 32
++
++#define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
++#define DWC3_EVENT_TYPE_MASK 0xfe
++
++#define DWC3_EVENT_TYPE_DEV 0
++#define DWC3_EVENT_TYPE_CARKIT 3
++#define DWC3_EVENT_TYPE_I2C 4
++
++#define DWC3_DEVICE_EVENT_DISCONNECT 0
++#define DWC3_DEVICE_EVENT_RESET 1
++#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
++#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
++#define DWC3_DEVICE_EVENT_WAKEUP 4
++#define DWC3_DEVICE_EVENT_EOPF 6
++#define DWC3_DEVICE_EVENT_SOF 7
++#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
++#define DWC3_DEVICE_EVENT_CMD_CMPL 10
++#define DWC3_DEVICE_EVENT_OVERFLOW 11
++
++#define DWC3_GEVNTCOUNT_MASK 0xfffc
++#define DWC3_GSNPSID_MASK 0xffff0000
++#define DWC3_GSNPSREV_MASK 0xffff
++
++/* Global Registers */
++#define DWC3_GSBUSCFG0 0xc100
++#define DWC3_GSBUSCFG1 0xc104
++#define DWC3_GTXTHRCFG 0xc108
++#define DWC3_GRXTHRCFG 0xc10c
++#define DWC3_GCTL 0xc110
++#define DWC3_GEVTEN 0xc114
++#define DWC3_GSTS 0xc118
++#define DWC3_GSNPSID 0xc120
++#define DWC3_GGPIO 0xc124
++#define DWC3_GUID 0xc128
++#define DWC3_GUCTL 0xc12c
++#define DWC3_GBUSERRADDR0 0xc130
++#define DWC3_GBUSERRADDR1 0xc134
++#define DWC3_GPRTBIMAP0 0xc138
++#define DWC3_GPRTBIMAP1 0xc13c
++#define DWC3_GHWPARAMS0 0xc140
++#define DWC3_GHWPARAMS1 0xc144
++#define DWC3_GHWPARAMS2 0xc148
++#define DWC3_GHWPARAMS3 0xc14c
++#define DWC3_GHWPARAMS4 0xc150
++#define DWC3_GHWPARAMS5 0xc154
++#define DWC3_GHWPARAMS6 0xc158
++#define DWC3_GHWPARAMS7 0xc15c
++#define DWC3_GDBGFIFOSPACE 0xc160
++#define DWC3_GDBGLTSSM 0xc164
++#define DWC3_GPRTBIMAP_HS0 0xc180
++#define DWC3_GPRTBIMAP_HS1 0xc184
++#define DWC3_GPRTBIMAP_FS0 0xc188
++#define DWC3_GPRTBIMAP_FS1 0xc18c
++
++#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
++#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
++
++#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
++
++#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
++
++#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
++#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
++
++#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
++#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
++#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
++#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
++
++#define DWC3_GHWPARAMS8 0xc600
++
++/* Device Registers */
++#define DWC3_DCFG 0xc700
++#define DWC3_DCTL 0xc704
++#define DWC3_DEVTEN 0xc708
++#define DWC3_DSTS 0xc70c
++#define DWC3_DGCMDPAR 0xc710
++#define DWC3_DGCMD 0xc714
++#define DWC3_DALEPENA 0xc720
++#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
++#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
++#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
++#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
++
++/* OTG Registers */
++#define DWC3_OCFG 0xcc00
++#define DWC3_OCTL 0xcc04
++#define DWC3_OEVTEN 0xcc08
++#define DWC3_OSTS 0xcc0C
++
++/* Bit fields */
++
++/* Global Configuration Register */
++#define DWC3_GCTL_PWRDNSCALE(n) (n << 19)
++#define DWC3_GCTL_U2RSTECN (1 << 16)
++#define DWC3_GCTL_RAMCLKSEL(x) ((x & DWC3_GCTL_CLK_MASK) << 6)
++#define DWC3_GCTL_CLK_BUS (0)
++#define DWC3_GCTL_CLK_PIPE (1)
++#define DWC3_GCTL_CLK_PIPEHALF (2)
++#define DWC3_GCTL_CLK_MASK (3)
++
++#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
++#define DWC3_GCTL_PRTCAPDIR(n) (n << 12)
++#define DWC3_GCTL_PRTCAP_HOST 1
++#define DWC3_GCTL_PRTCAP_DEVICE 2
++#define DWC3_GCTL_PRTCAP_OTG 3
++
++#define DWC3_GCTL_CORESOFTRESET (1 << 11)
++#define DWC3_GCTL_SCALEDOWN(n) (n << 4)
++#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
++#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
++
++/* Global USB2 PHY Configuration Register */
++#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
++#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
++
++/* Global USB3 PIPE Control Register */
++#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
++#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
++
++/* Global HWPARAMS1 Register */
++#define DWC3_GHWPARAMS1_EN_PWROPT(n) ((n & (3 << 24)) >> 24)
++#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
++#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
++
++/* Device Configuration Register */
++#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
++#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
++
++#define DWC3_DCFG_SPEED_MASK (7 << 0)
++#define DWC3_DCFG_SUPERSPEED (4 << 0)
++#define DWC3_DCFG_HIGHSPEED (0 << 0)
++#define DWC3_DCFG_FULLSPEED2 (1 << 0)
++#define DWC3_DCFG_LOWSPEED (2 << 0)
++#define DWC3_DCFG_FULLSPEED1 (3 << 0)
++
++/* Device Control Register */
++#define DWC3_DCTL_RUN_STOP (1 << 31)
++#define DWC3_DCTL_CSFTRST (1 << 30)
++#define DWC3_DCTL_LSFTRST (1 << 29)
++
++#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
++#define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24)
++
++#define DWC3_DCTL_APPL1RES (1 << 23)
++
++#define DWC3_DCTL_INITU2ENA (1 << 12)
++#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
++#define DWC3_DCTL_INITU1ENA (1 << 10)
++#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
++#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
++
++#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
++#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
++
++#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
++#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
++#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
++#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
++#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
++#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
++#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
++
++/* Device Event Enable Register */
++#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
++#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
++#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
++#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
++#define DWC3_DEVTEN_SOFEN (1 << 7)
++#define DWC3_DEVTEN_EOPFEN (1 << 6)
++#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
++#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
++#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
++#define DWC3_DEVTEN_USBRSTEN (1 << 1)
++#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
++
++/* Device Status Register */
++#define DWC3_DSTS_PWRUPREQ (1 << 24)
++#define DWC3_DSTS_COREIDLE (1 << 23)
++#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
++
++#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
++#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
++
++#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
++
++#define DWC3_DSTS_SOFFN_MASK (0x3ff << 3)
++#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
++
++#define DWC3_DSTS_CONNECTSPD (7 << 0)
++
++#define DWC3_DSTS_SUPERSPEED (4 << 0)
++#define DWC3_DSTS_HIGHSPEED (0 << 0)
++#define DWC3_DSTS_FULLSPEED2 (1 << 0)
++#define DWC3_DSTS_LOWSPEED (2 << 0)
++#define DWC3_DSTS_FULLSPEED1 (3 << 0)
++
++/* Device Generic Command Register */
++#define DWC3_DGCMD_SET_LMP 0x01
++#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
++#define DWC3_DGCMD_XMIT_FUNCTION 0x03
++#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
++#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
++#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
++#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
++
++/* Device Endpoint Command Register */
++#define DWC3_DEPCMD_PARAM_SHIFT 16
++#define DWC3_DEPCMD_PARAM(x) (x << DWC3_DEPCMD_PARAM_SHIFT)
++#define DWC3_DEPCMD_GET_RSC_IDX(x) ((x >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
++#define DWC3_DEPCMD_STATUS_MASK (0x0f << 12)
++#define DWC3_DEPCMD_STATUS(x) ((x & DWC3_DEPCMD_STATUS_MASK) >> 12)
++#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
++#define DWC3_DEPCMD_CMDACT (1 << 10)
++#define DWC3_DEPCMD_CMDIOC (1 << 8)
++
++#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
++#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
++#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
++#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
++#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
++#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
++#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
++#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
++#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
++
++/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
++#define DWC3_DALEPENA_EP(n) (1 << n)
++
++#define DWC3_DEPCMD_TYPE_CONTROL 0
++#define DWC3_DEPCMD_TYPE_ISOC 1
++#define DWC3_DEPCMD_TYPE_BULK 2
++#define DWC3_DEPCMD_TYPE_INTR 3
++
++/* Structures */
++
++struct dwc3_trb_hw;
++
++/**
++ * struct dwc3_event_buffer - Software event buffer representation
++ * @list: a list of event buffers
++ * @buf: _THE_ buffer
++ * @length: size of this buffer
++ * @dma: dma_addr_t
++ * @dwc: pointer to DWC controller
++ */
++struct dwc3_event_buffer {
++ void *buf;
++ unsigned length;
++ unsigned int lpos;
++
++ dma_addr_t dma;
++
++ struct dwc3 *dwc;
++};
++
++#define DWC3_EP_FLAG_STALLED (1 << 0)
++#define DWC3_EP_FLAG_WEDGED (1 << 1)
++
++#define DWC3_EP_DIRECTION_TX true
++#define DWC3_EP_DIRECTION_RX false
++
++#define DWC3_TRB_NUM 32
++#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
++
++/**
++ * struct dwc3_ep - device side endpoint representation
++ * @endpoint: usb endpoint
++ * @request_list: list of requests for this endpoint
++ * @req_queued: list of requests on this ep which have TRBs setup
++ * @trb_pool: array of transaction buffers
++ * @trb_pool_dma: dma address of @trb_pool
++ * @free_slot: next slot which is going to be used
++ * @busy_slot: first slot which is owned by HW
++ * @desc: usb_endpoint_descriptor pointer
++ * @dwc: pointer to DWC controller
++ * @flags: endpoint flags (wedged, stalled, ...)
++ * @current_trb: index of current used trb
++ * @number: endpoint number (1 - 15)
++ * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
++ * @res_trans_idx: Resource transfer index
++ * @interval: the intervall on which the ISOC transfer is started
++ * @name: a human readable name e.g. ep1out-bulk
++ * @direction: true for TX, false for RX
++ * @stream_capable: true when streams are enabled
++ */
++struct dwc3_ep {
++ struct usb_ep endpoint;
++ struct list_head request_list;
++ struct list_head req_queued;
++
++ struct dwc3_trb_hw *trb_pool;
++ dma_addr_t trb_pool_dma;
++ u32 free_slot;
++ u32 busy_slot;
++ const struct usb_endpoint_descriptor *desc;
++ const struct usb_ss_ep_comp_descriptor *comp_desc;
++ struct dwc3 *dwc;
++
++ unsigned flags;
++#define DWC3_EP_ENABLED (1 << 0)
++#define DWC3_EP_STALL (1 << 1)
++#define DWC3_EP_WEDGE (1 << 2)
++#define DWC3_EP_BUSY (1 << 4)
++#define DWC3_EP_PENDING_REQUEST (1 << 5)
++
++ /* This last one is specific to EP0 */
++#define DWC3_EP0_DIR_IN (1 << 31)
++
++ unsigned current_trb;
++
++ u8 number;
++ u8 type;
++ u8 res_trans_idx;
++ u32 interval;
++
++ char name[20];
++
++ unsigned direction:1;
++ unsigned stream_capable:1;
++};
++
++enum dwc3_phy {
++ DWC3_PHY_UNKNOWN = 0,
++ DWC3_PHY_USB3,
++ DWC3_PHY_USB2,
++};
++
++enum dwc3_ep0_next {
++ DWC3_EP0_UNKNOWN = 0,
++ DWC3_EP0_COMPLETE,
++ DWC3_EP0_NRDY_SETUP,
++ DWC3_EP0_NRDY_DATA,
++ DWC3_EP0_NRDY_STATUS,
++};
++
++enum dwc3_ep0_state {
++ EP0_UNCONNECTED = 0,
++ EP0_SETUP_PHASE,
++ EP0_DATA_PHASE,
++ EP0_STATUS_PHASE,
++};
++
++enum dwc3_link_state {
++ /* In SuperSpeed */
++ DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
++ DWC3_LINK_STATE_U1 = 0x01,
++ DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
++ DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
++ DWC3_LINK_STATE_SS_DIS = 0x04,
++ DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
++ DWC3_LINK_STATE_SS_INACT = 0x06,
++ DWC3_LINK_STATE_POLL = 0x07,
++ DWC3_LINK_STATE_RECOV = 0x08,
++ DWC3_LINK_STATE_HRESET = 0x09,
++ DWC3_LINK_STATE_CMPLY = 0x0a,
++ DWC3_LINK_STATE_LPBK = 0x0b,
++ DWC3_LINK_STATE_MASK = 0x0f,
++};
++
++enum dwc3_device_state {
++ DWC3_DEFAULT_STATE,
++ DWC3_ADDRESS_STATE,
++ DWC3_CONFIGURED_STATE,
++};
++
++/**
++ * struct dwc3_trb - transfer request block
++ * @bpl: lower 32bit of the buffer
++ * @bph: higher 32bit of the buffer
++ * @length: buffer size (up to 16mb - 1)
++ * @pcm1: packet count m1
++ * @trbsts: trb status
++ * 0 = ok
++ * 1 = missed isoc
++ * 2 = setup pending
++ * @hwo: hardware owner of descriptor
++ * @lst: last trb
++ * @chn: chain buffers
++ * @csp: continue on short packets (only supported on isoc eps)
++ * @trbctl: trb control
++ * 1 = normal
++ * 2 = control-setup
++ * 3 = control-status-2
++ * 4 = control-status-3
++ * 5 = control-data (first trb of data stage)
++ * 6 = isochronous-first (first trb of service interval)
++ * 7 = isochronous
++ * 8 = link trb
++ * others = reserved
++ * @isp_imi: interrupt on short packet / interrupt on missed isoc
++ * @ioc: interrupt on complete
++ * @sid_sofn: Stream ID / SOF Number
++ */
++struct dwc3_trb {
++ u64 bplh;
++
++ union {
++ struct {
++ u32 length:24;
++ u32 pcm1:2;
++ u32 reserved27_26:2;
++ u32 trbsts:4;
++#define DWC3_TRB_STS_OKAY 0
++#define DWC3_TRB_STS_MISSED_ISOC 1
++#define DWC3_TRB_STS_SETUP_PENDING 2
++ };
++ u32 len_pcm;
++ };
++
++ union {
++ struct {
++ u32 hwo:1;
++ u32 lst:1;
++ u32 chn:1;
++ u32 csp:1;
++ u32 trbctl:6;
++ u32 isp_imi:1;
++ u32 ioc:1;
++ u32 reserved13_12:2;
++ u32 sid_sofn:16;
++ u32 reserved31_30:2;
++ };
++ u32 control;
++ };
++} __packed;
++
++/**
++ * struct dwc3_trb_hw - transfer request block (hw format)
++ * @bpl: DW0-3
++ * @bph: DW4-7
++ * @size: DW8-B
++ * @trl: DWC-F
++ */
++struct dwc3_trb_hw {
++ __le32 bpl;
++ __le32 bph;
++ __le32 size;
++ __le32 ctrl;
++} __packed;
++
++static inline void dwc3_trb_to_hw(struct dwc3_trb *nat, struct dwc3_trb_hw *hw)
++{
++ hw->bpl = cpu_to_le32(lower_32_bits(nat->bplh));
++ hw->bph = cpu_to_le32(upper_32_bits(nat->bplh));
++ hw->size = cpu_to_le32p(&nat->len_pcm);
++ /* HWO is written last */
++ hw->ctrl = cpu_to_le32p(&nat->control);
++}
++
++static inline void dwc3_trb_to_nat(struct dwc3_trb_hw *hw, struct dwc3_trb *nat)
++{
++ u64 bplh;
++
++ bplh = le32_to_cpup(&hw->bpl);
++ bplh |= (u64) le32_to_cpup(&hw->bph) << 32;
++ nat->bplh = bplh;
++
++ nat->len_pcm = le32_to_cpup(&hw->size);
++ nat->control = le32_to_cpup(&hw->ctrl);
++}
++
++/**
++ * dwc3_hwparams - copy of HWPARAMS registers
++ * @hwparams0 - GHWPARAMS0
++ * @hwparams1 - GHWPARAMS1
++ * @hwparams2 - GHWPARAMS2
++ * @hwparams3 - GHWPARAMS3
++ * @hwparams4 - GHWPARAMS4
++ * @hwparams5 - GHWPARAMS5
++ * @hwparams6 - GHWPARAMS6
++ * @hwparams7 - GHWPARAMS7
++ * @hwparams8 - GHWPARAMS8
++ */
++struct dwc3_hwparams {
++ u32 hwparams0;
++ u32 hwparams1;
++ u32 hwparams2;
++ u32 hwparams3;
++ u32 hwparams4;
++ u32 hwparams5;
++ u32 hwparams6;
++ u32 hwparams7;
++ u32 hwparams8;
++};
++
++/* HWPARAMS0 */
++#define DWC3_MODE(n) ((n) & 0x7)
++
++#define DWC3_MODE_DEVICE 0
++#define DWC3_MODE_HOST 1
++#define DWC3_MODE_DRD 2
++#define DWC3_MODE_HUB 3
++
++/* HWPARAMS1 */
++#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
++
++struct dwc3_request {
++ struct usb_request request;
++ struct list_head list;
++ struct dwc3_ep *dep;
++
++ u8 epnum;
++ struct dwc3_trb_hw *trb;
++ dma_addr_t trb_dma;
++
++ unsigned direction:1;
++ unsigned mapped:1;
++ unsigned queued:1;
++};
++
++/**
++ * struct dwc3 - representation of our controller
++ * @ctrl_req: usb control request which is used for ep0
++ * @ep0_trb: trb which is used for the ctrl_req
++ * @ep0_bounce: bounce buffer for ep0
++ * @setup_buf: used while precessing STD USB requests
++ * @ctrl_req_addr: dma address of ctrl_req
++ * @ep0_trb: dma address of ep0_trb
++ * @ep0_usb_req: dummy req used while handling STD USB requests
++ * @setup_buf_addr: dma address of setup_buf
++ * @ep0_bounce_addr: dma address of ep0_bounce
++ * @lock: for synchronizing
++ * @dev: pointer to our struct device
++ * @xhci: pointer to our xHCI child
++ * @event_buffer_list: a list of event buffers
++ * @gadget: device side representation of the peripheral controller
++ * @gadget_driver: pointer to the gadget driver
++ * @regs: base address for our registers
++ * @regs_size: address space size
++ * @irq: IRQ number
++ * @num_event_buffers: calculated number of event buffers
++ * @u1u2: only used on revisions <1.83a for workaround
++ * @maximum_speed: maximum speed requested (mainly for testing purposes)
++ * @revision: revision register contents
++ * @mode: mode of operation
++ * @is_selfpowered: true when we are selfpowered
++ * @three_stage_setup: set if we perform a three phase setup
++ * @ep0_bounced: true when we used bounce buffer
++ * @ep0_expect_in: true when we expect a DATA IN transfer
++ * @start_config_issued: true when StartConfig command has been issued
++ * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
++ * @ep0_next_event: hold the next expected event
++ * @ep0state: state of endpoint zero
++ * @link_state: link state
++ * @speed: device speed (super, high, full, low)
++ * @mem: points to start of memory which is used for this struct.
++ * @hwparams: copy of hwparams registers
++ * @root: debugfs root folder pointer
++ */
++struct dwc3 {
++ struct usb_ctrlrequest *ctrl_req;
++ struct dwc3_trb_hw *ep0_trb;
++ void *ep0_bounce;
++ u8 *setup_buf;
++ dma_addr_t ctrl_req_addr;
++ dma_addr_t ep0_trb_addr;
++ dma_addr_t setup_buf_addr;
++ dma_addr_t ep0_bounce_addr;
++ struct dwc3_request ep0_usb_req;
++ /* device lock */
++ spinlock_t lock;
++ struct device *dev;
++
++ struct platform_device *xhci;
++ struct resource *res;
++
++ struct dwc3_event_buffer **ev_buffs;
++ struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
++
++ struct usb_gadget gadget;
++ struct usb_gadget_driver *gadget_driver;
++
++ void __iomem *regs;
++ size_t regs_size;
++
++ int irq;
++
++ u32 num_event_buffers;
++ u32 u1u2;
++ u32 maximum_speed;
++ u32 revision;
++ u32 mode;
++
++#define DWC3_REVISION_173A 0x5533173a
++#define DWC3_REVISION_175A 0x5533175a
++#define DWC3_REVISION_180A 0x5533180a
++#define DWC3_REVISION_183A 0x5533183a
++#define DWC3_REVISION_185A 0x5533185a
++#define DWC3_REVISION_188A 0x5533188a
++#define DWC3_REVISION_190A 0x5533190a
++
++ unsigned is_selfpowered:1;
++ unsigned three_stage_setup:1;
++ unsigned ep0_bounced:1;
++ unsigned ep0_expect_in:1;
++ unsigned start_config_issued:1;
++ unsigned setup_packet_pending:1;
++ unsigned delayed_status:1;
++
++ enum dwc3_ep0_next ep0_next_event;
++ enum dwc3_ep0_state ep0state;
++ enum dwc3_link_state link_state;
++ enum dwc3_device_state dev_state;
++
++ u8 speed;
++ void *mem;
++
++ struct dwc3_hwparams hwparams;
++ struct dentry *root;
++};
++
++/* -------------------------------------------------------------------------- */
++
++#define DWC3_TRBSTS_OK 0
++#define DWC3_TRBSTS_MISSED_ISOC 1
++#define DWC3_TRBSTS_SETUP_PENDING 2
++
++#define DWC3_TRBCTL_NORMAL 1
++#define DWC3_TRBCTL_CONTROL_SETUP 2
++#define DWC3_TRBCTL_CONTROL_STATUS2 3
++#define DWC3_TRBCTL_CONTROL_STATUS3 4
++#define DWC3_TRBCTL_CONTROL_DATA 5
++#define DWC3_TRBCTL_ISOCHRONOUS_FIRST 6
++#define DWC3_TRBCTL_ISOCHRONOUS 7
++#define DWC3_TRBCTL_LINK_TRB 8
++
++/* -------------------------------------------------------------------------- */
++
++struct dwc3_event_type {
++ u32 is_devspec:1;
++ u32 type:6;
++ u32 reserved8_31:25;
++} __packed;
++
++#define DWC3_DEPEVT_XFERCOMPLETE 0x01
++#define DWC3_DEPEVT_XFERINPROGRESS 0x02
++#define DWC3_DEPEVT_XFERNOTREADY 0x03
++#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
++#define DWC3_DEPEVT_STREAMEVT 0x06
++#define DWC3_DEPEVT_EPCMDCMPLT 0x07
++
++/**
++ * struct dwc3_event_depvt - Device Endpoint Events
++ * @one_bit: indicates this is an endpoint event (not used)
++ * @endpoint_number: number of the endpoint
++ * @endpoint_event: The event we have:
++ * 0x00 - Reserved
++ * 0x01 - XferComplete
++ * 0x02 - XferInProgress
++ * 0x03 - XferNotReady
++ * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
++ * 0x05 - Reserved
++ * 0x06 - StreamEvt
++ * 0x07 - EPCmdCmplt
++ * @reserved11_10: Reserved, don't use.
++ * @status: Indicates the status of the event. Refer to databook for
++ * more information.
++ * @parameters: Parameters of the current event. Refer to databook for
++ * more information.
++ */
++struct dwc3_event_depevt {
++ u32 one_bit:1;
++ u32 endpoint_number:5;
++ u32 endpoint_event:4;
++ u32 reserved11_10:2;
++ u32 status:4;
++#define DEPEVT_STATUS_BUSERR (1 << 0)
++#define DEPEVT_STATUS_SHORT (1 << 1)
++#define DEPEVT_STATUS_IOC (1 << 2)
++#define DEPEVT_STATUS_LST (1 << 3)
++
++/* Stream event only */
++#define DEPEVT_STREAMEVT_FOUND 1
++#define DEPEVT_STREAMEVT_NOTFOUND 2
++
++/* Control-only Status */
++#define DEPEVT_STATUS_CONTROL_SETUP 0
++#define DEPEVT_STATUS_CONTROL_DATA 1
++#define DEPEVT_STATUS_CONTROL_STATUS 2
++
++ u32 parameters:16;
++} __packed;
++
++/**
++ * struct dwc3_event_devt - Device Events
++ * @one_bit: indicates this is a non-endpoint event (not used)
++ * @device_event: indicates it's a device event. Should read as 0x00
++ * @type: indicates the type of device event.
++ * 0 - DisconnEvt
++ * 1 - USBRst
++ * 2 - ConnectDone
++ * 3 - ULStChng
++ * 4 - WkUpEvt
++ * 5 - Reserved
++ * 6 - EOPF
++ * 7 - SOF
++ * 8 - Reserved
++ * 9 - ErrticErr
++ * 10 - CmdCmplt
++ * 11 - EvntOverflow
++ * 12 - VndrDevTstRcved
++ * @reserved15_12: Reserved, not used
++ * @event_info: Information about this event
++ * @reserved31_24: Reserved, not used
++ */
++struct dwc3_event_devt {
++ u32 one_bit:1;
++ u32 device_event:7;
++ u32 type:4;
++ u32 reserved15_12:4;
++ u32 event_info:8;
++ u32 reserved31_24:8;
++} __packed;
++
++/**
++ * struct dwc3_event_gevt - Other Core Events
++ * @one_bit: indicates this is a non-endpoint event (not used)
++ * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
++ * @phy_port_number: self-explanatory
++ * @reserved31_12: Reserved, not used.
++ */
++struct dwc3_event_gevt {
++ u32 one_bit:1;
++ u32 device_event:7;
++ u32 phy_port_number:4;
++ u32 reserved31_12:20;
++} __packed;
++
++/**
++ * union dwc3_event - representation of Event Buffer contents
++ * @raw: raw 32-bit event
++ * @type: the type of the event
++ * @depevt: Device Endpoint Event
++ * @devt: Device Event
++ * @gevt: Global Event
++ */
++union dwc3_event {
++ u32 raw;
++ struct dwc3_event_type type;
++ struct dwc3_event_depevt depevt;
++ struct dwc3_event_devt devt;
++ struct dwc3_event_gevt gevt;
++};
++
++/*
++ * DWC3 Features to be used as Driver Data
++ */
++
++#define DWC3_HAS_PERIPHERAL BIT(0)
++#define DWC3_HAS_XHCI BIT(1)
++#define DWC3_HAS_OTG BIT(3)
++
++/* prototypes */
++void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
++
++int dwc3_host_init(struct dwc3 *dwc);
++static inline void dwc3_host_exit(struct dwc3 *dwc) {}
++
++int dwc3_gadget_init(struct dwc3 *dwc);
++void dwc3_gadget_exit(struct dwc3 *dwc);
++
++extern int dwc3_get_device_id(void);
++extern void dwc3_put_device_id(int id);
++
++#endif /* __DRIVERS_USB_DWC3_CORE_H */
+diff --git a/drivers/usb/dwc3/debug.h b/drivers/usb/dwc3/debug.h
+new file mode 100644
+index 0000000..52d0227
+--- /dev/null
++++ b/drivers/usb/dwc3/debug.h
+@@ -0,0 +1,49 @@
++/**
++ * debug.h - DesignWare USB3 DRD Controller Debug Header
++ *
++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Authors: Felipe Balbi ,
++ * Sebastian Andrzej Siewior
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include "core.h"
++
++#ifdef CONFIG_DEBUG_FS
++extern int dwc3_debugfs_init(struct dwc3 *);
++extern void dwc3_debugfs_exit(struct dwc3 *);
++#else
++static inline int dwc3_debugfs_init(struct dwc3 *d)
++{ return 0; }
++static inline void dwc3_debugfs_exit(struct dwc3 *d)
++{ }
++#endif
+diff --git a/drivers/usb/dwc3/debugfs.c b/drivers/usb/dwc3/debugfs.c
+new file mode 100644
+index 0000000..97b2c40
+--- /dev/null
++++ b/drivers/usb/dwc3/debugfs.c
+@@ -0,0 +1,521 @@
++/**
++ * debugfs.c - DesignWare USB3 DRD Controller DebugFS file
++ *
++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Authors: Felipe Balbi ,
++ * Sebastian Andrzej Siewior
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include
++#ifdef CONFIG_DWC3_off
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include "core.h"
++#include "gadget.h"
++#include "io.h"
++#include "debug.h"
++
++struct dwc3_register {
++ const char *name;
++ u32 offset;
++};
++
++#define dump_register(nm) \
++{ \
++ .name = __stringify(nm), \
++ .offset = DWC3_ ##nm, \
++}
++
++static const struct dwc3_register dwc3_regs[] = {
++ dump_register(GSBUSCFG0),
++ dump_register(GSBUSCFG1),
++ dump_register(GTXTHRCFG),
++ dump_register(GRXTHRCFG),
++ dump_register(GCTL),
++ dump_register(GEVTEN),
++ dump_register(GSTS),
++ dump_register(GSNPSID),
++ dump_register(GGPIO),
++ dump_register(GUID),
++ dump_register(GUCTL),
++ dump_register(GBUSERRADDR0),
++ dump_register(GBUSERRADDR1),
++ dump_register(GPRTBIMAP0),
++ dump_register(GPRTBIMAP1),
++ dump_register(GHWPARAMS0),
++ dump_register(GHWPARAMS1),
++ dump_register(GHWPARAMS2),
++ dump_register(GHWPARAMS3),
++ dump_register(GHWPARAMS4),
++ dump_register(GHWPARAMS5),
++ dump_register(GHWPARAMS6),
++ dump_register(GHWPARAMS7),
++ dump_register(GDBGFIFOSPACE),
++ dump_register(GDBGLTSSM),
++ dump_register(GPRTBIMAP_HS0),
++ dump_register(GPRTBIMAP_HS1),
++ dump_register(GPRTBIMAP_FS0),
++ dump_register(GPRTBIMAP_FS1),
++
++ dump_register(GUSB2PHYCFG(0)),
++ dump_register(GUSB2PHYCFG(1)),
++ dump_register(GUSB2PHYCFG(2)),
++ dump_register(GUSB2PHYCFG(3)),
++ dump_register(GUSB2PHYCFG(4)),
++ dump_register(GUSB2PHYCFG(5)),
++ dump_register(GUSB2PHYCFG(6)),
++ dump_register(GUSB2PHYCFG(7)),
++ dump_register(GUSB2PHYCFG(8)),
++ dump_register(GUSB2PHYCFG(9)),
++ dump_register(GUSB2PHYCFG(10)),
++ dump_register(GUSB2PHYCFG(11)),
++ dump_register(GUSB2PHYCFG(12)),
++ dump_register(GUSB2PHYCFG(13)),
++ dump_register(GUSB2PHYCFG(14)),
++ dump_register(GUSB2PHYCFG(15)),
++
++ dump_register(GUSB2I2CCTL(0)),
++ dump_register(GUSB2I2CCTL(1)),
++ dump_register(GUSB2I2CCTL(2)),
++ dump_register(GUSB2I2CCTL(3)),
++ dump_register(GUSB2I2CCTL(4)),
++ dump_register(GUSB2I2CCTL(5)),
++ dump_register(GUSB2I2CCTL(6)),
++ dump_register(GUSB2I2CCTL(7)),
++ dump_register(GUSB2I2CCTL(8)),
++ dump_register(GUSB2I2CCTL(9)),
++ dump_register(GUSB2I2CCTL(10)),
++ dump_register(GUSB2I2CCTL(11)),
++ dump_register(GUSB2I2CCTL(12)),
++ dump_register(GUSB2I2CCTL(13)),
++ dump_register(GUSB2I2CCTL(14)),
++ dump_register(GUSB2I2CCTL(15)),
++
++ dump_register(GUSB2PHYACC(0)),
++ dump_register(GUSB2PHYACC(1)),
++ dump_register(GUSB2PHYACC(2)),
++ dump_register(GUSB2PHYACC(3)),
++ dump_register(GUSB2PHYACC(4)),
++ dump_register(GUSB2PHYACC(5)),
++ dump_register(GUSB2PHYACC(6)),
++ dump_register(GUSB2PHYACC(7)),
++ dump_register(GUSB2PHYACC(8)),
++ dump_register(GUSB2PHYACC(9)),
++ dump_register(GUSB2PHYACC(10)),
++ dump_register(GUSB2PHYACC(11)),
++ dump_register(GUSB2PHYACC(12)),
++ dump_register(GUSB2PHYACC(13)),
++ dump_register(GUSB2PHYACC(14)),
++ dump_register(GUSB2PHYACC(15)),
++
++ dump_register(GUSB3PIPECTL(0)),
++ dump_register(GUSB3PIPECTL(1)),
++ dump_register(GUSB3PIPECTL(2)),
++ dump_register(GUSB3PIPECTL(3)),
++ dump_register(GUSB3PIPECTL(4)),
++ dump_register(GUSB3PIPECTL(5)),
++ dump_register(GUSB3PIPECTL(6)),
++ dump_register(GUSB3PIPECTL(7)),
++ dump_register(GUSB3PIPECTL(8)),
++ dump_register(GUSB3PIPECTL(9)),
++ dump_register(GUSB3PIPECTL(10)),
++ dump_register(GUSB3PIPECTL(11)),
++ dump_register(GUSB3PIPECTL(12)),
++ dump_register(GUSB3PIPECTL(13)),
++ dump_register(GUSB3PIPECTL(14)),
++ dump_register(GUSB3PIPECTL(15)),
++
++ dump_register(GTXFIFOSIZ(0)),
++ dump_register(GTXFIFOSIZ(1)),
++ dump_register(GTXFIFOSIZ(2)),
++ dump_register(GTXFIFOSIZ(3)),
++ dump_register(GTXFIFOSIZ(4)),
++ dump_register(GTXFIFOSIZ(5)),
++ dump_register(GTXFIFOSIZ(6)),
++ dump_register(GTXFIFOSIZ(7)),
++ dump_register(GTXFIFOSIZ(8)),
++ dump_register(GTXFIFOSIZ(9)),
++ dump_register(GTXFIFOSIZ(10)),
++ dump_register(GTXFIFOSIZ(11)),
++ dump_register(GTXFIFOSIZ(12)),
++ dump_register(GTXFIFOSIZ(13)),
++ dump_register(GTXFIFOSIZ(14)),
++ dump_register(GTXFIFOSIZ(15)),
++ dump_register(GTXFIFOSIZ(16)),
++ dump_register(GTXFIFOSIZ(17)),
++ dump_register(GTXFIFOSIZ(18)),
++ dump_register(GTXFIFOSIZ(19)),
++ dump_register(GTXFIFOSIZ(20)),
++ dump_register(GTXFIFOSIZ(21)),
++ dump_register(GTXFIFOSIZ(22)),
++ dump_register(GTXFIFOSIZ(23)),
++ dump_register(GTXFIFOSIZ(24)),
++ dump_register(GTXFIFOSIZ(25)),
++ dump_register(GTXFIFOSIZ(26)),
++ dump_register(GTXFIFOSIZ(27)),
++ dump_register(GTXFIFOSIZ(28)),
++ dump_register(GTXFIFOSIZ(29)),
++ dump_register(GTXFIFOSIZ(30)),
++ dump_register(GTXFIFOSIZ(31)),
++
++ dump_register(GRXFIFOSIZ(0)),
++ dump_register(GRXFIFOSIZ(1)),
++ dump_register(GRXFIFOSIZ(2)),
++ dump_register(GRXFIFOSIZ(3)),
++ dump_register(GRXFIFOSIZ(4)),
++ dump_register(GRXFIFOSIZ(5)),
++ dump_register(GRXFIFOSIZ(6)),
++ dump_register(GRXFIFOSIZ(7)),
++ dump_register(GRXFIFOSIZ(8)),
++ dump_register(GRXFIFOSIZ(9)),
++ dump_register(GRXFIFOSIZ(10)),
++ dump_register(GRXFIFOSIZ(11)),
++ dump_register(GRXFIFOSIZ(12)),
++ dump_register(GRXFIFOSIZ(13)),
++ dump_register(GRXFIFOSIZ(14)),
++ dump_register(GRXFIFOSIZ(15)),
++ dump_register(GRXFIFOSIZ(16)),
++ dump_register(GRXFIFOSIZ(17)),
++ dump_register(GRXFIFOSIZ(18)),
++ dump_register(GRXFIFOSIZ(19)),
++ dump_register(GRXFIFOSIZ(20)),
++ dump_register(GRXFIFOSIZ(21)),
++ dump_register(GRXFIFOSIZ(22)),
++ dump_register(GRXFIFOSIZ(23)),
++ dump_register(GRXFIFOSIZ(24)),
++ dump_register(GRXFIFOSIZ(25)),
++ dump_register(GRXFIFOSIZ(26)),
++ dump_register(GRXFIFOSIZ(27)),
++ dump_register(GRXFIFOSIZ(28)),
++ dump_register(GRXFIFOSIZ(29)),
++ dump_register(GRXFIFOSIZ(30)),
++ dump_register(GRXFIFOSIZ(31)),
++
++ dump_register(GEVNTADRLO(0)),
++ dump_register(GEVNTADRHI(0)),
++ dump_register(GEVNTSIZ(0)),
++ dump_register(GEVNTCOUNT(0)),
++
++ dump_register(GHWPARAMS8),
++ dump_register(DCFG),
++ dump_register(DCTL),
++ dump_register(DEVTEN),
++ dump_register(DSTS),
++ dump_register(DGCMDPAR),
++ dump_register(DGCMD),
++ dump_register(DALEPENA),
++
++ dump_register(DEPCMDPAR2(0)),
++ dump_register(DEPCMDPAR2(1)),
++ dump_register(DEPCMDPAR2(2)),
++ dump_register(DEPCMDPAR2(3)),
++ dump_register(DEPCMDPAR2(4)),
++ dump_register(DEPCMDPAR2(5)),
++ dump_register(DEPCMDPAR2(6)),
++ dump_register(DEPCMDPAR2(7)),
++ dump_register(DEPCMDPAR2(8)),
++ dump_register(DEPCMDPAR2(9)),
++ dump_register(DEPCMDPAR2(10)),
++ dump_register(DEPCMDPAR2(11)),
++ dump_register(DEPCMDPAR2(12)),
++ dump_register(DEPCMDPAR2(13)),
++ dump_register(DEPCMDPAR2(14)),
++ dump_register(DEPCMDPAR2(15)),
++ dump_register(DEPCMDPAR2(16)),
++ dump_register(DEPCMDPAR2(17)),
++ dump_register(DEPCMDPAR2(18)),
++ dump_register(DEPCMDPAR2(19)),
++ dump_register(DEPCMDPAR2(20)),
++ dump_register(DEPCMDPAR2(21)),
++ dump_register(DEPCMDPAR2(22)),
++ dump_register(DEPCMDPAR2(23)),
++ dump_register(DEPCMDPAR2(24)),
++ dump_register(DEPCMDPAR2(25)),
++ dump_register(DEPCMDPAR2(26)),
++ dump_register(DEPCMDPAR2(27)),
++ dump_register(DEPCMDPAR2(28)),
++ dump_register(DEPCMDPAR2(29)),
++ dump_register(DEPCMDPAR2(30)),
++ dump_register(DEPCMDPAR2(31)),
++
++ dump_register(DEPCMDPAR1(0)),
++ dump_register(DEPCMDPAR1(1)),
++ dump_register(DEPCMDPAR1(2)),
++ dump_register(DEPCMDPAR1(3)),
++ dump_register(DEPCMDPAR1(4)),
++ dump_register(DEPCMDPAR1(5)),
++ dump_register(DEPCMDPAR1(6)),
++ dump_register(DEPCMDPAR1(7)),
++ dump_register(DEPCMDPAR1(8)),
++ dump_register(DEPCMDPAR1(9)),
++ dump_register(DEPCMDPAR1(10)),
++ dump_register(DEPCMDPAR1(11)),
++ dump_register(DEPCMDPAR1(12)),
++ dump_register(DEPCMDPAR1(13)),
++ dump_register(DEPCMDPAR1(14)),
++ dump_register(DEPCMDPAR1(15)),
++ dump_register(DEPCMDPAR1(16)),
++ dump_register(DEPCMDPAR1(17)),
++ dump_register(DEPCMDPAR1(18)),
++ dump_register(DEPCMDPAR1(19)),
++ dump_register(DEPCMDPAR1(20)),
++ dump_register(DEPCMDPAR1(21)),
++ dump_register(DEPCMDPAR1(22)),
++ dump_register(DEPCMDPAR1(23)),
++ dump_register(DEPCMDPAR1(24)),
++ dump_register(DEPCMDPAR1(25)),
++ dump_register(DEPCMDPAR1(26)),
++ dump_register(DEPCMDPAR1(27)),
++ dump_register(DEPCMDPAR1(28)),
++ dump_register(DEPCMDPAR1(29)),
++ dump_register(DEPCMDPAR1(30)),
++ dump_register(DEPCMDPAR1(31)),
++
++ dump_register(DEPCMDPAR0(0)),
++ dump_register(DEPCMDPAR0(1)),
++ dump_register(DEPCMDPAR0(2)),
++ dump_register(DEPCMDPAR0(3)),
++ dump_register(DEPCMDPAR0(4)),
++ dump_register(DEPCMDPAR0(5)),
++ dump_register(DEPCMDPAR0(6)),
++ dump_register(DEPCMDPAR0(7)),
++ dump_register(DEPCMDPAR0(8)),
++ dump_register(DEPCMDPAR0(9)),
++ dump_register(DEPCMDPAR0(10)),
++ dump_register(DEPCMDPAR0(11)),
++ dump_register(DEPCMDPAR0(12)),
++ dump_register(DEPCMDPAR0(13)),
++ dump_register(DEPCMDPAR0(14)),
++ dump_register(DEPCMDPAR0(15)),
++ dump_register(DEPCMDPAR0(16)),
++ dump_register(DEPCMDPAR0(17)),
++ dump_register(DEPCMDPAR0(18)),
++ dump_register(DEPCMDPAR0(19)),
++ dump_register(DEPCMDPAR0(20)),
++ dump_register(DEPCMDPAR0(21)),
++ dump_register(DEPCMDPAR0(22)),
++ dump_register(DEPCMDPAR0(23)),
++ dump_register(DEPCMDPAR0(24)),
++ dump_register(DEPCMDPAR0(25)),
++ dump_register(DEPCMDPAR0(26)),
++ dump_register(DEPCMDPAR0(27)),
++ dump_register(DEPCMDPAR0(28)),
++ dump_register(DEPCMDPAR0(29)),
++ dump_register(DEPCMDPAR0(30)),
++ dump_register(DEPCMDPAR0(31)),
++
++ dump_register(DEPCMD(0)),
++ dump_register(DEPCMD(1)),
++ dump_register(DEPCMD(2)),
++ dump_register(DEPCMD(3)),
++ dump_register(DEPCMD(4)),
++ dump_register(DEPCMD(5)),
++ dump_register(DEPCMD(6)),
++ dump_register(DEPCMD(7)),
++ dump_register(DEPCMD(8)),
++ dump_register(DEPCMD(9)),
++ dump_register(DEPCMD(10)),
++ dump_register(DEPCMD(11)),
++ dump_register(DEPCMD(12)),
++ dump_register(DEPCMD(13)),
++ dump_register(DEPCMD(14)),
++ dump_register(DEPCMD(15)),
++ dump_register(DEPCMD(16)),
++ dump_register(DEPCMD(17)),
++ dump_register(DEPCMD(18)),
++ dump_register(DEPCMD(19)),
++ dump_register(DEPCMD(20)),
++ dump_register(DEPCMD(21)),
++ dump_register(DEPCMD(22)),
++ dump_register(DEPCMD(23)),
++ dump_register(DEPCMD(24)),
++ dump_register(DEPCMD(25)),
++ dump_register(DEPCMD(26)),
++ dump_register(DEPCMD(27)),
++ dump_register(DEPCMD(28)),
++ dump_register(DEPCMD(29)),
++ dump_register(DEPCMD(30)),
++ dump_register(DEPCMD(31)),
++
++ dump_register(OCFG),
++ dump_register(OCTL),
++ dump_register(OEVTEN),
++ dump_register(OSTS),
++};
++
++static int dwc3_regdump_show(struct seq_file *s, void *unused)
++{
++ struct dwc3 *dwc = s->private;
++ int i;
++
++ seq_printf(s, "DesignWare USB3 Core Register Dump\n");
++
++ for (i = 0; i < ARRAY_SIZE(dwc3_regs); i++) {
++ seq_printf(s, "%-20s : %08x\n", dwc3_regs[i].name,
++ dwc3_readl(dwc->regs, dwc3_regs[i].offset));
++ }
++
++ return 0;
++}
++
++static int dwc3_regdump_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, dwc3_regdump_show, inode->i_private);
++}
++
++static const struct file_operations dwc3_regdump_fops = {
++ .open = dwc3_regdump_open,
++ .read = seq_read,
++ .release = single_release,
++};
++
++static int dwc3_mode_show(struct seq_file *s, void *unused)
++{
++ struct dwc3 *dwc = s->private;
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&dwc->lock, flags);
++ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ switch (DWC3_GCTL_PRTCAP(reg)) {
++ case DWC3_GCTL_PRTCAP_HOST:
++ seq_printf(s, "host\n");
++ break;
++ case DWC3_GCTL_PRTCAP_DEVICE:
++ seq_printf(s, "device\n");
++ break;
++ case DWC3_GCTL_PRTCAP_OTG:
++ seq_printf(s, "OTG\n");
++ break;
++ default:
++ seq_printf(s, "UNKNOWN %08x\n", DWC3_GCTL_PRTCAP(reg));
++ }
++
++ return 0;
++}
++
++static int dwc3_mode_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, dwc3_mode_show, inode->i_private);
++}
++
++static ssize_t dwc3_mode_write(struct file *file,
++ const char __user *ubuf, size_t count, loff_t *ppos)
++{
++ struct seq_file *s = file->private_data;
++ struct dwc3 *dwc = s->private;
++ unsigned long flags;
++ u32 mode = 0;
++ char buf[32];
++
++ if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
++ return -EFAULT;
++
++ if (!strncmp(buf, "host", 4))
++ mode |= DWC3_GCTL_PRTCAP_HOST;
++
++ if (!strncmp(buf, "device", 6))
++ mode |= DWC3_GCTL_PRTCAP_DEVICE;
++
++ if (!strncmp(buf, "otg", 3))
++ mode |= DWC3_GCTL_PRTCAP_OTG;
++
++ if (mode) {
++ spin_lock_irqsave(&dwc->lock, flags);
++ dwc3_set_mode(dwc, mode);
++ spin_unlock_irqrestore(&dwc->lock, flags);
++ }
++ return count;
++}
++
++static const struct file_operations dwc3_mode_fops = {
++ .open = dwc3_mode_open,
++ .write = dwc3_mode_write,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++int __devinit dwc3_debugfs_init(struct dwc3 *dwc)
++{
++ struct dentry *root;
++ struct dentry *file;
++ int ret;
++
++ root = debugfs_create_dir(dev_name(dwc->dev), NULL);
++ if (IS_ERR(root)) {
++ ret = PTR_ERR(root);
++ goto err0;
++ }
++
++ dwc->root = root;
++
++ file = debugfs_create_file("regdump", S_IRUGO, root, dwc,
++ &dwc3_regdump_fops);
++ if (IS_ERR(file)) {
++ ret = PTR_ERR(file);
++ goto err1;
++ }
++
++ file = debugfs_create_file("mode", S_IRUGO | S_IWUSR, root,
++ dwc, &dwc3_mode_fops);
++ if (IS_ERR(file)) {
++ ret = PTR_ERR(file);
++ goto err1;
++ }
++
++ return 0;
++
++err1:
++ debugfs_remove_recursive(root);
++
++err0:
++ return ret;
++}
++
++void __devexit dwc3_debugfs_exit(struct dwc3 *dwc)
++{
++ debugfs_remove_recursive(dwc->root);
++ dwc->root = NULL;
++}
++#endif
+diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
+new file mode 100644
+index 0000000..11307c2
+--- /dev/null
++++ b/drivers/usb/dwc3/dwc3-omap.c
+@@ -0,0 +1,418 @@
++/**
++ * dwc3-omap.c - OMAP Specific Glue layer
++ *
++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Authors: Felipe Balbi ,
++ * Sebastian Andrzej Siewior
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include
++#ifdef CONFIG_DWC3_off
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include "core.h"
++#include "io.h"
++
++/*
++ * All these registers belong to OMAP's Wrapper around the
++ * DesignWare USB3 Core.
++ */
++
++#define USBOTGSS_REVISION 0x0000
++#define USBOTGSS_SYSCONFIG 0x0010
++#define USBOTGSS_IRQ_EOI 0x0020
++#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
++#define USBOTGSS_IRQSTATUS_0 0x0028
++#define USBOTGSS_IRQENABLE_SET_0 0x002c
++#define USBOTGSS_IRQENABLE_CLR_0 0x0030
++#define USBOTGSS_IRQSTATUS_RAW_1 0x0034
++#define USBOTGSS_IRQSTATUS_1 0x0038
++#define USBOTGSS_IRQENABLE_SET_1 0x003c
++#define USBOTGSS_IRQENABLE_CLR_1 0x0040
++#define USBOTGSS_UTMI_OTG_CTRL 0x0080
++#define USBOTGSS_UTMI_OTG_STATUS 0x0084
++#define USBOTGSS_MMRAM_OFFSET 0x0100
++#define USBOTGSS_FLADJ 0x0104
++#define USBOTGSS_DEBUG_CFG 0x0108
++#define USBOTGSS_DEBUG_DATA 0x010c
++
++/* SYSCONFIG REGISTER */
++#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
++#define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4)
++
++#define USBOTGSS_STANDBYMODE_FORCE_STANDBY 0
++#define USBOTGSS_STANDBYMODE_NO_STANDBY 1
++#define USBOTGSS_STANDBYMODE_SMART_STANDBY 2
++#define USBOTGSS_STANDBYMODE_SMART_WAKEUP 3
++
++#define USBOTGSS_STANDBYMODE_MASK (0x03 << 4)
++
++#define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2)
++
++#define USBOTGSS_IDLEMODE_FORCE_IDLE 0
++#define USBOTGSS_IDLEMODE_NO_IDLE 1
++#define USBOTGSS_IDLEMODE_SMART_IDLE 2
++#define USBOTGSS_IDLEMODE_SMART_WAKEUP 3
++
++#define USBOTGSS_IDLEMODE_MASK (0x03 << 2)
++
++/* IRQ_EOI REGISTER */
++#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
++
++/* IRQS0 BITS */
++#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
++
++/* IRQ1 BITS */
++#define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
++#define USBOTGSS_IRQ1_OEVT (1 << 16)
++#define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
++#define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
++#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
++#define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
++#define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
++#define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
++#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
++#define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
++
++/* UTMI_OTG_CTRL REGISTER */
++#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
++#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
++#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
++#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
++
++/* UTMI_OTG_STATUS REGISTER */
++#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
++#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
++#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
++#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
++#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
++#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
++#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
++
++struct dwc3_omap {
++ /* device lock */
++ spinlock_t lock;
++
++ struct platform_device *dwc3;
++ struct device *dev;
++
++ int irq;
++ void __iomem *base;
++
++ void *context;
++ u32 resource_size;
++
++ u32 dma_status:1;
++};
++
++static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
++{
++ struct dwc3_omap *omap = _omap;
++ u32 reg;
++
++ spin_lock(&omap->lock);
++
++ reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1);
++
++ if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
++ dev_dbg(omap->dev, "DMA Disable was Cleared\n");
++ omap->dma_status = false;
++ }
++
++ if (reg & USBOTGSS_IRQ1_OEVT)
++ dev_dbg(omap->dev, "OTG Event\n");
++
++ if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
++ dev_dbg(omap->dev, "DRVVBUS Rise\n");
++
++ if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
++ dev_dbg(omap->dev, "CHRGVBUS Rise\n");
++
++ if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
++ dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
++
++ if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
++ dev_dbg(omap->dev, "IDPULLUP Rise\n");
++
++ if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
++ dev_dbg(omap->dev, "DRVVBUS Fall\n");
++
++ if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
++ dev_dbg(omap->dev, "CHRGVBUS Fall\n");
++
++ if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
++ dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
++
++ if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
++ dev_dbg(omap->dev, "IDPULLUP Fall\n");
++
++ dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
++
++ reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_0);
++ dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
++
++ spin_unlock(&omap->lock);
++
++ return IRQ_HANDLED;
++}
++
++static int __devinit dwc3_omap_probe(struct platform_device *pdev)
++{
++ struct dwc3_omap_data *pdata = pdev->dev.platform_data;
++ struct platform_device *dwc3;
++ struct dwc3_omap *omap;
++ struct resource *res;
++
++ int devid;
++ int ret = -ENOMEM;
++ int irq;
++
++ u32 reg;
++
++ void __iomem *base;
++ void *context;
++
++ omap = kzalloc(sizeof(*omap), GFP_KERNEL);
++ if (!omap) {
++ dev_err(&pdev->dev, "not enough memory\n");
++ goto err0;
++ }
++
++ platform_set_drvdata(pdev, omap);
++
++ irq = platform_get_irq(pdev, 1);
++ if (irq < 0) {
++ dev_err(&pdev->dev, "missing IRQ resource\n");
++ ret = -EINVAL;
++ goto err1;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ if (!res) {
++ dev_err(&pdev->dev, "missing memory base resource\n");
++ ret = -EINVAL;
++ goto err1;
++ }
++
++ base = ioremap_nocache(res->start, resource_size(res));
++ if (!base) {
++ dev_err(&pdev->dev, "ioremap failed\n");
++ goto err1;
++ }
++
++ devid = dwc3_get_device_id();
++ if (devid < 0)
++ goto err2;
++
++ dwc3 = platform_device_alloc("dwc3", devid);
++ if (!dwc3) {
++ dev_err(&pdev->dev, "couldn't allocate dwc3 device\n");
++ goto err3;
++ }
++
++ context = kzalloc(resource_size(res), GFP_KERNEL);
++ if (!context) {
++ dev_err(&pdev->dev, "couldn't allocate dwc3 context memory\n");
++ goto err4;
++ }
++
++ spin_lock_init(&omap->lock);
++ dma_set_coherent_mask(&dwc3->dev, pdev->dev.coherent_dma_mask);
++
++ dwc3->dev.parent = &pdev->dev;
++ dwc3->dev.dma_mask = pdev->dev.dma_mask;
++ dwc3->dev.dma_parms = pdev->dev.dma_parms;
++ omap->resource_size = resource_size(res);
++ omap->context = context;
++ omap->dev = &pdev->dev;
++ omap->irq = irq;
++ omap->base = base;
++ omap->dwc3 = dwc3;
++
++ reg = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
++
++ if (!pdata) {
++ dev_dbg(&pdev->dev, "missing platform data\n");
++ } else {
++ switch (pdata->utmi_mode) {
++ case DWC3_OMAP_UTMI_MODE_SW:
++ reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
++ break;
++ case DWC3_OMAP_UTMI_MODE_HW:
++ reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
++ break;
++ default:
++ dev_dbg(&pdev->dev, "UNKNOWN utmi mode %d\n",
++ pdata->utmi_mode);
++ }
++ }
++
++ dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
++
++ /* check the DMA Status */
++ reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG);
++ omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
++
++ /* Set No-Idle and No-Standby */
++ reg &= ~(USBOTGSS_STANDBYMODE_MASK
++ | USBOTGSS_IDLEMODE_MASK);
++
++ reg |= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY)
++ | USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE));
++
++ dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg);
++
++ ret = request_irq(omap->irq, dwc3_omap_interrupt, 0,
++ "dwc3-omap", omap);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request IRQ #%d --> %d\n",
++ omap->irq, ret);
++ goto err5;
++ }
++
++ /* enable all IRQs */
++ reg = USBOTGSS_IRQO_COREIRQ_ST;
++ dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
++
++ reg = (USBOTGSS_IRQ1_OEVT |
++ USBOTGSS_IRQ1_DRVVBUS_RISE |
++ USBOTGSS_IRQ1_CHRGVBUS_RISE |
++ USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
++ USBOTGSS_IRQ1_IDPULLUP_RISE |
++ USBOTGSS_IRQ1_DRVVBUS_FALL |
++ USBOTGSS_IRQ1_CHRGVBUS_FALL |
++ USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
++ USBOTGSS_IRQ1_IDPULLUP_FALL);
++
++ dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
++
++ ret = platform_device_add_resources(dwc3, pdev->resource,
++ pdev->num_resources);
++ if (ret) {
++ dev_err(&pdev->dev, "couldn't add resources to dwc3 device\n");
++ goto err6;
++ }
++
++ ret = platform_device_add(dwc3);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to register dwc3 device\n");
++ goto err6;
++ }
++
++ return 0;
++
++err6:
++ free_irq(omap->irq, omap);
++
++err5:
++ kfree(omap->context);
++
++err4:
++ platform_device_put(dwc3);
++
++err3:
++ dwc3_put_device_id(devid);
++
++err2:
++ iounmap(base);
++
++err1:
++ kfree(omap);
++
++err0:
++ return ret;
++}
++
++static int __devexit dwc3_omap_remove(struct platform_device *pdev)
++{
++ struct dwc3_omap *omap = platform_get_drvdata(pdev);
++
++ platform_device_unregister(omap->dwc3);
++
++ dwc3_put_device_id(omap->dwc3->id);
++ free_irq(omap->irq, omap);
++ iounmap(omap->base);
++
++ kfree(omap->context);
++ kfree(omap);
++
++ return 0;
++}
++
++static const struct of_device_id of_dwc3_match[] = {
++ {
++ "ti,omap5430-dwc3"
++ },
++ {
++ "ti,omap5-dwc3"
++ },
++ { },
++};
++MODULE_DEVICE_TABLE(of, of_dwc3_match);
++
++static struct platform_driver dwc3_omap_driver = {
++ .probe = dwc3_omap_probe,
++ .remove = __devexit_p(dwc3_omap_remove),
++ .driver = {
++ .name = "omap-dwc3",
++ .of_match_table = of_dwc3_match,
++ },
++};
++
++MODULE_ALIAS("platform:omap-dwc3");
++MODULE_AUTHOR("Felipe Balbi ");
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
++
++static int __init dwc3_omap_init(void)
++{
++ return platform_driver_register(&dwc3_omap_driver);
++}
++module_init(dwc3_omap_init);
++
++static void __exit dwc3_omap_exit(void)
++{
++ platform_driver_unregister(&dwc3_omap_driver);
++}
++module_exit(dwc3_omap_exit);
++#endif
+diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
+new file mode 100644
+index 0000000..dda702c
+--- /dev/null
++++ b/drivers/usb/dwc3/dwc3-pci.c
+@@ -0,0 +1,187 @@
++/**
++ * dwc3-pci.c - PCI Specific glue layer
++ *
++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Authors: Felipe Balbi ,
++ * Sebastian Andrzej Siewior
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include
++#ifdef CONFIG_DWC3_off
++#include
++#include
++#include
++#include
++#include
++
++#include "core.h"
++
++/* FIXME define these in */
++#define PCI_VENDOR_ID_SYNOPSYS 0x16c3
++#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
++
++struct dwc3_pci {
++ struct device *dev;
++ struct platform_device *dwc3;
++};
++
++static int __devinit dwc3_pci_probe(struct pci_dev *pci,
++ const struct pci_device_id *id)
++{
++ struct resource res[2];
++ struct platform_device *dwc3;
++ struct dwc3_pci *glue;
++ int ret = -ENOMEM;
++ int devid;
++
++ glue = kzalloc(sizeof(*glue), GFP_KERNEL);
++ if (!glue) {
++ dev_err(&pci->dev, "not enough memory\n");
++ goto err0;
++ }
++
++ glue->dev = &pci->dev;
++
++ ret = pci_enable_device(pci);
++ if (ret) {
++ dev_err(&pci->dev, "failed to enable pci device\n");
++ goto err1;
++ }
++
++ pci_set_power_state(pci, PCI_D0);
++ pci_set_master(pci);
++
++ devid = dwc3_get_device_id();
++ if (devid < 0)
++ goto err2;
++
++ dwc3 = platform_device_alloc("dwc3", devid);
++ if (!dwc3) {
++ dev_err(&pci->dev, "couldn't allocate dwc3 device\n");
++ goto err3;
++ }
++
++ memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
++
++ res[0].start = pci_resource_start(pci, 0);
++ res[0].end = pci_resource_end(pci, 0);
++ res[0].name = "dwc_usb3";
++ res[0].flags = IORESOURCE_MEM;
++
++ res[1].start = pci->irq;
++ res[1].name = "dwc_usb3";
++ res[1].flags = IORESOURCE_IRQ;
++
++ ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
++ if (ret) {
++ dev_err(&pci->dev, "couldn't add resources to dwc3 device\n");
++ goto err4;
++ }
++
++ pci_set_drvdata(pci, glue);
++
++ dma_set_coherent_mask(&dwc3->dev, pci->dev.coherent_dma_mask);
++
++ dwc3->dev.dma_mask = pci->dev.dma_mask;
++ dwc3->dev.dma_parms = pci->dev.dma_parms;
++ dwc3->dev.parent = &pci->dev;
++ glue->dwc3 = dwc3;
++
++ ret = platform_device_add(dwc3);
++ if (ret) {
++ dev_err(&pci->dev, "failed to register dwc3 device\n");
++ goto err4;
++ }
++
++ return 0;
++
++err4:
++ pci_set_drvdata(pci, NULL);
++ platform_device_put(dwc3);
++
++err3:
++ dwc3_put_device_id(devid);
++
++err2:
++ pci_disable_device(pci);
++
++err1:
++ kfree(pci);
++
++err0:
++ return ret;
++}
++
++static void __devexit dwc3_pci_remove(struct pci_dev *pci)
++{
++ struct dwc3_pci *glue = pci_get_drvdata(pci);
++
++ dwc3_put_device_id(glue->dwc3->id);
++ platform_device_unregister(glue->dwc3);
++ pci_set_drvdata(pci, NULL);
++ pci_disable_device(pci);
++ kfree(glue);
++}
++
++static DEFINE_PCI_DEVICE_TABLE(dwc3_pci_id_table) = {
++ {
++ PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
++ PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
++ },
++ { } /* Terminating Entry */
++};
++MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
++
++static struct pci_driver dwc3_pci_driver = {
++ .name = "dwc3-pci",
++ .id_table = dwc3_pci_id_table,
++ .probe = dwc3_pci_probe,
++ .remove = __devexit_p(dwc3_pci_remove),
++};
++
++MODULE_AUTHOR("Felipe Balbi ");
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
++
++static int __init dwc3_pci_init(void)
++{
++ return pci_register_driver(&dwc3_pci_driver);
++}
++module_init(dwc3_pci_init);
++
++static void __exit dwc3_pci_exit(void)
++{
++ pci_unregister_driver(&dwc3_pci_driver);
++}
++module_exit(dwc3_pci_exit);
++#endif
+diff --git a/drivers/usb/dwc3/dwc3_core.c b/drivers/usb/dwc3/dwc3_core.c
+new file mode 100644
+index 0000000..26b6ff7
+--- /dev/null
++++ b/drivers/usb/dwc3/dwc3_core.c
+@@ -0,0 +1,513 @@
++/**
++ * core.c - DesignWare USB3 DRD Controller Core file
++ *
++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Authors: Felipe Balbi ,
++ * Sebastian Andrzej Siewior
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include
++#include
++
++#include
++#include
++
++#include "core.h"
++#include "gadget.h"
++#include "io.h"
++
++#include "debug.h"
++
++static char *maximum_speed = "super";
++/* -------------------------------------------------------------------------- */
++
++#define DWC3_DEVS_POSSIBLE 32
++
++
++int dwc3_get_device_id(void)
++{
++ static int dwc3_devs;
++
++ return dwc3_devs++;
++}
++
++void dwc3_put_device_id(int id)
++{
++}
++
++void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
++{
++ u32 reg;
++
++ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
++ reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
++ reg |= DWC3_GCTL_PRTCAPDIR(mode);
++ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
++}
++
++/**
++ * dwc3_core_soft_reset - Issues core soft reset and PHY reset
++ * @dwc: pointer to our context structure
++ */
++static void dwc3_core_soft_reset(struct dwc3 *dwc)
++{
++ u32 reg;
++
++ /* Before Resetting PHY, put Core in Reset */
++ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
++ reg |= DWC3_GCTL_CORESOFTRESET;
++ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
++
++ /* Assert USB3 PHY reset */
++ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
++ reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
++ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
++
++ /* Assert USB2 PHY reset */
++ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
++ reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
++ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
++
++ mdelay(100);
++
++ /* Clear USB3 PHY reset */
++ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
++ reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
++ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
++
++ /* Clear USB2 PHY reset */
++ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
++ reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
++ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
++
++ /* After PHYs are stable we can take Core out of reset state */
++ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
++ reg &= ~DWC3_GCTL_CORESOFTRESET;
++ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
++}
++
++/**
++ * dwc3_free_one_event_buffer - Frees one event buffer
++ * @dwc: Pointer to our controller context structure
++ * @evt: Pointer to event buffer to be freed
++ */
++static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
++ struct dwc3_event_buffer *evt)
++{
++ dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
++ kfree(evt);
++}
++
++/**
++ * dwc3_alloc_one_event_buffer - Allocated one event buffer structure
++ * @dwc: Pointer to our controller context structure
++ * @length: size of the event buffer
++ *
++ * Returns a pointer to the allocated event buffer structure on succes
++ * otherwise ERR_PTR(errno).
++ */
++static struct dwc3_event_buffer *__devinit
++dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
++{
++ struct dwc3_event_buffer *evt;
++
++ evt = kzalloc(sizeof(*evt), GFP_KERNEL);
++ if (!evt)
++ return ERR_PTR(-ENOMEM);
++
++ evt->dwc = dwc;
++ evt->length = length;
++ evt->buf = dma_alloc_coherent(dwc->dev, length,
++ &evt->dma, GFP_KERNEL);
++ if (!evt->buf) {
++ kfree(evt);
++ return ERR_PTR(-ENOMEM);
++ }
++
++ return evt;
++}
++
++/**
++ * dwc3_free_event_buffers - frees all allocated event buffers
++ * @dwc: Pointer to our controller context structure
++ */
++static void dwc3_free_event_buffers(struct dwc3 *dwc)
++{
++ struct dwc3_event_buffer *evt;
++ int i;
++
++ for (i = 0; i < dwc->num_event_buffers; i++) {
++ evt = dwc->ev_buffs[i];
++ if (evt) {
++ dwc3_free_one_event_buffer(dwc, evt);
++ dwc->ev_buffs[i] = NULL;
++ }
++ }
++}
++
++/**
++ * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
++ * @dwc: Pointer to out controller context structure
++ * @length: size of event buffer
++ *
++ * Returns 0 on success otherwise negative errno. In error the case, dwc
++ * may contain some buffers allocated but not all which were requested.
++ */
++static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
++{
++ int num;
++ int i;
++
++ num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
++ dwc->num_event_buffers = num;
++
++ dwc->ev_buffs = kzalloc(sizeof(*dwc->ev_buffs) * num, GFP_KERNEL);
++ if (!dwc->ev_buffs) {
++ dev_err(dwc->dev, "can't allocate event buffers array\n");
++ return -ENOMEM;
++ }
++
++ for (i = 0; i < num; i++) {
++ struct dwc3_event_buffer *evt;
++
++ evt = dwc3_alloc_one_event_buffer(dwc, length);
++ if (IS_ERR(evt)) {
++ dev_err(dwc->dev, "can't allocate event buffer\n");
++ return PTR_ERR(evt);
++ }
++ dwc->ev_buffs[i] = evt;
++ }
++
++ return 0;
++}
++
++/**
++ * dwc3_event_buffers_setup - setup our allocated event buffers
++ * @dwc: Pointer to out controller context structure
++ *
++ * Returns 0 on success otherwise negative errno.
++ */
++static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
++{
++ struct dwc3_event_buffer *evt;
++ int n;
++
++ for (n = 0; n < dwc->num_event_buffers; n++) {
++ evt = dwc->ev_buffs[n];
++ dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
++ evt->buf, (unsigned long long) evt->dma,
++ evt->length);
++
++ dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
++ lower_32_bits(evt->dma));
++ dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
++ upper_32_bits(evt->dma));
++ dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
++ evt->length & 0xffff);
++ dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
++ }
++
++ return 0;
++}
++
++static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
++{
++ struct dwc3_event_buffer *evt;
++ int n;
++
++ for (n = 0; n < dwc->num_event_buffers; n++) {
++ evt = dwc->ev_buffs[n];
++ dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
++ dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
++ dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
++ dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
++ }
++}
++
++static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
++{
++ struct dwc3_hwparams *parms = &dwc->hwparams;
++
++ parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
++ parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
++ parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
++ parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
++ parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
++ parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
++ parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
++ parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
++ parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
++}
++
++/**
++ * dwc3_core_init - Low-level initialization of DWC3 Core
++ * @dwc: Pointer to our controller context structure
++ *
++ * Returns 0 on success otherwise negative errno.
++ */
++static int __devinit dwc3_core_init(struct dwc3 *dwc)
++{
++ unsigned long timeout;
++ u32 reg;
++ int ret;
++
++ reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
++ /* This should read as U3 followed by revision number */
++ if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
++ dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
++ ret = -ENODEV;
++ goto err0;
++ }
++ dwc->revision = reg & DWC3_GSNPSREV_MASK;
++
++ dwc3_core_soft_reset(dwc);
++
++ /* issue device SoftReset too */
++ timeout = 500;
++ dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
++ do {
++ reg = dwc3_readl(dwc->regs, DWC3_DCTL);
++ if (!(reg & DWC3_DCTL_CSFTRST))
++ break;
++
++ mdelay(1);
++ timeout--;
++ if (!timeout) {
++ dev_err(dwc->dev, "Reset Timed Out\n");
++ ret = -ETIMEDOUT;
++ goto err0;
++ }
++
++ cpu_relax();
++ } while (true);
++
++ dwc3_cache_hwparams(dwc);
++
++ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
++ reg &= ~DWC3_GCTL_SCALEDOWN(3);
++ reg &= ~DWC3_GCTL_DISSCRAMBLE;
++
++ switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
++ case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
++ reg &= ~DWC3_GCTL_DSBLCLKGTNG;
++ break;
++ default:
++ dev_dbg(dwc->dev, "No power optimization available\n");
++ }
++
++ /*
++ * WORKAROUND: DWC3 revisions <1.90a have a bug
++ * when The device fails to connect at SuperSpeed
++ * and falls back to high-speed mode which causes
++ * the device to enter in a Connect/Disconnect loop
++ */
++ if (dwc->revision < DWC3_REVISION_190A)
++ reg |= DWC3_GCTL_U2RSTECN;
++
++ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
++
++ ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
++ if (ret) {
++ dev_err(dwc->dev, "failed to allocate event buffers\n");
++ ret = -ENOMEM;
++ goto err1;
++ }
++
++ ret = dwc3_event_buffers_setup(dwc);
++ if (ret) {
++ dev_err(dwc->dev, "failed to setup event buffers\n");
++ goto err1;
++ }
++
++ return 0;
++
++err1:
++ dwc3_free_event_buffers(dwc);
++
++err0:
++ return ret;
++}
++
++static void dwc3_core_exit(struct dwc3 *dwc)
++{
++ dwc3_event_buffers_cleanup(dwc);
++ dwc3_free_event_buffers(dwc);
++}
++
++#define DWC3_ALIGN_MASK (16 - 1)
++
++struct dwc3 *global_dwc3;
++
++int __devinit dwc3_probe(struct platform_device *pdev)
++{
++ struct dwc3 *dwc;
++
++ int ret = -ENOMEM;
++
++ void __iomem *regs;
++ void *mem;
++
++ u8 mode;
++
++ mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
++ if (!mem) {
++ dev_err(&pdev->dev, "not enough memory\n");
++ goto err0;
++ }
++ dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
++ dwc->mem = mem;
++ global_dwc3 = dwc;
++
++ dwc->regs = CONFIG_USB_DWC3_UDC_REGS;
++ dwc->regs_size = DWC3_USB_REGS_SIZE;
++ dwc->dev = &pdev->dev;
++ dwc->irq = 0;
++
++ if (!strncmp("super", maximum_speed, 5))
++ dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
++ else if (!strncmp("high", maximum_speed, 4))
++ dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
++ else if (!strncmp("full", maximum_speed, 4))
++ dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
++ else if (!strncmp("low", maximum_speed, 3))
++ dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
++ else
++ dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
++
++ pm_runtime_enable(&pdev->dev);
++ pm_runtime_get_sync(&pdev->dev);
++ pm_runtime_forbid(&pdev->dev);
++
++ ret = dwc3_core_init(dwc);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to initialize core\n");
++ goto err3;
++ }
++
++ mode = DWC3_MODE_DEVICE /*DWC3_MODE(dwc->hwparams.hwparams0)*/;
++
++ switch (mode) {
++ case DWC3_MODE_DEVICE:
++ dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
++ ret = dwc3_gadget_init(dwc);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to initialize gadget\n");
++ goto err4;
++ }
++ break;
++ case DWC3_MODE_HOST:
++ dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
++ ret = dwc3_host_init(dwc);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to initialize host\n");
++ goto err4;
++ }
++ break;
++ case DWC3_MODE_DRD:
++ dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
++ ret = dwc3_host_init(dwc);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to initialize host\n");
++ goto err4;
++ }
++
++ ret = dwc3_gadget_init(dwc);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to initialize gadget\n");
++ goto err4;
++ }
++ break;
++ default:
++ dev_err(&pdev->dev, "Unsupported mode of operation %d\n", mode);
++ goto err4;
++ }
++ dwc->mode = mode;
++
++ pm_runtime_allow(&pdev->dev);
++
++ return 0;
++err4:
++ dwc3_core_exit(dwc);
++
++err3:
++ iounmap(regs);
++ kfree(dwc->mem);
++err0:
++ return ret;
++}
++
++int __devexit dwc3_remove(struct platform_device *pdev)
++{
++ struct dwc3 *dwc = global_dwc3;
++
++ dwc3_debugfs_exit(dwc);
++
++ switch (dwc->mode) {
++ case DWC3_MODE_DEVICE:
++ dwc3_gadget_exit(dwc);
++ break;
++ case DWC3_MODE_HOST:
++ dwc3_host_exit(dwc);
++ break;
++ case DWC3_MODE_DRD:
++ dwc3_host_exit(dwc);
++ dwc3_gadget_exit(dwc);
++ break;
++ default:
++ /* do nothing */
++ break;
++ }
++
++ dwc3_core_exit(dwc);
++ iounmap(dwc->regs);
++ kfree(dwc->mem);
++
++ return 0;
++}
++
++int usb_gadget_init_udc(void)
++{
++ return dwc3_probe(NULL);
++}
++void usb_gadget_exit_udc(void)
++{
++ dwc3_remove(NULL);
++}
++
++irqreturn_t dwc3_interrupt(int irq, void *_dwc);
++int usb_gadget_handle_interrupts(void)
++{
++ dwc3_interrupt(0, global_dwc3);
++ WATCHDOG_RESET();
++ return 0;
++}
+diff --git a/drivers/usb/dwc3/dwc3_ep0.c b/drivers/usb/dwc3/dwc3_ep0.c
+new file mode 100644
+index 0000000..2e0d466
+--- /dev/null
++++ b/drivers/usb/dwc3/dwc3_ep0.c
+@@ -0,0 +1,851 @@
++/**
++ * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
++ *
++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Authors: Felipe Balbi ,
++ * Sebastian Andrzej Siewior
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include
++
++#include
++#include
++/* #include */
++
++#include "core.h"
++#include "gadget.h"
++#include "io.h"
++
++static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum);
++
++static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
++{
++ switch (state) {
++ case EP0_UNCONNECTED:
++ return "Unconnected";
++ case EP0_SETUP_PHASE:
++ return "Setup Phase";
++ case EP0_DATA_PHASE:
++ return "Data Phase";
++ case EP0_STATUS_PHASE:
++ return "Status Phase";
++ default:
++ return "UNKNOWN";
++ }
++}
++
++static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
++ u32 len, u32 type)
++{
++ struct dwc3_gadget_ep_cmd_params params;
++ struct dwc3_trb_hw *trb_hw;
++ struct dwc3_trb trb;
++ struct dwc3_ep *dep;
++
++ int ret;
++
++ dep = dwc->eps[epnum];
++ if (dep->flags & DWC3_EP_BUSY) {
++ dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
++ return 0;
++ }
++
++ trb_hw = dwc->ep0_trb;
++ memset(&trb, 0, sizeof(trb));
++
++ trb.trbctl = type;
++ trb.bplh = buf_dma;
++ trb.length = len;
++
++ trb.hwo = 1;
++ trb.lst = 1;
++ trb.ioc = 1;
++ trb.isp_imi = 1;
++
++ dwc3_trb_to_hw(&trb, trb_hw);
++
++ memset(¶ms, 0, sizeof(params));
++ params.param0 = upper_32_bits(dwc->ep0_trb_addr);
++ params.param1 = lower_32_bits(dwc->ep0_trb_addr);
++
++ ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
++ DWC3_DEPCMD_STARTTRANSFER, ¶ms);
++ if (ret < 0) {
++ dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
++ return ret;
++ }
++
++ dep->flags |= DWC3_EP_BUSY;
++ dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
++ dep->number);
++
++ dwc->ep0_next_event = DWC3_EP0_COMPLETE;
++
++ return 0;
++}
++
++static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
++ struct dwc3_request *req)
++{
++ struct dwc3 *dwc = dep->dwc;
++ u32 type;
++ int ret = 0;
++
++ req->request.actual = 0;
++ req->request.status = -EINPROGRESS;
++ req->epnum = dep->number;
++
++ list_add_tail(&req->list, &dep->request_list);
++
++ /*
++ * Gadget driver might not be quick enough to queue a request
++ * before we get a Transfer Not Ready event on this endpoint.
++ *
++ * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
++ * flag is set, it's telling us that as soon as Gadget queues the
++ * required request, we should kick the transfer here because the
++ * IRQ we were waiting for is long gone.
++ */
++ if (dep->flags & DWC3_EP_PENDING_REQUEST) {
++ unsigned direction;
++
++ direction = !!(dep->flags & DWC3_EP0_DIR_IN);
++
++ if (dwc->ep0state == EP0_STATUS_PHASE) {
++ type = dwc->three_stage_setup
++ ? DWC3_TRBCTL_CONTROL_STATUS3
++ : DWC3_TRBCTL_CONTROL_STATUS2;
++ } else if (dwc->ep0state == EP0_DATA_PHASE) {
++ type = DWC3_TRBCTL_CONTROL_DATA;
++ } else {
++ /* should never happen */
++ WARN_ON(1);
++ return 0;
++ }
++
++ ret = dwc3_ep0_start_trans(dwc, direction,
++ req->request.dma, req->request.length, type);
++ dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
++ DWC3_EP0_DIR_IN);
++
++ } else if (dwc->delayed_status && (dwc->ep0state == EP0_STATUS_PHASE)) {
++ dwc->delayed_status = false;
++ dwc3_ep0_do_control_status(dwc, 1);
++ }
++
++ return ret;
++}
++
++int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
++ gfp_t gfp_flags)
++{
++ struct dwc3_request *req = to_dwc3_request(request);
++ struct dwc3_ep *dep = to_dwc3_ep(ep);
++ struct dwc3 *dwc = dep->dwc;
++
++ unsigned long flags;
++
++ int ret;
++
++ spin_lock_irqsave(&dwc->lock, flags);
++ if (!dep->desc) {
++ dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
++ request, dep->name);
++ ret = -ESHUTDOWN;
++ goto out;
++ }
++
++ /* we share one TRB for ep0/1 */
++ if (!list_empty(&dep->request_list)) {
++ ret = -EBUSY;
++ goto out;
++ }
++
++ dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
++ request, dep->name, request->length,
++ dwc3_ep0_state_string(dwc->ep0state));
++
++ ret = __dwc3_gadget_ep0_queue(dep, req);
++
++out:
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ return ret;
++}
++
++static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
++{
++ struct dwc3_ep *dep = dwc->eps[0];
++
++ /* stall is always issued on EP0 */
++ __dwc3_gadget_ep_set_halt(dep, 1);
++ dep->flags = DWC3_EP_ENABLED;
++ dwc->delayed_status = false;
++
++ if (!list_empty(&dep->request_list)) {
++ struct dwc3_request *req;
++
++ req = next_request(&dep->request_list);
++ dwc3_gadget_giveback(dep, req, -ECONNRESET);
++ }
++
++ dwc->ep0state = EP0_SETUP_PHASE;
++ dwc3_ep0_out_start(dwc);
++}
++
++void dwc3_ep0_out_start(struct dwc3 *dwc)
++{
++ int ret;
++
++ ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
++ DWC3_TRBCTL_CONTROL_SETUP);
++ WARN_ON(ret < 0);
++}
++
++static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
++{
++ struct dwc3_ep *dep;
++ u32 windex = le16_to_cpu(wIndex_le);
++ u32 epnum;
++
++ epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
++ if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
++ epnum |= 1;
++
++ dep = dwc->eps[epnum];
++ if (dep->flags & DWC3_EP_ENABLED)
++ return dep;
++
++ return NULL;
++}
++
++static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
++{
++}
++/*
++ * ch 9.4.5
++ */
++static int dwc3_ep0_handle_status(struct dwc3 *dwc,
++ struct usb_ctrlrequest *ctrl)
++{
++ struct dwc3_ep *dep;
++ u32 recip;
++ u16 usb_status = 0;
++ __le16 *response_pkt;
++
++ recip = ctrl->bRequestType & USB_RECIP_MASK;
++ switch (recip) {
++ case USB_RECIP_DEVICE:
++ /*
++ * We are self-powered. U1/U2/LTM will be set later
++ * once we handle this states. RemoteWakeup is 0 on SS
++ */
++ usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
++ break;
++
++ case USB_RECIP_INTERFACE:
++ /*
++ * Function Remote Wake Capable D0
++ * Function Remote Wakeup D1
++ */
++ break;
++
++ case USB_RECIP_ENDPOINT:
++ dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
++ if (!dep)
++ return -EINVAL;
++
++ if (dep->flags & DWC3_EP_STALL)
++ usb_status = 1 << USB_ENDPOINT_HALT;
++ break;
++ default:
++ return -EINVAL;
++ };
++
++ response_pkt = (__le16 *) dwc->setup_buf;
++ *response_pkt = cpu_to_le16(usb_status);
++
++ dep = dwc->eps[0];
++ dwc->ep0_usb_req.dep = dep;
++ dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
++ dwc->ep0_usb_req.request.dma = dwc->setup_buf_addr;
++ dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
++
++ return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
++}
++
++static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
++ struct usb_ctrlrequest *ctrl, int set)
++{
++ struct dwc3_ep *dep;
++ u32 recip;
++ u32 wValue;
++ u32 wIndex;
++ u32 reg;
++ int ret;
++ u32 mode;
++
++ wValue = le16_to_cpu(ctrl->wValue);
++ wIndex = le16_to_cpu(ctrl->wIndex);
++ recip = ctrl->bRequestType & USB_RECIP_MASK;
++ switch (recip) {
++ case USB_RECIP_DEVICE:
++
++ /*
++ * 9.4.1 says only only for SS, in AddressState only for
++ * default control pipe
++ */
++ switch (wValue) {
++ case USB_DEVICE_U1_ENABLE:
++ case USB_DEVICE_U2_ENABLE:
++ case USB_DEVICE_LTM_ENABLE:
++ if (dwc->dev_state != DWC3_CONFIGURED_STATE)
++ return -EINVAL;
++ if (dwc->speed != DWC3_DSTS_SUPERSPEED)
++ return -EINVAL;
++ }
++
++ /* XXX add U[12] & LTM */
++ switch (wValue) {
++ case USB_DEVICE_REMOTE_WAKEUP:
++ break;
++ case USB_DEVICE_U1_ENABLE:
++ break;
++ case USB_DEVICE_U2_ENABLE:
++ break;
++ case USB_DEVICE_LTM_ENABLE:
++ break;
++
++ case USB_DEVICE_TEST_MODE:
++ if ((wIndex & 0xff) != 0)
++ return -EINVAL;
++ if (!set)
++ return -EINVAL;
++
++ mode = wIndex >> 8;
++ reg = dwc3_readl(dwc->regs, DWC3_DCTL);
++ reg &= ~DWC3_DCTL_TSTCTRL_MASK;
++
++ switch (mode) {
++ case TEST_J:
++ case TEST_K:
++ case TEST_SE0_NAK:
++ case TEST_PACKET:
++ case TEST_FORCE_EN:
++ reg |= mode << 1;
++ break;
++ default:
++ return -EINVAL;
++ }
++ dwc3_writel(dwc->regs, DWC3_DCTL, reg);
++ break;
++ default:
++ return -EINVAL;
++ }
++ break;
++
++ case USB_RECIP_INTERFACE:
++ switch (wValue) {
++ case USB_INTRF_FUNC_SUSPEND:
++ if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
++ /* XXX enable Low power suspend */
++ ;
++ if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
++ /* XXX enable remote wakeup */
++ ;
++ break;
++ default:
++ return -EINVAL;
++ }
++ break;
++
++ case USB_RECIP_ENDPOINT:
++ switch (wValue) {
++ case USB_ENDPOINT_HALT:
++ dep = dwc3_wIndex_to_dep(dwc, wIndex);
++ if (!dep)
++ return -EINVAL;
++ ret = __dwc3_gadget_ep_set_halt(dep, set);
++ if (ret)
++ return -EINVAL;
++ break;
++ default:
++ return -EINVAL;
++ }
++ break;
++
++ default:
++ return -EINVAL;
++ };
++
++ return 0;
++}
++
++static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
++{
++ u32 addr;
++ u32 reg;
++
++ addr = le16_to_cpu(ctrl->wValue);
++ if (addr > 127) {
++ dev_dbg(dwc->dev, "invalid device address %d\n", addr);
++ return -EINVAL;
++ }
++
++ if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
++ dev_dbg(dwc->dev, "trying to set address when configured\n");
++ return -EINVAL;
++ }
++
++ reg = dwc3_readl(dwc->regs, DWC3_DCFG);
++ reg &= ~(DWC3_DCFG_DEVADDR_MASK);
++ reg |= DWC3_DCFG_DEVADDR(addr);
++ dwc3_writel(dwc->regs, DWC3_DCFG, reg);
++
++ if (addr)
++ dwc->dev_state = DWC3_ADDRESS_STATE;
++ else
++ dwc->dev_state = DWC3_DEFAULT_STATE;
++
++ return 0;
++}
++
++static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
++{
++ int ret;
++
++ spin_unlock(&dwc->lock);
++ ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
++ spin_lock(&dwc->lock);
++ return ret;
++}
++
++static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
++{
++ u32 cfg;
++ int ret;
++
++ dwc->start_config_issued = false;
++ cfg = le16_to_cpu(ctrl->wValue);
++
++ switch (dwc->dev_state) {
++ case DWC3_DEFAULT_STATE:
++ return -EINVAL;
++ break;
++
++ case DWC3_ADDRESS_STATE:
++ ret = dwc3_ep0_delegate_req(dwc, ctrl);
++ /* if the cfg matches and the cfg is non zero */
++ if (!ret && cfg)
++ dwc->dev_state = DWC3_CONFIGURED_STATE;
++ break;
++
++ case DWC3_CONFIGURED_STATE:
++ ret = dwc3_ep0_delegate_req(dwc, ctrl);
++ if (!cfg)
++ dwc->dev_state = DWC3_ADDRESS_STATE;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
++static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
++{
++ int ret;
++
++ switch (ctrl->bRequest) {
++ case USB_REQ_GET_STATUS:
++ dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
++ ret = dwc3_ep0_handle_status(dwc, ctrl);
++ break;
++ case USB_REQ_CLEAR_FEATURE:
++ dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
++ ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
++ break;
++ case USB_REQ_SET_FEATURE:
++ dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
++ ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
++ break;
++ case USB_REQ_SET_ADDRESS:
++ dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
++ ret = dwc3_ep0_set_address(dwc, ctrl);
++ break;
++ case USB_REQ_SET_CONFIGURATION:
++ dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
++ ret = dwc3_ep0_set_config(dwc, ctrl);
++ break;
++ default:
++ dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
++ ret = dwc3_ep0_delegate_req(dwc, ctrl);
++ break;
++ };
++
++ return ret;
++}
++
++static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
++ const struct dwc3_event_depevt *event)
++{
++ struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
++ int ret;
++ u32 len;
++
++ if (!dwc->gadget_driver)
++ goto err;
++
++ len = le16_to_cpu(ctrl->wLength);
++ if (!len) {
++ dwc->three_stage_setup = false;
++ dwc->ep0_expect_in = false;
++ dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
++ } else {
++ dwc->three_stage_setup = true;
++ dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
++ dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
++ }
++
++ if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
++ ret = dwc3_ep0_std_request(dwc, ctrl);
++ else
++ ret = dwc3_ep0_delegate_req(dwc, ctrl);
++
++ if (ret == USB_GADGET_DELAYED_STATUS)
++ dwc->delayed_status = true;
++
++ if (ret >= 0)
++ return;
++
++err:
++ dwc3_ep0_stall_and_restart(dwc);
++}
++
++static void dwc3_ep0_complete_data(struct dwc3 *dwc,
++ const struct dwc3_event_depevt *event)
++{
++ struct dwc3_request *r = NULL;
++ struct usb_request *ur;
++ struct dwc3_trb trb;
++ struct dwc3_ep *ep0;
++ u32 transferred;
++ u8 epnum;
++
++ epnum = event->endpoint_number;
++ ep0 = dwc->eps[0];
++
++ dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
++
++ r = next_request(&ep0->request_list);
++ ur = &r->request;
++
++ dwc3_trb_to_nat(dwc->ep0_trb, &trb);
++
++ if (dwc->ep0_bounced) {
++
++ transferred = min_t(u32, ur->length,
++ ep0->endpoint.maxpacket - trb.length);
++ memcpy(ur->buf, dwc->ep0_bounce, transferred);
++ dwc->ep0_bounced = false;
++ } else {
++ transferred = ur->length - trb.length;
++ ur->actual += transferred;
++ }
++
++ if ((epnum & 1) && ur->actual < ur->length) {
++ /* for some reason we did not get everything out */
++
++ dwc3_ep0_stall_and_restart(dwc);
++ } else {
++ /*
++ * handle the case where we have to send a zero packet. This
++ * seems to be case when req.length > maxpacket. Could it be?
++ */
++ if (r)
++ dwc3_gadget_giveback(ep0, r, 0);
++ }
++}
++
++static void dwc3_ep0_complete_req(struct dwc3 *dwc,
++ const struct dwc3_event_depevt *event)
++{
++ struct dwc3_request *r;
++ struct dwc3_ep *dep;
++
++ dep = dwc->eps[0];
++
++ if (!list_empty(&dep->request_list)) {
++ r = next_request(&dep->request_list);
++
++ dwc3_gadget_giveback(dep, r, 0);
++ }
++
++ dwc->ep0state = EP0_SETUP_PHASE;
++ dwc3_ep0_out_start(dwc);
++}
++
++static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
++ const struct dwc3_event_depevt *event)
++{
++ struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
++
++ dep->flags &= ~DWC3_EP_BUSY;
++ dwc->setup_packet_pending = false;
++
++ switch (dwc->ep0state) {
++ case EP0_SETUP_PHASE:
++ dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
++ dwc3_ep0_inspect_setup(dwc, event);
++ break;
++
++ case EP0_DATA_PHASE:
++ dev_vdbg(dwc->dev, "Data Phase\n");
++ dwc3_ep0_complete_data(dwc, event);
++ break;
++
++ case EP0_STATUS_PHASE:
++ dev_vdbg(dwc->dev, "Status Phase\n");
++ dwc3_ep0_complete_req(dwc, event);
++ break;
++ default:
++ WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
++ }
++}
++
++static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
++ const struct dwc3_event_depevt *event)
++{
++ dwc3_ep0_out_start(dwc);
++}
++
++static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
++ const struct dwc3_event_depevt *event)
++{
++ struct dwc3_ep *dep;
++ struct dwc3_request *req;
++ int ret;
++
++ dep = dwc->eps[0];
++
++ if (list_empty(&dep->request_list)) {
++ dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
++ dep->flags |= DWC3_EP_PENDING_REQUEST;
++
++ if (event->endpoint_number)
++ dep->flags |= DWC3_EP0_DIR_IN;
++ return;
++ }
++
++ req = next_request(&dep->request_list);
++ req->direction = !!event->endpoint_number;
++
++ if (req->request.length == 0) {
++ ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
++ dwc->ctrl_req_addr, 0,
++ DWC3_TRBCTL_CONTROL_DATA);
++ } else if ((req->request.length % dep->endpoint.maxpacket)
++ && (event->endpoint_number == 0)) {
++ dwc3_map_buffer_to_dma(req);
++
++ WARN_ON(req->request.length > dep->endpoint.maxpacket);
++
++ dwc->ep0_bounced = true;
++
++ /*
++ * REVISIT in case request length is bigger than EP0
++ * wMaxPacketSize, we will need two chained TRBs to handle
++ * the transfer.
++ */
++ ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
++ dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
++ DWC3_TRBCTL_CONTROL_DATA);
++ } else {
++ dwc3_map_buffer_to_dma(req);
++
++ ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
++ req->request.dma, req->request.length,
++ DWC3_TRBCTL_CONTROL_DATA);
++ }
++
++ WARN_ON(ret < 0);
++}
++
++static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
++{
++ struct dwc3 *dwc = dep->dwc;
++ u32 type;
++
++ type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
++ : DWC3_TRBCTL_CONTROL_STATUS2;
++
++ return dwc3_ep0_start_trans(dwc, dep->number,
++ dwc->ctrl_req_addr, 0, type);
++}
++
++static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum)
++{
++ struct dwc3_ep *dep = dwc->eps[epnum];
++
++ WARN_ON(dwc3_ep0_start_control_status(dep));
++}
++
++static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
++ const struct dwc3_event_depevt *event)
++{
++ dwc->setup_packet_pending = true;
++
++ /*
++ * This part is very tricky: If we has just handled
++ * XferNotReady(Setup) and we're now expecting a
++ * XferComplete but, instead, we receive another
++ * XferNotReady(Setup), we should STALL and restart
++ * the state machine.
++ *
++ * In all other cases, we just continue waiting
++ * for the XferComplete event.
++ *
++ * We are a little bit unsafe here because we're
++ * not trying to ensure that last event was, indeed,
++ * XferNotReady(Setup).
++ *
++ * Still, we don't expect any condition where that
++ * should happen and, even if it does, it would be
++ * another error condition.
++ */
++ if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) {
++ switch (event->status) {
++ case DEPEVT_STATUS_CONTROL_SETUP:
++ dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n");
++ dwc3_ep0_stall_and_restart(dwc);
++ break;
++ case DEPEVT_STATUS_CONTROL_DATA:
++ /* FALLTHROUGH */
++ case DEPEVT_STATUS_CONTROL_STATUS:
++ /* FALLTHROUGH */
++ default:
++ dev_vdbg(dwc->dev, "waiting for XferComplete\n");
++ }
++
++ return;
++ }
++
++ switch (event->status) {
++ case DEPEVT_STATUS_CONTROL_SETUP:
++ dev_vdbg(dwc->dev, "Control Setup\n");
++
++ dwc->ep0state = EP0_SETUP_PHASE;
++
++ dwc3_ep0_do_control_setup(dwc, event);
++ break;
++
++ case DEPEVT_STATUS_CONTROL_DATA:
++ dev_vdbg(dwc->dev, "Control Data\n");
++
++ dwc->ep0state = EP0_DATA_PHASE;
++
++ if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
++ dev_vdbg(dwc->dev, "Expected %d got %d\n",
++ dwc->ep0_next_event,
++ DWC3_EP0_NRDY_DATA);
++
++ dwc3_ep0_stall_and_restart(dwc);
++ return;
++ }
++
++ /*
++ * One of the possible error cases is when Host _does_
++ * request for Data Phase, but it does so on the wrong
++ * direction.
++ *
++ * Here, we already know ep0_next_event is DATA (see above),
++ * so we only need to check for direction.
++ */
++ if (dwc->ep0_expect_in != event->endpoint_number) {
++ dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
++ dwc3_ep0_stall_and_restart(dwc);
++ return;
++ }
++
++ dwc3_ep0_do_control_data(dwc, event);
++ break;
++
++ case DEPEVT_STATUS_CONTROL_STATUS:
++ dev_vdbg(dwc->dev, "Control Status\n");
++
++ dwc->ep0state = EP0_STATUS_PHASE;
++
++ if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
++ dev_vdbg(dwc->dev, "Expected %d got %d\n",
++ dwc->ep0_next_event,
++ DWC3_EP0_NRDY_STATUS);
++
++ dwc3_ep0_stall_and_restart(dwc);
++ return;
++ }
++
++ if (dwc->delayed_status) {
++ WARN_ON_ONCE(event->endpoint_number != 1);
++ dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
++ return;
++ }
++
++ dwc3_ep0_do_control_status(dwc, event->endpoint_number);
++ }
++}
++
++void dwc3_ep0_interrupt(struct dwc3 *dwc,
++ const struct dwc3_event_depevt *event)
++{
++ u8 epnum = event->endpoint_number;
++
++ dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
++ dwc3_ep_event_string(event->endpoint_event),
++ epnum >> 1, (epnum & 1) ? "in" : "out",
++ dwc3_ep0_state_string(dwc->ep0state));
++
++ switch (event->endpoint_event) {
++ case DWC3_DEPEVT_XFERCOMPLETE:
++ dwc3_ep0_xfer_complete(dwc, event);
++ break;
++
++ case DWC3_DEPEVT_XFERNOTREADY:
++ dwc3_ep0_xfernotready(dwc, event);
++ break;
++
++ case DWC3_DEPEVT_XFERINPROGRESS:
++ case DWC3_DEPEVT_RXTXFIFOEVT:
++ case DWC3_DEPEVT_STREAMEVT:
++ case DWC3_DEPEVT_EPCMDCMPLT:
++ break;
++ }
++}
+diff --git a/drivers/usb/dwc3/dwc3_gadget.c b/drivers/usb/dwc3/dwc3_gadget.c
+new file mode 100644
+index 0000000..7c1a479
+--- /dev/null
++++ b/drivers/usb/dwc3/dwc3_gadget.c
+@@ -0,0 +1,2184 @@
++/**
++ * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
++ *
++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Authors: Felipe Balbi ,
++ * Sebastian Andrzej Siewior
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include
++
++#include
++#include
++
++#include "core.h"
++#include "gadget.h"
++#include "io.h"
++
++#define DMA_ADDR_INVALID (~(dma_addr_t)0)
++
++void dwc3_map_buffer_to_dma(struct dwc3_request *req)
++{
++ struct dwc3 *dwc = req->dep->dwc;
++
++ if (req->request.length == 0) {
++ /* req->request.dma = dwc->setup_buf_addr; */
++ return;
++ }
++
++ if (req->request.dma == DMA_ADDR_INVALID) {
++ req->request.dma = dma_map_single(dwc->dev, req->request.buf,
++ req->request.length, req->direction
++ ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
++ req->mapped = true;
++ }
++}
++
++void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
++{
++ struct dwc3 *dwc = req->dep->dwc;
++
++ if (req->request.length == 0) {
++ req->request.dma = DMA_ADDR_INVALID;
++ return;
++ }
++
++ if (req->mapped) {
++ dma_unmap_single(dwc->dev, req->request.dma,
++ req->request.length, req->direction
++ ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
++ req->mapped = 0;
++ req->request.dma = DMA_ADDR_INVALID;
++ }
++}
++
++void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
++ int status)
++{
++ struct dwc3 *dwc = dep->dwc;
++
++ if (req->queued) {
++ dep->busy_slot++;
++ /*
++ * Skip LINK TRB. We can't use req->trb and check for
++ * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
++ * completed (not the LINK TRB).
++ */
++ if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
++ usb_endpoint_xfer_isoc(dep->desc))
++ dep->busy_slot++;
++ }
++ list_del(&req->list);
++
++ if (req->request.status == -EINPROGRESS)
++ req->request.status = status;
++
++ dwc3_unmap_buffer_from_dma(req);
++
++ dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
++ req, dep->name, req->request.actual,
++ req->request.length, status);
++
++ spin_unlock(&dwc->lock);
++ req->request.complete(&req->dep->endpoint, &req->request);
++ spin_lock(&dwc->lock);
++}
++
++static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
++{
++ switch (cmd) {
++ case DWC3_DEPCMD_DEPSTARTCFG:
++ return "Start New Configuration";
++ case DWC3_DEPCMD_ENDTRANSFER:
++ return "End Transfer";
++ case DWC3_DEPCMD_UPDATETRANSFER:
++ return "Update Transfer";
++ case DWC3_DEPCMD_STARTTRANSFER:
++ return "Start Transfer";
++ case DWC3_DEPCMD_CLEARSTALL:
++ return "Clear Stall";
++ case DWC3_DEPCMD_SETSTALL:
++ return "Set Stall";
++ case DWC3_DEPCMD_GETSEQNUMBER:
++ return "Get Data Sequence Number";
++ case DWC3_DEPCMD_SETTRANSFRESOURCE:
++ return "Set Endpoint Transfer Resource";
++ case DWC3_DEPCMD_SETEPCONFIG:
++ return "Set Endpoint Configuration";
++ default:
++ return "UNKNOWN command";
++ }
++}
++
++int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
++ unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
++{
++ struct dwc3_ep *dep = dwc->eps[ep];
++ u32 timeout = 500;
++ u32 reg;
++
++ dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
++ dep->name,
++ dwc3_gadget_ep_cmd_string(cmd), params->param0,
++ params->param1, params->param2);
++
++ dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
++ dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
++ dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
++
++ dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
++ do {
++ reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
++ if (!(reg & DWC3_DEPCMD_CMDACT)) {
++ dev_vdbg(dwc->dev, "Command Complete --> %d\n",
++ DWC3_DEPCMD_STATUS(reg));
++ return 0;
++ }
++
++ /*
++ * We can't sleep here, because it is also called from
++ * interrupt context.
++ */
++ timeout--;
++ if (!timeout)
++ return -ETIMEDOUT;
++
++ udelay(1);
++ } while (1);
++}
++
++static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
++ struct dwc3_trb_hw *trb)
++{
++ u32 offset = (char *) trb - (char *) dep->trb_pool;
++
++ return dep->trb_pool_dma + offset;
++}
++
++static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
++{
++ struct dwc3 *dwc = dep->dwc;
++
++ if (dep->trb_pool)
++ return 0;
++
++ if (dep->number == 0 || dep->number == 1)
++ return 0;
++
++ dep->trb_pool = dma_alloc_coherent(dwc->dev,
++ sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
++ &dep->trb_pool_dma, GFP_KERNEL);
++ if (!dep->trb_pool) {
++ dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
++ dep->name);
++ return -ENOMEM;
++ }
++
++ return 0;
++}
++
++static void dwc3_free_trb_pool(struct dwc3_ep *dep)
++{
++ struct dwc3 *dwc = dep->dwc;
++
++ dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
++ dep->trb_pool, dep->trb_pool_dma);
++
++ dep->trb_pool = NULL;
++ dep->trb_pool_dma = 0;
++}
++
++static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
++{
++ struct dwc3_gadget_ep_cmd_params params;
++ u32 cmd;
++
++ memset(¶ms, 0x00, sizeof(params));
++
++ if (dep->number != 1) {
++ cmd = DWC3_DEPCMD_DEPSTARTCFG;
++ /* XferRscIdx == 0 for ep0 and 2 for the remaining */
++ if (dep->number > 1) {
++ if (dwc->start_config_issued)
++ return 0;
++ dwc->start_config_issued = true;
++ cmd |= DWC3_DEPCMD_PARAM(2);
++ }
++
++ return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
++ }
++
++ return 0;
++}
++
++static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
++ const struct usb_endpoint_descriptor *desc,
++ const struct usb_ss_ep_comp_descriptor *comp_desc)
++{
++ struct dwc3_gadget_ep_cmd_params params;
++
++ memset(¶ms, 0x00, sizeof(params));
++
++ params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
++ | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
++ | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
++
++ params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
++ | DWC3_DEPCFG_XFER_NOT_READY_EN;
++
++#if 0
++ if (comp_desc && USB_SS_MAX_STREAMS(comp_desc->bmAttributes)
++ && usb_endpoint_xfer_bulk(desc)) {
++ params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
++ | DWC3_DEPCFG_STREAM_EVENT_EN;
++ dep->stream_capable = true;
++ }
++#endif
++
++ if (usb_endpoint_xfer_isoc(desc))
++ params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
++
++ /*
++ * We are doing 1:1 mapping for endpoints, meaning
++ * Physical Endpoints 2 maps to Logical Endpoint 2 and
++ * so on. We consider the direction bit as part of the physical
++ * endpoint number. So USB endpoint 0x81 is 0x03.
++ */
++ params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
++
++ /*
++ * We must use the lower 16 TX FIFOs even though
++ * HW might have more
++ */
++ if (dep->direction)
++ params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
++
++ if (desc->bInterval) {
++ params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
++ dep->interval = 1 << (desc->bInterval - 1);
++ }
++
++ return dwc3_send_gadget_ep_cmd(dwc, dep->number,
++ DWC3_DEPCMD_SETEPCONFIG, ¶ms);
++}
++
++static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
++{
++ struct dwc3_gadget_ep_cmd_params params;
++
++ memset(¶ms, 0x00, sizeof(params));
++
++ params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
++
++ return dwc3_send_gadget_ep_cmd(dwc, dep->number,
++ DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
++}
++
++/**
++ * __dwc3_gadget_ep_enable - Initializes a HW endpoint
++ * @dep: endpoint to be initialized
++ * @desc: USB Endpoint Descriptor
++ *
++ * Caller should take care of locking
++ */
++static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
++ const struct usb_endpoint_descriptor *desc,
++ const struct usb_ss_ep_comp_descriptor *comp_desc)
++{
++ struct dwc3 *dwc = dep->dwc;
++ u32 reg;
++ int ret = -ENOMEM;
++
++ if (!(dep->flags & DWC3_EP_ENABLED)) {
++ ret = dwc3_gadget_start_config(dwc, dep);
++ if (ret)
++ return ret;
++ }
++
++ ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
++ if (ret)
++ return ret;
++
++ if (!(dep->flags & DWC3_EP_ENABLED)) {
++ struct dwc3_trb_hw *trb_st_hw;
++ struct dwc3_trb_hw *trb_link_hw;
++ struct dwc3_trb trb_link;
++
++ ret = dwc3_gadget_set_xfer_resource(dwc, dep);
++ if (ret)
++ return ret;
++
++ dep->desc = desc;
++ dep->comp_desc = comp_desc;
++ dep->type = usb_endpoint_type(desc);
++ dep->flags |= DWC3_EP_ENABLED;
++
++ reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
++ reg |= DWC3_DALEPENA_EP(dep->number);
++ dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
++
++ if (!usb_endpoint_xfer_isoc(desc))
++ return 0;
++
++ memset(&trb_link, 0, sizeof(trb_link));
++
++ /* Link TRB for ISOC. The HWO but is never reset */
++ trb_st_hw = &dep->trb_pool[0];
++
++ trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw);
++ trb_link.trbctl = DWC3_TRBCTL_LINK_TRB;
++ trb_link.hwo = true;
++
++ trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1];
++ dwc3_trb_to_hw(&trb_link, trb_link_hw);
++ }
++
++ return 0;
++}
++
++static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
++static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
++{
++ struct dwc3_request *req;
++
++ if (!list_empty(&dep->req_queued))
++ dwc3_stop_active_transfer(dwc, dep->number);
++
++ while (!list_empty(&dep->request_list)) {
++ req = next_request(&dep->request_list);
++
++ dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
++ }
++}
++
++/**
++ * __dwc3_gadget_ep_disable - Disables a HW endpoint
++ * @dep: the endpoint to disable
++ *
++ * This function also removes requests which are currently processed ny the
++ * hardware and those which are not yet scheduled.
++ * Caller should take care of locking.
++ */
++static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
++{
++ struct dwc3 *dwc = dep->dwc;
++ u32 reg;
++
++ dwc3_remove_requests(dwc, dep);
++
++ reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
++ reg &= ~DWC3_DALEPENA_EP(dep->number);
++ dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
++
++ dep->stream_capable = false;
++ dep->desc = NULL;
++ dep->comp_desc = NULL;
++ dep->type = 0;
++ dep->flags = 0;
++
++ return 0;
++}
++
++/* -------------------------------------------------------------------------- */
++
++static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
++ const struct usb_endpoint_descriptor *desc)
++{
++ return -EINVAL;
++}
++
++static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
++{
++ return -EINVAL;
++}
++
++/* -------------------------------------------------------------------------- */
++
++static int dwc3_gadget_ep_enable(struct usb_ep *ep,
++ const struct usb_endpoint_descriptor *desc)
++{
++ struct dwc3_ep *dep;
++ struct dwc3 *dwc;
++ unsigned long flags;
++ int ret;
++
++ if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
++ pr_debug("dwc3: invalid parameters\n");
++ return -EINVAL;
++ }
++
++ if (!desc->wMaxPacketSize) {
++ pr_debug("dwc3: missing wMaxPacketSize\n");
++ return -EINVAL;
++ }
++
++ dep = to_dwc3_ep(ep);
++ dwc = dep->dwc;
++
++ switch (usb_endpoint_type(desc)) {
++ case USB_ENDPOINT_XFER_CONTROL:
++ strncat(dep->name, "-control", sizeof(dep->name));
++ break;
++ case USB_ENDPOINT_XFER_ISOC:
++ strncat(dep->name, "-isoc", sizeof(dep->name));
++ break;
++ case USB_ENDPOINT_XFER_BULK:
++ strncat(dep->name, "-bulk", sizeof(dep->name));
++ break;
++ case USB_ENDPOINT_XFER_INT:
++ strncat(dep->name, "-int", sizeof(dep->name));
++ break;
++ default:
++ dev_err(dwc->dev, "invalid endpoint transfer type\n");
++ }
++
++ if (dep->flags & DWC3_EP_ENABLED) {
++ dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
++ dep->name);
++ return 0;
++ }
++
++ dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
++
++ spin_lock_irqsave(&dwc->lock, flags);
++ ret = __dwc3_gadget_ep_enable(dep, desc, NULL /*ep->comp_desc*/);
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ return ret;
++}
++
++static int dwc3_gadget_ep_disable(struct usb_ep *ep)
++{
++ struct dwc3_ep *dep;
++ struct dwc3 *dwc;
++ unsigned long flags;
++ int ret;
++
++ if (!ep) {
++ pr_debug("dwc3: invalid parameters\n");
++ return -EINVAL;
++ }
++
++ dep = to_dwc3_ep(ep);
++ dwc = dep->dwc;
++
++ if (!(dep->flags & DWC3_EP_ENABLED)) {
++ dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
++ dep->name);
++ return 0;
++ }
++
++ snprintf(dep->name, sizeof(dep->name), "ep%d%s",
++ dep->number >> 1,
++ (dep->number & 1) ? "in" : "out");
++
++ spin_lock_irqsave(&dwc->lock, flags);
++ ret = __dwc3_gadget_ep_disable(dep);
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ return ret;
++}
++
++static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
++ gfp_t gfp_flags)
++{
++ struct dwc3_request *req;
++ struct dwc3_ep *dep = to_dwc3_ep(ep);
++
++ req = kzalloc(sizeof(*req), gfp_flags);
++ if (!req) {
++ dev_err(dwc->dev, "not enough memory\n");
++ return NULL;
++ }
++
++ req->epnum = dep->number;
++ req->dep = dep;
++ req->request.dma = DMA_ADDR_INVALID;
++
++ return &req->request;
++}
++
++static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
++ struct usb_request *request)
++{
++ struct dwc3_request *req = to_dwc3_request(request);
++
++ kfree(req);
++}
++
++/*
++ * dwc3_prepare_trbs - setup TRBs from requests
++ * @dep: endpoint for which requests are being prepared
++ * @starting: true if the endpoint is idle and no requests are queued.
++ *
++ * The functions goes through the requests list and setups TRBs for the
++ * transfers. The functions returns once there are not more TRBs available or
++ * it run out of requests.
++ */
++static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep,
++ bool starting)
++{
++ struct dwc3_request *req, *n, *ret = NULL;
++ struct dwc3_trb_hw *trb_hw;
++ struct dwc3_trb trb;
++ u32 trbs_left;
++
++ BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
++
++ /* the first request must not be queued */
++ trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
++ /*
++ * if busy & slot are equal than it is either full or empty. If we are
++ * starting to proceed requests then we are empty. Otherwise we ar
++ * full and don't do anything
++ */
++ if (!trbs_left) {
++ if (!starting)
++ return NULL;
++ trbs_left = DWC3_TRB_NUM;
++ /*
++ * In case we start from scratch, we queue the ISOC requests
++ * starting from slot 1. This is done because we use ring
++ * buffer and have no LST bit to stop us. Instead, we place
++ * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
++ * after the first request so we start at slot 1 and have
++ * 7 requests proceed before we hit the first IOC.
++ * Other transfer types don't use the ring buffer and are
++ * processed from the first TRB until the last one. Since we
++ * don't wrap around we have to start at the beginning.
++ */
++ if (usb_endpoint_xfer_isoc(dep->desc)) {
++ dep->busy_slot = 1;
++ dep->free_slot = 1;
++ } else {
++ dep->busy_slot = 0;
++ dep->free_slot = 0;
++ }
++ }
++
++ /* The last TRB is a link TRB, not used for xfer */
++ if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
++ return NULL;
++
++ list_for_each_entry_safe(req, n, &dep->request_list, list) {
++ unsigned int last_one = 0;
++ unsigned int cur_slot;
++
++ trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
++ cur_slot = dep->free_slot;
++ dep->free_slot++;
++
++ /* Skip the LINK-TRB on ISOC */
++ if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
++ usb_endpoint_xfer_isoc(dep->desc))
++ continue;
++
++ dwc3_gadget_move_request_queued(req);
++ memset(&trb, 0, sizeof(trb));
++ trbs_left--;
++
++ /* Is our TRB pool empty? */
++ if (!trbs_left)
++ last_one = 1;
++ /* Is this the last request? */
++ if (list_empty(&dep->request_list))
++ last_one = 1;
++
++ /*
++ * FIXME we shouldn't need to set LST bit always but we are
++ * facing some weird problem with the Hardware where it doesn't
++ * complete even though it has been previously started.
++ *
++ * While we're debugging the problem, as a workaround to
++ * multiple TRBs handling, use only one TRB at a time.
++ */
++ last_one = 1;
++
++ req->trb = trb_hw;
++ if (!ret)
++ ret = req;
++
++ trb.bplh = req->request.dma;
++
++ if (usb_endpoint_xfer_isoc(dep->desc)) {
++ trb.isp_imi = true;
++ trb.csp = true;
++ } else {
++ trb.lst = last_one;
++ }
++
++ if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
++ trb.sid_sofn = req->request.stream_id;
++
++ switch (usb_endpoint_type(dep->desc)) {
++ case USB_ENDPOINT_XFER_CONTROL:
++ trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
++ break;
++
++ case USB_ENDPOINT_XFER_ISOC:
++ trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
++
++ /* IOC every DWC3_TRB_NUM / 4 so we can refill */
++ if (!(cur_slot % (DWC3_TRB_NUM / 4)))
++ trb.ioc = last_one;
++ break;
++
++ case USB_ENDPOINT_XFER_BULK:
++ case USB_ENDPOINT_XFER_INT:
++ trb.trbctl = DWC3_TRBCTL_NORMAL;
++ break;
++ default:
++ /*
++ * This is only possible with faulty memory because we
++ * checked it already :)
++ */
++ BUG();
++ }
++
++ trb.length = req->request.length;
++ trb.hwo = true;
++
++ dwc3_trb_to_hw(&trb, trb_hw);
++ req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
++
++ if (last_one)
++ break;
++ }
++
++ return ret;
++}
++
++static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
++ int start_new)
++{
++ struct dwc3_gadget_ep_cmd_params params;
++ struct dwc3_request *req;
++ struct dwc3 *dwc = dep->dwc;
++ int ret;
++ u32 cmd;
++
++ if (start_new && (dep->flags & DWC3_EP_BUSY)) {
++ dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
++ return -EBUSY;
++ }
++ dep->flags &= ~DWC3_EP_PENDING_REQUEST;
++
++ /*
++ * If we are getting here after a short-out-packet we don't enqueue any
++ * new requests as we try to set the IOC bit only on the last request.
++ */
++ if (start_new) {
++ if (list_empty(&dep->req_queued))
++ dwc3_prepare_trbs(dep, start_new);
++
++ /* req points to the first request which will be sent */
++ req = next_request(&dep->req_queued);
++ } else {
++ /*
++ * req points to the first request where HWO changed
++ * from 0 to 1
++ */
++ req = dwc3_prepare_trbs(dep, start_new);
++ }
++ if (!req) {
++ dep->flags |= DWC3_EP_PENDING_REQUEST;
++ return 0;
++ }
++
++ memset(¶ms, 0, sizeof(params));
++ params.param0 = upper_32_bits(req->trb_dma);
++ params.param1 = lower_32_bits(req->trb_dma);
++
++ if (start_new)
++ cmd = DWC3_DEPCMD_STARTTRANSFER;
++ else
++ cmd = DWC3_DEPCMD_UPDATETRANSFER;
++
++ cmd |= DWC3_DEPCMD_PARAM(cmd_param);
++ ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
++ if (ret < 0) {
++ dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
++
++ /*
++ * FIXME we need to iterate over the list of requests
++ * here and stop, unmap, free and del each of the linked
++ * requests instead of we do now.
++ */
++ dwc3_unmap_buffer_from_dma(req);
++ list_del(&req->list);
++ return ret;
++ }
++
++ dep->flags |= DWC3_EP_BUSY;
++ dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
++ dep->number);
++ return 0;
++}
++
++static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
++{
++ req->request.actual = 0;
++ req->request.status = -EINPROGRESS;
++ req->direction = dep->direction;
++ req->epnum = dep->number;
++
++ /*
++ * We only add to our list of requests now and
++ * start consuming the list once we get XferNotReady
++ * IRQ.
++ *
++ * That way, we avoid doing anything that we don't need
++ * to do now and defer it until the point we receive a
++ * particular token from the Host side.
++ *
++ * This will also avoid Host cancelling URBs due to too
++ * many NACKs.
++ */
++ dwc3_map_buffer_to_dma(req);
++ list_add_tail(&req->list, &dep->request_list);
++
++ /*
++ * There is one special case: XferNotReady with
++ * empty list of requests. We need to kick the
++ * transfer here in that situation, otherwise
++ * we will be NAKing forever.
++ *
++ * If we get XferNotReady before gadget driver
++ * has a chance to queue a request, we will ACK
++ * the IRQ but won't be able to receive the data
++ * until the next request is queued. The following
++ * code is handling exactly that.
++ */
++ if (dep->flags & DWC3_EP_PENDING_REQUEST) {
++ int ret;
++ int start_trans;
++
++ start_trans = 1;
++ if (usb_endpoint_xfer_isoc(dep->desc) &&
++ dep->flags & DWC3_EP_BUSY)
++ start_trans = 0;
++
++ ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
++ if (ret && ret != -EBUSY) {
++ struct dwc3 *dwc = dep->dwc;
++
++ dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
++ dep->name);
++ }
++ };
++
++ return 0;
++}
++
++static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
++ gfp_t gfp_flags)
++{
++ struct dwc3_request *req = to_dwc3_request(request);
++ struct dwc3_ep *dep = to_dwc3_ep(ep);
++ struct dwc3 *dwc = dep->dwc;
++
++ unsigned long flags;
++
++ int ret;
++
++ if (!dep->desc) {
++ dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
++ request, ep->name);
++ return -ESHUTDOWN;
++ }
++
++ dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
++ request, ep->name, request->length);
++
++ spin_lock_irqsave(&dwc->lock, flags);
++ ret = __dwc3_gadget_ep_queue(dep, req);
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ return ret;
++}
++
++static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
++ struct usb_request *request)
++{
++ struct dwc3_request *req = to_dwc3_request(request);
++ struct dwc3_request *r = NULL;
++
++ struct dwc3_ep *dep = to_dwc3_ep(ep);
++ struct dwc3 *dwc = dep->dwc;
++
++ unsigned long flags;
++ int ret = 0;
++
++ spin_lock_irqsave(&dwc->lock, flags);
++
++ list_for_each_entry(r, &dep->request_list, list) {
++ if (r == req)
++ break;
++ }
++
++ if (r != req) {
++ list_for_each_entry(r, &dep->req_queued, list) {
++ if (r == req)
++ break;
++ }
++ if (r == req) {
++ /* wait until it is processed */
++ dwc3_stop_active_transfer(dwc, dep->number);
++ goto out0;
++ }
++ dev_err(dwc->dev, "request %p was not queued to %s\n",
++ request, ep->name);
++ ret = -EINVAL;
++ goto out0;
++ }
++
++ /* giveback the request */
++ dwc3_gadget_giveback(dep, req, -ECONNRESET);
++
++out0:
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ return ret;
++}
++
++int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
++{
++ struct dwc3_gadget_ep_cmd_params params;
++ struct dwc3 *dwc = dep->dwc;
++ int ret;
++
++ memset(¶ms, 0x00, sizeof(params));
++
++ if (value) {
++ if (dep->number == 0 || dep->number == 1) {
++ /*
++ * Whenever EP0 is stalled, we will restart
++ * the state machine, thus moving back to
++ * Setup Phase
++ */
++ dwc->ep0state = EP0_SETUP_PHASE;
++ }
++
++ ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
++ DWC3_DEPCMD_SETSTALL, ¶ms);
++ if (ret)
++ dev_err(dwc->dev, "failed to %s STALL on %s\n",
++ value ? "set" : "clear",
++ dep->name);
++ else
++ dep->flags |= DWC3_EP_STALL;
++ } else {
++ if (dep->flags & DWC3_EP_WEDGE)
++ return 0;
++
++ ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
++ DWC3_DEPCMD_CLEARSTALL, ¶ms);
++ if (ret)
++ dev_err(dwc->dev, "failed to %s STALL on %s\n",
++ value ? "set" : "clear",
++ dep->name);
++ else
++ dep->flags &= ~DWC3_EP_STALL;
++ }
++
++ return ret;
++}
++
++static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
++{
++ struct dwc3_ep *dep = to_dwc3_ep(ep);
++
++ unsigned long flags;
++
++ int ret;
++
++ spin_lock_irqsave(&dwc->lock, flags);
++
++ if (usb_endpoint_xfer_isoc(dep->desc)) {
++ dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
++ ret = -EINVAL;
++ goto out;
++ }
++
++ ret = __dwc3_gadget_ep_set_halt(dep, value);
++out:
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ return ret;
++}
++
++/* -------------------------------------------------------------------------- */
++
++static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
++ .bLength = USB_DT_ENDPOINT_SIZE,
++ .bDescriptorType = USB_DT_ENDPOINT,
++ .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
++};
++
++static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
++ .enable = dwc3_gadget_ep0_enable,
++ .disable = dwc3_gadget_ep0_disable,
++ .alloc_request = dwc3_gadget_ep_alloc_request,
++ .free_request = dwc3_gadget_ep_free_request,
++ .queue = dwc3_gadget_ep0_queue,
++ .dequeue = dwc3_gadget_ep_dequeue,
++ .set_halt = dwc3_gadget_ep_set_halt,
++};
++
++static const struct usb_ep_ops dwc3_gadget_ep_ops = {
++ .enable = dwc3_gadget_ep_enable,
++ .disable = dwc3_gadget_ep_disable,
++ .alloc_request = dwc3_gadget_ep_alloc_request,
++ .free_request = dwc3_gadget_ep_free_request,
++ .queue = dwc3_gadget_ep_queue,
++ .dequeue = dwc3_gadget_ep_dequeue,
++ .set_halt = dwc3_gadget_ep_set_halt,
++};
++
++/* -------------------------------------------------------------------------- */
++
++static int dwc3_gadget_get_frame(struct usb_gadget *g)
++{
++ struct dwc3 *dwc = gadget_to_dwc(g);
++ u32 reg;
++
++ reg = dwc3_readl(dwc->regs, DWC3_DSTS);
++ return DWC3_DSTS_SOFFN(reg);
++}
++
++static int dwc3_gadget_wakeup(struct usb_gadget *g)
++{
++ struct dwc3 *dwc = gadget_to_dwc(g);
++
++ unsigned long timeout;
++ unsigned long flags;
++
++ u32 reg;
++
++ int ret = 0;
++
++ u8 link_state;
++ u8 speed;
++
++ spin_lock_irqsave(&dwc->lock, flags);
++
++ /*
++ * According to the Databook Remote wakeup request should
++ * be issued only when the device is in early suspend state.
++ *
++ * We can check that via USB Link State bits in DSTS register.
++ */
++ reg = dwc3_readl(dwc->regs, DWC3_DSTS);
++
++ speed = reg & DWC3_DSTS_CONNECTSPD;
++ if (speed == DWC3_DSTS_SUPERSPEED) {
++ dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
++ ret = -EINVAL;
++ goto out;
++ }
++
++ link_state = DWC3_DSTS_USBLNKST(reg);
++
++ switch (link_state) {
++ case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
++ case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
++ break;
++ default:
++ dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
++ link_state);
++ ret = -EINVAL;
++ goto out;
++ }
++
++ reg = dwc3_readl(dwc->regs, DWC3_DCTL);
++
++ /*
++ * Switch link state to Recovery. In HS/FS/LS this means
++ * RemoteWakeup Request
++ */
++ reg |= DWC3_DCTL_ULSTCHNG_RECOVERY;
++ dwc3_writel(dwc->regs, DWC3_DCTL, reg);
++
++ /* wait for at least 2000us */
++ usleep_range(2000, 2500);
++
++ /* write zeroes to Link Change Request */
++ reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
++ dwc3_writel(dwc->regs, DWC3_DCTL, reg);
++
++ /* pool until Link State change to ON */
++ timeout = 100;
++
++ while (timeout) {
++ reg = dwc3_readl(dwc->regs, DWC3_DSTS);
++
++ /* in HS, means ON */
++ if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
++ break;
++ timeout--;
++ mdelay(1);
++ }
++
++ if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
++ dev_err(dwc->dev, "failed to send remote wakeup\n");
++ ret = -EINVAL;
++ }
++
++out:
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ return ret;
++}
++
++static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
++ int is_selfpowered)
++{
++ struct dwc3 *dwc = gadget_to_dwc(g);
++
++ dwc->is_selfpowered = !!is_selfpowered;
++
++ return 0;
++}
++
++static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
++{
++ u32 reg;
++ u32 timeout = 500;
++
++ reg = dwc3_readl(dwc->regs, DWC3_DCTL);
++ if (is_on)
++ reg |= DWC3_DCTL_RUN_STOP;
++ else
++ reg &= ~DWC3_DCTL_RUN_STOP;
++
++ dwc3_writel(dwc->regs, DWC3_DCTL, reg);
++
++ do {
++ reg = dwc3_readl(dwc->regs, DWC3_DSTS);
++ if (is_on) {
++ if (!(reg & DWC3_DSTS_DEVCTRLHLT))
++ break;
++ } else {
++ if (reg & DWC3_DSTS_DEVCTRLHLT)
++ break;
++ }
++ timeout--;
++ if (!timeout)
++ break;
++ udelay(1);
++ } while (1);
++}
++
++static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
++{
++ struct dwc3 *dwc = gadget_to_dwc(g);
++ unsigned long flags;
++
++ is_on = !!is_on;
++
++ spin_lock_irqsave(&dwc->lock, flags);
++ dwc3_gadget_run_stop(dwc, is_on);
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ return 0;
++}
++
++static int dwc3_gadget_start(struct usb_gadget *g,
++ struct usb_gadget_driver *driver)
++{
++ struct dwc3 *dwc = gadget_to_dwc(g);
++ struct dwc3_ep *dep;
++ unsigned long flags;
++ int ret = 0;
++ u32 reg;
++
++ spin_lock_irqsave(&dwc->lock, flags);
++
++ if (dwc->gadget_driver) {
++ dev_err(dwc->dev, "%s is already bound\n",
++ dwc->gadget.name);
++ ret = -EBUSY;
++ goto err0;
++ }
++
++ dwc->gadget_driver = driver;
++ /* dwc->gadget.dev.driver = &driver->driver; */
++
++ reg = dwc3_readl(dwc->regs, DWC3_DCFG);
++ reg &= ~(DWC3_DCFG_SPEED_MASK);
++ reg |= dwc->maximum_speed;
++ dwc3_writel(dwc->regs, DWC3_DCFG, reg);
++
++ dwc->start_config_issued = false;
++
++ /* Start with SuperSpeed Default */
++ dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
++
++ dep = dwc->eps[0];
++ ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
++ if (ret) {
++ dev_err(dwc->dev, "failed to enable %s\n", dep->name);
++ goto err0;
++ }
++
++ dep = dwc->eps[1];
++ ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
++ if (ret) {
++ dev_err(dwc->dev, "failed to enable %s\n", dep->name);
++ goto err1;
++ }
++
++ /* begin to receive SETUP packets */
++ dwc->ep0state = EP0_SETUP_PHASE;
++ dwc3_ep0_out_start(dwc);
++
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ return 0;
++
++err1:
++ __dwc3_gadget_ep_disable(dwc->eps[0]);
++
++err0:
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ return ret;
++}
++
++#if 0
++static int dwc3_gadget_stop(struct usb_gadget *g,
++ struct usb_gadget_driver *driver)
++{
++ struct dwc3 *dwc = gadget_to_dwc(g);
++ unsigned long flags;
++
++ spin_lock_irqsave(&dwc->lock, flags);
++
++ __dwc3_gadget_ep_disable(dwc->eps[0]);
++ __dwc3_gadget_ep_disable(dwc->eps[1]);
++
++ dwc->gadget_driver = NULL;
++
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ return 0;
++}
++#endif
++static const struct usb_gadget_ops dwc3_gadget_ops = {
++ .get_frame = dwc3_gadget_get_frame,
++ .wakeup = dwc3_gadget_wakeup,
++ .set_selfpowered = dwc3_gadget_set_selfpowered,
++ .pullup = dwc3_gadget_pullup,
++
++
++};
++
++int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
++ int (*bind)(struct usb_gadget *))
++{
++ int ret;
++
++ ret = bind(&global_dwc3->gadget);
++ if (ret)
++ return ret;
++ ret = dwc3_gadget_start(&global_dwc3->gadget, driver);
++ if (ret)
++ return ret;
++ ret = usb_gadget_connect(&global_dwc3->gadget);
++ if (ret)
++ return ret;
++ return 0;
++}
++
++/* -------------------------------------------------------------------------- */
++
++static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
++{
++ struct dwc3_ep *dep;
++ u8 epnum;
++
++ INIT_LIST_HEAD(&dwc->gadget.ep_list);
++
++ for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
++ dep = kzalloc(sizeof(*dep), GFP_KERNEL);
++ if (!dep) {
++ dev_err(dwc->dev, "can't allocate endpoint %d\n",
++ epnum);
++ return -ENOMEM;
++ }
++
++ dep->dwc = dwc;
++ dep->number = epnum;
++ dwc->eps[epnum] = dep;
++
++ snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
++ (epnum & 1) ? "in" : "out");
++ dep->endpoint.name = dep->name;
++ dep->direction = (epnum & 1);
++
++ if (epnum == 0 || epnum == 1) {
++ dep->endpoint.maxpacket = 64;
++ dep->endpoint.ops = &dwc3_gadget_ep0_ops;
++ if (!epnum)
++ dwc->gadget.ep0 = &dep->endpoint;
++ } else {
++ int ret;
++
++ dep->endpoint.maxpacket = 1024;
++ dep->endpoint.ops = &dwc3_gadget_ep_ops;
++ list_add_tail(&dep->endpoint.ep_list,
++ &dwc->gadget.ep_list);
++
++ ret = dwc3_alloc_trb_pool(dep);
++ if (ret)
++ return ret;
++ }
++
++ INIT_LIST_HEAD(&dep->request_list);
++ INIT_LIST_HEAD(&dep->req_queued);
++ }
++
++ return 0;
++}
++
++static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
++{
++ struct dwc3_ep *dep;
++ u8 epnum;
++
++ for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
++ dep = dwc->eps[epnum];
++ dwc3_free_trb_pool(dep);
++
++ if (epnum != 0 && epnum != 1)
++ list_del(&dep->endpoint.ep_list);
++
++ kfree(dep);
++ }
++}
++
++static struct dwc3 *the_dwc;
++
++/* -------------------------------------------------------------------------- */
++static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
++ const struct dwc3_event_depevt *event, int status)
++{
++ struct dwc3_request *req;
++ struct dwc3_trb trb;
++ unsigned int count;
++ unsigned int s_pkt = 0;
++
++ do {
++ req = next_request(&dep->req_queued);
++ if (!req) {
++ WARN_ON_ONCE(1);
++ return 1;
++ }
++
++ dwc3_trb_to_nat(req->trb, &trb);
++
++ if (trb.hwo && status != -ESHUTDOWN)
++ /*
++ * We continue despite the error. There is not much we
++ * can do. If we don't clean in up we loop for ever. If
++ * we skip the TRB than it gets overwritten reused after
++ * a while since we use them in a ring buffer. a BUG()
++ * would help. Lets hope that if this occures, someone
++ * fixes the root cause instead of looking away :)
++ */
++ dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
++ dep->name, req->trb);
++ count = trb.length;
++
++ if (dep->direction) {
++ if (count) {
++ dev_err(dwc->dev, "incomplete IN transfer %s\n",
++ dep->name);
++ status = -ECONNRESET;
++ }
++ } else {
++ if (count && (event->status & DEPEVT_STATUS_SHORT))
++ s_pkt = 1;
++ }
++
++ /*
++ * We assume here we will always receive the entire data block
++ * which we should receive. Meaning, if we program RX to
++ * receive 4K but we receive only 2K, we assume that's all we
++ * should receive and we simply bounce the request back to the
++ * gadget driver for further processing.
++ */
++ req->request.actual += req->request.length - count;
++ dwc3_gadget_giveback(dep, req, status);
++ if (s_pkt)
++ break;
++ if ((event->status & DEPEVT_STATUS_LST) && trb.lst)
++ break;
++ if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
++ break;
++ } while (1);
++
++ if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
++ return 0;
++ return 1;
++}
++
++static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
++ struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
++ int start_new)
++{
++ unsigned status = 0;
++ int clean_busy;
++
++ if (event->status & DEPEVT_STATUS_BUSERR)
++ status = -ECONNRESET;
++
++ clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
++ if (clean_busy) {
++ dep->flags &= ~DWC3_EP_BUSY;
++ dep->res_trans_idx = 0;
++ }
++
++ /*
++ * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
++ * See dwc3_gadget_linksts_change_interrupt() for 1st half.
++ */
++ if (dwc->revision < DWC3_REVISION_183A) {
++ u32 reg;
++ int i;
++
++ for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
++ struct dwc3_ep *dep = dwc->eps[i];
++
++ if (!(dep->flags & DWC3_EP_ENABLED))
++ continue;
++
++ if (!list_empty(&dep->req_queued))
++ return;
++ }
++
++ reg = dwc3_readl(dwc->regs, DWC3_DCTL);
++ reg |= dwc->u1u2;
++ dwc3_writel(dwc->regs, DWC3_DCTL, reg);
++
++ dwc->u1u2 = 0;
++ }
++}
++
++static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
++ struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
++{
++ u32 uf;
++
++ if (list_empty(&dep->request_list)) {
++ dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
++ dep->name);
++ return;
++ }
++
++ if (event->parameters) {
++ u32 mask;
++
++ mask = ~(dep->interval - 1);
++ uf = event->parameters & mask;
++ /* 4 micro frames in the future */
++ uf += dep->interval * 4;
++ } else {
++ uf = 0;
++ }
++
++ __dwc3_gadget_kick_transfer(dep, uf, 1);
++}
++
++static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
++ const struct dwc3_event_depevt *event)
++{
++ struct dwc3 *dwc = dep->dwc;
++ struct dwc3_event_depevt mod_ev = *event;
++
++ /*
++ * We were asked to remove one requests. It is possible that this
++ * request and a few other were started together and have the same
++ * transfer index. Since we stopped the complete endpoint we don't
++ * know how many requests were already completed (and not yet)
++ * reported and how could be done (later). We purge them all until
++ * the end of the list.
++ */
++ mod_ev.status = DEPEVT_STATUS_LST;
++ dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
++ dep->flags &= ~DWC3_EP_BUSY;
++ /* pending requets are ignored and are queued on XferNotReady */
++}
++
++static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
++ const struct dwc3_event_depevt *event)
++{
++ u32 param = event->parameters;
++ u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
++
++ switch (cmd_type) {
++ case DWC3_DEPCMD_ENDTRANSFER:
++ dwc3_process_ep_cmd_complete(dep, event);
++ break;
++ case DWC3_DEPCMD_STARTTRANSFER:
++ dep->res_trans_idx = param & 0x7f;
++ break;
++ default:
++ break;
++ };
++}
++
++static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
++ const struct dwc3_event_depevt *event)
++{
++ struct dwc3_ep *dep;
++ u8 epnum = event->endpoint_number;
++
++ dep = dwc->eps[epnum];
++
++ dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
++ dwc3_ep_event_string(event->endpoint_event));
++
++ if (epnum == 0 || epnum == 1) {
++ dwc3_ep0_interrupt(dwc, event);
++ return;
++ }
++
++ switch (event->endpoint_event) {
++ case DWC3_DEPEVT_XFERCOMPLETE:
++ if (usb_endpoint_xfer_isoc(dep->desc)) {
++ dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
++ dep->name);
++ return;
++ }
++
++ dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
++ break;
++ case DWC3_DEPEVT_XFERINPROGRESS:
++ if (!usb_endpoint_xfer_isoc(dep->desc)) {
++ dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
++ dep->name);
++ return;
++ }
++
++ dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
++ break;
++ case DWC3_DEPEVT_XFERNOTREADY:
++ if (usb_endpoint_xfer_isoc(dep->desc)) {
++ dwc3_gadget_start_isoc(dwc, dep, event);
++ } else {
++ int ret;
++
++ dev_vdbg(dwc->dev, "%s: reason %s\n",
++ dep->name, event->status
++ ? "Transfer Active"
++ : "Transfer Not Active");
++
++ ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
++ if (!ret || ret == -EBUSY)
++ return;
++ dev_dbg(dwc->dev, "%s: failed to kick transfers %d.\n",
++ dep->name, ret);
++ }
++
++ break;
++ case DWC3_DEPEVT_STREAMEVT:
++ if (!usb_endpoint_xfer_bulk(dep->desc)) {
++ dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
++ dep->name);
++ return;
++ }
++
++ switch (event->status) {
++ case DEPEVT_STREAMEVT_FOUND:
++ dev_vdbg(dwc->dev, "Stream %d found and started\n",
++ event->parameters);
++
++ break;
++ case DEPEVT_STREAMEVT_NOTFOUND:
++ /* FALLTHROUGH */
++ default:
++ dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
++ }
++ break;
++ case DWC3_DEPEVT_RXTXFIFOEVT:
++ dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
++ break;
++ case DWC3_DEPEVT_EPCMDCMPLT:
++ dwc3_ep_cmd_compl(dep, event);
++ break;
++ }
++}
++
++static void dwc3_disconnect_gadget(struct dwc3 *dwc)
++{
++ if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
++ spin_unlock(&dwc->lock);
++ dwc->gadget_driver->disconnect(&dwc->gadget);
++ spin_lock(&dwc->lock);
++ }
++}
++
++static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
++{
++ struct dwc3_ep *dep;
++ struct dwc3_gadget_ep_cmd_params params;
++ u32 cmd;
++ int ret;
++
++ dep = dwc->eps[epnum];
++
++ WARN_ON(!dep->res_trans_idx);
++ if (dep->res_trans_idx) {
++ cmd = DWC3_DEPCMD_ENDTRANSFER;
++ cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
++ cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
++ memset(¶ms, 0, sizeof(params));
++ ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
++ WARN_ON_ONCE(ret);
++ dep->res_trans_idx = 0;
++ }
++}
++
++static void dwc3_stop_active_transfers(struct dwc3 *dwc)
++{
++ u32 epnum;
++
++ for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
++ struct dwc3_ep *dep;
++
++ dep = dwc->eps[epnum];
++ if (!(dep->flags & DWC3_EP_ENABLED))
++ continue;
++
++ dwc3_remove_requests(dwc, dep);
++ }
++}
++
++static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
++{
++ u32 epnum;
++
++ for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
++ struct dwc3_ep *dep;
++ struct dwc3_gadget_ep_cmd_params params;
++ int ret;
++
++ dep = dwc->eps[epnum];
++
++ if (!(dep->flags & DWC3_EP_STALL))
++ continue;
++
++ dep->flags &= ~DWC3_EP_STALL;
++
++ memset(¶ms, 0, sizeof(params));
++ ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
++ DWC3_DEPCMD_CLEARSTALL, ¶ms);
++ WARN_ON_ONCE(ret);
++ }
++}
++
++static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
++{
++ dev_vdbg(dwc->dev, "%s\n", __func__);
++#if 0
++ XXX
++ U1/U2 is powersave optimization. Skip it for now. Anyway we need to
++ enable it before we can disable it.
++
++ reg = dwc3_readl(dwc->regs, DWC3_DCTL);
++ reg &= ~DWC3_DCTL_INITU1ENA;
++ dwc3_writel(dwc->regs, DWC3_DCTL, reg);
++
++ reg &= ~DWC3_DCTL_INITU2ENA;
++ dwc3_writel(dwc->regs, DWC3_DCTL, reg);
++#endif
++
++ dwc3_stop_active_transfers(dwc);
++ dwc3_disconnect_gadget(dwc);
++ dwc->start_config_issued = false;
++
++ dwc->gadget.speed = USB_SPEED_UNKNOWN;
++ dwc->setup_packet_pending = false;
++}
++
++static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
++{
++ u32 reg;
++
++ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
++
++ if (on)
++ reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
++ else
++ reg |= DWC3_GUSB3PIPECTL_SUSPHY;
++
++ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
++}
++
++static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
++{
++ u32 reg;
++
++ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
++
++ if (on)
++ reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
++ else
++ reg |= DWC3_GUSB2PHYCFG_SUSPHY;
++
++ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
++}
++
++static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
++{
++ u32 reg;
++
++ dev_vdbg(dwc->dev, "%s\n", __func__);
++
++ /*
++ * WORKAROUND: DWC3 revisions <1.88a have an issue which
++ * would cause a missing Disconnect Event if there's a
++ * pending Setup Packet in the FIFO.
++ *
++ * There's no suggested workaround on the official Bug
++ * report, which states that "unless the driver/application
++ * is doing any special handling of a disconnect event,
++ * there is no functional issue".
++ *
++ * Unfortunately, it turns out that we _do_ some special
++ * handling of a disconnect event, namely complete all
++ * pending transfers, notify gadget driver of the
++ * disconnection, and so on.
++ *
++ * Our suggested workaround is to follow the Disconnect
++ * Event steps here, instead, based on a setup_packet_pending
++ * flag. Such flag gets set whenever we have a XferNotReady
++ * event on EP0 and gets cleared on XferComplete for the
++ * same endpoint.
++ *
++ * Refers to:
++ *
++ * STAR#9000466709: RTL: Device : Disconnect event not
++ * generated if setup packet pending in FIFO
++ */
++ if (dwc->revision < DWC3_REVISION_188A) {
++ if (dwc->setup_packet_pending)
++ dwc3_gadget_disconnect_interrupt(dwc);
++ }
++
++ /* Enable PHYs */
++ dwc3_gadget_usb2_phy_power(dwc, true);
++ dwc3_gadget_usb3_phy_power(dwc, true);
++
++ if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
++ dwc3_disconnect_gadget(dwc);
++
++ reg = dwc3_readl(dwc->regs, DWC3_DCTL);
++ reg &= ~DWC3_DCTL_TSTCTRL_MASK;
++ dwc3_writel(dwc->regs, DWC3_DCTL, reg);
++
++ dwc3_stop_active_transfers(dwc);
++ dwc3_clear_stall_all_ep(dwc);
++ dwc->start_config_issued = false;
++
++ /* Reset device address to zero */
++ reg = dwc3_readl(dwc->regs, DWC3_DCFG);
++ reg &= ~(DWC3_DCFG_DEVADDR_MASK);
++ dwc3_writel(dwc->regs, DWC3_DCFG, reg);
++}
++
++static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
++{
++ u32 reg;
++ u32 usb30_clock = DWC3_GCTL_CLK_BUS;
++
++ /*
++ * We change the clock only at SS but I dunno why I would want to do
++ * this. Maybe it becomes part of the power saving plan.
++ */
++
++ if (speed != DWC3_DSTS_SUPERSPEED)
++ return;
++
++ /*
++ * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
++ * each time on Connect Done.
++ */
++ if (!usb30_clock)
++ return;
++
++ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
++ reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
++ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
++}
++
++static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
++{
++ switch (speed) {
++ case USB_SPEED_SUPER:
++ dwc3_gadget_usb2_phy_power(dwc, false);
++ break;
++ case USB_SPEED_HIGH:
++ case USB_SPEED_FULL:
++ case USB_SPEED_LOW:
++ dwc3_gadget_usb3_phy_power(dwc, false);
++ break;
++ }
++}
++
++static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
++{
++ struct dwc3_gadget_ep_cmd_params params;
++ struct dwc3_ep *dep;
++ int ret;
++ u32 reg;
++ u8 speed;
++
++ dev_vdbg(dwc->dev, "%s\n", __func__);
++
++ memset(¶ms, 0x00, sizeof(params));
++
++ reg = dwc3_readl(dwc->regs, DWC3_DSTS);
++ speed = reg & DWC3_DSTS_CONNECTSPD;
++ dwc->speed = speed;
++
++ dwc3_update_ram_clk_sel(dwc, speed);
++
++ switch (speed) {
++ case DWC3_DCFG_SUPERSPEED:
++ /*
++ * WORKAROUND: DWC3 revisions <1.90a have an issue which
++ * would cause a missing USB3 Reset event.
++ *
++ * In such situations, we should force a USB3 Reset
++ * event by calling our dwc3_gadget_reset_interrupt()
++ * routine.
++ *
++ * Refers to:
++ *
++ * STAR#9000483510: RTL: SS : USB3 reset event may
++ * not be generated always when the link enters poll
++ */
++ if (dwc->revision < DWC3_REVISION_190A)
++ dwc3_gadget_reset_interrupt(dwc);
++
++ dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
++ dwc->gadget.ep0->maxpacket = 512;
++ dwc->gadget.speed = USB_SPEED_SUPER;
++ break;
++ case DWC3_DCFG_HIGHSPEED:
++ dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
++ dwc->gadget.ep0->maxpacket = 64;
++ dwc->gadget.speed = USB_SPEED_HIGH;
++ break;
++ case DWC3_DCFG_FULLSPEED2:
++ case DWC3_DCFG_FULLSPEED1:
++ dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
++ dwc->gadget.ep0->maxpacket = 64;
++ dwc->gadget.speed = USB_SPEED_FULL;
++ break;
++ case DWC3_DCFG_LOWSPEED:
++ dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
++ dwc->gadget.ep0->maxpacket = 8;
++ dwc->gadget.speed = USB_SPEED_LOW;
++ break;
++ }
++
++ /* Disable unneded PHY */
++ dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
++
++ dep = dwc->eps[0];
++ ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
++ if (ret) {
++ dev_err(dwc->dev, "failed to enable %s\n", dep->name);
++ return;
++ }
++
++ dep = dwc->eps[1];
++ ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
++ if (ret) {
++ dev_err(dwc->dev, "failed to enable %s\n", dep->name);
++ return;
++ }
++
++ /*
++ * Configure PHY via GUSB3PIPECTLn if required.
++ *
++ * Update GTXFIFOSIZn
++ *
++ * In both cases reset values should be sufficient.
++ */
++}
++
++static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
++{
++ dev_vdbg(dwc->dev, "%s\n", __func__);
++
++ /*
++ * TODO take core out of low power mode when that's
++ * implemented.
++ */
++
++ dwc->gadget_driver->resume(&dwc->gadget);
++}
++
++static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
++ unsigned int evtinfo)
++{
++ enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
++
++ /*
++ * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
++ * on the link partner, the USB session might do multiple entry/exit
++ * of low power states before a transfer takes place.
++ *
++ * Due to this problem, we might experience lower throughput. The
++ * suggested workaround is to disable DCTL[12:9] bits if we're
++ * transitioning from U1/U2 to U0 and enable those bits again
++ * after a transfer completes and there are no pending transfers
++ * on any of the enabled endpoints.
++ *
++ * This is the first half of that workaround.
++ *
++ * Refers to:
++ *
++ * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
++ * core send LGO_Ux entering U0
++ */
++ if (dwc->revision < DWC3_REVISION_183A) {
++ if (next == DWC3_LINK_STATE_U0) {
++ u32 u1u2;
++ u32 reg;
++
++ switch (dwc->link_state) {
++ case DWC3_LINK_STATE_U1:
++ case DWC3_LINK_STATE_U2:
++ reg = dwc3_readl(dwc->regs, DWC3_DCTL);
++ u1u2 = reg & (DWC3_DCTL_INITU2ENA
++ | DWC3_DCTL_ACCEPTU2ENA
++ | DWC3_DCTL_INITU1ENA
++ | DWC3_DCTL_ACCEPTU1ENA);
++
++ if (!dwc->u1u2)
++ dwc->u1u2 = reg & u1u2;
++
++ reg &= ~u1u2;
++
++ dwc3_writel(dwc->regs, DWC3_DCTL, reg);
++ break;
++ default:
++ /* do nothing */
++ break;
++ }
++ }
++ }
++
++ dwc->link_state = next;
++
++ dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
++}
++
++static void dwc3_gadget_interrupt(struct dwc3 *dwc,
++ const struct dwc3_event_devt *event)
++{
++ switch (event->type) {
++ case DWC3_DEVICE_EVENT_DISCONNECT:
++ dwc3_gadget_disconnect_interrupt(dwc);
++ break;
++ case DWC3_DEVICE_EVENT_RESET:
++ dwc3_gadget_reset_interrupt(dwc);
++ break;
++ case DWC3_DEVICE_EVENT_CONNECT_DONE:
++ dwc3_gadget_conndone_interrupt(dwc);
++ break;
++ case DWC3_DEVICE_EVENT_WAKEUP:
++ dwc3_gadget_wakeup_interrupt(dwc);
++ break;
++ case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
++ dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
++ break;
++ case DWC3_DEVICE_EVENT_EOPF:
++ dev_vdbg(dwc->dev, "End of Periodic Frame\n");
++ break;
++ case DWC3_DEVICE_EVENT_SOF:
++ dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
++ break;
++ case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
++ dev_vdbg(dwc->dev, "Erratic Error\n");
++ break;
++ case DWC3_DEVICE_EVENT_CMD_CMPL:
++ dev_vdbg(dwc->dev, "Command Complete\n");
++ break;
++ case DWC3_DEVICE_EVENT_OVERFLOW:
++ dev_vdbg(dwc->dev, "Overflow\n");
++ break;
++ default:
++ dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
++ }
++}
++
++static void dwc3_process_event_entry(struct dwc3 *dwc,
++ const union dwc3_event *event)
++{
++ /* Endpoint IRQ, handle it and return early */
++ if (event->type.is_devspec == 0) {
++ /* depevt */
++ return dwc3_endpoint_interrupt(dwc, &event->depevt);
++ }
++
++ switch (event->type.type) {
++ case DWC3_EVENT_TYPE_DEV:
++ dwc3_gadget_interrupt(dwc, &event->devt);
++ break;
++ /* REVISIT what to do with Carkit and I2C events ? */
++ default:
++ dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
++ }
++}
++
++static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
++{
++ struct dwc3_event_buffer *evt;
++ int left;
++ u32 count;
++
++ count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
++ count &= DWC3_GEVNTCOUNT_MASK;
++ if (!count)
++ return IRQ_NONE;
++
++ evt = dwc->ev_buffs[buf];
++ left = count;
++
++ while (left > 0) {
++ union dwc3_event event;
++
++ memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw));
++ dwc3_process_event_entry(dwc, &event);
++ /*
++ * XXX we wrap around correctly to the next entry as almost all
++ * entries are 4 bytes in size. There is one entry which has 12
++ * bytes which is a regular entry followed by 8 bytes data. ATM
++ * I don't know how things are organized if were get next to the
++ * a boundary so I worry about that once we try to handle that.
++ */
++ evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
++ left -= 4;
++
++ dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
++ }
++
++ return IRQ_HANDLED;
++}
++
++irqreturn_t dwc3_interrupt(int irq, void *_dwc)
++{
++ struct dwc3 *dwc = _dwc;
++ int i;
++ irqreturn_t ret = IRQ_NONE;
++
++ spin_lock(&dwc->lock);
++
++ for (i = 0; i < dwc->num_event_buffers; i++) {
++ irqreturn_t status;
++
++ status = dwc3_process_event_buf(dwc, i);
++ if (status == IRQ_HANDLED)
++ ret = status;
++ }
++
++ spin_unlock(&dwc->lock);
++
++ return ret;
++}
++
++/**
++ * dwc3_gadget_init - Initializes gadget related registers
++ * @dwc: Pointer to out controller context structure
++ *
++ * Returns 0 on success otherwise negative errno.
++ */
++int __devinit dwc3_gadget_init(struct dwc3 *dwc)
++{
++ u32 reg;
++ int ret;
++
++ dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
++ &dwc->ctrl_req_addr, GFP_KERNEL);
++ if (!dwc->ctrl_req) {
++ dev_err(dwc->dev, "failed to allocate ctrl request\n");
++ ret = -ENOMEM;
++ goto err0;
++ }
++
++ dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
++ &dwc->ep0_trb_addr, GFP_KERNEL);
++ if (!dwc->ep0_trb) {
++ dev_err(dwc->dev, "failed to allocate ep0 trb\n");
++ ret = -ENOMEM;
++ goto err1;
++ }
++
++ dwc->setup_buf = dma_alloc_coherent(dwc->dev,
++ sizeof(*dwc->setup_buf) * 2,
++ &dwc->setup_buf_addr, GFP_KERNEL);
++ if (!dwc->setup_buf) {
++ dev_err(dwc->dev, "failed to allocate setup buffer\n");
++ ret = -ENOMEM;
++ goto err2;
++ }
++
++ dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
++ 512, &dwc->ep0_bounce_addr, GFP_KERNEL);
++ if (!dwc->ep0_bounce) {
++ dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
++ ret = -ENOMEM;
++ goto err3;
++ }
++
++ dev_set_name(&dwc->gadget.dev, "gadget");
++
++ dwc->gadget.ops = &dwc3_gadget_ops;
++ dwc->gadget.is_dualspeed = true;
++ dwc->gadget.speed = USB_SPEED_UNKNOWN;
++
++ dwc->gadget.name = "dwc3-gadget";
++
++ the_dwc = dwc;
++
++ /*
++ * REVISIT: Here we should clear all pending IRQs to be
++ * sure we're starting from a well known location.
++ */
++
++ ret = dwc3_gadget_init_endpoints(dwc);
++ if (ret)
++ goto err4;
++
++ /* Enable all but Start and End of Frame IRQs */
++ reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
++ DWC3_DEVTEN_EVNTOVERFLOWEN |
++ DWC3_DEVTEN_CMDCMPLTEN |
++ DWC3_DEVTEN_ERRTICERREN |
++ DWC3_DEVTEN_WKUPEVTEN |
++ DWC3_DEVTEN_ULSTCNGEN |
++ DWC3_DEVTEN_CONNECTDONEEN |
++ DWC3_DEVTEN_USBRSTEN |
++ DWC3_DEVTEN_DISCONNEVTEN);
++ dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
++ return 0;
++
++ device_unregister(&dwc->gadget.dev);
++ dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
++ dwc3_gadget_free_endpoints(dwc);
++
++err4:
++ dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
++ dwc->ep0_bounce_addr);
++
++err3:
++ dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
++ dwc->setup_buf, dwc->setup_buf_addr);
++
++err2:
++ dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
++ dwc->ep0_trb, dwc->ep0_trb_addr);
++
++err1:
++ dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
++ dwc->ctrl_req, dwc->ctrl_req_addr);
++
++err0:
++ return ret;
++}
++
++void dwc3_gadget_exit(struct dwc3 *dwc)
++{
++ dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
++
++ dwc3_gadget_free_endpoints(dwc);
++
++ dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
++ dwc->ep0_bounce_addr);
++
++ dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
++ dwc->setup_buf, dwc->setup_buf_addr);
++
++ dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
++ dwc->ep0_trb, dwc->ep0_trb_addr);
++
++ dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
++ dwc->ctrl_req, dwc->ctrl_req_addr);
++
++ device_unregister(&dwc->gadget.dev);
++
++ the_dwc = NULL;
++}
++
++/* -------------------------------------------------------------------------- */
++
++int usb_gadget_register_driver(struct usb_gadget_driver *driver)
++{
++ return usb_gadget_probe_driver(driver, driver->bind);
++}
++
++/**
++ * usb_gadget_unregister_driver - unregisters a gadget driver.
++ * @driver: the gadget driver to unregister
++ */
++int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
++{
++ struct dwc3 *dwc = the_dwc;
++ unsigned long flags;
++
++ if (!driver || !driver->unbind)
++ return -EINVAL;
++
++ if (!dwc)
++ return -ENODEV;
++
++ if (dwc->gadget_driver != driver)
++ return -EINVAL;
++
++ driver->disconnect(&dwc->gadget);
++ driver->unbind(&dwc->gadget);
++
++ spin_lock_irqsave(&dwc->lock, flags);
++
++ dwc->gadget_driver = NULL;
++
++ spin_unlock_irqrestore(&dwc->lock, flags);
++
++ return 0;
++}
+diff --git a/drivers/usb/dwc3/dwc3_host.c b/drivers/usb/dwc3/dwc3_host.c
+new file mode 100644
+index 0000000..7cfe211
+--- /dev/null
++++ b/drivers/usb/dwc3/dwc3_host.c
+@@ -0,0 +1,102 @@
++/**
++ * host.c - DesignWare USB3 DRD Controller Host Glue
++ *
++ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Authors: Felipe Balbi ,
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include
++
++#include "core.h"
++
++static struct resource generic_resources[] = {
++ {
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++int dwc3_host_init(struct dwc3 *dwc)
++{
++ struct platform_device *xhci;
++ int ret;
++
++ xhci = platform_device_alloc("xhci", -1);
++ if (!xhci) {
++ dev_err(dwc->dev, "couldn't allocate xHCI device\n");
++ ret = -ENOMEM;
++ goto err0;
++ }
++
++ dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
++
++ xhci->dev.parent = dwc->dev;
++ xhci->dev.dma_mask = dwc->dev->dma_mask;
++ xhci->dev.dma_parms = dwc->dev->dma_parms;
++
++ dwc->xhci = xhci;
++
++ /* setup resources */
++ generic_resources[0].start = dwc->irq;
++
++ generic_resources[1].start = dwc->res->start;
++ generic_resources[1].end = dwc->res->start + 0x7fff;
++
++ ret = platform_device_add_resources(xhci, generic_resources,
++ ARRAY_SIZE(generic_resources));
++ if (ret) {
++ dev_err(dwc->dev, "couldn't add resources to xHCI device\n");
++ goto err1;
++ }
++
++ ret = platform_device_add(xhci);
++ if (ret) {
++ dev_err(dwc->dev, "failed to register xHCI device\n");
++ goto err1;
++ }
++
++ return 0;
++
++err1:
++ platform_device_put(xhci);
++
++err0:
++ return ret;
++}
++
++void dwc3_host_exit(struct dwc3 *dwc)
++{
++ platform_device_unregister(dwc->xhci);
++}
+diff --git a/drivers/usb/dwc3/dwc3_misc.c b/drivers/usb/dwc3/dwc3_misc.c
+new file mode 100644
+index 0000000..628e11e
+--- /dev/null
++++ b/drivers/usb/dwc3/dwc3_misc.c
+@@ -0,0 +1,20 @@
++#include
++
++#include
++#include
++
++#include "misc.h"
++#if 0
++int snprintf(char *buf, size_t size, const char *fmt, ...)
++{
++ va_list args;
++ int i;
++
++ va_start(args, fmt);
++ i = vsprintf(buf, fmt, args);
++ va_end(args);
++ if (i > size)
++ printf("*** Wrote too much bytes into the buffer ***\n");
++ return i;
++}
++#endif
+diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h
+new file mode 100644
+index 0000000..d97f467
+--- /dev/null
++++ b/drivers/usb/dwc3/gadget.h
+@@ -0,0 +1,186 @@
++/**
++ * gadget.h - DesignWare USB3 DRD Gadget Header
++ *
++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Authors: Felipe Balbi ,
++ * Sebastian Andrzej Siewior
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __DRIVERS_USB_DWC3_GADGET_H
++#define __DRIVERS_USB_DWC3_GADGET_H
++
++#include
++#include
++#include "io.h"
++
++struct dwc3;
++#define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint))
++#define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget))
++
++/* DEPCFG parameter 1 */
++#define DWC3_DEPCFG_INT_NUM(n) ((n) << 0)
++#define DWC3_DEPCFG_XFER_COMPLETE_EN (1 << 8)
++#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9)
++#define DWC3_DEPCFG_XFER_NOT_READY_EN (1 << 10)
++#define DWC3_DEPCFG_FIFO_ERROR_EN (1 << 11)
++#define DWC3_DEPCFG_STREAM_EVENT_EN (1 << 13)
++#define DWC3_DEPCFG_BINTERVAL_M1(n) ((n) << 16)
++#define DWC3_DEPCFG_STREAM_CAPABLE (1 << 24)
++#define DWC3_DEPCFG_EP_NUMBER(n) ((n) << 25)
++#define DWC3_DEPCFG_BULK_BASED (1 << 30)
++#define DWC3_DEPCFG_FIFO_BASED (1 << 31)
++
++/* DEPCFG parameter 0 */
++#define DWC3_DEPCFG_EP_TYPE(n) ((n) << 1)
++#define DWC3_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3)
++#define DWC3_DEPCFG_FIFO_NUMBER(n) ((n) << 17)
++#define DWC3_DEPCFG_BURST_SIZE(n) ((n) << 22)
++#define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26)
++#define DWC3_DEPCFG_IGN_SEQ_NUM (1 << 31)
++
++/* DEPXFERCFG parameter 0 */
++#define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
++
++struct dwc3_gadget_ep_cmd_params {
++ u32 param2;
++ u32 param1;
++ u32 param0;
++};
++
++/* -------------------------------------------------------------------------- */
++
++#define to_dwc3_request(r) (container_of(r, struct dwc3_request, request))
++
++static inline struct dwc3_request *next_request(struct list_head *list)
++{
++ if (list_empty(list))
++ return NULL;
++
++ return list_first_entry(list, struct dwc3_request, list);
++}
++
++static inline void dwc3_gadget_move_request_queued(struct dwc3_request *req)
++{
++ struct dwc3_ep *dep = req->dep;
++
++ req->queued = true;
++ list_move_tail(&req->list, &dep->req_queued);
++}
++
++void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
++ int status);
++
++void dwc3_ep0_interrupt(struct dwc3 *dwc,
++ const struct dwc3_event_depevt *event);
++void dwc3_ep0_out_start(struct dwc3 *dwc);
++int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
++ gfp_t gfp_flags);
++int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value);
++int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
++ unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
++void dwc3_map_buffer_to_dma(struct dwc3_request *req);
++void dwc3_unmap_buffer_from_dma(struct dwc3_request *req);
++
++/**
++ * dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW
++ * @dwc: DesignWare USB3 Pointer
++ * @number: DWC endpoint number
++ *
++ * Caller should take care of locking
++ */
++static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3 *dwc, u8 number)
++{
++ u32 res_id;
++
++ res_id = dwc3_readl(dwc->regs, DWC3_DEPCMD(number));
++
++ return DWC3_DEPCMD_GET_RSC_IDX(res_id);
++}
++
++/**
++ * dwc3_gadget_event_string - returns event name
++ * @event: the event code
++ */
++static inline const char *dwc3_gadget_event_string(u8 event)
++{
++ switch (event) {
++ case DWC3_DEVICE_EVENT_DISCONNECT:
++ return "Disconnect";
++ case DWC3_DEVICE_EVENT_RESET:
++ return "Reset";
++ case DWC3_DEVICE_EVENT_CONNECT_DONE:
++ return "Connection Done";
++ case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
++ return "Link Status Change";
++ case DWC3_DEVICE_EVENT_WAKEUP:
++ return "WakeUp";
++ case DWC3_DEVICE_EVENT_EOPF:
++ return "End-Of-Frame";
++ case DWC3_DEVICE_EVENT_SOF:
++ return "Start-Of-Frame";
++ case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
++ return "Erratic Error";
++ case DWC3_DEVICE_EVENT_CMD_CMPL:
++ return "Command Complete";
++ case DWC3_DEVICE_EVENT_OVERFLOW:
++ return "Overflow";
++ }
++
++ return "UNKNOWN";
++}
++
++/**
++ * dwc3_ep_event_string - returns event name
++ * @event: then event code
++ */
++static inline const char *dwc3_ep_event_string(u8 event)
++{
++ switch (event) {
++ case DWC3_DEPEVT_XFERCOMPLETE:
++ return "Transfer Complete";
++ case DWC3_DEPEVT_XFERINPROGRESS:
++ return "Transfer In-Progress";
++ case DWC3_DEPEVT_XFERNOTREADY:
++ return "Transfer Not Ready";
++ case DWC3_DEPEVT_RXTXFIFOEVT:
++ return "FIFO";
++ case DWC3_DEPEVT_STREAMEVT:
++ return "Stream";
++ case DWC3_DEPEVT_EPCMDCMPLT:
++ return "Endpoint Command Complete";
++ }
++
++ return "UNKNOWN";
++}
++
++#endif /* __DRIVERS_USB_DWC3_GADGET_H */
+diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
+new file mode 100644
+index 0000000..bc957db
+--- /dev/null
++++ b/drivers/usb/dwc3/io.h
+@@ -0,0 +1,54 @@
++/**
++ * io.h - DesignWare USB3 DRD IO Header
++ *
++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Authors: Felipe Balbi ,
++ * Sebastian Andrzej Siewior
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions, and the following disclaimer,
++ * without modification.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. The names of the above-listed copyright holders may not be used
++ * to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") version 2, as published by the Free
++ * Software Foundation.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __DRIVERS_USB_DWC3_IO_H
++#define __DRIVERS_USB_DWC3_IO_H
++
++#include
++
++static inline u32 dwc3_readl(void __iomem *base, u32 offset)
++{
++ return readl(base + offset);
++}
++
++static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
++{
++ writel(value, base + offset);
++}
++
++#endif /* __DRIVERS_USB_DWC3_IO_H */
+diff --git a/drivers/usb/dwc3/misc.h b/drivers/usb/dwc3/misc.h
+new file mode 100644
+index 0000000..da9012c
+--- /dev/null
++++ b/drivers/usb/dwc3/misc.h
+@@ -0,0 +1,269 @@
++#ifndef dwc3_misc_h
++#define dwc3_misc_h
++
++#include
++#include
++#include
++#include
++
++#define DWC3_USB_REGS_SIZE (CONFIG_USB_DWC3_UDC_REGS - \
++ CONFIG_USB_DWC3_UDC_REGS_END + 1)
++#define DWC3_WRAPPER_REGS_SIZE (CONFIG_USB_DWC3_WRAP_REGS - \
++ CONFIG_USB_DWC3_WRAP_REGS_END + 1)
++
++#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
++#define lower_32_bits(n) ((u32)(n))
++
++extern struct dwc3 *global_dwc3;
++
++typedef int mutex_t;
++typedef int spinlock_t;
++/*
++enum {
++ false = 0,
++ true = 1
++};
++typedef unsigned int bool;
++*/
++#define min_t(type, x, y) ({ \
++ type __min1 = (x); \
++ type __min2 = (y); \
++ __min1 < __min2 ? __min1: __min2; })
++
++#define __init
++#define __devinit
++#define __devinitconst
++#define __devexit
++
++static inline void *dma_alloc_coherent(void *dev, size_t size,
++ dma_addr_t *dma_handle, gfp_t gfp)
++{
++ void *p;
++
++ p = malloc(size);
++ *dma_handle = (unsigned long)p;
++ return p;
++}
++
++
++static inline void dma_free_coherent(struct device *dev, size_t size,
++ void *vaddr, dma_addr_t bus)
++{
++ free(vaddr);
++}
++
++static inline void kfree(void *p)
++{
++ free(p);
++}
++
++static inline void *kzalloc(unsigned int size, unsigned int flags)
++{
++ void *p;
++
++ p = malloc(size);
++ memset(p, 0, size);
++ return p;
++}
++
++#define GFP_KERNEL 0
++
++#define MAX_ERRNO 4095
++
++#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
++
++static inline void *ERR_PTR(long error)
++{
++ return (void *) error;
++}
++
++static inline long PTR_ERR(const void *ptr)
++{
++ return (long) ptr;
++}
++
++static inline long IS_ERR(const void *ptr)
++{
++ return IS_ERR_VALUE((unsigned long)ptr);
++}
++
++#define dev_err(dev, format, ...) printf(format, ## __VA_ARGS__)
++#if 0
++#define dev_dbg(dev, format, ...) printf(format, ## __VA_ARGS__)
++#define dev_vdbg(dev, format, ...) printf(format, ## __VA_ARGS__)
++#define pr_debug(format, ...) printf(format, ## __VA_ARGS__)
++#else
++static inline void dwc3_valength_dummy(void *p, char *fmt, ...) {}
++#define dev_dbg(dev, format, ...) dwc3_valength_dummy(dev, format, ## __VA_ARGS__)
++#define dev_vdbg(dev, format, ...) dwc3_valength_dummy(dev, format, ## __VA_ARGS__)
++#define pr_debug(format, ...) dwc3_valength_dummy(NULL, format, ## __VA_ARGS__)
++#endif
++
++static inline void pm_runtime_enable(struct device *dev) {}
++static inline void pm_runtime_get_sync(struct device *dev) {}
++static inline void pm_runtime_forbid(struct device *dev) {}
++static inline void pm_runtime_allow(struct device *dev) {}
++
++#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
++
++#define PAGE_SHIFT 12
++#define PAGE_SIZE (1UL << PAGE_SHIFT)
++#define PAGE_MASK (~(PAGE_SIZE-1))
++
++struct platform_device {
++ struct device dev;
++};
++
++static inline void __arch_iounmap(void *p) {}
++
++#define cpu_relax() asm volatile("" ::: "memory")
++
++enum dma_data_direction {
++ DMA_BIDIRECTIONAL = 0,
++ DMA_TO_DEVICE = 1,
++ DMA_FROM_DEVICE = 2,
++};
++
++static inline dma_addr_t dma_map_single(struct device *dev, void *ptr,
++ size_t size,
++ enum dma_data_direction dir)
++{
++ return (unsigned long)ptr;
++}
++
++static inline void dma_unmap_single(struct device *dev, dma_addr_t addr,
++ size_t size,
++ enum dma_data_direction dir)
++{
++}
++
++static inline void dma_sync_single_for_device(struct device *dev,
++ dma_addr_t addr, size_t size,
++ enum dma_data_direction dir)
++{
++}
++static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr,
++ size_t size,
++ enum dma_data_direction dir)
++{
++}
++
++static inline int device_register(struct device *dev)
++{
++ return 0;
++}
++
++static inline void device_unregister(struct device *dev)
++{
++}
++
++static inline int dev_set_name(struct device *dev, const char *fmt, ...)
++{
++ return 0;
++}
++
++#define spin_lock(x)
++#define spin_unlock(x)
++#define spin_lock_irqsave(x, y) y = 0;
++#define spin_unlock_irqrestore(x, y)
++#if 0
++static inline void mdelay(unsigned int msec)
++{
++ int i;
++
++ /* XXX VirtIO currently hangs on udelay(10+) */
++ for (i = 0; i < msec; i++)
++ udelay(5);
++}
++#endif
++static inline void msleep(unsigned int msec)
++{
++ mdelay(msec);
++}
++
++static inline void usleep_range(unsigned long min, unsigned long max)
++{
++ udelay(min);
++}
++
++#define container_of(ptr, type, member) ({ \
++ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
++ (type *)( (char *)__mptr - offsetof(type,member) );})
++
++#define __WARN_printf(arg...) do { printf("WarnON() in %s: %s(%d)\n", __FILE__, __func__, __LINE__); printf(arg); } while (0)
++
++#define WARN(condition, format...) ({ \
++ int __ret_warn_on = !!(condition); \
++ if (unlikely(__ret_warn_on)) \
++ __WARN_printf(format); \
++ unlikely(__ret_warn_on); \
++ })
++
++#define WARN_ONCE(condition, format...) ({ \
++ static bool __warned; \
++ int __ret_warn_once = !!(condition); \
++ \
++ if (unlikely(__ret_warn_once)) \
++ if (WARN(!__warned, format)) \
++ __warned = true; \
++ unlikely(__ret_warn_once); \
++ })
++
++#define dev_WARN_ONCE(dev, condition, format, arg...) \
++ WARN_ONCE(condition, format, ## arg)
++
++#define WARN_ON(condition) ({ \
++ int __ret_warn_on = !!(condition); \
++ if (unlikely(__ret_warn_on)) \
++ printf("WarnON() in %s: %s(%d)\n", __FILE__, __func__, __LINE__); \
++ unlikely(__ret_warn_on); \
++ })
++
++#define WARN_ON_ONCE(condition) ({ \
++ static bool __warned; \
++ int __ret_warn_once = !!(condition); \
++ \
++ if (unlikely(__ret_warn_once)) \
++ if (WARN_ON(!__warned)) \
++ __warned = true; \
++ unlikely(__ret_warn_once); \
++ })
++
++#define BUILD_BUG_ON_NOT_POWER_OF_2(n) \
++ BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0))
++#if 0
++/* never do isoc */
++static inline int usb_endpoint_xfer_isoc(
++ const struct usb_endpoint_descriptor *epd)
++{
++ return 0;
++}
++static inline int usb_endpoint_type(const struct usb_endpoint_descriptor *epd)
++{
++ return epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
++}
++#endif
++
++enum irqreturn {
++ IRQ_NONE,
++ IRQ_HANDLED,
++ IRQ_WAKE_THREAD,
++};
++
++typedef enum irqreturn irqreturn_t;
++
++int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
++ int (*bind)(struct usb_gadget *));
++int usb_gadget_unregister_driver(struct usb_gadget_driver *driver);
++
++struct dwc3;
++int snprintf(char *buf, size_t size, const char *fmt, ...);
++int __devinit dwc3_probe(struct platform_device *pdev);
++int __devexit dwc3_remove(struct platform_device *pdev);
++
++extern unsigned int dwc3_cable_connected;
++extern unsigned int dwc3_high_speed;
++
++#define USB_GADGET_DELAYED_STATUS 0x7fff /* Impossibly large value */
++
++#endif
+diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
+index 804a2bd..1ada7bb 100644
+--- a/drivers/usb/gadget/Makefile
++++ b/drivers/usb/gadget/Makefile
+@@ -17,6 +17,7 @@ obj-$(CONFIG_THOR_FUNCTION) += f_thor.o
+ obj-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o
+ obj-$(CONFIG_DFU_FUNCTION) += f_dfu.o
+ obj-$(CONFIG_USB_GADGET_MASS_STORAGE) += f_mass_storage.o
++obj-$(CONFIG_USB_FASTBOOT) += f_fastboot.o u_fastboot.o
+ endif
+ ifdef CONFIG_USB_ETHER
+ obj-y += ether.o
+diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
+index de75ff1..3b8b48b 100644
+--- a/drivers/usb/gadget/f_dfu.c
++++ b/drivers/usb/gadget/f_dfu.c
+@@ -601,6 +601,7 @@ dfu_handle(struct usb_function *f, const struct usb_ctrlrequest *ctrl)
+ (w_value >> 8) == DFU_DT_FUNC) {
+ value = min(len, (u16) sizeof(dfu_func));
+ memcpy(req->buf, &dfu_func, value);
++ dfu_trigger_enum_done();
+ }
+ } else /* DFU specific request */
+ value = dfu_state[f_dfu->dfu_state] (f_dfu, ctrl, gadget, req);
+diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
+new file mode 100644
+index 0000000..7570440
+--- /dev/null
++++ b/drivers/usb/gadget/f_fastboot.c
+@@ -0,0 +1,559 @@
++/*
++ * (C) Copyright 2008 - 2009
++ * Windriver,
++ * Tom Rix
++ *
++ * Copyright (c) 2011 Sebastian Andrzej Siewior
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include "g_fastboot.h"
++
++#define CONFIGURATION_NORMAL 1
++#define BULK_ENDPOINT 1
++#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0 (0x0200)
++#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 (0x0040)
++#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE (0x0040)
++
++static struct usb_string def_usb_fb_strings[] = {
++ { FB_STR_PRODUCT_IDX, "Default Product" },
++ { FB_STR_SERIAL_IDX, "1234567890" },
++ { FB_STR_CONFIG_IDX, "Android Fastboot" },
++ { FB_STR_INTERFACE_IDX, "Android Fastboot" },
++ { FB_STR_MANUFACTURER_IDX, "Default Manufacturer" },
++ { FB_STR_PROC_REV_IDX, "Default 1.0" },
++ { FB_STR_PROC_TYPE_IDX, "Emulator" },
++ { }
++};
++
++static struct usb_gadget_strings def_fb_strings = {
++ .language = 0x0409, /* en-us */
++ .strings = def_usb_fb_strings,
++};
++
++static struct usb_gadget_strings *vendor_fb_strings;
++
++static unsigned int gadget_is_connected;
++
++static u8 ep0_buffer[512];
++static u8 ep_out_buffer[EP_BUFFER_SIZE];
++static u8 ep_in_buffer[EP_BUFFER_SIZE];
++static int current_config;
++
++/* e1 */
++static struct usb_endpoint_descriptor fs_ep_in = {
++ .bLength = USB_DT_ENDPOINT_SIZE,
++ .bDescriptorType = USB_DT_ENDPOINT,
++ .bEndpointAddress = USB_DIR_IN, /* IN */
++ .bmAttributes = USB_ENDPOINT_XFER_BULK,
++ .wMaxPacketSize = TX_ENDPOINT_MAXIMUM_PACKET_SIZE,
++ .bInterval = 0x00,
++};
++
++/* e2 */
++static struct usb_endpoint_descriptor fs_ep_out = {
++ .bLength = USB_DT_ENDPOINT_SIZE,
++ .bDescriptorType = USB_DT_ENDPOINT,
++ .bEndpointAddress = USB_DIR_OUT, /* OUT */
++ .bmAttributes = USB_ENDPOINT_XFER_BULK,
++ .wMaxPacketSize = RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1,
++ .bInterval = 0x00,
++};
++
++static struct usb_endpoint_descriptor hs_ep_out = {
++ .bLength = USB_DT_ENDPOINT_SIZE,
++ .bDescriptorType = USB_DT_ENDPOINT,
++ .bEndpointAddress = USB_DIR_OUT, /* OUT */
++ .bmAttributes = USB_ENDPOINT_XFER_BULK,
++ .wMaxPacketSize = RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0,
++ .bInterval = 0x00,
++};
++
++const char *fb_find_usb_string(unsigned int id)
++{
++ struct usb_string *s;
++
++ for (s = vendor_fb_strings->strings; s && s->s; s++) {
++ if (s->id == id)
++ break;
++ }
++ if (!s || !s->s) {
++ for (s = def_fb_strings.strings; s && s->s; s++) {
++ if (s->id == id)
++ break;
++ }
++ }
++ if (!s)
++ return NULL;
++ return s->s;
++}
++
++static struct usb_gadget *g;
++static struct usb_request *ep0_req;
++
++struct usb_ep *ep_in;
++struct usb_request *req_in;
++
++struct usb_ep *ep_out;
++struct usb_request *req_out;
++
++static void fastboot_ep0_complete(struct usb_ep *ep, struct usb_request *req)
++{
++ int status = req->status;
++
++ if (!status)
++ return;
++ printf("ep0 status %d\n", status);
++}
++
++static int fastboot_bind(struct usb_gadget *gadget)
++{
++
++ g = gadget;
++ ep0_req = usb_ep_alloc_request(g->ep0, 0);
++ if (!ep0_req)
++ goto err;
++ ep0_req->buf = ep0_buffer;
++ ep0_req->complete = fastboot_ep0_complete;
++
++ ep_in = usb_ep_autoconfig(gadget, &fs_ep_in);
++ if (!ep_in)
++ goto err;
++ ep_in->driver_data = ep_in;
++
++ ep_out = usb_ep_autoconfig(gadget, &fs_ep_out);
++ if (!ep_out)
++ goto err;
++ ep_out->driver_data = ep_out;
++
++ hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress;
++ return 0;
++err:
++ return -1;
++}
++
++static void fastboot_unbind(struct usb_gadget *gadget)
++{
++ usb_ep_free_request(g->ep0, ep0_req);
++ ep_in->driver_data = NULL;
++ ep_out->driver_data = NULL;
++}
++
++/* This is the TI USB vendor id a product ID from TI's internal tree */
++#define DEVICE_VENDOR_ID 0x0451
++#define DEVICE_PRODUCT_ID 0xd022
++#define DEVICE_BCD 0x0100
++
++struct usb_device_descriptor fb_descriptor = {
++ .bLength = sizeof(fb_descriptor),
++ .bDescriptorType = USB_DT_DEVICE,
++ .bcdUSB = 0x200,
++ .bMaxPacketSize0 = 0x40,
++ .idVendor = DEVICE_VENDOR_ID,
++ .idProduct = DEVICE_PRODUCT_ID,
++ .bcdDevice = DEVICE_BCD,
++ .iManufacturer = FB_STR_MANUFACTURER_IDX,
++ .iProduct = FB_STR_PRODUCT_IDX,
++ .iSerialNumber = FB_STR_SERIAL_IDX,
++ .bNumConfigurations = 1,
++};
++
++#define TOT_CFG_DESC_LEN (USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + \
++ USB_DT_ENDPOINT_SIZE + USB_DT_ENDPOINT_SIZE)
++
++static struct usb_config_descriptor config_desc = {
++ .bLength = USB_DT_CONFIG_SIZE,
++ .bDescriptorType = USB_DT_CONFIG,
++ .wTotalLength = cpu_to_le16(TOT_CFG_DESC_LEN),
++ .bNumInterfaces = 1,
++ .bConfigurationValue = CONFIGURATION_NORMAL,
++ .iConfiguration = FB_STR_CONFIG_IDX,
++ .bmAttributes = 0xc0,
++ .bMaxPower = 0x32,
++};
++
++static struct usb_interface_descriptor interface_desc = {
++ .bLength = USB_DT_INTERFACE_SIZE,
++ .bDescriptorType = USB_DT_INTERFACE,
++ .bInterfaceNumber = 0x00,
++ .bAlternateSetting = 0x00,
++ .bNumEndpoints = 0x02,
++ .bInterfaceClass = FASTBOOT_INTERFACE_CLASS,
++ .bInterfaceSubClass = FASTBOOT_INTERFACE_SUB_CLASS,
++ .bInterfaceProtocol = FASTBOOT_INTERFACE_PROTOCOL,
++ .iInterface = FB_STR_INTERFACE_IDX,
++};
++
++static struct usb_qualifier_descriptor qual_desc = {
++ .bLength = sizeof(qual_desc),
++ .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
++ .bcdUSB = 0x200,
++ .bMaxPacketSize0 = 0x40,
++ .bNumConfigurations = 1,
++};
++
++static int fastboot_setup_get_descr(struct usb_gadget *gadget,
++ const struct usb_ctrlrequest *ctrl)
++{
++ u16 w_value = le16_to_cpu(ctrl->wValue);
++ u16 w_length = le16_to_cpu(ctrl->wLength);
++ u16 val;
++ int ret;
++ u32 bytes_remaining;
++ u32 bytes_total;
++ u32 this_inc;
++
++ val = w_value >> 8;
++
++ switch (val) {
++ case USB_DT_DEVICE:
++
++ memcpy(ep0_buffer, &fb_descriptor, sizeof(fb_descriptor));
++ ep0_req->length = min(w_length, sizeof(fb_descriptor));
++ ret = usb_ep_queue(gadget->ep0, ep0_req, 0);
++ break;
++
++ case USB_DT_CONFIG:
++
++ bytes_remaining = min(w_length, sizeof(ep0_buffer));
++ bytes_total = 0;
++
++ /* config */
++ this_inc = min(bytes_remaining, USB_DT_CONFIG_SIZE);
++ bytes_remaining -= this_inc;
++ memcpy(ep0_buffer + bytes_total, &config_desc, this_inc);
++ bytes_total += this_inc;
++
++ /* interface */
++ this_inc = min(bytes_remaining, USB_DT_INTERFACE_SIZE);
++ bytes_remaining -= this_inc;
++ memcpy(ep0_buffer + bytes_total, &interface_desc, this_inc);
++ bytes_total += this_inc;
++
++ /* ep in */
++ this_inc = min(bytes_remaining, USB_DT_ENDPOINT_SIZE);
++ bytes_remaining -= this_inc;
++ memcpy(ep0_buffer + bytes_total, &fs_ep_in, this_inc);
++ bytes_total += this_inc;
++
++ /* ep out */
++ this_inc = min(bytes_remaining, USB_DT_ENDPOINT_SIZE);
++
++ if (gadget->speed == USB_SPEED_HIGH)
++ memcpy(ep0_buffer + bytes_total, &hs_ep_out,
++ this_inc);
++ else
++ memcpy(ep0_buffer + bytes_total, &fs_ep_out,
++ this_inc);
++ bytes_total += this_inc;
++
++ ep0_req->length = bytes_total;
++ ret = usb_ep_queue(gadget->ep0, ep0_req, 0);
++ break;
++
++ case USB_DT_STRING:
++
++ ret = usb_gadget_get_string(vendor_fb_strings,
++ w_value & 0xff, ep0_buffer);
++ if (ret < 0)
++ ret = usb_gadget_get_string(&def_fb_strings,
++ w_value & 0xff, ep0_buffer);
++ if (ret < 0)
++ break;
++
++ ep0_req->length = ret;
++ ret = usb_ep_queue(gadget->ep0, ep0_req, 0);
++ break;
++
++ case USB_DT_DEVICE_QUALIFIER:
++
++ memcpy(ep0_buffer, &qual_desc, sizeof(qual_desc));
++ ep0_req->length = min(w_length, sizeof(qual_desc));
++ ret = usb_ep_queue(gadget->ep0, ep0_req, 0);
++ break;
++ default:
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
++static int fastboot_setup_get_conf(struct usb_gadget *gadget,
++ const struct usb_ctrlrequest *ctrl)
++{
++ u16 w_length = le16_to_cpu(ctrl->wLength);
++
++ if (w_length == 0)
++ return -1;
++
++ ep0_buffer[0] = current_config;
++ ep0_req->length = 1;
++ return usb_ep_queue(gadget->ep0, ep0_req, 0);
++}
++
++static void fastboot_complete_in(struct usb_ep *ep, struct usb_request *req)
++{
++ int status = req->status;
++
++ if (status)
++ printf("status: %d ep_in trans: %d\n",
++ status,
++ req->actual);
++}
++
++static int fastboot_disable_ep(struct usb_gadget *gadget)
++{
++ if (req_out) {
++ usb_ep_free_request(ep_out, req_out);
++ req_out = NULL;
++ }
++ if (req_in) {
++ usb_ep_free_request(ep_in, req_in);
++ req_in = NULL;
++ }
++ usb_ep_disable(ep_out);
++ usb_ep_disable(ep_in);
++
++ return 0;
++}
++
++static int fastboot_enable_ep(struct usb_gadget *gadget)
++{
++ int ret;
++
++ /* make sure we don't enable the ep twice */
++ if (gadget->speed == USB_SPEED_HIGH)
++ ret = usb_ep_enable(ep_out, &hs_ep_out);
++ else
++ ret = usb_ep_enable(ep_out, &fs_ep_out);
++ if (ret) {
++ printf("failed to enable out ep\n");
++ goto err;
++ }
++
++ req_out = usb_ep_alloc_request(ep_out, 0);
++ if (!req_out) {
++ printf("failed to alloc out req\n");
++ goto err;
++ }
++
++ ret = usb_ep_enable(ep_in, &fs_ep_in);
++ if (ret) {
++ printf("failed to enable in ep\n");
++ goto err;
++ }
++ req_in = usb_ep_alloc_request(ep_in, 0);
++ if (!req_in) {
++ printf("failed alloc req in\n");
++ goto err;
++ }
++
++ req_out->complete = rx_handler_command;
++ req_out->buf = ep_out_buffer;
++ req_out->length = sizeof(ep_out_buffer);
++
++ req_in->buf = ep_in_buffer;
++ req_in->length = sizeof(ep_in_buffer);
++
++ ret = usb_ep_queue(ep_out, req_out, 0);
++ if (ret)
++ goto err;
++
++ return 0;
++err:
++ fastboot_disable_ep(gadget);
++ return -1;
++}
++
++static int fastboot_set_interface(struct usb_gadget *gadget, u32 enable)
++{
++ if (enable && req_out)
++ return 0;
++ if (!enable && !req_out)
++ return 0;
++
++ if (enable)
++ return fastboot_enable_ep(gadget);
++ else
++ return fastboot_disable_ep(gadget);
++}
++
++static int fastboot_setup_out_req(struct usb_gadget *gadget,
++ const struct usb_ctrlrequest *req)
++{
++ switch (req->bRequestType & USB_RECIP_MASK) {
++ case USB_RECIP_DEVICE:
++ switch (req->bRequest) {
++ case USB_REQ_SET_CONFIGURATION:
++
++ ep0_req->length = 0;
++ if (req->wValue == CONFIGURATION_NORMAL) {
++ current_config = CONFIGURATION_NORMAL;
++ fastboot_set_interface(gadget, 1);
++ return usb_ep_queue(gadget->ep0,
++ ep0_req, 0);
++ }
++ if (req->wValue == 0) {
++ current_config = 0;
++ fastboot_set_interface(gadget, 0);
++ return usb_ep_queue(gadget->ep0,
++ ep0_req, 0);
++ }
++ return -1;
++ break;
++ default:
++ return -1;
++ };
++
++ case USB_RECIP_INTERFACE:
++ switch (req->bRequest) {
++ case USB_REQ_SET_INTERFACE:
++
++ ep0_req->length = 0;
++ if (!fastboot_set_interface(gadget, 1))
++ return usb_ep_queue(gadget->ep0,
++ ep0_req, 0);
++ return -1;
++ break;
++ default:
++ return -1;
++ }
++
++ case USB_RECIP_ENDPOINT:
++ switch (req->bRequest) {
++ case USB_REQ_CLEAR_FEATURE:
++
++ return usb_ep_queue(gadget->ep0, ep0_req, 0);
++ break;
++ default:
++ return -1;
++ }
++ }
++ return -1;
++}
++
++static int fastboot_setup(struct usb_gadget *gadget,
++ const struct usb_ctrlrequest *req)
++{
++ if ((req->bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
++ return -1;
++
++ if ((req->bRequestType & USB_DIR_IN) == 0)
++ /* host-to-device */
++ return fastboot_setup_out_req(gadget, req);
++
++ /* device-to-host */
++ if ((req->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
++ switch (req->bRequest) {
++ case USB_REQ_GET_DESCRIPTOR:
++ return fastboot_setup_get_descr(gadget, req);
++ break;
++
++ case USB_REQ_GET_CONFIGURATION:
++ return fastboot_setup_get_conf(gadget, req);
++ break;
++ default:
++ return -1;
++ }
++ }
++ return -1;
++}
++
++static void fastboot_disconnect(struct usb_gadget *gadget)
++{
++ fastboot_disable_ep(gadget);
++ gadget_is_connected = 0;
++}
++
++struct usb_gadget_driver fast_gadget = {
++ .bind = fastboot_bind,
++ .unbind = fastboot_unbind,
++ .setup = fastboot_setup,
++ .disconnect = fastboot_disconnect,
++};
++
++static int udc_is_probbed;
++
++int fastboot_init(void)
++{
++ int ret;
++
++ ret = fastboot_board_init(&fb_cfg, &vendor_fb_strings);
++ if (ret)
++ return ret;
++ if (!vendor_fb_strings)
++ return -EINVAL;
++
++ ret = usb_gadget_init_udc();
++ if (ret) {
++ printf("gadget probe failed\n");
++ return 1;
++ }
++ udc_is_probbed = 1;
++
++ ret = usb_gadget_register_driver(&fast_gadget);
++ if (ret) {
++ printf("Add gadget failed\n");
++ goto err;
++ }
++
++ gadget_is_connected = 1;
++ usb_gadget_handle_interrupts();
++ return 0;
++
++err:
++ fastboot_shutdown();
++ return 1;
++}
++
++int fastboot_poll(void)
++{
++ usb_gadget_handle_interrupts();
++
++ if (gadget_is_connected)
++ return 0;
++ else
++ return 1;
++}
++
++void fastboot_shutdown(void)
++{
++ if (!udc_is_probbed)
++ return;
++ udc_is_probbed = 0;
++ usb_gadget_exit_udc();
++}
++
++int fastboot_tx_write(const char *buffer, unsigned int buffer_size)
++{
++ int ret;
++
++ if (req_in->complete == NULL)
++ req_in->complete = fastboot_complete_in;
++
++ memcpy(req_in->buf, buffer, buffer_size);
++ req_in->length = buffer_size;
++ ret = usb_ep_queue(ep_in, req_in, 0);
++ if (ret)
++ printf("Error %d on queue\n", ret);
++ return 0;
++}
+diff --git a/drivers/usb/gadget/g_fastboot.h b/drivers/usb/gadget/g_fastboot.h
+new file mode 100644
+index 0000000..ff2621c
+--- /dev/null
++++ b/drivers/usb/gadget/g_fastboot.h
+@@ -0,0 +1,20 @@
++#ifndef _G_FASTBOOT_H_
++#define _G_FASTBOOT_H_
++
++#define EP_BUFFER_SIZE 4096
++#define FASTBOOT_INTERFACE_CLASS 0xff
++#define FASTBOOT_INTERFACE_SUB_CLASS 0x42
++#define FASTBOOT_INTERFACE_PROTOCOL 0x03
++#define FASTBOOT_VERSION "0.4"
++
++extern struct fastboot_config fb_cfg;
++extern struct usb_ep *ep_in;
++extern struct usb_request *req_in;
++extern struct usb_ep *ep_out;
++extern struct usb_request *req_out;
++
++void rx_handler_command(struct usb_ep *ep, struct usb_request *req);
++int fastboot_tx_write(const char *buffer, unsigned int buffer_size);
++const char *fb_find_usb_string(unsigned int id);
++
++#endif
+diff --git a/drivers/usb/gadget/u_fastboot.c b/drivers/usb/gadget/u_fastboot.c
+new file mode 100644
+index 0000000..00762aa
+--- /dev/null
++++ b/drivers/usb/gadget/u_fastboot.c
+@@ -0,0 +1,308 @@
++/*
++ * (C) Copyright 2008 - 2009
++ * Windriver,
++ * Tom Rix
++ *
++ * Copyright (c) 2011 Sebastian Andrzej Siewior
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * Part of the rx_handler were copied from the Android project.
++ * Specifically rx command parsing in the usb_rx_data_complete
++ * function of the file bootable/bootloader/legacy/usbloader/usbloader.c
++ *
++ * The logical naming of flash comes from the Android project
++ * Thse structures and functions that look like fastboot_flash_*
++ * They come from bootable/bootloader/legacy/libboot/flash.c
++ *
++ * This is their Copyright:
++ *
++ * Copyright (C) 2008 The Android Open Source Project
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
++ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
++ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
++ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
++ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
++ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
++ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
++ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
++ * SUCH DAMAGE.
++ */
++#include
++#include
++#include
++#include
++#include "g_fastboot.h"
++
++/* The 64 defined bytes plus \0 */
++#define RESPONSE_LEN (64 + 1)
++
++struct fastboot_config fb_cfg;
++
++static unsigned int download_size;
++static unsigned int download_bytes;
++
++static int fastboot_tx_write_str(const char *buffer)
++{
++ return fastboot_tx_write(buffer, strlen(buffer));
++}
++
++static void compl_do_reset(struct usb_ep *ep, struct usb_request *req)
++{
++ do_reset(NULL, 0, 0, NULL);
++}
++
++static void cb_reboot(struct usb_ep *ep, struct usb_request *req)
++{
++ req_in->complete = compl_do_reset;
++ fastboot_tx_write_str("OKAY");
++}
++
++static int strcmp_l1(const char *s1, const char *s2)
++{
++ return strncmp(s1, s2, strlen(s1));
++}
++
++static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
++{
++ char *cmd = req->buf;
++ char response[RESPONSE_LEN];
++ const char *s;
++
++ strcpy(response, "OKAY");
++ strsep(&cmd, ":");
++ if (!cmd) {
++ fastboot_tx_write_str("FAILmissing var");
++ return;
++ }
++
++ if (!strcmp_l1("version", cmd)) {
++ strncat(response, FASTBOOT_VERSION, sizeof(response));
++
++ } else if (!strcmp_l1("downloadsize", cmd)) {
++ char str_num[12];
++
++ sprintf(str_num, "%08x", fb_cfg.transfer_buffer_size);
++ strncat(response, str_num, sizeof(response));
++
++ } else if (!strcmp_l1("product", cmd)) {
++
++ s = fb_find_usb_string(FB_STR_PRODUCT_IDX);
++ if (s)
++ strncat(response, s, sizeof(response));
++ else
++ strcpy(response, "FAILValue not set");
++
++ } else if (!strcmp_l1("serialno", cmd)) {
++
++ s = fb_find_usb_string(FB_STR_SERIAL_IDX);
++ if (s)
++ strncat(response, s, sizeof(response));
++ else
++ strcpy(response, "FAILValue not set");
++
++ } else if (!strcmp_l1("cpurev", cmd)) {
++
++ s = fb_find_usb_string(FB_STR_PROC_REV_IDX);
++ if (s)
++ strncat(response, s, sizeof(response));
++ else
++ strcpy(response, "FAILValue not set");
++ } else if (!strcmp_l1("secure", cmd)) {
++
++ s = fb_find_usb_string(FB_STR_PROC_TYPE_IDX);
++ if (s)
++ strncat(response, s, sizeof(response));
++ else
++ strcpy(response, "FAILValue not set");
++ } else {
++ strcpy(response, "FAILVariable not implemented");
++ }
++ fastboot_tx_write_str(response);
++}
++
++static unsigned int rx_bytes_expected(void)
++{
++ int rx_remain = download_size - download_bytes;
++ if (rx_remain < 0)
++ return 0;
++ if (rx_remain > EP_BUFFER_SIZE)
++ return EP_BUFFER_SIZE;
++ return rx_remain;
++}
++
++#define BYTES_PER_DOT 32768
++static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req)
++{
++ char response[RESPONSE_LEN];
++ unsigned int transfer_size = download_size - download_bytes;
++ const unsigned char *buffer = req->buf;
++ unsigned int buffer_size = req->actual;
++
++ if (req->status != 0) {
++ printf("Bad status: %d\n", req->status);
++ return;
++ }
++
++ if (buffer_size < transfer_size)
++ transfer_size = buffer_size;
++
++ memcpy(fb_cfg.transfer_buffer + download_bytes,
++ buffer, transfer_size);
++
++ download_bytes += transfer_size;
++
++ /* Check if transfer is done */
++ if (download_bytes >= download_size) {
++ /*
++ * Reset global transfer variable, keep download_bytes because
++ * it will be used in the next possible flashing command
++ */
++ download_size = 0;
++ req->complete = rx_handler_command;
++ req->length = EP_BUFFER_SIZE;
++
++ sprintf(response, "OKAY");
++ fastboot_tx_write_str(response);
++
++ printf("\ndownloading of %d bytes finished\n",
++ download_bytes);
++ } else
++ req->length = rx_bytes_expected();
++
++ if (download_bytes && !(download_bytes % BYTES_PER_DOT)) {
++ printf(".");
++ if (!(download_bytes % (74 * BYTES_PER_DOT)))
++ printf("\n");
++
++ }
++ req->actual = 0;
++ usb_ep_queue(ep, req, 0);
++}
++
++static void cb_download(struct usb_ep *ep, struct usb_request *req)
++{
++ char *cmd = req->buf;
++ char response[RESPONSE_LEN];
++
++ strsep(&cmd, ":");
++ download_size = simple_strtoul(cmd, NULL, 16);
++ download_bytes = 0;
++
++ printf("Starting download of %d bytes\n",
++ download_size);
++
++ if (0 == download_size) {
++ sprintf(response, "FAILdata invalid size");
++ } else if (download_size >
++ fb_cfg.transfer_buffer_size) {
++ download_size = 0;
++ sprintf(response, "FAILdata too large");
++ } else {
++ sprintf(response, "DATA%08x", download_size);
++ req->complete = rx_handler_dl_image;
++ req->length = rx_bytes_expected();
++ }
++ fastboot_tx_write_str(response);
++}
++
++static char boot_addr_start[32];
++static char *bootm_args[] = { "bootm", boot_addr_start, NULL };
++
++static void do_bootm_on_complete(struct usb_ep *ep, struct usb_request *req)
++{
++ req->complete = NULL;
++ fastboot_shutdown();
++ printf("Booting kernel..\n");
++
++ do_bootm(NULL, 0, 2, bootm_args);
++
++ /* This only happens if image is somehow faulty so we start over */
++ do_reset(NULL, 0, 0, NULL);
++}
++
++static void cb_boot(struct usb_ep *ep, struct usb_request *req)
++{
++ sprintf(boot_addr_start, "0x%p", fb_cfg.transfer_buffer);
++
++ req_in->complete = do_bootm_on_complete;
++ fastboot_tx_write_str("OKAY");
++ return;
++}
++
++struct cmd_dispatch_info {
++ char *cmd;
++ void (*cb)(struct usb_ep *ep, struct usb_request *req);
++};
++
++static struct cmd_dispatch_info cmd_dispatch_info[] = {
++ {
++ .cmd = "reboot",
++ .cb = cb_reboot,
++ }, {
++ .cmd = "getvar:",
++ .cb = cb_getvar,
++ }, {
++ .cmd = "download:",
++ .cb = cb_download,
++ }, {
++ .cmd = "boot",
++ .cb = cb_boot,
++ },
++};
++
++void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
++{
++ char response[RESPONSE_LEN];
++ char *cmdbuf = req->buf;
++ void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL;
++ int i;
++
++ sprintf(response, "FAIL");
++
++ for (i = 0; i < ARRAY_SIZE(cmd_dispatch_info); i++) {
++ if (!strcmp_l1(cmd_dispatch_info[i].cmd, cmdbuf)) {
++ func_cb = cmd_dispatch_info[i].cb;
++ break;
++ }
++ }
++
++ if (!func_cb)
++ fastboot_tx_write_str("FAILunknown command");
++ else
++ func_cb(ep, req);
++
++ if (req->status == 0) {
++ *cmdbuf = '\0';
++ req->actual = 0;
++ usb_ep_queue(ep, req, 0);
++ }
++}
+diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
+index 9ab5446..e0f6f52 100644
+--- a/examples/standalone/Makefile
++++ b/examples/standalone/Makefile
+@@ -40,6 +40,10 @@ ELF := $(addprefix $(obj)/,$(ELF))
+
+ gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
++ifeq ($(ARCH) , x86)
++gcclibdir := $(shell dirname $(NORMAL_LIBGCC))
++endif
++
+ # For PowerPC there's no need to compile standalone applications as a
+ # relocatable executable. The relocation data is not needed, and
+ # also causes the entry point of the standalone application to be
+diff --git a/fs/fat/fat.c b/fs/fat/fat.c
+index 54f42ea..23e99d3 100644
+--- a/fs/fat/fat.c
++++ b/fs/fat/fat.c
+@@ -42,6 +42,7 @@ static disk_partition_t cur_part_info;
+ #define DOS_BOOT_MAGIC_OFFSET 0x1fe
+ #define DOS_FS_TYPE_OFFSET 0x36
+ #define DOS_FS32_TYPE_OFFSET 0x52
++#define DOS_PART_TBL_OFFSET 0x1be
+
+ static int disk_read(__u32 block, __u32 nr_blocks, void *buf)
+ {
+@@ -76,7 +77,37 @@ int fat_set_blk_dev(block_dev_desc_t *dev_desc, disk_partition_t *info)
+ return 0;
+ if (!memcmp(buffer + DOS_FS32_TYPE_OFFSET, "FAT32", 5))
+ return 0;
+-
++#ifdef CONFIG_FAT_MBR_SCAN
++ /* Test if it could be an MBR, and update start block to the
++ * first available primary partition
++ */
++ unsigned char *part_desc = (buffer + DOS_PART_TBL_OFFSET);
++ int i = 0;
++ for (i = 0; i < 4; i++, part_desc+=16) {
++ /* Check part type to be a primary FAT partition*/
++ if ((*(part_desc+4) == 0x1) || (*(part_desc+4) == 0x4) ||
++ (*(part_desc+4) == 0x6) || (*(part_desc+4) == 0xb) ||
++ (*(part_desc+4) == 0xc) || (*(part_desc+4) == 0xe) ){
++ int lba_start = (*(part_desc + 8 + 3) << 24) +
++ (*(part_desc + 8 + 2) << 16) +
++ (*(part_desc + 8 + 1) << 8) +
++ *(part_desc + 8 + 0);
++ int lba_size = (*(part_desc + 12 + 3) << 24) +
++ (*(part_desc + 12 + 2) << 16) +
++ (*(part_desc + 12 + 1) << 8) +
++ *(part_desc + 12 + 0);
++ debug("Found partition in MBR lba start:%d lba size:%d\n",
++ lba_start, lba_size);
++ debug("Old partition info lba start:"LBAFU" size:"LBAFU"\n",
++ cur_part_info.start, cur_part_info.size);
++ cur_part_info.start += lba_start;
++ cur_part_info.size = lba_size;
++ debug("New partition info lba start:"LBAFU" size:"LBAFU"\n",
++ cur_part_info.start, cur_part_info.size);
++ return 0;
++ }
++ }
++#endif
+ cur_dev = NULL;
+ return -1;
+ }
+@@ -185,7 +216,7 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry)
+ }
+
+ debug("FAT%d: entry: 0x%04x = %d, offset: 0x%04x = %d\n",
+- mydata->fatsize, entry, entry, offset, offset);
++ mydata->fatsize, entry, entry, offset, offset);
+
+ /* Read a new block of FAT entries into the cache. */
+ if (bufnum != mydata->fatbufnum) {
+@@ -246,7 +277,7 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry)
+ break;
+ }
+ debug("FAT%d: ret: %08x, offset: %04x\n",
+- mydata->fatsize, ret, offset);
++ mydata->fatsize, ret, offset);
+
+ return ret;
+ }
+diff --git a/include/android_image.h b/include/android_image.h
+new file mode 100644
+index 0000000..5af32c5
+--- /dev/null
++++ b/include/android_image.h
+@@ -0,0 +1,102 @@
++/*
++ * This is from the Android Project,
++ * bootloader/legacy/include/boot/bootimg.h
++ *
++ * Copyright (C) 2008 The Android Open Source Project
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
++ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
++ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
++ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
++ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
++ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
++ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
++ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
++ * SUCH DAMAGE.
++ */
++
++#ifndef _ANDROID_IMAGE_H_
++#define _ANDROID_IMAGE_H_
++
++#define ANDR_BOOT_MAGIC "ANDROID!"
++#define ANDR_BOOT_MAGIC_SIZE 8
++#define ANDR_BOOT_NAME_SIZE 16
++#define ANDR_BOOT_ARGS_SIZE 512
++
++struct andr_img_hdr {
++ u8 magic[ANDR_BOOT_MAGIC_SIZE];
++
++ u32 kernel_size; /* size in bytes */
++ u32 kernel_addr; /* physical load addr */
++
++ u32 ramdisk_size; /* size in bytes */
++ u32 ramdisk_addr; /* physical load addr */
++
++ u32 second_size; /* size in bytes */
++ u32 second_addr; /* physical load addr */
++
++ u32 tags_addr; /* physical addr for kernel tags */
++ u32 page_size; /* flash page size we assume */
++ u32 unused[2]; /* future expansion: should be 0 */
++
++ char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */
++
++ char cmdline[ANDR_BOOT_ARGS_SIZE];
++
++ u32 id[8]; /* timestamp / checksum / sha1 / etc */
++};
++
++#ifdef CONFIG_ANDROID_BOOT_IMAGE
++u32 android_img_get_end(struct andr_img_hdr *hdr);
++u32 android_img_get_kload(struct andr_img_hdr *hdr);
++int android_image_get_kernel(struct andr_img_hdr *hdr, int verify);
++#else
++static inline u32 android_img_get_end(struct andr_img_hdr *hdr) { return 0; }
++static inline u32 android_img_get_kload(struct andr_img_hdr *hdr) { return 0; }
++static inline int android_image_get_kernel(struct andr_img_hdr *hdr, int verify)
++{
++ return -1;
++}
++#endif
++
++/*
++ * +-----------------+
++ * | boot header | 1 page
++ * +-----------------+
++ * | kernel | n pages
++ * +-----------------+
++ * | ramdisk | m pages
++ * +-----------------+
++ * | second stage | o pages
++ * +-----------------+
++ *
++ * n = (kernel_size + page_size - 1) / page_size
++ * m = (ramdisk_size + page_size - 1) / page_size
++ * o = (second_size + page_size - 1) / page_size
++ *
++ * 0. all entities are page_size aligned in flash
++ * 1. kernel and ramdisk are required (size != 0)
++ * 2. second is optional (second_size == 0 -> no second)
++ * 3. load each element (kernel, ramdisk, second) at
++ * the specified physical address (kernel_addr, etc)
++ * 4. prepare tags at tag_addr. kernel_args[] is
++ * appended to the kernel commandline in the tags.
++ * 5. r0 = 0, r1 = MACHINE_TYPE, r2 = tags_addr
++ * 6. if second_size != 0: jump to second_addr
++ * else: jump to kernel_addr
++ */
++#endif
+diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
+index d1d732f..b5b1f7f 100644
+--- a/include/configs/coreboot.h
++++ b/include/configs/coreboot.h
+@@ -27,6 +27,7 @@
+ #define CONFIG_SYS_EARLY_PCI_INIT
+
+ #define CONFIG_LMB
++#define CONFIG_USE_FDT
+ #define CONFIG_OF_LIBFDT
+ #define CONFIG_OF_CONTROL
+ #define CONFIG_OF_SEPARATE
+diff --git a/include/configs/edison.h b/include/configs/edison.h
+new file mode 100644
+index 0000000..fe0759f
+--- /dev/null
++++ b/include/configs/edison.h
+@@ -0,0 +1,268 @@
++#ifndef _EDISON_H
++#define _EDISON_H
++
++#define CONFIG_WATCHDOG
++#define CONFIG_WATCHDOG_HEARTBEAT 30
++#define CONFIG_SFI
++#define CONFIG_BOARD_LATE_INIT
++
++/*-----------------------------------------------------------------------
++ * Misc
++ */
++
++#define CONFIG_CMD_ITEST
++#define CONFIG_CMD_ASKENV
++#define CONFIG_CMD_BDI
++#define CONFIG_CMD_BSP
++#define CONFIG_CMD_BOOTD
++#define CONFIG_CMD_CACHE
++#define CONFIG_CMD_CONSOLE
++/*
++ *#define CONFIG_CMD_DATE
++ */
++#define CONFIG_CMD_DIAG
++#define CONFIG_CMD_ECHO
++#define CONFIG_CMD_EDITENV
++#define CONFIG_CMD_ELF
++#define CONFIG_CMD_ENV_CALLBACK
++#define CONFIG_CMD_ENV_FLAGS
++#define CONFIG_CMD_ENV_EXISTS
++/*
++ *#define CONFIG_CMD_GETTIME
++ */
++#define CONFIG_CMD_GREPENV
++#define CONFIG_CMD_HASH
++#define CONFIG_CMD_INI
++/*
++ *#define CONFIG_CMD_KGDB
++ */
++/*
++ *#define CONFIG_CMD_MD5SUM
++ */
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMORY
++#define CONFIG_CMD_PORTIO
++#define CONFIG_CMD_READ
++#define CONFIG_CMD_REGINFO
++/*
++ *#define CONFIG_CMD_I2C
++ *#define CONFIG_SYS_I2C_SPEED 50000
++ */
++/*
++ *#define CONFIG_CMD_SHA1SUM
++ */
++#define CONFIG_CMD_SOURCE
++/*
++ *#define CONFIG_CMD_SPI
++ */
++#define CONFIG_CMD_TIMER
++
++/*
++ *#define CONFIG_CMD_TRACE
++ */
++/*
++ *#define CONFIG_CMD_DATE
++ */
++#define CONFIG_CMD_ECHO
++/*
++ *#define CONFIG_CMD_GPIO
++ */
++#define CONFIG_CMD_LOADB
++#define CONFIG_CMD_LOADS
++#define CONFIG_CMD_IRQ
++#define CONFIG_CMD_MEMORY
++#define CONFIG_CMD_MISC
++#define CONFIG_CMD_PCI
++#define CONFIG_CMD_SOURCE
++/*
++ *#define CONFIG_CMD_TIME
++ *#define CONFIG_CMD_GETTIME
++ */
++/*
++ *#define CONFIG_CMD_USB
++ */
++/*
++ *#define EARLY_TRACE
++ *#define FTRACE
++ */
++
++
++/*-----------------------------------------------------------------------
++ * Boot
++ */
++
++#define CONFIG_ZBOOT_32
++#define CONFIG_CMD_ZBOOT
++#define CONFIG_AUTOBOOT
++#define CONFIG_BOOTCOMMAND "run bootcmd"
++#define CONFIG_BOOTDELAY 3
++
++/*-----------------------------------------------------------------------
++ * DEBUG
++ */
++
++/*
++ *#define DEBUG
++ */
++
++/*
++ *#define CONFIG_PRE_CONSOLE_BUFFER
++ *#define CONFIG_PRE_CON_BUF_SZ (1024*1024*2)
++ *#define CONFIG_PRE_CON_BUF_ADDR 0x29200000
++ */
++
++/*-----------------------------------------------------------------------
++ * Serial
++ */
++
++#define CONFIG_SERIAL
++#define CONFIG_SYS_TNG_SERIAL
++#define CONFIG_SYS_TNG_SERIAL2
++#define CONFIG_BAUDRATE 115200
++
++/*
++* MMC
++ */
++#define CONFIG_MD5
++#define CONFIG_GENERIC_MMC
++#define CONFIG_MMC
++#define CONFIG_SDHCI
++#define CONFIG_TANGIER_SDHCI
++#define CONFIG_CMD_MMC
++#define CONFIG_MMC_SDMA
++/*#define CONFIG_MMC_TRACE*/
++
++/************************************************************
++ * DISK Partition support
++ ************************************************************/
++#define CONFIG_EFI_PARTITION
++#define CONFIG_DOS_PARTITION
++#define CONFIG_MAC_PARTITION
++
++#define CONFIG_FS_FAT
++#define CONFIG_CMD_FAT
++#define CONFIG_FAT_MBR_SCAN
++#define CONFIG_FAT_WRITE
++
++#define CONFIG_CMD_GPT
++#define CONFIG_CMD_PART
++#define CONFIG_CMD_EXT4
++#define CONFIG_CMD_EXT4_WRITE
++#define CONFIG_PARTITION_UUIDS
++#define CONFIG_RANDOM_UUID
++#define CONFIG_CMD_FS_GENERIC
++ /*
++ * Miscellaneous configurable options
++ */
++#define CONFIG_SYS_LONGHELP
++#define CONFIG_SYS_PROMPT "boot > "
++#define CONFIG_SYS_CBSIZE 2048
++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
++ sizeof(CONFIG_SYS_PROMPT) + \
++ 16)
++#define CONFIG_SYS_MAXARGS 128
++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
++#define CONFIG_AUTO_COMPLETE
++#define CONFIG_SYS_HUSH_PARSER
++
++#define CONFIG_SHA1
++#define CONFIG_CMD_SHA1SUM
++/*-----------------------------------------------------------------------
++ * Board Features
++ */
++
++#define CONFIG_SYS_NO_FLASH
++#define CONFIG_INHERIT_GDT
++
++/*-----------------------------------------------------------------------
++ * Memory
++ */
++
++#define CONFIG_SYS_LOAD_ADDR 0x100000
++#define CONFIG_PHYSMEM
++
++#define CONFIG_SYS_CACHELINE_SIZE 64
++
++#define CONFIG_NR_DRAM_BANKS 3
++
++#define CONFIG_SYS_STACK_SIZE (32 * 1024)
++
++#define CONFIG_SYS_CAR_ADDR 0x19200000
++#define CONFIG_SYS_CAR_SIZE (16 * 1024)
++
++#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
++#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
++
++#define CONFIG_SYS_MALLOC_LEN ( 128 * 1024 * 1024)
++
++#define CONFIG_SYS_HEAP_SIZE (128*1024*1024)
++#define CONFIG_SYS_HEAP_MINI_SIZE (5*1024*1024)
++
++#define CONFIG_SYS_MEMTEST_START 0x00100000
++#define CONFIG_SYS_MEMTEST_END 0x01000000
++
++/*-----------------------------------------------------------------------
++ * CPU Features
++ */
++
++#define CONFIG_SYS_X86_TSC_TIMER
++#define CONFIG_SYS_NUM_IRQS 16
++#define CONFIG_PCI
++#define CONFIG_SYS_PCAT_INTERRUPTS
++
++#define CONFIG_CMD_GETTIME
++#define CONFIG_INTEL_MID
++
++/*-----------------------------------------------------------------------
++ * Environment
++ */
++#define CONFIG_ENV_IS_IN_MMC
++#define CONFIG_SYS_MMC_ENV_DEV 0
++#define CONFIG_SYS_MMC_ENV_PART 0
++#define CONFIG_ENV_SIZE (64*1024)
++#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
++#define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024)
++#define CONFIG_CMD_SAVEENV
++#define CONFIG_CMD_RUN
++#define CONFIG_SUPPORT_EMMC_BOOT
++#define CONFIG_CMD_SETEXPR
++
++/*-----------------------------------------------------------------------
++ * USB
++ */
++#define iounmap(x)
++#define CONFIG_USB_DWC3
++#define CONFIG_USB_DWC3_UDC_REGS (void *) 0xf9100000
++#define CONFIG_USB_DWC3_UDC_REGS_END (void *) 0xf9100400
++
++
++#define CONFIG_USB_DWC3_GADGET
++#define CONFIG_USB_DEVICE
++#define CONFIG_USB_GADGET
++#define CONFIG_USB_GADGET_VBUS_DRAW 2
++#define CONFIG_USB_GADGET_DUALSPEED
++
++#define CONFIG_USBDOWNLOAD_GADGET
++#define CONFIG_G_DNL_MANUFACTURER "Intel"
++#define CONFIG_G_DNL_VENDOR_NUM 0x8087
++#define CONFIG_G_DNL_PRODUCT_NUM 0x0a99
++
++#define CONFIG_DFU_FUNCTION
++#define CONFIG_CMD_DFU
++#define CONFIG_DFU_TIMEOUT
++#define CONFIG_DFU_MMC
++#define CONFIG_DFU_RAM
++
++/*-----------------------------------------------------------------------
++ * SCU
++ */
++
++#define CONFIG_INTEL_SCU
++#define CONFIG_SCU_BASE_ADDR 0xff000000
++#define CONFIG_SCU_IPC_BASE 0xff009000
++#define CONFIG_SCU_I2C_BASE 0xff00d000
++#define CONFIG_CPU_CHIP 4
++#define CONFIG_X86_MRFLD
++
++
++#endif
+diff --git a/include/dfu.h b/include/dfu.h
+index 6c71ecb..d3fdf97 100644
+--- a/include/dfu.h
++++ b/include/dfu.h
+@@ -37,12 +37,17 @@ enum dfu_op {
+ DFU_OP_WRITE,
+ };
+
++#define DFU_NOT_SUPPORTED -1
++
+ struct mmc_internal_data {
+ /* RAW programming */
+ unsigned int lba_start;
+ unsigned int lba_size;
+ unsigned int lba_blk_size;
+
++ /* Partition access */
++ int partition_access;
++
+ /* FAT/EXT */
+ unsigned int dev;
+ unsigned int part;
+@@ -132,8 +137,10 @@ const char *dfu_get_layout(enum dfu_layout l);
+ struct dfu_entity *dfu_get_entity(int alt);
+ char *dfu_extract_token(char** e, int *n);
+ void dfu_trigger_reset(void);
++void dfu_trigger_enum_done(void);
+ int dfu_get_alt(char *name);
+ bool dfu_reset(void);
++bool dfu_enum_done(void);
+ int dfu_init_env_entities(char *interface, int dev);
+ unsigned char *dfu_get_buf(void);
+ unsigned char *dfu_free_buf(void);
+diff --git a/include/intel_scu_ipc.h b/include/intel_scu_ipc.h
+new file mode 100644
+index 0000000..a9cf406
+--- /dev/null
++++ b/include/intel_scu_ipc.h
+@@ -0,0 +1,69 @@
++#ifndef _INTEL_SCU_IPC_H_
++#define _INTEL_SCU_IPC_H_
++
++/* IPC defines the following message types */
++#define IPCMSG_WARM_RESET 0xF0
++#define IPCMSG_COLD_RESET 0xF1
++#define IPCMSG_SOFT_RESET 0xF2
++#define IPCMSG_COLD_BOOT 0xF3
++#define IPCMSG_GET_FW_REVISION 0xF4
++#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
++
++#define IPC_ERR_NONE 0
++#define IPC_ERR_CMD_NOT_SUPPORTED 1
++#define IPC_ERR_CMD_NOT_SERVICED 2
++#define IPC_ERR_UNABLE_TO_SERVICE 3
++#define IPC_ERR_CMD_INVALID 4
++#define IPC_ERR_CMD_FAILED 5
++#define IPC_ERR_EMSECURITY 6
++
++/* Command id associated with message IPCMSG_VRTC */
++#define IPC_CMD_VRTC_SETTIME 1 /* Set time */
++#define IPC_CMD_VRTC_SETALARM 2 /* Set alarm */
++#define IPC_CMD_VRTC_SYNC_RTC 3 /* Sync MSIC/PMIC RTC to VRTC */
++
++union ipc_ifwi_version {
++ u8 raw[16];
++ struct {
++ u16 ifwi_minor;
++ u8 ifwi_major;
++ u8 hardware_id;
++ u32 reserved[3];
++ } fw __attribute__((packed));
++} __attribute__((packed));
++
++/* Issue commands to the SCU with or without data */
++void intel_scu_ipc_send_command(u32 cmd);
++int intel_scu_ipc_check_status(void);
++int intel_scu_ipc_simple_command(int cmd, int sub);
++void intel_scu_ipc_lock(void);
++void intel_scu_ipc_unlock(void);
++int intel_scu_ipc_command(u32 cmd, u32 sub, u8 * in, u8 inlen,
++ u32 * out, u32 outlen);
++int intel_scu_ipc_raw_cmd(u32 cmd, u32 sub, u8 * in, u8 inlen,
++ u32 * out, u32 outlen, u32 dptr, u32 sptr);
++
++
++void ipc_data_writel(u32 data, u32 offset); /* Write ipc data */
++u32 ipc_read_status(void);
++u8 ipc_data_readb(u32 offset); /* Read ipc byte data */
++u32 ipc_data_readl(u32 offset); /* Read ipc u32 data */
++int intel_scu_ipc_command(u32 cmd, u32 sub, u8 * in, u8 inlen, u32 * out,
++ u32 outlen);
++int init_scu_ipc(void);
++
++enum intel_mid_cpu_type {
++ INTEL_CPU_CHIP_NOTMID = 0,
++ INTEL_MID_CPU_CHIP_LINCROFT,
++ INTEL_MID_CPU_CHIP_PENWELL,
++ INTEL_MID_CPU_CHIP_CLOVERVIEW,
++ INTEL_MID_CPU_CHIP_TANGIER,
++};
++
++static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
++{
++ return INTEL_MID_CPU_CHIP_TANGIER;
++}
++
++
++#endif //_INTEL_SCU_IPC_H_
+diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
+index a8a5763..118a736 100644
+--- a/include/linux/usb/gadget.h
++++ b/include/linux/usb/gadget.h
+@@ -20,6 +20,7 @@
+
+ #include
+ #include
++#include
+
+ struct usb_ep;
+
+@@ -95,6 +96,7 @@ struct usb_request {
+
+ int status;
+ unsigned actual;
++ unsigned stream_id;
+ };
+
+ /*-------------------------------------------------------------------------*/
+@@ -145,6 +147,8 @@ struct usb_ep {
+ const struct usb_ep_ops *ops;
+ struct list_head ep_list;
+ unsigned maxpacket:16;
++ unsigned max_streams:16;
++ unsigned maxburst:16;
+ };
+
+ /*-------------------------------------------------------------------------*/
+@@ -412,7 +416,6 @@ struct usb_gadget_ops {
+
+ struct device {
+ void *driver_data; /* data private to the driver */
+- void *device_data; /* data private to the device */
+ };
+
+ /**
+@@ -483,11 +486,6 @@ static inline void *get_gadget_data(struct usb_gadget *gadget)
+ return gadget->dev.driver_data;
+ }
+
+-static inline struct usb_gadget *dev_to_usb_gadget(struct device *dev)
+-{
+- return container_of(dev, struct usb_gadget, dev);
+-}
+-
+ /* iterates the non-control endpoints; 'tmp' is a struct usb_ep pointer */
+ #define gadget_for_each_ep(tmp, gadget) \
+ list_for_each_entry(tmp, &(gadget)->ep_list, ep_list)
+@@ -861,4 +859,9 @@ extern void usb_ep_autoconfig_reset(struct usb_gadget *);
+
+ extern int usb_gadget_handle_interrupts(void);
+
++extern int usb_gadget_init_udc(void);
++extern void usb_gadget_exit_udc(void);
++extern int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
++ int (*bind)(struct usb_gadget *));
++
+ #endif /* __LINUX_USB_GADGET_H */
+diff --git a/include/usb/fastboot.h b/include/usb/fastboot.h
+new file mode 100644
+index 0000000..e55149a
+--- /dev/null
++++ b/include/usb/fastboot.h
+@@ -0,0 +1,100 @@
++/*
++ * (C) Copyright 2008 - 2009
++ * Windriver,
++ * Tom Rix
++ *
++ * Copyright (c) 2011 Sebastian Andrzej Siewior
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * The logical naming of flash comes from the Android project
++ * Thse structures and functions that look like fastboot_flash_*
++ * They come from bootloader/legacy/include/boot/flash.h
++ *
++ * The boot_img_hdr structure and associated magic numbers also
++ * come from the Android project. They are from
++ * bootloader/legacy/include/boot/bootimg.h
++ *
++ * Here are their copyrights
++ *
++ * Copyright (C) 2008 The Android Open Source Project
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
++ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
++ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
++ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
++ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
++ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
++ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
++ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
++ * SUCH DAMAGE.
++ *
++ */
++
++#ifndef FASTBOOT_H
++#define FASTBOOT_H
++
++#include
++#include
++#include
++#include
++#include
++
++struct fastboot_config {
++
++ /*
++ * Transfer buffer for storing data sent by the client. It should be
++ * able to hold a kernel image and flash partitions. Care should be
++ * take so it does not overrun bootloader memory
++ */
++ unsigned char *transfer_buffer;
++
++ /* Size of the buffer mentioned above */
++ unsigned int transfer_buffer_size;
++};
++
++#define FB_STR_PRODUCT_IDX 1
++#define FB_STR_SERIAL_IDX 2
++#define FB_STR_CONFIG_IDX 3
++#define FB_STR_INTERFACE_IDX 4
++#define FB_STR_MANUFACTURER_IDX 5
++#define FB_STR_PROC_REV_IDX 6
++#define FB_STR_PROC_TYPE_IDX 7
++
++#if (CONFIG_CMD_FASTBOOT)
++
++int fastboot_init(void);
++void fastboot_shutdown(void);
++int fastboot_poll(void);
++
++int fastboot_board_init(struct fastboot_config *interface,
++ struct usb_gadget_strings **str);
++#endif
++#endif
+diff --git a/pft-config.xml b/pft-config.xml
+new file mode 100644
+index 0000000..885875f
+--- /dev/null
++++ b/pft-config.xml
+@@ -0,0 +1,28 @@
++
++
++ system
++ saltbay
++
++ 0x80000007
++
++
++
++ ifwi_saltbay_pr2.bin
++ 0003.008d
++
++
++ dnx_fwr_saltbay_pr2.bin
++ 0003.008d
++
++
++ dnx_osr_saltbay_pr2.bin
++ 0003.008d
++
++
++
++
++ u-boot.bin.osip
++ main-weekly-1115
++
++
++
+--
+1.7.9.5
+
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/u-boot-fw-utils_2014.04.bb b/device-software/meta-edison/recipes-bsp/u-boot/u-boot-fw-utils_2014.04.bb
new file mode 100644
index 0000000..0c2353c
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/u-boot-fw-utils_2014.04.bb
@@ -0,0 +1,28 @@
+DESCRIPTION = "U-boot bootloader fw_printenv/setenv utils"
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://Licenses/README;md5=025bf9f768cbcb1a165dbe1a110babfb"
+SECTION = "bootloader"
+
+require u-boot-internal.inc
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+SRC_URI += "file://fw_env.config"
+
+EXTRA_OEMAKE = 'CROSS_COMPILE=${TARGET_PREFIX} CC="${TARGET_PREFIX}gcc ${TOOLCHAIN_OPTIONS}"'
+
+do_compile () {
+ oe_runmake ${UBOOT_MACHINE}
+ oe_runmake env
+}
+
+do_install () {
+ install -d ${D}${sbindir}
+ install -m 755 ${S}/tools/env/fw_printenv_unstripped ${D}${sbindir}/fw_printenv
+ # This is not a typo, this tool checks the args[0] to change its behavior a-la-busybox
+ install -m 755 ${S}/tools/env/fw_printenv_unstripped ${D}${sbindir}/fw_setenv
+}
+
+FILES_${PN} = "${sbindir}/*"
+FILES_${PN} += "${sysconfdir}/fw_env.config"
+
+DEPENDS = "u-boot"
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/u-boot-internal.inc b/device-software/meta-edison/recipes-bsp/u-boot/u-boot-internal.inc
new file mode 100644
index 0000000..35698d7
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/u-boot-internal.inc
@@ -0,0 +1,10 @@
+PV = "2014.04-1"
+S = "${WORKDIR}/git"
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+SRC_URI = "git://git.denx.de/u-boot.git;branch=master"
+SRC_URI += "file://upstream_to_edison.patch"
+SRC_URI += "file://${MACHINE}.env"
+SRC_URI += "file://target_env/*.env"
+SRCREV = "dda0dbfc69f3d560c87f5be85f127ed862ea6721"
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/u-boot-osip.inc b/device-software/meta-edison/recipes-bsp/u-boot/u-boot-osip.inc
new file mode 100644
index 0000000..d05d440
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/u-boot-osip.inc
@@ -0,0 +1,208 @@
+OSIP_STARTING_LBA = "2048"
+OSIP_DESTINATION_POINTER = "17825792"
+OSIP_HANDOFF_POINTER = "17829888"
+
+# env is U-Boot primary environment where internal U-Boot variables are stored
+# this default generated binary environment, is embedded in a raw OSIP image
+# use by XFSTK tools to do the initial boot
+ENV_IMAGE = "${S}/env.bin"
+BASE_IMAGE = "${S}/u-boot.bin"
+UBOOT_OSIP_SUFFIX = "img"
+UBOOT_TMP_IMG = "${S}/u-boot.${UBOOT_OSIP_SUFFIX}.no-osip"
+UBOOT_IMG = "${S}/u-boot.${UBOOT_OSIP_SUFFIX}"
+UBOOT_OSIP_IMAGE = "u-boot-${MACHINE}-${PV}-${PR}.${UBOOT_OSIP_SUFFIX}"
+UBOOT_OSIP_BINARY = "u-boot.${UBOOT_OSIP_SUFFIX}"
+UBOOT_OSIP_SYMLINK = "u-boot-${MACHINE}.${UBOOT_OSIP_SUFFIX}"
+
+
+do_uboot_padding() {
+ # U-Boot.bin map
+ # 0x000000 - 0x001000 | padding with 0
+ # 0x001000 - 0x200000 | u-boot0
+ dd if=/dev/zero of=u-boot.padding bs=4096 count=1
+ cat u-boot.padding ${BASE_IMAGE} | dd of=u-boot.bin.padded
+
+ # Align u-boot.bin to 4K for dfu
+ filesize=$(stat -c %s u-boot.bin.padded)
+ alignment=$(echo "4096 - (${filesize} % 4096)" | bc)
+ if [ ${alignment} -ne 0 ];
+ then
+ dd if=/dev/zero of=u-boot.bin.padded bs=1 count=${alignment} conv=notrunc seek=${filesize}
+ fi
+
+ cp u-boot.bin.padded ${BASE_IMAGE}
+}
+
+do_uboot_uboot_env_mkimage() {
+
+ # U-Boot.img map
+ # 0x000000 - 0x001000 | padding with 0
+ # 0x001000 - 0x200000 | u-boot0
+ # 0x200000 - 0x300000 | primary environment
+ # 0x300000 - 0x500000 | reserved
+ # 0x500000 - 0x600000 | secondary environment
+
+ # U-Boot.img on eMMC in LBA (LBA size: 512 bytes)
+ # | description | OSII | GPT label
+ # 0x000000 - 0x000001 | MBR + OSIP | - | -
+ # 0x000001 - 0x000022 | GPT | - | -
+ # 0x000022 - 0x000800 | padding with 0 (alignment) | - | -
+ # 0x000800 - 0x001800 | u-boot0 | 1 | u-boot0
+ # 0x001800 - 0x002600 | primary environment | - | u-boot-env0
+ # 0x002600 - 0x003600 | u-boot1 | 2 | u-boot1
+ # 0x003600 - 0x004400 | secondary environment | - | u-boot-env1
+
+
+ # Fill U-Boot.img with 0
+ dd if=/dev/zero of=${UBOOT_TMP_IMG} bs=6M count=1
+ # copy u-boot.bin in u-boot.img (u-boot0)
+ dd if=${BASE_IMAGE} of=${UBOOT_TMP_IMG} bs=1M conv=notrunc
+ # copy (offset 2M) u-boot_env0.bin in u-boot.img (u-boot0)
+ dd if=${ENV_IMAGE} of=${UBOOT_TMP_IMG} bs=1M conv=notrunc seek=2
+ # copy (offset 5M) u-boot_env1.bin in u-boot.img (u-boot0)
+ dd if=${ENV_IMAGE} of=${UBOOT_TMP_IMG} bs=1M conv=notrunc seek=5
+}
+
+python do_osip_mkimage() {
+ #
+ # Stitch an image to create an OSIP image (OS Image Profile).
+ # This script currently supports only one OSII (OS Image Identifier)
+ # If more is necessary, it will need to be adjusted.
+ #
+ # This is the C struct for one OSII (size = 24 bytes)
+ # struct OSII { //os image identifier
+ # uint16_t os_rev_minor;
+ # uint16_t os_rev_major;
+ # uint32_t logical_start_block; //units defined by get_block_size() if
+ # //reading/writing to/from nand, units of
+ # //512 bytes if cracking a stitched image
+ # uint32_t ddr_load_address;
+ # uint32_t entry_point;
+ # uint32_t size_of_os_image; //units defined by get_page_size() if
+ # //reading/writing to/from nand, units of
+ # //512 bytes if cracking a stitched image
+ # uint8_t attribute;
+ # uint8_t reserved[3];
+ # };
+
+ # This is what a full OSIP header contains
+ # Its size is 512 bytes
+ # Offset Size (bytes) Description
+ # 0x000 4 OSIP Signature "$OS$"
+ # 0x004 1 Reserved
+ # 0x005 1 Header minor revision
+ # 0x006 1 Header major revision
+ # 0x007 1 Header checksum
+ # 0x008 1 Number of pointers
+ # 0x009 1 Number of images
+ # 0x00a 2 Header size
+ # 0x00c 20 Reserved
+ # 0x020 24 1st bootable image descriptor (OSII)
+ # 0x038 24 2nd bootable image descriptor (OSII)
+ # ... ... ...
+ # 0x170 24 15th bootable image descriptor (OSII)
+ # 0x188 48 Not used
+ # 0x1B8 4 Disk signature
+ # 0x1BC 2 Null (0x0000)
+ # 0x1BE 16 1st primary partition descriptor
+ # 0x1CE 16 2nd primary partition descriptor
+ # 0x1DE 16 3rd primary partition descriptor
+ # 0x1EE 16 4th primary partition descriptor
+ # 0x1FE 1 0x55
+ # 0x1FF 1 0xaa
+
+ import os
+ import sys
+ import argparse
+ import struct
+
+ # As only a small portion of the OSIP header needs to be changed
+ # we simply store a full binary copy and we'll change just the
+ # necessary values in it
+ OSIP_HEADER_HEX_DATA = \
+ '244f532400000121010138000000000000000000000000000000000000' \
+ '00000000000000220000000000100100101001380100000f000000ffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff' \
+ 'ffffffffff00000000000000000000ee0000000100000000e0a3030000' \
+ '0000000000000000000000000000000000000000000000000000000000' \
+ '000000000000000000000000000000000055aa'
+
+ def main():
+ input_file = "${UBOOT_TMP_IMG}"
+ output_file = "${UBOOT_IMG}"
+ handoff_pointer = ${OSIP_HANDOFF_POINTER}
+ destination_pointer = ${OSIP_DESTINATION_POINTER}
+ starting_lba = ${OSIP_STARTING_LBA}
+
+ in_file_data = open(input_file, 'rb').read()
+
+ out_file = open(output_file, 'wb')
+
+ # Write OSIP header data
+ osip_header_data = bytearray(OSIP_HEADER_HEX_DATA.decode('hex'))
+
+ # Override some values
+
+ # Overrides starting LBA of imge in eMMC
+ starting_lba_packed = struct.pack("I", starting_lba)
+ osip_header_data[0x24:0x27+1]=starting_lba_packed
+
+ # Overrides destination pointer to image in DDR
+ destination_pointer_packed = struct.pack("I", destination_pointer)
+ osip_header_data[0x28:0x2B+1]=destination_pointer_packed
+
+ # Overrides pointer to handoff entry point in image
+ handoff_pointer_packed = struct.pack("I", handoff_pointer)
+ osip_header_data[0x2C:0x2F+1]=handoff_pointer_packed
+
+ # The file needs to be padded to be multiple of 512 bytes
+
+ # Overrides passed image size (in unit of 512 bytes blocks)
+ padding_len_packed_block = struct.pack("I", ( (6*1024*1024) / 512))
+ osip_header_data[0x30:0x33+1]=padding_len_packed_block
+
+ # Compute XOR checksum
+ osip_header_size = 1*0x18+0x20 # 24 bytes per OSII + 32 bytes header
+ osip_header_data[0x07]=0
+ crc = osip_header_data[0]
+ for i in range(1, osip_header_size):
+ crc ^= osip_header_data[i]
+ osip_header_data[0x07]=crc
+
+ out_file.write(osip_header_data)
+
+ # Write image content
+ out_file.write(in_file_data)
+
+ out_file.close()
+
+ return 0
+
+ main()
+}
+
+do_deploy_append() {
+ install -d ${DEPLOYDIR}
+ install ${UBOOT_IMG} ${DEPLOYDIR}/${UBOOT_OSIP_IMAGE}
+
+ cd ${DEPLOYDIR}
+ rm -f ${UBOOT_IMG} ${UBOOT_OSIP_SYMLINK}
+ ln -sf ${UBOOT_OSIP_IMAGE} ${UBOOT_OSIP_SYMLINK}
+ ln -sf ${UBOOT_OSIP_IMAGE} ${UBOOT_OSIP_BINARY}
+}
+
+addtask uboot_padding before do_environment_mkimage before do_deploy after do_compile
+addtask uboot_uboot_env_mkimage before do_osip_mkimage after do_environment_mkimage
+addtask osip_mkimage before do_deploy after do_uboot_uboot_env_mkimage
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/u-boot-target-env.inc b/device-software/meta-edison/recipes-bsp/u-boot/u-boot-target-env.inc
new file mode 100644
index 0000000..6dee3d1
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/u-boot-target-env.inc
@@ -0,0 +1,93 @@
+# Handle severals environments generation for u-boot
+# and link the default one for Ifwi to u-boot-osip recipe
+
+#Env binary size
+ENV_SIZE = "0x10000"
+
+#Env base Name
+ENV_BASE_NAME = "${MACHINE}"
+# Env base file correspond to common part of all environment
+ENV_BASE_FILE = "${WORKDIR}/${ENV_BASE_NAME}.env"
+
+# Env directory is where target variant files are stored
+ENV_DIR = "${WORKDIR}/target_env"
+# Env composed is directory where target env are composed
+# by concatening of base environment file and variant files
+# pattern name is applied the resulting files: base-variant.env
+ENV_COMPOSED_DIR = "${WORKDIR}/target_composed"
+# Env bin is directory where target env are store in binary form
+# filename follows pattern name above : base-variant.bin
+ENV_BIN_DIR = "${WORKDIR}/target_env_bin"
+
+# Env deploy dir is the name of directory where binary envs will be deployed
+ENV_DEPLOY_DIR="u-boot-envs"
+
+# Env deploy src dir is the name of directory where txt envs will be deployed
+ENV_SRC_DEPLOY_DIR="u-boot-envs-src"
+
+# Env target to use for IFWI stitching process
+ENV_IFWI_TARGET_NAME="ifwi"
+# Env image is U-Boot primary environment (where internal U-Boot variables are stored)
+# The same vairiable is also defined in u-boot-osip recip in charge of doing stitching
+# process for IFWI
+ENV_IMAGE = "${S}/env.bin"
+
+do_build_mkimage_tool () {
+ HOSTCC="${CC}" HOSTLD="${LD}" HOSTLDFLAGS="${LDFLAGS}" HOSTSTRIP=true oe_runmake tools
+}
+
+python do_environment_mkimage() {
+ import subprocess
+ import shutil
+ # list env variant target files
+ target_root_dir = d.getVar('ENV_DIR',True)
+ env_files = os.listdir(target_root_dir )
+ # builds absolute paths
+ env_files = [ os.path.join(target_root_dir,f) for f in env_files]
+
+ env_bin_dir = d.getVar("ENV_BIN_DIR",True)
+ # cleans if it exists env_bin directory
+ shutil.rmtree(env_bin_dir, ignore_errors=True)
+ # create env bin directory
+ os.mkdir(env_bin_dir)
+ # if a previous env image used for osip process exists delete it
+ env_image = d.getVar('ENV_IMAGE',True)
+ try:
+ os.unlink(env_image)
+ except OSError: pass
+ print 'Building binary environments in : %s' % env_bin_dir
+ # iterate targets list to build binary environment files
+ for target_env in env_files :
+ # get only filename without path and extension
+ target_filename = os.path.splitext(os.path.basename(target_env))[0]
+ # build output file path with ext
+ target_bin = os.path.join(env_bin_dir,
+ d.getVar('ENV_BASE_NAME',True) + '-' + target_filename + '.bin')
+ # generated mkenvimage tool command line
+ cmd_mkimg ='cat %s %s | grep -v -E "^$|^\#" |' \
+ ' ./tools/mkenvimage -s %s -r -o %s -' \
+ % ( d.getVar('ENV_BASE_FILE',True),target_env,
+ d.getVar("ENV_SIZE",True), target_bin)
+ print 'Building binary for %s target:' % (target_filename)
+ print '%s' % cmd_mkimg
+ # execute shell command
+ ret = subprocess.call(cmd_mkimg, shell=True)
+ if ret: return ret
+ if d.getVar('ENV_IFWI_TARGET_NAME',True) in target_bin :
+ # create a symbolic link on default binary file env file to
+ # avoid modifying to much osip part
+ print 'Create for IFWI stitching symlink %s to %s' % (env_image, target_bin)
+ os.symlink(target_bin, env_image)
+ return 0
+}
+
+do_deploy_append() {
+ install -d ${DEPLOYDIR}
+ # deploy binary U-boot environments
+ echo "Deploying U-boot Environments binary files in ${DEPLOYDIR}/${ENV_DEPLOY_DIR}"
+ install -d ${DEPLOYDIR}/${ENV_DEPLOY_DIR}
+ cp ${ENV_BIN_DIR}/*.bin ${DEPLOYDIR}/${ENV_DEPLOY_DIR}
+}
+
+addtask build_mkimage_tool after do_compile before do_environment_mkimage
+addtask environment_mkimage after do_build_mkimage_tool before do_deploy
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/u-boot-tools_2014.04.bb b/device-software/meta-edison/recipes-bsp/u-boot/u-boot-tools_2014.04.bb
new file mode 100644
index 0000000..ebbef01
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/u-boot-tools_2014.04.bb
@@ -0,0 +1,22 @@
+DESCRIPTION = "U-boot bootloader mkimage tool"
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://Licenses/README;md5=025bf9f768cbcb1a165dbe1a110babfb"
+SECTION = "bootloader"
+
+require u-boot-internal.inc
+
+EXTRA_OEMAKE = 'HOSTCC="${CC}" HOSTLD="${LD}" HOSTLDFLAGS="${LDFLAGS}" HOSTSTRIP=true'
+
+do_compile () {
+ oe_runmake tools
+}
+
+do_install () {
+ install -d ${D}${bindir}
+ install -m 0755 tools/mkimage ${D}${bindir}/uboot-mkimage
+ install -m 0755 tools/mkenvimage ${D}${bindir}/uboot-mkenvimage
+ ln -sf uboot-mkimage ${D}${bindir}/mkimage
+ ln -sf uboot-mkenvimage ${D}${bindir}/mkenvimage
+}
+
+BBCLASSEXTEND = "native nativesdk"
diff --git a/device-software/meta-edison/recipes-bsp/u-boot/u-boot_2014.04.bb b/device-software/meta-edison/recipes-bsp/u-boot/u-boot_2014.04.bb
new file mode 100644
index 0000000..3785576
--- /dev/null
+++ b/device-software/meta-edison/recipes-bsp/u-boot/u-boot_2014.04.bb
@@ -0,0 +1,7 @@
+require u-boot-internal.inc
+require recipes-bsp/u-boot/u-boot.inc
+require u-boot-target-env.inc
+require u-boot-osip.inc
+
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://Licenses/README;md5=025bf9f768cbcb1a165dbe1a110babfb"
diff --git a/device-software/meta-edison/recipes-kernel/linux/files/defconfig b/device-software/meta-edison/recipes-kernel/linux/files/defconfig
index 7f3e626..b1ed708 100644
--- a/device-software/meta-edison/recipes-kernel/linux/files/defconfig
+++ b/device-software/meta-edison/recipes-kernel/linux/files/defconfig
@@ -153,7 +153,7 @@ CONFIG_NAMESPACES=y
# CONFIG_IPC_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
-# CONFIG_NET_NS is not set
+CONFIG_NET_NS=y
CONFIG_UIDGID_CONVERTED=y
# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set
CONFIG_SCHED_AUTOGROUP=y
@@ -1544,7 +1544,7 @@ CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_DESIGNWARE_CORE_FORK=y
CONFIG_I2C_DESIGNWARE_PCI_FORK=y
# CONFIG_I2C_DESIGNWARE_PLATFORM_FORK is not set
-# CONFIG_I2C_DW_SPEED_MODE_DEBUG is not set
+CONFIG_I2C_DW_SPEED_MODE_DEBUG=y
CONFIG_I2C_PMIC=y
# CONFIG_I2C_DESIGNWARE_PCI is not set
# CONFIG_I2C_EG20T is not set
@@ -1719,6 +1719,7 @@ CONFIG_BATTERY_MAX17042=y
# CONFIG_POWER_RESET is not set
# CONFIG_POWER_AVS is not set
CONFIG_HWMON=y
+CONFIG_INTEL_MCU=y
# CONFIG_HWMON_VID is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
@@ -2039,13 +2040,80 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_V4L2=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_VMALLOC=m
# CONFIG_VIDEO_V4L2_INT_DEVICE is not set
# CONFIG_TTPCI_EEPROM is not set
#
# Media drivers
#
-# CONFIG_MEDIA_USB_SUPPORT is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+
+#
+# Webcam devices
+#
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_JL2005BCD is not set
+# CONFIG_USB_GSPCA_KINECT is not set
+# CONFIG_USB_GSPCA_KONICA is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_NW80X is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SE401 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_SQ930X is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TOPRO is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_USB_SN9C102 is not set
+
+#
+# Webcam, TV (analog/digital) USB devices
+#
+# CONFIG_VIDEO_EM28XX is not set
# CONFIG_MEDIA_PCI_SUPPORT is not set
# CONFIG_V4L_PLATFORM_DRIVERS is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
@@ -2314,7 +2382,8 @@ CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
-CONFIG_SND_COMPRESS_OFFLOAD=y
+# CONFIG_SND_COMPRESS_OFFLOAD is not set
+# CONFIG_SND_EFFECTS_OFFLOAD is not set
CONFIG_SND_JACK=y
CONFIG_SND_SEQUENCER=y
# CONFIG_SND_SEQ_DUMMY is not set
@@ -2344,7 +2413,7 @@ CONFIG_SND_ALOOP=y
# CONFIG_SND_PCI is not set
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
+CONFIG_SND_USB_AUDIO=y
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_USX2Y is not set
# CONFIG_SND_USB_CAIAQ is not set
@@ -2353,8 +2422,15 @@ CONFIG_SND_USB=y
CONFIG_SND_SOC=y
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_MFLD_MACHINE is not set
+CONFIG_SND_INTEL_SST=y
+CONFIG_SND_MRFLD_MACHINE=y
+CONFIG_SND_SST_PLATFORM=y
+CONFIG_SST_MRFLD_DPCM=y
+CONFIG_SND_SST_MACHINE=y
CONFIG_SND_SOC_I2C_AND_SPI=y
# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM_HUBS=y
+CONFIG_SND_SOC_WM8994=y
# CONFIG_SND_SIMPLE_CARD is not set
# CONFIG_SOUND_PRIME is not set
@@ -2672,7 +2748,7 @@ CONFIG_USB_U_SERIAL=m
# CONFIG_USB_G_ACM_MS is not set
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
-# CONFIG_USB_G_MULTI_CDC is not set
+CONFIG_USB_G_MULTI_CDC=y
# CONFIG_USB_G_HID is not set
# CONFIG_USB_G_DBGP is not set
# CONFIG_USB_G_WEBCAM is not set
@@ -3030,6 +3106,7 @@ CONFIG_INTEL_MID_POWER_BUTTON=y
# CONFIG_IBM_RTL is not set
# CONFIG_SAMSUNG_LAPTOP is not set
CONFIG_INTEL_SCU_FLIS=y
+CONFIG_INTEL_PSH_IPC=y
#
# Hardware Spinlock drivers
@@ -3296,7 +3373,22 @@ CONFIG_PSTORE_RAM=y
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
# CONFIG_F2FS_FS is not set
-# CONFIG_AUFS_FS is not set
+CONFIG_AUFS_FS=m
+CONFIG_AUFS_BRANCH_MAX_127=y
+# CONFIG_AUFS_BRANCH_MAX_511 is not set
+# CONFIG_AUFS_BRANCH_MAX_1023 is not set
+# CONFIG_AUFS_BRANCH_MAX_32767 is not set
+CONFIG_AUFS_SBILIST=y
+# CONFIG_AUFS_HNOTIFY is not set
+# CONFIG_AUFS_EXPORT is not set
+# CONFIG_AUFS_RDU is not set
+# CONFIG_AUFS_PROC_MAP is not set
+# CONFIG_AUFS_SP_IATTR is not set
+# CONFIG_AUFS_SHWH is not set
+# CONFIG_AUFS_BR_RAMFS is not set
+# CONFIG_AUFS_BR_FUSE is not set
+CONFIG_AUFS_BDEV_LOOP=y
+# CONFIG_AUFS_DEBUG is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
diff --git a/device-software/meta-edison/recipes-kernel/linux/files/upstream_to_edison.patch b/device-software/meta-edison/recipes-kernel/linux/files/upstream_to_edison.patch
index 6207981..14ed5ec 100644
--- a/device-software/meta-edison/recipes-kernel/linux/files/upstream_to_edison.patch
+++ b/device-software/meta-edison/recipes-kernel/linux/files/upstream_to_edison.patch
@@ -1,16 +1,16 @@
-From 225d200472d9c9af2117c8085b3682bcdd4dbeae Mon Sep 17 00:00:00 2001
+From 0146a06734d5329d58c801e99f1bef8b9c373036 Mon Sep 17 00:00:00 2001
From: Jenkins
-Date: Tue, 14 Oct 2014 14:57:16 +0200
+Date: Fri, 30 Jan 2015 14:24:05 +0100
Subject: [PATCH] Squashed all commits from upstream to Edison
-Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
+Change-Id: Id0e266dc44eb4f56c9e1970345eba7a1ff2b3baa
---
Documentation/kernel-parameters.txt | 6 +-
arch/x86/Kconfig | 62 +-
arch/x86/Kconfig.cpu | 19 +-
arch/x86/Makefile | 2 +
arch/x86/Makefile_32.cpu | 2 +
- arch/x86/configs/i386_edison_defconfig | 3768 +++++++++++++
+ arch/x86/configs/i386_edison_defconfig | 3860 +++++++++++++
arch/x86/configs/i386_mrfl_defconfig | 3980 ++++++++++++++
arch/x86/include/asm/apb_timer.h | 1 +
arch/x86/include/asm/bcm_bt_lpm.h | 46 +
@@ -29,15 +29,21 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
arch/x86/include/asm/intel_mid_thermal.h | 77 +
arch/x86/include/asm/intel_mid_vrtc.h | 9 +
arch/x86/include/asm/intel_mip.h | 32 +
+ arch/x86/include/asm/intel_psh_ipc.h | 35 +
arch/x86/include/asm/intel_scu_flis.h | 326 ++
arch/x86/include/asm/intel_scu_ipc.h | 105 +-
arch/x86/include/asm/intel_scu_ipcutil.h | 135 +
arch/x86/include/asm/intel_scu_pmic.h | 16 +
arch/x86/include/asm/intel_soc_debug.h | 43 +
+ arch/x86/include/asm/intel_sst_mrfld.h | 44 +
arch/x86/include/asm/module.h | 2 +-
arch/x86/include/asm/mrst-vrtc.h | 9 -
arch/x86/include/asm/mrst.h | 81 -
arch/x86/include/asm/mwait.h | 6 +
+ arch/x86/include/asm/platform_byt_audio.h | 49 +
+ arch/x86/include/asm/platform_mrfld_audio.h | 25 +
+ arch/x86/include/asm/platform_sst.h | 132 +
+ arch/x86/include/asm/platform_sst_audio.h | 161 +
arch/x86/include/asm/pmic_pdata.h | 45 +
arch/x86/include/asm/required-features.h | 2 +-
arch/x86/include/asm/scu_ipc_rpmsg.h | 19 +
@@ -58,11 +64,12 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
arch/x86/pci/mrst.c | 21 +-
arch/x86/platform/Makefile | 2 +-
arch/x86/platform/intel-mid/Makefile | 27 +
- arch/x86/platform/intel-mid/board.c | 160 +
- arch/x86/platform/intel-mid/device_libs/Makefile | 64 +
+ arch/x86/platform/intel-mid/board.c | 166 +
+ arch/x86/platform/intel-mid/device_libs/Makefile | 66 +
.../platform/intel-mid/device_libs/pci/Makefile | 6 +
.../intel-mid/device_libs/pci/platform_sdhci_pci.c | 588 ++
.../intel-mid/device_libs/pci/platform_sdhci_pci.h | 30 +
+ .../intel-mid/device_libs/pci/platform_sst_pci.c | 229 +
.../intel-mid/device_libs/pci/platform_usb_otg.c | 93 +
.../intel-mid/device_libs/platform_ads7955.c | 37 +
.../intel-mid/device_libs/platform_ads7955.h | 20 +
@@ -99,6 +106,7 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
.../device_libs/platform_mrfl_regulator.c | 125 +
.../intel-mid/device_libs/platform_mrfl_thermal.c | 133 +
.../intel-mid/device_libs/platform_mrfl_thermal.h | 26 +
+ .../intel-mid/device_libs/platform_mrfld_audio.c | 130 +
.../platform/intel-mid/device_libs/platform_msic.c | 92 +
.../platform/intel-mid/device_libs/platform_msic.h | 21 +
.../intel-mid/device_libs/platform_msic_adc.c | 56 +
@@ -126,6 +134,7 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
.../intel-mid/device_libs/platform_soc_thermal.h | 20 +
.../intel-mid/device_libs/platform_spidev.c | 73 +
.../intel-mid/device_libs/platform_spidev.h | 20 +
+ .../intel-mid/device_libs/platform_sst_audio.c | 152 +
.../intel-mid/device_libs/platform_tc35876x.c | 26 +
.../intel-mid/device_libs/platform_tc35876x.h | 16 +
.../intel-mid/device_libs/platform_tca6416.c | 45 +
@@ -134,12 +143,14 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
.../platform/intel-mid/device_libs/platform_wifi.h | 21 +
.../intel-mid/device_libs/platform_wl12xx.c | 182 +
.../intel-mid/device_libs/platform_wl12xx.h | 21 +
+ .../intel-mid/device_libs/platform_wm8994.c | 221 +
+ .../intel-mid/device_libs/platform_wm8994.h | 5 +
.../platform/intel-mid/early_printk_intel_mid.c | 637 +++
arch/x86/platform/intel-mid/intel-mid.c | 239 +
arch/x86/platform/intel-mid/intel_mid_pcihelpers.c | 105 +
arch/x86/platform/intel-mid/intel_mid_scu.c | 92 +
arch/x86/platform/intel-mid/intel_mid_scu.h | 15 +
- arch/x86/platform/intel-mid/intel_mid_sfi.c | 588 ++
+ arch/x86/platform/intel-mid/intel_mid_sfi.c | 608 ++
arch/x86/platform/intel-mid/intel_mid_vrtc.c | 169 +
arch/x86/platform/intel-mid/intel_mid_weak_decls.h | 22 +
arch/x86/platform/intel-mid/intel_soc_clv.c | 146 +
@@ -172,9 +183,9 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
drivers/cpufreq/sfi-cpufreq.c | 581 ++
drivers/cpufreq/sfi-cpufreq.h | 65 +
drivers/dma/Makefile | 2 +-
- drivers/dma/intel_mid_dma.c | 1278 +++--
- drivers/dma/intel_mid_dma_acpi.c | 177 +
- drivers/dma/intel_mid_dma_regs.h | 164 +-
+ drivers/dma/intel_mid_dma.c | 1280 +++--
+ drivers/dma/intel_mid_dma_acpi.c | 192 +
+ drivers/dma/intel_mid_dma_regs.h | 168 +-
drivers/gpio/Kconfig | 11 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-langwell.c | 1061 +++-
@@ -185,9 +196,11 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
drivers/gpu/drm/gma500/mdfld_dsi_output.h | 2 +-
drivers/gpu/drm/gma500/oaktrail_device.c | 2 +-
drivers/gpu/drm/gma500/oaktrail_lvds.c | 2 +-
- drivers/hwmon/Kconfig | 16 +
- drivers/hwmon/Makefile | 1 +
+ drivers/hwmon/Kconfig | 25 +
+ drivers/hwmon/Makefile | 2 +
drivers/hwmon/coretemp.c | 362 +-
+ drivers/hwmon/intel_mcu_common.c | 700 +++
+ drivers/hwmon/intel_mcu_common.h | 79 +
drivers/hwmon/intel_mid_gpadc.c | 1212 ++++
drivers/i2c/busses/Kconfig | 46 +
drivers/i2c/busses/Makefile | 8 +
@@ -215,30 +228,31 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
drivers/misc/pti.c | 95 +-
drivers/misc/stm.c | 470 ++
drivers/misc/stm.h | 114 +
- drivers/mmc/card/block.c | 6 +
+ drivers/mmc/card/block.c | 194 +-
drivers/mmc/card/queue.c | 3 +-
drivers/mmc/card/queue.h | 1 +
drivers/mmc/core/Makefile | 2 +-
drivers/mmc/core/bus.c | 3 +-
drivers/mmc/core/core.c | 25 +-
drivers/mmc/core/debugfs.c | 3 +
- drivers/mmc/core/mmc.c | 161 +-
- drivers/mmc/core/mmc_ops.c | 4 +-
+ drivers/mmc/core/mmc.c | 177 +-
+ drivers/mmc/core/mmc_ops.c | 416 +-
drivers/mmc/core/mmc_panic_ops.c | 837 +++
drivers/mmc/core/sdio_cis.c | 129 +-
drivers/mmc/host/sdhci-pci.c | 819 ++-
- drivers/mmc/host/sdhci.c | 1452 ++++-
+ drivers/mmc/host/sdhci.c | 1454 ++++-
drivers/mmc/host/sdhci.h | 13 +-
drivers/net/wireless/Kconfig | 10 +
drivers/pci/Makefile | 1 +
drivers/pci/pci-atom_soc.c | 78 +
drivers/pci/pci.c | 5 +-
drivers/pci/quirks.c | 6 +-
- drivers/platform/x86/Kconfig | 23 +
- drivers/platform/x86/Makefile | 4 +-
+ drivers/platform/x86/Kconfig | 40 +
+ drivers/platform/x86/Makefile | 6 +-
drivers/platform/x86/intel_mid_powerbtn.c | 252 +-
drivers/platform/x86/intel_mid_thermal.c | 574 --
drivers/platform/x86/intel_pmic_gpio.c | 2 +-
+ drivers/platform/x86/intel_psh_ipc.c | 637 +++
drivers/platform/x86/intel_scu_flis.c | 747 +++
drivers/platform/x86/intel_scu_fw_update.c | 1087 ++++
drivers/platform/x86/intel_scu_ipc.c | 636 +--
@@ -260,7 +274,7 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
drivers/pwm/Kconfig | 13 +
drivers/pwm/Makefile | 2 +
drivers/pwm/core.c | 25 +-
- drivers/pwm/pwm-intel-mid.c | 405 ++
+ drivers/pwm/pwm-intel-mid.c | 404 ++
drivers/pwm/sysfs.c | 353 ++
drivers/regulator/Kconfig | 6 +-
drivers/regulator/Makefile | 2 +
@@ -269,7 +283,7 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
drivers/remoteproc/Makefile | 1 +
drivers/remoteproc/intel_mid_rproc_core.c | 269 +
drivers/remoteproc/intel_mid_rproc_core.h | 82 +
- drivers/remoteproc/intel_mid_rproc_scu.c | 438 ++
+ drivers/remoteproc/intel_mid_rproc_scu.c | 441 ++
drivers/rpmsg/Kconfig | 9 +
drivers/rpmsg/Makefile | 1 +
drivers/rpmsg/intel_mid_rpmsg.c | 446 ++
@@ -277,7 +291,7 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
drivers/rtc/rtc-mrst.c | 296 +-
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1 +
- drivers/spi/intel_mid_ssp_spi.c | 1751 ++++++
+ drivers/spi/intel_mid_ssp_spi.c | 1787 ++++++
drivers/spi/spi-dw-mid.c | 133 +-
drivers/spi/spi-dw-pci.c | 102 +-
drivers/spi/spi-dw.c | 151 +-
@@ -346,15 +360,17 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
include/linux/irqdesc.h | 7 +
include/linux/lnw_gpio.h | 14 +
include/linux/mfd/intel_msic.h | 42 +
- include/linux/mmc/card.h | 5 +
- include/linux/mmc/core.h | 1 +
+ include/linux/mfd/wm8994/pdata.h | 19 +
+ include/linux/mfd/wm8994/registers.h | 8 +
+ include/linux/mmc/card.h | 11 +
+ include/linux/mmc/core.h | 35 +
include/linux/mmc/host.h | 64 +
include/linux/mmc/mmc.h | 5 +
include/linux/mmc/sdhci-pci-data.h | 16 +
include/linux/mmc/sdhci.h | 52 +
include/linux/mmc/sdio_ids.h | 2 +
include/linux/panic_gbuffer.h | 37 +
- include/linux/pci_ids.h | 13 +
+ include/linux/pci_ids.h | 14 +
include/linux/platform_data/intel_mid_remoteproc.h | 119 +
include/linux/platform_data/ti-ads7955.h | 21 +
include/linux/power/battery_id.h | 78 +
@@ -380,7 +396,21 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
include/linux/usb/phy.h | 14 +
include/linux/wl12xx.h | 5 +
include/linux/wlan_plat.h | 29 +
+ include/net/bluetooth/hci_core.h | 2 +
+ include/net/bluetooth/l2cap.h | 8 +-
+ include/sound/compress_driver.h | 15 +
+ include/sound/core.h | 5 +
+ include/sound/effect_driver.h | 63 +
+ include/sound/intel_sst_ioctl.h | 63 +
+ include/sound/pcm.h | 1 +
+ include/sound/soc-dai.h | 4 +-
+ include/sound/soc-dapm.h | 2 +
+ include/sound/soc-dpcm.h | 22 +
+ include/sound/soc.h | 35 +
+ include/uapi/linux/mmc/ioctl.h | 13 +
include/uapi/linux/usb/ch9.h | 1 +
+ include/uapi/sound/compress_offload.h | 8 +-
+ include/uapi/sound/effect_offload.h | 62 +
init/main.c | 2 +
kernel/cgroup.c | 6 +-
kernel/irq/chip.c | 1 +
@@ -388,8 +418,66 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
kernel/power/process.c | 2 +
kernel/printk.c | 18 +-
kernel/trace/trace.c | 5 +-
+ net/bluetooth/l2cap_core.c | 20 +-
+ net/bluetooth/l2cap_sock.c | 5 +-
+ sound/core/Kconfig | 3 +
+ sound/core/Makefile | 2 +
+ sound/core/compress_offload.c | 123 +-
+ sound/core/effects_offload.c | 307 ++
+ sound/soc/Kconfig | 2 +-
+ sound/soc/Makefile | 2 +-
sound/soc/codecs/sn95031.c | 2 +-
- 384 files changed, 83928 insertions(+), 6468 deletions(-)
+ sound/soc/codecs/wm8994.c | 491 +-
+ sound/soc/codecs/wm8994.h | 14 +
+ sound/soc/codecs/wm_hubs.c | 20 +-
+ sound/soc/intel/Kconfig | 58 +
+ sound/soc/intel/Makefile | 22 +
+ sound/soc/intel/board/Makefile | 14 +
+ sound/soc/intel/board/merr_dpcm_dummy.c | 233 +
+ sound/soc/intel/board/merr_dpcm_wm8958.c | 932 ++++
+ sound/soc/intel/board/merr_saltbay_wm8958.c | 887 +++
+ sound/soc/intel/compress.c | 254 +
+ sound/soc/intel/effects.c | 405 ++
+ sound/soc/intel/pcm.c | 1021 ++++
+ sound/soc/intel/platform-libs/controls_v1.c | 184 +
+ sound/soc/intel/platform-libs/controls_v2.c | 1770 ++++++
+ sound/soc/intel/platform-libs/controls_v2.h | 708 +++
+ sound/soc/intel/platform-libs/controls_v2_dpcm.c | 1803 ++++++
+ sound/soc/intel/platform-libs/ipc_lib.h | 33 +
+ sound/soc/intel/platform-libs/ipc_lib_v2.c | 109 +
+ sound/soc/intel/platform-libs/sst_widgets.h | 337 ++
+ sound/soc/intel/platform_ipc_v2.h | 693 +++
+ sound/soc/intel/ssp/Makefile | 5 +
+ sound/soc/intel/ssp/mid_ssp.c | 1436 +++++
+ sound/soc/intel/ssp/mid_ssp.h | 124 +
+ sound/soc/intel/sst/Makefile | 13 +
+ sound/soc/intel/sst/sst.c | 1255 +++++
+ sound/soc/intel/sst/sst.h | 932 ++++
+ sound/soc/intel/sst/sst_acpi.c | 669 +++
+ sound/soc/intel/sst/sst_app_compat_interface.c | 85 +
+ sound/soc/intel/sst/sst_app_interface.c | 342 ++
+ sound/soc/intel/sst/sst_debug.c | 1328 +++++
+ sound/soc/intel/sst/sst_drv_interface.c | 1111 ++++
+ sound/soc/intel/sst/sst_dsp.c | 1995 +++++++
+ sound/soc/intel/sst/sst_ipc.c | 768 +++
+ sound/soc/intel/sst/sst_pvt.c | 577 ++
+ sound/soc/intel/sst/sst_stream.c | 831 +++
+ sound/soc/intel/sst/sst_trace.h | 147 +
+ sound/soc/intel/sst_platform.h | 155 +
+ sound/soc/intel/sst_platform_pvt.h | 127 +
+ sound/soc/mid-x86/Kconfig | 13 -
+ sound/soc/mid-x86/Makefile | 5 -
+ sound/soc/mid-x86/mfld_machine.c | 447 --
+ sound/soc/mid-x86/sst_dsp.h | 134 -
+ sound/soc/mid-x86/sst_platform.c | 733 ---
+ sound/soc/mid-x86/sst_platform.h | 157 -
+ sound/soc/soc-compress.c | 343 +-
+ sound/soc/soc-core.c | 36 +-
+ sound/soc/soc-dapm.c | 13 +-
+ sound/soc/soc-jack.c | 14 +-
+ sound/soc/soc-pcm.c | 83 +-
+ sound/soc/soc-utils.c | 34 +-
+ 472 files changed, 110390 insertions(+), 8166 deletions(-)
create mode 100644 arch/x86/configs/i386_edison_defconfig
create mode 100644 arch/x86/configs/i386_mrfl_defconfig
create mode 100644 arch/x86/include/asm/bcm_bt_lpm.h
@@ -406,12 +494,18 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
create mode 100644 arch/x86/include/asm/intel_mid_thermal.h
create mode 100644 arch/x86/include/asm/intel_mid_vrtc.h
create mode 100644 arch/x86/include/asm/intel_mip.h
+ create mode 100644 arch/x86/include/asm/intel_psh_ipc.h
create mode 100644 arch/x86/include/asm/intel_scu_flis.h
create mode 100644 arch/x86/include/asm/intel_scu_ipcutil.h
create mode 100644 arch/x86/include/asm/intel_scu_pmic.h
create mode 100644 arch/x86/include/asm/intel_soc_debug.h
+ create mode 100644 arch/x86/include/asm/intel_sst_mrfld.h
delete mode 100644 arch/x86/include/asm/mrst-vrtc.h
delete mode 100644 arch/x86/include/asm/mrst.h
+ create mode 100644 arch/x86/include/asm/platform_byt_audio.h
+ create mode 100644 arch/x86/include/asm/platform_mrfld_audio.h
+ create mode 100644 arch/x86/include/asm/platform_sst.h
+ create mode 100644 arch/x86/include/asm/platform_sst_audio.h
create mode 100644 arch/x86/include/asm/pmic_pdata.h
create mode 100644 arch/x86/include/asm/scu_ipc_rpmsg.h
create mode 100644 arch/x86/platform/intel-mid/Makefile
@@ -420,6 +514,7 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
create mode 100644 arch/x86/platform/intel-mid/device_libs/pci/Makefile
create mode 100644 arch/x86/platform/intel-mid/device_libs/pci/platform_sdhci_pci.c
create mode 100644 arch/x86/platform/intel-mid/device_libs/pci/platform_sdhci_pci.h
+ create mode 100644 arch/x86/platform/intel-mid/device_libs/pci/platform_sst_pci.c
create mode 100644 arch/x86/platform/intel-mid/device_libs/pci/platform_usb_otg.c
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_ads7955.c
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_ads7955.h
@@ -456,6 +551,7 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_mrfl_regulator.c
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_mrfl_thermal.c
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_mrfl_thermal.h
+ create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_mrfld_audio.c
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_msic.c
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_msic.h
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_msic_adc.c
@@ -483,6 +579,7 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_soc_thermal.h
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_spidev.c
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_spidev.h
+ create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_sst_audio.c
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_tc35876x.c
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_tc35876x.h
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_tca6416.c
@@ -491,6 +588,8 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_wifi.h
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_wl12xx.c
create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_wl12xx.h
+ create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_wm8994.c
+ create mode 100644 arch/x86/platform/intel-mid/device_libs/platform_wm8994.h
create mode 100644 arch/x86/platform/intel-mid/early_printk_intel_mid.c
create mode 100644 arch/x86/platform/intel-mid/intel-mid.c
create mode 100644 arch/x86/platform/intel-mid/intel_mid_pcihelpers.c
@@ -525,6 +624,8 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
create mode 100644 drivers/dma/intel_mid_dma_acpi.c
create mode 100644 drivers/gpio/gpiodebug.c
create mode 100644 drivers/gpio/gpiodebug.h
+ create mode 100644 drivers/hwmon/intel_mcu_common.c
+ create mode 100644 drivers/hwmon/intel_mcu_common.h
create mode 100644 drivers/hwmon/intel_mid_gpadc.c
create mode 100644 drivers/i2c/busses/i2c-pmic-regs.h
create mode 100644 drivers/i2c/busses/i2c-pmic.c
@@ -540,6 +641,7 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
create mode 100644 drivers/mmc/core/mmc_panic_ops.c
create mode 100644 drivers/pci/pci-atom_soc.c
delete mode 100644 drivers/platform/x86/intel_mid_thermal.c
+ create mode 100644 drivers/platform/x86/intel_psh_ipc.c
create mode 100644 drivers/platform/x86/intel_scu_flis.c
create mode 100644 drivers/platform/x86/intel_scu_fw_update.c
create mode 100644 drivers/platform/x86/intel_scu_mip.c
@@ -600,6 +702,51 @@ Change-Id: Ifec2f1375746c4c608cb0f799a6a5b9c2c96eaa6
create mode 100644 include/linux/usb/dwc3-intel-mrfl.h
create mode 100644 include/linux/usb/penwell_otg.h
create mode 100644 include/linux/wlan_plat.h
+ create mode 100644 include/sound/effect_driver.h
+ create mode 100644 include/sound/intel_sst_ioctl.h
+ create mode 100644 include/uapi/sound/effect_offload.h
+ create mode 100644 sound/core/effects_offload.c
+ create mode 100644 sound/soc/intel/Kconfig
+ create mode 100644 sound/soc/intel/Makefile
+ create mode 100644 sound/soc/intel/board/Makefile
+ create mode 100644 sound/soc/intel/board/merr_dpcm_dummy.c
+ create mode 100644 sound/soc/intel/board/merr_dpcm_wm8958.c
+ create mode 100644 sound/soc/intel/board/merr_saltbay_wm8958.c
+ create mode 100644 sound/soc/intel/compress.c
+ create mode 100644 sound/soc/intel/effects.c
+ create mode 100644 sound/soc/intel/pcm.c
+ create mode 100644 sound/soc/intel/platform-libs/controls_v1.c
+ create mode 100644 sound/soc/intel/platform-libs/controls_v2.c
+ create mode 100644 sound/soc/intel/platform-libs/controls_v2.h
+ create mode 100644 sound/soc/intel/platform-libs/controls_v2_dpcm.c
+ create mode 100644 sound/soc/intel/platform-libs/ipc_lib.h
+ create mode 100644 sound/soc/intel/platform-libs/ipc_lib_v2.c
+ create mode 100644 sound/soc/intel/platform-libs/sst_widgets.h
+ create mode 100644 sound/soc/intel/platform_ipc_v2.h
+ create mode 100644 sound/soc/intel/ssp/Makefile
+ create mode 100644 sound/soc/intel/ssp/mid_ssp.c
+ create mode 100644 sound/soc/intel/ssp/mid_ssp.h
+ create mode 100644 sound/soc/intel/sst/Makefile
+ create mode 100644 sound/soc/intel/sst/sst.c
+ create mode 100644 sound/soc/intel/sst/sst.h
+ create mode 100644 sound/soc/intel/sst/sst_acpi.c
+ create mode 100644 sound/soc/intel/sst/sst_app_compat_interface.c
+ create mode 100644 sound/soc/intel/sst/sst_app_interface.c
+ create mode 100644 sound/soc/intel/sst/sst_debug.c
+ create mode 100644 sound/soc/intel/sst/sst_drv_interface.c
+ create mode 100644 sound/soc/intel/sst/sst_dsp.c
+ create mode 100644 sound/soc/intel/sst/sst_ipc.c
+ create mode 100644 sound/soc/intel/sst/sst_pvt.c
+ create mode 100644 sound/soc/intel/sst/sst_stream.c
+ create mode 100644 sound/soc/intel/sst/sst_trace.h
+ create mode 100644 sound/soc/intel/sst_platform.h
+ create mode 100644 sound/soc/intel/sst_platform_pvt.h
+ delete mode 100644 sound/soc/mid-x86/Kconfig
+ delete mode 100644 sound/soc/mid-x86/Makefile
+ delete mode 100644 sound/soc/mid-x86/mfld_machine.c
+ delete mode 100644 sound/soc/mid-x86/sst_dsp.h
+ delete mode 100644 sound/soc/mid-x86/sst_platform.c
+ delete mode 100644 sound/soc/mid-x86/sst_platform.h
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 2fe6e76..8ec1e55 100644
@@ -802,10 +949,10 @@ index 6647ed4..a2eb6c6 100644
cflags-$(CONFIG_MELAN) += -march=i486
diff --git a/arch/x86/configs/i386_edison_defconfig b/arch/x86/configs/i386_edison_defconfig
new file mode 100644
-index 0000000..e79bdd1
+index 0000000..b1ed708
--- /dev/null
+++ b/arch/x86/configs/i386_edison_defconfig
-@@ -0,0 +1,3768 @@
+@@ -0,0 +1,3860 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/x86 3.10.17 Kernel Configuration
@@ -961,7 +1108,7 @@ index 0000000..e79bdd1
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
-+# CONFIG_NET_NS is not set
++CONFIG_NET_NS=y
+CONFIG_UIDGID_CONVERTED=y
+# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set
+CONFIG_SCHED_AUTOGROUP=y
@@ -2352,7 +2499,7 @@ index 0000000..e79bdd1
+CONFIG_I2C_DESIGNWARE_CORE_FORK=y
+CONFIG_I2C_DESIGNWARE_PCI_FORK=y
+# CONFIG_I2C_DESIGNWARE_PLATFORM_FORK is not set
-+# CONFIG_I2C_DW_SPEED_MODE_DEBUG is not set
++CONFIG_I2C_DW_SPEED_MODE_DEBUG=y
+CONFIG_I2C_PMIC=y
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_EG20T is not set
@@ -2527,6 +2674,7 @@ index 0000000..e79bdd1
+# CONFIG_POWER_RESET is not set
+# CONFIG_POWER_AVS is not set
+CONFIG_HWMON=y
++CONFIG_INTEL_MCU=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
@@ -2847,13 +2995,80 @@ index 0000000..e79bdd1
+CONFIG_VIDEO_V4L2=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEOBUF2_CORE=m
++CONFIG_VIDEOBUF2_MEMOPS=m
++CONFIG_VIDEOBUF2_VMALLOC=m
+# CONFIG_VIDEO_V4L2_INT_DEVICE is not set
+# CONFIG_TTPCI_EEPROM is not set
+
+#
+# Media drivers
+#
-+# CONFIG_MEDIA_USB_SUPPORT is not set
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_JL2005BCD is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SE401 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TOPRO is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++# CONFIG_USB_SN9C102 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_MEDIA_PCI_SUPPORT is not set
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
@@ -3122,7 +3337,8 @@ index 0000000..e79bdd1
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
-+CONFIG_SND_COMPRESS_OFFLOAD=y
++# CONFIG_SND_COMPRESS_OFFLOAD is not set
++# CONFIG_SND_EFFECTS_OFFLOAD is not set
+CONFIG_SND_JACK=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
@@ -3152,7 +3368,7 @@ index 0000000..e79bdd1
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
-+# CONFIG_SND_USB_AUDIO is not set
++CONFIG_SND_USB_AUDIO=y
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_USX2Y is not set
+# CONFIG_SND_USB_CAIAQ is not set
@@ -3161,8 +3377,15 @@ index 0000000..e79bdd1
+CONFIG_SND_SOC=y
+# CONFIG_SND_ATMEL_SOC is not set
+# CONFIG_SND_MFLD_MACHINE is not set
++CONFIG_SND_INTEL_SST=y
++CONFIG_SND_MRFLD_MACHINE=y
++CONFIG_SND_SST_PLATFORM=y
++CONFIG_SST_MRFLD_DPCM=y
++CONFIG_SND_SST_MACHINE=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
++CONFIG_SND_SOC_WM_HUBS=y
++CONFIG_SND_SOC_WM8994=y
+# CONFIG_SND_SIMPLE_CARD is not set
+# CONFIG_SOUND_PRIME is not set
+
@@ -3838,6 +4061,7 @@ index 0000000..e79bdd1
+# CONFIG_IBM_RTL is not set
+# CONFIG_SAMSUNG_LAPTOP is not set
+CONFIG_INTEL_SCU_FLIS=y
++CONFIG_INTEL_PSH_IPC=y
+
+#
+# Hardware Spinlock drivers
@@ -4104,7 +4328,22 @@ index 0000000..e79bdd1
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_F2FS_FS is not set
-+# CONFIG_AUFS_FS is not set
++CONFIG_AUFS_FS=m
++CONFIG_AUFS_BRANCH_MAX_127=y
++# CONFIG_AUFS_BRANCH_MAX_511 is not set
++# CONFIG_AUFS_BRANCH_MAX_1023 is not set
++# CONFIG_AUFS_BRANCH_MAX_32767 is not set
++CONFIG_AUFS_SBILIST=y
++# CONFIG_AUFS_HNOTIFY is not set
++# CONFIG_AUFS_EXPORT is not set
++# CONFIG_AUFS_RDU is not set
++# CONFIG_AUFS_PROC_MAP is not set
++# CONFIG_AUFS_SP_IATTR is not set
++# CONFIG_AUFS_SHWH is not set
++# CONFIG_AUFS_BR_RAMFS is not set
++# CONFIG_AUFS_BR_FUSE is not set
++CONFIG_AUFS_BDEV_LOOP=y
++# CONFIG_AUFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V2=y
@@ -9685,6 +9924,47 @@ index 0000000..f05fc05
+
+int get_smip_property_by_name(enum platform_prop);
+#endif
+diff --git a/arch/x86/include/asm/intel_psh_ipc.h b/arch/x86/include/asm/intel_psh_ipc.h
+new file mode 100644
+index 0000000..ed4d3c14
+--- /dev/null
++++ b/arch/x86/include/asm/intel_psh_ipc.h
+@@ -0,0 +1,35 @@
++#ifndef _ASM_X86_INTEL_PSH_IPC_H_
++#define _ASM_X86_INTEL_PSH_IPC_H_
++
++#define CHANNEL_BUSY (1 << 31)
++#define PSH_IPC_CONTINUE (1 << 30)
++
++struct psh_msg {
++ u32 msg;
++ u32 param;
++};
++
++enum psh_channel {
++ PSH_SEND_CH0 = 0,
++ PSH_SEND_CH1,
++ PSH_SEND_CH2,
++ PSH_SEND_CH3,
++ NUM_IA2PSH_IPC,
++ PSH_RECV_CH0 = NUM_IA2PSH_IPC,
++ PSH_RECV_CH1,
++ PSH_RECV_CH2,
++ PSH_RECV_CH3,
++ PSH_RECV_END,
++ NUM_PSH2IA_IPC = PSH_RECV_END - PSH_RECV_CH0,
++ NUM_ALL_CH = NUM_IA2PSH_IPC + NUM_PSH2IA_IPC,
++};
++
++typedef void(*psh_channel_handle_t)(u32 msg, u32 param, void *data);
++int intel_ia2psh_command(struct psh_msg *in, struct psh_msg *out,
++ int ch, int timeout);
++int intel_psh_ipc_bind(int ch, psh_channel_handle_t handle, void *data);
++void intel_psh_ipc_unbind(int ch);
++
++void intel_psh_ipc_disable_irq(void);
++void intel_psh_ipc_enable_irq(void);
++#endif
diff --git a/arch/x86/include/asm/intel_scu_flis.h b/arch/x86/include/asm/intel_scu_flis.h
new file mode 100644
index 0000000..7cea735
@@ -10357,6 +10637,56 @@ index 0000000..9edb166
+#endif
+
+#endif
+diff --git a/arch/x86/include/asm/intel_sst_mrfld.h b/arch/x86/include/asm/intel_sst_mrfld.h
+new file mode 100644
+index 0000000..041ff85
+--- /dev/null
++++ b/arch/x86/include/asm/intel_sst_mrfld.h
+@@ -0,0 +1,44 @@
++/* intel_sst_mrlfd.h - Common enum of the Merrifield platform
++ *
++ * Copyright (C) 2013 Intel Corp
++ * Author: Samreen Nilofer
++ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
++ *
++ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ */
++#ifndef _INTEL_SST_MRFLD_H
++#define _INTEL_SST_MRFLD_H
++
++enum {
++ MERR_SALTBAY_AUDIO = 0,
++ MERR_SALTBAY_COMPR,
++ MERR_SALTBAY_VOIP,
++ MERR_SALTBAY_PROBE,
++ MERR_SALTBAY_AWARE,
++ MERR_SALTBAY_VAD,
++ MERR_SALTBAY_POWER,
++};
++
++enum {
++ MERR_DPCM_AUDIO = 0,
++ MERR_DPCM_DB,
++ MERR_DPCM_LL,
++ MERR_DPCM_COMPR,
++ MERR_DPCM_VOIP,
++ MERR_DPCM_PROBE,
++};
++
++#endif
diff --git a/arch/x86/include/asm/module.h b/arch/x86/include/asm/module.h
index e3b7819..a11269b 100644
--- a/arch/x86/include/asm/module.h
@@ -10487,6 +10817,397 @@ index 2f366d0..2d34917 100644
+#endif
+
#endif /* _ASM_X86_MWAIT_H */
+diff --git a/arch/x86/include/asm/platform_byt_audio.h b/arch/x86/include/asm/platform_byt_audio.h
+new file mode 100644
+index 0000000..fed2b1b
+--- /dev/null
++++ b/arch/x86/include/asm/platform_byt_audio.h
+@@ -0,0 +1,49 @@
++/*
++ * platform_byt_audio.h: Baytrail audio platform data header file
++ *
++ * (C) Copyright 2013 Intel Corporation
++ * Author: Omair Md Abdullah
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; version 2
++ * of the License.
++ */
++#ifndef _PLATFORM_BYT_AUDIO_H_
++#define _PLATFORM_BYT_AUDIO_H_
++
++enum {
++ BYT_AUD_AIF1 = 0,
++ BYT_AUD_AIF2,
++ BYT_AUD_COMPR_DEV,
++#ifdef CONFIG_SND_SOC_COMMS_SSP
++ BYT_COMMS_BT,
++ BYT_COMMS_MODEM,
++#endif /* CONFIG_SND_SOC_COMMS_SSP */
++ BYT_AUD_PROBE_DEV,
++};
++
++enum {
++ BYT_CR_AUD_AIF1 = 0,
++ BYT_CR_AUD_COMPR_DEV,
++ BYT_CR_COMMS_BT,
++};
++/* LPE viewpoint addresses */
++/* TODO: move to DSDT */
++#define SST_BYT_IRAM_PHY_START 0xff2c0000
++#define SST_BYT_IRAM_PHY_END 0xff2d4000
++#define SST_BYT_DRAM_PHY_START 0xff300000
++#define SST_BYT_DRAM_PHY_END 0xff320000
++#define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
++#define SST_BYT_IMR_VIRT_END 0xc01fffff
++#define SST_BYT_SHIM_PHY_ADDR 0xff340000
++#define SST_BYT_MBOX_PHY_ADDR 0xff344000
++#define SST_BYT_DMA0_PHY_ADDR 0xff298000
++#define SST_BYT_DMA1_PHY_ADDR 0xff29c000
++#define SST_BYT_SSP0_PHY_ADDR 0xff2a0000
++#define SST_BYT_SSP2_PHY_ADDR 0xff2a2000
++
++#define BYT_FW_MOD_TABLE_OFFSET 0x80000
++#define BYT_FW_MOD_TABLE_SIZE 0x100
++
++#endif
+diff --git a/arch/x86/include/asm/platform_mrfld_audio.h b/arch/x86/include/asm/platform_mrfld_audio.h
+new file mode 100644
+index 0000000..e2b1749
+--- /dev/null
++++ b/arch/x86/include/asm/platform_mrfld_audio.h
+@@ -0,0 +1,25 @@
++/*
++ * platform_mrfld_audio.h: MRFLD audio platform data header file
++ *
++ * (C) Copyright 2012 Intel Corporation
++ * Author: Vinod Koul
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; version 2
++ * of the License.
++ */
++#ifndef _PLATFORM_MRFLD_AUDIO_H_
++#define _PLATFORM_MRFLD_AUDIO_H_
++
++#include