Changes in code.

Author: jgu222

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

@@ -9081,7 +9081,7 @@ bool EmitPass::validateInlineAsmConstraints(llvm::CallInst *inst, SmallVector<St
     } else if (str.getAsInteger(10, matchVal) == 0) {
       // Also allows matching input reg to output reg
       return true;
-    } else if (str.equals("i")) {
+    } else if (str.equals("i") || str.equals("P")) {
       return cv && cv->IsImmediate();
     } else if (str.equals("rw.u")) {
       return cv && cv->IsUniform();
@@ -9205,7 +9205,7 @@ void EmitPass::EmitInlineAsm(llvm::CallInst *inst) {
     }
     // Special handling if LLVM replaces a variable with an immediate, we need
     // to insert an extra move
-    else if (opVar->IsImmediate() && !constraint.equals("i")) {
+    else if (opVar->IsImmediate() && !constraint.equals("i") && !constraint.equals("P")) {
       CVariable *tempMov = m_currShader->GetNewVariable(1, opVar->GetType(), EALIGN_GRF, true, opVar->getName());
       m_encoder->Copy(tempMov, opVar);
       m_encoder->Push();
@@ -9271,7 +9271,13 @@ void EmitPass::EmitInlineAsm(llvm::CallInst *inst) {
       IGC_ASSERT_MESSAGE(0, "Invalid operand index");
       return;
     }
-    string varName = opnds[val] ? m_encoder->GetVariableName(opnds[val]) : "null";
+    string varName;
+    if (constraints[val].equals("P"))
+      varName = std::to_string(opnds[val]->GetImmediateValue());
+    else if (opnds[val])
+      varName = m_encoder->GetVariableName(opnds[val]);
+    else
+      varName = "null";
     asmStr.replace(varPos, (idEnd - idStart + 1), varName);
 
     startPos = varPos + varName.size();

IGC/Compiler/tests/EmitVISAPass/inline_asm_constraint_P.ll

@@ -0,0 +1,74 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2023 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; To test inline as on constraint "P" : plain immediate
+
+; REQUIRES: llvm-14-plus, regkeys
+
+; RUN: igc_opt --opaque-pointers --CheckInstrTypes --igc-update-instrtypes-on-run -inputocl --neo \
+; RUN:         -platformpvc -igc-emit-visa -regkey DumpVISAASMToConsole -simd-mode 16 %s  \
+; RUN: | FileCheck %s
+
+; CHECK-LABEL: .function
+; CHECK:  dpas.bf.bf.8.2 (M1, 16)
+; CHECK: ret (M1, 1)
+
+; Function Attrs: convergent nounwind null_pointer_is_valid
+define spir_kernel void @test(i32 addrspace(1)* align 4 %a, i32 addrspace(1)* align 4 %b, <8 x i32> %r0, <8 x i32> %payloadHeader,
+       i16 %localIdX, i16 %localIdY, i16 %localIdZ ) {
+entry:
+  %lid = zext i16 %localIdX to i64
+  %base = ptrtoint i32 addrspace(1)* %a to i64
+  %bbase = ptrtoint i32 addrspace(1)* %b to i64
+  %tmp0 = add i64  %base, %lid
+  %a_addr = inttoptr i64 %tmp0 to i16 addrspace(1)*
+  %tmp1 = add i64  %bbase, %lid
+  %b_addr = inttoptr i64 %tmp1 to i16 addrspace(1)*
+  %ma = load i32, ptr addrspace(1) %a, align 4
+  %mb = load i32, ptr addrspace(1) %b, align 4
+
+  %r = call i32 asm "dpas.bf.bf.8.$4 (M1, 16) $0.0  $1.0  $2.0  $3(0,0)" , "=rw,rw,rw,rw,P"(i32 0, i32 %ma, i32 %mb, i32 2)
+
+  %tmp3 = add i64  %tmp0, 1024
+  %d_addr = inttoptr i64 %tmp3 to i32 addrspace(1)*
+  store i32 %r, i32 addrspace(1)* %d_addr
+  ret void
+}
+
+
+!igc.functions = !{!0}
+!IGCMetadata = !{!13}
+
+!0 = !{void (i16 addrspace(1)*, i16 addrspace(1)*, <8 x i32>, <8 x i32>, i16, i16, i16)* @test, !1}
+!1 = !{!2, !3}
+!2 = !{!"function_type", i32 0}
+!3 = !{!"sub_group_size", i32 16}
+!13 = !{!"ModuleMD", !14}
+!14 = !{!"FuncMD", !15, !16}
+!15 = !{!"FuncMDMap[0]", void (i16 addrspace(1)*, i16 addrspace(1)*, <8 x i32>, <8 x i32>, i16, i16, i16)* @test}
+!16 = !{!"FuncMDValue[0]", !90, !100, !226}
+!90 = !{!"localOffsets"}
+!100 = !{!"resAllocMD", !183, !184, !185, !186}
+!183 = !{!"uavsNumType", i32 0}
+!184 = !{!"srvsNumType", i32 0}
+!185 = !{!"samplersNumType", i32 0}
+!186 = !{!"argAllocMDList", !187, !191, !192, !193, !194, !195, !196}
+!187 = !{!"argAllocMDListVec[0]", !188, !189, !190}
+!188 = !{!"type", i32 0}
+!189 = !{!"extensionType", i32 -1}
+!190 = !{!"indexType", i32 -1}
+!191 = !{!"argAllocMDListVec[1]", !188, !189, !190}
+!192 = !{!"argAllocMDListVec[2]", !188, !189, !190}
+!193 = !{!"argAllocMDListVec[3]", !188, !189, !190}
+!194 = !{!"argAllocMDListVec[4]", !188, !189, !190}
+!195 = !{!"argAllocMDListVec[5]", !188, !189, !190}
+!196 = !{!"argAllocMDListVec[6]", !188, !189, !190}
+!226 = !{!"m_OpenCLArgTypeQualifiers", !227, !228}
+!227 = !{!"m_OpenCLArgTypeQualifiersVec[0]", !""}
+!228 = !{!"m_OpenCLArgTypeQualifiersVec[1]", !""}
+