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fangliu2020igcbot
authored andcommitted
Fix the access bound check issue of src operand for madw instruction
For madw instruction, only the dst operand needs special handling in verifier and src operand should be treated as other instructions.
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-11
lines changed

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+13
-11
lines changed

visa/IsaVerification.cpp

Lines changed: 13 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -510,6 +510,7 @@ void vISAVerifier::verifyRegion(const CISA_INST *inst, unsigned i) {
510510
Common_ISA_Operand_Class operand_class = vect.getOperandClass();
511511

512512
unsigned dstIndex = getDstIndex(inst);
513+
bool isDst = (i == dstIndex);
513514

514515
unsigned numPreDefinedVars = Get_CISA_PreDefined_Var_Count();
515516

@@ -565,7 +566,7 @@ void vISAVerifier::verifyRegion(const CISA_INST *inst, unsigned i) {
565566
REPORT_INSTRUCTION(options, false, "Invalid execution size");
566567
}
567568

568-
if (i == dstIndex) {
569+
if (isDst) {
569570
REPORT_INSTRUCTION(
570571
options, 0 != h_stride_val,
571572
"Horizontal Stride should not be 0 for a destination operand.");
@@ -632,7 +633,7 @@ void vISAVerifier::verifyRegion(const CISA_INST *inst, unsigned i) {
632633
"Legal CISA region vertical stride parameter values: "
633634
"{0, 1, 2, 4, 8, 16, 32}.");
634635
}
635-
} else if (dstIndex != i) {
636+
} else if (!isDst) {
636637
// check for out-of-bound addresses for VxH operand
637638
int numAddr = exec_sz / width_val;
638639
REPORT_INSTRUCTION(options, numAddr <= (int)irBuilder->getNumAddrRegisters(),
@@ -699,13 +700,14 @@ void vISAVerifier::verifyRegion(const CISA_INST *inst, unsigned i) {
699700
firstElementIndex +
700701
(((i * v_stride_val) + (j * h_stride_val)) * VN_size);
701702

702-
// Madw instruction has both low and high results. So, need to check
703-
// the offset of high result.
704-
unsigned hiOffset = 0;
705-
if (inst->opcode == ISA_MADW) {
706-
hiOffset = (region_offset - firstElementIndex + 1 + grfSize - 1) &
703+
// Madw instruction has both low and high results in dst. So, need
704+
// to check the offset of high result.
705+
unsigned dstHiOffset = 0;
706+
if (inst->opcode == ISA_MADW && isDst) {
707+
dstHiOffset =
708+
(region_offset - firstElementIndex + 1 + grfSize - 1) &
707709
(~(grfSize - 1)); // GRF-aligned
708-
region_offset += hiOffset;
710+
region_offset += dstHiOffset;
709711
}
710712

711713
if (region_offset >= var_size) {
@@ -719,16 +721,16 @@ void vISAVerifier::verifyRegion(const CISA_INST *inst, unsigned i) {
719721
std::cout << " The access fails the following check to determine "
720722
"correct bounds (see CISA manual section 5.1 "
721723
"Region-based Addressing):\n";
722-
if (inst->opcode == ISA_MADW) {
724+
if (inst->opcode == ISA_MADW && isDst) {
723725
std::cout
724726
<< "(row_offset * GRF_SIZE + col_offset * type_size) + "
725727
"(((i * v_stride) + (j * h_stride)) * type_size) + "
726-
"high_offset < type_size * num_elements:\n";
728+
"dstHiOffset < type_size * num_elements:\n";
727729
std::cout << "(" << (int)row_offset << " * " << grfSize << " + "
728730
<< (int)col_offset << " * " << VN_size << ") + (((" << i
729731
<< " * " << v_stride_val << ") + (" << j << " * "
730732
<< h_stride_val << ")) * " << VN_size << ") + "
731-
<< hiOffset << " < " << VN_size << " * "
733+
<< dstHiOffset << " < " << VN_size << " * "
732734
<< num_elements << "\n";
733735
} else {
734736
std::cout

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