Added better debouncer.

Author: jakubcabal

rtl/comp/debouncer.vhd

@@ -0,0 +1,79 @@
+--------------------------------------------------------------------------------
+-- PROJECT: SIMPLE UART FOR FPGA
+--------------------------------------------------------------------------------
+-- MODULE:  DEBOUNCER
+-- AUTHORS: Jakub Cabal <[email protected]>
+-- LICENSE: The MIT License (MIT), please read LICENSE file
+-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity DEBOUNCER is
+    Generic (
+        -- latency of debouncer in clock cycles, minimum value is 2,
+        -- value also corresponds to the number of bits compared
+        LATENCY : natural := 4
+    );
+    Port (
+        CLK     : in  std_logic; -- system clock
+        DEB_IN  : in  std_logic; -- input of signal from outside FPGA
+        DEB_OUT : out std_logic  -- output of debounced (filtered) signal
+    );
+end DEBOUNCER;
+
+architecture RTL of DEBOUNCER is
+
+    constant SHREG_DEPTH : natural := LATENCY-1;
+
+    signal input_shreg    : std_logic_vector(SHREG_DEPTH-1 downto 0);
+    signal output_reg_rst : std_logic;
+    signal output_reg_set : std_logic;
+
+begin
+
+    -- parameterized input shift register
+    input_shreg_p : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            input_shreg <= input_shreg(SHREG_DEPTH-2 downto 0) & DEB_IN;
+        end if;
+    end process;
+
+    -- output register will be reset when all compared bits are low
+    output_reg_rst_p : process (DEB_IN, input_shreg)
+        variable or_var : std_logic;
+    begin
+        or_var := DEB_IN;
+        all_bits_or_l : for i in 0 to SHREG_DEPTH-1 loop
+            or_var := or_var or input_shreg(i);
+        end loop;
+        output_reg_rst <= not or_var;
+    end process;
+
+    -- output register will be set when all compared bits are high
+    output_reg_set_p : process (DEB_IN, input_shreg)
+        variable and_var : std_logic;
+    begin
+        and_var := DEB_IN;
+        all_bits_and_l : for i in 0 to SHREG_DEPTH-1 loop
+            and_var := and_var and input_shreg(i);
+        end loop;
+        output_reg_set <= and_var;
+    end process;
+
+    -- output register
+    output_reg_p : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (output_reg_rst = '1') then
+                DEB_OUT <= '0';
+            elsif (output_reg_set = '1') then
+                DEB_OUT <= '1';
+            end if;
+        end if;
+    end process;
+
+end RTL;

rtl/uart.vhd

@@ -48,7 +48,6 @@ architecture FULL of UART is
 
     signal uart_clk_cnt       : unsigned(CLK_CNT_WIDTH-1 downto 0);
     signal uart_clk_en        : std_logic;
-    signal uart_rxd_shreg     : std_logic_vector(3 downto 0);
     signal uart_rxd_debounced : std_logic;
 
 begin
@@ -75,34 +74,19 @@ begin
     uart_clk_en <= '1' when (uart_clk_cnt = CLK_CNT_MAX) else '0';
 
     -- -------------------------------------------------------------------------
-    --  UART RXD SHIFT REGISTER AND DEBAUNCER
+    --  UART RXD DEBAUNCER
     -- -------------------------------------------------------------------------
 
     use_debouncer_g : if (USE_DEBOUNCER = True) generate
-        uart_rxd_shreg_p : process (CLK)
-        begin
-            if (rising_edge(CLK)) then
-                if (RST = '1') then
-                    uart_rxd_shreg <= (others => '1');
-                else
-                    uart_rxd_shreg <= UART_RXD & uart_rxd_shreg(3 downto 1);
-                end if;
-            end if;
-        end process;
-
-        uart_rxd_debounced_reg_p : process (CLK)
-        begin
-            if (rising_edge(CLK)) then
-                if (RST = '1') then
-                    uart_rxd_debounced <= '1';
-                else
-                    uart_rxd_debounced <= uart_rxd_shreg(0) or
-                                          uart_rxd_shreg(1) or
-                                          uart_rxd_shreg(2) or
-                                          uart_rxd_shreg(3);
-                end if;
-            end if;
-        end process;
+        debouncer_i : entity work.DEBOUNCER
+        generic map(
+            LATENCY => 4
+        )
+        port map (
+            CLK     => CLK,
+            DEB_IN  => UART_RXD,
+            DEB_OUT => uart_rxd_debounced
+        );
     end generate;
 
     not_use_debouncer_g : if (USE_DEBOUNCER = False) generate

sim/sim.tcl

@@ -11,6 +11,7 @@
 vlib work
 
 # Compile VHDL files
+vcom -93 ../rtl/comp/debouncer.vhd
 vcom -93 ../rtl/comp/uart_parity.vhd
 vcom -93 ../rtl/comp/uart_tx.vhd
 vcom -93 ../rtl/comp/uart_rx.vhd
@@ -21,6 +22,6 @@ vcom -93 ./uart_tb.vhd
 vsim work.uart_tb
 
 # Setup and start simulation
-add wave *
-#add wave sim:/uart_tb/utt/*
+#add wave *
+add wave sim:/uart_tb/utt/*
 run 200 us