UART: Added parity support

jakubcabal · jakubcabal · commit a0473ef260cf · 2015-10-22T17:55:44.000+02:00
diff --git a/README.md b/README.md
@@ -4,13 +4,17 @@ Simple UART (Universal Asynchronous Receiver & Transmitter) module for serial co
 
 **The default settings are 115200 baud rate, 8 data bits, 1 stop bit, no parity, disable input data FIFO, 50 MHz system clock.**
 
-The UART module was tested in hardware. In the near future it will be implemented generic support for parity bit and set the number of stop bits. Stay tuned!
+The UART module was tested in hardware. In the near future it will be implemented generic support settings of stop bits. Stay tuned!
 
 **Synthesis resource usage summary:**
 
-Input FIFO | LE (LUT) | FF | BRAM
---- | --- | --- | ---
-disable | 72 | 46 | 0
-enable | 110 | 63 | 1
+Parity | Input FIFO | LE (LUT) | FF | BRAM
+--- | --- | --- | --- | ---
+none | disable | 72 | 46 | 0
+none | enable | 110 | 63 | 1
+even/odd | disable | 82 | 49 | 0
+even/odd | enable | 121 | 66 | 1
+mark/space | disable | 77 | 49 | 0
+mark/space | enable | 115 | 66 | 1
 
 *Synthesis was performed using Quartus II 64-Bit Version 13.0.1 with default settings for FPGA Altera Cyclone II.*
diff --git a/example/uart_loopback.vhd b/example/uart_loopback.vhd
@@ -29,11 +29,12 @@ use IEEE.NUMERIC_STD.ALL;
  
 entity UART_LOOPBACK is
     Generic (
-        BAUD_RATE  : integer := 115200;
-        DATA_BITS  : integer := 8;
-        CLK_FREQ   : integer := 50e6;
-        INPUT_FIFO : boolean := True;
-        FIFO_DEPTH : integer := 256
+        BAUD_RATE  : integer := 115200; -- baud rate value
+        DATA_BITS  : integer := 8;      -- legal values: 5,6,7,8
+        PARITY_BIT : string  := "none"; -- legal values: "none", "even", "odd", "mark", "space"
+        CLK_FREQ   : integer := 50e6;   -- set system clock frequency in Hz
+        INPUT_FIFO : boolean := True;   -- enable input data FIFO
+        FIFO_DEPTH : integer := 256     -- set depth of input data FIFO
     );
     Port (
         CLK        : in  std_logic; -- system clock
@@ -65,6 +66,7 @@ begin
     generic map (
         BAUD_RATE   => BAUD_RATE,
         DATA_BITS   => DATA_BITS,
+        PARITY_BIT  => PARITY_BIT,
         CLK_FREQ    => CLK_FREQ,
         INPUT_FIFO  => INPUT_FIFO,
         FIFO_DEPTH  => FIFO_DEPTH
diff --git a/example/uart_loopback_tb.vhd b/example/uart_loopback_tb.vhd
@@ -49,11 +49,12 @@ begin
  
 	utt: entity work.UART_LOOPBACK
     generic map (
-        BAUD_RATE   => 115200, -- baud rate value
-        DATA_BITS   => 8,      -- legal values: 5,6,7,8
-        CLK_FREQ    => 50e6,   -- set system clock frequency in Hz
-        INPUT_FIFO  => True,   -- enable input data FIFO
-        FIFO_DEPTH  => 256	   -- set depth of input data FIFO
+        BAUD_RATE   => 115200,
+        DATA_BITS   => 8,
+        PARITY_BIT  => "none",
+        CLK_FREQ    => 50e6,
+        INPUT_FIFO  => True,
+        FIFO_DEPTH  => 256
     )
     port map (
         CLK         => CLK,
diff --git a/source/comp/uart_parity.vhd b/source/comp/uart_parity.vhd
@@ -0,0 +1,89 @@
+-- The MIT License (MIT)
+--
+-- Copyright (c) 2015 Jakub Cabal
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+-- 
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+-- SOFTWARE.
+--
+-- Website: https://github.com/jakubcabal/uart_for_fpga    
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity UART_PARITY is
+    Generic (
+        DATA_WIDTH  : integer := 8;
+        PARITY_TYPE : string  := "none" -- legal values: "none", "even", "odd", "mark", "space"
+    );
+    Port (
+        DATA_IN     : in  std_logic_vector(DATA_WIDTH-1 downto 0);
+        PARITY_OUT  : out std_logic
+    );
+end UART_PARITY;
+
+architecture FULL of UART_PARITY is
+
+begin
+
+    -- -------------------------------------------------------------------------
+    --                        PARITY BIT GENERATOR
+    -- -------------------------------------------------------------------------
+
+    even_parity_g : if (PARITY_TYPE = "even") generate
+
+        process (DATA_IN)
+        	variable parity_temp : std_logic;
+        begin
+            parity_temp := '0';
+            for i in DATA_IN'range loop
+                parity_temp := parity_temp XOR DATA_IN(i);
+            end loop;
+            PARITY_OUT <= parity_temp;
+        end process;
+
+    end generate;
+
+    odd_parity_g : if (PARITY_TYPE = "odd") generate
+
+        process (DATA_IN)
+        	variable parity_temp : std_logic;
+        begin
+            parity_temp := '1';
+            for i in DATA_IN'range loop
+                parity_temp := parity_temp XOR DATA_IN(i);
+            end loop;
+            PARITY_OUT <= parity_temp;
+        end process;
+
+    end generate;
+
+    mark_parity_g : if (PARITY_TYPE = "mark") generate
+
+        PARITY_OUT <= '1';
+
+    end generate;
+
+    space_parity_g : if (PARITY_TYPE = "space") generate
+
+        PARITY_OUT <= '0';
+
+    end generate;
+
+end FULL;
diff --git a/source/uart.vhd b/source/uart.vhd
@@ -31,8 +31,8 @@ entity UART is
     Generic (
         BAUD_RATE   : integer := 115200; -- baud rate value
         DATA_BITS   : integer := 8;      -- legal values: 5,6,7,8
-        --PARITY_BIT  : string  := "none"; -- TODO, now must be none parity bit, legal values: "none", "odd", "even", "mark", "space"
-        --STOP_BITS   : integer;           -- TODO, now must be 1 stop bit
+        PARITY_BIT  : string  := "none"; -- legal values: "none", "even", "odd", "mark", "space"
+        --STOP_BITS   : integer;         -- TODO, now must be 1 stop bit
         CLK_FREQ    : integer := 50e6;   -- set system clock frequency in Hz
         INPUT_FIFO  : boolean := False;  -- enable input data FIFO
         FIFO_DEPTH  : integer := 256     -- set depth of input data FIFO
@@ -67,6 +67,7 @@ architecture FULL of UART is
     signal tx_busy              : std_logic;
     signal tx_data_in           : std_logic_vector(DATA_BITS-1 downto 0);
     signal tx_data_send         : std_logic;
+    signal tx_parity_bit        : std_logic;
 
     signal uart_ticks           : integer range 0 to divider_value-1;
     signal uart_clk_en          : std_logic;
@@ -82,8 +83,11 @@ architecture FULL of UART is
     signal rx_bit_count_en      : std_logic;
     signal rx_bit_count_rst     : std_logic;
     signal rx_data_shreg_en     : std_logic;
+    signal rx_parity_bit        : std_logic;
+    signal rx_parity_error      : std_logic := '0';
+    signal rx_parity_check_en   : std_logic;
 
-    type state is (idle, txsync, startbit, databits, stopbit);
+    type state is (idle, txsync, startbit, databits, paritybit, stopbit);
     signal tx_pstate : state;
     signal tx_nstate : state;
     signal rx_pstate : state;
@@ -207,6 +211,24 @@ begin
         end if;
     end process;
 
+    -- -------------------------------------------------------------------------
+    --                        UART TRANSMITTER PARITY GENERATOR
+    -- -------------------------------------------------------------------------
+
+    tx_parity_g : if (PARITY_BIT /= "none") generate
+
+        tx_parity_gen_i: entity work.UART_PARITY
+        generic map (
+            DATA_WIDTH  => DATA_BITS,
+            PARITY_TYPE => PARITY_BIT
+        )
+        port map (
+            DATA_IN     => tx_data,
+            PARITY_OUT  => tx_parity_bit
+        );
+
+    end generate;
+
     -- -------------------------------------------------------------------------
     --                        UART TRANSMITTER FSM
     -- -------------------------------------------------------------------------
@@ -224,7 +246,7 @@ begin
     end process;
 
     -- NEXT STATE AND OUTPUTS LOGIC
-    process (tx_pstate, tx_data_send, tx_clk_en, tx_data, tx_bit_count)
+    process (tx_pstate, tx_data_send, tx_clk_en, tx_data, tx_bit_count, tx_parity_bit)
     begin
 
         case tx_pstate is
@@ -272,11 +294,27 @@ begin
                 tx_bit_count_en <= '1';
 
                 if ((tx_clk_en = '1') AND (tx_bit_count = DATA_BITS-1)) then
-                    tx_nstate <= idle;
+                    if (PARITY_BIT = "none") then
+                        tx_nstate <= idle;
+                    else
+                        tx_nstate <= paritybit;
+                    end if ;
                 else
                     tx_nstate <= databits;
                 end if;
 
+            when paritybit =>
+                tx_busy <= '1';
+                TX_UART <= tx_parity_bit;
+                tx_bit_count_rst <= '1';
+                tx_bit_count_en <= '0';
+
+                if (tx_clk_en = '1') then
+                    tx_nstate <= idle;
+                else
+                    tx_nstate <= paritybit;
+                end if;
+
             when others => 
                 tx_busy <= '1';
                 TX_UART <= '1';
@@ -353,6 +391,35 @@ begin
 
     DATA_OUT <= rx_data;
 
+    -- -------------------------------------------------------------------------
+    --                        UART RECEIVER PARITY GENERATOR AND CHECK
+    -- -------------------------------------------------------------------------
+
+    rx_parity_g : if (PARITY_BIT /= "none") generate
+
+        rx_parity_gen_i: entity work.UART_PARITY
+        generic map (
+            DATA_WIDTH  => DATA_BITS,
+            PARITY_TYPE => PARITY_BIT
+        )
+        port map (
+            DATA_IN     => rx_data,
+            PARITY_OUT  => rx_parity_bit
+        );
+
+        rx_parity_check_reg : process (CLK) 
+        begin
+            if (rising_edge(CLK)) then
+                if (RST = '1') then
+                    rx_parity_error <= '0';
+                elsif (rx_parity_check_en = '1') then
+                    rx_parity_error <= rx_parity_bit XOR RX_UART;
+                end if;
+            end if;
+        end process;
+
+    end generate;
+
     -- -------------------------------------------------------------------------
     --                        UART RECEIVER FSM
     -- -------------------------------------------------------------------------
@@ -370,7 +437,7 @@ begin
     end process;
 
     -- NEXT STATE AND OUTPUTS LOGIC
-    process (rx_pstate, RX_UART, rx_clk_en, rx_bit_count)
+    process (rx_pstate, RX_UART, rx_clk_en, rx_bit_count, rx_parity_error)
     begin
         case rx_pstate is
      
@@ -381,6 +448,7 @@ begin
                 rx_bit_count_en <= '0';
                 rx_data_shreg_en <= '0';
                 rx_clk_divider_en <= '0';
+                rx_parity_check_en <= '0';
 
                 if (RX_UART = '0') then
                     rx_nstate <= startbit;
@@ -395,6 +463,7 @@ begin
                 rx_bit_count_en <= '0';
                 rx_data_shreg_en <= '0';
                 rx_clk_divider_en <= '1';
+                rx_parity_check_en <= '0';
 
                 if (rx_clk_en = '1') then
                     rx_nstate <= databits;
@@ -409,22 +478,44 @@ begin
                 rx_bit_count_en <= '1';
                 rx_data_shreg_en <= '1';
                 rx_clk_divider_en <= '1';
+                rx_parity_check_en <= '0';
 
                 if ((rx_clk_en = '1') AND (rx_bit_count = DATA_BITS-1)) then
-                    rx_nstate <= stopbit;
+                    if (PARITY_BIT = "none") then
+                        rx_nstate <= stopbit;
+                    else
+                        rx_nstate <= paritybit;
+                    end if ;
                 else
                     rx_nstate <= databits;
                 end if;
 
+            when paritybit =>
+                DATA_VLD <= '0';
+                FRAME_ERROR <= '0';
+                rx_bit_count_rst <= '1';
+                rx_bit_count_en <= '0';
+                rx_data_shreg_en <= '0';
+                rx_clk_divider_en <= '1';
+
+                if (rx_clk_en = '1') then
+                    rx_nstate <= stopbit;
+                    rx_parity_check_en <= '1';
+                else
+                    rx_nstate <= paritybit;
+                    rx_parity_check_en <= '0';
+                end if;
+
             when stopbit =>
                 rx_bit_count_rst <= '1';
                 rx_bit_count_en <= '0';
                 rx_data_shreg_en <= '0';
                 rx_clk_divider_en <= '1';
+                rx_parity_check_en <= '0';
 
                 if (rx_clk_en = '1') then
                     rx_nstate <= idle;
-                    DATA_VLD <= '1';
+                    DATA_VLD <= NOT rx_parity_error;
                     FRAME_ERROR <= NOT RX_UART;
                 else
                     rx_nstate <= stopbit;
@@ -439,6 +530,7 @@ begin
                 rx_bit_count_en <= '0';
                 rx_data_shreg_en <= '0';
                 rx_clk_divider_en <= '0';
+                rx_parity_check_en <= '0';
                 rx_nstate <= idle;
          
         end case;
diff --git a/source/uart_tb.vhd b/source/uart_tb.vhd
