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jakubcabaljakubcabal
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Some small edits in RTL code.
1 parent 4ddde0c commit a0be2fc

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3 files changed

+38
-37
lines changed

3 files changed

+38
-37
lines changed

‎rtl/comp/uart_rx.vhd‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,9 @@ entity UART_RX is
2222
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
2323
UART_RXD : in std_logic; -- serial receive data
2424
-- USER DATA OUTPUT INTERFACE
25-
DATA_OUT : out std_logic_vector(7 downto 0); -- output data
26-
DATA_VLD : out std_logic; -- when DATA_VLD = 1, output data are valid
27-
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid
25+
DOUT : out std_logic_vector(7 downto 0); -- data received via UART
26+
DOUT_VLD : out std_logic; -- when DOUT_VLD = 1, DOUT is valid (is assert only for one clock cycle)
27+
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid (is assert only for one clock cycle)
2828
);
2929
end UART_RX;
3030

@@ -117,7 +117,7 @@ begin
117117
end if;
118118
end process;
119119

120-
DATA_OUT <= rx_data;
120+
DOUT <= rx_data;
121121

122122
-- -------------------------------------------------------------------------
123123
-- UART RECEIVER PARITY GENERATOR AND CHECK
@@ -158,14 +158,14 @@ begin
158158
begin
159159
if (rising_edge(CLK)) then
160160
if (RST = '1') then
161-
DATA_VLD <= '0';
161+
DOUT_VLD <= '0';
162162
FRAME_ERROR <= '0';
163163
else
164164
if (rx_clk_en = '1' AND rx_output_reg_en = '1') then
165-
DATA_VLD <= NOT rx_parity_error AND UART_RXD;
165+
DOUT_VLD <= NOT rx_parity_error AND UART_RXD;
166166
FRAME_ERROR <= NOT UART_RXD;
167167
else
168-
DATA_VLD <= '0';
168+
DOUT_VLD <= '0';
169169
FRAME_ERROR <= '0';
170170
end if;
171171
end if;
@@ -194,9 +194,9 @@ begin
194194
case rx_pstate is
195195

196196
when idle =>
197-
rx_output_reg_en <= '0';
198-
rx_receiving_data <= '0';
199-
rx_clk_divider_en <= '0';
197+
rx_output_reg_en <= '0';
198+
rx_receiving_data <= '0';
199+
rx_clk_divider_en <= '0';
200200
rx_parity_check_en <= '0';
201201

202202
if (UART_RXD = '0') then
@@ -206,9 +206,9 @@ begin
206206
end if;
207207

208208
when startbit =>
209-
rx_output_reg_en <= '0';
210-
rx_receiving_data <= '0';
211-
rx_clk_divider_en <= '1';
209+
rx_output_reg_en <= '0';
210+
rx_receiving_data <= '0';
211+
rx_clk_divider_en <= '1';
212212
rx_parity_check_en <= '0';
213213

214214
if (rx_clk_en = '1') then
@@ -218,9 +218,9 @@ begin
218218
end if;
219219

220220
when databits =>
221-
rx_output_reg_en <= '0';
222-
rx_receiving_data <= '1';
223-
rx_clk_divider_en <= '1';
221+
rx_output_reg_en <= '0';
222+
rx_receiving_data <= '1';
223+
rx_clk_divider_en <= '1';
224224
rx_parity_check_en <= '0';
225225

226226
if ((rx_clk_en = '1') AND (rx_bit_count = "111")) then
@@ -234,9 +234,9 @@ begin
234234
end if;
235235

236236
when paritybit =>
237-
rx_output_reg_en <= '0';
238-
rx_receiving_data <= '0';
239-
rx_clk_divider_en <= '1';
237+
rx_output_reg_en <= '0';
238+
rx_receiving_data <= '0';
239+
rx_clk_divider_en <= '1';
240240
rx_parity_check_en <= '1';
241241

242242
if (rx_clk_en = '1') then
@@ -246,10 +246,10 @@ begin
246246
end if;
247247

248248
when stopbit =>
249-
rx_receiving_data <= '0';
250-
rx_clk_divider_en <= '1';
249+
rx_receiving_data <= '0';
250+
rx_clk_divider_en <= '1';
251251
rx_parity_check_en <= '0';
252-
rx_output_reg_en <= '1';
252+
rx_output_reg_en <= '1';
253253

254254
if (rx_clk_en = '1') then
255255
rx_nstate <= idle;
@@ -258,9 +258,9 @@ begin
258258
end if;
259259

260260
when others =>
261-
rx_output_reg_en <= '0';
262-
rx_receiving_data <= '0';
263-
rx_clk_divider_en <= '0';
261+
rx_output_reg_en <= '0';
262+
rx_receiving_data <= '0';
263+
rx_clk_divider_en <= '0';
264264
rx_parity_check_en <= '0';
265265
rx_nstate <= idle;
266266

‎rtl/comp/uart_tx.vhd‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,9 @@ entity UART_TX is
2222
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
2323
UART_TXD : out std_logic; -- serial transmit data
2424
-- USER DATA INPUT INTERFACE
25-
DATA_IN : in std_logic_vector(7 downto 0); -- input data
26-
DATA_SEND : in std_logic; -- when DATA_SEND = 1, input data are valid and will be transmit
27-
BUSY : out std_logic -- when BUSY = 1, transmitter is busy and you must not set DATA_SEND to 1
25+
DIN : in std_logic_vector(7 downto 0); -- data to be transmitted over UART
26+
DIN_VLD : in std_logic; -- when DIN_VLD = 1, DIN is valid and will be accepted for transmiting
27+
BUSY : out std_logic -- when BUSY = 1, transmitter is busy and DIN can not be accepted
2828
);
2929
end UART_TX;
3030

@@ -93,8 +93,8 @@ begin
9393
if (rising_edge(CLK)) then
9494
if (RST = '1') then
9595
tx_data <= (others => '0');
96-
elsif (DATA_SEND = '1' AND tx_busy = '0') then
97-
tx_data <= DATA_IN;
96+
elsif (DIN_VLD = '1' AND tx_busy = '0') then
97+
tx_data <= DIN;
9898
end if;
9999
end if;
100100
end process;
@@ -179,7 +179,7 @@ begin
179179
end process;
180180

181181
-- NEXT STATE AND OUTPUTS LOGIC
182-
process (tx_pstate, DATA_SEND, tx_clk_en, tx_bit_count)
182+
process (tx_pstate, DIN_VLD, tx_clk_en, tx_bit_count)
183183
begin
184184

185185
case tx_pstate is
@@ -190,7 +190,7 @@ begin
190190
tx_bit_count_en <= '0';
191191
tx_clk_divider_en <= '0';
192192

193-
if (DATA_SEND = '1') then
193+
if (DIN_VLD = '1') then
194194
tx_nstate <= txsync;
195195
else
196196
tx_nstate <= idle;
@@ -254,7 +254,7 @@ begin
254254
tx_bit_count_en <= '0';
255255
tx_clk_divider_en <= '1';
256256

257-
if (DATA_SEND = '1') then
257+
if (DIN_VLD = '1') then
258258
tx_nstate <= txsync;
259259
elsif (tx_clk_en = '1') then
260260
tx_nstate <= idle;

‎rtl/uart.vhd‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ entity UART is
2323
USE_DEBOUNCER : boolean := True -- enable/disable debouncer
2424
);
2525
Port (
26+
-- CLOCK AND RESET
2627
CLK : in std_logic; -- system clock
2728
RST : in std_logic; -- high active synchronous reset
2829
-- UART INTERFACE
@@ -123,8 +124,8 @@ begin
123124
UART_CLK_EN => uart_clk_en,
124125
UART_TXD => UART_TXD,
125126
-- USER DATA INPUT INTERFACE
126-
DATA_IN => DIN,
127-
DATA_SEND => DIN_VLD,
127+
DIN => DIN,
128+
DIN_VLD => DIN_VLD,
128129
BUSY => BUSY
129130
);
130131

@@ -143,8 +144,8 @@ begin
143144
UART_CLK_EN => uart_clk_en,
144145
UART_RXD => uart_rxd_debounced,
145146
-- USER DATA OUTPUT INTERFACE
146-
DATA_OUT => DOUT,
147-
DATA_VLD => DOUT_VLD,
147+
DOUT => DOUT,
148+
DOUT_VLD => DOUT_VLD,
148149
FRAME_ERROR => FRAME_ERROR
149150
);
150151

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